! ! © Copyright 1976, 2010 Hewlett-Packard Development Company, L.P. ! ! Confidential computer software. Valid license from HP and/or ! its subsidiaries required for possession, use, or copying. ! ! Consistent with FAR 12.211 and 12.212, Commercial Computer Software, ! Computer Software Documentation, and Technical Data for Commercial ! Items are licensed to the U.S. Government under vendor's standard ! commercial license. ! ! Neither HP nor any of its subsidiaries shall be liable for technical ! or editorial errors or omissions contained herein. The information ! in this document is provided "as is" without warranty of any kind and ! is subject to change without notice. The warranties for HP products ! are set forth in the express limited warranty statements accompanying ! such products. Nothing herein should be construed as constituting an ! additional warranty. ! ! ! ---- < End of module COPYRIGHT.R32 - 30-MAR-2010 16:38:38.32 > - ! ! ! ************************************************************************* ! * * ! * © Copyright 2010, Hewlett-Packard Development Company, L.P. * ! * * ! * Confidential computer software. Valid license from HP and/or * ! * its subsidiaries required for possession, use, or copying. * ! * * ! * Consistent with FAR 12.211 and 12.212, Commercial Computer Software, * ! * Computer Software Documentation, and Technical Data for Commercial * ! * Items are licensed to the U.S. Government under vendor's standard * ! * commercial license. * ! * * ! * Neither HP nor any of its subsidiaries shall be liable for technical * ! * or editorial errors or omissions contained herein. The information * ! * in this document is provided "as is" without warranty of any kind and * ! * is subject to change without notice. The warranties for HP products * ! * are set forth in the express limited warranty statements accompanying * ! * such products. Nothing herein should be construed as constituting an * ! * additional warranty. * ! * * ! ************************************************************************* ! ******************************************************************************************************************************** ! Created: 30-Mar-2010 16:30:11 by OpenVMS SDL EV3-3 ! Source: 30-MAR-2010 16:29:57 $1$DGA7374:[LIB.SRC]SYSDEF.SDL;1 ! ******************************************************************************************************************************** !*** MODULE NPOOL_DATA *** ! + ! DEFINITION OF SYSTEM PRIMITIVES LOCAL NON-PAGED POOL DATA ! - literal IOC_C_INVALID_ADDRESS = -8388608; ! 4G - 8M literal IOC_C_NUMLISTS = 160; ! No. of lookaside lists for all system pools ! *** See warning above *** literal IOC_C_NPAGGRNMSK = 63; ! Mask for rounding literal IOC_C_NPAGGRNBITS = 6; ! Granularity = 2^6 literal IOC_C_MAXLISTPKT = 10240; ! Max. lookaside list size literal IOC_C_PAGGRNMSK = 15; ! Mask for rounding literal IOC_C_PAGGRNBITS = 4; ! Granularity = 2^4 literal IOC_C_PAGMAXLISIZ = 2560; ! Max. lookaside list size literal LSTHDS$S_LSTHDS = 2648; macro LSTHDS$L_FILLER0 = 0,0,32,0 %; ! Formerly IRPLIST macro LSTHDS$L_VARALLOCBYTES = 4,0,32,0 %; ! How many bytes allocated from variable list macro LSTHDS$L_VARIABLELIST_UNUSED = 8,0,32,0 %; ! Historically important: What EXE$GL_NONPAGED points to macro LSTHDS$PS_VARIABLELIST = 12,0,32,1 %; ! Pointer to next packet on variable list macro LSTHDS$L_VARIABLELIST_HIGH = 16,0,32,0 %; ! For future use if we have 64-bit lists macro LSTHDS$L_EXPANSIONS = 20,0,32,0 %; ! How many times this pool has been expanded macro LSTHDS$L_FILLER2 = 24,0,32,0 %; ! Formerly SRPLIST macro LSTHDS$AR_LISTATTEMPTS = 28,0,32,1 %; ! Ptr to array of lookaside list tries macro LSTHDS$AR_LISTFAILS = 32,0,32,1 %; ! Ptr to array of lookaside list failures macro LSTHDS$AR_LISTDEALLOCS = 36,0,32,1 %; ! Ptr to array of lookaside list deallocations macro LSTHDS$L_RAD = 40,0,32,0 %; macro LSTHDS$L_POOLTYPE = 44,0,32,0 %; macro LSTHDS$PS_NPOOL_DATA = 48,0,32,1 %; ! Pointer to the NPOOL data structure for this pool macro LSTHDS$L_DISABLE_POOL_EXP_MSG = 52,0,32,0 %; macro LSTHDS$Q_LISTHEADS = 56,0,0,1 %; literal LSTHDS$S_LISTHEADS = 1288; ! The actual lookaside lists. Must be 56 bytes from beginning. macro LSTHDS$Q_LISTCOUNTERS = 1360,0,0,0 %; literal LSTHDS$S_LISTCOUNTERS = 1288; literal LSTHDS$K_LENGTH = 2648; literal LSTHDS$C_LENGTH = 2648; literal POOL_MAP$S_POOL_MAP = 32; macro POOL_MAP$pq_segment_address = 0,0,0,1 %; literal POOL_MAP$s_segment_address = 8; macro POOL_MAP$q_segment_length = 8,0,0,0 %; literal POOL_MAP$s_segment_length = 8; macro POOL_MAP$pq_segment_end_address = 16,0,0,1 %; literal POOL_MAP$s_segment_end_address = 8; macro POOL_MAP$l_rad = 24,0,32,0 %; macro POOL_MAP$l_filler1 = 28,0,32,1 %; literal POOL_MAP$K_LENGTH = 32; literal NPOOL$M_NOT_NPP = %X'1'; literal NPOOL$M_POOL_SEPARATE = %X'2'; literal NPOOL$M_POOL_WITHIN_NPP = %X'4'; literal NPOOL$M_MINIMUM_MODE = %X'8'; literal S_NPOOL_DATA = 184; macro NPOOL$L_ON_RAD_DEALLOC = 0,0,32,0 %; ! Count deallocs from same RAD as alloc macro NPOOL$L_TOTAL_DEALLOC = 4,0,32,0 %; ! Count total deallocs to get % macro NPOOL$Q_PER_POOL_DIAG = 8,0,0,0 %; literal NPOOL$S_PER_POOL_DIAG = 8; ! Use for diagnostic info ! The following are only used in the NPP NPOOL structure for now. ! Some other time, we could have one for each pool and sequence tag each entry. macro NPOOL$PS_RINGBUF = 16,0,32,1 %; ! Pointer to the ring buffer macro NPOOL$PS_NEXTNPH = 20,0,32,1 %; ! Pointer to next element to write to in ring buffer macro NPOOL$L_RINGBUFCNT = 24,0,32,0 %; ! How many entries in ring buffer? macro NPOOL$Q_RINGBUFLOCK = 32,0,0,0 %; literal NPOOL$S_RINGBUFLOCK = 8; ! Lock access to the ringbuffer ! The filler forces mostly-read stuff beyond a 128-byte ! boundary and hopefully into a different cache block from the frequently-written list heads macro FILLER6 = 40,0,0,1 %; literal S_FILLER6 = 88; ! After this point, we have read-mostly information. macro NPOOL$AR_LSTHDS = 128,0,0,1 %; literal NPOOL$S_LSTHDS = 8; ! Pointer to the array of pool list heads macro NPOOL$L_MAX_LSTHDS = 136,0,32,0 %; ! Biggest entry in list heads array? macro NPOOL$L_GRAN_MASK = 140,0,32,0 %; ! Granularity of the pool in bytes macro NPOOL$L_NUM_LOOKASIDE = 144,0,32,0 %; ! How many lookaside lists in LSTHDS? macro NPOOL$PS_VARIABLE_LIST = 148,0,32,1 %; ! Pointer to the pool's variable list (compatibility) macro NPOOL$PS_POOL_MAP = 152,0,32,1 %; macro NPOOL$L_POOL_MAP_SIZE = 156,0,32,0 %; ! Number of bytes allcoated for POOL_MAP macro NPOOL$L_POOL_MAP_SEGMENTS = 160,0,32,0 %; ! Number of segments in POOL_MAP actually used macro NPOOL$AR_POOL_DATA = 164,0,0,1 %; literal NPOOL$S_POOL_DATA = 16; ! Dimension should be MMG$K_POOLTYPE_MAXIMUM; ! This are mainly for SDA format. Most uses should index using POOL_TYPE. macro NPOOL$AR_NPP_POOL_DATA = 164,0,0,1 %; literal NPOOL$S_NPP_POOL_DATA = 8; macro NPOOL$AR_BAP_POOL_DATA = 172,0,0,1 %; literal NPOOL$S_BAP_POOL_DATA = 8; macro NPOOL$L_POOL_FLAGS = 164,0,32,0 %; macro NPOOL$V_NOT_NPP = 164,0,1,0 %; ! Note: If this NPOOL *does* represent non-paged pool, there is an ! address here, which will not have bit 0 set. Thus, this flag is ! valid in all cases macro NPOOL$V_POOL_SEPARATE = 164,1,1,0 %; macro NPOOL$V_POOL_WITHIN_NPP = 164,2,1,0 %; macro NPOOL$V_MINIMUM_MODE = 164,3,1,0 %; literal NPOOL$K_LENGTH = 184; literal NPOOL$C_LENGTH = 184; !*** MODULE $NPHDEF *** ! + ! DEFINITION OF NON-PAGED POOL HISTORY RECORD IN RING BUFFER ! - literal NPH$C_ALONONPAGED = 0; ! Caller was EXE$ALONONPAGED literal NPH$C_ALONPAGVAR = 1; ! Caller was EXE$ALONPAGVAR literal NPH$C_DEANONPAGED = 2; ! Caller was EXE$DEANONPAGED literal NPH$C_DEANONPGDSIZ = 3; ! Caller was EXE$DEANONPGDSIZ literal NPH$C_ALLOCATE_POOL_NPP = 4; ! Caller was EXE$ALLOCATE_POOL with NPP pooltype literal NPH$C_ALLOCATE_POOL_NPP_ALIGNED = 5; ! Caller was EXE$ALLOCATE_POOL with NPP pooltype and non-0 alignment literal NPH$C_DEALLOCATE_POOL_NPP = 6; ! Caller was EXE$DEALLOCATE_POOL with NPP pooltype and size in memory literal NPH$C_DEALLOCATE_POOL_NPP_SIZED = 7; ! Caller was EXE$DEALLOCATE_POOL with NPP pooltype and size specified literal NPH$C_ALLOCATE_POOL_BAP = 8; ! Caller was EXE$ALLOCATE_POOL with BAP pooltype literal NPH$C_ALLOCATE_POOL_BAP_ALIGNED = 9; ! Caller was EXE$ALLOCATE_POOL with BAP pooltype and non-0 alignment literal NPH$C_DEALLOCATE_POOL_BAP = 10; ! Caller was EXE$DEALLOCATE_POOL with BAP pooltype and size in memory literal NPH$C_DEALLOCATE_POOL_BAP_SIZED = 11; ! Caller was EXE$DEALLOCATE_POOL with BAP pooltype and size specified literal NPH$C_POOLZONE_ALLOCATE = 12; ! Caller was EXE$POOL_ALLOCATE literal NPH$C_POOLZONE_DEALLOCATE = 13; ! Caller was EXE$POOL_DEALLOCATE literal NPH$C_BAP_NOT_CONTIGUOUS = 14; ! Failure of BAP due to non-contiguous physical memory literal NPH$C_ALLOCATE_POOL_NPP_VAR = 15; ! Allocating NPP from the variable pool literal NPH$C_ALLOCATE_POOL_BAP_VAR = 16; ! Allocating BAP from the variable pool literal NPH$C_ALONONPAGED_ALN = 17; ! Allocating with EXE$ALONONPAGED_ALN literal NPH$C_EXPAND_NPP = 18; ! Pool expansion literal NPH$C_EXPAND_BAP = 19; ! Pool expansion literal NPH$C_MAX_FUNC_TYPE = 20; ! Maximum expected function type for SDA literal NPH$S_NPHDEF = 32; ! Old size name - synonym literal NPH$S_NPH = 32; macro NPH$Q_ADDR = 0,0,0,0 %; literal NPH$S_ADDR = 8; ! Address of packet macro NPH$L_ADDR_LOW = 0,0,32,0 %; ! low longword of pkt addr macro NPH$L_ADDR_HIGH = 4,0,32,0 %; ! high longword of pkt addr macro NPH$L_PC = 8,0,32,1 %; ! PC of caller's caller macro NPH$W_FUNCTION = 12,0,16,0 %; ! Function of caller macro NPH$B_TYPE = 14,0,8,0 %; ! Pkt. type macro NPH$B_RMOD = 15,0,8,0 %; ! Pkt. RMOD or subtype macro NPH$L_SIZE = 16,0,32,0 %; ! Size of pkt. being manip. macro NPH$B_IPL = 20,0,8,0 %; ! IPL of caller macro NPH$B_CPU = 21,0,8,0 %; ! CPU number function was called on macro NPH$w_unused = 22,0,16,0 %; ! Round up to quadword macro NPH$Q_TIME = 24,0,0,0 %; literal NPH$S_TIME = 8; ! System time of operation macro NPH$L_TIME_LOW = 24,0,32,0 %; ! low longword of time macro NPH$L_TIME_HIGH = 28,0,32,0 %; ! high longword of time !*** MODULE $PTEDEF *** ! + ! Define page table entry vields and values ! - literal PTE$C_BYTES_PER_PTE = 8; ! Byte length of Page Table Entry literal PTE$C_SHIFT_SIZE = 3; ! PTE size as a power of 2 ! ! Vield definition for "valid" PTEs ! literal PTE$M_VALID = %X'1'; literal PTE$M_FOR = %X'2'; literal PTE$M_FOW = %X'4'; literal PTE$M_FOE = %X'8'; literal PTE$M_MA = %X'70'; literal PTE$M_PROT = %X'F80'; literal PTE$M_GH = %X'F000'; literal PTE$C_GROUP_OF_1 = 0; ! Page in group of 1 literal PTE$C_GROUP_OF_8 = 1; ! Page in group of 8 literal PTE$C_GROUP_OF_64 = 2; ! Page in group of 64 literal PTE$C_GROUP_OF_512 = 3; ! Page in group of 512 literal PTE$M_SOFTWARE = %X'FF0000'; literal PTE$M_PFN = %X'FFFFFFFFFF000000'; literal PTE$M_PL = %X'180'; literal PTE$M_AR = %X'E00'; literal PTE$M_DUMPKEY = %X'80'; literal PTE$M_DUMPOTHER = %X'100'; literal PTE$M_ASM = %X'1'; literal PTE$M_RESERVED = %X'30'; literal PTE$M_UNCACHED = %X'40'; literal PTE$M_WINDOW = %X'10000'; literal PTE$M_OWN = %X'60000'; literal PTE$M_MODIFY = %X'100000'; literal PTE$M_CPY = %X'600000'; literal PTE$M_S0_MBZ = %X'800000'; literal PTE$M_TYP0 = %X'10000'; literal PTE$M_PARTIAL_SECTION = %X'80000'; literal PTE$M_TYP1 = %X'100000'; literal PTE$M_STX = %X'FFFF00000000'; literal PTE$M_CRF = %X'1000000000000'; literal PTE$M_DZRO = %X'2000000000000'; literal PTE$M_WRT = %X'4000000000000'; literal PTE$M_PGFLPAG = %X'FFFFFF00000000'; literal PTE$M_PGFLX = %X'FF00000000000000'; literal PTE$M_PGFLMAP = %X'FFFFFFFF00000000'; literal PTE$M_GPTX = %X'FFFFFFFF00000000'; literal PTE$M_BAKX = %X'FFFFFFFFFF000000'; literal PTE$C_NOPGFLPAG = 255; ! + literal PTE$C_NA = 0; ! No Access literal PTE$C_KR = 512; ! Kernel Read only AR=1 PL=0 (execute) literal PTE$C_KW = 1024; ! Kernel Write AR=2 PL=0 (no execute) literal PTE$C_ER = 640; ! Exec Read only AR=1 PL=1 (execute) literal PTE$C_EW = 1152; ! Exec Write AR=2 PL=1 (no execute) literal PTE$C_SR = 768; ! Super Read only AR=1 PL=2 (execute) literal PTE$C_SW = 1280; ! Super Write AR=2 PL=2 (no execute) literal PTE$C_UR = 896; ! User Read only AR=1 PL=3 (execute) literal PTE$C_UW = 1408; ! User Write AR=2 PL=3 (no execute) literal PTE$C_ERKW = 2176; ! Exec Read Kernel Write AR=4 PL=1 (no execute) literal PTE$C_SRKW = 2816; ! Super Read Kernel Write AR=5 PL=2 (execute) literal PTE$C_SREW = 2304; ! Super Read Exec Write AR=4 PL=2 (no execute) literal PTE$C_URKW = 2944; ! User Read Kernel Write AR=5 PL=3 (execute) ! UREW cannot be expressed in IA64 AR/PL form. We use URSW which allows SW access. literal PTE$C_UREW = 2432; ! User Read Exec Write AR=4 PL=3 (no execute) literal PTE$C_URSW = 2432; ! User Read Super Write AR=4 PL=3 (no execute) ! + literal PTE$C_KOWN = 0; ! Kernel Owner Mode literal PTE$C_EOWN = 131072; ! Executive Owner Mode literal PTE$C_SOWN = 262144; ! Supervisor Owner Mode literal PTE$C_UOWN = 393216; ! User Owner Mode ! + literal PTE$C_COPY = 0; ! Copy literal PTE$C_NOCOPY = 2097152; ! No copy literal PTE$C_DZRO = 4194304; ! Copy as DZRO ! + literal PTE$C_DZRO_L1PTE = 1024; ! Kernel Write, no execute AR=2 PL=0 literal PTE$C_DZRO_L2PTE = 2176; ! Exec read, kernel write, no execute AR=4 PL=1 literal PTE$S_PTE = 8; macro PTE$R_PTE_UNION = 0,0,0,0 %; literal PTE$S_PTE_UNION = 8; macro PTE$V_VALID = 0,0,1,0 %; ! VALID bit macro PTE$V_FOR = 0,1,1,0 %; ! Fault On Read macro PTE$V_FOW = 0,2,1,0 %; ! Fault On Write macro PTE$V_FOE = 0,3,1,0 %; ! Fault On Execute macro PTE$V_MA = 0,4,3,0 %; literal PTE$S_MA = 3; ! Memory attributes macro PTE$V_PROT = 0,7,5,0 %; literal PTE$S_PROT = 5; ! Page Protection macro PTE$V_GH = 0,12,4,0 %; literal PTE$S_GH = 4; ! Granularity Hint macro PTE$V_SOFTWARE = 0,16,8,0 %; literal PTE$S_SOFTWARE = 8; ! Bits Reserved to Software macro PTE$V_PFN = 0,24,40,0 %; literal PTE$S_PFN = 40; ! Page Frame Number macro PTE$V_PL = 0,7,2,0 %; literal PTE$S_PL = 2; ! Privilege level macro PTE$V_AR = 0,9,3,0 %; literal PTE$S_AR = 3; ! Access rights macro PTE$V_DUMPKEY = 0,7,1,0 %; ! Global page must be dumped on key pass macro PTE$V_DUMPOTHER = 0,8,1,0 %; ! Global page must be dumped on other pass macro PTE$V_ASM = 0,0,1,0 %; ! Obsolete on IA64 ! (ASM can only be set if valid is set ! so, we use this trick for porting) macro PTE$V_FAULT_BITS = 0,1,3,0 %; ! For SDA macro PTE$V_UNCACHED = 0,6,1,0 %; ! Mapping is uncached (UC or WC) macro PTE$V_WINDOW = 0,16,1,0 %; ! Windowed Page Bit macro PTE$V_OWN = 0,17,2,0 %; literal PTE$S_OWN = 2; ! Page Owner Mode macro PTE$V_MODIFY = 0,20,1,0 %; ! Page Modified Bit macro PTE$V_CPY = 0,21,2,0 %; literal PTE$S_CPY = 2; ! Copy characteristic macro PTE$V_S0_MBZ = 0,23,1,0 %; ! S0 space bit: MBZ in PTE ! ! Vield definitions for various invalid forms of PTE ! macro PTE$V_TYP0 = 0,16,1,0 %; ! TYP0 Bit macro PTE$V_PARTIAL_SECTION = 0,19,1,0 %; ! Only part of page maps to section macro PTE$V_TYP1 = 0,20,1,0 %; ! TYP1 Bit macro PTE$V_STX = 4,0,16,0 %; literal PTE$S_STX = 16; ! Section Table Index macro PTE$V_CRF = 4,16,1,0 %; ! Copy on Reference macro PTE$V_DZRO = 4,17,1,0 %; ! Demand Zero macro PTE$V_WRT = 4,18,1,0 %; ! Section file accessed for write macro PTE$v_filler_17 = 4,19,13,0 %; literal PTE$s_filler_17 = 13; ! Not marked 'fill' for SDA macro PTE$V_PGFLPAG = 4,0,24,0 %; literal PTE$S_PGFLPAG = 24; ! Page File Page Number (not a VBN) macro PTE$V_PGFLX = 4,24,8,0 %; literal PTE$S_PGFLX = 8; ! System page file index macro PTE$V_PGFLMAP = 4,0,32,0 %; literal PTE$S_PGFLMAP = 32; ! Page file page number and index macro PTE$V_GPTX = 4,0,32,0 %; literal PTE$S_GPTX = 32; ! Global Page Table Index macro PTE$V_BAKX = 0,24,40,0 %; literal PTE$S_BAKX = 40; ! Backup Address (uninterpreted) macro PTE$Q_ENTRY = 0,0,0,0 %; literal PTE$S_ENTRY = 8; ! The entire page table entry macro PTE$L_ENTRY_L = 0,0,32,0 %; ! The low longword of the PTE macro PTE$L_ENTRY_H = 4,0,32,0 %; ! The high longword of the PTE macro PTE$V_PFN40 = 0,24,40,0 %; literal PTE$S_PFN40 = 40; ! For use with 50-bit I/O space on IPF ! + ! Define a constant indicating "no pagefile page assigned": all bits set in PGFLX ! - ! Protection field definitions. These protection encodings provide ! a way to express page protection using VAX-like protection symbols. ! - ! + ! These constants are not meant to be shifted into the PROT position. ! They incorporate protection information as bitmasks relative to the ! start of a PTE already. ! - ! OWNer mode field definitions ! ! These constants are not meant to be shifted into the owner field. They ! incorporate ownership information as a bitmask relative to the start of ! a PTE already. ! _ ! CoPY field definitions ! ! These constants are not meant to be shifted into the copy characteristic ! field. They incorporate copy characteristic information relative to the ! start of a PTE already. ! _ ! Demand zero PTE defintions for L1 and L2 PTEs ! - literal PTE$M_FREE_PTE_MBZ1 = %X'FFFF'; literal PTE$M_SINGLE_PTE = %X'10000'; literal PTE$M_FREE_PTE_MBZ2 = %X'60000'; literal PTE$S_VA_PTE_FREE = 16; macro PTE$Q_INDEX = 0,0,0,0 %; literal PTE$S_INDEX = 8; ! PTE index field. For historic reasons, index field is defined macro PTE$V_FREE_PTE_MBZ1 = 0,0,16,0 %; literal PTE$S_FREE_PTE_MBZ1 = 16; ! Bits <15:0> are MBZ. macro PTE$V_SINGLE_PTE = 0,16,1,0 %; ! Bit <16> denotes that the element contains a sigle PTE. macro PTE$V_FREE_PTE_MBZ2 = 0,17,2,0 %; literal PTE$S_FREE_PTE_MBZ2 = 2; ! Bits <18:17> are MBZ in order for code to distinguish between a ! free PTE and a GPTE. macro PTE$L_FREE_COUNT = 12,0,32,0 %; ! Count of free PTEs in this block. literal PTE$S_PTEDEF = 16; ! Old PTE size constant for compatibility ! ! ! Define a constant that's used to shift the index value into the ! appropriate bits of the index quadword of the VA_PTE_FREE structure. ! literal PTE$C_INDEX_SHIFT_VALUE = 19; literal PTE$C_FREE_BLOCK = 16; ! Byte length of VA_PTE free block. ! Head of a private list of free PTEs literal PTELIST$S_PTELIST = 24; macro PTELIST$Q_HEAD = 0,0,0,0 %; literal PTELIST$S_HEAD = 8; ! PTE index of head and tail element macro PTELIST$Q_TAIL = 8,0,0,0 %; literal PTELIST$S_TAIL = 8; ! in free list; same format as in VA_PTE_FREE macro PTELIST$Q_COUNT = 16,0,0,1 %; literal PTELIST$S_COUNT = 8; ! count of free PTEs in this list literal PTELIST$K_LENGTH = 24; ! length of block; literal PTELIST$C_LENGTH = 24; ! length of block; !*** MODULE $DIOBMDEF *** ! + ! DIOBM - Direct I/O Buffer Map ! ! The DIOBM structure is used to solve the "cross-process PTE problem" for ! buffers that have been locked into memory for direct I/O. The ! cross-process PTE access problem results from memory management ! infrastructure changes made to support 64-bit virtual addressing. ! Because the process page tables are in process-private page table space ! and no longer in the balance set slots in S0/S1 space, only the PTEs for ! the current process can be accessed directly. Moreover, the virtual ! address for these PTEs in page table space requires a full 64-bits. ! ! There are two variants of the DIOBM structure. The first is the primary ! DIOBM structure. The primary DIOBM structure can be used in the ! following mutually exclusive ways: ! ! 1. To contain copies of the actual PTEs that map the buffer. ! ! 2. To point to a larger secondary DIOBM structure if the primary DIOBM ! structure has insufficient room for all the PTEs that map the user ! buffer. ! ! 3. To manage a PTE window in S0/S1 space onto the actual PTEs that map ! the buffer if the required PTE count exceeds the capacity of the ! largest allowable DIOBM structure. ! ! Each of the above methods yield a 32-bit system virtual address for the ! PTEs that map the buffer. This address is valid regardless of process ! or system context. ! ! The fixed-size DIOBM structure contains room for exactly ! DIOBM$K_PTECNT_FIX (9) PTEs which are enough to map a 64 Kb buffer with ! an 8 Kb page size. The IRP, IRPE, VCRP, and DCBE structures all contain ! an embedded fixed-sized primary DIOBM structure. A secondary DIOBM ! structure is used only for PTE copies and can have room for up to the ! number of PTEs specified in the IOC$GL_DIOBM_PTECNT_MAX data cell. ! The value of the IOC$GL_DIOBM_PTECNT_MAX data cell is set to ! DIOBM$K_PTECNT_MAX_UNI (94) on a uniprocessor system and ! DIOBM$K_PTECNT_MAX_SMP (430) on an SMP system. ! ! For additional details about the usage of the DIOBM, see "Chapter 20: ! QIO and Device Drivers" in DOCD$:[EVMS.CMS_64B]DS-64BITS.PS. ! - literal DIOBM$M_REL_DEALLOC = %X'1'; literal DIOBM$M_PTE_WINDOW = %X'2'; literal DIOBM$M_AUX_INUSE = %X'4'; literal DIOBM$M_INUSE = %X'8'; literal DIOBM$M_S0PTE_WINDOW = %X'10'; literal DIOBM$K_HDRLEN = 16; ! Size of minimal DIOBM packet header excluding PTE vector literal DIOBM$K_PTECNT_FIX = 9; ! Number of PTE entries in fixed size DIOBM ! Max PTE entries in variably sized DIOBM before using PTE window literal DIOBM$K_PTECNT_MAX_UNI = 94; ! Max PTE entries on uniprocessor system (experimentally derived) literal DIOBM$K_PTECNT_MAX_SMP = 430; ! Higher value for max PTE entries on SMP system (experimentally derived) literal DIOBM$S_DIOBM = 88; macro DIOBM$PS_AUX_DIOBM = 0,0,32,1 %; ! Pointer to a secondary DIOBM structure ! Valid if and only if DIOBM$V_AUX_INUSE set macro DIOBM$L_PTE_COUNT = 4,0,32,0 %; ! If DIOBM$V_PTE_WINDOW is clear, count of ! PTEs copied to the PTE vector ! If DIOBM$V_PTE_WINDOW is set, count of ! SPTEs allocated for a PTE window macro DIOBM$W_SIZE = 8,0,16,0 %; ! Structure size macro DIOBM$B_TYPE = 10,0,8,0 %; ! Structure type, DYN$C_MISC macro DIOBM$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype, DYN$C_DIOBM macro DIOBM$L_FLAGS = 12,0,32,0 %; ! Flag bits: macro DIOBM$V_REL_DEALLOC = 12,0,1,0 %; ! Deallocate this DIOBM on release macro DIOBM$V_PTE_WINDOW = 12,1,1,0 %; ! This DIOBM manages a PTE window macro DIOBM$V_AUX_INUSE = 12,2,1,0 %; ! DIOBM$PS_AUX_DIOBM points to secondary DIOBM macro DIOBM$V_INUSE = 12,3,1,0 %; ! This DIOBM is in use (if "full checking" enabled) macro DIOBM$V_S0PTE_WINDOW = 12,4,1,0 %; ! S0/S1 PTE window was used to derive 32-bit SVAPTE ! The PTE window is more expensive on an SMP system macro DIOBM$Q_PTE_VECTOR = 16,0,0,0 %; literal DIOBM$S_PTE_VECTOR = 72; ! Vector of PTEs ! that are copies of the PTEs that map the buffer ! Valid only if both DIOBM$V_PTE_WINDOW and DIOBM$V_AUX_INUSE clear macro DIOBM$PQ_PTEW_VA_SPTE = 16,0,0,1 %; literal DIOBM$S_PTEW_VA_SPTE = 8; ! 64-bit VA for first SPTE allocated for window ! Valid if and only if DIOBM$V_PTE_WINDOW set macro DIOBM$PS_PTEW_S0VA = 24,0,32,1 %; ! Lowest S0/S1 va mapped by SPTEs for PTE window ! Valid if and only if DIOBM$V_PTE_WINDOW set literal DIOBM$K_LENGTH = 88; ! Size of fixed size DIOBM ! Flag bit mask definitions for use on the flags parameter to routines ! IOC_STD$CREATE_DIOBM and IOC_STD$FILL_DIOBM ! literal DIOBM$M_NORESWAIT = 1; ! No resource wait; return error !*** MODULE $CDRPDEF *** ! + ! CDRP - CLASS DRIVER I/O REQUEST PACKET ! ! This structure contains within it, at negative offsets, a full IRP. ! For this reason all IRP fields must be at the same relative offsets ! as the corresponding fields in the IRP. ! ! NOTE: The equivalency of these IRP and CDRP offsets is verified by ASSUME ! statements in the [LIB]VFY_IRP_A_LIKES.MAR module. These ASSUMEs may need ! to be altered as well whenever an CDRP or IRP field is removed or altered. ! - ! Define DIOBM type; IRP in CDRP contains an embedded DIOBM type literal CDRP$M_WLE_REUSE = %X'1'; literal CDRP$M_WLE_SUPWL = %X'2'; literal CDRP$K_CDRPBASE = 0; literal CDRP$C_CDRPBASE = 0; literal CDRP$C_RSPID_WAIT = 1; ! Waiting for Rspid Resource literal CDRP$C_POOL_WAIT = 2; ! Waiting for Pool Resource literal CDRP$C_CREDIT_WAIT = 3; ! Waiting for Credit Resource literal CDRP$C_BD_WAIT = 4; ! Waiting for Buffer Descriptor Resource literal CDRP$M_SYSAP_STALLED = %X'1'; literal CDRP$M_RBUN_WANTED = %X'2'; literal CDRP$K_LENGTH = 80; literal CDRP$C_LENGTH = 80; ! CDRP extensions literal CDRP$K_BT_LEN = 96; literal CDRP$C_BT_LEN = 96; literal CDRP$M_CAND = %X'1'; literal CDRP$M_CANIO = %X'2'; literal CDRP$M_ERLIP = %X'4'; literal CDRP$M_PERM = %X'8'; literal CDRP$M_HIRT = %X'10'; literal CDRP$M_DENSCK = %X'20'; literal CDRP$M_CONNWALK = %X'40'; literal CDRP$M_COPYSHAD = %X'80'; literal CDRP$M_IVCMD = %X'100'; literal CDRP$M_WALK_2P = %X'200'; literal CDRP$M_LOC_ONLY = %X'400'; literal CDRP$M_LOADBAL = %X'800'; literal CDRP$M_NORETRY = %X'1000'; literal CDRP$M_INTERNAL = %X'2000'; literal CDRP$K_CD_LEN = 144; literal CDRP$C_CD_LEN = 144; literal CDRP$K_NORMAL = 0; ! The standard case (particulary no block xfer) literal CDRP$K_REQUESTOR = 1; ! Block transfer requestor literal CDRP$K_PARTNER = 2; ! Block transfer partner, active literal CDRP$K_PART_IDLE = 3; ! Block transfer partner, idle literal CDRP$K_REQ_MAP = 4; ! Block transfer requestor, waiting for buffer handle literal CDRP$K_PART_MAP = 5; ! Block transfer partner, waiting for buffer handle literal CDRP$K_PART_FORK_WAIT = 6; ! Block transfer partner, on fork_wait queue literal CDRP$K_CNX_MSG = 0; ! Send message literal CDRP$K_CNX_BLKRD = 1; ! Block read literal CDRP$K_CNX_BLKWRT = 2; ! Block write literal CDRP$K_CNX_REQ = 3; ! Request block xfer literal CDRP$M_HAVE_SYNCH = %X'1'; literal CDRP$M_MSGBLD_SYNCH = %X'2'; literal CDRP$M_CPL_SYNCH = %X'4'; literal CDRP$M_STALL_SYNCH = %X'8'; literal CDRP$M_RM_BLKRD_DONE = %X'10'; literal CDRP$M_RM_XFRPROC_DONE = %X'20'; literal CDRP$K_CM_LENGTH = 224; literal CDRP$K_VCNX_NORMAL = 0; ! The standard case (particulary no block xfer) literal CDRP$K_VCNX_REQUESTOR = 1; ! Block transfer requestor literal CDRP$K_VCNX_PARTNER = 2; ! Block transfer partner, active literal CDRP$K_VCNX_PART_IDLE = 3; ! Block transfer partner, idle literal CDRP$K_VCNX_REQ_MAP = 4; ! Block transfer requestor, waiting for buffer handle literal CDRP$K_VCNX_PART_MAP = 5; ! Block transfer partner, waiting for buffer handle literal CDRP$M_CDRP_PARTNER_VALID = %X'1'; literal CDRP$M_XMT_CDRP_BLKXFR = %X'2'; literal CDRP$M_XMT_REQ_SUCCESS = %X'4'; literal CDRP$M_XMT_XFER_DONE = %X'8'; literal CDRP$M_PARTNER_ABORT = %X'10'; literal CDRP$M_XMT_NOTIFIED = %X'20'; literal CDRP$M_XMT_SEGMENT = %X'40'; literal CDRP$M_XMT_MUX_MSG = %X'80'; literal CDRP$K_VCNX_MSG = 0; ! Normal messages literal CDRP$K_VCNX_BLKRD = 1; ! Block transfer read literal CDRP$K_VCNX_BLKWRT = 2; ! Block transfer write literal CDRP$K_VCNX_REQ = 3; ! Requestor literal CDRP$K_SCATP_LENGTH = 168; literal CDRP$K_IDLE = 0; ! CDRP is idle literal CDRP$K_ALLOC_MSG_BUF = 1; ! Allocate message in progress literal CDRP$K_RECYCLE_MSG_BUF = 2; ! Message is being recycled literal CDRP$K_MAP = 3; ! Map wait is in progress literal CDRP$K_SEND_DATA = 4; ! Block transfer is in progress literal CDRP$K_SEND_MSG = 5; ! Message sending in progress literal CDRP$K_ALLOC_RSPID = 6; ! Allocate rspid in progress literal CDRP$K_SDA_LEN = 160; literal CDRP$C_SDA_LEN = 160; literal CDRP$S_CDRP = 544; macro CDRP$L_IOQFL = -320,0,32,1 %; ! I/O QUEUE FORWARD LINK macro CDRP$L_IOQBL = -316,0,32,1 %; ! I/O QUEUE BACKWARD LINK macro CDRP$W_IRP_SIZE = -312,0,16,0 %; ! SIZE OF IRP IN BYTES macro CDRP$B_IRP_TYPE = -310,0,8,0 %; ! STRUCTURE TYPE FOR IRP macro CDRP$B_RMOD = -309,0,8,0 %; ! ACCESS MODE OF REQUEST macro CDRP$L_PID = -308,0,32,0 %; ! PROCESS ID OF REQUESTING PROCESS macro CDRP$L_ACB64X_OFFSET = -304,0,32,1 %; ! Offset to ACB64X structure embedded in this IRP macro CDRP$L_ACB_FLAGS = -296,0,32,0 %; ! ACB flags; valid only if ACB$M_FLAGS_VALID in RMOD set macro CDRP$L_THREAD_PID = -292,0,32,0 %; ! (Reserved for Kernel Threads) macro CDRP$L_WIND = -288,0,32,1 %; ! ADDRESS OF WINDOW BLOCK macro CDRP$L_MIRP = -288,0,32,1 %; ! LINK TO MASTER IRP macro CDRP$L_KAST = -288,0,32,1 %; ! PIGGY BACK KERNEL AST ADDRESS macro CDRP$L_UCB = -284,0,32,1 %; ! ADDRESS OF DEVICE UCB macro CDRP$PQ_ACB64_AST = -280,0,0,1 %; literal CDRP$S_ACB64_AST = 8; ! 64-bit user AST routine address macro CDRP$L_SHD_IOFL = -280,0,32,1 %; ! Link to clone IRPs macro CDRP$L_IIRP_P0 = -280,0,32,1 %; ! Generic parameter cell in internal IRPs macro CDRP$Q_ACB64_ASTPRM = -272,0,0,0 %; literal CDRP$S_ACB64_ASTPRM = 8; ! 64-bit user AST parameter value macro CDRP$L_SHAD = -272,0,32,1 %; ! SHAD address macro CDRP$L_HRB = -272,0,32,1 %; ! HRB address macro CDRP$L_MV_TMO = -272,0,32,1 %; ! Timeout value in internal mount verification IRPs macro CDRP$L_IIRP_P1 = -272,0,32,1 %; ! Generic parameter cell in internal IRPs macro CDRP$Q_USER_THREAD_ID = -264,0,0,0 %; literal CDRP$S_USER_THREAD_ID = 8; ! Unique user thread identifier macro CDRP$B_EFN = -256,0,8,0 %; ! EVENT FLAG NUMBER AND EVENT GROUP macro CDRP$B_PRI = -255,0,8,0 %; ! BASE PRIORITY OF REQUESTING PROCESS macro CDRP$B_CLN_INDX = -254,0,8,0 %; ! Shadow Clone membership index macro CDRP$B_WLG_FLAGS = -253,0,8,0 %; ! These flags are shared by DUDRIVER and SHDRIVER and MSCP. macro CDRP$V_WLE_REUSE = -253,0,1,0 %; ! Reuse writelog entry macro CDRP$V_WLE_SUPWL = -253,1,1,0 %; ! Supplementary writelog ! ! macro CDRP$L_CHAN = -252,0,32,0 %; ! Process I/O channel macro CDRP$PQ_IOSB = -248,0,0,1 %; literal CDRP$S_IOSB = 8; ! 64-bit address of caller's IOSB macro CDRP$L_CLN_WLE = -248,0,32,0 %; ! write log entry macro CDRP$L_IIRP_P2 = -248,0,32,1 %; ! Generic parameter cell in internal IRPs macro CDRP$Q_STATUS = -240,0,0,0 %; literal CDRP$S_STATUS = 8; macro CDRP$L_STS = -240,0,32,0 %; ! Request status macro CDRP$L_STS2 = -236,0,32,0 %; ! Second status word macro CDRP$PQ_VA_PTE = -232,0,0,1 %; literal CDRP$S_VA_PTE = 8; ! 64-bit process virtual addr of PTE macro CDRP$L_SVAPTE = -224,0,32,1 %; ! 32-bit S0/S1 address of first PTE macro CDRP$PS_BUFIO_PKT = -224,0,32,1 %; ! Pointer to buffered I/O packet macro CDRP$L_BCNT = -220,0,32,0 %; ! BYTE COUNT OF TRANSFER macro CDRP$L_BOFF = -216,0,32,0 %; ! Byte offset macro CDRP$L_OBOFF = -212,0,32,0 %; ! Original BOFF, for segmented DIO macro CDRP$L_EXTEND = -208,0,32,1 %; ! ADDRESS OF IRPE macro CDRP$PS_FDT_CONTEXT = -204,0,32,1 %; ! Contains addr of the FDT Context structure macro CDRP$R_DIOBM = -200,0,0,0 %; literal CDRP$S_DIOBM = 88; ! Embedded DIOBM to handle cross-process 32-bit PTE access macro CDRP$L_IOST1 = -112,0,32,0 %; ! FIRST I/O STATUS LONGWORD (FOR I/O POST) macro CDRP$L_MEDIA = -112,0,32,1 %; ! MEDIA ADDRESS macro CDRP$L_IOST2 = -108,0,32,0 %; ! SECOND I/O STATUS LONGWORD macro CDRP$L_TT_TERM = -108,0,32,1 %; ! ADDRESS OF READ TERMINATORS MASK macro CDRP$B_CARCON = -108,0,8,0 %; ! CARRIAGE CONTROL macro CDRP$Q_NT_PRVMSK = -104,0,0,0 %; literal CDRP$S_NT_PRVMSK = 8; ! PRIVILEGE MASK FOR DECNET macro CDRP$Q_STATION = -104,0,0,0 %; literal CDRP$S_STATION = 8; ! STATION FIELD FOR DECNET DRIVERS macro CDRP$Q_TT_STATE = -104,0,0,0 %; literal CDRP$S_TT_STATE = 8; ! TERMINAL STATE DEFINITIONS macro CDRP$L_ABCNT = -104,0,32,0 %; ! ACCUMULATED BYTES TRANSFERED macro CDRP$L_OBCNT = -100,0,32,0 %; ! ORIGINAL TRANSFER BYTE COUNT macro CDRP$L_FUNC = -96,0,32,0 %; ! I/O function code macro CDRP$Q_SEGVBN = -88,0,0,0 %; literal CDRP$S_SEGVBN = 8; ! 64-bit VBN macro CDRP$L_SEGVBN = -88,0,32,0 %; ! VIRTUAL BLOCK NUMBER OF CURRENT SEGMENT macro CDRP$L_DIAGBUF = -80,0,32,1 %; ! DIAGNOSTIC BUFFER ADDRESS macro CDRP$L_SCB_BUF = -80,0,32,1 %; ! SCB BUFFER ADDRESS macro CDRP$W_TT_PRMPT = -80,0,16,0 %; ! PROMPT SIZE macro CDRP$L_SEQNUM = -76,0,32,0 %; ! SEQUENCE NUMBER macro CDRP$L_DCD_SRC_UCB = -76,0,32,1 %; ! DISK COPY DATA SOURCE UCB macro CDRP$L_ARB = -72,0,32,1 %; ! ACCESS RIGHTS BLOCK ADDRESS macro CDRP$L_KEYDESC = -68,0,32,1 %; ! ADDRESS OF ENCRYPTION DESCRIPTOR macro CDRP$L_WLE_PTR = -68,0,32,0 %; ! Clone Write log index macro CDRP$B_CPY_MODE = -68,0,8,0 %; ! Copy mode identifier macro CDRP$PS_KPB = -64,0,32,1 %; ! Pointer to KP block macro CDRP$PS_CCB = -60,0,32,1 %; ! Pointer to CCB for this I/O macro CDRP$Q_QIO_P1 = -56,0,0,1 %; literal CDRP$S_QIO_P1 = 8; ! QIO argument #1 (64-bits) macro CDRP$L_QIO_P1 = -56,0,32,1 %; ! (low-order 32-bit) macro CDRP$Q_QIO_P2 = -48,0,0,1 %; literal CDRP$S_QIO_P2 = 8; ! QIO argument #2 (64-bits) macro CDRP$L_QIO_P2 = -48,0,32,1 %; ! (low-order 32-bit) macro CDRP$Q_QIO_P3 = -40,0,0,1 %; literal CDRP$S_QIO_P3 = 8; ! QIO argument #3 (64-bits) macro CDRP$L_QIO_P3 = -40,0,32,1 %; ! (low-order 32-bit) macro CDRP$Q_QIO_P4 = -32,0,0,1 %; literal CDRP$S_QIO_P4 = 8; ! QIO argument #4 (64-bits) macro CDRP$L_QIO_P4 = -32,0,32,1 %; ! (low-order 32-bit) macro CDRP$Q_QIO_P5 = -24,0,0,1 %; literal CDRP$S_QIO_P5 = 8; ! QIO argument #5 (64-bits) macro CDRP$L_QIO_P5 = -24,0,32,1 %; ! (low-order 32-bit) macro CDRP$Q_QIO_P6 = -16,0,0,1 %; literal CDRP$S_QIO_P6 = 8; ! QIO argument #6 (64-bits) macro CDRP$L_QIO_P6 = -16,0,32,1 %; ! (low-order 32-bit) macro CDRP$Q_LBN_64 = -8,0,0,0 %; literal CDRP$S_LBN_64 = 8; ! 64-bit LBN ! ALL FIELDS INSERTED ABOVE THIS POINT IN THE CDRP ! MUST BE CHANGED IN THE IRPDEF.SDL FILE. ! ! macro CDRP$L_FQFL = 0,0,32,1 %; ! Fork Queue FLINK macro CDRP$L_FQBL = 4,0,32,1 %; ! Fork Queue Blink macro CDRP$W_CDRPSIZE = 8,0,16,0 %; ! Size field for positive section only macro CDRP$B_CD_TYPE = 10,0,8,0 %; ! Type, always of interest macro CDRP$B_FLCK = 11,0,8,0 %; ! Fork lock macro CDRP$L_FPC = 12,0,32,1 %; ! Fork PC macro CDRP$Q_FR3 = 16,0,0,1 %; literal CDRP$S_FR3 = 8; ! Fork R3 macro CDRP$Q_FR4 = 24,0,0,1 %; literal CDRP$S_FR4 = 8; ! Fork R4 macro CDRP$L_SAVD_RTN = 32,0,32,1 %; ! Saved return address from level 1 JSB macro CDRP$L_MSG_BUF = 36,0,32,1 %; ! Address of allocated MSCP buffer macro CDRP$L_RSPID = 40,0,32,0 %; ! Allocated Request ID macro CDRP$L_CDT = 44,0,32,1 %; ! Address of Connection Descriptor Table macro CDRP$Q_RES_WAIT_STATE = 48,0,0,0 %; literal CDRP$S_RES_WAIT_STATE = 8; ! SCS Resource Wait State Information macro CDRP$L_WAIT_STATE = 48,0,32,0 %; ! SCS Resource Wait State: >0 = SCS Wait, <0 = Port-specific Wait ! Possible SCS states: macro CDRP$L_SCS_STATE = 52,0,32,0 %; ! SCS State bits: macro CDRP$V_SYSAP_STALLED = 52,0,1,0 %; ! SYSAP context has been saved in CDRP fork block macro CDRP$V_RBUN_WANTED = 52,1,1,0 %; ! RBUN was wanted but none existed macro CDRP$L_SCS_STALL_DATA = 56,0,32,1 %; ! Data cell used by SCS to save data over a stall macro CDRP$L_RWCPTR = 60,0,32,1 %; ! RWAITCNT pointer macro CDRP$L_BD_ADDR = 64,0,32,1 %; ! Address of Buffer Descriptor that maps I/O buffer macro CDRP$L_RBUN = 68,0,32,1 %; ! Address of Resource Bundle macro CDRP$L_LBUFH_AD = 72,0,32,1 %; ! Local BUFfer Handle ADress ! Block Transfer Extension macro CDRP$L_LBOFF = 80,0,32,0 %; ! Local Byte OFFset macro CDRP$L_RBUFH_AD = 84,0,32,1 %; ! Remote BUFfer Handle ADress macro CDRP$L_RBOFF = 88,0,32,0 %; ! Remote Byte OFFset macro CDRP$L_XCT_LEN = 92,0,32,0 %; ! Transfer length in bytes ! Class Driver Extension macro CDRP$T_LBUFHNDL = 80,0,0,0 %; literal CDRP$S_LBUFHNDL = 12; ! Local buffer handle macro CDRP$L_UBARSRCE = 92,0,32,0 %; ! Scratch Cell used for DU/TUDRIVER convenience macro CDRP$L_DUTUFLAGS = 96,0,32,0 %; ! Class driver status flags: macro CDRP$V_CAND = 96,0,1,0 %; ! canceled I/O request macro CDRP$V_CANIO = 96,1,1,0 %; ! cancel operation I/O request macro CDRP$V_ERLIP = 96,2,1,0 %; ! error log in progress macro CDRP$V_PERM = 96,3,1,0 %; ! CDDB permanent IRP/CDRP macro CDRP$V_HIRT = 96,4,1,0 %; ! HIRT permanent IRP/CDRP macro CDRP$V_DENSCK = 96,5,1,0 %; ! Tape density check required macro CDRP$V_CONNWALK = 96,6,1,0 %; ! Thread walking connections macro CDRP$V_COPYSHAD = 96,7,1,0 %; ! CDRP represents an active IO$_COPYSHAD macro CDRP$V_IVCMD = 96,8,1,0 %; ! Invalid command processing in progress macro CDRP$V_WALK_2P = 96,9,1,0 %; ! Thread trying secondary path before walking other connections macro CDRP$V_LOC_ONLY = 96,10,1,0 %; ! VMS MSCPservers are to be ignored during this connection walk macro CDRP$V_LOADBAL = 96,11,1,0 %; ! A load balancing pass of connection walking is active macro CDRP$V_NORETRY = 96,12,1,0 %; ! Don't retry this cdrp if connection fails, post it instead. macro CDRP$V_INTERNAL = 96,13,1,0 %; ! Internal tempory CDRP. macro CDRP$W_DUTUCNTR = 100,0,16,0 %; ! General purpose counter macro CDRP$W_ENDMSGSIZ = 102,0,16,0 %; ! Size of most recent MSCP end message macro CDRP$L_PDT = 104,0,32,0 %; ! PDT for this CDRP macro CDRP$L_CDDB = 108,0,32,0 %; ! Current CDDB macro CDRP$L_WALK_STATE = 112,0,32,0 %; ! State for connection walking macro CDRP$L_WALK_SVPC = 116,0,32,0 %; ! Return address for resumption from connection walking macro CDRP$L_LB_CDDB = 120,0,32,0 %; ! Load balancing CDDB macro CDRP$L_DUTU_RSVD1 = 128,0,32,0 %; macro CDRP$L_DUTU_RSVD2 = 132,0,32,0 %; macro CDRP$L_DUTU_RSVD3 = 136,0,32,0 %; macro CDRP$L_DUTU_RSVD4 = 140,0,32,0 %; ! Connection management extension macro CDRP$L_VAL1 = 80,0,32,0 %; ! data value 1 macro CDRP$Q_VAL1 = 80,0,0,0 %; literal CDRP$S_VAL1 = 8; ! data value 1 macro CDRP$L_VAL2 = 88,0,32,0 %; ! data value 2 macro CDRP$Q_VAL2 = 88,0,0,0 %; literal CDRP$S_VAL2 = 8; ! data value 2 macro CDRP$L_VAL3 = 96,0,32,0 %; ! data value 3 macro CDRP$L_VAL4 = 100,0,32,0 %; ! data value 4 macro CDRP$L_VAL5 = 104,0,32,0 %; ! data value 5 macro CDRP$L_VAL6 = 108,0,32,0 %; ! data value 6 macro CDRP$L_VAL7 = 112,0,32,0 %; ! data value 7 macro CDRP$L_VAL8 = 116,0,32,0 %; ! data value 8 macro CDRP$L_VAL9 = 120,0,32,0 %; ! data value 9 macro CDRP$L_VAL10 = 124,0,32,0 %; ! data value 10 macro CDRP$L_VAL11 = 128,0,32,0 %; ! data value 11 macro CDRP$L_VAL12 = 132,0,32,0 %; ! data value 12 macro CDRP$L_FILL_VAL = 80,0,0,1 %; literal CDRP$S_FILL_VAL = 28; macro CDRP$L_CNXSVAPTE = 108,0,32,1 %; ! Block SVAPTE macro CDRP$L_CNXBCNT = 112,0,32,0 %; ! Block xfer length macro CDRP$W_CNXBOFF = 116,0,16,0 %; ! Block buffer offset macro CDRP$B_CNXRMOD = 118,0,8,0 %; ! Block access mode macro CDRP$B_CLTSTS = 119,0,8,0 %; ! A client's status field macro CDRP$L_MSGBLD = 136,0,32,1 %; ! Address of MSG BUILD routine macro CDRP$L_SAVEPC = 140,0,32,1 %; ! Caller's saved PC macro CDRP$W_SENDSEQNM = 144,0,16,0 %; ! Message sequence number macro CDRP$B_CNXSTATE = 146,0,8,0 %; ! CNX message state ! Possible states: macro CDRP$B_CNX_FUNCTION = 147,0,8,0 %; ! Function code ! Possible states: macro CDRP$L_RETRSPID = 148,0,32,0 %; ! RSPID to return macro CDRP$L_LCKMGR_FLAGS = 152,0,32,0 %; ! Lock Manager flags macro CDRP$V_HAVE_SYNCH = 152,0,1,0 %; ! This thread has LCKMGR Synchronization macro CDRP$V_MSGBLD_SYNCH = 152,1,1,0 %; ! MSGBLD Routine needs LCKMGR Synchronization macro CDRP$V_CPL_SYNCH = 152,2,1,0 %; ! Completion call back needs LCKMGR Synchronziation macro CDRP$V_STALL_SYNCH = 152,3,1,0 %; ! CDRP is stalled to obtain LCKMGR Synchronization macro CDRP$V_RM_BLKRD_DONE = 152,4,1,0 %; ! Remaster block xfer read has completed macro CDRP$V_RM_XFRPROC_DONE = 152,5,1,0 %; ! Remaster processing on block xfer has completed ! ! macro CDRP$Q_VAL13 = 160,0,0,0 %; literal CDRP$S_VAL13 = 8; macro CDRP$L_VAL13 = 160,0,32,0 %; macro CDRP$L_VAL14 = 168,0,32,0 %; macro CDRP$Q_VAL14 = 168,0,0,0 %; literal CDRP$S_VAL14 = 8; macro CDRP$L_VAL15 = 176,0,32,0 %; macro CDRP$Q_VAL15 = 176,0,0,0 %; literal CDRP$S_VAL15 = 8; macro CDRP$L_VAL16 = 184,0,32,0 %; macro CDRP$Q_VAL16 = 184,0,0,0 %; literal CDRP$S_VAL16 = 8; macro CDRP$L_VAL17 = 192,0,32,0 %; macro CDRP$Q_VAL17 = 192,0,0,0 %; literal CDRP$S_VAL17 = 8; macro CDRP$L_VAL18 = 200,0,32,0 %; macro CDRP$Q_VAL18 = 200,0,0,0 %; literal CDRP$S_VAL18 = 8; macro CDRP$L_VAL19 = 208,0,32,0 %; macro CDRP$Q_VAL19 = 208,0,0,0 %; literal CDRP$S_VAL19 = 8; macro CDRP$L_VAL20 = 216,0,32,0 %; macro CDRP$Q_VAL20 = 216,0,0,0 %; literal CDRP$S_VAL20 = 8; ! IPC SCA Transport extension macro CDRP$L_SCATP_VAL1 = 80,0,32,0 %; ! data value 1 macro CDRP$L_SCATP_VAL2 = 84,0,32,0 %; ! data value 2 macro CDRP$L_SCATP_VAL3 = 88,0,32,0 %; ! data value 3 macro CDRP$L_SCATP_VAL4 = 92,0,32,0 %; ! data value 4 macro CDRP$L_SCATP_VAL5 = 96,0,32,0 %; ! data value 5 macro CDRP$L_SCATP_VAL6 = 100,0,32,0 %; ! data value 6 macro CDRP$L_SCATP_VAL7 = 104,0,32,0 %; ! data value 7 macro CDRP$L_SCATP_VAL8 = 108,0,32,0 %; ! data value 8 macro CDRP$L_VCNXSVAPTE = 100,0,32,1 %; ! Block SVAPTE macro CDRP$L_VCNXBCNT = 104,0,32,0 %; ! Block xfer length NOTE these two fields are the macro CDRP$W_VCNXBOFF = 108,0,16,0 %; ! Block buffer offset NOTE other way round on VAX macro CDRP$B_VCNXRMOD = 110,0,8,0 %; ! Block access mode macro CDRP$B_SCATP_CLTSTS = 111,0,8,0 %; ! A client's status field macro CDRP$L_SCATP_MSGBLD = 112,0,32,1 %; ! Address of MSG BUILD routine macro CDRP$L_SCATP_SAVEPC = 116,0,32,1 %; ! Caller's saved PC macro CDRP$W_SCATP_SENDSEQNM = 120,0,16,0 %; ! Message sequence number macro CDRP$B_VCNXSTATE = 122,0,8,0 %; ! VCNX message state ! Possible states: macro CDRP$B_SCATP_FLAGS = 123,0,8,0 %; ! FLAGS byte macro CDRP$V_CDRP_PARTNER_VALID = 123,0,1,0 %; ! The CDRP_PARTNER has valid ! data. macro CDRP$V_XMT_CDRP_BLKXFR = 123,1,1,0 %; ! This is block transfer CDRP macro CDRP$V_XMT_REQ_SUCCESS = 123,2,1,0 %; ! The transmit request ! processing is done ! successfully for this CDRP. macro CDRP$V_XMT_XFER_DONE = 123,3,1,0 %; ! The data transfer is ! completed for this CDRP. macro CDRP$V_PARTNER_ABORT = 123,4,1,0 %; ! This block transfer ! request is aborted by ! partner node. macro CDRP$V_XMT_NOTIFIED = 123,5,1,0 %; ! Indicates that the associated ! VCRP has been returned to ! the user macro CDRP$V_XMT_SEGMENT = 123,6,1,0 %; ! Indicates this is part ! of a larger message macro CDRP$V_XMT_MUX_MSG = 123,7,1,0 %; ! Indicates this message ! has Session multiplexed ! link protocol header ! ! macro CDRP$L_SCATP_RETRSPID = 124,0,32,0 %; ! RSPID to return macro CDRP$L_CDRP_PARTNER = 128,0,32,1 %; ! Partner's CDRP/RCVREQ macro CDRP$L_VCRP = 132,0,32,1 %; ! VCRP addr macro CDRP$L_TLCB = 136,0,32,1 %; ! TLCB address macro CDRP$L_RCVREQ = 140,0,32,1 %; ! RCVREQ address macro CDRP$L_SAVE_RET = 144,0,32,1 %; ! Saved caller's ! return PC. macro CDRP$L_TLCBFQFL = 148,0,32,1 %; ! Fork queue (in TLCB) flink macro CDRP$L_TLCBFQBL = 152,0,32,1 %; ! Fork queue (in TLCB) blink macro CDRP$L_DISC_REASON = 156,0,32,0 %; ! Disconnect reason ! for DI msg. macro CDRP$L_SAVED_STATUS = 160,0,32,0 %; ! Save the status for the VCRP macro CDRP$B_VCNX_FUNCTION = 164,0,8,0 %; ! VCNX function ! Possible functions: ! Remote SDA Extension ! Reserve space for block transfer extension macro CDRP$L_MYSVAPTE = 96,0,32,1 %; ! System Virtual Address PTE macro CDRP$L_MYBCNT = 100,0,32,0 %; ! Byte Count macro CDRP$L_MYBOFF = 104,0,32,0 %; ! Byte Offset macro CDRP$T_MYBUFHDL = 108,0,0,0 %; literal CDRP$S_MYBUFHDL = 12; ! Buffer handle macro CDRP$L_SAVD_MSG_BUF = 120,0,32,1 %; ! Saved message buffer address ! during a BLOCK Transfer macro CDRP$L_SAVD_MSG_SIZ = 124,0,32,0 %; ! Saved message size macro CDRP$PQ_VIRT_ADDR = 128,0,0,1 %; literal CDRP$S_VIRT_ADDR = 8; ! 64-bit Virtual Address macro CDRP$L_SDA_BCNT = 136,0,32,0 %; ! Byte Count macro CDRP$L_SDA_PID = 140,0,32,0 %; ! Process ID macro CDRP$Q_PTE = 144,0,0,0 %; literal CDRP$S_PTE = 8; ! Target PTE macro CDRP$L_CPU = 152,0,32,0 %; ! Target CPU macro CDRP$W_STATE = 156,0,16,0 %; ! CDRP state ! Possible states: macro CDRP$W_BLK_STATUS = 158,0,16,0 %; ! Block transfer status literal CDRP$S_CDRPDEF = 544; ! Old size name, synonym for CDRP$S_CDRP !*** MODULE $IRPDEF *** ! + ! IRP - I/O REQUEST PACKET ! ! I/O REQUEST PACKETS ARE CONSTRUCTED BY THE QUEUE I/O REQUEST SYSTEM ! SERVICE. THE CONTENT OF AN I/O REQUEST PACKET DESCRIBES A FUNCTION TO ! BE PERFORMED ON A DEVICE UNIT. ! ! NOTE: Several fields of the IRP must be at the same offsets as their ! corresponding fields in the IRPE and CDRP. The equivalency of these ! offsets is verified by ASSUME statements in the [LIB]VFY_IRP_A_LIKES.MAR ! module. These ASSUMEs may need to be altered as well whenever an IRP ! field is removed or altered. ! - literal IRP$M_WLE_REUSE = %X'1'; literal IRP$M_WLE_SUPWL = %X'2'; literal IRP$M_WLE_READ_CONTID = %X'4'; literal IRP$M_WLE_WROTE_CONTID = %X'8'; literal IRP$M_HIST_LOGGED = %X'10'; literal IRP$M_ALLO_FAIL = %X'20'; literal IRP$M_HIST_LOST = %X'40'; literal IRP$M_TABFU = %X'80'; literal IRP$M_BUFIO = %X'1'; literal IRP$M_FUNC = %X'2'; literal IRP$M_PAGIO = %X'4'; literal IRP$M_COMPLX = %X'8'; literal IRP$M_VIRTUAL = %X'10'; literal IRP$M_CHAINED = %X'20'; literal IRP$M_SWAPIO = %X'40'; literal IRP$M_DIAGBUF = %X'80'; literal IRP$M_PHYSIO = %X'100'; literal IRP$M_TERMIO = %X'200'; literal IRP$M_MBXIO = %X'400'; literal IRP$M_EXTEND = %X'800'; literal IRP$M_FILACP = %X'1000'; literal IRP$M_MVIRP = %X'2000'; literal IRP$M_SRVIO = %X'4000'; literal IRP$M_CCB_LOOKED_UP = %X'8000'; literal IRP$M_CACHE_PAGIO = %X'10000'; literal IRP$M_FILL_BIT = %X'20000'; literal IRP$M_BUFOBJ = %X'40000'; literal IRP$M_TRUSTED = %X'80000'; literal IRP$M_FASTIO_DONE = %X'100000'; literal IRP$M_FASTIO = %X'200000'; literal IRP$M_FAST_FINISH = %X'400000'; literal IRP$M_DOPMS = %X'800000'; literal IRP$M_HIFORK = %X'1000000'; literal IRP$M_SRV_ABORT = %X'2000000'; literal IRP$M_LOCK_RELEASEABLE = %X'4000000'; literal IRP$M_DID_FAST_FDT = %X'8000000'; literal IRP$M_SYNCSTS = %X'10000000'; literal IRP$M_FINIPL8 = %X'20000000'; literal IRP$M_FILE_FLUSH = %X'40000000'; literal IRP$M_BARRIER = %X'80000000'; literal IRP$M_READ_TO_EOF = %X'80000000'; literal IRP$M_START_PAST_HWM = %X'1'; literal IRP$M_END_PAST_HWM = %X'2'; literal IRP$M_ERASE = %X'4'; literal IRP$M_PART_HWM = %X'8'; literal IRP$M_LCKIO = %X'10'; literal IRP$M_SHDIO = %X'20'; literal IRP$M_CACHEIO = %X'40'; literal IRP$M_WLE = %X'80'; literal IRP$M_CACHE_SAFE = %X'100'; literal IRP$M_NOCACHE = %X'200'; literal IRP$M_ABORTIO = %X'400'; literal IRP$M_FORCEMV = %X'800'; literal IRP$M_HBRIO = %X'1000'; literal IRP$M_ON_ACT_Q = %X'2000'; literal IRP$M_MPDEV_RETRIED = %X'4000'; literal IRP$M_PVIRP = %X'80000'; literal IRP$M_USEALTDDT = %X'100000'; literal IRP$M_PID_S0_MV = %X'200000'; literal IRP$M_CACHE_RESUME = %X'400000'; literal IRP$M_QSVD = %X'2000000'; literal IRP$M_PR_VREG = %X'4000000'; literal IRP$M_SKIP_BD_CDRP_CHECK = %X'8000000'; literal IRP$M_RWH = %X'10000000'; literal IRP$M_FCODE = %X'3F'; literal IRP$K_CDRP = 320; ! Offset to the CDRP within the IRP literal IRP$C_CDRP = 320; ! Offset to the CDRP within the IRP literal IRP$M_PIO_ERROR = %X'1'; literal IRP$M_PIO_FANOUT = %X'2'; literal IRP$M_PIO_NOQUE = %X'4'; literal IRP$M_PIO_CANCEL = %X'8'; literal IRP$M_PIO_CTHRDOK = %X'10'; literal IRP$M_PIO_PHASEII = %X'20'; literal IRP$M_PIO_BBR = %X'40'; literal IRP$M_SHD_EXPEL_REMOVED = %X'1'; literal IRP$M_SHD_RETRY = %X'2'; literal IRP$M_CLN_READY = %X'1'; literal IRP$M_CLN_DONE = %X'2'; literal IRP$M_SHADOW_SERVER_FINI = %X'4'; literal IRP$M_RTN_ALT_SUCCESS = %X'8'; literal IRP$M_WBM_DELETE = %X'10'; literal IRP$M_WBM_LOGGED = %X'20'; literal IRP$M_CLN_SCB_WRITTEN = %X'40'; literal IRP$K_BT_LEN = 416; literal IRP$C_BT_LEN = 416; literal IRP$K_CD_LEN = 464; literal IRP$C_CD_LEN = 464; literal IRP$S_IRP = 560; macro IRP$L_IOQFL = 0,0,32,1 %; ! I/O QUEUE FORWARD LINK macro IRP$L_IOQBL = 4,0,32,1 %; ! I/O QUEUE BACKWARD LINK macro IRP$W_SIZE = 8,0,16,0 %; ! SIZE OF IRP IN BYTES macro IRP$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE FOR IRP macro IRP$B_RMOD = 11,0,8,0 %; ! ACCESS MODE OF REQUEST macro IRP$V_MODE = 11,0,2,0 %; literal IRP$S_MODE = 2; ! MODE SUBFIELD macro IRP$L_PID = 12,0,32,0 %; ! PROCESS ID OF REQUESTING PROCESS macro IRP$Q_PARAM_0 = 16,0,0,1 %; literal IRP$S_PARAM_0 = 8; ! For PAGEFAULT and IOCIOPOST macro IRP$L_ACB64X_OFFSET = 16,0,32,1 %; ! Offset to ACB64X structure embedded in this IRP macro IRP$Q_PARAM_1 = 24,0,0,1 %; literal IRP$S_PARAM_1 = 8; ! For PAGEFAULT and IOCIOPOST macro IRP$L_ACB_FLAGS = 24,0,32,0 %; ! ACB flags; valid only if ACB$M_FLAGS_VALID in RMOD set macro IRP$L_THREAD_PID = 28,0,32,0 %; ! (Reserved for Kernel Threads) macro IRP$L_WIND = 32,0,32,1 %; ! ADDRESS OF WINDOW BLOCK macro IRP$L_MIRP = 32,0,32,1 %; ! LINK TO MASTER IRP macro IRP$L_KAST = 32,0,32,1 %; ! PIGGY BACK KERNEL AST ADDRESS macro IRP$L_UCB = 36,0,32,1 %; ! ADDRESS OF DEVICE UCB macro IRP$PQ_ACB64_AST = 40,0,0,1 %; literal IRP$S_ACB64_AST = 8; ! 64-bit user AST routine address macro IRP$L_SHD_IOFL = 40,0,32,1 %; ! Link to clone IRPs macro IRP$L_CTXB = 40,0,32,1 %; ! Link to CTXB macro IRP$L_IIRP_P0 = 40,0,32,1 %; ! Generic parameter cell in internal IRPs macro IRP$Q_ACB64_ASTPRM = 48,0,0,0 %; literal IRP$S_ACB64_ASTPRM = 8; ! 64-bit user AST parameter value macro IRP$L_SHAD = 48,0,32,1 %; ! SHAD address macro IRP$L_HRB = 48,0,32,1 %; ! HRB address macro IRP$L_MV_TMO = 48,0,32,1 %; ! Timeout value in internal mount verification IRPs macro IRP$L_IIRP_P1 = 48,0,32,1 %; ! Generic parameter cell in internal IRPs macro IRP$Q_USER_THREAD_ID = 56,0,0,0 %; literal IRP$S_USER_THREAD_ID = 8; ! Unique user thread identifier macro IRP$B_EFN = 64,0,8,0 %; ! EVENT FLAG NUMBER AND EVENT GROUP macro IRP$B_PRI = 65,0,8,0 %; ! BASE PRIORITY OF REQUESTING PROCESS macro IRP$B_CLN_INDX = 66,0,8,0 %; ! Shadow Clone membership index macro IRP$B_WLG_FLAGS = 67,0,8,0 %; ! These flags are shared by DUDRIVER and SHDRIVER and MSCP. macro IRP$V_WLE_REUSE = 67,0,1,0 %; ! Reuse writelog entry macro IRP$V_WLE_SUPWL = 67,1,1,0 %; ! Supplementary writelog macro IRP$V_WLE_READ_CONTID = 67,2,1,0 %; ! Read the controller ID macro IRP$V_WLE_WROTE_CONTID = 67,3,1,0 %; ! Controller ID recorded macro IRP$V_HIST_LOGGED = 67,4,1,0 %; ! Write Log Successfully created or reused macro IRP$V_ALLO_FAIL = 67,5,1,0 %; ! Allocation Failure Table successfully update macro IRP$V_HIST_LOST = 67,6,1,0 %; ! Write log state lost macro IRP$V_TABFU = 67,7,1,0 %; ! Write log table full ! ! macro IRP$L_CHAN = 68,0,32,0 %; ! Process I/O channel macro IRP$PQ_IOSB = 72,0,0,1 %; literal IRP$S_IOSB = 8; ! 64-bit address of caller's IOSB macro IRP$L_CLN_WLE = 72,0,32,0 %; ! write log entry macro IRP$Q_PARAM_2 = 72,0,0,1 %; literal IRP$S_PARAM_2 = 8; ! For PAGEFAULT and IOCIOPOST (Kthreads) macro IRP$L_IIRP_P2 = 72,0,32,1 %; ! Generic parameter cell in internal IRPs macro IRP$Q_STATUS = 80,0,0,0 %; literal IRP$S_STATUS = 8; ! Big time REQUEST STATUS macro IRP$R_STS_BITS = 80,0,32,0 %; ! Create a union so that STS bits can be overloaded macro IRP$L_STS = 80,0,32,0 %; ! Status macro IRP$V_BUFIO = 80,0,1,0 %; ! BUFFERED I/O FLAG ;THESE BITS macro IRP$V_FUNC = 80,1,1,0 %; ! 1=>READ FUNCTION ;MUST BE ADJACENT macro IRP$V_PAGIO = 80,2,1,0 %; ! PAGING I/O FLAG ;AND IN ORDER macro IRP$V_COMPLX = 80,3,1,0 %; ! COMPLEX BUFFERED I/O macro IRP$V_VIRTUAL = 80,4,1,0 %; ! VIRTUAL I/O FUNCTION macro IRP$V_CHAINED = 80,5,1,0 %; ! CHAINED BUFFERED I/O OPERATION macro IRP$V_SWAPIO = 80,6,1,0 %; ! SWAP I/O OPERATION macro IRP$V_DIAGBUF = 80,7,1,0 %; ! DIAGNOSTIC BUFFER ALLOCATED macro IRP$V_PHYSIO = 80,8,1,0 %; ! PHYSICAL I/O macro IRP$V_TERMIO = 80,9,1,0 %; ! TERMINAL I/O (FOR SELECTING PRIORITY INC) macro IRP$V_MBXIO = 80,10,1,0 %; ! MAILBOX BUFFERED READ macro IRP$V_EXTEND = 80,11,1,0 %; ! AN IRPE IS LINKED TO THIS IRP macro IRP$V_FILACP = 80,12,1,0 %; ! FILE ACP I/O (BOTH DIOCNT AND BIOCNT) macro IRP$V_MVIRP = 80,13,1,0 %; ! MOUNT VERIFICATION IRP macro IRP$V_SRVIO = 80,14,1,0 %; ! SERVER TYPE I/O (TRIGGER MOUNTVER ON ERROR BUT DON'T STALL) macro IRP$V_CCB_LOOKED_UP = 80,15,1,0 %; ! Set if IRP$PS_CCB contains valid CCB address macro IRP$V_CACHE_PAGIO = 80,16,1,0 %; ! Cached page i/o macro IRP$V_FILL_BIT = 80,17,1,0 %; ! Unused macro IRP$V_BUFOBJ = 80,18,1,0 %; ! Set if buffer object I/O macro IRP$V_TRUSTED = 80,19,1,0 %; ! Set if trusted Component I/O macro IRP$V_FASTIO_DONE = 80,20,1,0 %; ! Set if this is an available Fast-IO IRP macro IRP$V_FASTIO = 80,21,1,0 %; ! Set if IRP created by $IO_SETUP -- special delete action macro IRP$V_FAST_FINISH = 80,22,1,0 %; ! Set if IPL8 completion is expected macro IRP$V_DOPMS = 80,23,1,0 %; ! =1 if this IRP should call PMS$ logging routines macro IRP$V_HIFORK = 80,24,1,0 %; ! Device fork IPL > IPL$C_SCS macro IRP$V_SRV_ABORT = 80,25,1,0 %; ! Server I/O should be aborted macro IRP$V_LOCK_RELEASEABLE = 80,26,1,0 %; ! Forklock can be released in favor of PM spinlock on Start I/O macro IRP$V_DID_FAST_FDT = 80,27,1,0 %; ! Fast-IO may have locked buffers via standard FDT dispatch macro IRP$V_SYNCSTS = 80,28,1,0 %; ! VIOC can return SS$_SYNC on HIT if set. macro IRP$V_FINIPL8 = 80,29,1,0 %; ! Finish at IPL8 hook macro IRP$V_FILE_FLUSH = 80,30,1,0 %; ! Flush the file following this I/O macro IRP$V_BARRIER = 80,31,1,0 %; ! Insert a barrier following this I/O macro IRP$L_STS_OVERLAY = 80,0,32,0 %; macro IRP$V_READ_TO_EOF = 80,31,1,0 %; ! Reserved for Internal Use only. ! End of union macro IRP$L_STS2 = 84,0,32,0 %; ! EXTENSION OF STATUS WORD macro IRP$V_START_PAST_HWM = 84,0,1,0 %; ! I/O STARTS PAST HIGHWATER MARK macro IRP$V_END_PAST_HWM = 84,1,1,0 %; ! I/O ENDS PAST HIGHWATER MARK macro IRP$V_ERASE = 84,2,1,0 %; ! ERASE I/O FUNCTION macro IRP$V_PART_HWM = 84,3,1,0 %; ! PARTIAL HIGHWATER MARK UPDATE macro IRP$V_LCKIO = 84,4,1,0 %; ! Locked I/O request (DECnet) macro IRP$V_SHDIO = 84,5,1,0 %; ! This is a shadowing IRP macro IRP$V_CACHEIO = 84,6,1,0 %; ! uses VBN cache buffers macro IRP$V_WLE = 84,7,1,0 %; ! I/O USES A WRITE LOG Phase I ENTRY macro IRP$V_CACHE_SAFE = 84,8,1,0 %; ! this indicates that ! the request has been ! checked as regards ! caching. macro IRP$V_NOCACHE = 84,9,1,0 %; ! IO$M_NOVCACHE was ! set in QIO function macro IRP$V_ABORTIO = 84,10,1,0 %; ! set in EXE$ABORTIO macro IRP$V_FORCEMV = 84,11,1,0 %; ! set to indicate forced MV in progress macro IRP$V_HBRIO = 84,12,1,0 %; ! This is a host based raid IRP. macro IRP$V_ON_ACT_Q = 84,13,1,0 %; ! Set if application IRP has already been queued (for HBVS) macro IRP$V_MPDEV_RETRIED = 84,14,1,0 %; ! Set if I/O on a multipath device will be tried on a different path macro IRP$V_PVIRP = 84,19,1,0 %; ! Set if a path verification IRP macro IRP$V_USEALTDDT = 84,20,1,0 %; ! Set if IRP$PS_ALTDDT should be used instead of UCB$L_DDT macro IRP$V_PID_S0_MV = 84,21,1,0 %; ! Set if normal MV desired for IRP$L_PID with S0/S1 address macro IRP$V_CACHE_RESUME = 84,22,1,0 %; ! Set if cache needs to see IRP again macro IRP$V_QSVD = 84,25,1,0 %; ! Obsolete QIOserver function bit that will never be set ! However, the pain to remove it exceeds the benefit, at this time. macro IRP$V_PR_VREG = 84,26,1,0 %; ! Set if Persistent Registrations need to be verified on device macro IRP$V_SKIP_BD_CDRP_CHECK = 84,27,1,0 %; ! X-68b Inhibit BD/CDRP consistency check (MSCP.MAR X-77A1A1) macro IRP$V_RWH = 84,28,1,0 %; ! X-68b Read/Write History attached to this IRP macro IRP$PQ_VA_PTE = 88,0,0,1 %; literal IRP$S_VA_PTE = 8; ! 64-bit process virtual addr of PTE macro IRP$L_SVAPTE = 96,0,32,1 %; ! 32-bit S0/S1 address of first PTE macro IRP$PS_BUFIO_PKT = 96,0,32,1 %; ! Pointer to buffered I/O packet macro IRP$L_BCNT = 100,0,32,0 %; ! BYTE COUNT OF TRANSFER macro IRP$L_BOFF = 104,0,32,0 %; ! Byte offset macro IRP$L_OBOFF = 108,0,32,0 %; ! Original BOFF, for segmented DIO macro IRP$L_ABOFF = 108,0,32,0 %; ! "Ambient" BOFF, for NETDRIVER macro IRP$L_EXTEND = 112,0,32,1 %; ! ADDRESS OF IRPE macro IRP$PS_FDT_CONTEXT = 116,0,32,1 %; ! Contains addr of the FDT Context structure macro IRP$PS_ALTDDT = 116,0,32,1 %; ! Pointer to DDT if IRP$V_USEALTDDT is set macro IRP$R_DIOBM = 120,0,0,0 %; literal IRP$S_DIOBM = 88; ! Embedded DIOBM to handle cross-process 32-bit PTE access macro IRP$L_IOST1 = 208,0,32,0 %; ! FIRST I/O STATUS LONGWORD (FOR I/O POST) macro IRP$L_MEDIA = 208,0,32,1 %; ! MEDIA ADDRESS macro IRP$L_IOST2 = 212,0,32,0 %; ! SECOND I/O STATUS LONGWORD macro IRP$L_TT_TERM = 212,0,32,1 %; ! ADDRESS OF READ TERMINATORS MASK macro IRP$B_CARCON = 212,0,8,0 %; ! CARRIAGE CONTROL macro IRP$W_SHD_COPY_TYPE = 212,0,16,0 %; ! TYPE OF COPY TO PERFORM macro IRP$W_SHD_VUN = 212,0,16,0 %; ! VIRTUAL UNIT NUMBER macro IRP$W_SHD_DEV_TYPE = 214,0,16,0 %; ! DEVICE TYPE macro IRP$W_SHD_MSCP_DISK_MODIFIER = 214,0,16,0 %; ! FIELD FOR MODIFIERS macro IRP$Q_NT_PRVMSK = 216,0,0,0 %; literal IRP$S_NT_PRVMSK = 8; ! PRIVILEGE MASK FOR DECNET macro IRP$Q_STATION = 216,0,0,0 %; literal IRP$S_STATION = 8; ! STATION FIELD FOR DECNET DRIVERS macro IRP$Q_TT_STATE = 216,0,0,0 %; literal IRP$S_TT_STATE = 8; ! TERMINAL STATE DEFINITIONS macro IRP$L_ABCNT = 216,0,32,0 %; ! ACCUMULATED BYTES TRANSFERED macro IRP$L_OBCNT = 220,0,32,0 %; ! ORIGINAL TRANSFER BYTE COUNT macro IRP$L_FUNC = 224,0,32,0 %; ! I/O function code macro IRP$V_FCODE = 224,0,6,0 %; literal IRP$S_FCODE = 6; ! FUNCTION CODE FIELD macro IRP$V_FMOD = 224,6,10,0 %; literal IRP$S_FMOD = 10; ! FUNCTION MODIFIER FIELD macro IRP$Q_SEGVBN = 232,0,0,0 %; literal IRP$S_SEGVBN = 8; ! 64-bit VBN macro IRP$L_SEGVBN = 232,0,32,0 %; ! VIRTUAL BLOCK NUMBER OF CURRENT SEGMENT macro IRP$L_DIAGBUF = 240,0,32,1 %; ! DIAGNOSTIC BUFFER ADDRESS macro IRP$L_SCB_BUF = 240,0,32,1 %; ! SCB BUFFER ADDRESS macro IRP$W_TT_PRMPT = 240,0,16,0 %; ! PROMPT SIZE macro IRP$L_SEQNUM = 244,0,32,0 %; ! SEQUENCE NUMBER macro IRP$L_DCD_SRC_UCB = 244,0,32,1 %; ! DISK COPY DATA SOURCE UCB macro IRP$L_ARB = 248,0,32,1 %; ! ACCESS RIGHTS BLOCK ADDRESS macro IRP$L_KEYDESC = 252,0,32,1 %; ! ADDRESS OF ENCRYPTION DESCRIPTOR macro IRP$L_WLE_PTR = 252,0,32,0 %; ! Clone Write log index macro IRP$B_CPY_MODE = 252,0,8,0 %; ! Copy mode identifier macro IRP$PS_KPB = 256,0,32,1 %; ! Pointer to KP block macro IRP$PS_CCB = 260,0,32,1 %; ! Pointer to CCB for this I/O macro IRP$Q_QIO_P1 = 264,0,0,1 %; literal IRP$S_QIO_P1 = 8; ! QIO argument #1 (64-bits) macro IRP$L_QIO_P1 = 264,0,32,1 %; ! (low-order 32-bit) macro IRP$Q_QIO_P2 = 272,0,0,1 %; literal IRP$S_QIO_P2 = 8; ! QIO argument #2 (64-bits) macro IRP$L_QIO_P2 = 272,0,32,1 %; ! (low-order 32-bit) macro IRP$Q_QIO_P3 = 280,0,0,1 %; literal IRP$S_QIO_P3 = 8; ! QIO argument #3 (64-bits) macro IRP$L_QIO_P3 = 280,0,32,1 %; ! (low-order 32-bit) macro IRP$Q_PARAM_3 = 280,0,0,1 %; literal IRP$S_PARAM_3 = 8; ! (for PAGEFAULT and IOCIOPOST) macro IRP$Q_QIO_P4 = 288,0,0,1 %; literal IRP$S_QIO_P4 = 8; ! QIO argument #4 (64-bits) macro IRP$L_QIO_P4 = 288,0,32,1 %; ! (low-order 32-bit) macro IRP$Q_QIO_P5 = 296,0,0,1 %; literal IRP$S_QIO_P5 = 8; ! QIO argument #5 (64-bits) macro IRP$L_QIO_P5 = 296,0,32,1 %; ! (low-order 32-bit) macro IRP$Q_QIO_P6 = 304,0,0,1 %; literal IRP$S_QIO_P6 = 8; ! QIO argument #6 (64-bits) macro IRP$L_QIO_P6 = 304,0,32,1 %; ! (low-order 32-bit) macro IRP$Q_LBN_64 = 312,0,0,0 %; literal IRP$S_LBN_64 = 8; ! 64-bit LBN ! ALL FIELDS INSERTED ABOVE THIS POINT IN THE IRP ! MUST BE CHANGED IN THE CDRPDEF.SDL FILE. ! Standard IRP must contain space for Class Driver CDRP fields. macro IRP$L_FQFL = 320,0,32,1 %; ! Fork Queue FLINK macro IRP$L_FQBL = 324,0,32,1 %; ! Fork Queue Blink macro IRP$W_CDRPSIZE = 328,0,16,0 %; ! Size field for positive section only macro IRP$B_CD_TYPE = 330,0,8,0 %; ! Type, always of interest macro IRP$B_FLCK = 331,0,8,0 %; ! Fork Lock number macro IRP$L_FPC = 332,0,32,1 %; ! Fork PC macro IRP$Q_FR3 = 336,0,0,1 %; literal IRP$S_FR3 = 8; ! Fork R3 macro IRP$Q_FR4 = 344,0,0,1 %; literal IRP$S_FR4 = 8; ! Fork R4 macro IRP$L_SAVD_RTN = 352,0,32,1 %; ! Saved return address from level 1 JSB macro IRP$L_MSG_BUF = 356,0,32,1 %; ! Address of allocated MSCP buffer macro IRP$L_RSPID = 360,0,32,0 %; ! Allocated Request ID macro IRP$L_CDT = 364,0,32,1 %; ! Address of Connection Descriptor Table macro IRP$Q_RES_WAIT_STATE = 368,0,0,0 %; literal IRP$S_RES_WAIT_STATE = 8; ! SCS Resource Wait State macro IRP$L_SCS_STALL_DATA = 376,0,32,1 %; ! Data cell used by SCS to save data over a stall macro IRP$L_RWCPTR = 380,0,32,1 %; ! RWAITCNT pointer macro IRP$L_BD_ADDR = 384,0,32,1 %; ! Address of Buffer Descriptor that maps I/O buffer macro IRP$L_RBUN = 388,0,32,1 %; ! Address of Resource Bundle macro IRP$L_LBUFH_AD = 392,0,32,1 %; ! Local BUFfer Handle ADress macro IRP$AR_PSB = 396,0,32,1 %; ! Pointer to PSB from which QIO was called. ! Extensions to the CDRP within the IRP ! Host-Based Shadowing Extension macro IRP$B_SHD_PIO_CNT = 400,0,8,0 %; ! Tot num phys IRPs assoc. macro IRP$B_SHD_PIO_ACT = 401,0,8,0 %; ! Tot num phys IRPs active. ! Note Keep SHD_PIO_FLAGS, SHD_PIO_ERRCNT, contiguous. macro IRP$B_SHD_PIO_FLAGS = 402,0,8,0 %; ! Master Flags Byte macro IRP$V_PIO_ERROR = 402,0,1,0 %; ! Errant clone in Chain macro IRP$V_PIO_FANOUT = 402,1,1,0 %; ! Chained Clones. macro IRP$V_PIO_NOQUE = 402,2,1,0 %; ! Don't queue to server macro IRP$V_PIO_CANCEL = 402,3,1,0 %; ! This master cancelled macro IRP$V_PIO_CTHRDOK = 402,4,1,0 %; ! Copy thread validated. macro IRP$V_PIO_PHASEII = 402,5,1,0 %; ! Bi-phasic Phase II write macro IRP$V_PIO_BBR = 402,6,1,0 %; ! Bad Block Replacement has been attempted macro IRP$B_SHD_PIO_ERRCNT = 403,0,8,0 %; ! Number of errors in chain macro IRP$B_SHD_PIO_ERRINDEX = 404,0,8,0 %; ! Index of erring device macro IRP$B_SHD_PIO_ERRSEV = 405,0,8,0 %; ! Relative error severity macro IRP$Q_SHD_LOCK_FR0 = 408,0,0,0 %; literal IRP$S_SHD_LOCK_FR0 = 8; ! Lock fork R0 macro IRP$Q_SHD_LOCK_FR1 = 416,0,0,0 %; literal IRP$S_SHD_LOCK_FR1 = 8; ! Lock fork R1 macro IRP$Q_SHD_LOCK_FR2 = 424,0,0,0 %; literal IRP$S_SHD_LOCK_FR2 = 8; ! Lock fork R2 macro IRP$Q_SHD_LOCK_FR4 = 432,0,0,0 %; literal IRP$S_SHD_LOCK_FR4 = 8; ! Lock fork R4 macro IRP$Q_SHD_LOCK_FR5 = 440,0,0,0 %; literal IRP$S_SHD_LOCK_FR5 = 8; ! Lock fork R5 macro IRP$L_SHD_LOCK_FPC = 448,0,32,1 %; ! Lock fork PC macro IRP$L_SHD_PIO_ERROR = 452,0,32,0 %; ! BCNT and Error Status (SS$_) macro IRP$L_WBM_RMTSND_STS = 452,0,32,0 %; ! In WBM, return status of ioc_std$remote_set_bits macro IRP$L_SHD_PIO_LNK = 456,0,32,1 %; ! Link to clone IRP(s) macro IRP$L_WBM_REFCNT = 456,0,32,0 %; ! In WBM, count of IRP reference macro IRP$L_SHDSPC = 460,0,32,1 %; ! Shadowing return PC macro IRP$L_SHD_CONTROL_IRP = 464,0,32,1 %; ! address of control IRP macro IRP$L_SHD_TEMP = 468,0,32,1 %; ! used for temporary storage macro IRP$Q_SHD_SAVED_R1 = 472,0,0,0 %; literal IRP$S_SHD_SAVED_R1 = 8; ! second save area for WLG macro IRP$Q_SHD_SAVED_R2 = 480,0,0,0 %; literal IRP$S_SHD_SAVED_R2 = 8; macro IRP$Q_SHD_SAVED_R4 = 488,0,0,0 %; literal IRP$S_SHD_SAVED_R4 = 8; macro IRP$L_SHD_SVD_CNT_IRP = 496,0,32,0 %; ! save SHD_CONTROL_IRP macro IRP$L_SHD_SAVED_STATUS = 500,0,32,0 %; ! save area for status macro IRP$L_SHD_WLG_MODE_FPC = 504,0,32,0 %; ! saved PC for WLG_MODE fork macro IRP$L_SHD_PERLKID = 508,0,32,0 %; ! holds sublock id for ! per-disk macro IRP$L_SHD_EXPEL_TIMER = 512,0,32,0 %; ! Clone error timer macro IRP$L_SHD_EXPEL_FLAGS = 516,0,32,0 %; ! Clone IRP flags macro IRP$V_SHD_EXPEL_REMOVED = 516,0,1,0 %; ! Device is expelled macro IRP$V_SHD_RETRY = 516,1,1,0 %; ! PACKACK the Member timeout seconds macro IRP$L_SHD_EXPEL_MASK = 520,0,32,0 %; ! indicate units to be expelled in MIRP macro IRP$Q_DATACHECKRETRYCOUNTER = 528,0,0,0 %; literal IRP$S_DATACHECKRETRYCOUNTER = 8; ! For said purposes macro IRP$Q_SHD_RESERV_Q8 = 528,0,0,0 %; literal IRP$S_SHD_RESERV_Q8 = 8; ! will be needed for 64-bit saves macro IRP$Q_CURRENT_CLONE = 536,0,0,0 %; literal IRP$S_CURRENT_CLONE = 8; ! " " " macro IRP$Q_SHD_RESERV_Q9 = 536,0,0,0 %; literal IRP$S_SHD_RESERV_Q9 = 8; ! will be needed for 64-bit saves macro IRP$Q_SHD_RESERV_Q10 = 544,0,0,0 %; literal IRP$S_SHD_RESERV_Q10 = 8; ! will be needed for 64-bit saves macro IRP$B_SHD_FLAGS = 552,0,8,0 %; ! Shadow Clone Flags macro IRP$V_CLN_READY = 552,0,1,0 %; ! Clone is ready for I/O macro IRP$V_CLN_DONE = 552,1,1,0 %; ! Clone has done I/O macro IRP$V_SHADOW_SERVER_FINI = 552,2,1,0 %; ! Indicator on some IRPs to SHDRIVER that Shadow Server finished with IRP macro IRP$V_RTN_ALT_SUCCESS = 552,3,1,0 %; ! Mini Copy Return status macro IRP$V_WBM_DELETE = 552,4,1,0 %; ! Mini Copy WBM Delete bit map was called macro IRP$V_WBM_LOGGED = 552,5,1,0 %; ! Mini Copy Tracing Code macro IRP$V_CLN_SCB_WRITTEN = 552,6,1,0 %; ! Data Check recovery ! ! ! Block Transfer Extension macro IRP$L_LBOFF = 400,0,32,0 %; ! Local Byte OFFset macro IRP$L_RBUFH_AD = 404,0,32,1 %; ! Remote BUFfer Handle ADress macro IRP$L_CDRPFL = 404,0,32,1 %; macro IRP$L_RBOFF = 408,0,32,0 %; ! Remote Byte OFFset macro IRP$L_XCT_LEN = 412,0,32,0 %; ! Transfer length in bytes ! Class Driver Extension macro IRP$T_LBUFHNDL = 400,0,0,0 %; literal IRP$S_LBUFHNDL = 12; ! Local buffer handle macro IRP$L_UBARSRCE = 412,0,32,0 %; ! Scratch Cell used for DU/TUDRIVER convenience macro IRP$L_DUTUFLAGS = 416,0,32,0 %; ! Class driver status flags: macro IRP$W_DUTUCNTR = 420,0,16,0 %; ! General purpose counter macro IRP$W_ENDMSGSIZ = 422,0,16,0 %; ! Size of most recent MSCP end message macro IRP$L_PDT = 424,0,32,0 %; ! PDT for this CDRP macro IRP$L_WALK_CDDB = 428,0,32,0 %; ! Current controller for connection walking macro IRP$L_WALK_ALCLS = 432,0,32,0 %; ! Allocation class for connection walking macro IRP$L_WALK_SVPC = 436,0,32,0 %; ! Return address for resumption from connection walking macro IRP$L_LB_CDDB = 440,0,32,0 %; ! Load balancing CDDB macro IRP$L_DUTU_RSVD1 = 448,0,32,0 %; macro IRP$L_DUTU_RSVD2 = 452,0,32,0 %; macro IRP$L_DUTU_RSVD3 = 456,0,32,0 %; macro IRP$L_DUTU_RSVD4 = 460,0,32,0 %; ! File system extensions macro IRP$Q_ERASE_VBN = 400,0,0,0 %; literal IRP$S_ERASE_VBN = 8; macro IRP$L_ERASE_VBN = 400,0,32,0 %; literal IRP$K_LENGTH = 560; ! LENGTH OF STANDARD IRP literal IRP$C_LENGTH = 560; ! LENGTH OF STANDARD IRP literal IRP$S_IRPDEF = 560; ! OLD IRP SIZE FOR COMPATIBILITY !*** MODULE $ACMDEF *** ! + ! ACMDEF - ACCOUNTING MANAGER DEFINITIONS ! - literal ACM$S_ACMDEF = 2; ! Old size name, synonym literal ACM$S_ACM = 2; macro ACM$V_PROCESS = 0,0,1,0 %; ! PROCESS ACCOUNTING ENABLED macro ACM$V_IMAGE = 0,1,1,0 %; ! IMAGE ACCOUNTING ENABLED macro ACM$V_INTERACTIVE = 0,2,1,0 %; ! INTERACTIVE ACCOUNTING ENABLED macro ACM$V_LOGFAIL = 0,3,1,0 %; ! LOGIN FAILURE ACCOUNTING ENABLED macro ACM$V_SUBPROCESS = 0,4,1,0 %; ! SUBPROCESS ACCOUNTING ENABLED macro ACM$V_DETACHED = 0,5,1,0 %; ! DETACHED PROCESS ACCOUNTING ENABLED macro ACM$V_BATCH = 0,6,1,0 %; ! BATCH ACCOUNTING ENABLED macro ACM$V_NETWORK = 0,7,1,0 %; ! NETWORK PROCESS ACCOUNTING ENABLED macro ACM$V_PRINT = 0,8,1,0 %; ! PRINT JOB ACCOUNTING ENABLED macro ACM$V_USER_DATA = 0,9,1,0 %; ! USER_DATA ACCOUNTING ENABLED macro ACM$V_ACM_FUNC = 0,10,1,0 %; ! ACM FUNCTION ACCOUNTING ENABLED macro ACM$V_SYS_FUNC = 0,11,1,0 %; ! SYSTEM FUNCTION ACCOUNTING ENABLED macro ACM$V_CCAENAB = 0,12,1,0 %; ! CHARGE CODE ACCOUNTING ENABLED macro ACM$V_CCVENAB = 0,13,1,0 %; ! CHARGE CODE VALIDATION ENABLED literal ACM$S_ACMHDR = 68; macro ACM$W_TYPE = 0,0,16,0 %; ! MESSAGE TYPE macro ACM$W_MAILBOX = 2,0,16,0 %; ! MAILBOX UNIT NUMBER macro ACM$Q_PRVMSK = 4,0,0,0 %; literal ACM$S_PRVMSK = 8; ! PROCESS PRIVILEGE MASK macro ACM$L_UIC = 12,0,32,0 %; ! PROCESS UIC macro ACM$W_MEM = 12,0,16,0 %; ! MEMBER UIC macro ACM$W_GRP = 14,0,16,0 %; ! GROUP UIC macro ACM$L_PSB_ADDRESS = 4,0,32,1 %; ! ADDRESS OF CLONED PERSONA macro ACM$T_USERNAME = 16,0,0,0 %; literal ACM$S_USERNAME = 12; ! USERNAME macro ACM$T_ACCOUNT = 28,0,0,0 %; literal ACM$S_ACCOUNT = 8; ! ACCOUNT NAME macro ACM$B_PROCPRI = 36,0,8,0 %; ! PROCESS BASE PRIORITY macro ACM$B_RMOD = 37,0,8,0 %; ! REQUESTOR'S ACCESS MODE macro ACM$L_PID = 40,0,32,0 %; ! PROCESS ID macro ACM$L_STS = 44,0,32,0 %; ! PROCESS STATUS macro ACM$L_OWNER = 48,0,32,0 %; ! OWNER PROCESS ID (0 => NONE) macro ACM$T_TERMINAL = 52,0,0,0 %; literal ACM$S_TERMINAL = 8; ! TERMINAL NAME (COUNTED ASCII STRING) macro ACM$Q_SYSTIME = 60,0,0,0 %; literal ACM$S_SYSTIME = 8; ! CURRENT SYSTEM TIME literal ACM$S_ACMDEF1 = 76; ! Old size name - synonym literal ACM$S_ACM1 = 76; macro ACM$W_MSGSTS = -8,0,16,0 %; ! MSG STATUS IN MAILBOX IOSB (JOBCTL SPECIFIC) macro ACM$W_MSGLEN = -6,0,16,0 %; ! MSG LENGTH IN MAILBOX IOSB (JOBCTL SPECIFIC) macro ACM$L_PROCID = -4,0,32,0 %; ! PROCESS ID IN MAILBOX IOSB (JOBCTL SPECIFIC) ! ! SEND TO ACCOUNTING MANAGER FIELDS ! literal ACM$S_ACMDEF2 = 326; ! Old size name - synonym literal ACM$S_ACM2 = 326; macro ACM$W_USERREQ = 68,0,16,0 %; ! USER REQUEST TYPE macro ACM$T_DATA = 70,0,0,0 %; literal ACM$S_DATA = 256; ! USER DATA ! ! PROCESS/IMAGE DELETE/PURGE FIELDS ! literal ACM$M_UIDGID = %X'1'; literal ACM$K_PROCLEN = 144; ! MIN. PROCESS/IMAGE TERMINATION MESSAGE LENGTH literal ACM$C_PROCLEN = 144; ! MIN. PROCESS/IMAGE TERMINATION MESSAGE LENGTH literal ACM$S_ACMDEF3 = 160; ! Old size name - synonym literal ACM$S_ACM3 = 160; macro ACM$Q_LOGIN = 68,0,0,0 %; literal ACM$S_LOGIN = 8; ! PROCESS/IMAGE START TIME macro ACM$L_FINALSTS = 76,0,32,0 %; ! PROCESS FINAL STATUS macro ACM$L_IMGCNT = 80,0,32,0 %; ! IMAGE EXECUTION COUNT macro ACM$L_CPUTIME = 84,0,32,0 %; ! CPU USAGE macro ACM$L_PAGEFLTS = 88,0,32,0 %; ! PAGEFAULT COUNT macro ACM$L_PGFLTIO = 92,0,32,0 %; ! PAGEFAULT I/O macro ACM$L_WSPEAK = 96,0,32,0 %; ! WORKING SET PEAK macro ACM$L_PGFLPEAK = 100,0,32,0 %; ! PAGE FILE PEAK macro ACM$L_DIOCNT = 104,0,32,0 %; ! DIRECT I/O COUNT macro ACM$L_BIOCNT = 108,0,32,0 %; ! BUFFERED I/O COUNT macro ACM$L_VOLUMES = 112,0,32,0 %; ! VOLUME MOUNT COUNT macro ACM$L_VP_CPUTIME = 116,0,32,0 %; ! VECTOR CPU TIME macro ACM$W_NODEADDR = 120,0,16,0 %; ! MESSAGE OFFSET TO REMOTE NODE ADDRESS macro ACM$W_NODENAME = 122,0,16,0 %; ! MESSAGE OFFSET TO REMOTE NODE NAME macro ACM$W_REMOTEID = 124,0,16,0 %; ! MESSAGE OFFSET TO REMOTE ID macro ACM$W_IMAGENAME = 126,0,16,0 %; ! MESSAGE OFFSET TO IMAGE NAME macro ACM$W_FULLADDR = 128,0,16,0 %; ! MESSAGE OFFSET to remote PhaseV address macro ACM$W_FULLNAME = 130,0,16,0 %; ! MESSAGE OFFSET to remote Fullname macro ACM$L_FLAGS = 132,0,32,1 %; ! FLAGS macro ACM$V_UIDGID = 132,0,1,0 %; ! (0) NOT PRESENT/(1) = PRESENT macro ACM$L_POSIX_UID = 136,0,32,0 %; ! POSIX UID macro ACM$L_POSIX_GID = 140,0,32,0 %; ! POSIX GID macro ACM$L_QMGRS_USED = 144,0,0,1 %; literal ACM$S_QMGRS_USED = 16; ! BITMAP OF QUEUE MANAGERS ACCESSED BY PROCESS ! ! SNDJBC MESSAGE FIELDS ! literal ACM$S_SNDJBCDEF = 90; literal ACM$S_ACMDEF4 = 90; ! Old size name - synonym literal ACM$S_ACM4 = 90; macro ACM$L_IMAGECNT = 68,0,32,0 %; ! IMAGE COUNT FOR PROCESS macro ACM$L_EFN = 72,0,32,0 %; ! COMPLETION EVENT FLAG macro ACM$L_IOSB = 76,0,32,1 %; ! COMPLETION IOSB ADDRESS macro ACM$L_ASTADR = 80,0,32,1 %; ! COMPLETION AST ADRESS macro ACM$L_ASTPRM = 84,0,32,0 %; ! COMPLETION AST PARAMETER macro ACM$W_FUNC = 88,0,16,0 %; ! SNDJBC/GETQUI FUNCTION CODE macro ACM$T_ITMLST = 90,0,0,0 %; ! START OF ITEMLIST DATA !*** MODULE $ACBDEF *** ! + ! AST CONTROL BLOCK DEFINITIONS ! ! AST CONTROL BLOCKS EXIST AS SEPARATE STRUCTURES AND AS SUBSTRUCTURES ! WITHIN LARGER CONTROL BLOCKS SUCH AS I/O REQUEST PACKETS AND TIMER ! QUEUE ENTRIES. ! ! - literal ACB$M_FLAGS_VALID = %X'4'; literal ACB$M_POSIX_ACB = %X'8'; literal ACB$M_PKAST = %X'10'; literal ACB$M_NODELETE = %X'20'; literal ACB$M_QUOTA = %X'40'; literal ACB$M_KAST = %X'80'; literal ACB$M_THREAD_SAFE = %X'1'; literal ACB$M_THREAD_PID_VALID = %X'2'; literal ACB$M_UPCALL = %X'4'; literal ACB$M_FASTIO = %X'8'; literal ACB$M_64BITS = %X'10'; literal ACB$M_NOFLOAT = %X'20'; literal ACB$M_KAST_NOFLOAT = %X'40'; literal ACB$M_USER_THREAD_ID_VALID = %X'80'; literal ACB$M_EXCLUSIVE = %X'100'; literal ACB$M_TOLERANT = %X'200'; literal ACB$M_NODUP = %X'400'; literal ACB$M_FIRST_IN_QUEUE = %X'800'; literal ACB$S_ACB = 36; macro ACB$L_ASTQFL = 0,0,32,1 %; ! AST QUEUE FORWARD LINK macro ACB$L_ASTQBL = 4,0,32,1 %; ! AST QUEUE BACKWARD LINK macro ACB$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro ACB$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE CODE macro ACB$B_RMOD = 11,0,8,0 %; ! REQUEST ACCESS MODE macro ACB$V_MODE = 11,0,2,0 %; literal ACB$S_MODE = 2; ! MODE FOR FINAL DELIVERY macro ACB$V_FLAGS_VALID = 11,2,1,0 %; ! FLAGS IN FLAG_ID ARE VALID macro ACB$V_POSIX_ACB = 11,3,1,0 %; ! USED FOR DELIVERING SIGNALS/EVENTS macro ACB$V_PKAST = 11,4,1,0 %; ! PIGGY BACK SPECIAL KERNEL AST macro ACB$V_NODELETE = 11,5,1,0 %; ! DON'T DELETE ACB ON DELIVERY macro ACB$V_QUOTA = 11,6,1,0 %; ! ACCOUNT FOR QUOTA macro ACB$V_KAST = 11,7,1,0 %; ! SPECIAL KERNEL AST macro ACB$L_PID = 12,0,32,0 %; ! PROCESS ID OF REQUEST macro ACB$L_AST = 16,0,32,1 %; ! AST ROUTINE ADDRESS macro ACB$L_ACB64X = 16,0,32,0 %; ! OFFSET TO ACB64X STRUCTURE macro ACB$L_ASTPRM = 20,0,32,0 %; ! AST PARAMETER macro ACB$L_FLAGS = 24,0,32,0 %; ! AST CONTROL FLAGS macro ACB$V_THREAD_SAFE = 24,0,1,0 %; ! AST DOES NOT REQUIRE SYNCHRONIZATION macro ACB$V_THREAD_PID_VALID = 24,1,1,0 %; ! THREAD_PID FIELD CONTAINS A VALID THREAD PID macro ACB$V_UPCALL = 24,2,1,0 %; ! THIS AST IS ALREADY AN UPCALL macro ACB$V_FASTIO = 24,3,1,0 %; ! This ACB is really a Fast-IO IRP macro ACB$V_64BITS = 24,4,1,0 %; ! This ACB has a 64-bit AST and ASTPRM macro ACB$V_NOFLOAT = 24,5,1,0 %; ! The AST routine will not use FP registers macro ACB$V_KAST_NOFLOAT = 24,6,1,0 %; ! The special kernel AST routine will not use FP registers macro ACB$V_USER_THREAD_ID_VALID = 24,7,1,0 %; ! USER_THREAD_ID field contains a valid identifier ! Only valid in conjunction with '64BITS' macro ACB$V_EXCLUSIVE = 24,8,1,0 %; ! AST REQUIRES EXCLUSIVE ACCESS TO INNER MODE macro ACB$V_TOLERANT = 24,9,1,0 %; ! THREAD SAFE AST WHICH BLOCKS EXCLUSIVE ACCESS TO INNER MODE macro ACB$V_NODUP = 24,10,1,0 %; ! Do not queue the ACB if ASTADR/ASTPRM match ACB at the tail macro ACB$V_FIRST_IN_QUEUE = 24,11,1,0 %; ! Should be queued first. Don't put (e.g.) stalled ACBs in front. macro ACB$L_THREAD_PID = 28,0,32,0 %; ! PID of actual target KTB macro ACB$L_KAST = 32,0,32,1 %; ! INTERNAL KERNEL MODE XFER ADDRESS literal ACB$K_LENGTH = 36; ! Length of block. literal ACB$C_LENGTH = 36; ! Length of block. literal ACB$S_ACBDEF = 36; ! Old size name, synonym for ACB$S_ACB literal ACB64X$S_ACB64X = 24; macro ACB64X$PQ_AST = 0,0,0,1 %; literal ACB64X$S_AST = 8; ! 64-BIT AST ROUTINE ADDRESS macro ACB64X$Q_ASTPRM = 8,0,0,0 %; literal ACB64X$S_ASTPRM = 8; ! 64-BIT AST PARAMETER macro ACB64X$Q_USER_THREAD_ID = 16,0,0,0 %; literal ACB64X$S_USER_THREAD_ID = 8; ! Unique user thread identifier literal ACB64X$K_LENGTH = 24; ! Length of block. literal ACB64X$C_LENGTH = 24; ! Length of block. literal ACB64$M_FLAGS_VALID = %X'4'; literal ACB64$M_POSIX_ACB = %X'8'; literal ACB64$M_PKAST = %X'10'; literal ACB64$M_NODELETE = %X'20'; literal ACB64$M_QUOTA = %X'40'; literal ACB64$M_KAST = %X'80'; literal ACB64$M_THREAD_SAFE = %X'1'; literal ACB64$M_THREAD_PID_VALID = %X'2'; literal ACB64$M_UPCALL = %X'4'; literal ACB64$M_FASTIO = %X'8'; literal ACB64$M_64BITS = %X'10'; literal ACB64$M_NOFLOAT = %X'20'; literal ACB64$M_KAST_NOFLOAT = %X'40'; literal ACB64$M_USER_THREAD_ID_VALID = %X'80'; literal ACB64$M_EXCLUSIVE = %X'100'; literal ACB64$M_TOLERANT = %X'200'; literal ACB64$S_ACB64 = 64; macro ACB64$L_ASTQFL = 0,0,32,1 %; ! AST QUEUE FORWARD LINK macro ACB64$L_ASTQBL = 4,0,32,1 %; ! AST QUEUE BACKWARD LINK macro ACB64$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro ACB64$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE CODE macro ACB64$B_RMOD = 11,0,8,0 %; ! REQUEST ACCESS MODE macro ACB64$V_MODE = 11,0,2,0 %; literal ACB64$S_MODE = 2; ! MODE FOR FINAL DELIVERY macro ACB64$V_FLAGS_VALID = 11,2,1,0 %; ! FLAGS IN FLAG_ID ARE VALID (always set in ACB64) macro ACB64$V_POSIX_ACB = 11,3,1,0 %; ! USED FOR DELIVERING SIGNALS/EVENTS macro ACB64$V_PKAST = 11,4,1,0 %; ! PIGGY BACK SPECIAL KERNEL AST macro ACB64$V_NODELETE = 11,5,1,0 %; ! DON'T DELETE ACB ON DELIVERY macro ACB64$V_QUOTA = 11,6,1,0 %; ! ACCOUNT FOR QUOTA macro ACB64$V_KAST = 11,7,1,0 %; ! SPECIAL KERNEL AST macro ACB64$L_PID = 12,0,32,0 %; ! PROCESS ID OF REQUEST macro ACB64$L_ACB64X = 16,0,32,0 %; ! OFFSET TO ACB64X STRUCTURE (Always equals ACB64$Q_AST in ACB64) macro ACB64$L_FLAGS = 24,0,32,0 %; ! AST CONTROL FLAGS macro ACB64$V_THREAD_SAFE = 24,0,1,0 %; ! AST DOES NOT REQUIRE SYNCHRONIZATION macro ACB64$V_THREAD_PID_VALID = 24,1,1,0 %; ! THREAD_PID FIELD CONTAINS A VALID THREAD PID macro ACB64$V_UPCALL = 24,2,1,0 %; ! THIS AST IS ALREADY AN UPCALL macro ACB64$V_FASTIO = 24,3,1,0 %; ! This ACB is really a Fast-IO IRP macro ACB64$V_64BITS = 24,4,1,0 %; ! This ACB has a 64-bit AST and ASTPRM (always set in ACB64) macro ACB64$V_NOFLOAT = 24,5,1,0 %; ! The AST routine will not use FP registers macro ACB64$V_KAST_NOFLOAT = 24,6,1,0 %; ! The special kernel AST routine will not use FP registers macro ACB64$V_USER_THREAD_ID_VALID = 24,7,1,0 %; ! USER_THREAD_ID field contains a valid identifier macro ACB64$V_EXCLUSIVE = 24,8,1,0 %; ! AST REQUIRES EXCLUSIVE ACCESS TO INNER MODE macro ACB64$V_TOLERANT = 24,9,1,0 %; ! THREAD SAFE AST WHICH BLOCKS EXCLUSIVE ACCESS TO INNER MODE macro ACB64$L_THREAD_PID = 28,0,32,0 %; ! PID of actual target KTB macro ACB64$L_KAST = 32,0,32,1 %; ! INTERNAL KERNEL MODE XFER ADDRESS macro ACB64$PQ_AST = 40,0,0,1 %; literal ACB64$S_AST = 8; ! 64-BIT AST ROUTINE ADDRESS macro ACB64$Q_ASTPRM = 48,0,0,0 %; literal ACB64$S_ASTPRM = 8; ! 64-BIT AST PARAMETER macro ACB64$Q_USER_THREAD_ID = 56,0,0,0 %; literal ACB64$S_USER_THREAD_ID = 8; ! Unique user thread identifier literal ACB64$K_LENGTH = 64; ! Length of block. literal ACB64$C_LENGTH = 64; ! Length of block. ! ! In order to make the inner mode semaphore history trace in SDA readable, ! the following symbols are defined. These are the values that are stored ! in the second longword of the semaphore history record. SDA automatically ! tries to symbolize these values. By creating named values, the semaphore ! history can be effectively read like prose. ! ! Note that __RELEASE_KERNEL_AST is defined by hand in ASTDEL_STACK.M64 ! literal ACQUIRE_SCH$QAST = 180355072; literal ACQUIRE_KERNEL_AST = 178257920; literal ACQUIRE_EXEC_AST = 178323456; literal ACQUIRE_SPKAST = 178388992; literal ACQUIRE_PIGGYBACK = 178454528; literal __RELEASE_KERNEL_AST = 183500800; literal __RELEASE_EXEC_AST = 183566336; literal __RELEASE_SPKAST = 183631872; literal __RELEASE_PIGGYBACK = 183697408; literal __RELEASE_AST_ERROR = 183369728; literal __RELEASE_ASTFAULT = 183435264; !*** MODULE $ADBDEF *** literal ADB$S_ADB = 64; ! Defined in the form of a standard structure header macro ADB$Q_AST_PROC = 0,0,0,1 %; literal ADB$S_AST_PROC = 8; ! AST ROUTINE ADDRESS macro ADB$W_SIZE = 8,0,16,0 %; macro ADB$B_STRUCT_TYPE = 10,0,8,0 %; macro ADB$B_STRUCT_SUBTYPE = 11,0,8,0 %; macro ADB$R_FLAGS_UNION = 12,0,32,0 %; literal ADB$S_FLAGS_UNION = 4; macro ADB$L_FLAGS = 12,0,32,1 %; macro ADB$Q_AST_PARM = 16,0,0,1 %; literal ADB$S_AST_PARM = 8; macro ADB$Q_SAVED_IP = 24,0,0,1 %; literal ADB$S_SAVED_IP = 8; ! For the 0.0001% of ASTs that care about the undocumented macro ADB$Q_SAVED_PS = 32,0,0,1 %; literal ADB$S_SAVED_PS = 8; ! Alpha "Saved PC/Saved PS", we have to build these. macro ADB$L_AST_TARGET_PID = 40,0,32,0 %; ! Where an AST was queued -- we may have delivered it ! elsewhere because of IMSEM ownership macro ADB$L_AST_SPARE_LONG = 44,0,32,0 %; ! Currently unused macro ADB$Q_TIE_AST_PROC = 48,0,0,1 %; literal ADB$S_TIE_AST_PROC = 8; ! Target AST address if AST to be delivered via TIE macro ADB$Q_AST_SPARE_QUAD = 56,0,0,0 %; literal ADB$S_AST_SPARE_QUAD = 8; ! Unused, round out size to an even 40 bytes literal ADB$K_LENGTH = 64; !*** MODULE $AIBDEF *** ! + ! FORMAT OF ACP I/O BUFFER PACKET. THIS PACKET CONTAINS ALL THE DATA ! TRANSMITTED FROM THE USER TO THE ACP AND BACK FOR AN ACP FUNCTION. ! NOTE THAT THE DESCRIPTORS IN THE PACKET ARE TREATED BY BLISS CODE ! AS A BLOCKVECTOR. ! - literal AIB$K_LENGTH = 12; ! LENGTH OF PACKET HEADER literal AIB$C_LENGTH = 12; ! LENGTH OF PACKET HEADER literal AIB$S_AIBDEF = 12; ! OLD SIZE NAME, SYNONYM FOR AIB$S_AIB literal AIB$S_AIB = 12; macro AIB$L_DESCRIPT = 0,0,32,1 %; ! ADDRESS OF START OF DESCRIPTORS macro AIB$W_SIZE = 8,0,16,0 %; ! SIZE OF PACKET macro AIB$B_TYPE = 10,0,8,0 %; ! PACKET TYPE CODE !*** MODULE $ABDDEF *** literal ABD$K_LENGTH = 8; ! SIZE OF DESCRIPTOR literal ABD$C_LENGTH = 8; ! SIZE OF DESCRIPTOR literal ABD$S_ABDDEF = 8; ! OLD SIZE NAME, SYNONYM FOR ABD$S_ABD literal ABD$C_WINDOW = 0; ! DESCRIPTOR FOR WINDOW ADDRESS literal ABD$C_FIB = 1; ! DESCRIPTOR FOR FIB literal ABD$C_NAME = 2; ! DESCRIPTOR FOR NAME STRING literal ABD$C_RESL = 3; ! DESCRIPTOR FOR RESULT LENGTH literal ABD$C_RES = 4; ! DESCRIPTOR FOR RESULT STRING literal ABD$C_ATTRIB = 5; ! FIRST ATTRIBUTE DESCRIPTOR literal ABD$S_ABD = 8; macro ABD$W_TEXT = 0,0,16,0 %; ! WORD OFFSET TO DATA TEXT macro ABD$W_COUNT = 2,0,16,0 %; ! BYTE COUNT OF TEXT macro ABD$L_USERVA = 4,0,32,1 %; ! USER VIRTUAL ADDRESS OF TEXT !*** MODULE $ALFDEF *** ! + ! ! $ALFDEF - structure for auto-login file. ! ! - literal ALF$C_LENGTH = 128; literal ALF$K_LENGTH = 128; literal ALF$S_ALFDEF = 128; literal ALF$S_ALF = 128; macro ALF$T_DEVNAME = 0,0,0,0 %; literal ALF$S_DEVNAME = 63; ! Terminal device name macro ALF$T_USERNAME = 63,0,0,0 %; literal ALF$S_USERNAME = 32; ! Associated username !*** MODULE $APECSDEF *** literal APECS$Q_D21071CA_BASE = -2147483648; literal APECS$Q_D21071CA_BASE_H = 1; literal APECS$Q_D21071DA_BASE = -1610612736; literal APECS$Q_D21071DA_BASE_H = 1; literal APECS$Q_PCI_SCS = -1342177280; literal APECS$Q_PCI_SCS_H = 1; literal APECS$Q_PCI_SPARSE_IO = -1073741824; literal APECS$Q_PCI_SPARSE_IO_H = 1; literal APECS$Q_PCI_CONFIG = -536870912; literal APECS$Q_PCI_CONFIG_H = 1; literal APECS$Q_PCI_SPARSE_MEM = 0; literal APECS$Q_PCI_SPARSE_MEM_H = 2; literal APECS$Q_PCI_DENSE_MEM = 0; literal APECS$Q_PCI_DENSE_MEM_H = 3; literal APECS_PCI_NODE_COUNT = 13; literal APECS$K_MEMORY_BANKS = 9; literal APECS$M_TBASE1_32_10 = %X'FFFFFE00'; literal APECS$M_TBASE2_32_10 = %X'FFFFFE00'; literal APECS$M_PCIBASE1_SG_EN = %X'40000'; literal APECS$M_PCIBASE1_WEN = %X'80000'; literal APECS$M_PCIBASE2_SG_EN = %X'40000'; literal APECS$M_PCIBASE2_WEN = %X'80000'; literal APECS$M_PCIMASK1_31_20 = %X'FFF00000'; literal APECS$M_PCIMASK2_31_20 = %X'FFF00000'; literal APECS$M_HAXR1_PCI_31_27 = %X'F8000000'; literal APECS$M_HAXR2_PCI_1_0 = %X'3'; literal APECS$M_HAXR2_PCI_31_24 = %X'FF000000'; literal APECS$M_PMLC = %X'FF'; literal APECS$K_LENGTH = 16384; literal APECS$S_APECS = 16384; macro APECS$L_GCSR = 0,0,32,1 %; macro APECS$R_BANKSET_BASES = 2048,0,0,0 %; literal APECS$S_BANKSET_BASES = 512; macro APECS$R_BANKSET_BASE = 2048,0,0,0 %; literal APECS$S_BANKSET_BASE = 288; macro APECS$W_BASE_CSR = 2048,0,16,1 %; macro APECS$w_fill_base = 2050,0,0,1 %; literal APECS$s_fill_base = 30; macro APECS$b_fill_base_array = 2336,0,0,1 %; literal APECS$s_fill_base_array = 224; macro APECS$R_BANKSET_CONFIGS = 2560,0,0,0 %; literal APECS$S_BANKSET_CONFIGS = 512; macro APECS$R_BANKSET_CONFIG = 2560,0,0,0 %; literal APECS$S_BANKSET_CONFIG = 288; macro APECS$R_BANKSET_CONFIG_REG = 2560,0,16,0 %; literal APECS$S_BANKSET_CONFIG_REG = 2; macro APECS$W_CONFIG_CSR = 2560,0,16,1 %; macro APECS$R_BITS = 2560,0,8,0 %; literal APECS$S_BITS = 1; macro APECS$V_VALID = 2560,0,1,0 %; macro APECS$R_BANKSET_timing_aS = 3072,0,0,0 %; literal APECS$S_BANKSET_timing_aS = 512; macro APECS$R_BANKSET_timing_a = 3072,0,0,0 %; literal APECS$S_BANKSET_timing_a = 288; macro APECS$W_TIMING_A_CSR = 3072,0,16,1 %; macro APECS$R_BANKSET_timing_bS = 3584,0,0,0 %; literal APECS$S_BANKSET_timing_bS = 512; macro APECS$R_BANKSET_timing_b = 3584,0,0,0 %; literal APECS$S_BANKSET_timing_b = 288; macro APECS$W_TIMING_B_CSR = 3584,0,16,1 %; macro APECS$L_DCSR = 8192,0,32,1 %; macro APECS$L_PEAR = 8224,0,32,1 %; macro APECS$L_SEAR = 8256,0,32,1 %; macro APECS$L_DR1 = 8288,0,32,1 %; macro APECS$L_DR2 = 8320,0,32,1 %; macro APECS$L_DR3 = 8352,0,32,1 %; macro APECS$L_TBASE1 = 8384,0,32,1 %; macro APECS$V_TBASE1_32_10 = 8384,9,23,0 %; literal APECS$S_TBASE1_32_10 = 23; macro APECS$L_TBASE2 = 8416,0,32,1 %; macro APECS$V_TBASE2_32_10 = 8416,9,23,0 %; literal APECS$S_TBASE2_32_10 = 23; macro APECS$L_PCIBASE1 = 8448,0,32,1 %; macro APECS$V_PCIBASE1_SG_EN = 8448,18,1,0 %; macro APECS$V_PCIBASE1_WEN = 8448,19,1,0 %; macro APECS$L_PCIBASE2 = 8480,0,32,1 %; macro APECS$V_PCIBASE2_SG_EN = 8480,18,1,0 %; macro APECS$V_PCIBASE2_WEN = 8480,19,1,0 %; macro APECS$L_PCIMASK1 = 8512,0,32,1 %; macro APECS$V_PCIMASK1_31_20 = 8512,20,12,0 %; literal APECS$S_PCIMASK1_31_20 = 12; macro APECS$L_PCIMASK2 = 8544,0,32,1 %; macro APECS$V_PCIMASK2_31_20 = 8544,20,12,0 %; literal APECS$S_PCIMASK2_31_20 = 12; macro APECS$L_HAXR0 = 8576,0,32,1 %; macro APECS$L_HAXR1 = 8608,0,32,1 %; macro APECS$V_HAXR1_PCI_31_27 = 8608,27,5,0 %; literal APECS$S_HAXR1_PCI_31_27 = 5; macro APECS$L_HAXR2 = 8640,0,32,1 %; macro APECS$V_HAXR2_PCI_1_0 = 8640,0,2,0 %; literal APECS$S_HAXR2_PCI_1_0 = 2; macro APECS$V_HAXR2_PCI_31_24 = 8640,24,8,0 %; literal APECS$S_HAXR2_PCI_31_24 = 8; macro APECS$L_PMLT = 8672,0,32,1 %; macro APECS$V_PMLC = 8672,0,8,0 %; literal APECS$S_PMLC = 8; macro APECS$L_TLB_TAG0 = 8704,0,32,1 %; macro APECS$L_TLB_TAG1 = 8736,0,32,1 %; macro APECS$L_TLB_TAG2 = 8768,0,32,1 %; macro APECS$L_TLB_TAG3 = 8800,0,32,1 %; macro APECS$L_TLB_TAG4 = 8832,0,32,1 %; macro APECS$L_TLB_TAG5 = 8864,0,32,1 %; macro APECS$L_TLB_TAG6 = 8896,0,32,1 %; macro APECS$L_TLB_TAG7 = 8928,0,32,1 %; macro APECS$L_TLB_DATA0 = 8960,0,32,1 %; macro APECS$L_TLB_DATA1 = 8992,0,32,1 %; macro APECS$L_TLB_DATA2 = 9024,0,32,1 %; macro APECS$L_TLB_DATA3 = 9056,0,32,1 %; macro APECS$L_TLB_DATA4 = 9088,0,32,1 %; macro APECS$L_TLB_DATA5 = 9120,0,32,1 %; macro APECS$L_TLB_DATA6 = 9152,0,32,1 %; macro APECS$L_TLB_DATA7 = 9184,0,32,1 %; macro APECS$L_TBIA = 9216,0,32,1 %; !*** MODULE $APLDDEF *** literal APLD$C_LENGTH = 20; ! Length of APLD literal APLD$S_APLD$DEF = 20; ! Old size name - synonym literal APLD$S_APLD = 20; macro APLD$L_BASE = 0,0,32,1 %; ! Used as base of APLD struct macro APLD$PS_CMOD_TABLE = 0,0,32,1 %; macro APLD$PS_CMOD_TABLE_END = 4,0,32,1 %; ! end of cmod table macro APLD$PS_PLV_LIST = 8,0,32,1 %; ! base address of routine list macro APLD$PS_PLV_FLAGS_LIST = 12,0,32,1 %; ! base address of routine flags macro APLD$L_MAXCODE = 16,0,32,0 %; ! max cmod code assigned literal APLD$C_VECTOR_ENTRIES = 42; literal APLD$C_MSG_VECTOR_ENTRIES = 128; literal APLD$C_VECTOR_LENGTH = 2584; literal APLD$S_APLD$VECTOR_DEF = 2584; literal APLD$S_APLD$VECTOR = 2584; macro APLD$L_EXEC_APLD_INDEX = 0,0,32,0 %; ! # of EXEC aplds entries macro APLD$L_KERN_APLD_INDEX = 4,0,32,0 %; ! # of KERN aplds entries macro APLD$L_EXEC_RUNDOWN_INDEX = 8,0,32,0 %; ! # of EXEC rndown entries macro APLD$L_KERN_RUNDOWN_INDEX = 12,0,32,0 %; ! # of KERN rndown entries macro APLD$L_EXEC_APLD_COUNT = 16,0,32,0 %; ! # EXEC aplds relocated macro APLD$L_KERN_APLD_COUNT = 20,0,32,0 %; ! # KERN aplds relocated macro APLD$L_EXEC_RUNDOWN_COUNT = 24,0,32,0 %; ! # EXEC rndown relocated macro APLD$L_KERN_RUNDOWN_COUNT = 28,0,32,0 %; ! # KERN rndown relocated macro APLD$L_EXEC_APLD_PERM = 32,0,32,0 %; ! # of EXEC aplds process perm macro APLD$L_KERN_APLD_PERM = 36,0,32,0 %; ! # of KERN aplds process perm macro APLD$L_EXEC_RUNDOWN_PERM = 40,0,32,0 %; ! # of EXEC rndown proc perm macro APLD$L_KERN_RUNDOWN_PERM = 44,0,32,0 %; ! # of KERN rndown proc perm macro APLD$L_MESSAGE_COUNT = 48,0,32,0 %; ! # of message entries macro APLD$L_MESSAGE_PERM = 52,0,32,0 %; ! # proc perm message entries macro APLD$R_EXEC_APLD_VECTOR = 56,0,0,0 %; literal APLD$S_EXEC_APLD_VECTOR = 840; ! base of EXEC apld structures macro APLD$R_KERN_APLD_VECTOR = 896,0,0,0 %; literal APLD$S_KERN_APLD_VECTOR = 840; ! base of KERN apld structures macro APLD$PS_EXEC_RUNDOWN_VECTOR = 1736,0,0,1 %; literal APLD$S_EXEC_RUNDOWN_VECTOR = 168; ! base of EXEC rundown vector macro APLD$PS_KERN_RUNDOWN_VECTOR = 1904,0,0,1 %; literal APLD$S_KERN_RUNDOWN_VECTOR = 168; ! base of KERN rundown vector macro APLD$L_MESSAGE_VECTOR = 2072,0,0,0 %; literal APLD$S_MESSAGE_VECTOR = 512; ! base of message vector !*** MODULE $AQBDEF *** ! + ! DEFINITION OF ACP QUEUE HEADER ! - literal AQB$M_UNIQUE = %X'1'; literal AQB$M_DEFCLASS = %X'2'; literal AQB$M_DEFSYS = %X'4'; literal AQB$M_CREATING = %X'8'; literal AQB$M_XQIOPROC = %X'10'; literal AQB$K_UNDEFINED = 0; ! UNDEFINED ACP literal AQB$K_F11V1 = 1; ! FILES-11 STRUCTURE LEVEL 1 literal AQB$K_F11V2 = 2; ! FILES-11 STRUCTURE LEVEL 2 literal AQB$K_MTA = 3; ! MAGTAPE literal AQB$K_NET = 4; ! NETWORKS literal AQB$K_REM = 5; ! REMOTE I/O literal AQB$K_HBS = 6; ! HOST BASED SHADOWING literal AQB$K_F11V3 = 7; ! Files-11 presentation of ISO 9660 literal AQB$K_F11V4 = 8; ! Files-11 presentation of High Sierra literal AQB$K_F64 = 9; ! Dollar ACP type literal AQB$K_UCX = 10; ! ACP for TCP/IP Services for OpenVMS literal AQB$K_F11V5 = 11; ! FILES-11 STRUCTURE LEVEL 5 literal AQB$K_F11V6 = 12; ! FILES-11 STRUCTURE LEVEL 6 literal AQB$K_HBVS = 13; ! Host Based Volume Shadowing SCP literal AQB$C_MAXACP = 13; ! maximum AQB supported literal AQB$K_LENGTH = 40; ! SIZE OF AQB literal AQB$C_LENGTH = 40; ! SIZE OF AQB literal AQB$S_AQBDEF = 40; ! OLD SIZE NAME, SYNONYM FOR AQB$S_AQB literal AQB$S_AQB = 40; macro AQB$Q_ACPIQ = 0,0,0,0 %; literal AQB$S_ACPIQ = 8; ! INTERLOCKED QUEUE macro AQB$R_ACP_Q_STRUCTURE = 0,0,0,0 %; literal AQB$S_ACP_Q_STRUCTURE = 8; macro AQB$L_ACPQFL = 0,0,32,1 %; ! QUEUE FORWARD LINK macro AQB$L_ACPQBL = 4,0,32,1 %; ! QUEUE BACK LINK macro AQB$W_SIZE = 8,0,16,0 %; ! CONTROL BLOCK SIZE IN BYTES macro AQB$B_TYPE = 10,0,8,0 %; ! BLOCK TYPE CODE macro AQB$B_MNTCNT = 11,0,8,0 %; ! THIS FIELD IS NOW OBSOLETE ! AND HAS BEEN REPLACED BY ! AQB$L_MOUNT_COUNT macro AQB$L_ACPPID = 12,0,32,0 %; ! ACP PROCESS PID macro AQB$L_LINK = 16,0,32,1 %; ! AQB LIST LINKAGE macro AQB$B_STATUS = 20,0,8,0 %; ! STATUS BYTE macro AQB$V_UNIQUE = 20,0,1,0 %; ! ACP IS UNIQUE TO THIS DEVICE macro AQB$V_DEFCLASS = 20,1,1,0 %; ! ACP IS DEFAULT FOR THIS CLASS macro AQB$V_DEFSYS = 20,2,1,0 %; ! ACP IS DEFAULT FOR THE SYSTEM macro AQB$V_CREATING = 20,3,1,0 %; ! ACP IS CURRENTLY BEING CREATED macro AQB$V_XQIOPROC = 20,4,1,0 %; ! eXtended QIO PROCessor is being used. macro AQB$B_ACPTYPE = 21,0,8,0 %; ! ACP TYPE CODE ! ! ***** The following ACP type codes are now a user visible interface ! ***** and the values may not be changed. There are parallel definitions ! ***** in the $DVIDEF macro that define symbols of the form: ! ***** ! ***** DVI$C_ACP_F11V1 ! ***** DVI$C_ACP_F11V2 ! ***** DVI$C_ACP_MTA ! ***** ... ! ***** ! ***** All new ACP type values must be added at the end and the names ! ***** must be 5 characters or less to keep the DVI form of the name ! ***** 15 characters or less. Any additions must also be made in $DVIDEF ! ***** and in the list of ASSUMES in the module SYSGETDEV in [SYS.SRC] ! macro AQB$B_CLASS = 22,0,8,0 %; ! ACP CLASS CODE macro AQB$L_BUFCACHE = 24,0,32,1 %; ! POINTER TO BUFFER CACHE macro AQB$L_MOUNT_COUNT = 28,0,32,0 %; ! ACP MOUNT COUNT (REPLACES AQB$B_MNTCNT) macro AQB$L_ORPHANED_VCB = 32,0,32,1 %; ! Pointer to Orphaned VCB macro AQB$L_ASTADR = 36,0,32,1 %; ! AST address used for XQP-type file ! system processing !*** MODULE $ARDEF *** ! ! Definitions for IPF Access Rights ! literal AR$C_UR_KR = 0; ! Read only literal AR$C_RO = 0; ! Read only - synonym literal AR$C_URX_KRX = 1; ! Read, execute literal AR$C_RX = 1; ! Read, execute - synonym literal AR$C_URW_KRW = 2; ! Read, write literal AR$C_RW = 2; ! Read, write literal AR$C_URWX_KRWX = 3; ! Read, write, execute literal AR$C_RWX = 3; ! Read, write, execute literal AR$C_UR_KRW = 4; ! Read only, read write literal AR$C_URX_KRWX = 5; ! Read, execute, kernel: read, write, execute literal AR$C_URWX_KRW = 6; ! Read, write, execute, kernel: read, write literal AR$C_UX_KRX = 7; ! Execute, promote, Kernel: read, execute literal AR$C_PRX = 7; ! Promote, execute - synonym !*** MODULE $ARBDEF *** ! + ! ! Access Rights Block - structure defining process access rights and ! privileges. Currently part of the PCB (meaning that the size of the ! ARB declared here must track in the PCB). ! ! - literal ARB$C_HEADER = 52; ! Length of header literal ARB$K_HEADER = 52; ! Length of header literal ARB$K_LENGTH = 124; ! Structure length literal ARB$C_LENGTH = 124; ! Structure length literal ARB$S_ARBDEF = 124; literal ARB$S_ARB = 124; macro ARB$Q_PRIV = 0,0,0,0 %; literal ARB$S_PRIV = 8; ! Privilege mask macro ARB$W_SIZE = 8,0,16,0 %; ! Structure size macro ARB$B_TYPE = 10,0,8,0 %; ! Structure type macro ARB$B_FLAGS = 11,0,8,0 %; ! ARB flags (unused) macro ARB$R_CLASS = 12,0,0,0 %; literal ARB$S_CLASS = 20; ! Security classification mask macro ARB$L_RIGHTSLIST = 32,0,0,1 %; literal ARB$S_RIGHTSLIST = 20; ! Rights list descriptors macro ARB$L_PROCESS = 32,0,32,1 %; ! process rights macro ARB$L_SYSTEM = 36,0,32,1 %; ! system rights macro ARB$L_EXTENDED = 40,0,32,1 %; ! extended process rights macro ARB$L_IMAGE = 44,0,32,1 %; ! image rights macro ARB$L_RESERVED = 48,0,32,1 %; ! reserved macro ARB$R_RIGHTSDESC = 52,0,0,0 %; literal ARB$S_RIGHTSDESC = 8; ! Descriptor for local rights list macro ARB$R_LOCALRIGHTS = 60,0,0,0 %; literal ARB$S_LOCALRIGHTS = 64; ! Process local rights list macro ARB$L_UIC = 60,0,32,0 %; ! Process UID macro ARB$W_MEM = 60,0,16,0 %; ! Member number macro ARB$W_GRP = 62,0,16,0 %; ! Group number !*** MODULE $ARCDEF *** ! + ! ! Bit definitions for EXE$GL_ARCHFLAG - flags for VAX architecture differences ! ! - literal ARC$M_CHAR_EMUL = %X'10'; literal ARC$M_DCML_EMUL = %X'20'; literal ARC$M_EDPC_EMUL = %X'40'; literal ARC$M_CRC_EMUL = %X'80'; literal ARC$M_DFLT_EMUL = %X'100'; literal ARC$M_FFLT_EMUL = %X'200'; literal ARC$M_GFLT_EMUL = %X'400'; literal ARC$M_HFLT_EMUL = %X'800'; literal ARC$M_EMOD_EMUL = %X'1000'; literal ARC$M_POLY_EMUL = %X'2000'; literal ARC$M_VIRT_SCB = %X'4000'; literal ARC$M_VIRT_SPT = %X'8000'; literal ARC$M_VIRT_PCB = %X'10000'; literal ARC$M_LOAD_SMP = %X'20000'; literal ARC$S_ARCDEF = 4; literal ARC$S_ARC = 4; macro ARC$R_ARCDEF_BITS = 0,0,32,0 %; macro ARC$V_CHAR_EMUL = 0,4,1,0 %; ! Char Str Ins Emul macro ARC$V_DCML_EMUL = 0,5,1,0 %; ! Decimal String Emul macro ARC$V_EDPC_EMUL = 0,6,1,0 %; ! EDITPC Instr Emul macro ARC$V_CRC_EMUL = 0,7,1,0 %; ! CRC Instr Emul macro ARC$V_DFLT_EMUL = 0,8,1,0 %; ! D-flt Data Type Emul macro ARC$V_FFLT_EMUL = 0,9,1,0 %; ! F-flt Data Type Emul macro ARC$V_GFLT_EMUL = 0,10,1,0 %; ! G-flt Data Type Emul macro ARC$V_HFLT_EMUL = 0,11,1,0 %; ! H-flt Data Type Emul macro ARC$V_EMOD_EMUL = 0,12,1,0 %; ! EMOD Instr Emul macro ARC$V_POLY_EMUL = 0,13,1,0 %; ! POLY Instr Emul macro ARC$V_VIRT_SCB = 0,14,1,0 %; ! SCB located in virtual memory macro ARC$V_VIRT_SPT = 0,15,1,0 %; ! SPT located in virtual memory macro ARC$V_VIRT_PCB = 0,16,1,0 %; ! HWPCB located in virtual memory macro ARC$V_LOAD_SMP = 0,17,1,0 %; ! Load SMP uncoditionally !*** MODULE $ASTSTKDEF *** ! ! AST stack - this defines the architected stack contents during ! an AST. ! ! This also contains a definition of the stack frame for SCH$ASTDEL(_K). ! Offsets are defined both as positive from the base of the stack frame, and ! as negative from the base of the ASTSTK$ structure. ! ! It would be nice if ORIGIN could be used to let SDL do this, but the C ! backend doesn't know what to do with ORIGIN. ! literal ASTSTK$M_FEN = %X'1'; literal ASTSTK$M_FP_SAVE_DELAYED = %X'2'; literal ASTSTK$M_FP_SAVE_ENABLE = %X'4'; literal ASTSTK$M_FP_RECLEAR_FEN = %X'8'; literal ASTSTK$ASTDEL_FRAME$Q_FP = -8; literal ASTSTK$ASTDEL_FRAME$Q_R14 = -16; literal ASTSTK$ASTDEL_FRAME$Q_R13 = -24; literal ASTSTK$ASTDEL_FRAME$Q_RET_PC = -32; literal ASTSTK$ASTDEL_FRAME$Q_HANDLER = -40; literal ASTSTK$ASTDEL_FRAME$Q_PV = -48; literal ASTDEL_FRAME$K_SIZE = 48; literal ASTDEL_FRAME$C_SIZE = 48; literal ASTSTK$K_NO_FEN_LENGTH = 144; literal ASTSTK$C_NO_FEN_LENGTH = 144; literal ASTSTK$K_FEN_LENGTH = 336; literal ASTSTK$C_FEN_LENGTH = 336; literal ASTSTK$S_ASTSTKDEF = 336; literal ASTSTK$S_ASTSTK = 336; macro ASTSTK$Q_FLAGS = 0,0,0,0 %; literal ASTSTK$S_FLAGS = 8; macro ASTSTK$V_FEN = 0,0,1,0 %; ! Floating point enabled macro ASTSTK$V_FP_SAVE_DELAYED = 0,1,1,0 %; ! FP register save delayed macro ASTSTK$V_FP_SAVE_ENABLE = 0,2,1,0 %; ! Don't save without this bit set macro ASTSTK$V_FP_RECLEAR_FEN = 0,3,1,0 %; ! If set, clear FEN after ast macro ASTDEL_FRAME$Q_PV = 0,0,0,0 %; literal ASTDEL_FRAME$S_PV = 8; macro ASTSTK$Q_NO_FEN_R0 = 8,0,0,0 %; literal ASTSTK$S_NO_FEN_R0 = 8; macro ASTSTK$Q_F0 = 8,0,0,0 %; literal ASTSTK$S_F0 = 8; macro ASTDEL_FRAME$Q_HANDLER = 8,0,0,0 %; literal ASTDEL_FRAME$S_HANDLER = 8; macro ASTSTK$Q_NO_FEN_R1 = 16,0,0,0 %; literal ASTSTK$S_NO_FEN_R1 = 8; macro ASTSTK$Q_F1 = 16,0,0,0 %; literal ASTSTK$S_F1 = 8; macro ASTDEL_FRAME$Q_RET_PC = 16,0,0,0 %; literal ASTDEL_FRAME$S_RET_PC = 8; macro ASTSTK$Q_NO_FEN_R16 = 24,0,0,0 %; literal ASTSTK$S_NO_FEN_R16 = 8; macro ASTSTK$Q_F10 = 24,0,0,0 %; literal ASTSTK$S_F10 = 8; macro ASTDEL_FRAME$Q_R13 = 24,0,0,0 %; literal ASTDEL_FRAME$S_R13 = 8; macro ASTSTK$Q_NO_FEN_R17 = 32,0,0,0 %; literal ASTSTK$S_NO_FEN_R17 = 8; macro ASTSTK$Q_F11 = 32,0,0,0 %; literal ASTSTK$S_F11 = 8; macro ASTDEL_FRAME$Q_R14 = 32,0,0,0 %; literal ASTDEL_FRAME$S_R14 = 8; macro ASTSTK$Q_NO_FEN_R18 = 40,0,0,0 %; literal ASTSTK$S_NO_FEN_R18 = 8; macro ASTSTK$Q_F12 = 40,0,0,0 %; literal ASTSTK$S_F12 = 8; macro ASTDEL_FRAME$Q_FP = 40,0,0,0 %; literal ASTDEL_FRAME$S_FP = 8; macro ASTSTK$Q_NO_FEN_R19 = 48,0,0,0 %; literal ASTSTK$S_NO_FEN_R19 = 8; macro ASTSTK$Q_F13 = 48,0,0,0 %; literal ASTSTK$S_F13 = 8; macro ASTSTK$Q_NO_FEN_R20 = 56,0,0,0 %; literal ASTSTK$S_NO_FEN_R20 = 8; macro ASTSTK$Q_F14 = 56,0,0,0 %; literal ASTSTK$S_F14 = 8; macro ASTSTK$Q_NO_FEN_R21 = 64,0,0,0 %; literal ASTSTK$S_NO_FEN_R21 = 8; macro ASTSTK$Q_F15 = 64,0,0,0 %; literal ASTSTK$S_F15 = 8; macro ASTSTK$Q_NO_FEN_R22 = 72,0,0,0 %; literal ASTSTK$S_NO_FEN_R22 = 8; macro ASTSTK$Q_F16 = 72,0,0,0 %; literal ASTSTK$S_F16 = 8; macro ASTSTK$Q_NO_FEN_R23 = 80,0,0,0 %; literal ASTSTK$S_NO_FEN_R23 = 8; macro ASTSTK$Q_F17 = 80,0,0,0 %; literal ASTSTK$S_F17 = 8; macro ASTSTK$Q_NO_FEN_R24 = 88,0,0,0 %; literal ASTSTK$S_NO_FEN_R24 = 8; macro ASTSTK$Q_F18 = 88,0,0,0 %; literal ASTSTK$S_F18 = 8; macro ASTSTK$Q_NO_FEN_R25 = 96,0,0,0 %; literal ASTSTK$S_NO_FEN_R25 = 8; macro ASTSTK$Q_F19 = 96,0,0,0 %; literal ASTSTK$S_F19 = 8; macro ASTSTK$Q_NO_FEN_R26 = 104,0,0,0 %; literal ASTSTK$S_NO_FEN_R26 = 8; macro ASTSTK$Q_F20 = 104,0,0,0 %; literal ASTSTK$S_F20 = 8; macro ASTSTK$Q_NO_FEN_R27 = 112,0,0,0 %; literal ASTSTK$S_NO_FEN_R27 = 8; macro ASTSTK$Q_F21 = 112,0,0,0 %; literal ASTSTK$S_F21 = 8; macro ASTSTK$Q_NO_FEN_R28 = 120,0,0,0 %; literal ASTSTK$S_NO_FEN_R28 = 8; macro ASTSTK$Q_F22 = 120,0,0,0 %; literal ASTSTK$S_F22 = 8; macro ASTSTK$Q_NO_FEN_R29 = 128,0,0,0 %; literal ASTSTK$S_NO_FEN_R29 = 8; macro ASTSTK$Q_F23 = 128,0,0,0 %; literal ASTSTK$S_F23 = 8; macro ASTSTK$Q_NO_FEN_FILL = 136,0,0,0 %; literal ASTSTK$S_NO_FEN_FILL = 8; ! Fill to ensure octaword alignment macro ASTSTK$Q_F24 = 136,0,0,0 %; literal ASTSTK$S_F24 = 8; macro ASTSTK$Q_F25 = 144,0,0,0 %; literal ASTSTK$S_F25 = 8; macro ASTSTK$Q_F26 = 152,0,0,0 %; literal ASTSTK$S_F26 = 8; macro ASTSTK$Q_F27 = 160,0,0,0 %; literal ASTSTK$S_F27 = 8; macro ASTSTK$Q_F28 = 168,0,0,0 %; literal ASTSTK$S_F28 = 8; macro ASTSTK$Q_F29 = 176,0,0,0 %; literal ASTSTK$S_F29 = 8; macro ASTSTK$Q_F30 = 184,0,0,0 %; literal ASTSTK$S_F30 = 8; macro ASTSTK$Q_F31 = 192,0,0,0 %; literal ASTSTK$S_F31 = 8; ! Placeholder for octword alignment macro ASTSTK$Q_FEN_R0 = 200,0,0,0 %; literal ASTSTK$S_FEN_R0 = 8; macro ASTSTK$Q_FEN_R1 = 208,0,0,0 %; literal ASTSTK$S_FEN_R1 = 8; macro ASTSTK$Q_FEN_R16 = 216,0,0,0 %; literal ASTSTK$S_FEN_R16 = 8; macro ASTSTK$Q_FEN_R17 = 224,0,0,0 %; literal ASTSTK$S_FEN_R17 = 8; macro ASTSTK$Q_FEN_R18 = 232,0,0,0 %; literal ASTSTK$S_FEN_R18 = 8; macro ASTSTK$Q_FEN_R19 = 240,0,0,0 %; literal ASTSTK$S_FEN_R19 = 8; macro ASTSTK$Q_FEN_R20 = 248,0,0,0 %; literal ASTSTK$S_FEN_R20 = 8; macro ASTSTK$Q_FEN_R21 = 256,0,0,0 %; literal ASTSTK$S_FEN_R21 = 8; macro ASTSTK$Q_FEN_R22 = 264,0,0,0 %; literal ASTSTK$S_FEN_R22 = 8; macro ASTSTK$Q_FEN_R23 = 272,0,0,0 %; literal ASTSTK$S_FEN_R23 = 8; macro ASTSTK$Q_FEN_R24 = 280,0,0,0 %; literal ASTSTK$S_FEN_R24 = 8; macro ASTSTK$Q_FEN_R25 = 288,0,0,0 %; literal ASTSTK$S_FEN_R25 = 8; macro ASTSTK$Q_FEN_R26 = 296,0,0,0 %; literal ASTSTK$S_FEN_R26 = 8; macro ASTSTK$Q_FEN_R27 = 304,0,0,0 %; literal ASTSTK$S_FEN_R27 = 8; macro ASTSTK$Q_FEN_R28 = 312,0,0,0 %; literal ASTSTK$S_FEN_R28 = 8; macro ASTSTK$Q_FEN_R29 = 320,0,0,0 %; literal ASTSTK$S_FEN_R29 = 8; macro ASTSTK$Q_FEN_FILL = 328,0,0,0 %; literal ASTSTK$S_FEN_FILL = 8; ! Fill to ensure octaword alignment !*** MODULE $BBSDEF *** ! + ! ! Structure of message from disk ACP to bad block scan utility. ! ! - literal BBS$K_LENGTH = 18; literal BBS$C_LENGTH = 18; literal BBS$S_BBSDEF = 18; literal BBS$S_BBS = 18; macro BBS$B_MSGTYPE = 0,0,8,0 %; ! message type code (MSG$C_SCANBAD) macro BBS$W_SEQUENCE = 4,0,16,0 %; ! message sequence number macro BBS$L_UCB = 8,0,32,1 %; ! UCB address of device macro BBS$W_FID = 12,0,0,0 %; literal BBS$S_FID = 6; ! file ID of file !*** MODULE $BDDEF *** ! + ! BD - Buffer Descriptor format in Buffer Descriptor Leaf table ! - literal BD$M_VALID = %X'1'; literal BD$M_RO = %X'2'; literal BD$K_LENGTH = 64; ! Length of a Buffer Descriptor literal BD$C_LENGTH = 64; ! Length of a Buffer Descriptor literal BD$C_PORT_PAGE_SZ = 8192; ! 8K Port Page Size literal BD$C_BD_IN_BDL = 128; ! Number of BDs in a BDL literal BD$S_SHIFT_SIZE = 5; ! Factor for shift left of a BDL index to get BD address within a BDL ! Note this shift size must reflect the NPort requirement that the BDL_INDEX be literal BD$S_BDDEF = 64; ! Old size name, synonym literal BD$S_BUFDESC = 64; macro BD$Q_FILL_1 = 0,0,0,0 %; literal BD$S_FILL_1 = 8; ! Fill for hex alignement. If possible keep bit 16 of this field zero so ! the even number descriptor is never treated as a valid BD. macro BD$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro BD$B_TYPE = 10,0,8,0 %; ! Structure Type macro BD$B_SUBTYPE = 11,0,8,0 %; ! Structure Subtype for BD macro BD$L_CDRP = 12,0,32,1 %; ! Addr of associated CDRP macro BD$L_LINK = 12,0,32,1 %; ! or addr of next free descriptor macro BD$Q_ROOT_PTR0_VIR = 16,0,0,0 %; literal BD$S_ROOT_PTR0_VIR = 8; ! Virtual Root Pointer 0 macro BD$Q_ROOT_PTR1_VIR = 24,0,0,0 %; literal BD$S_ROOT_PTR1_VIR = 8; ! Virtual Root Pointer 1 macro BD$W_PAGE_OFFSET = 32,0,16,0 %; ! Byte offset of start of buffer macro BD$W_FLAGS = 34,0,16,0 %; ! Flags word macro BD$V_VALID = 34,0,1,0 %; ! Valid bit macro BD$V_RO = 34,1,1,0 %; ! Read-Only access mode check enabled if set ! - Currently not supported macro BD$L_BNAME = 36,0,32,0 %; ! Buffer Name macro BD$V_BDL_INDEX = 36,0,8,0 %; literal BD$S_BDL_INDEX = 8; ! BDL Index macro BD$V_BDLT_INDEX = 36,8,12,0 %; literal BD$S_BDLT_INDEX = 12; ! BDLT Index macro BD$V_KEY = 36,20,12,0 %; literal BD$S_KEY = 12; ! Sequence Number macro BD$L_BUF_LEN = 40,0,32,0 %; ! Length of mapped buffer macro BD$L_SBZ1 = 44,0,32,0 %; ! Should be zero ! used by ports with no MAP routine (like PEDRIVER). macro BD$L_SVAPTE = 48,0,32,1 %; ! First SVAPTE of User Data Buffer macro BD$Q_ROOT_PTR0_PHY = 48,0,0,0 %; literal BD$S_ROOT_PTR0_PHY = 8; ! Physical Root Pointer 0 macro BD$V_PTR0_TYPE = 48,0,2,0 %; literal BD$S_PTR0_TYPE = 2; ! Type macro BD$Q_ROOT_PTR1_PHY = 56,0,0,0 %; literal BD$S_ROOT_PTR1_PHY = 8; ! Physical Root Pointer 1 macro BD$V_PTR1_TYPE = 56,0,2,0 %; literal BD$S_PTR1_TYPE = 2; ! Type macro BD$L_FILL_2 = 48,0,32,1 %; ! Skip over "First SVAPTE of User Data Buffer" macro BD$L_CRCTX = 52,0,32,1 %; ! Address of CRCTX assoicated with this I/O request ! based on a buffer descriptor size of 32. !*** MODULE $BDLPTRDEF *** ! + ! BDLPTR - NPORT Buffer Descriptor Leaf pointer ! ! This table is sharable among all SCS ports using the NPORT architectured ! named buffer convention. buffer descriptors (BD's) are allocated for SCS ! block transfers. the BDLT must be aligned on a an 8K boundary. The BDLT can ! support up to 4096 BDL pointers but in this implementation will only ! support up to 32 BDL pointers for a maximum of 8148 buffer descriptors. This ! definition only defines a single BDL pointer, each BDL pointer has the ! identical structure. The VMS implementation uses the first few pointers as ! defined in CMNBDLTDEF. ! ! 63 1 0 ! ----------------------------------------------------- ! | BDL_PTR_PHY |V| V=valid ! ----------------------------------------------------- ! | BDL_PTR_VIR | ! ----------------------------------------------------- ! - literal BDLPTR$M_VALID = %X'1'; literal BDLPTR$C_LENGTH = 16; ! Length of structure literal BDLPTR$S_SHIFT_SIZE = 4; ! Factor for shift left of BDLT index to get BDL address literal BDLPTR$S_BDLPTRDEF = 16; literal BDLPTR$S_BDLPTR = 16; macro BDLPTR$Q_PHY_ADDR = 0,0,0,0 %; literal BDLPTR$S_PHY_ADDR = 8; ! Buffer Descriptor 0 Leaf Physical Pointer macro BDLPTR$V_VALID = 0,0,1,0 %; ! Valid Bit macro BDLPTR$Q_VIR_ADDR = 8,0,0,0 %; literal BDLPTR$S_VIR_ADDR = 8; ! Buffer Descriptor 0 Leaf Virtual Pointer !*** MODULE $BNAMDEF *** ! + ! BNAM - NPORT Buffer Name Descriptor ! ! - literal BNAM$C_LENGTH = 4; ! Length of structure literal BNAM$M_BDLT_MASK = -1048321; ! Mask to use extract BDLT index literal BNAM$M_BDL_MASK = -256; ! Mask to use extract BDL index literal BNAM$M_KEY_MASK = 1048575; ! Mask to use extract KEY literal BNAM$S_BNAMDEF = 4; literal BNAM$S_BNAM = 4; macro BNAM$L_BNAME = 0,0,32,1 %; ! Buffer NAME macro BNAM$V_BDL_INDEX = 0,0,8,0 %; literal BNAM$S_BDL_INDEX = 8; ! BDL Index macro BNAM$V_BDLT_INDEX = 0,8,12,0 %; literal BNAM$S_BDLT_INDEX = 12; ! BDLT Index macro BNAM$V_KEY = 0,20,12,0 %; literal BNAM$S_KEY = 12; ! Sequence Number !*** MODULE $BODDEF *** ! + ! BOD - Buffer Object Descriptor ! ! A buffer object descriptor defines a buffer object used ! by the I/O subsystem. ! - literal BOD$M_DELPEN = %X'1'; literal BOD$M_NOQUOTA = %X'2'; literal BOD$M_S2_WINDOW = %X'4'; literal BOD$M_NOSVA = %X'8'; literal BOD$M_SYSBUFOBJ = %X'10'; literal BOD$S_BOD = 64; macro BOD$L_FLINK = 0,0,32,1 %; ! FLINK into PCB list macro BOD$L_BLINK = 4,0,32,1 %; ! BLINK into PCB list macro BOD$W_SIZE = 8,0,16,0 %; ! Size of fixed portion of BOOTCB macro BOD$B_TYPE = 10,0,8,0 %; ! Type of control block macro BOD$L_ACMODE = 12,0,32,0 %; ! Owner access mode macro BOD$L_SEQNUM = 16,0,32,0 %; ! Sequence # at object creation macro BOD$L_REFCNT = 20,0,32,0 %; ! No. of references to this BOD macro BOD$L_FLAGS = 24,0,32,0 %; ! Flags longword macro BOD$V_DELPEN = 24,0,1,0 %; ! Delete pending macro BOD$V_NOQUOTA = 24,1,1,0 %; ! No quota charge for S0 window macro BOD$V_S2_WINDOW = 24,2,1,0 %; ! Buffer object mapped into S2 space macro BOD$V_NOSVA = 24,3,1,0 %; ! BO without associated system space macro BOD$V_SYSBUFOBJ = 24,4,1,0 %; ! System buffer object (no process space ties) macro BOD$L_PID = 28,0,32,0 %; ! PID of creating process macro BOD$PQ_BASEPVA = 32,0,0,1 %; literal BOD$S_BASEPVA = 8; ! Base process address of buffer object macro BOD$PQ_BASESVA = 40,0,0,1 %; literal BOD$S_BASESVA = 8; ! Base S2 address (valid iff BOD$V_S2_WINDOW) macro BOD$L_BASESVA = 40,0,32,1 %; ! Base system address of buffer object macro BOD$PQ_VA_PTE = 48,0,0,1 %; literal BOD$S_VA_PTE = 8; ! S2 VA_PTE (valid iff BOD$V_S2_WINDOW) macro BOD$PS_SVAPTE = 48,0,32,1 %; ! SVAPTE of first system page of buffer object macro BOD$L_PAGCNT = 56,0,32,0 %; ! No. of pages in buffer object literal BOD$K_LENGTH = 64; ! LENGTH OF STRUCTURE literal BOD$C_LENGTH = 64; ! LENGTH OF STRUCTURE literal BOD$S_BODDEF = 64; !*** MODULE $boocmddef *** ! + ! Definitions for SYSGEN/SYSBOOT command options flags ! - literal boocmd$m_nocheck = %X'1'; literal boocmd$m_noreset = %X'2'; literal boocmd$m_save = %X'4'; literal boocmd$m_user = %X'8'; literal boocmd$m_pagefile = %X'10'; literal boocmd$m_noncontig = %X'20'; literal boocmd$m_select = %X'40'; literal boocmd$m_exclude = %X'80'; literal boocmd$m_cont = %X'100'; literal boocmd$M_DEFAULT = %X'200'; literal boocmd$m_usefile = %X'400'; literal boocmd$m_dishex = %X'800'; literal boocmd$m_autolog = %X'1000'; literal boocmd$m_output = %X'2000'; literal boocmd$m_input = %X'4000'; literal boocmd$m_setoutput = %X'8000'; literal boocmd$m_terminal = %X'10000'; literal boocmd$m_contig = %X'20000'; literal boocmd$m_nochkpnt = %X'40000'; literal boocmd$m_remote = %X'80000'; literal boocmd$m_logical = %X'100000'; literal boocmd$m_uart1 = %X'200000'; literal boocmd$m_uart2 = %X'400000'; literal boocmd$m_uart3 = %X'800000'; literal boocmd$m_ni = %X'1000000'; literal boocmd$m_nl_user = %X'2000000'; literal boocmd$m_dins_all = %X'4000000'; literal boocmd$m_dins_idx = %X'8000000'; literal boocmd$m_setcmd = %X'10000000'; literal boocmd$m_clr_modify = %X'20000000'; literal boocmd$m_dynamic_only = %X'40000000'; literal boocmd$S_boocmddef = 4; literal boocmd$S_boocmd = 4; macro boocmd$v_nocheck = 0,0,1,0 %; macro boocmd$v_noreset = 0,1,1,0 %; macro boocmd$v_save = 0,2,1,0 %; macro boocmd$v_user = 0,3,1,0 %; macro boocmd$v_pagefile = 0,4,1,0 %; macro boocmd$v_noncontig = 0,5,1,0 %; macro boocmd$v_select = 0,6,1,0 %; macro boocmd$v_exclude = 0,7,1,0 %; macro boocmd$v_cont = 0,8,1,0 %; macro boocmd$V_DEFAULT = 0,9,1,0 %; macro boocmd$v_usefile = 0,10,1,0 %; macro boocmd$v_dishex = 0,11,1,0 %; macro boocmd$v_autolog = 0,12,1,0 %; macro boocmd$v_output = 0,13,1,0 %; macro boocmd$v_input = 0,14,1,0 %; macro boocmd$v_setoutput = 0,15,1,0 %; macro boocmd$v_terminal = 0,16,1,0 %; macro boocmd$v_contig = 0,17,1,0 %; macro boocmd$v_nochkpnt = 0,18,1,0 %; macro boocmd$v_remote = 0,19,1,0 %; macro boocmd$v_logical = 0,20,1,0 %; macro boocmd$v_uart1 = 0,21,1,0 %; macro boocmd$v_uart2 = 0,22,1,0 %; macro boocmd$v_uart3 = 0,23,1,0 %; macro boocmd$v_ni = 0,24,1,0 %; macro boocmd$v_nl_user = 0,25,1,0 %; macro boocmd$v_dins_all = 0,26,1,0 %; macro boocmd$v_dins_idx = 0,27,1,0 %; macro boocmd$v_setcmd = 0,28,1,0 %; macro boocmd$v_clr_modify = 0,29,1,0 %; macro boocmd$v_dynamic_only = 0,30,1,0 %; !*** MODULE $BOODEF *** ! + ! BOO - Boot Control Block ! ! A boot control block is produced by SYSBOOT and placed in non-paged ! pool. It is pointed to by the cell EXE$GL_BOOTCB and contains ! the mapping information for SYSDUMP.DMP. ! - literal BOO$K_LENGTH = 52; literal BOO$C_LENGTH = 52; literal BOO$S_BOODEF = 52; literal BOO$S_BOO = 52; macro BOO$L_CHECKSUM = 0,0,32,0 %; ! Checksum macro BOO$L_TIMELBN = 4,0,32,0 %; ! LBN of system time quadword macro BOO$W_SIZE = 8,0,16,0 %; ! Size of fixed portion of BOOTCB macro BOO$B_TYPE = 10,0,8,0 %; ! Type of control block macro BOO$B_SUBTYP = 11,0,8,0 %; ! Sub-type macro BOO$L_SPARE = 12,0,32,0 %; ! Was "Starting VBN for dump file" macro BOO$L_DMP_SIZE = 16,0,32,0 %; ! Size in blocks of dump file ! from starting VBN to end of file macro BOO$L_DMP_MAP = 20,0,32,1 %; ! Adr of map for SYSDUMP.DMP macro BOO$L_BUG_WCB = 24,0,32,1 %; ! Adr of WCB for bugcheck image macro BOO$L_BUG_IMAGE_VA = 28,0,32,1 %; ! Base VA of image containing bugcheck macro BOO$PQ_BUG_PTE_ADDR = 32,0,0,1 %; literal BOO$S_BUG_PTE_ADDR = 8; ! PTEs allocated to do QIOs to dump file macro BOO$L_SCB_LBN = 40,0,32,0 %; ! LBN of the storage control block (SCB) on system disk macro BOO$L_ERL_SIZE = 44,0,32,0 %; ! Size in blocks of error log dump file ! from starting VBN to end of file macro BOO$L_ERL_MAP = 48,0,32,1 %; ! Adr of map for SYS$ERRLOG.DMP !*** MODULE $boopardef *** literal boopar$k_length = 360; ! Length of argument list literal boopar$S_booparam = 360; macro boopar$l_arg_revision = 0,0,32,0 %; ! Argument list revision macro boopar$l_pfn_map = 4,0,32,1 %; ! Address of allocation bitmap macro boopar$l_state = 8,0,32,0 %; ! exe$gl_state macro boopar$l_va_to_vpn = 12,0,32,0 %; ! Negated vpn_to_va macro boopar$l_vpn_to_va = 16,0,32,0 %; ! Size of byte within page field macro boopar$l_bwp_mask = 20,0,32,0 %; ! Byte within a page mask macro boopar$l_file_cache = 24,0,32,1 %; ! addr of file cache macro boopar$l_cache_size = 28,0,32,0 %; ! file cache size macro boopar$l_sptbase = 32,0,32,1 %; ! SPT base macro boopar$l_scb = 36,0,32,1 %; ! SCB address macro boopar$l_hpdesc = 40,0,32,1 %; ! ldr huge page structure macro boopar$l_xdtscb = 44,0,32,1 %; ! Xdelta's SCB address macro boopar$pq_l1_base = 48,0,0,1 %; literal boopar$s_l1_base = 8; ! VA of L1PT in PT_space for process space macro boopar$pq_l2_base = 56,0,0,1 %; literal boopar$s_l2_base = 8; ! VA of L2PTs in PT_space for process space macro boopar$q_non_va_mask = 64,0,0,1 %; literal boopar$s_non_va_mask = 8; ! Mask for bits above L1 MSB macro boopar$pq_pt_base = 72,0,0,1 %; literal boopar$s_pt_base = 8; ! VA of PT_space base for process space macro boopar$l_system_l1_index = 80,0,32,0 %; ! L1 index of S0/S1 L1PTE macro boopar$l_pt_space_l1_index = 84,0,32,0 %; ! L1 index of self-mapped L1PTE for process space macro boopar$pq_gap_lo = 88,0,0,1 %; literal boopar$s_gap_lo = 8; ! Low address end of gap macro boopar$pq_gap_hi = 96,0,0,1 %; literal boopar$s_gap_hi = 8; ! High address end of gap macro boopar$pq_proc_space_lim = 104,0,0,1 %; literal boopar$s_proc_space_lim = 8; ! Highest process space address macro boopar$pq_s0s1base_pte_addr = 112,0,0,1 %; literal boopar$s_s0s1base_pte_addr = 8; ! Address of PTE that maps base of S0/S1 space macro boopar$pq_shared_va_ptes = 120,0,0,1 %; literal boopar$s_shared_va_ptes = 8; ! Boundary between process and system ptes macro boopar$pq_sys_virt_base = 128,0,0,1 %; literal boopar$s_sys_virt_base = 8; ! Base address of system space (lowest addr in S2) macro boopar$l_va_bits = 136,0,32,0 %; ! Number of bits in 3 level fields plus byte ! within page field macro boopar$q_virbnd = 144,0,0,1 %; literal boopar$s_virbnd = 8; ! VIRBND register contents macro boopar$q_sysptbr = 152,0,0,1 %; literal boopar$s_sysptbr = 8; ! System Page Table Base Register macro boopar$pq_l1_basesys = 160,0,0,1 %; literal boopar$s_l1_basesys = 8; ! VA of L1PT in PT_space for system space macro boopar$pq_l2_basesys = 168,0,0,1 %; literal boopar$s_l2_basesys = 8; ! VA of L2PTs in PT_space for system space macro boopar$pq_pt_basesys = 176,0,0,1 %; literal boopar$s_pt_basesys = 8; ! VA of PT_space base for system space macro boopar$l_pt_space_l1_indexsys = 184,0,32,0 %; ! L1 index of self-mapped L1PTE for system space macro boopar$q_pal_proc = 192,0,0,1 %; literal boopar$s_pal_proc = 8; ! Address of IA64 PAL code procedure entry point macro boopar$q_non_pt_mask = 200,0,0,1 %; literal boopar$s_non_pt_mask = 8; ! Mask for bits not in segments macro boopar$q_level_width = 208,0,0,1 %; literal boopar$s_level_width = 8; ! size of each segment field in VA; aka "level width" macro boopar$q_non_pa_mask = 216,0,0,1 %; literal boopar$s_non_pa_mask = 8; ! mask for bits not in physical address range macro boopar$q_ptes_per_page = 224,0,0,1 %; literal boopar$s_ptes_per_page = 8; ! how many PTEs fit into a page macro boopar$gpq_idt = 232,0,0,1 %; literal boopar$s_idt = 8; ! pointer to IDT table macro boopar$pq_sal_plabel0 = 240,0,0,1 %; literal boopar$s_sal_plabel0 = 8; ! Code address of SAL macro boopar$pq_sal_plabel1 = 248,0,0,1 %; literal boopar$s_sal_plabel1 = 8; ! GP for SAL macro boopar$pq_fpswa = 256,0,0,1 %; literal boopar$s_fpswa = 8; ! Address of FPSWA routine macro boopar$pq_efi_runtime_services = 264,0,0,1 %; literal boopar$s_efi_runtime_services = 8; ! Address of EFI runtime service routines macro boopar$pq_efi_system_table = 272,0,0,1 %; literal boopar$s_efi_system_table = 8; ! Address of EFI system table macro boopar$pq_vcons_plabel0 = 280,0,0,1 %; literal boopar$s_vcons_plabel0 = 8; ! Code address of vcons service macro boopar$pq_vcons_plabel1 = 288,0,0,1 %; literal boopar$s_vcons_plabel1 = 8; ! GP for vcons service macro boopar$q_min_bitmap_pfn = 296,0,0,1 %; literal boopar$s_min_bitmap_pfn = 8; ! Lowest PFN described by the first allocation bitmap macro boopar$q_max_bitmap_pfn = 304,0,0,1 %; literal boopar$s_max_bitmap_pfn = 8; ! Highest PFN described by the first allocation bitmap macro boopar$pq_shsba_plabel0 = 312,0,0,1 %; literal boopar$s_shsba_plabel0 = 8; ! Code address of shsba service macro boopar$pq_shsba_plabel1 = 320,0,0,1 %; literal boopar$s_shsba_plabel1 = 8; ! GP for shsba service macro boopar$pq_esi_table = 328,0,0,1 %; literal boopar$s_esi_table = 8; ! Extensible SAL interface table macro boopar$q_min_bitmap_pfn2 = 336,0,0,1 %; literal boopar$s_min_bitmap_pfn2 = 8; ! Lowest PFN described by the second allocation bitmap macro boopar$q_max_bitmap_pfn2 = 344,0,0,1 %; literal boopar$s_max_bitmap_pfn2 = 8; ! Highest PFN described by the second allocation bitmap macro boopar$l_pfn_map2 = 352,0,32,1 %; ! Address of second allocation bitmap !*** MODULE BOOSTATEDEF *** literal BOOSTATE$M_SYSBOOT = %X'1'; literal BOOSTATE$M_INIT = %X'2'; literal BOOSTATE$M_SWAPPER = %X'4'; literal BOOSTATE$M_SYSINIT = %X'8'; literal BOOSTATE$M_STARTUP = %X'10'; literal BOOSTATE$M_PFN_INIT = %X'20'; literal BOOSTATE$M_POOL_INIT = %X'40'; literal BOOSTATE$M_XQP = %X'80'; literal BOOSTATE$M_RMS = %X'100'; literal BOOSTATE$M_CONSOLE = %X'200'; literal BOOSTATE$M_SPNLCK_AVAIL = %X'400'; literal BOOSTATE$M_NORDONLY = %X'800'; literal BOOSTATE$M_EXEC_SLICING = %X'1000'; literal BOOSTATE$M_OBJREG = %X'2000'; literal BOOSTATE$M_AUDITING = %X'4000'; literal BOOSTATE$M_OBJECT_SERVICE = %X'8000'; literal BOOSTATE$M_FOREIGN_BOOT = %X'10000'; literal BOOSTATE$M_LANACP = %X'20000'; literal BOOSTATE$M_SPARE_1 = %X'40000'; literal BOOSTATE$M_STACONFIG_IP = %X'80000'; literal BOOSTATE$M_POOL_AVAIL = %X'100000'; literal BOOSTATE$M_SYSMUT_INIT = %X'200000'; literal BOOSTATE$M_BUGCHECK_INIT = %X'400000'; literal BOOSTATE$S_BOOSTATE = 4; macro BOOSTATE$L_BITS = 0,0,32,1 %; macro BOOSTATE$V_SYSBOOT = 0,0,1,0 %; ! SYSBOOT is executing macro BOOSTATE$V_INIT = 0,1,1,0 %; ! INIT is executing macro BOOSTATE$V_SWAPPER = 0,2,1,0 %; ! The SWAPPER process is executing macro BOOSTATE$V_SYSINIT = 0,3,1,0 %; ! The SYSINIT process is executing macro BOOSTATE$V_STARTUP = 0,4,1,0 %; ! The STARTUP process is executing macro BOOSTATE$V_PFN_INIT = 0,5,1,0 %; ! The PFN database is initialized macro BOOSTATE$V_POOL_INIT = 0,6,1,0 %; ! Nonpaged pool - (only low level interfaces) macro BOOSTATE$V_XQP = 0,7,1,0 %; ! The XQP has been mapped macro BOOSTATE$V_RMS = 0,8,1,0 %; ! RMS has been loaded macro BOOSTATE$V_CONSOLE = 0,9,1,0 %; ! Console routines are connected macro BOOSTATE$V_SPNLCK_AVAIL = 0,10,1,0 %; ! Spinlock database available macro BOOSTATE$V_NORDONLY = 0,11,1,0 %; ! If set, EXEC should not be ! made read only. macro BOOSTATE$V_EXEC_SLICING = 0,12,1,0 %; ! If set, execlets should not ! sliced during load. macro BOOSTATE$V_OBJREG = 0,13,1,0 %; ! Security Object Registration enabled macro BOOSTATE$V_AUDITING = 0,14,1,0 %; ! Security auditing subsystem initialized macro BOOSTATE$V_OBJECT_SERVICE = 0,15,1,0 %; ! Security object service initialized macro BOOSTATE$V_FOREIGN_BOOT = 0,16,1,0 %; ! If set, system disk is foreign to VMS macro BOOSTATE$V_LANACP = 0,17,1,0 %; ! If set, LANACP is started macro BOOSTATE$V_SPARE_1 = 0,18,1,0 %; ! was used for QIOserver macro BOOSTATE$V_STACONFIG_IP = 0,19,1,0 %; ! If set, STACONFIG Process is in progress macro BOOSTATE$V_POOL_AVAIL = 0,20,1,0 %; ! Nonpaged pool is fully available macro BOOSTATE$V_SYSMUT_INIT = 0,21,1,0 %; ! (IA64 only) System MUT has been initialized macro BOOSTATE$V_BUGCHECK_INIT = 0,22,1,0 %; ! BUGCHECK has been initialized (can take dumps) literal BOOSTATE$S_BOOSTATEDEF = 4; !*** MODULE $BPTDEF *** ! + ! ! Define bits which control which hardcoded calls to INI$BRK (the initial BPT) ! will be executed as a system is being booted. ! ! - literal BPT$M_INITBEGIN = %X'1'; literal BPT$M_INITEND = %X'2'; literal BPT$M_SMPSTART = %X'4'; literal BPT$M_ANYMODE = %X'8'; literal BPT$M_LDR_INIT = %X'10'; literal BPT$M_PROCDUMP = %X'20'; literal BPT$S_BPTDEF = 4; ! Old size name, synonym literal BPT$S_BPT = 4; macro BPT$V_INITBEGIN = 0,0,1,0 %; ! BRK at start of INIT macro BPT$V_INITEND = 0,1,1,0 %; ! BRK at end of INIT macro BPT$V_SMPSTART = 0,2,1,0 %; ! BRK at INIT call to setup SMP macro BPT$V_ANYMODE = 0,3,1,0 %; ! Trap to XDELTA in any mode macro BPT$V_LDR_INIT = 0,4,1,0 %; ! BRK before calling init routines macro BPT$V_PROCDUMP = 0,5,1,0 %; ! Trap to XDELTA before a process dump ! is written (requires ANYMODE be set too) !*** MODULE $BRKTDEF *** ! ! + ! ! Structure of breakthru message descriptor block. ! ! - literal BRK$M_LOCKED = %X'1'; literal BRK$M_DONE = %X'2'; literal BRK$M_CHKPRIV = %X'4'; literal BRK$M_CHKUIC = %X'8'; literal BRK$C_LENGTH = 146; literal BRK$S_BRKTHRU_1 = 146; ! Old size field (when aggregate had different name) literal BRK$S_BRK = 147; ! ! Common Storage ! macro BRK$L_LOCPSBID = 0,0,32,0 %; ! local PSB ID macro BRK$L_SAVPSBID = 4,0,32,0 %; ! saved PSB ID macro BRK$W_SIZE = 8,0,16,0 %; ! block size macro BRK$W_OUTCNT = 10,0,16,0 %; ! outstanding I/O count macro BRK$T_DEVNAME = 12,0,0,0 %; literal BRK$S_DEVNAME = 16; ! device name for $ASSIGN macro BRK$L_DEVUIC = 28,0,32,0 %; ! UIC of the terminal's owner macro BRK$L_PCB = 32,0,32,1 %; ! Address of PCB macro BRK$L_IOSB = 36,0,32,1 %; ! Address of return IOSB macro BRK$L_ASTADR = 40,0,32,1 %; ! Address of AST routine macro BRK$L_ASTPRM = 44,0,32,0 %; ! Value of AST parameter macro BRK$Q_TIMEOUT = 48,0,0,0 %; literal BRK$S_TIMEOUT = 8; ! Timeout value macro BRK$L_CARCON = 56,0,32,0 %; ! carriage control macro BRK$L_FLAGS = 60,0,32,0 %; ! flags macro BRK$T_SENDNAME = 64,0,0,0 %; literal BRK$S_SENDNAME = 16; ! username/terminal name macro BRK$W_SENDTYPE = 80,0,16,0 %; ! send descriptor type macro BRK$W_SECONDS = 82,0,16,0 %; ! Timeout in seconds macro BRK$L_REQID = 84,0,32,0 %; ! send requestor ID ! ! miscellaneous context ! macro BRK$L_PIDCTX = 88,0,32,0 %; ! Last PID in user search macro BRK$L_UCBCTX = 92,0,32,1 %; ! Last UCB in TTY search macro BRK$L_DDBCTX = 96,0,32,1 %; ! Last DDB in TTY search macro BRK$L_QIOCTX = 100,0,32,1 %; ! per QIO context address macro BRK$W_EFN = 104,0,16,0 %; ! user event flag *BYTE***? macro BRK$B_STS = 106,0,8,0 %; ! status flags macro BRK$V_LOCKED = 106,0,1,0 %; ! I/O dataabse locked macro BRK$V_DONE = 106,1,1,0 %; ! done looking for terminals macro BRK$V_CHKPRIV = 106,2,1,0 %; ! check privilege macro BRK$V_CHKUIC = 106,3,1,0 %; ! check UIC of terminal owner macro BRK$B_PRVMODE = 107,0,8,0 %; ! previous mode macro BRK$L_SCRMSGLEN = 108,0,32,0 %; ! screen message length macro BRK$L_SCRMSG = 112,0,32,0 %; ! screen message address ! ! status block ! macro BRK$W_STATUS = 116,0,16,0 %; ! status macro BRK$W_SUCCESSCNT = 118,0,16,0 %; ! Success count macro BRK$W_TIMEOUTCNT = 120,0,16,0 %; ! Timeout count macro BRK$W_REFUSEDCNT = 122,0,16,0 %; ! Refused count ! ! start of mailbox message ! macro BRK$W_TRMMSG = 124,0,16,0 %; ! mailbox message code macro BRK$W_TRMUNIT = 126,0,16,0 %; ! tty unit number macro BRK$T_TRMNAME = 128,0,0,0 %; literal BRK$S_TRMNAME = 16; ! terminal name ! ! real message starts here ! macro BRK$W_MSGLEN = 144,0,16,0 %; ! length of msgbuf ! ! Length ! macro BRK$T_MSGBUF = 146,0,8,0 %; ! start of message (Do not include in the length. This field ! marks the begining of the variable length buffer. It has a ! real size for C) literal BRK2$S_BRK2 = 16; ! ! Per QIO storage ! macro BRK2$L_COMMON = 0,0,32,1 %; ! address of common area macro BRK2$Q_IOSB = 4,0,0,0 %; literal BRK2$S_IOSB = 8; ! iosb for QIO macro BRK2$W_CHAN = 12,0,16,0 %; ! channel ! subsequent & adjacent BRK2. ! ! Length of Per QIO context ! literal BRK2$C_LENGTH = 16; literal BRKTHRU_2$S_LENGTH = 16; ! Old size field (when aggregate had different name) !*** MODULE $btadpdef *** literal btadp$m_booted_device = %X'1'; literal btadp$m_valid = %X'2'; literal btadp$m_foreign = %X'4'; literal btadp$m_foreign_port = %X'8'; literal btadp$m_no_hardware = %X'10'; literal btadp$m_skip_dump = %X'20'; literal btadp$m_secondary_boot = %X'40'; literal btadp$m_hcdp_device = %X'80'; literal btadp$m_hardware_device = %X'100'; literal btadp$m_memorydisk = %X'200'; literal btadp$m_unit_known = %X'400'; literal btadp$m_sas_device = %X'800'; literal btadp$m_sas_ext_device = %X'1000'; literal btadp$m_ciss_ext_lun = %X'2000'; literal btadp$K_COMPARE_LEN = 324; ! Length of that part of the BTADP to use ! when comparing against the Booted Device literal BTADP$K_IDE_CHAN_PRI = 0; ! Primary Channel literal BTADP$K_IDE_CHAN_SEC = 1; ! Secondary Channel literal BTADP$K_IDE_DRIVE_MASTER = 0; ! Master Drive literal BTADP$K_IDE_DRIVE_SLAVE = 1; ! Slave Driver literal btadp$c_length = 448; ! Length Of Btadp literal btadp$k_length = 448; ! Length Of Btadp ! literal BTADP$K_FLAVOR_ETH_NOPAD = 0; ! Ethernet flavor without pad field literal BTADP$K_FLAVOR_ETH_PAD = 1; ! Ethernet flavor with pad field literal BTADP$K_FLAVOR_802E_NOPAD = 2; ! 802E flavor without pad field literal BTADP$K_FLAVOR_802E_PAD = 3; ! 802E flavor with pad field literal BTADP$K_LAN_TYPE_CSMACD = 1; ! CSMACD data link literal BTADP$K_LAN_TYPE_FDDI = 2; ! FDDI data link literal btadp$S_btadp = 496; macro btadp$pq_flink = 0,0,0,1 %; literal btadp$s_flink = 8; ! BTADP forward link macro btadp$pl_flink_l = 0,0,32,1 %; macro btadp$il_flink_h = 4,0,32,0 %; macro btadp$pq_blink = 8,0,0,1 %; literal btadp$s_blink = 8; ! BTADP backward link macro btadp$pl_blink_l = 8,0,32,1 %; macro btadp$il_blink_h = 12,0,32,0 %; macro btadp$iq_devtype = 16,0,0,0 %; literal btadp$s_devtype = 8; ! Bootstrap Device Type macro btadp$il_devtype_l = 16,0,32,0 %; macro btadp$il_devtype_h = 20,0,32,0 %; macro btadp$iq_unit = 24,0,0,0 %; literal btadp$s_unit = 8; ! Boot Device Unit Number macro btadp$il_unit_l = 24,0,32,0 %; macro btadp$il_unit_h = 28,0,32,0 %; macro btadp$pq_csrphy = 32,0,0,1 %; literal btadp$s_csrphy = 8; ! Phys. Csr Addr. Of Boot Dev macro btadp$pl_csrphy_l = 32,0,32,1 %; macro btadp$il_csrphy_h = 36,0,32,0 %; macro btadp$pq_csrvir = 40,0,0,1 %; literal btadp$s_csrvir = 8; ! Virtual Csr Addr. Of Boot Dev macro btadp$pl_csrvir_l = 40,0,32,1 %; macro btadp$il_csrvir_h = 44,0,32,0 %; macro btadp$pq_adpphy = 48,0,0,1 %; literal btadp$s_adpphy = 8; ! Phys. Csr Addr. Of Boot Adp macro btadp$pl_adpphy_l = 48,0,32,1 %; macro btadp$il_adpphy_h = 52,0,32,0 %; macro btadp$pq_adpvir = 56,0,0,1 %; literal btadp$s_adpvir = 8; ! Virtual Csr Addr. Of Boot Adp macro btadp$pl_adpvir_l = 56,0,32,1 %; macro btadp$il_adpvir_h = 60,0,32,0 %; macro btadp$iq_bootndt = 64,0,0,0 %; literal btadp$s_bootndt = 8; ! Nexus Device Type Of Boot macro btadp$il_bootndt_l = 64,0,32,0 %; macro btadp$il_bootndt_h = 68,0,32,0 %; macro btadp$pq_node_space_addr = 72,0,0,1 %; literal btadp$s_node_space_addr = 8; ! SVA of node space macro btadp$pl_node_space_addr_l = 72,0,32,1 %; macro btadp$il_node_space_addr_h = 76,0,32,0 %; macro btadp$pq_bdtab = 80,0,0,1 %; literal btadp$s_bdtab = 8; ! Pointer to BDTAB macro btadp$pl_bdtab_l = 80,0,32,1 %; macro btadp$il_bdtab_h = 84,0,32,0 %; macro btadp$iq_protocol = 88,0,0,1 %; literal btadp$s_protocol = 8; ! macro btadp$il_protocol_l = 88,0,32,0 %; macro btadp$il_protocol_h = 92,0,32,0 %; macro btadp$iq_hose = 96,0,0,1 %; literal btadp$s_hose = 8; ! macro btadp$il_hose_l = 96,0,32,0 %; macro btadp$il_hose_h = 100,0,32,0 %; macro btadp$iq_slot = 104,0,0,1 %; literal btadp$s_slot = 8; ! XMI/FBUS slot macro btadp$il_slot_l = 104,0,32,0 %; macro btadp$il_slot_h = 108,0,32,0 %; macro btadp$pq_remote_addr = 112,0,0,1 %; literal btadp$s_remote_addr = 8; ! remote addr (eg. XZA) macro btadp$pl_remote_addr_l = 112,0,32,1 %; macro btadp$il_remote_addr_h = 116,0,32,0 %; macro btadp$iq_chan = 120,0,0,1 %; literal btadp$s_chan = 8; ! Channel macro btadp$il_chan_l = 120,0,32,0 %; macro btadp$il_chan_h = 124,0,32,0 %; macro btadp$iq_bus_type = 128,0,0,1 %; literal btadp$s_bus_type = 8; ! Bus type value macro btadp$il_bus_type_l = 128,0,32,0 %; macro btadp$il_bus_type_h = 132,0,32,0 %; macro btadp$iq_dma_map_register = 136,0,0,1 %; literal btadp$s_dma_map_register = 8; ! Base DMA mapping register macro btadp$il_dma_map_register_l = 136,0,32,0 %; macro btadp$il_dma_map_register_h = 140,0,32,0 %; ! ! Define the fields used to control the device name. ! ! ! NOTE: There is code within the boot path that is dependent on the ! order of the fields from MSCP_SLUN through RSRVD. If you ! need to add fields, please do so after the RSRVD field. ! macro btadp$IQ_MSCP_SLUN = 144,0,0,0 %; literal btadp$S_MSCP_SLUN = 8; ! TMSCP/MSCP SLUN for this device. macro btadp$T_DEVICE_NAME = 152,0,0,0 %; literal btadp$S_DEVICE_NAME = 32; ! Counted string. Remote device name. Used for NISCA booting only. macro btadp$T_NODE_NAME = 184,0,0,0 %; literal btadp$S_NODE_NAME = 16; ! Counted string. Remote system's SCS node name. macro btadp$IQ_SCSSYSTEMID = 200,0,0,0 %; literal btadp$S_SCSSYSTEMID = 8; ! Remote system's SCSSYSTEMID value. macro btadp$T_CONTROLLER_PREFIX = 208,0,0,0 %; literal btadp$S_CONTROLLER_PREFIX = 8; ! Counted string. Remote device's controller prefix. macro btadp$B_CONTROLLER_LETTER = 216,0,8,0 %; ! Remote device's controller letter in ASCII. macro btadp$IL_DUMPDEV_ORDER = 220,0,32,0 %; ! The placement of this device in the DUMP_DEV list. ! ie. (first (1), second (2), etc. macro btadp$T_PSEUDO_DEVNAM = 224,0,32,0 %; literal btadp$S_PSEUDO_DEVNAM = 4; ! Counted string. Pseudo driver prefix. Used for MOP devices only. ! This should NOT exceed 1 char for count and 3 for DEVNAM macro btadp$iq_flags = 228,0,0,1 %; literal btadp$s_flags = 8; ! Flags macro btadp$il_flags_l = 228,0,32,0 %; macro btadp$il_flags_h = 232,0,32,0 %; macro btadp$v_booted_device = 228,0,1,0 %; ! is this the boot device macro btadp$v_valid = 228,1,1,0 %; ! BTADP validity macro btadp$v_foreign = 228,2,1,0 %; ! this device is a foreign class macro btadp$v_foreign_port = 228,3,1,0 %; ! this device is a foreign port macro btadp$v_no_hardware = 228,4,1,0 %; ! this device is not associated with hardware macro btadp$v_skip_dump = 228,5,1,0 %; ! the device should not be used for dumping macro btadp$v_secondary_boot = 228,6,1,0 %; ! this device is the secondary boot device macro btadp$v_hcdp_device = 228,7,1,0 %; ! Headless Console Debug Port device macro btadp$v_hardware_device = 228,8,1,0 %; ! Actual hardware device when booting memory disk macro btadp$v_memorydisk = 228,9,1,0 %; ! this device is a memory disk macro btadp$v_unit_known = 228,10,1,0 %; ! BUGCHECK has determined the unit number macro btadp$v_sas_device = 228,11,1,0 %; ! this device is a SAS device macro btadp$v_sas_ext_device = 228,12,1,0 %; ! this device is a SAS external device macro btadp$v_ciss_ext_lun = 228,13,1,0 %; ! CISS external Raid controller LUN macro btadp$IL_ALLOCLASS = 236,0,32,1 %; ! port allocation class for SCSI devices macro btadp$il_dumpdev_skipped = 240,0,32,0 %; ! The number of dump devices which are not valid dump ! devices before we found this device. macro btadp$L_PATHNAME_LEN = 244,0,32,1 %; ! length of console pathname string macro btadp$T_PATHNAME = 248,0,0,0 %; literal btadp$S_PATHNAME = 76; ! console pathname string for this device ! Block within the Select Bootdriver routine. ! Define fibre channel world-wide identifier (WWID) index. ! This is obtained from the console in a BOOT_DEV or BOOTED_DEV ! string in the format: @WWIDn, where n is the WWID index. ! If there is no @WWIDn specifier in the string, then APB ! stores -1 in this field. macro btadp$L_WWID_INDEX = 324,0,32,1 %; ! World-wide identifier index ! Define fibre channel Target ID and LUN. If unavailable from the ! console, then set them to -1. They are both quadword fields but ! are split into _L and _H longwords so that BLISS-32 can handle them. macro btadp$Q_TARGET_ID = 328,0,0,1 %; literal btadp$S_TARGET_ID = 8; ! 24-bit fibre channel destination ID, including AL-PA macro btadp$L_TARGET_ID_L = 328,0,32,1 %; macro btadp$L_TARGET_ID_H = 332,0,32,1 %; macro btadp$Q_LUN = 336,0,0,1 %; literal btadp$S_LUN = 8; ! SCSI Logical Unit Number macro btadp$L_LUN_L = 336,0,32,1 %; macro btadp$L_LUN_H = 340,0,32,1 %; macro btadp$L_HW_CHANNEL = 344,0,32,1 %; ! Channel number assigned to boot device macro btadp$L_HSZ_ALLOCLASS = 348,0,32,1 %; ! Allocation class from HSZ70/80 ! ! QIOSERVER booting ! macro btadp$Q_QSLUN = 352,0,0,0 %; literal btadp$S_QSLUN = 8; ! QIOSERVER QSLUN for remote device macro btadp$L_RTDRIVER_CLASS_LEN = 360,0,32,0 %; ! length of driver name string macro btadp$T_RTDRIVER_CLASS = 364,0,0,0 %; literal btadp$S_RTDRIVER_CLASS = 16; ! length of driver name string ! ! ! Define ATA/ATAPI IDE fields ! macro btadp$L_IDE_CHAN_PRI = 380,0,32,0 %; ! 0:Primary Channel 1: Secondary Channel macro btadp$L_IDE_DRIVE_MASTER = 384,0,32,0 %; ! 0: Master Drive 1: Slave Drive macro btadp$L_IDE_LUN = 388,0,32,0 %; ! ATA Logical Unit Number (Serial ATA) macro btadp$L_IDE_PIO = 392,0,32,0 %; ! PIO mode setting macro btadp$L_IDE_DMA = 396,0,32,0 %; ! DMA mode setting macro btadp$PQ_PORT_CHAN = 400,0,0,1 %; literal btadp$S_PORT_CHAN = 8; ! port boot driver macro btadp$PL_PORT_CHAN_L = 400,0,32,1 %; macro btadp$IL_PORT_CHAN_H = 404,0,32,0 %; ! ! ! Define Fields required for Cell-Based Boot/Crash Driver Support ! macro btadp$iq_hid = 408,0,0,1 %; literal btadp$s_hid = 8; ! ACPI Hardware ID macro btadp$il_hid_l = 408,0,32,0 %; macro btadp$il_hid_h = 412,0,32,0 %; macro btadp$iq_uid = 416,0,0,1 %; literal btadp$s_uid = 8; ! ACPI Unique ID macro btadp$il_uid_l = 416,0,32,0 %; macro btadp$il_uid_h = 420,0,32,0 %; ! ! The TRA_OFFSET identifier is being deprecated in favor of ! the TRA_MMIO identifier, since we need a TRA for Port IO ! space as well. ! macro btadp$iq_tra_mmio = 424,0,0,0 %; literal btadp$s_tra_mmio = 8; ! New Name macro btadp$iq_tra_offset = 424,0,0,0 %; literal btadp$s_tra_offset = 8; ! TRanslation Addreess macro btadp$iq_pci_cfg_data = 432,0,0,1 %; literal btadp$s_pci_cfg_data = 8; macro btadp$pl_pci_cfg_data = 432,0,32,1 %; ! ! This field will contain the TRA for Port IO addresses. ! macro btadp$iq_tra_portio = 440,0,0,0 %; literal btadp$s_tra_portio = 8; ! ! Define the minimum BTADP data structure length. ! ! Define the LAN boot driver fields. ! ! Transmit and receive control variables. ! macro btadp$Q_XMT_TIMEOUT = 448,0,0,0 %; literal btadp$S_XMT_TIMEOUT = 8; ! LAN transmit timeout. macro btadp$G_LAN_HW_ADDR = 456,0,0,0 %; literal btadp$S_LAN_HW_ADDR = 6; ! LAN hardware address. macro btadp$B_LAN_DEV_TYPE = 462,0,8,0 %; ! LAN adapter type (from DYN symbols). macro btadp$Q_PROTOCOL_TYPE = 464,0,0,0 %; literal btadp$S_PROTOCOL_TYPE = 8; ! Protocol type value. macro btadp$L_PROTOCOL_FLAVOR = 472,0,32,0 %; ! (0=Eth/NoPad,1=Eth/Pad,2=802E/NoPad,3=802E/Pad) macro btadp$L_LAN_HDR_SIZE = 476,0,32,0 %; ! LAN header size. macro btadp$L_MAX_XMT_SIZE = 480,0,32,0 %; ! Maximum datagram size. macro btadp$L_MIN_XMT_SIZE = 484,0,32,0 %; ! Minimum datagram size. ! ! Define the LAN type. ! macro btadp$L_LAN_TYPE = 488,0,32,0 %; ! Type of LAN. ! ! Define the minimum BTADP data structure length required for LAN devices. ! literal BTADP$S_BTADPDEF = 496; literal BTADP$K_LAN_LENGTH = 496; literal BTADP$C_LAN_LENGTH = 496; !*** MODULE $BTBDEF *** literal BTB$K_VAX_SECTOR = 0; ! address of VAX bootblock LBN literal BTB$K_ALPHA_SECTOR = 0; ! address of Alpha bootblock LBN literal BTB$K_LENGTH_PART1 = 480; ! Length of 1st part of boot block literal BTB$M_NOTCONTIG = %X'1'; literal BTB$K_LENGTH = 512; ! Length of a boot block literal BTB$S_BTBDEF = 512; ! Old size name, synonym literal BTB$S_BTB = 512; macro BTB$B_NOP1 = 0,0,8,0 %; ! Contains NOP opcode macro BTB$B_BRB = 1,0,8,0 %; ! Contains BRB opcode macro BTB$B_BRB_OFFSET = 2,0,8,0 %; ! Contains PC relative offset of branch macro BTB$B_NOP2 = 3,0,8,0 %; ! Contains NOP opcode macro BTB$L_LBN1 = 4,0,32,1 %; ! Starting LBN of 1st boot file macro BTB$W_HIGH_LBN = 4,0,16,0 %; ! High 32-bits of LBN macro BTB$W_LOW_LBN = 6,0,16,0 %; ! Low 32-bits of LBN macro BTB$B_VAX_BRB = 12,0,8,0 %; ! Contains BRB opcode (VAX) macro BTB$B_VAX_OFFSET = 13,0,8,0 %; ! Contains PC relative offset of branch macro BTB$B_PDP_BRB = 15,0,8,0 %; ! Contain BRB opcode (PDP) macro BTB$B_PDP_OFFSET = 16,0,8,0 %; ! Contains PC relative offset of branch macro BTB$B_INST_SET = 24,0,8,0 %; ! Instruction set code (%x18=VAX) macro BTB$B_CTRL_TYPE = 25,0,8,0 %; ! Controller type macro BTB$B_FILE_STR = 26,0,8,0 %; ! File structure (ODS-II =2) macro BTB$B_COMP3 = 27,0,8,0 %; ! Complement of sum of previous 3 bytes macro BTB$B_VERSION = 29,0,8,0 %; ! Boot block version=1 macro BTB$L_SIZE = 32,0,32,0 %; ! Size in LBNs of image macro BTB$L_LOAD_OFFSET = 36,0,32,0 %; ! Load offset into good memory macro BTB$L_START_OFFSET = 40,0,32,0 %; ! Offset to begin execution macro BTB$L_CHECKSUM = 44,0,32,0 %; ! Checksum of three previous longwords macro BTB$B_VAX_CODE = 48,0,0,1 %; literal BTB$S_VAX_CODE = 92; ! VAX boot block code macro BTB$L_STUFF = 48,0,32,1 %; ! macro BTB$L_MORE_STUFF = 52,0,32,1 %; ! macro BTB$T_COMMENT = 56,0,0,0 %; literal BTB$S_COMMENT = 20; ! macro BTB$B_FILL8 = 140,0,0,1 %; literal BTB$S_FILL8 = 340; ! Reserved for future use macro BTB$Q_SIZE2 = 480,0,0,1 %; literal BTB$S_SIZE2 = 8; ! Size of 2nd boot file macro BTB$L_LOW_SIZE2 = 480,0,32,1 %; ! Low 32-bits of size macro BTB$L_HIGH_SIZE2 = 484,0,32,1 %; ! High 32-bits of size macro BTB$Q_LBN2 = 488,0,0,1 %; literal BTB$S_LBN2 = 8; ! Starting LBN of 2nd boot file macro BTB$L_LOW_LBN2 = 488,0,32,1 %; ! Low 32-bits of LBN macro BTB$L_HIGH_LBN2 = 492,0,32,1 %; ! High 32-bits of LBN macro BTB$Q_FLAGS = 496,0,0,0 %; literal BTB$S_FLAGS = 8; ! Boot block flags macro BTB$L_LOW_FLAGS = 496,0,32,0 %; ! Low longword of flags macro BTB$L_HIGH_FLAGS = 500,0,32,0 %; ! High longword of flags macro BTB$V_NOTCONTIG = 496,0,1,0 %; ! Bootstrap is not contiguous macro BTB$Q_CHECKSUM2 = 504,0,0,1 %; literal BTB$S_CHECKSUM2 = 8; ! Checksum of entire block macro BTB$L_LOW_CHECK2 = 504,0,32,1 %; ! Low 32-bits of checksum macro BTB$L_HIGH_CHECK2 = 508,0,32,1 %; ! High 32-bits of checksum !*** MODULE $BTDDEF *** ! + ! ! Boot device codes ! ! - ! "$K_" added, 8/30/79, CHP literal BTD$K_MB = 0; ! Massbus device ! Types 1-31. reserved for ! Unibus(Qbus) devices literal BTD$K_DM = 1; ! RK06/7 literal BTD$K_DL = 2; ! RL02 literal BTD$K_DQ = 3; ! RB02/RB80 literal BTD$K_PROM = 8; ! PROM (not copied) literal BTD$K_PROM_COPY = 9; ! PROM copied (Mayflower) literal BTD$K_UDA = 17; ! UDA literal BTD$K_TK50 = 18; ! TK50 (MAYA) literal BTD$K_KFQSA = 19; ! KFQSA literal BTD$K_QBUS_SCSI = 20; ! Qbus SCSI adapter ! End of Unibus(Qbus) devices literal BTD$K_HSCCI = 32; ! HSC on CI literal BTD$K_BDA = 33; ! BI disk adapter literal BTD$K_BVPSSP = 34; ! BVP Storage Systems ports literal BTD$K_AIE_TK50 = 35; ! AIE/TK50 port literal BTD$k_ST506_DISK = 36; ! ST506 disk (PVAX/VAXstar) literal BTD$K_KA410_DISK = 36; ! VAXstar ST506 disk literal BTD$K_KA420_DISK = 36; ! PVAX ST506 disk literal BTD$K_SCSI_5380_TAPE = 37; ! NCR 5380 SCSI tape (PVAX/VAXstar) literal BTD$K_KA410_TAPE = 37; ! VAXstar SCSI tape literal BTD$K_KA420_TAPE = 37; ! PVAX SCSI tape literal BTD$K_DISK9 = 38; ! Disk on 009 literal BTD$K_SII = 39; ! Embedded DSSI controller literal BTD$K_SHAC = 41; ! Single chip DSSI adapter. literal BTD$K_SCSI_5380_DISK = 42; ! NCR 5380 SCSI disk (PVAX) literal BTD$K_HSX = 43; literal BTD$K_KDM70 = 43; literal BTD$K_HSXTAPE = 44; literal BTD$K_KDM70TAPE = 44; literal BTD$K_SWIFT = 45; ! Another embedded DSSI controller-CIRRUS literal BTD$K_SCSI_53C94_DISK = 46; literal BTD$K_SCSI_53C94_TAPE = 47; literal BTD$K_CONSOLE = 64; ! Console block storage device ! Network boot devices (96-103) literal BTD$K_NET_DLL = 96; ! Start of network boot devices ! Codes 96-127 reserved literal BTD$K_QNA = 96; ! DEQNA literal BTD$K_UNA = 97; ! DEUNA literal BTD$K_AIE_NI = 98; ! AIE/NI literal BTD$K_LANCE = 99; ! LANCE NI chip literal BTD$K_KA410_NI = 99; ! VAXstar NI (LANCE chip) literal BTD$K_KA420_NI = 99; ! PVAX NI (LANCE chip) literal BTD$K_SGEC = 100; ! SGEC chip literal BTD$K_SERVER_DEBNA = 101; ! NI-CDROM server literal BTD$K_SERVER_DEBNI = 102; ! NI-CDROM server literal BTD$K_SERVER_XNA = 103; ! NI-CDROM server literal BTD$K_DEBNI = 104; ! DEBNI literal BTD$K_DEMNA = 105; ! DEMNA literal BTD$K_KA520_NI = 106; ! CIRRUS NI literal BTD$K_SERVER_QNA = 107; ! NI-CDROM server literal BTD$K_SERVER_AIE_NI = 108; ! NI-CDROM server literal BTD$K_SERVER_LANCE = 109; ! NI-CDROM server literal BTD$K_SERVER_SGEC = 110; ! NI-CDROM server literal BTD$K_SERVER_KA520_NI = 111; ! NI-CDROM server literal BTD$K_DEMFA = 112; ! DEMFA literal BTD$K_SERVER_DEMFA = 113; ! NI-CDROM server literal BTD$K_DEFZA = 114; ! DEFZA literal BTD$K_SERVER_DEFZA = 115; ! NI-CDROM server literal BTD$K_PMAD = 116; ! PMAD literal BTD$K_SERVER_PMAD = 117; ! NI-CDROM server literal BDT$K_TGEC = 118; ! TGEC ethernet chip literal BTD$K_SERVER_TGEC = 119; ! NI-CDROM server literal BDT$K_DEANA = 120; ! Futurebus to Ethernet literal BTD$K_SERVER_DEANA = 121; ! NI-CDROM server literal BTD$K_NETWORK_BOOT = 128; ! Generic boot over NI literal BTD$K_NISCS = 128; ! SCS disk over NI !*** MODULE $BUSDEF *** ! ! Bus Type definitions. ! ! DEFINE Bus Types -- used in BUSARRAY$L_BUS_TYPE and ! CMDTABLE$L_BUS_TYPE ! ! DEFINE BUS TYPES ! literal BUS$_FBUS = 1; literal BUS$_XMI = 2; literal BUS$_LBUS = 3; literal BUS$_TURBO = 4; literal BUS$_CBUS = 5; literal BUS$_LSB = 6; literal BUS$_NI = 7; literal BUS$_CI = 8; literal BUS$_FDDI = 9; literal BUS$_SCSI = 10; literal BUS$_DSSI = 11; literal BUS$_KDM70 = 12; literal BUS$_GENXMI = 13; literal BUS$_BUSLESS_SYSTEM = 14; literal BUS$_COREIO = 15; literal BUS$_EISA = 16; literal BUS$_VTI_COMBO = 17; literal BUS$_VME = 18; literal BUS$_PCI = 19; literal BUS$_ISA = 20; literal BUS$_XBUS = 21; literal BUS$_THIRDPARTY0 = 22; literal BUS$_THIRDPARTY1 = 23; literal BUS$_THIRDPARTY2 = 24; literal BUS$_THIRDPARTY3 = 25; literal BUS$_THIRDPARTY4 = 26; literal BUS$_THIRDPARTY5 = 27; literal BUS$_THIRDPARTY6 = 28; literal BUS$_THIRDPARTY7 = 29; literal BUS$_TLSB = 30; literal BUS$_TIOP = 31; literal BUS$_ITIOP = 32; literal BUS$_PCMCIA = 33; literal BUS$_GLOBAL_BUS = 34; literal BUS$_MC_BUS = 35; literal BUS$_WF_BUS = 36; literal BUS$_IA64_BUS = 37; literal BUS$_NULL = 38; literal BUS$_PCIE = 39; !*** MODULE $BUFIODEF *** ! + ! BUFIO - Buffered I/O Packet Header ! ! There are two alternative formats for the packet header of a simple ! buffered I/O packet. The first is the "traditional" 12 byte header ! (symbolic constant BUFIO$K_HDRLEN32) that contains room for a 32-bit ! user buffer address. The second alternative format, with size ! BUFIO$K_HDRLEN64, that contains room for a 64-bit user buffer address. ! ! These two types of simple buffered I/O packets are "self identifying." ! That is, it is possible to distinguish a 32-bit from a 64-bit format ! packet from the 32-bit user buffer address cell. A -1 value (symbolic ! constant BUFIO$K_64) in this cell indicates that this is a 64-bit buffered ! I/O packet and that the user buffer address is in the BUFIO$PQ_UVA64 cell. ! This is very similar to the method used to identify a 64-bit descriptor. ! - literal BUFIO$K_64 = -1; ! BUFIO$K_64, see BUFIO$PQ_UVA64 literal BUFIO$K_HDRLEN32 = 12; ! Size of 32-bit BUFIO packet header literal BUFIO$K_HDRLEN64 = 24; ! Size of 64-bit BUFIO packet header literal BUFIO$S_BUFIO = 24; macro BUFIO$PS_PKTDATA = 0,0,32,1 %; ! Pointer to the buffered data within the packet macro BUFIO$PS_UVA32 = 4,0,32,1 %; ! 32-bit pointer to user's buffer, or BUFIO$K_64 (-1) macro BUFIO$W_SIZE = 8,0,16,0 %; ! Total packet size macro BUFIO$B_TYPE = 10,0,8,0 %; ! Structure type, DYN$C_BUFIO macro BUFIO$PQ_UVA64 = 16,0,0,1 %; literal BUFIO$S_UVA64 = 8; ! 64-bit pointer to user's buffer ! Valid if and only if BUFIO$PS_UVA32 contains ! the value BUFIO$K_64 (-1). !*** MODULE $BUGLOGDEF *** ! + ! BUGLOG - BUGcheck LOG buffer ! ! A BUGLOG buffer is a per-CPU data area that may contain ! additional information for use in analyzing a crash dump. ! - literal BUGLOG$M_DATA_PRESENT = %X'1'; literal BUGLOG$S_BUGLOG = 256; macro BUGLOG$Q_TIMESTAMP = 0,0,0,1 %; literal BUGLOG$S_TIMESTAMP = 8; ! System time when SYS$GET_BUGLOG was called to reserve this structure macro BUGLOG$W_SIZE = 8,0,16,0 %; ! Size of entire BUGLOG structure in bytes macro BUGLOG$B_TYPE = 10,0,8,0 %; ! Structure type (DYN$C_MISC) macro BUGLOG$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype (DYN$C_BUGLOG) macro BUGLOG$W_FLAGS = 12,0,16,0 %; ! BUGLOG flags macro BUGLOG$V_DATA_PRESENT = 12,0,1,0 %; ! Buffer has been reserved for use, data should be present macro BUGLOG$W_DATA_LEN = 14,0,16,0 %; ! Number of bytes starting at DATASTART that caller may use macro BUGLOG$Q_CALLER_PC = 16,0,0,0 %; literal BUGLOG$S_CALLER_PC = 8; ! Caller's return address macro BUGLOG$Q_SAVED_R0 = 24,0,0,0 %; literal BUGLOG$S_SAVED_R0 = 8; ! Caller's R0 macro BUGLOG$Q_SAVED_R1 = 32,0,0,0 %; literal BUGLOG$S_SAVED_R1 = 8; ! Caller's R1 macro BUGLOG$Q_RESERVED = 40,0,0,0 %; literal BUGLOG$S_RESERVED = 8; ! Reserved macro BUGLOG$Q_QW01 = 48,0,0,1 %; literal BUGLOG$S_QW01 = 8; ! User data area as quadwords macro BUGLOG$Q_QW02 = 56,0,0,1 %; literal BUGLOG$S_QW02 = 8; macro BUGLOG$Q_QW03 = 64,0,0,1 %; literal BUGLOG$S_QW03 = 8; macro BUGLOG$Q_QW04 = 72,0,0,1 %; literal BUGLOG$S_QW04 = 8; macro BUGLOG$Q_QW05 = 80,0,0,1 %; literal BUGLOG$S_QW05 = 8; macro BUGLOG$Q_QW06 = 88,0,0,1 %; literal BUGLOG$S_QW06 = 8; macro BUGLOG$Q_QW07 = 96,0,0,1 %; literal BUGLOG$S_QW07 = 8; macro BUGLOG$Q_QW08 = 104,0,0,1 %; literal BUGLOG$S_QW08 = 8; macro BUGLOG$Q_QW09 = 112,0,0,1 %; literal BUGLOG$S_QW09 = 8; macro BUGLOG$Q_QW10 = 120,0,0,1 %; literal BUGLOG$S_QW10 = 8; macro BUGLOG$Q_QW11 = 128,0,0,1 %; literal BUGLOG$S_QW11 = 8; macro BUGLOG$Q_QW12 = 136,0,0,1 %; literal BUGLOG$S_QW12 = 8; macro BUGLOG$Q_QW13 = 144,0,0,1 %; literal BUGLOG$S_QW13 = 8; macro BUGLOG$Q_QW14 = 152,0,0,1 %; literal BUGLOG$S_QW14 = 8; macro BUGLOG$Q_QW15 = 160,0,0,1 %; literal BUGLOG$S_QW15 = 8; macro BUGLOG$Q_QW16 = 168,0,0,1 %; literal BUGLOG$S_QW16 = 8; macro BUGLOG$Q_QW17 = 176,0,0,1 %; literal BUGLOG$S_QW17 = 8; macro BUGLOG$Q_QW18 = 184,0,0,1 %; literal BUGLOG$S_QW18 = 8; macro BUGLOG$Q_QW19 = 192,0,0,1 %; literal BUGLOG$S_QW19 = 8; macro BUGLOG$Q_QW20 = 200,0,0,1 %; literal BUGLOG$S_QW20 = 8; macro BUGLOG$Q_QW21 = 208,0,0,1 %; literal BUGLOG$S_QW21 = 8; macro BUGLOG$Q_QW22 = 216,0,0,1 %; literal BUGLOG$S_QW22 = 8; macro BUGLOG$Q_QW23 = 224,0,0,1 %; literal BUGLOG$S_QW23 = 8; macro BUGLOG$Q_QW24 = 232,0,0,1 %; literal BUGLOG$S_QW24 = 8; macro BUGLOG$Q_QW25 = 240,0,0,1 %; literal BUGLOG$S_QW25 = 8; macro BUGLOG$Q_QW26 = 248,0,0,1 %; literal BUGLOG$S_QW26 = 8; macro BUGLOG$T_DATASTART = 48,0,0,1 %; literal BUGLOG$S_DATASTART = 208; ! User data area as byte block literal BUGLOG$K_LENGTH = 256; ! Standard length of BUGLOG structure literal BUGLOG$C_LENGTH = 256; ! Ditto literal BUGLOG$S_BUGLOGDEF = 256; ! Another size name synonym !*** MODULE $C2DEF *** ! + ! C2 - C2 Subset Definitions ! ! This structures maps the bits in the SECURITY_POLICY SYSGEN parameter that ! are used to enable or remove features that have not been formally evaluated ! by the NCSC under our C2/B1 VMS/SEVMS evaluation. ! ! - literal C2$M_ALLOW_DISPLAY_POSTSCRIPT = %X'1'; literal C2$M_ALLOW_MULTIPLE_DECW_USERS = %X'2'; literal C2$M_ALLOW_ALTERNATE_TRANSPORTS = %X'4'; literal C2$M_ALLOW_SPAN_JOB_TREES = %X'8'; literal C2$M_LOCAL_UPDATE = %X'10'; literal C2$M_LOCAL_PROFILE = %X'20'; literal C2$M_ALLOW_CAPTIVE_SPAWN = %X'40'; literal C2$M_COMPRESS_MAC_STRINGS = %X'80'; literal C2$M_UPPERCASE_INPUT = %X'100'; literal C2$M_GUARD_PASSWORDS = %X'200'; literal C2$M_DOI_AUTHORIZATION_ONLY = %X'400'; literal C2$M_IGNORE_EXTAUTH = %X'800'; literal C2$M_INTRUSIONS_ARE_LOCAL = %X'1000'; literal C2$M_USE_POSIX_UIDGID = %X'2000'; literal C2$M_ALLOW_SYMLINK_ACCESS = %X'4000'; literal C2$S_SECPOLDEF = 4; literal C2$S_SECPOL = 4; macro C2$L_SECURITY_POLICY = 0,0,32,0 %; macro C2$V_ALLOW_DISPLAY_POSTSCRIPT = 0,0,1,0 %; ! allow display postscript extensions macro C2$V_ALLOW_MULTIPLE_DECW_USERS = 0,1,1,0 %; ! allow multiple username to connect to DECW$SERVER macro C2$V_ALLOW_ALTERNATE_TRANSPORTS = 0,2,1,0 %; ! allow unevaluated transports macro C2$V_ALLOW_SPAN_JOB_TREES = 0,3,1,0 %; ! allow $SIGPRC to span job trees ! The following bits control profile management for cluster object ! when the object server is unavailable. Setting these bits will ! allow these objects to have inconsistent profiles within a security ! domain (cluster). macro C2$V_LOCAL_UPDATE = 0,4,1,0 %; ! allow local profile changes macro C2$V_LOCAL_PROFILE = 0,5,1,0 %; ! allow local object creation macro C2$V_ALLOW_CAPTIVE_SPAWN = 0,6,1,0 %; ! allow SPAWN or LIB$SPAWN in CAPTIVE accounts macro C2$V_COMPRESS_MAC_STRINGS = 0,7,1,0 %; ! compress MAC category strings (SEVMS) macro C2$V_UPPERCASE_INPUT = 0,8,1,0 %; ! as prior to VMS V7.1 macro C2$V_GUARD_PASSWORDS = 0,9,1,0 %; ! ACMEs shall not share macro C2$V_DOI_AUTHORIZATION_ONLY = 0,10,1,0 %; ! prevent feature mixing macro C2$V_IGNORE_EXTAUTH = 0,11,1,0 %; ! ignore user-specific EXTAUTH and VMSAUTH restrictions macro C2$V_INTRUSIONS_ARE_LOCAL = 0,12,1,0 %; ! consider local intrusions only when set macro C2$V_USE_POSIX_UIDGID = 0,13,1,0 %; ! perform UID/GID lookup in tcpip proxy database macro C2$V_ALLOW_SYMLINK_ACCESS = 0,14,1,0 %; ! execute access permits read-attributes on FN and/or backlink !*** MODULE $CADEF *** ! + ! CONDITIONAL ASSEMBLY PARAMETER DEFINITIONS ! ! A NONZERO PARAMETER VALUE INDICATES PRESENCE OF THE FEATURE. ! A ZERO PARAMETER VALUE INDICATES ABSENCE OF THE FEATURE ! ! ALL PARAMETERS MUST BE DEFINED ! - literal CA$_SIMULATOR = 1; ! INCLUDE SIMULATOR SUPPORT CODE literal CA$_MEASURE = 2; ! INCLUDE PERFORMANCE MEASUREMENT HOOKS literal CA$_MEASURE_IOT = 4; ! INCLUDE I/O TRANSACTION DATA COLLECTION literal CA$_LNM_MEASURE = 0; ! Exclude new logical name counters !*** MODULE $CALDEF *** ! ! CAL - Calibration information ! literal CAL$K_LENGTH = 96; ! Structure size literal CAL$C_LENGTH = 96; ! Structure size literal CAL$S_CAL = 96; macro CAL$Q_LAST_CALIBRATION = 0,0,0,0 %; literal CAL$S_LAST_CALIBRATION = 8; ! timestamp of last calibration macro CAL$W_MBO = 8,0,16,0 %; ! must-be-one field macro CAL$B_TYPE = 10,0,8,0 %; ! Structure type (DYN$C_CAL) macro CAL$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro CAL$L_FLAGS = 12,0,32,0 %; ! flags macro CAL$V_IP = 12,0,1,0 %; ! calibration in-progress macro CAL$Q_SIZE = 16,0,0,1 %; literal CAL$S_SIZE = 8; ! total size in bytes macro CAL$L_MAX_CPUS = 24,0,32,0 %; ! maximum number of CPUs macro CAL$L_PAGES = 28,0,32,0 %; ! total size in pages macro CAL$L_SPINLOCK = 32,0,32,1 %; ! pointer to dynamic spinlock structure macro CAL$Q_COUNT = 40,0,0,0 %; literal CAL$S_COUNT = 8; ! count number of calibrations macro CAL$Q_DIVISOR = 48,0,0,0 %; literal CAL$S_DIVISOR = 8; ! divisor for timestamp conversion macro CAL$Q_SCC_REF = 56,0,0,1 %; literal CAL$S_SCC_REF = 8; ! pointer to array of cache lines macro CAL$Q_SCC = 64,0,0,1 %; literal CAL$S_SCC = 8; ! pointer to array of cycle counts per possible CPU macro CAL$Q_SYSTIME = 72,0,0,1 %; literal CAL$S_SYSTIME = 8; ! pointer to array of systime info per possible CPU macro CAL$Q_RESERVED1 = 80,0,0,0 %; literal CAL$S_RESERVED1 = 8; macro CAL$Q_RESERVED2 = 88,0,0,0 %; literal CAL$S_RESERVED2 = 8; !*** MODULE $CANDEF *** ! + ! CAN - DEFINE DRIVER CANCEL ROUTINE REASON CODES ! ! THESE CODES ARE PASSED TO THE CANCEL ROUTINE OF A DRIVER SO THAT ! THE ROUTINE CAN DISTINGUISH BETWEEN CALLS FROM $DASSGN AND $CANCEL. ! ! - literal CAN$C_CANCEL = 0; ! CANCEL INVOKED DUE TO $CANCEL SERVICE literal CAN$C_DASSGN = 1; ! CANCEL INVOKED DUE TO $DASSGN SERVICE literal CAN$C_AMBXDGN = 2; ! CANCEL INVOKED DUE TO MB DISASSOCIATION literal CAN$C_MSCPSERVER = 3; ! CANCEL INVOKED BY MSCP SERVER DUE TO ! CONNECTION LOSS TO CLIENT NODE !*** MODULE $CBBDEF *** literal CBB$M_OVERRIDE_LOCK = 1; literal CBB$M_ZERO = 2; literal CBB$M_DUPLICATE_COPY = 4; ! + ! ! Common bitmask block definition. The purpose of this data structure ! is to represent a variable, potentially unlimited number of CPUs in ! bitmask format. The CBB is intended to be a generic construct as well; ! flexible enough for other applications that require bitmask support. ! - literal CBB$M_LOCK_BIT = %X'1'; literal CBB$M_AUTO_LOCK = %X'2'; literal CBB$M_TIMEOUT_CRASH = %X'4'; literal CBB$M_SUMMARY_BITS = %X'8'; literal CBB$M_SET_COUNT = %X'10'; literal CBB$S_CBB = 48; macro CBB$L_DATA_OFFSET = 0,0,32,0 %; ! Offset to start of bit data macro CBB$W_UNIT_COUNT = 4,0,16,0 %; ! Valid data units within block macro CBB$B_UNIT_SIZE = 6,0,8,0 %; ! Size of data units in bytes macro CBB$B_LOCK_IPL = 7,0,8,0 %; ! Synchronization IPL for CBB macro CBB$W_SIZE = 8,0,16,0 %; ! Structure size macro CBB$B_TYPE = 10,0,8,0 %; ! Structure type macro CBB$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro CBB$L_BIT_COUNT = 12,0,32,0 %; ! Number of data bits set in block macro CBB$Q_INTERLOCK = 16,0,0,0 %; literal CBB$S_INTERLOCK = 8; ! Alias for locking macro CBB$Q_STATE = 16,0,0,0 %; literal CBB$S_STATE = 8; ! State bitmask macro CBB$V_LOCK_BIT = 16,0,1,0 %; ! Atomic locking bit macro CBB$V_AUTO_LOCK = 16,1,1,0 %; ! Automatic locking state macro CBB$V_TIMEOUT_CRASH = 16,2,1,0 %; ! Crash if timeout exceeded macro CBB$V_SUMMARY_BITS = 16,3,1,0 %; ! Summary masks to be updated macro CBB$V_SET_COUNT = 16,4,1,0 %; ! Count of bits set kept macro CBB$L_TIMEOUT_COUNT = 24,0,32,0 %; ! Timeout interval in 10usec macro CBB$L_SAVED_IPL = 28,0,32,0 %; ! Caller's IPL upon entrance to ! Exe$cbb_lock macro CBB$L_VALID_BITS = 32,0,32,0 %; ! # of bits (specified by the user ! on input to allocate, get_size, and ! initialize) represented by this Cbb ! ! All new fields must be added before the SUMMARY_BITMASK field. The SUMMARY_BITMASK ! field below may be the 1st summary bitmask field of many. ! macro CBB$Q_SUMMARY_BITMASK = 40,0,0,0 %; literal CBB$S_SUMMARY_BITMASK = 8; ! Summary bitmask of 64 unit bitmasks literal CBB$K_LENGTH = 48; ! Length of CBB literal CBB$C_LENGTH = 48; ! Length of CBB ! Function code values for the function input parameter to the routine, ! Exe$cbb_boolean_oper. ! literal CBB$C_OR = 0; ! Logical Sum literal CBB$C_AND = 1; ! Logical Product literal CBB$C_XOR = 2; ! Logical Difference literal CBB$C_BIC = 3; ! Logical Product with Complement literal CBB$C_ORNOT = 4; ! Logical Sum with Complement literal CBB$C_EQV = 5; ! Logical Equivalence (XORNOT) literal CBB$C_COMP = 6; ! Logical ones complement of source literal CBB$C_MAX_FUNCTION = 6; literal CBB$K_STATIC_CPU_COUNT = 1024; literal cbb$K_static_block = 176; !*** MODULE $CINDEF *** ! + ! ! Connect to interrupt definitions for QIO parameters ! ! - literal CIN$M_EFN = %X'1'; literal CIN$M_USECAL = %X'2'; literal CIN$M_REPEAT = %X'4'; literal CIN$M_AST = %X'8'; literal CIN$M_INIDEV = %X'10'; literal CIN$M_START = %X'20'; literal CIN$M_ISR = %X'40'; literal CIN$M_CANCEL = %X'80'; literal CIN$M_EFNUM = %X'FFFF0000'; literal CIN$S_CINDEF = 4; literal CIN$S_CIN = 4; macro CIN$V_EFN = 0,0,1,0 %; ! Set event flag on interrupt. macro CIN$V_USECAL = 0,1,1,0 %; ! Use CALL interface. macro CIN$V_REPEAT = 0,2,1,0 %; ! Do repeated interrupt service. macro CIN$V_AST = 0,3,1,0 %; ! Queue AST on interrupt. macro CIN$V_INIDEV = 0,4,1,0 %; ! Device initialization to do. macro CIN$V_START = 0,5,1,0 %; ! Start I/O routine. macro CIN$V_ISR = 0,6,1,0 %; ! ISR to execute. macro CIN$V_CANCEL = 0,7,1,0 %; ! Cancel I/O routine. macro CIN$V_EFNUM = 0,16,16,0 %; literal CIN$S_EFNUM = 16; ! Event flag number. literal CIN$S_CINDEF1 = 16; literal CIN$S_CIN1 = 16; macro CIN$L_INIDEV = 0,0,32,0 %; ! Offset to device init routine. macro CIN$L_START = 4,0,32,0 %; ! Offset to start device routine. macro CIN$L_ISR = 8,0,32,0 %; ! Offset to interrupt service routine. macro CIN$L_CANCEL = 12,0,32,0 %; ! Offset to cancel I/O routine. literal CIN$S_CINDEF2 = 8; literal CIN$S_CIN2 = 8; macro CIN$L_SPTCOUNT = 0,0,32,0 %; ! Number of SPTs allocated. macro CIN$L_STARTVPN = 4,0,32,0 %; ! Starting VPN allocated. macro CIN$L_STARTBIT = 4,0,32,0 %; ! Starting bit in bitmap. !*** MODULE $CCBDEF *** ! + ! CCB - CHANNEL CONTROL BLOCK ! ! THERE IS ONE CHANNEL CONTROL BLOCK FOR EACH SOFTWARE CHANNEL THAT A ! PROCESS MAY INITIATE I/O REQUESTS ON. THE NUMBER OF SUCH I/O CHANNELS ! IS DETERMINED BY THE FIXED NUMBER ASSIGNED TO A PROCESS PLUS ANY ! ADDITIONAL CHANNELS REQUIRED BY THE IMAGE CURRENTLY BEING EXECUTED ! BY THE PROCESS. ! ! - literal CCB$M_AMB = %X'1'; literal CCB$M_IMGTMP = %X'2'; literal CCB$M_RDCHKDON = %X'4'; literal CCB$M_WRTCHKDON = %X'8'; literal CCB$M_LOGCHKDON = %X'10'; literal CCB$M_PHYCHKDON = %X'20'; literal CCB$M_NOREADACC = %X'40'; literal CCB$M_NOWRITEACC = %X'80'; literal CCB$M_CLONE = %X'100'; literal CCB$S_CCB = 32; macro CCB$L_UCB = 0,0,32,1 %; ! ADDRESS OF ASSIGNED DEVICE UCB macro CCB$L_STS = 4,0,32,0 %; ! CHANNEL STATUS macro CCB$V_AMB = 4,0,1,0 %; ! MAILBOX ASSOCIATED WITH CHANNEL macro CCB$V_IMGTMP = 4,1,1,0 %; ! IMAGE TEMPORARY macro CCB$V_RDCHKDON = 4,2,1,0 %; ! READ PROTECTION CHECK COMPLETED macro CCB$V_WRTCHKDON = 4,3,1,0 %; ! WRITE PROTECTION CHECK COMPLETED macro CCB$V_LOGCHKDON = 4,4,1,0 %; ! LOGICAL I/O ACCESS CHECK DONE macro CCB$V_PHYCHKDON = 4,5,1,0 %; ! PHYSICAL I/O ACCESS CHECK DONE macro CCB$V_NOREADACC = 4,6,1,0 %; ! READ ACCESS TO DEVICE DISABLED macro CCB$V_NOWRITEACC = 4,7,1,0 %; ! WRITE ACCESS TO DEVICE DISABLED macro CCB$V_CLONE = 4,8,1,0 %; ! Clone channel after Posix fork() macro CCB$L_IOC = 8,0,32,0 %; ! Number of outstanding I/O requests on channel macro CCB$L_DIRP = 12,0,32,1 %; ! DEACCESS I/O REQUEST PACKET ADDRESS macro CCB$B_AMOD = 16,0,8,1 %; ! ACCESS MODE THAT ASSIGNED CHANNEL macro CCB$L_WIND = 20,0,32,1 %; ! Address of Window Control Block macro CCB$L_CHAN = 24,0,32,1 %; ! associated channel number macro CCB$W_CHAN = 24,0,16,0 %; literal CCB$K_LENGTH = 32; ! LENGTH OF CCB literal CCB$S_CCBDEF = 32; ! OLD SIZE NAME, SYNONYM FOR CCB$S_CCB !*** MODULE $CCDDEF *** literal CCD$M_NOVALIDATE = %X'1'; literal CCD$M_NOEVENT = %X'2'; literal CCD$M_NORESET = %X'4'; literal CCD$M_SETTODEF = %X'8'; literal CCD$M_SETTOCUR = %X'10'; literal CCD$S_CODE_NOW = 8; ! current size of code field literal CCD$K_MAINT = 1; ! CHARGE record literal CCD$K_CHARGE = 8; ! CHARGE record literal CCD$K_DEFAULT = 16; ! DEFAULT record literal CCD$K_GRANT = 24; ! GRANT record literal CCD$S_USER_NOW = 12; ! current size of user field literal CCD$S_DEFAULT = 68; ! size of DEFAULT record literal CCD$S_GRANT = 68; ! size of GRANT record literal CCD$M_DISABLE = %X'1'; literal CCD$S_MAINT = 112; ! size of MAINTenance record literal CCD$S_CHARGE = 112; ! size of CHARGE record literal CCD$K_CTU_KEY = 0; ! primary key literal CCD$S_CTU_KEY = 66; ! primary key size literal CCD$K_UT_KEY = 1; ! secondary key literal CCD$S_UT_KEY = 34; ! secondary key size literal CCD$K_EQ = 0; ! EQ matching literal CCD$K_EQNXT = 1; ! EQNXT matching literal CCD$S_CCDDEF = 112; macro CCD$R_FUNCTION_MODIFIERS = 0,0,8,0 %; literal CCD$S_FUNCTION_MODIFIERS = 1; ! for $SET_CHARGE macro CCD$V_NOVALIDATE = 0,0,1,0 %; ! don't validate CC macro CCD$V_NOEVENT = 0,1,1,0 %; ! don't sink an event macro CCD$V_NORESET = 0,2,1,0 %; ! don't reset counters macro CCD$V_SETTODEF = 0,3,1,0 %; ! set to default CC macro CCD$V_SETTOCUR = 0,4,1,0 %; ! set to current CC macro CCD$R_RECORD = 0,0,0,0 %; literal CCD$S_RECORD = 112; ! within charge code database macro CCD$T_CODE = 0,0,0,0 %; literal CCD$S_CODE = 32; ! charge code name macro CCD$L_TYPE = 32,0,32,0 %; ! record type macro CCD$T_USER = 36,0,0,0 %; literal CCD$S_USER = 32; ! user name macro CCD$L_FLAGS = 68,0,32,0 %; ! flags bits macro CCD$V_DISABLE = 68,0,1,0 %; ! disabled macro CCD$Q_EXPIRY = 72,0,0,0 %; literal CCD$S_EXPIRY = 8; ! expiry date+time macro CCD$T_DESC = 80,0,0,0 %; literal CCD$S_DESC = 32; ! description !*** MODULE $CDDBDEF *** ! + ! CDDB - Class Driver Data Block ! ! Auxiliary data block pointed at by the CRB$L_AUXSTRUC of an MSCP speaking ! intelligent disk or tape controller. There is one CDDB per such intelligent ! controller. ! ! - literal CDDB$M_SNGLSTRM = %X'1'; literal CDDB$M_IMPEND = %X'2'; literal CDDB$M_INITING = %X'4'; literal CDDB$M_RECONNECT = %X'8'; literal CDDB$M_RESYNCH = %X'10'; literal CDDB$M_POLLING = %X'20'; literal CDDB$M_ALCLS_SET = %X'40'; literal CDDB$M_NOCONN = %X'80'; literal CDDB$M_RSTRTWAIT = %X'100'; literal CDDB$M_QUORLOST = %X'200'; literal CDDB$M_DAPBSY = %X'400'; literal CDDB$M_2PBSY = %X'800'; literal CDDB$M_BSHADOW = %X'1000'; literal CDDB$M_DISABLED = %X'2000'; literal CDDB$M_PATHMOVE = %X'4000'; literal CDDB$M_PRMBSY = %X'8000'; literal CDDB$M_DISC_PEND = %X'10000'; literal CDDB$M_CRNSET = %X'20000'; literal CDDB$M_FIRM_WREV = %X'40000'; literal CDDB$M_PRMBSY_CLEANUP_PERMITTED = %X'80000'; literal CDDB$K_LENGTH = 168; ! Standard length of CDDB literal CDDB$C_LENGTH = 168; ! Standard length of CDDB literal CDDB$S_CDDB = 168; macro CDDB$L_CDRPQFL = 0,0,32,1 %; ! Active CDRP Q FLINK macro CDDB$L_CDRPQBL = 4,0,32,1 %; ! Active CDRP Q BLINK macro CDDB$W_SIZE = 8,0,16,0 %; ! Size of CDDB in bytes macro CDDB$B_TYPE = 10,0,8,0 %; ! Major structure type for Class Driver macro CDDB$B_SUBTYPE = 11,0,8,0 %; ! CDDB structure subtype field macro CDDB$B_SYSTEMID = 12,0,0,0 %; literal CDDB$S_SYSTEMID = 8; ! 48 bit system ID. macro CDDB$L_STATUS = 20,0,32,0 %; ! Status macro CDDB$V_SNGLSTRM = 20,0,1,0 %; ! Single stream mode after VC crash macro CDDB$V_IMPEND = 20,1,1,0 %; ! IMmediate command PENDing macro CDDB$V_INITING = 20,2,1,0 %; ! Currently initializing CONNECTION macro CDDB$V_RECONNECT = 20,3,1,0 %; ! Currently re-CONNECTING to MSCP server macro CDDB$V_RESYNCH = 20,4,1,0 %; ! re_CONNECT initiated by Class Driver macro CDDB$V_POLLING = 20,5,1,0 %; ! Polling for units macro CDDB$V_ALCLS_SET = 20,6,1,0 %; ! Allocation class has been set macro CDDB$V_NOCONN = 20,7,1,0 %; ! CDDB currently has no connection macro CDDB$V_RSTRTWAIT = 20,8,1,0 %; ! Waiting to RESTART_NEXT_CDRP macro CDDB$V_QUORLOST = 20,9,1,0 %; ! CNXMAN quorum lost processing macro CDDB$V_DAPBSY = 20,10,1,0 %; ! DAP CDRP is busy macro CDDB$V_2PBSY = 20,11,1,0 %; ! Failover fork block is busy macro CDDB$V_BSHADOW = 20,12,1,0 %; ! Controller uses "bundled" shadowing macro CDDB$V_DISABLED = 20,13,1,0 %; ! Controller not in use by class driver action macro CDDB$V_PATHMOVE = 20,14,1,0 %; ! Closing connection for port load balance macro CDDB$V_PRMBSY = 20,15,1,0 %; ! Permanent CDRP in use macro CDDB$V_DISC_PEND = 20,16,1,0 %; ! Connection disconnect pending macro CDDB$V_CRNSET = 20,17,1,0 %; ! ctrl ref not being seen macro CDDB$V_FIRM_WREV = 20,18,1,0 %; ! firmware problem macro CDDB$V_PRMBSY_CLEANUP_PERMITTED = 20,19,1,0 %; ! Permanent CDRP is busy but connection cleanup has permission to cleanup ! the PRMCDRP without arbitrating for it. macro CDDB$L_PDT = 24,0,32,1 %; ! Port Descriptor Table address macro CDDB$L_CRB = 28,0,32,1 %; ! CRB address macro CDDB$L_DDB = 32,0,32,1 %; ! DDB address macro CDDB$Q_CNTRLID = 36,0,0,0 %; literal CDDB$S_CNTRLID = 8; ! Controller ID returned by MSCP END PACKET macro CDDB$B_CNTRLMDL = 42,0,8,0 %; ! Controller model ! (byte 6 of controller id) macro CDDB$B_CNTRLCLS = 43,0,8,0 %; ! Controller class (byte 7 of controller id) macro CDDB$W_CNTRLFLGS = 44,0,16,0 %; ! Controller flags also returned by END PACKET macro CDDB$W_CNTRLTMO = 46,0,16,0 %; ! Controller timeout also returned by END PACKET macro CDDB$L_OLDRSPID = 48,0,32,0 %; ! RSPID of oldest outstanding MSCP command macro CDDB$L_OLDCMDSTS = 52,0,32,0 %; ! Latest MSCP command status for this command macro CDDB$L_RSTRTCDRP = 56,0,32,1 %; ! Addr of only active CDRP after VC re-establish macro CDDB$L_RETRYCNT = 60,0,32,0 %; ! # retries remaining for CDRP after VC reset macro CDDB$L_DAPCOUNT = 64,0,32,0 %; ! # DU$TMR loops until DAP_THREAD macro CDDB$L_RSTRTCNT = 68,0,32,0 %; ! # of resynch or connection error since boot macro CDDB$L_RSTRTQFL = 72,0,32,1 %; ! Queue wherein we accumulate, sort and select macro CDDB$L_RSTRTQBL = 76,0,32,1 %; ! for re-submission following VC re-establish macro CDDB$L_SAVED_PC = 80,0,32,1 %; ! Saved PC on internal subroutine calls macro CDDB$L_SAVED_PC1 = 84,0,32,1 %; ! Saved PC on internal subroutine calls macro CDDB$L_UCBCHAIN = 88,0,32,1 %; ! Chain of UCBs on connection macro CDDB$L_ORIGUCB = 92,0,32,1 %; ! Ptr to Orig. UCB if unchained macro CDDB$L_ALLOCLS = 96,0,32,0 %; ! Device Allocation Class macro CDDB$L_DAPCDRP = 100,0,32,1 %; ! Ptr to Deter.Acc.Path CDRP macro CDDB$L_CDDBLINK = 104,0,32,1 %; ! Link in CDDB chain macro CDDB$L_FOVER_CTR = 108,0,32,0 %; ! counter of reconnect intervals per failover try macro CDDB$L_WTUCBCTR = 112,0,32,0 %; ! counter of UCBs waiting for mount ver. to finish macro CDDB$L_MAXBCNT = 116,0,32,0 %; ! Max byte count for this connection macro CDDB$L_CTRLTR_MASK = 120,0,32,0 %; ! Mask of controller letters (ddCu:) used by this controller macro CDDB$L_CPYSEQNUM = 124,0,32,0 %; ! Base value IO$_COPYSHAD sequence number macro CDDB$L_DAP_LIMIT = 128,0,32,0 %; ! Credit stall counter macro CDDB$B_CSVRSN = 132,0,8,0 %; ! Controller microcode version macro CDDB$B_CHVRSN = 133,0,8,0 %; ! Controller hardware version macro CDDB$W_LOAD_AVAIL = 134,0,16,0 %; ! Load available from MSCP server macro CDDB$L_COUNTER = 136,0,32,0 %; ! General purpose counter (currently used by wrong-CDT check) macro CDDB$L_CONID = 140,0,32,0 %; ! Connection ID macro CDDB$L_CDT = 144,0,32,0 %; ! Ptr to Conn. Desc. Table macro CDDB$L_PRMCDRP = 148,0,32,1 %; ! Ptr to Perm. CDRP macro CDDB$L_RSVD1 = 152,0,32,0 %; macro CDDB$L_RSVD2 = 156,0,32,0 %; macro CDDB$L_RSVD3 = 160,0,32,0 %; macro CDDB$L_RSVD4 = 164,0,32,0 %; literal CDDB$S_CDDBDEF = 168; ! Old size name, synonym for CDDB$S_CDDB !*** MODULE $CDLDEF *** ! + ! CDL - SCS CONNECTION DESCRIPTOR LIST ! ! THERE IS A SYSTEM WIDE LIST OF CONNECTION DESCRIPTORS POINTED ! TO BY THE CDL. ! - literal CDL$C_LENGTH = 16; ! LENGTH OF NEG PORTION OF STRUCTURE literal CDL$S_CDLDEF = 20; literal CDL$S_CDL = 20; macro CDL$W_MAXCONIDX = -16,0,16,0 %; ! MAXIMUM ! OF CDT'S macro CDL$L_FREECDT = -12,0,32,1 %; ! ADDR OF 1ST FREE CDT macro CDL$W_SIZE = -8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro CDL$B_TYPE = -6,0,8,0 %; ! SCS STRUCTURE TYPE macro CDL$B_SUBTYP = -5,0,8,0 %; ! SCS STRUCT SUBTYPE FOR CDL macro CDL$L_NOCDT_CNT = -4,0,32,0 %; ! Count of CDT allocation failures macro CDL$L_BASE = 0,0,32,1 %; ! BASE OF THE TABLE !*** MODULE $CDTDEF *** ! + ! CDT - SCS CONNECTION DESCRIPTOR TABLE ! ! THESE DESCRIPTORS ARE POINTED TO BY THE SYSTEM WIDE CONNECTION ! DESCRIPTOR LIST (CDL). ONE CDT IS USED PER SCS VIRTUAL CIRCUIT ! OR LISTENING CONNECTION. ! - literal CDT$C_CLOSED = 0; ! CLOSED literal CDT$C_LISTEN = 1; ! LISTENING FOR CONNX REQUESTS literal CDT$C_OPEN = 2; ! OPEN literal CDT$C_DISC_ACK = 3; ! DISCONNECT ACKNOWLEDGED literal CDT$C_DISC_REC = 4; ! DISCONNECT REQ RECEIVED literal CDT$C_DISC_SENT = 5; ! DISCONNECT SENT literal CDT$C_DISC_MTCH = 6; ! DISCONNECT MATCH literal CDT$C_CON_SENT = 7; ! CONNECT REQ SENT literal CDT$C_CON_ACK = 8; ! CONNECT REQ SENT AND ACK'ED literal CDT$C_CON_REC = 9; ! CONNECT REQ RECEIVED literal CDT$C_ACCP_SENT = 10; ! ACCEPT REQ SENT literal CDT$C_REJ_SENT = 11; ! REJECT SENT literal CDT$C_DISC_MTCH_RSPQ = 12; ! MATCHING DISCONNECT RESPONSE IN PROGRESS literal CDT$C_DISC_RSPQ = 13; ! DISCONNECT RESPONSE IN PROGRESS literal CDT$C_VC_FAIL = 14; ! VIRTUAL CIRCUIT FAILED ! literal CDT$C_CON_PEND = 1; ! WAITING TO SEND CONNECT REQ literal CDT$C_ACCP_PEND = 2; ! WAITING TO SEND ACCEPT REQ literal CDT$C_REJ_PEND = 3; ! WAITING TO SEND REJECT REQ literal CDT$C_DISC_PEND = 4; ! WAITING TO SEND DISCONNECT REQ literal CDT$C_CR_PEND = 5; ! WAITING TO SEND CREDIT literal CDT$C_DCR_PEND = 6; ! WAITING TO SEND CREDIT IN ! PREPARATION FOR DISCONNECT literal CDT$C_RATING0 = 0; ! (TYC 4-JAN-89) Undefined yet but valid value literal CDT$C_RATING1 = 1; ! (TYC 4-JAN-89) Undefined yet but valid value literal CDT$C_RATING2 = 2; ! (TYC 4-JAN-89) Undefined yet but valid value literal CDT$C_RATING3 = 3; ! (TYC 4-JAN-89) Undefined yet but valid value ! MOVE SUGGESTED FOR AN EQUAL PATH (I.E. CI->CI) literal CDT$C_YELLOW = 4; ! (TYC 4-JAN-89) port is in YELLOW zone literal CDT$C_RATING5 = 5; ! (TYC 4-JAN-89) Undefined yet but valid value literal CDT$C_RED = 6; ! port is in RED zone (i.e. port is saturated) literal CDT$C_UNEQUAL_PATH = 7; ! MOVE SUGGESTED FOR AN UNEQUAL PATH (I.E. NI->CI) literal CDT$C_LOAD_SHARE_DISABLE = 8; ! load sharing disabled ! literal CDT$C_BAD_RATING = -2147483648; ! (TYC 4-JAN-89) Bad load rating marker literal CDT$K_BAD_RATING = -2147483648; literal CDT$C_LOADSHARE = 0; ! (TYC 21-Jun-89) Load sharing SYSAP literal CDT$C_PRE_LOADSHARE = 1; ! (TYC 21-Jun-89) Pre-load sharing SYSAP ! literal CDT$K_LENGTH = 400; ! LENGTH OF CDT literal CDT$C_LENGTH = 400; ! LENGTH OF CDT literal CDT$S_CDTDEF = 400; ! Old size name, synonym literal CDT$S_CDT = 400; macro CDT$L_MSGINPUT = 0,0,32,1 %; ! SYSAP Message Input Dispatcher routine macro CDT$L_LINK = 0,0,32,1 %; ! OR LINK TO NEXT FREE CDT macro CDT$L_DGINPUT = 4,0,32,1 %; ! SYSAP Datagram Received Routine macro CDT$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro CDT$B_TYPE = 10,0,8,0 %; ! SCS STRUCTURE TYPE macro CDT$B_SUBTYP = 11,0,8,0 %; ! SCS STRUCT SUBTYPE FOR CDT macro CDT$L_ERRADDR = 12,0,32,1 %; ! SYSAP Error Notification routine macro CDT$L_FAST_RECVMSG_REQUEST = 16,0,32,1 %; ! SYSAP routine to see if Fast Path can be used for a received message macro CDT$L_FAST_RECVMSG_PM = 20,0,32,1 %; ! SYSAP routine to process received message via Fast Path macro CDT$L_CHANGE_AFFINITY = 24,0,32,1 %; ! SYSAP routine to process changes in Fast Path port CPU affinity macro CDT$L_PDT = 28,0,32,1 %; ! ADDR OF ASSOC PORT DESC TABLE macro CDT$L_RCONID = 32,0,32,0 %; ! REMOTE CONNECTION ID macro CDT$L_LCONID = 36,0,32,0 %; ! LOCAL CONNECTION ID macro CDT$L_PB = 40,0,32,1 %; ! ADDR OF ASSOC PATH BLOCK macro CDT$B_RSTATION = 44,0,0,0 %; literal CDT$S_RSTATION = 6; ! REMOTE STATION ADDR macro CDT$W_REASON = 50,0,16,0 %; ! REJECT/DISCONNECT REASON macro CDT$W_STATE = 52,0,16,0 %; ! CONNECTION STATE ! STATE VALUES: ! 0 ORIGIN, INCREMENTS OF 1: macro CDT$W_BLKSTATE = 54,0,16,0 %; ! SCS SEND BLOCKED STATE ! STATE VALUES: ! 1 ORIGIN, INCREMENTS OF 1: ! macro CDT$L_SCSMSG = 56,0,32,1 %; ! ADDR OF SCS RECEIVE BUFFER macro CDT$L_WAITQFL = 60,0,32,1 %; ! SEND SCS MSG WAIT QUEUE FLINK macro CDT$L_WAITQBL = 64,0,32,1 %; ! SEND SCS MSG WAIT QUEUE BLINK macro CDT$L_CRWAITQFL = 68,0,32,1 %; ! SEND CREDIT WAIT QUEUE FLINK macro CDT$L_CRWAITQBL = 72,0,32,1 %; ! SEND CREDIT WAIT QUEUE BLINK macro CDT$W_SEND = 76,0,16,0 %; ! CURRENT SEND CREDIT macro CDT$W_REC = 78,0,16,0 %; ! RECEIVE CREDIT (SEND CREDIT ! HELD BY REMOTE) macro CDT$W_MINREC = 80,0,16,0 %; ! MINIMUM RECEIVE CREDIT (MIN ! SEND REQUIRED BY REMOTE) macro CDT$W_PENDREC = 82,0,16,0 %; ! RECEIVE CREDIT NOT YET EXTENDED ! TO REMOTE macro CDT$W_INITLREC = 84,0,16,0 %; ! INITIAL RECEIVE CREDIT macro CDT$W_MINSEND = 86,0,16,0 %; ! MINIMUM SEND CREDIT macro CDT$W_DGREC = 88,0,16,0 %; ! DATAGRAMS QUEUED FOR RECEIVE macro CDT$B_PRIORITY = 90,0,8,0 %; ! BLOCK TRANSFER PRIORIY macro CDT$L_RPROCNAM = 92,0,32,1 %; ! ADDR OF REMOTE PROCESS NAME macro CDT$L_LPROCNAM = 96,0,32,1 %; ! ADDR OF LOCAL PROCESS NAME macro CDT$L_CONDAT = 100,0,32,1 %; ! ADDR OF CONNECT DATA macro CDT$L_AUXSTRUC = 104,0,32,1 %; ! ADDR OF AUXILARY DATA STRUCTURE macro CDT$L_BADRSP = 108,0,32,1 %; ! ADDR IN SYSAP TO CALL WITH ! BAD RESPONSE(UNIMPLEMENTED) macro CDT$L_FPC = 112,0,32,0 %; ! SAVED FORK PROCESS PC macro CDT$L_FR5 = 116,0,32,0 %; ! SAVED FORK PROCESS R5 macro CDT$L_CDTLST = 120,0,32,1 %; ! LINK FOR CDT LIST FROM PB macro CDT$L_DGSENT = 124,0,32,0 %; ! # APPLICATION DGS SENT macro CDT$L_DGRCVD = 128,0,32,0 %; ! # APPLICATION DGS REC'D macro CDT$L_DGDISCARD = 132,0,32,0 %; ! # DGS DISCARDED BY DRIVER macro CDT$L_MSGSENT = 136,0,32,0 %; ! # APPLICATION MSGS SENT macro CDT$L_MSGRCVD = 140,0,32,0 %; ! # APPLICATION MSGS REC'D macro CDT$L_NON_FP_SENDMSGS = 144,0,32,0 %; ! Counter of number of non-Fast Path send messages macro CDT$L_NON_FP_RCVDMSGS = 148,0,32,0 %; ! Counter of number of non-Fast Path receive messages macro CDT$L_SNDDATS = 152,0,32,0 %; ! # SEND DATAS INITIATED macro CDT$L_BYTSENT = 156,0,32,0 %; ! # BYTES SENT VIA SEND DATAS macro CDT$L_REQDATS = 160,0,32,0 %; ! #REQ DATAS INITIATED macro CDT$L_BYTREQD = 164,0,32,0 %; ! BYTES REC'D VIA REQ DATAS macro CDT$L_BYTMAPD = 168,0,32,0 %; ! TOTAL BYTES MAPPED macro CDT$W_QCR_CNT = 172,0,16,0 %; ! # TIMES QUEUED FOR SEND CREDIT macro CDT$W_QBDLT_CNT = 174,0,16,0 %; ! # TIMES QUEUED FOR BDLT ! (TYC 14-FEB-89) LOAD SHARING FIELDS macro CDT$L_MOVE_PATH_ADDR = 176,0,32,1 %; ! CONNECTION MOVE ADDRESS ! 1 ORIGIN, INCREMENTS OF 1: macro CDT$L_SHARE_FLINK = 180,0,32,1 %; ! DYNAMIC LOAD SHARING CDT QUEUE FLINK macro CDT$L_SHARE_BLINK = 184,0,32,1 %; ! DYNAMIC LOAD SHARING CDT QUEUE BLINK macro CDT$L_SB = 188,0,32,1 %; ! SYSTEM BLOCK ADDRESS ! R1 load rating on entry (TYC 4-JAN-89) macro CDT$L_CON_REQ_CTR = 192,0,32,0 %; ! (TYC 25-Apr-89) # of times CONN REQ sent macro CDT$L_LOAD_RATING = 196,0,32,0 %; ! LOAD RATING (TYC 4-JAN-89 now used) macro CDT$L_TIME_STAMP = 200,0,32,0 %; ! TIME STAMP (EXE$GL_ABSTIM) OF CONNECTION FORMATION macro CDT$L_QUEUE_TIME_STAMP = 204,0,32,0 %; ! (TYC 15-Feb-89) TIME STAMP OF MOVING CDT TO QUEUE macro CDT$L_DISCON_COUNTER = 208,0,32,0 %; ! (TYC 15-Feb-89) LOAD SHARING DISCONNECT COUNTER ! used with conditional assembly macro CDT$L_OPTIMAL_PATH = 212,0,32,1 %; ! (TYC 15-Feb-89) PATH ADDRESS OF THE OPTIMAL PORT macro CDT$L_BYTES_XFER = 216,0,32,0 %; ! (TYC 15-Feb-89) TOTAL BYTES XFERRED (BOTH XMIT & RCV) macro CDT$L_BYTES_DG_XMT = 220,0,32,0 %; ! (TYC 15-Feb-89) TOTAL DG BYTES XMITTED macro CDT$L_BYTES_DG_RCV = 224,0,32,0 %; ! (TYC 15-Feb-89) TOTAL DG BYTES RECEIVED macro CDT$L_BYTES_MSG_XMT = 228,0,32,0 %; ! (TYC 15-Feb-89) TOTAL MSG BYTES XMITTED macro CDT$L_BYTES_MSG_RCV = 232,0,32,0 %; ! (TYC 15-Feb-89) TOTAL MSG BYTES RECEIVED macro CDT$L_BYTES_XFER_LAST = 236,0,32,0 %; ! (TYC 31-Aug-89) TOTAL BYTES XFERRED ! UP TO LAST LOAD SHARING INTERVAL macro CDT$L_BYTES_DG_XMT_LAST = 240,0,32,0 %; ! (TYC 31-Aug-89) TOTAL DG BYTES XMITTED ! UP TO LAST LOAD SHARING INTERVAL macro CDT$L_BYTES_DG_RCV_LAST = 244,0,32,0 %; ! (TYC 31-Aug-89) TOTAL DG BYTES RECEIVED ! UP TO LAST LOAD SHARING INTERVAL macro CDT$L_BYTES_MSG_XMT_LAST = 248,0,32,0 %; ! (TYC 31-Aug-89) TOTAL MSG BYTES XMITTED ! UP TO LAST LOAD SHARING INTERVAL macro CDT$L_BYTES_MSG_RCV_LAST = 252,0,32,0 %; ! (TYC 31-Aug-89) TOTAL MSG BYTES RECEIVED ! UP TO LAST LOAD SHARING INTERVAL macro CDT$L_BYTMAPD_LAST = 256,0,32,0 %; ! (TYC 31-Aug-89) TOTAL BYTES MAPPED ! UP TO LAST LOAD SHARING INTERVAL macro CDT$L_DGSENT_LAST = 260,0,32,0 %; ! (TYC 31-Aug-89) TOTAL DGS XMITTED ! UP TO LAST LOAD SHARING INTERVAL macro CDT$L_DGRCVD_LAST = 264,0,32,0 %; ! (TYC 31-Aug-89) TOTAL DGS RECEIVED ! UP TO LAST LOAD SHARING INTERVAL macro CDT$L_MSGSENT_LAST = 268,0,32,0 %; ! (TYC 31-Aug-89) TOTAL MSGS XMITTED ! UP TO LAST LOAD SHARING INTERVAL macro CDT$L_MSGRCVD_LAST = 272,0,32,0 %; ! (TYC 31-Aug-89) TOTAL MSGS RECEIVED ! UP TO LAST LOAD SHARING INTERVAL ! (TYC 17-Feb-89) peak counters used with conditional assembly macro CDT$L_BYTES_XFER_PEAK = 276,0,32,0 %; ! PEAK VALUE OF TOTAL BYTES XFERRED macro CDT$L_BYTES_DG_XMT_PEAK = 280,0,32,0 %; ! PEAK VALUE OF TOTAL DG BYTES XMITTED macro CDT$L_BYTES_DG_RCV_PEAK = 284,0,32,0 %; ! PEAK VALUE OF TOTAL DG BYTES RECEIVED macro CDT$L_BYTES_MSG_XMT_PEAK = 288,0,32,0 %; ! PEAK VALUE OF TOTAL MSG BYTES XMITTED macro CDT$L_BYTES_MSG_RCV_PEAK = 292,0,32,0 %; ! PEAK VALUE OF TOTAL MSG BYTES RECEIVED macro CDT$L_BYTMAPD_PEAK = 296,0,32,0 %; ! PEAK VALUE OF TOTAL BYTES MAPPED macro CDT$L_DGSENT_PEAK = 300,0,32,0 %; ! PEAK VALUE OF TOTAL DGS XMITTED macro CDT$L_DGRCVD_PEAK = 304,0,32,0 %; ! PEAK VALUE OF TOTAL DGS RECEIVED macro CDT$L_MSGSENT_PEAK = 308,0,32,0 %; ! PEAK VALUE OF TOTAL MSGS XMITTED macro CDT$L_MSGRCVD_PEAK = 312,0,32,0 %; ! PEAK VALUE OF TOTAL MSGS RECEIVED ! (TYC 17-Feb-89) average counters used with conditional assembly macro CDT$L_BYTES_XFER_AVG = 316,0,32,0 %; ! AVERAGE VALUE OF TOTAL BYTES XFERRED macro CDT$L_BYTES_DG_XMT_AVG = 320,0,32,0 %; ! AVERAGE VALUE OF TOTAL DG BYTES XMITTED macro CDT$L_BYTES_DG_RCV_AVG = 324,0,32,0 %; ! AVERAGE VALUE OF TOTAL DG BYTES RECEIVED macro CDT$L_BYTES_MSG_XMT_AVG = 328,0,32,0 %; ! AVERAGE VALUE OF TOTAL MSG BYTES XMITTED macro CDT$L_BYTES_MSG_RCV_AVG = 332,0,32,0 %; ! AVERAGE VALUE OF TOTAL MSG BYTES RECEIVED macro CDT$L_BYTMAPD_AVG = 336,0,32,0 %; ! AVERAGE VALUE OF TOTAL BYTES MAPPED macro CDT$L_DGSENT_AVG = 340,0,32,0 %; ! AVERAGE VALUE OF TOTAL DGS XMITTED macro CDT$L_DGRCVD_AVG = 344,0,32,0 %; ! AVERAGE VALUE OF TOTAL DGS RECEIVED macro CDT$L_MSGSENT_AVG = 348,0,32,0 %; ! AVERAGE VALUE OF TOTAL MSGS XMITTED macro CDT$L_MSGRCVD_AVG = 352,0,32,0 %; ! AVERAGE VALUE OF TOTAL MSGS RECEIVED macro CDT$L_BYTES_XFER_INT = 356,0,32,0 %; ! (TYC 31-AUG-89) TOTAL BYTES XFERRED ! DURING LAST LOAD SHARING INTERVAL ! (TYC 21-Jun-89) Moved fields macro CDT$W_LOCAL_INDEX = 360,0,16,0 %; ! LOCAL PROCESS NAME INDEX macro CDT$B_LS_FLAG = 362,0,8,0 %; ! (TYC 15-Feb-89) LOAD SHARING FLAG. IF SET, ! THE CONNECTION IS REQUESTED TO DISCONNECT macro CDT$B_SYSAP_VERSION = 363,0,8,0 %; ! (TYC 21-Jun-89) Flag for SYSAP version ! (TYC 21-Jun-89) SYSAP version constants ! be quadword aligned: macro CDT$B_SCS_MAINT_BLOCK = 368,0,0,0 %; literal CDT$S_SCS_MAINT_BLOCK = 16; ! Add a Maintenance block to the CDT ! which must be quadword aligned macro CDT$L_FP_SCS_NOSEND = 384,0,32,0 %; ! Counter of number of times SCS votes no on Send Msg macro CDT$L_FP_SCS_NORECV = 388,0,32,0 %; ! Counter of number of times SCS votes no on Receive Msg macro CDT$L_RESERVED3 = 392,0,32,0 %; ! RESERVED macro CDT$L_RESERVED4 = 396,0,32,0 %; ! RESERVED !*** MODULE $CEBDEF *** ! + ! COMMON EVENT BLOCK ! - literal CEB$M_NOQUOTA = %X'1'; literal CEB$M_PERM = %X'2'; literal CEB$M_RSRVD_2_31 = %X'FFFFFFFC'; literal CEB$K_LENGTH = 72; ! LENGTH OF COMMON EVENT BLOCK literal CEB$C_LENGTH = 72; ! LENGTH OF COMMON EVENT BLOCK literal CEB$S_CEBDEF = 72; literal CEB$S_CEB = 72; macro CEB$L_CEBFL = 0,0,32,1 %; ! POINTER TO NEXT COMMON EVENT BLOCK macro CEB$L_CEBBL = 4,0,32,1 %; ! POINTER TO PREVIOUS COMMON EVENT BLOCK macro CEB$W_SIZE = 8,0,16,0 %; ! SIZE OF COMMON EVENT BLOCK IN BYTES macro CEB$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE CODE FOR CEB macro CEB$L_STS = 12,0,32,0 %; ! STATUS FLAGS FOR CEB macro CEB$V_NOQUOTA = 12,0,1,0 %; ! NO QUOTA UPDATE macro CEB$V_PERM = 12,1,1,0 %; ! PERMANENT CLUSTER macro CEB$V_RSRVD_2_31 = 12,2,30,0 %; literal CEB$S_RSRVD_2_31 = 30; macro CEB$L_PID = 16,0,32,0 %; ! PID OF CREATOR macro CEB$L_EFC = 20,0,32,0 %; ! EVENT FLAGS (32 BIT VECTOR) macro CEB$L_WQFL = 24,0,32,1 %; ! HEAD OF WAIT QUEUE macro CEB$L_WQBL = 28,0,32,1 %; ! TAIL OF WAIT QUEUE macro CEB$L_WQCNT = 32,0,32,0 %; ! WAIT QUEUE COUNT(LENGTH) macro CEB$L_STATE = 36,0,32,0 %; ! CEF WAIT STATE NUMBER macro CEB$L_ORB = 40,0,32,1 %; ! POINTER TO THE ORB macro CEB$L_UIC = 44,0,32,0 %; ! USER IDENT OF CEB CREATOR macro CEB$W_GRP = 46,0,16,0 %; ! GROUP NUMBER OF OWNER macro CEB$L_PROT = 48,0,32,0 %; ! PROTECTION MASK macro CEB$L_REFC = 52,0,32,0 %; ! REFERENCE COUNT FOR CEB macro CEB$T_EFCNAM = 56,0,0,0 %; literal CEB$S_EFCNAM = 16; ! EVENT CLUSTER TEXT NAME !*** MODULE CFGDEF *** literal CFG$K_GALAXY_ID_LENGTH = 16; ! ! typedef the ID and HANDLE ! macro CFG_ID = 0,0,0,0 %; literal S_CFG_ID = 8; macro CFG_HANDLE = 0,0,0,1 %; literal S_CFG_HANDLE = 8; ! ! Version 6.1 for Itanium Systems (free to move ahead) ! literal CFG$K_REVISION_MAJOR = 6; literal CFG$K_REVISION_MINOR = 1; ! ! Success codes ! literal CFG$K_SUCCESS = 1; literal CFG$K_NOSTATUS = 0; ! ! Error codes. All negative, all even (low bit clear) ! This allows BLISS tests for errors on the low bit to ! work correctly... even though they are not VMS error ! codes. ! literal CFG$K_BADPARAM = -2; ! Bad parameter in call literal CFG$K_ILLEGAL = -4; ! Operation is illegal literal CFG$K_NOTFOUND = -6; ! Lookup failed literal CFG$K_BADALIGN = -8; ! Bad PA alignment literal CFG$K_BADALLOC = -10; ! Invalid size increment literal CFG$K_OVERLAP = -12; ! Fragment overlaps with existing literal CFG$K_NOTINITIALIZED = -14; ! Tree not initialized literal CFG$K_BADHANDLE = -16; ! Illegal HANDLE literal CFG$K_NOTDELETED = -18; ! Node was not deleted literal CFG$K_MAXEXCEEDED = -20; ! Too many memory fragments literal CFG$K_NOTALLOWED = -22; ! Operation is not allowed literal CFG$K_BADOWNER = -24; ! Node does not have the right owner literal CFG$K_NOTDONE = -26; ! Assync callback has not yet finished literal CFG$K_NOTPARTITION = -28; ! The node is not a partition literal CFG$K_NOTCOMMUNITY = -30; ! The node is not a community literal CFG$K_ILLEGALTREE = -32; ! Corrupt tree state literal CFG$K_NOTHARDWARE = -34; ! The node is not a hardware component literal CFG$K_NOMEMORY = -36; ! Failed to allocate the node literal CFG$K_BADPFN = -38; ! PFN is not in the memory system literal CFG$K_BADCOUNT = -40; ! Fragment count is not valid literal CFG$K_TREELOCKED = -42; ! Attempt to lock a locked tree literal CFG$K_BADUPDATELEVEL = -44; ! Illegal update level input literal CFG$K_NOTMEMORYDESC = -46; ! Not a memory descriptor node literal CFG$K_NOTLOCKED = -48; ! Tried to unlock an unlocked tree literal CFG$K_UNAVAILABLE = -50; ! Node is not available literal CFG$K_STILLACTIVE = -52; ! HW Component is still active literal CFG$K_CHILDSTILLACTIVE = -54; ! A component part of HW is still active literal CFG$K_CHILDALREADYOWNED = -56; ! A child is owned internal error literal CFG$K_NOTSHARED = -58; ! Can't assign because an ancestor is not shared literal CFG$K_TREEBEINGUPDATED = -60; ! Update in progress literal CFG$K_BADTREEINTEGRITY = -62; ! Tree corruption detected literal CFG$K_NOTHARDPARTITION = -64; ! The node is not a hard partition literal CFG$K_NOTIMPLEMENTED = -66; ! A callback which is not yet implemented literal CFG$K_ALREADYOWNED = -68; ! Node already has an owner literal CFG$K_CHANGECOLLISION = -70; ! Node change_counter does not match literal CFG$K_NOTSOFTWARE = -72; ! Node is not a software node literal CFG$K_NO_TREE_CHANGE = -74; ! Tree was not changed literal CFG$K_WRONG_SPEED = -76; ! Incompatible operating speed literal CFG$K_WRONG_MODE = -78; ! Incompatible operating mode literal CFG$K_POWER_BUDGET_EXCEEDED = -80; ! Scotty, I need more power! literal CFG$K_MEMORY_SPACE_EXCEEDED = -82; ! PCI Memory Exceeded literal CFG$K_IO_SPACE_EXCEEDED = -84; ! PCI IO Space Exceeded literal CFG$K_CONSOLE_REJECTED_CHANGE = -86; ! Console rejected hot-plug operation literal CFG$K_POWER_FAULT = -88; ! Device Power Fault literal CFG$K_PHPC_FAULT = -90; ! Hot-plug controller fault literal CFG$K_ACCEPTREJECT = -92; ! Flags deny resource assignment ! ! Node TYPE codes ! literal CFG$K_NODE_ROOT = 1; ! Root node literal CFG$K_NODE_HW_ROOT = 2; ! Hardware Root literal CFG$K_NODE_SW_ROOT = 3; ! Software Root literal CFG$K_NODE_TEMPLATE_ROOT = 4; ! Template Root literal CFG$K_NODE_COMMUNITY = 5; ! Community literal CFG$K_NODE_PARTITION = 6; ! Partition literal CFG$K_NODE_SBB = 7; ! System Building Block literal CFG$K_NODE_PSEUDO = 8; ! Pseudo device literal CFG$K_NODE_CPU = 9; ! CPU literal CFG$K_NODE_MEMORY_SUB = 10; ! Memory Subsystem literal CFG$K_NODE_MEMORY_DESC = 11; ! Memory Description literal CFG$K_NODE_MEMORY_CTRL = 12; ! Memory Controller literal CFG$K_NODE_IOP = 13; ! IO Processor literal CFG$K_NODE_HOSE = 14; ! IO Hose literal CFG$K_NODE_BUS = 15; ! Option Bus literal CFG$K_NODE_IO_CTRL = 16; ! IO Controller literal CFG$K_NODE_SLOT = 17; ! Option slot literal CFG$K_NODE_CPU_MODULE = 18; ! CPU module board literal CFG$K_NODE_POWER_ENVIR = 19; ! Power Environmental literal CFG$K_NODE_FRU_ROOT = 20; ! FRU Root literal CFG$K_NODE_FRU_DESC = 21; ! FRU Descripter literal CFG$K_NODE_SMB = 22; ! System Mother Board literal CFG$K_NODE_CAB = 23; ! Cabinet literal CFG$K_NODE_CHASSIS = 24; ! System Chassis literal CFG$K_NODE_EXP_CHASSIS = 25; ! Expander Chassis literal CFG$K_NODE_SYS_INTER_SWITCH = 26; ! System Interconnect Switch literal CFG$K_NODE_HARD_PARTITION = 27; ! Hard partition (firewall) literal CFG$K_NODE_RISER = 28; ! IO Riser Module literal CFG$K_NODE_SOC = 29; ! System Ona Chip literal CFG$K_NODE_SOCKET = 30; ! Processor Socket literal CFG$K_NODE_CORE = 31; ! Processor Core literal CFG$K_NODE_THREAD = 32; ! Processor Thread literal CFG$K_NODE_LAST = 33; ! Always Last ! ! Routine index values for console callbacks ! literal CFG$K_READ_LOCK = 1; ! Take out a read lock literal CFG$K_READ_UNLOCK = 2; ! Release the read lock literal CFG$K_SET_NODE_FLAGS = 3; ! Set bits a node's flags literal CFG$K_CLEAR_NODE_FLAGS = 4; ! Clear bits in a node's flags literal CFG$K_ASSIGN_DESCRIPTOR = 5; ! Assign a memory descriptor literal CFG$K_UPDATE_TREE = 6; ! Update configuration tree literal CFG$K_CREATE_COMMUNITY = 7; ! Create a community node literal CFG$K_DELETE_COMMUNITY = 8; ! Delete a community literal CFG$K_CREATE_PARTITION = 9; ! Create a partition node literal CFG$K_DELETE_PARTITION = 10; ! Delete a partition literal CFG$K_ASSIGN_HW = 11; ! Assign HW to a community or partition literal CFG$K_UPDATE_OS_USAGE = 12; ! Update OS-specific field literal CFG$K_FIND_PARTITION = 13; ! Find Partition literal CFG$K_FIND_NODE = 14; ! Search for a component literal CFG$K_GET_TEXT = 15; ! Get a text string literal CFG$K_UPDATE_GMDB = 16; ! Update GMDB area in community literal CFG$K_VALIDATE_PARTITION = 17; ! Validate a partition literal CFG$K_INITIALIZE_PARTITION = 18; ! Initialize a partition literal CFG$K_UPDATE_GALAXY_ID = 19; ! Update the Galaxy ID literal CFG$K_GET_MAX_PARTITION = 20; ! RETAINED BUT NO LONGER USED literal CFG$K_UPDATE_INSTANCE_NAME = 21; ! Read/Write Instance Name literal CFG$K_SAVE_CONFIG = 22; ! Save Configuration literal CFG$K_GET_SENSOR_INFO = 23; ! Get sensor information literal CFG$K_CREATE_HARD_PARTITION = 24; ! Create a hard partition literal CFG$K_DELETE_HARD_PARTITION = 25; ! DELETE a hard partition literal CFG$K_POWER_HW = 26; ! Power Management Control literal CFG$K_UPDATE_TESTED_PFNS = 27; ! Update tested PFN field literal CFG$K_SET_ERROR_TARGET = 28; ! Declare the new error target literal CFG$K_CLEAR_CB_STATE = 29; ! Clear callback state literal CFG$K_GET_AVAIL_HW = 30; ! Get available hardware information literal CFG$K_UPDATE_NODE = 31; ! Update all environmental sensor data ! ! Routine argument values for SET/CLEAR_NODE_FLAGS callback ! literal CFG$K_NODE_FLAGS = 0; ! Operate on node flags literal CFG$K_PART_FLAGS = 1; ! Operate on partition flags literal CFG$K_COMM_FLAGS = 2; ! Operate on community flags literal CFG$K_HARD_FLAGS = 3; ! Operate on hard partition flags literal CFG$K_ROOT_FLAGS = 4; ! Operate on root node flags ! ! Routine argument mask bits for ASSIGN_HW callback ! literal CFG$M_ALL_DESCENDANTS = 1; literal CFG$M_ASSIGN_POWER_UP = 2; literal CFG$M_ASSIGN_POWER_DOWN = 4; literal CFG$M_IGNORE_COUNTER = 8; ! Synonyms for UP and DOWN literal CFG$M_ASSIGN_POWER_ON = 2; literal CFG$M_ASSIGN_POWER_OFF = 4; ! ! Routine argument mask bits for UPDATE_OS_USAGE callback ! literal CFG$M_NO_TREE_CHANGE = 0; ! ! Routine argument mask values for SAVE_CONFIG callback ! Note the longer prefix. This was required to resolve duplicate ! defs of ALL_DESCENDANTS ! literal CFG$M_CURRENT_OWNER = 1; literal CFG$M_SAVE_DESCENDANTS = 2; ! ! Routine argument values for POWER_HW callback ! literal CFG$K_POWER_HW_DOWN = 0; literal CFG$K_POWER_HW_UP = 1; ! Synonyms for DOWN and UP literal CFG$K_POWER_HW_OFF = 0; literal CFG$K_POWER_HW_ON = 1; ! ! Node subtype codes ! literal CFG$K_SNODE_UNKNOWN = 0; ! Unknown subtype ! CPU codes literal CFG$K_SNODE_CPU_NOPRIMARY = 1; ! A CPU not capable of being a primary ! Bus codes literal CFG$K_SNODE_PCI = 2; ! Peripheral Component Interconnect literal CFG$K_SNODE_EISA = 3; ! Extended ISA bus literal CFG$K_SNODE_ISA = 4; ! Industry Standard Architecture bus literal CFG$K_SNODE_XMI = 5; ! XMI bus literal CFG$K_SNODE_FBUS = 6; ! FutureBus literal CFG$K_SNODE_XBUS = 7; ! Built in device bus literal CFG$K_SNODE_USB = 8; ! Univeral Serial Bus ! IO controller codes literal CFG$K_SNODE_SERIAL_PORT = 9; ! Serial port literal CFG$K_SNODE_FLOPPY = 10; ! Standard Floppy literal CFG$K_SNODE_PARALLEL_PORT = 11; ! Parallel port literal CFG$K_SNODE_SCSI = 12; ! SCSI Controller literal CFG$K_SNODE_IDE = 13; ! IDE Controller literal CFG$K_SNODE_NI = 14; ! Ethernet Controller literal CFG$K_SNODE_FDDI = 15; ! FDDI literal CFG$K_SNODE_TOKEN_RING = 16; ! Token Ring literal CFG$K_SNODE_NI_SCSI = 17; ! Combo card literal CFG$K_SNODE_GRAPHICS = 18; ! Graphics Controller literal CFG$K_SNODE_ATM = 19; ! ATM Controller literal CFG$K_SNODE_MEM_CHAN = 20; ! Memory Channel literal CFG$K_SNODE_CI = 21; ! CI adapter literal CFG$K_SNODE_1394 = 22; ! literal CFG$K_SNODE_AGP = 23; ! AGP (Graphics Port) literal CFG$K_SNODE_SUPER_HIPPI = 24; ! Super Hippi literal CFG$K_SNODE_FIBRECHANNEL = 25; ! Fibrechannel literal CFG$K_SNODE_CAB = 26; ! Cabinet literal CFG$K_SNODE_CHASSIS = 27; ! System Chassis literal CFG$K_SNODE_EXP_CHASSIS = 28; ! Expander Chassis literal CFG$K_SNODE_POWER_SUPPLY = 29; ! Power Envir - Power Supply literal CFG$K_SNODE_COOLING = 30; ! Power Envir - Cooling literal CFG$K_SNODE_SIMM = 31; ! SIMM memory card literal CFG$K_SNODE_DIMM = 32; ! DIMM memory card literal CFG$K_SNODE_RIMM = 33; ! RIMM memory card literal CFG$K_SNODE_CPU_MODULE = 34; literal CFG$K_SNODE_CPU_CACHE_MODULE = 35; literal CFG$K_SNODE_CPU_MEMORY_MODULE = 36; literal CFG$K_SNODE_MEM_CARRIER_MODULE = 37; literal CFG$K_SNODE_BACKPLANE_ASSY = 38; literal CFG$K_SNODE_MOTHER_BOARD = 39; literal CFG$K_SNODE_FAN = 40; literal CFG$K_SNODE_SYS_INTERCONN_PORT = 41; literal CFG$K_SNODE_SYS_INTERCONN_SW = 42; literal CFG$K_SNODE_MEM_COHERE_MODULE = 43; literal CFG$K_SNODE_IO_PORT_MODULE = 44; literal CFG$K_SNODE_REMOTE_MGNT_MODULE = 45; literal CFG$K_SNODE_PWR_ENV_CTRL_MODULE = 46; literal CFG$K_SNODE_MULTI_DEVICE = 47; literal CFG$K_SNODE_IO_EXP_CAB = 48; literal CFG$K_SNODE_EXPANSION_CAB = 49; literal CFG$k_reserved1 = 50; literal CFG$K_SNODE_DAUGHTER_CARD = 51; literal CFG$K_SNODE_RISER_CARD = 52; literal CFG$K_SNODE_CPU_FAN = 53; literal CFG$K_SNODE_MASTER_CLOCK = 54; ! Master Clock Module literal CFG$K_SNODE_CLOCK_DIST = 55; ! Clock splitter/distribution module literal CFG$K_SNODE_POWER_SUB_RACK = 56; ! Start of Marvel Specific Snodes literal CFG$K_SNODE_OCP = 57; literal CFG$K_SNODE_SYSTEM_CABINET = 58; literal CFG$K_SNODE_VOLTAGE_REG_MODULE = 59; literal CFG$K_SNODE_CPU_CHIP = 60; literal CFG$K_SNODE_IO_EXPANSION_DRAWER = 61; literal CFG$K_SNODE_SYSTEM_DRAWER = 62; literal CFG$K_SNODE_PCI_X = 63; literal CFG$K_SNODE_IO_EXP_ASSEMBLY = 64; ! End of Marvel Specific Snodes literal CFG$K_SNODE_KEYBD_MOUSE = 65; literal CFG$K_SNODE_LAST = 66; ! Highest ! ! Lookup flags ! literal CFG$M_FIND_ANY = 0; literal CFG$M_FIND_BY_OWNER = 1; literal CFG$M_FIND_BY_TYPE = 2; literal CFG$M_FIND_BY_SUBTYPE = 4; literal CFG$M_FIND_BY_ID = 8; literal CFG$M_FIND_UNAVAILABLE = 16; ! ! Lock types ! literal CFG$K_LOCK_FOR_READ = 1; ! Just want to read the tree literal CFG$K_LOCK_FOR_UPDATE = 2; ! Want to update the tree literal CFG$K_UNLOCK_READ = 3; ! Unlock a read literal CFG$K_UNLOCK_UPDATE = 4; ! Unlock an update literal CFG$K_UNLOCK_NO_UPDATE = 5; ! Unlock an update lock with no update ! ! Magic ! literal CFG$K_NODE_VALID = 1498958919; ! ! OS types ! literal CFG$K_OS_VMS = 1; ! OS is VMS on Partition literal CFG$K_OS_OSF = 2; ! OS is OSF (aka Tru64) on Partition literal CFG$K_OS_NT = 3; ! OS is NT on Partition literal CFG$K_OS_LINUX = 4; ! OS is Linux on Partition literal CFG$K_OS_LAST = 5; ! Always last ! ! Values for text lookups ! literal CFG$K_NAME_IS_PRETTY = 256; ! Return plain text literal CFG$K_NAME_IS_FLAG = 512; ! Input is flags literal CFG$K_FLAG_NAMES = 512; ! Decode CFG$q_node_flags literal CFG$K_MEM_FLAG_NAMES = 513; ! Decode mem_flags literal CFG$K_SUBTYPE_NAMES = 2; ! Decode Subtypes literal CFG$K_TYPE_NAMES = 3; ! Decode Types literal CFG$K_OS_NAMES = 4; ! Decode OS name literal CFG$K_ERROR_TEXT = 5; ! Decode Error value literal CFG$K_RTN_NAMES = 6; ! Callback routine names literal CFG$K_LOCK_TYPES = 7; ! Lock types for calls ! ! Define the CFG_NODE structure ! literal cfg$m_node_hardware = %X'1'; literal cfg$m_node_hotswap = %X'2'; literal cfg$m_node_unavailable = %X'4'; literal cfg$m_node_hw_template = %X'8'; literal cfg$m_node_initialized = %X'10'; literal cfg$m_node_cpu_primary = %X'20'; literal cfg$m_node_in_console = %X'40'; literal cfg$m_node_pwr_down = %X'80'; literal cfg$m_node_pwr_ctrl_point = %X'100'; literal cfg$m_node_present = %X'200'; literal cfg$m_node_reassignable = %X'400'; literal cfg$m_node_hard_partitioned = %X'800'; literal cfg$m_node_disabled = %X'1000'; literal cfg$m_node_updating = %X'2000'; literal cfg$m_node_unhealthy = %X'4000'; literal cfg$m_node_attention = %X'8000'; literal cfg$m_node_ins_ext = %X'10000'; literal cfg$m_node_decon_pend = %X'20000'; literal cfg$m_node_indicted = %X'40000'; literal cfg$m_node_19_31 = %X'FFF80000'; literal cfg$m_node_32_63 = %X'FFFFFFFF00000000'; literal cfg$S_cfg_node = 128; macro cfg$b_type = 0,0,8,0 %; ! Node type macro cfg$b_subtype = 1,0,8,0 %; ! Type-specific subtype macro cfg$w_size = 2,0,16,0 %; ! Size of node macro cfg$il_hd_extension = 4,0,32,0 %; ! Header Extension offset macro cfg$r_root_overlay = 8,0,0,0 %; literal cfg$s_root_overlay = 16; ! These two quadwords pertain to all nodes except the root node macro cfg$iq_owner = 8,0,0,1 %; literal cfg$s_owner = 8; ! Software owner of node macro cfg$iq_current_owner = 16,0,0,1 %; literal cfg$s_current_owner = 8; ! Active user of the node (not used in the root node) ! These two quadwords are only defined for the root node macro cfg$il_buffer_size = 8,0,32,0 %; ! Size of entire config tree in bytes macro cfg$r_revision = 12,0,32,0 %; literal cfg$s_revision = 4; macro cfg$il_rev_full = 12,0,32,0 %; ! Structure revision of node (entire macro cfg$iw_rev_major = 12,0,16,0 %; ! Major revision macro cfg$iw_rev_minor = 14,0,16,0 %; ! Minor revision macro cfg$iq_reserved1 = 16,0,0,1 %; literal cfg$s_reserved1 = 8; ! Reserved for future use in the root node only, MBZ macro cfg$iq_cfg_id64 = 24,0,0,0 %; literal cfg$s_cfg_id64 = 8; ! Reference the entire 64-bit structure macro cfg$_CFG_NODE_ID_ROOT = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_ROOT = 8; macro cfg$v_node_id_root = 24,0,8,0 %; literal cfg$s_node_id_root = 8; macro cfg$_CFG_NODE_ID_HW_ROOT = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_HW_ROOT = 8; macro cfg$v_node_id_hw_root = 24,0,8,0 %; literal cfg$s_node_id_hw_root = 8; macro cfg$_CFG_NODE_ID_SW_ROOT = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_SW_ROOT = 8; macro cfg$v_node_id_sw_root = 24,0,8,0 %; literal cfg$s_node_id_sw_root = 8; macro cfg$_CFG_NODE_ID_TEMPLATE_ROOT = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_TEMPLATE_ROOT = 8; macro cfg$v_node_id_tmplt_root = 24,0,8,0 %; literal cfg$s_node_id_tmplt_root = 8; macro cfg$_CFG_NODE_ID_COMMUNITY = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_COMMUNITY = 8; macro cfg$v_node_id_comm_id = 24,0,16,0 %; literal cfg$s_node_id_comm_id = 16; macro cfg$_CFG_NODE_ID_PARTITION = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_PARTITION = 8; macro cfg$v_node_id_part_id = 24,0,16,0 %; literal cfg$s_node_id_part_id = 16; macro cfg$_CFG_NODE_ID_SBB = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_SBB = 8; macro cfg$v_node_id_sbb_hsbb = 28,0,8,0 %; literal cfg$s_node_id_sbb_hsbb = 8; macro cfg$v_node_id_sbb_sbb = 28,16,8,0 %; literal cfg$s_node_id_sbb_sbb = 8; macro cfg$_CFG_NODE_ID_PSEUDO = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_PSEUDO = 8; macro cfg$v_node_id_pseudo_num = 24,0,16,0 %; literal cfg$s_node_id_pseudo_num = 16; macro cfg$_CFG_NODE_ID_CPU = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_CPU = 8; macro cfg$v_node_id_cpu_cpu = 24,0,16,0 %; literal cfg$s_node_id_cpu_cpu = 16; macro cfg$v_node_id_cpu_revcnt = 24,24,8,0 %; literal cfg$s_node_id_cpu_revcnt = 8; macro cfg$v_node_id_cpu_hsbb = 28,0,8,0 %; literal cfg$s_node_id_cpu_hsbb = 8; macro cfg$v_node_id_cpu_smb = 28,8,8,0 %; literal cfg$s_node_id_cpu_smb = 8; macro cfg$v_node_id_cpu_sbb = 28,16,8,0 %; literal cfg$s_node_id_cpu_sbb = 8; macro cfg$_CFG_NODE_ID_MEM_SUB = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_MEM_SUB = 8; macro cfg$v_node_id_mem_sub_memsub = 24,0,8,0 %; literal cfg$s_node_id_mem_sub_memsub = 8; macro cfg$v_node_id_mem_sub_hsbb = 28,0,8,0 %; literal cfg$s_node_id_mem_sub_hsbb = 8; macro cfg$v_node_id_mem_sub_smb = 28,8,8,0 %; literal cfg$s_node_id_mem_sub_smb = 8; macro cfg$v_node_id_mem_sub_sbb = 28,16,8,0 %; literal cfg$s_node_id_mem_sub_sbb = 8; macro cfg$_CFG_NODE_ID_MEM_DESC = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_MEM_DESC = 8; macro cfg$v_node_id_mem_desc_memdesc = 24,0,16,0 %; literal cfg$s_node_id_mem_desc_memdesc = 16; macro cfg$v_node_id_mem_desc_memsub = 24,16,8,0 %; literal cfg$s_node_id_mem_desc_memsub = 8; macro cfg$v_node_id_mem_desc_hsbb = 28,0,8,0 %; literal cfg$s_node_id_mem_desc_hsbb = 8; macro cfg$v_node_id_mem_desc_smb = 28,8,8,0 %; literal cfg$s_node_id_mem_desc_smb = 8; macro cfg$v_node_id_mem_desc_sbb = 28,16,8,0 %; literal cfg$s_node_id_mem_desc_sbb = 8; macro cfg$_CFG_NODE_ID_MEM_CTRL = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_MEM_CTRL = 8; macro cfg$v_node_id_mem_ctrl_memctrl = 24,0,16,0 %; literal cfg$s_node_id_mem_ctrl_memctrl = 16; macro cfg$v_node_id_mem_ctrl_memsub = 24,16,8,0 %; literal cfg$s_node_id_mem_ctrl_memsub = 8; macro cfg$v_node_id_mem_ctrl_hsbb = 28,0,8,0 %; literal cfg$s_node_id_mem_ctrl_hsbb = 8; macro cfg$v_node_id_mem_ctrl_smb = 28,8,8,0 %; literal cfg$s_node_id_mem_ctrl_smb = 8; macro cfg$v_node_id_mem_ctrl_sbb = 28,16,8,0 %; literal cfg$s_node_id_mem_ctrl_sbb = 8; macro cfg$_CFG_NODE_ID_IOP = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_IOP = 8; macro cfg$v_node_id_iop_iop = 24,0,8,0 %; literal cfg$s_node_id_iop_iop = 8; macro cfg$v_node_id_iop_hsbb = 28,0,8,0 %; literal cfg$s_node_id_iop_hsbb = 8; macro cfg$v_node_id_iop_smb = 28,8,8,0 %; literal cfg$s_node_id_iop_smb = 8; macro cfg$v_node_id_iop_sbb = 28,16,8,0 %; literal cfg$s_node_id_iop_sbb = 8; macro cfg$_CFG_NODE_ID_HOSE = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_HOSE = 8; macro cfg$v_node_id_hose_hose = 24,0,8,0 %; literal cfg$s_node_id_hose_hose = 8; macro cfg$v_node_id_hose_iop = 24,8,8,0 %; literal cfg$s_node_id_hose_iop = 8; macro cfg$v_node_id_hose_hsbb = 28,0,8,0 %; literal cfg$s_node_id_hose_hsbb = 8; macro cfg$v_node_id_hose_smb = 28,8,8,0 %; literal cfg$s_node_id_hose_smb = 8; macro cfg$v_node_id_hose_sbb = 28,16,8,0 %; literal cfg$s_node_id_hose_sbb = 8; macro cfg$_CFG_NODE_ID_BUS = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_BUS = 8; macro cfg$v_node_id_bus_bus = 24,0,8,0 %; literal cfg$s_node_id_bus_bus = 8; macro cfg$v_node_id_bus_hose = 24,8,8,0 %; literal cfg$s_node_id_bus_hose = 8; macro cfg$v_node_id_bus_iop = 24,16,8,0 %; literal cfg$s_node_id_bus_iop = 8; macro cfg$v_node_id_bus_hsbb = 28,0,8,0 %; literal cfg$s_node_id_bus_hsbb = 8; macro cfg$v_node_id_bus_smb = 28,8,8,0 %; literal cfg$s_node_id_bus_smb = 8; macro cfg$v_node_id_bus_sbb = 28,16,8,0 %; literal cfg$s_node_id_bus_sbb = 8; macro cfg$_CFG_NODE_ID_IO_CTRL = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_IO_CTRL = 8; macro cfg$v_node_id_io_ctrl_ctrlr = 24,0,8,0 %; literal cfg$s_node_id_io_ctrl_ctrlr = 8; macro cfg$v_node_id_io_ctrl_bus = 24,8,8,0 %; literal cfg$s_node_id_io_ctrl_bus = 8; macro cfg$v_node_id_io_ctrl_hose = 24,16,8,0 %; literal cfg$s_node_id_io_ctrl_hose = 8; macro cfg$v_node_id_io_ctrl_iop = 24,24,8,0 %; literal cfg$s_node_id_io_ctrl_iop = 8; macro cfg$v_node_id_io_ctrl_hsbb = 28,0,8,0 %; literal cfg$s_node_id_io_ctrl_hsbb = 8; macro cfg$v_node_id_io_ctrl_smb = 28,8,8,0 %; literal cfg$s_node_id_io_ctrl_smb = 8; macro cfg$v_node_id_io_ctrl_sbb = 28,16,8,0 %; literal cfg$s_node_id_io_ctrl_sbb = 8; macro cfg$_CFG_NODE_ID_SLOT = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_SLOT = 8; macro cfg$v_node_id_slot_slot = 24,0,8,0 %; literal cfg$s_node_id_slot_slot = 8; macro cfg$v_node_id_slot_bus = 24,8,8,0 %; literal cfg$s_node_id_slot_bus = 8; macro cfg$v_node_id_slot_hose = 24,16,8,0 %; literal cfg$s_node_id_slot_hose = 8; macro cfg$v_node_id_slot_iop = 24,24,8,0 %; literal cfg$s_node_id_slot_iop = 8; macro cfg$v_node_id_slot_hsbb = 28,0,8,0 %; literal cfg$s_node_id_slot_hsbb = 8; macro cfg$v_node_id_slot_smb = 28,8,8,0 %; literal cfg$s_node_id_slot_smb = 8; macro cfg$v_node_id_slot_sbb = 28,16,8,0 %; literal cfg$s_node_id_slot_sbb = 8; macro cfg$_CFG_NODE_ID_CPU_MODULE = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_CPU_MODULE = 8; macro cfg$v_node_id_cpu_mod = 24,0,8,0 %; literal cfg$s_node_id_cpu_mod = 8; macro cfg$v_node_id_cpu_mod_hsbb = 28,0,8,0 %; literal cfg$s_node_id_cpu_mod_hsbb = 8; macro cfg$v_node_id_cpu_mod_smb = 28,8,8,0 %; literal cfg$s_node_id_cpu_mod_smb = 8; macro cfg$v_node_id_cpu_mod_sbb = 28,16,8,0 %; literal cfg$s_node_id_cpu_mod_sbb = 8; macro cfg$_CFG_NODE_ID_POWER_ENV = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_POWER_ENV = 8; macro cfg$v_node_id_power_env_pe_num = 24,0,16,0 %; literal cfg$s_node_id_power_env_pe_num = 16; macro cfg$v_node_id_power_env_cab = 24,24,8,0 %; literal cfg$s_node_id_power_env_cab = 8; macro cfg$v_node_id_power_env_hsbb = 28,0,8,0 %; literal cfg$s_node_id_power_env_hsbb = 8; macro cfg$v_node_id_power_env_smb = 28,8,8,0 %; literal cfg$s_node_id_power_env_smb = 8; macro cfg$v_node_id_power_env_sbb = 28,16,8,0 %; literal cfg$s_node_id_power_env_sbb = 8; macro cfg$v_node_id_power_env_chassis = 28,24,8,0 %; literal cfg$s_node_id_power_env_chassis = 8; macro cfg$_CFG_NODE_ID_FRU_ROOT = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_FRU_ROOT = 8; macro cfg$v_node_id_fru_root_site_loc = 24,0,8,0 %; literal cfg$s_node_id_fru_root_site_loc = 8; macro cfg$v_node_id_fru_root_cab_id = 24,8,8,0 %; literal cfg$s_node_id_fru_root_cab_id = 8; macro cfg$v_node_id_fru_root_position = 24,16,8,0 %; literal cfg$s_node_id_fru_root_position = 8; macro cfg$v_node_id_fru_root_chassis = 24,24,8,0 %; literal cfg$s_node_id_fru_root_chassis = 8; macro cfg$v_node_id_fru_root_assembly = 28,0,8,0 %; literal cfg$s_node_id_fru_root_assembly = 8; macro cfg$v_node_id_fru_root_subassem = 28,8,8,0 %; literal cfg$s_node_id_fru_root_subassem = 8; macro cfg$v_node_id_fru_root_slot = 28,16,16,0 %; literal cfg$s_node_id_fru_root_slot = 16; macro cfg$_CFG_NODE_ID_FRU_DESC = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_FRU_DESC = 8; macro cfg$v_node_id_fru_desc_site_loc = 24,0,8,0 %; literal cfg$s_node_id_fru_desc_site_loc = 8; macro cfg$v_node_id_fru_desc_cab_id = 24,8,8,0 %; literal cfg$s_node_id_fru_desc_cab_id = 8; macro cfg$v_node_id_fru_desc_position = 24,16,8,0 %; literal cfg$s_node_id_fru_desc_position = 8; macro cfg$v_node_id_fru_desc_chassis = 24,24,8,0 %; literal cfg$s_node_id_fru_desc_chassis = 8; macro cfg$v_node_id_fru_desc_assembly = 28,0,8,0 %; literal cfg$s_node_id_fru_desc_assembly = 8; macro cfg$v_node_id_fru_desc_subassem = 28,8,8,0 %; literal cfg$s_node_id_fru_desc_subassem = 8; macro cfg$v_node_id_fru_desc_slot = 28,16,16,0 %; literal cfg$s_node_id_fru_desc_slot = 16; macro cfg$_CFG_NODE_ID_SMB = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_SMB = 8; macro cfg$v_node_id_smb_hsbb = 28,0,8,0 %; literal cfg$s_node_id_smb_hsbb = 8; macro cfg$v_node_id_smb_smb = 28,8,8,0 %; literal cfg$s_node_id_smb_smb = 8; macro cfg$v_node_id_smb_sbb = 28,16,8,0 %; literal cfg$s_node_id_smb_sbb = 8; macro cfg$_CFG_NODE_ID_CAB = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_CAB = 8; macro cfg$v_node_id_cab = 24,0,8,0 %; literal cfg$s_node_id_cab = 8; macro cfg$_CFG_NODE_ID_CHASSIS = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_CHASSIS = 8; macro cfg$v_node_id_chassis = 24,0,8,0 %; literal cfg$s_node_id_chassis = 8; macro cfg$_CFG_NODE_ID_EXP_CHASSIS = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_EXP_CHASSIS = 8; macro cfg$v_node_id_exp_chassis = 24,0,8,0 %; literal cfg$s_node_id_exp_chassis = 8; macro cfg$_CFG_NODE_ID_SYS_INTER_SW = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_SYS_INTER_SW = 8; macro cfg$v_node_id_switch_id = 24,0,16,0 %; literal cfg$s_node_id_switch_id = 16; macro cfg$v_node_id_switch_hsbb = 28,0,8,0 %; literal cfg$s_node_id_switch_hsbb = 8; macro cfg$_CFG_NODE_ID_HARD_PART = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_HARD_PART = 8; macro cfg$v_node_id_hard_part = 24,0,16,0 %; literal cfg$s_node_id_hard_part = 16; macro cfg$_CFG_NODE_ID_RISER = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_RISER = 8; macro cfg$v_node_id_riser_riser = 24,0,8,0 %; literal cfg$s_node_id_riser_riser = 8; macro cfg$v_node_id_riser_iop = 24,8,8,0 %; literal cfg$s_node_id_riser_iop = 8; macro cfg$v_node_id_riser_hsbb = 28,0,8,0 %; literal cfg$s_node_id_riser_hsbb = 8; macro cfg$v_node_id_riser_smb = 28,8,8,0 %; literal cfg$s_node_id_riser_smb = 8; macro cfg$v_node_id_riser_sbb = 28,16,8,0 %; literal cfg$s_node_id_riser_sbb = 8; macro cfg$_CFG_NODE_ID_SOC = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_SOC = 8; macro cfg$v_node_id_soc_num = 24,0,16,0 %; literal cfg$s_node_id_soc_num = 16; macro cfg$v_node_id_soc_hsbb = 28,0,8,0 %; literal cfg$s_node_id_soc_hsbb = 8; macro cfg$v_node_id_soc_smb = 28,8,8,0 %; literal cfg$s_node_id_soc_smb = 8; macro cfg$v_node_id_soc_sbb = 28,16,8,0 %; literal cfg$s_node_id_soc_sbb = 8; macro cfg$_CFG_NODE_ID_SOCKET = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_SOCKET = 8; macro cfg$v_node_id_socket_id = 24,0,16,0 %; literal cfg$s_node_id_socket_id = 16; macro cfg$v_node_id_socket_hsbb = 28,0,8,0 %; literal cfg$s_node_id_socket_hsbb = 8; macro cfg$v_node_id_socket_smb = 28,8,8,0 %; literal cfg$s_node_id_socket_smb = 8; macro cfg$v_node_id_socket_sbb = 28,16,8,0 %; literal cfg$s_node_id_socket_sbb = 8; macro cfg$_CFG_NODE_ID_CORE = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_CORE = 8; macro cfg$v_node_id_core_id = 24,0,16,0 %; literal cfg$s_node_id_core_id = 16; macro cfg$v_node_id_core_hsbb = 28,0,8,0 %; literal cfg$s_node_id_core_hsbb = 8; macro cfg$v_node_id_core_smb = 28,8,8,0 %; literal cfg$s_node_id_core_smb = 8; macro cfg$v_node_id_core_sbb = 28,16,8,0 %; literal cfg$s_node_id_core_sbb = 8; macro cfg$_CFG_NODE_ID_THREAD = 24,0,0,0 %; literal cfg$S_CFG_NODE_ID_THREAD = 8; macro cfg$v_node_id_thread_id = 24,0,16,0 %; literal cfg$s_node_id_thread_id = 16; macro cfg$v_node_id_thread_hsbb = 28,0,8,0 %; literal cfg$s_node_id_thread_hsbb = 8; macro cfg$v_node_id_thread_smb = 28,8,8,0 %; literal cfg$s_node_id_thread_smb = 8; macro cfg$v_node_id_thread_sbb = 28,16,8,0 %; literal cfg$s_node_id_thread_sbb = 8; macro cfg$iq_node_flags = 32,0,0,0 %; literal cfg$s_node_flags = 8; ! flags macro cfg$v_node_hardware = 32,0,1,0 %; ! Node represents hardware macro cfg$v_node_hotswap = 32,1,1,0 %; ! Hardware can be hotswapped macro cfg$v_node_unavailable = 32,2,1,0 %; ! Hardware is not available for use macro cfg$v_node_hw_template = 32,3,1,0 %; ! Node is a template device macro cfg$v_node_initialized = 32,4,1,0 %; ! Partition is initialized macro cfg$v_node_cpu_primary = 32,5,1,0 %; ! CPU is primary macro cfg$v_node_in_console = 32,6,1,0 %; ! CPU is in console mode macro cfg$v_node_pwr_down = 32,7,1,0 %; ! Hardware is powered down macro cfg$v_node_pwr_ctrl_point = 32,8,1,0 %; ! Node controls power down (circ bkr) macro cfg$v_node_present = 32,9,1,0 %; ! Node is physically populated macro cfg$v_node_reassignable = 32,10,1,0 %; ! Node is reassignable macro cfg$v_node_hard_partitioned = 32,11,1,0 %; ! Node is hard partitioned macro cfg$v_node_disabled = 32,12,1,0 %; ! Set in HW node if disabled by SW macro cfg$v_node_updating = 32,13,1,0 %; ! Set in HW node during changes macro cfg$v_node_unhealthy = 32,14,1,0 %; ! Set in HW node if unhealthy, chk diag_flag macro cfg$v_node_attention = 32,15,1,0 %; ! Set in HW node if oper add/rem resource macro cfg$v_node_ins_ext = 32,16,1,0 %; ! Set in HW node during add/rem macro cfg$v_node_decon_pend = 32,17,1,0 %; ! Node has pending deconfigure on reboot macro cfg$v_node_indicted = 32,18,1,0 %; ! Node has been indicted at least once this boot macro cfg$v_node_19_31 = 32,19,13,0 %; literal cfg$s_node_19_31 = 13; ! Unused bits in first longword macro cfg$v_node_32_63 = 36,0,32,0 %; literal cfg$s_node_32_63 = 32; ! Unused bits in second longword macro cfg$w_rev = 40,0,16,0 %; ! Revision of this node macro cfg$w_change_counter = 42,0,16,0 %; ! Change bit macro cfg$il_rsvd1 = 44,0,32,0 %; ! Reserved macro cfg$iq_saved_owner = 48,0,0,1 %; literal cfg$s_saved_owner = 8; ! Saved Owner configuration macro cfg$iq_affinity = 56,0,0,1 %; literal cfg$s_affinity = 8; ! Affinity (performance) macro cfg$iq_parent = 64,0,0,1 %; literal cfg$s_parent = 8; ! Parent node macro cfg$iq_next_sib = 72,0,0,1 %; literal cfg$s_next_sib = 8; ! Next sibling node macro cfg$iq_prev_sib = 80,0,0,1 %; literal cfg$s_prev_sib = 8; ! Previous sibling node macro cfg$iq_child = 88,0,0,1 %; literal cfg$s_child = 8; ! Child node macro cfg$iq_fw_usage = 96,0,0,0 %; literal cfg$s_fw_usage = 8; ! FW usage macro cfg$iq_os_usage = 104,0,0,0 %; literal cfg$s_os_usage = 8; ! OS usage macro cfg$iq_fru_id = 112,0,0,0 %; literal cfg$s_fru_id = 8; ! NODE_ID_FRU_DESC structure macro cfg$v_fru_id_site_loc = 112,0,8,0 %; literal cfg$s_fru_id_site_loc = 8; macro cfg$v_fru_id_cab_id = 112,8,8,0 %; literal cfg$s_fru_id_cab_id = 8; macro cfg$v_fru_id_position = 112,16,8,0 %; literal cfg$s_fru_id_position = 8; macro cfg$v_fru_id_chassis = 112,24,8,0 %; literal cfg$s_fru_id_chassis = 8; macro cfg$v_fru_id_assembly = 116,0,8,0 %; literal cfg$s_fru_id_assembly = 8; macro cfg$v_fru_id_subassem = 116,8,8,0 %; literal cfg$s_fru_id_subassem = 8; macro cfg$v_fru_id_slot = 116,16,16,0 %; literal cfg$s_fru_id_slot = 16; macro cfg$is_checksum = 120,0,32,0 %; ! Checksum field macro cfg$il_magic = 124,0,32,0 %; ! Valid bits 'GLXY' literal CFG$K_INSTANCE_NAME_LENGTH = 128; literal CFG$K_PARTITION_NAME_LENGTH = 64; literal CFG$K_COMM_BLOCK_SIZE = 8; literal cfg$m_partitions_capable = %X'1'; literal cfg$m_partition_callbacks = %X'2'; literal cfg$m_cellular_platform = %X'4'; literal cfg$m_rootflag_3_31 = %X'FFFFFFF8'; literal cfg$S_cfg_root_node = 384; macro cfg$r_hd_root = 0,0,0,0 %; literal cfg$s_hd_root = 128; macro cfg$iq_lock = 128,0,0,0 %; literal cfg$s_lock = 8; ! Software lock macro cfg$iq_transient_level = 136,0,0,0 %; literal cfg$s_transient_level = 8; ! Update counter (in prog) macro cfg$iq_current_level = 144,0,0,0 %; literal cfg$s_current_level = 8; ! Update counter (actual) macro cfg$iq_console_req = 152,0,0,0 %; literal cfg$s_console_req = 8; ! Memory required for console macro cfg$iq_min_alloc = 160,0,0,0 %; literal cfg$s_min_alloc = 8; ! Minimum memory allocation macro cfg$iq_min_align = 168,0,0,0 %; literal cfg$s_min_align = 8; ! Memory allocation alignment macro cfg$iq_base_alloc = 176,0,0,0 %; literal cfg$s_base_alloc = 8; ! Base memory min allocation macro cfg$iq_base_align = 184,0,0,0 %; literal cfg$s_base_align = 8; ! Base memory alloc alignment macro cfg$iq_max_phys_address = 192,0,0,0 %; literal cfg$s_max_phys_address = 8; ! Largest Physical Address macro cfg$iq_mem_size = 200,0,0,0 %; literal cfg$s_mem_size = 8; ! Total current memory size macro cfg$iq_platform_type = 208,0,0,0 %; literal cfg$s_platform_type = 8; ! Type code of platform macro cfg$iq_platform_name = 216,0,0,1 %; literal cfg$s_platform_name = 8; ! Offset to name string macro cfg$iq_primary_instance = 224,0,0,1 %; literal cfg$s_primary_instance = 8; ! Handle of GALAXY Primary Partiion macro cfg$iq_first_free = 232,0,0,1 %; literal cfg$s_first_free = 8; ! First free byte of tree pool macro cfg$iq_high_limit = 240,0,0,1 %; literal cfg$s_high_limit = 8; ! High address limit for nodes macro cfg$iq_lookaside = 248,0,0,1 %; literal cfg$s_lookaside = 8; ! Lookaside list for node deletion macro cfg$il_available = 256,0,32,1 %; ! Amount of bytes in pool macro cfg$il_max_partition = 260,0,32,0 %; ! Max partitions macro cfg$iq_partitions = 264,0,0,1 %; literal cfg$s_partitions = 8; ! Offset to partition ID map macro cfg$iq_communities = 272,0,0,1 %; literal cfg$s_communities = 8; ! Offset to community ID map macro cfg$iq_bindings = 280,0,0,1 %; literal cfg$s_bindings = 8; ! Offset to array of bindings macro cfg$il_max_platform_partition = 288,0,32,0 %; ! Max part platform supports macro cfg$il_max_desc = 292,0,32,0 %; ! Max memory descriptors macro cfg$b_galaxy_id = 296,0,0,1 %; literal cfg$s_galaxy_id = 16; ! Galaxy ID macro cfg$b_galaxy_id_pad = 312,0,32,1 %; literal cfg$s_galaxy_id_pad = 4; ! Pad ID with a longword of bytes (ensures a null terminator) macro cfg$il_root_flags = 316,0,32,0 %; ! Flags in root node macro cfg$v_partitions_capable = 316,0,1,0 %; ! Console supports partitions macro cfg$v_partition_callbacks = 316,1,1,0 %; ! Console contains Galaxy/partitioning callback routines macro cfg$v_cellular_platform = 316,2,1,0 %; ! System is cell-based macro cfg$v_rootflag_3_31 = 316,3,29,0 %; literal cfg$s_rootflag_3_31 = 29; ! Unused bits macro cfg$b_complex_name = 320,0,0,1 %; literal cfg$s_complex_name = 64; ! Complex Profile Name literal cfg$S_cfg_hw_root_node = 128; macro cfg$r_hd_hw_root = 0,0,0,0 %; literal cfg$s_hd_hw_root = 128; literal cfg$S_cfg_sw_root_node = 128; macro cfg$r_hd_sw_root = 0,0,0,0 %; literal cfg$s_hd_sw_root = 128; literal cfg$S_cfg_template_root_node = 128; macro cfg$r_hd_template_root = 0,0,0,0 %; literal cfg$s_hd_template_root = 128; literal cfg$m_can_accept_shmem = %X'1'; literal cfg$m_commflag_1_31 = %X'FFFFFFFE'; literal cfg$S_cfg_community_node = 208; macro cfg$r_hd_community = 0,0,0,0 %; literal cfg$s_hd_community = 128; macro cfg$iq_gmdb = 128,0,0,0 %; literal cfg$s_gmdb = 64; ! Communication block macro cfg$iq_mcd_shared_header = 192,0,0,1 %; literal cfg$s_mcd_shared_header = 8; ! Offset from base of GCT to first shared MCD macro cfg$il_comm_flags = 200,0,32,0 %; ! Flags in community node macro cfg$v_can_accept_shmem = 200,0,1,0 %; ! Community will accept in-swapped or reassigned memory macro cfg$v_commflag_1_31 = 200,1,31,0 %; literal cfg$s_commflag_1_31 = 31; ! Unused bits macro cfg$il_community_mbz1 = 204,0,32,1 %; ! Reserved, MBZ literal cfg$m_can_accept_mem = %X'1'; literal cfg$m_can_accept_cpu = %X'2'; literal cfg$m_can_accept_io = %X'4'; literal cfg$m_tree_change_notify = %X'8'; literal cfg$m_hw_change_notify = %X'10'; literal cfg$m_error_target = %X'20'; literal cfg$m_error_pending = %X'40'; literal cfg$m_partflag_7_31 = %X'FFFFFF80'; literal cfg$S_cfg_partition_node = 296; macro cfg$r_hd_partition = 0,0,0,0 %; literal cfg$s_hd_partition = 128; macro cfg$iq_hwrpb = 128,0,0,0 %; literal cfg$s_hwrpb = 8; ! HWRPB PA macro cfg$iq_incarnation = 136,0,0,0 %; literal cfg$s_incarnation = 8; ! Partition incarnation macro cfg$iq_priority = 144,0,0,0 %; literal cfg$s_priority = 8; ! Partition priority macro cfg$il_os_type = 152,0,32,0 %; ! OS type macro cfg$il_part_flags = 156,0,32,0 %; ! Flags in partition node macro cfg$v_can_accept_mem = 156,0,1,0 %; ! Instance can accept in-swapped or reassigned memory macro cfg$v_can_accept_cpu = 156,1,1,0 %; ! Instance can accept in-swapped or reassigned CPU macro cfg$v_can_accept_io = 156,2,1,0 %; ! Instance can accept in-swapped or reassigned IO macro cfg$v_tree_change_notify = 156,3,1,0 %; ! Notify instance of configuration tree changes macro cfg$v_hw_change_notify = 156,4,1,0 %; ! Notify instance of new hardware (hot-swap) macro cfg$v_error_target = 156,5,1,0 %; ! I am the error target macro cfg$v_error_pending = 156,6,1,0 %; ! I have pending errors macro cfg$v_partflag_7_31 = 156,7,25,0 %; literal cfg$s_partflag_7_31 = 25; ! Unused bits macro cfg$b_instance_name = 160,0,0,1 %; literal cfg$s_instance_name = 128; ! Instance Name macro cfg$iq_part_mbz1 = 288,0,0,1 %; literal cfg$s_part_mbz1 = 8; ! Reserved, MBZ literal cfg$S_cfg_sbb_node = 128; macro cfg$r_hd_sbb = 0,0,0,0 %; literal cfg$s_hd_sbb = 128; literal cfg$S_cfg_pseudo_node = 128; macro cfg$r_hd_pseudo = 0,0,0,0 %; literal cfg$s_hd_pseudo = 128; literal cfg$S_cfg_cpu_node = 128; macro cfg$r_hd_cpu = 0,0,0,0 %; literal cfg$s_hd_cpu = 128; literal cfg$m_mcd_usage_console = %X'1'; literal cfg$m_mcd_usage_nvram = %X'2'; literal cfg$m_mcd_usage_shared = %X'4'; literal cfg$m_mcd_usage_fixed = %X'8'; literal cfg$m_mcd_4_31 = %X'FFFFFFF0'; literal cfg$S_cfg_mcd = 96; ! Checksum quadword macro cfg$iq_mcd_checksum = 0,0,0,0 %; literal cfg$s_mcd_checksum = 8; ! Offset from GCT base to next MCD in private or shared list ! (-1 if end of list, 0 if not on private or shared list) macro cfg$iq_mcd_usage_link = 8,0,0,1 %; literal cfg$s_mcd_usage_link = 8; ! First PFN in contiguous range of PFNs described by this MCD macro cfg$r_mcd_pfn_union = 16,0,0,0 %; literal cfg$s_mcd_pfn_union = 8; macro cfg$I_mcd_start_pfn = 16,0,0,0 %; literal cfg$s_mcd_start_pfn = 8; macro cfg$il_mcd_start_pfn = 16,0,32,0 %; ! Count of PFNs described by this MCD macro cfg$r_mcd_count_union = 24,0,0,0 %; literal cfg$s_mcd_count_union = 8; macro cfg$I_mcd_pfn_count = 24,0,0,0 %; literal cfg$s_mcd_pfn_count = 8; macro cfg$il_mcd_pfn_count = 24,0,32,0 %; ! Number of the lowest-ordered PFNs described by this MCD that have been tested macro cfg$r_mcd_tested_union = 32,0,0,0 %; literal cfg$s_mcd_tested_union = 8; macro cfg$I_mcd_tested_pfn_count = 32,0,0,0 %; literal cfg$s_mcd_tested_pfn_count = 8; macro cfg$il_mcd_tested_pfn_count = 32,0,32,0 %; ! Memory Usage Bits: ! 0 - software private ! 1 - console ! 2 - software NVRAM ! 3 - not a valid combination of bits (console NVRAM) ! 4 - software shared ! 5 - console shared ! 6 - not a valid combination of bits (shared NVRAM) ! 7 - not a valid combination of bits (console, shared, NVRAM) ! 8 - software private "FIXED" ! 9 - software console "FIXED" macro cfg$il_mcd_usage_bits = 40,0,32,0 %; ! Memory usage bits macro cfg$v_mcd_usage_console = 40,0,1,0 %; ! Console memory macro cfg$v_mcd_usage_nvram = 40,1,1,0 %; ! Software (NVRAM) macro cfg$v_mcd_usage_shared = 40,2,1,0 %; ! Shared memory macro cfg$v_mcd_usage_fixed = 40,3,1,0 %; ! "FIXED" memory, cannot be out-swapped or reassigned macro cfg$v_mcd_4_31 = 40,4,28,0 %; literal cfg$s_mcd_4_31 = 28; ! Unused bits in longword ! Physical address of bitmap, zero if none macro cfg$iq_mcd_bitmap_pa = 44,0,0,0 %; literal cfg$s_mcd_bitmap_pa = 8; ! Checksum of the lowest-ordered quadwords of bitmap. Only those ! bitmap quadwords up to test_pfn_count are included. macro cfg$iq_mcd_bitmap_checksum = 52,0,0,0 %; literal cfg$s_mcd_bitmap_checksum = 8; ! Reserved, must be zero macro cfg$iq_mcd_mbz_1 = 60,0,0,0 %; literal cfg$s_mcd_mbz_1 = 8; macro cfg$iq_mcd_mbz_2 = 68,0,0,0 %; literal cfg$s_mcd_mbz_2 = 8; macro cfg$iq_mcd_mbz_3 = 76,0,0,0 %; literal cfg$s_mcd_mbz_3 = 8; macro cfg$iq_mcd_mbz_4 = 84,0,0,0 %; literal cfg$s_mcd_mbz_4 = 8; literal cfg$S_cfg_memory_sub_node = 144; macro cfg$r_hd_memory_sub = 0,0,0,0 %; literal cfg$s_hd_memory_sub = 128; macro cfg$iq_min_pa = 128,0,0,0 %; literal cfg$s_min_pa = 8; ! Lowest possible PA in subsystem macro cfg$iq_max_pa = 136,0,0,0 %; literal cfg$s_max_pa = 8; ! Highest possible PA in subsys literal cfg$S_cfg_mem_desc_node = 224; macro cfg$r_hd_mem_desc = 0,0,0,0 %; literal cfg$s_hd_mem_desc = 128; macro cfg$r_mem_cluster_desc = 128,0,0,0 %; literal cfg$s_mem_cluster_desc = 96; literal cfg$S_cfg_memory_ctrl_node = 128; macro cfg$r_hd_memory_ctrl = 0,0,0,0 %; literal cfg$s_hd_memory_ctrl = 128; literal cfg$S_cfg_iop_node = 144; macro cfg$r_hd_iop = 0,0,0,0 %; literal cfg$s_hd_iop = 128; macro cfg$iq_min_io_pa = 128,0,0,0 %; literal cfg$s_min_io_pa = 8; ! Lowest possible PA in I/O subsystem macro cfg$iq_max_io_pa = 136,0,0,0 %; literal cfg$s_max_io_pa = 8; ! Highest possible PA in I/O subsys literal cfg$S_cfg_hose_node = 128; macro cfg$r_hd_hose = 0,0,0,0 %; literal cfg$s_hd_hose = 128; literal cfg$S_cfg_bus_node = 128; macro cfg$r_hd_bus = 0,0,0,0 %; literal cfg$s_hd_bus = 128; literal cfg$S_cfg_io_ctrl_node = 128; macro cfg$r_hd_io_ctrl = 0,0,0,0 %; literal cfg$s_hd_io_ctrl = 128; literal cfg$S_cfg_slot_node = 128; macro cfg$r_hd_slot = 0,0,0,0 %; literal cfg$s_hd_slot = 128; literal cfg$S_cfg_cpu_module_node = 128; macro cfg$r_hd_cpu_module = 0,0,0,0 %; literal cfg$s_hd_cpu_module = 128; literal cfg$S_cfg_power_env_node = 128; macro cfg$r_hd_power_env = 0,0,0,0 %; literal cfg$s_hd_power_env = 128; literal cfg$S_cfg_fru_info = 16; macro cfg$il_fru_info_diag_flag = 0,0,32,0 %; macro cfg$il_fru_info_diag_info = 4,0,32,0 %; macro cfg$b_fru_info_first_tlv = 8,0,8,0 %; ! Start of five string TLVs containing mfg, model, p/n, s/n and rev. ! You are wise to use TLV macros from Nigel Croxon (Alpha FW) to ref these. literal cfg$S_cfg_fru_root_node = 144; macro cfg$r_hd_fru_root = 0,0,0,0 %; literal cfg$s_hd_fru_root = 128; macro cfg$r_fru_root_info = 128,0,0,0 %; literal cfg$s_fru_root_info = 16; literal cfg$S_cfg_fru_desc_node = 144; macro cfg$r_hd_fru_desc = 0,0,0,0 %; literal cfg$s_hd_fru_desc = 128; macro cfg$r_fru_desc_info = 128,0,0,0 %; literal cfg$s_fru_desc_info = 16; literal cfg$S_cfg_smb_node = 128; macro cfg$r_hd_smb = 0,0,0,0 %; literal cfg$s_hd_smb = 128; literal cfg$S_cfg_cab_node = 128; macro cfg$r_hd_cab = 0,0,0,0 %; literal cfg$s_hd_cab = 128; literal cfg$S_cfg_chassis_node = 128; macro cfg$r_hd_chassis = 0,0,0,0 %; literal cfg$s_hd_chassis = 128; literal cfg$S_cfg_exp_chassis_node = 128; macro cfg$r_hd_exp_chassis = 0,0,0,0 %; literal cfg$s_hd_exp_chassis = 128; literal cfg$S_cfg_switch_node = 128; macro cfg$r_hd_switch = 0,0,0,0 %; literal cfg$s_hd_switch = 128; literal cfg$m_accept_hw_unsolicited = %X'1'; literal cfg$m_hardflag_1_31 = %X'FFFFFFFE'; literal cfg$S_cfg_hard_partition_node = 208; macro cfg$r_hd_hard_partition = 0,0,0,0 %; literal cfg$s_hd_hard_partition = 128; macro cfg$il_hard_flags = 128,0,32,0 %; ! Flags in root node macro cfg$v_accept_hw_unsolicited = 128,0,1,0 %; ! Hard partition can accept new or reassigned hardware macro cfg$v_hardflag_1_31 = 128,1,31,0 %; literal cfg$s_hardflag_1_31 = 31; ! Unused bits macro cfg$il_hard_partition_cell_cnt = 132,0,32,1 %; ! Number of Cells if Cellular macro cfg$iq_hard_partition_mbz1 = 136,0,0,1 %; literal cfg$s_hard_partition_mbz1 = 8; ! Reserved, MBZ macro cfg$b_hard_partition_name = 144,0,0,1 %; literal cfg$s_hard_partition_name = 64; ! Hard Partition Name literal cfg$S_cfg_riser_node = 128; macro cfg$r_hd_riser = 0,0,0,0 %; literal cfg$s_hd_riser = 128; literal cfg$S_cfg_soc_node = 128; macro cfg$r_hd_soc = 0,0,0,0 %; literal cfg$s_hd_soc = 128; literal cfg$S_cfg_socket_node = 128; macro cfg$r_hd_socket = 0,0,0,0 %; literal cfg$s_hd_socket = 128; literal cfg$S_cfg_core_node = 136; macro cfg$r_hd_core = 0,0,0,0 %; literal cfg$s_hd_core = 128; macro cfg$iq_core_socket_id = 128,0,0,1 %; literal cfg$s_core_socket_id = 8; ! Socket/Package ID literal cfg$S_cfg_thread_node = 144; macro cfg$r_hd_thread = 0,0,0,0 %; literal cfg$s_hd_thread = 128; macro cfg$iq_thread_socket_id = 128,0,0,1 %; literal cfg$s_thread_socket_id = 8; ! Socket/Package ID macro cfg$iq_thread_core_id = 136,0,0,1 %; literal cfg$s_thread_core_id = 8; ! Core ID ! ! TLV strings... To access them -- you need to use the tag to understand ! the data type, the length to get the number of bytes in the value. ! You are wise to use TLV macros from Nigel Croxon (Alpha FW) to ref these. ! literal cfg$S_CFG_TLV = 8; macro cfg$iw_tlv_tag = 0,0,16,0 %; ! The Type of data macro cfg$iw_tlv_length = 2,0,16,0 %; ! Its length macro cfg$b_tlv_value = 4,0,8,0 %; ! The first byte(s) in the value literal CFG$K_TLV_TAG_ISOLATIN1 = 1; literal CFG$K_TLV_TAG_QUOTED = 2; literal CFG$K_TLV_TAG_BINARY = 3; literal CFG$K_TLV_TAG_UNICODE = 4; ! ! define the diag_failure structure ! literal cfg$S_cfg_diag_failure = 4; macro cfg$b_failure_type_rev = 0,0,8,0 %; ! type nibble (0:3) and revision (4:7) macro cfg$b_failure_test = 1,0,8,0 %; ! Test macro cfg$b_failure_subtest = 2,0,8,0 %; ! Subtest code macro cfg$b_failure_error = 3,0,8,0 %; ! Error code literal CFG$K_DIAG_ST_NA = 1; ! literal CFG$K_DIAG_ST_PASSED = 1; ! literal CFG$K_DIAG_ST_RSRVD_03_31 = -4; ! ! ! System Resource Configuration Subpacket header format ! literal cfg$S_cfg_subpack = 16; macro cfg$iw_subpack_length = 0,0,16,0 %; ! Length macro cfg$iw_subpack_class = 2,0,16,0 %; ! Class macro cfg$iw_subpack_type = 4,0,16,0 %; ! Type macro cfg$iw_subpack_rev = 6,0,16,0 %; ! Revision macro cfg$il_subpack_diag_flags = 8,0,32,0 %; macro cfg$il_subpack_diag_failure = 12,0,32,0 %; ! ! Subpacket TYPE codes for CLASS 1 ( System Resource Conf Subpackets ) ! literal CFG$K_SUBPACK_UNUSED_1 = 1; ! Used to be SYSTEM_PLATFORM literal CFG$K_SUBPACK_PROCESSOR = 2; literal CFG$K_SUBPACK_MEMORY = 3; literal CFG$K_SUBPACK_SYS_BUS_BRIDGE = 4; literal CFG$K_SUBPACK_PCI_DEVICE = 5; literal CFG$K_SUBPACK_UNUSED_6 = 6; literal CFG$K_SUBPACK_CACHE = 7; literal CFG$K_SUBPACK_POWER = 8; literal CFG$K_SUBPACK_COOLING = 9; literal CFG$K_SUBPACK_SYS_INIT_LOG = 10; literal CFG$K_SUBPACK_UNUSED_11 = 11; literal CFG$K_SUBPACK_UNUSED_12 = 12; literal CFG$K_SUBPACK_VME = 13; literal CFG$K_SUBPACK_SBB = 14; literal CFG$K_SUBPACK_IOP = 15; literal CFG$K_SUBPACK_HOSE = 16; literal CFG$K_SUBPACK_BUS = 17; literal CFG$K_SUBPACK_ISA_DEVICE = 18; literal CFG$K_SUBPACK_USB_DEVICE = 19; literal CFG$K_SUBPACK_CONSOLE = 20; literal CFG$K_SUBPACK_POWER_ENVIR = 21; literal CFG$K_SUBPACK_UNUSED_22 = 22; literal CFG$K_SUBPACK_UNUSED_23 = 23; literal CFG$K_SUBPACK_UNUSED_24 = 24; literal CFG$K_SUBPACK_UNUSED_25 = 25; literal CFG$K_SUBPACK_UNUSED_26 = 26; literal CFG$K_SUBPACK_UNUSED_27 = 27; literal CFG$K_SUBPACK_UNUSED_28 = 28; literal CFG$K_SUBPACK_UNUSED_29 = 29; literal CFG$K_SUBPACK_PCI_VPD = 30; literal CFG$K_SUBPACK_SMB = 31; literal CFG$K_SUBPACK_FIBRECHANNEL = 32; literal CFG$K_SUBPACK_AGP = 33; literal CFG$K_SUBPACK_IDE = 34; literal CFG$K_SUBPACK_SCSI = 35; literal CFG$K_SUBPACK_1394 = 36; literal CFG$K_SUBPACK_SUPER_HIPPI = 37; literal CFG$K_SUBPACK_MEMORY_DIR = 38; literal CFG$K_SUBPACK_NUMA_PORT = 39; literal CFG$K_SUBPACK_NUMA_SWITCH = 40; literal CFG$K_SUBPACK_RMC = 41; literal CFG$K_SUBPACK_SENSOR = 42; literal CFG$K_SUBPACK_SYSEVT = 43; literal CFG$K_SUBPACK_LAST = 44; ! ! CPU Resource subpacket ( Class 1 Type 2 ) ! literal cfg$S_subpkt_cpu_fru = 80; macro cfg$r_cpu_sub = 0,0,0,0 %; literal cfg$s_cpu_sub = 16; macro cfg$il_cpu_id = 16,0,32,0 %; macro cfg$il_cpu_family = 20,0,32,0 %; macro cfg$iq_cpu_state = 24,0,0,0 %; literal cfg$s_cpu_state = 8; macro cfg$iq_cpu_ovms_palcode_rev = 32,0,0,0 %; literal cfg$s_cpu_ovms_palcode_rev = 8; macro cfg$iq_cpu_dunix_palcode_rev = 40,0,0,0 %; literal cfg$s_cpu_dunix_palcode_rev = 8; macro cfg$iq_cpu_wnt_palcode_rev = 48,0,0,0 %; literal cfg$s_cpu_wnt_palcode_rev = 8; macro cfg$iq_cpu_alpha_type = 56,0,0,0 %; literal cfg$s_cpu_alpha_type = 8; macro cfg$iq_cpu_variation = 64,0,0,0 %; literal cfg$s_cpu_variation = 8; macro cfg$r_cpu_first_tlv = 72,0,0,0 %; literal cfg$s_cpu_first_tlv = 8; ! Three TLV's exist: ! You are wise to use TLV macros from Nigel Croxon (Alpha FW) to ref these. ! cpu_manufacturer CFG_TLV; ! cpu_serial_number CFG_TLV; ! cpu_revision_level CFG_TLV; ! ! MEMORY Resouce subpacket ( Class 1 Type 3) ! literal cfg$S_subpkt_mem_fru = 32; macro cfg$r_mem_sub = 0,0,0,0 %; literal cfg$s_mem_sub = 16; macro cfg$iq_mem_id = 16,0,0,0 %; literal cfg$s_mem_id = 8; macro cfg$il_mem_register_count = 28,0,32,0 %; ! ! BUSBRIDGE Resouce subpacket ( Class 1 Type 4) ! literal cfg$S_subpkt_bridge_fru = 32; macro cfg$r_bridge_sub = 0,0,0,0 %; literal cfg$s_bridge_sub = 16; macro cfg$iw_bridge_level = 16,0,16,0 %; macro cfg$iw_bridge_type = 18,0,16,0 %; macro cfg$il_bridge_register_count = 20,0,32,0 %; macro cfg$iq_bridge_physical_addr = 24,0,0,0 %; literal cfg$s_bridge_physical_addr = 8; literal CFG$K_BRIDGE_LVL_PRIMARY = 1; literal CFG$K_BRIDGE_LVL_SECONDARY = 2; literal CFG$K_BRIDGE_LVL_TERTIARY = 3; literal CFG$K_BRIDGE_TYPE_HOSE = 1; literal CFG$K_BRIDGE_TYPE_PCI = 2; literal CFG$K_BRIDGE_TYPE_XMI = 3; literal CFG$K_BRIDGE_TYPE_FBUS = 4; literal CFG$K_BRIDGE_TYPE_VME = 5; literal CFG$K_BRIDGE_TYPE_ISA = 6; literal CFG$K_BRIDGE_TYPE_AGP = 7; literal CFG$K_BRIDGE_TYPE_LAST = 8; ! ! PCI Resouce subpacket ( Class 1 Type 5) ! literal cfg$S_subpkt_pci_fru = 88; macro cfg$r_pci_sub = 0,0,0,0 %; literal cfg$s_pci_sub = 16; macro cfg$iq_pci_config_addr = 16,0,0,0 %; literal cfg$s_pci_config_addr = 8; macro cfg$iq_pci_config_head0 = 24,0,0,0 %; literal cfg$s_pci_config_head0 = 8; macro cfg$iq_pci_config_head1 = 32,0,0,0 %; literal cfg$s_pci_config_head1 = 8; macro cfg$iq_pci_config_head2 = 40,0,0,0 %; literal cfg$s_pci_config_head2 = 8; macro cfg$iq_pci_config_head3 = 48,0,0,0 %; literal cfg$s_pci_config_head3 = 8; macro cfg$iq_pci_config_head4 = 56,0,0,0 %; literal cfg$s_pci_config_head4 = 8; macro cfg$iq_pci_config_head5 = 64,0,0,0 %; literal cfg$s_pci_config_head5 = 8; macro cfg$iq_pci_config_head6 = 72,0,0,0 %; literal cfg$s_pci_config_head6 = 8; macro cfg$iq_pci_config_head7 = 80,0,0,0 %; literal cfg$s_pci_config_head7 = 8; ! ! Cache Resouce subpacket ( Class 1 Type 7 ) ! literal cfg$S_subpkt_cache_fru = 32; macro cfg$r_cache_sub = 0,0,0,0 %; literal cfg$s_cache_sub = 16; macro cfg$iw_cache_level = 16,0,16,0 %; macro cfg$iw_cache_speed = 18,0,16,0 %; macro cfg$iw_cache_size = 20,0,16,0 %; macro cfg$iw_cache_size_avail = 22,0,16,0 %; macro cfg$iw_cache_wp = 24,0,16,0 %; macro cfg$iw_cache_ec = 26,0,16,0 %; macro cfg$iw_cache_type = 28,0,16,0 %; macro cfg$iw_cache_state = 30,0,16,0 %; ! ! CACHE types ! literal CFG$K_CACHE_OTHER = 1; ! literal CFG$K_CACHE_UNKNOWN = 2; ! literal CFG$K_CACHE_LVL_PRIMARY = 3; ! 1st level literal CFG$K_CACHE_LVL_SECONDARY = 4; ! 2nd level literal CFG$K_CACHE_LVL_TERTIARY = 5; ! 3rd level literal CFG$K_CACHE_LAST = 6; ! literal CFG$K_CACHE_WP_WRITEBACK = 3; literal CFG$K_CACHE_WP_WRITETHROUGH = 4; literal CFG$K_CACHE_WP_LATEWRITE = 5; literal CFG$K_CACHE_EC_NONE = 3; literal CFG$K_CACHE_EC_PARITY = 4; literal CFG$K_CACHE_EC_SINGLEBITECC = 5; literal CFG$K_CACHE_EC_MULTIBITECC = 6; literal CFG$K_CACHE_TYPE_INSTRUCTION = 3; literal CFG$K_CACHE_TYPE_DATA = 4; literal CFG$K_CACHE_TYPE_UNIFIED = 5; literal CFG$K_CACHE_STAT_ENABLED = 3; literal CFG$K_CACHE_STAT_DISABLED = 4; literal CFG$K_CACHE_STAT_NOTAPPLY = 5; ! ! Power Resouce subpacket ( Class 1 Type 8 ) ! literal cfg$S_subpkt_power_fru = 40; macro cfg$r_power_sub = 0,0,0,0 %; literal cfg$s_power_sub = 16; macro cfg$il_power_fru_count = 16,0,32,0 %; macro cfg$il_power_fru_reserved = 20,0,32,0 %; macro cfg$iq_power_fru_offset = 24,0,0,0 %; literal cfg$s_power_fru_offset = 8; macro cfg$iw_power_type = 32,0,16,0 %; macro cfg$iw_power_id = 34,0,16,0 %; macro cfg$il_power_status = 36,0,32,0 %; literal CFG$K_POWER_PS_TYPE_DC = 1; literal CFG$K_POWER_PS_TYPE_AC = 2; literal CFG$K_POWER_PS_TYPE_GNDCUR = 3; literal CFG$K_POWER_PS_TYPE_BBU = 4; literal CFG$K_POWER_PS_TYPE_UPS = 5; ! ! Cooling Resouce subpacket ( Class 1 Type 9 ) ! literal cfg$S_subpkt_cooling_fru = 40; macro cfg$r_cooling_sub = 0,0,0,0 %; literal cfg$s_cooling_sub = 16; macro cfg$il_cooling_fru_count = 16,0,32,0 %; macro cfg$il_cooling_fru_reserved = 20,0,32,0 %; macro cfg$iq_cooling_fru_offset = 24,0,0,0 %; literal cfg$s_cooling_fru_offset = 8; macro cfg$iw_cooling_type = 32,0,16,0 %; macro cfg$iw_cooling_id = 34,0,16,0 %; macro cfg$il_cooling_status = 36,0,32,0 %; literal CFG$K_COOLING_COOL_TYPE_FAN = 1; literal CFG$K_COOLING_COOL_TYPE_TEMP = 2; ! ! Bus Resouce subpacket ( Class 1 Type 17 ) ! literal cfg$S_subpkt_bus_fru = 32; macro cfg$r_bus_sub = 0,0,0,0 %; literal cfg$s_bus_sub = 16; macro cfg$iq_bus_id = 16,0,0,0 %; literal cfg$s_bus_id = 8; macro cfg$il_bus_register_count = 28,0,32,0 %; ! ! CSL Resouce subpacket ( Class 1 Type 20 ) ! literal cfg$S_subpkt_csl_fru = 32; macro cfg$r_csl_sub = 0,0,0,0 %; literal cfg$s_csl_sub = 16; macro cfg$il_csl_reset_reason = 16,0,32,0 %; macro cfg$il_csl_ev_count = 20,0,32,0 %; macro cfg$r_csl_first_tlv = 24,0,0,0 %; literal cfg$s_csl_first_tlv = 8; ! Four TLV's exist: ! You are wise to use TLV macros from Nigel Croxon (Alpha FW) to ref these. ! csl_srm_part_number CFG_TLV; ! csl_srm_rev CFG_TLV; ! csl_alphabios_part_number CFG_TLV; ! csl_alphabios_rev CFG_TLV; literal CFG$K_CSL_UNKNOWN_RESET = 0; literal CFG$K_CSL_SOFT_RESET = 2; literal CFG$K_CSL_HARD_RESET = 4; literal CFG$K_CSL_OCP_RESET = 8; literal CFG$K_CSL_REMOTE_RESET = 16; ! ! PCI VPD Resouce subpacket ( Class 1 Type 30 ) ! literal cfg$S_subpkt_vpd_fru = 80; macro cfg$r_vpd_sub = 0,0,0,0 %; literal cfg$s_vpd_sub = 16; macro cfg$iq_vpd_load_id = 16,0,0,0 %; literal cfg$s_vpd_load_id = 8; macro cfg$iq_vpd_rom_level = 24,0,0,0 %; literal cfg$s_vpd_rom_level = 8; macro cfg$iq_vpd_rom_rev = 32,0,0,0 %; literal cfg$s_vpd_rom_rev = 8; macro cfg$iq_vpd_net_addr = 40,0,0,0 %; literal cfg$s_vpd_net_addr = 8; macro cfg$iq_vpd_dev_driv_level = 48,0,0,0 %; literal cfg$s_vpd_dev_driv_level = 8; macro cfg$iq_vpd_diag_level = 56,0,0,0 %; literal cfg$s_vpd_diag_level = 8; macro cfg$iq_vpd_load_ucode_level = 64,0,0,0 %; literal cfg$s_vpd_load_ucode_level = 8; macro cfg$iq_vpd_bin_func_num = 72,0,0,0 %; literal cfg$s_vpd_bin_func_num = 8; ! ! SMB Resouce subpacket ( Class 1 Type 31 ) ! literal cfg$S_subpkt_smb_fru = 32; macro cfg$r_smb_sub = 0,0,0,0 %; literal cfg$s_smb_sub = 16; macro cfg$iq_smb_id = 16,0,0,0 %; literal cfg$s_smb_id = 8; macro cfg$il_smb_register_count = 28,0,32,0 %; ! ! RMC Resouce subpacket ( Class 1 Type 41 ) ! literal cfg$S_subpkt_rmc_fru = 32; macro cfg$r_rmc_sub = 0,0,0,0 %; literal cfg$s_rmc_sub = 16; macro cfg$iq_rmc_id = 16,0,0,0 %; literal cfg$s_rmc_id = 8; macro cfg$il_rmc_pic_hw_rev = 24,0,32,0 %; macro cfg$il_rmc_pic_fw_rev = 28,0,32,0 %; ! ! SENSOR Resouce subpacket ( Class 1 Type 42 ) ! literal cfg$m_sensor_prop_status = %X'1'; literal cfg$m_sensor_prop_value = %X'2'; literal cfg$m_sensor_prop_writeable = %X'4'; literal cfg$m_sensor_prop_bitfield = %X'8'; literal cfg$m_sensor_prop_fill = %X'FFFFFFF0'; literal cfg$S_subpkt_sensor_fru = 48; macro cfg$r_sensor_sub = 0,0,0,0 %; literal cfg$s_sensor_sub = 16; macro cfg$il_sensor_fru_count = 16,0,32,0 %; macro cfg$il_sensor_fru_reserved = 20,0,32,0 %; macro cfg$iq_sensor_fru_offset = 24,0,0,0 %; literal cfg$s_sensor_fru_offset = 8; macro cfg$iq_sensor_console_id = 32,0,0,0 %; literal cfg$s_sensor_console_id = 8; macro cfg$il_sensor_console_id = 32,0,32,0 %; macro cfg$il_sensor_bitfield = 36,0,32,0 %; macro cfg$il_sensor_class = 40,0,32,0 %; macro cfg$il_sensor_prop = 44,0,32,0 %; ! Sensor properties macro cfg$v_sensor_prop_status = 44,0,1,0 %; macro cfg$v_sensor_prop_value = 44,1,1,0 %; macro cfg$v_sensor_prop_writeable = 44,2,1,0 %; macro cfg$v_sensor_prop_bitfield = 44,3,1,0 %; literal CFG$K_SENSOR_CLASS_FAN = 1; literal CFG$K_SENSOR_CLASS_TEMPERATURE = 2; literal CFG$K_SENSOR_CLASS_AC = 3; literal CFG$K_SENSOR_CLASS_DC = 4; literal CFG$K_SENSOR_CLASS_BATTERY = 5; ! ! Define the header extension structure. Offset to by hd_extension ! in the common header. If zero, no extended header information is ! present for the node. ! literal cfg$S_cfg_hd_ext = 24; macro cfg$il_hd_ext_fru_count = 0,0,32,0 %; macro cfg$il_reserved_1 = 4,0,32,0 %; macro cfg$iq_hd_ext_fru = 8,0,0,1 %; literal cfg$s_hd_ext_fru = 8; macro cfg$il_hd_ext_subpkt_count = 16,0,32,0 %; macro cfg$il_hd_ext_subpkt_offset = 20,0,32,0 %; literal CFG$K_NODE_HARDWARE = 1; literal CFG$K_NODE_HOTSWAP = 2; literal CFG$K_NODE_UNAVAILABLE = 4; literal CFG$K_NODE_HW_TEMPLATE = 8; literal CFG$K_NODE_INITIALIZED = 16; literal CFG$K_NODE_CPU_PRIMARY = 32; literal CFG$K_NODE_IN_CONSOLE = 64; literal CFG$K_NODE_PWR_DOWN = 128; literal CFG$K_NODE_PWR_CTRL_POINT = 256; literal CFG$K_NODE_PRESENT = 512; literal CFG$K_NODE_REASSIGNABLE = 1024; literal CFG$K_NODE_HARD_PARTITIONED = 2048; literal CFG$K_NODE_DISABLED = 4096; literal CFG$K_NODE_UPDATING = 8192; literal CFG$K_NODE_UNHEALTHY = 16384; literal CFG$K_NODE_ATTENTION = 32768; literal CFG$K_NODE_INS_EXT = 65536; literal CFG$K_NODE_DECON_PEND = 131072; literal CFG$K_NODE_INDICTED = 262144; literal CFG$K_NODE_RSRVD_19_31 = -524288; literal CFG$K_NODE_RSRVD_32_63 = -1; !*** MODULE $CHFCTXDEF *** ! ! CONDITION HANDLING FACILITY INTERNAL CONTEXT OFFSETS ! ! This module defines the layout of the Condition Handling Facility ! internal context on the stack (in the mode of the exception). ! This context is created by the VMS hardware exception handling ! facility and the RTL LIB$SIGNAL/LIB$STOP routines. This context ! is used by the Condition Handling Facility as well as DEBUG. ! ! Note that this structure definition only provides offsets for a ! small portion of the whole exception context. The whole exception ! context contains: ! ! Internal context area (structure defined here) ! ALPHA mechanism array ! Signal array (which includes the ALPHA exception record) ! Exception frame generated by PAL ! ! The mechanism array can't be embedded here because it is subject to ! change, and there is no easy way to "include" the mechanism array ! definition into this module. ! ! The signal array is variable length, depending on the exception. ! literal CHFCTX$M_SIGNAL = %X'1'; literal CHFCTX$M_STOP = %X'2'; literal CHFCTX$M_FPREGS_VALID = %X'4'; literal CHFCTX$M_UNWIND_AST = %X'8'; literal CHFCTX$M_REINVOKABLE = %X'10'; literal CHFCTX$M_FPREGS_READY = %X'20'; literal CHFCTX$M_SYS_UNWIND = %X'40'; literal CHFCTX$M_GOTO_UNWIND = %X'80'; literal CHFCTX$M_EXIT_UNWIND = %X'100'; literal CHFCTX$M_RECALL_TARGET = %X'200'; literal CHFCTX$M_REENABLE_ASTS = %X'400'; literal CHFCTX$M_CALL_CLRAST = %X'800'; literal CHFCTX$M_SIG64 = %X'1000'; literal CHFCTX$M_TARGET_IS_REGFRAME = %X'2000'; literal CHFCTX$M_SET_STACK_TO_BASE = %X'4000'; literal CHFCTX$M_SOFTWARE_GENERATED = %X'8000'; literal CHFCTX$M_BADSTACK = %X'10000'; literal CHFCTX$M_REBUILT = %X'20000'; literal CHFCTX$K_LENGTH = 112; ! Length of CHFCTX literal CHFCTX$C_LENGTH = 112; ! Length of CHFCTX literal CHFCTX$C_LENGTH_V731 = 80; ! Length of V7.3-1 CHFCTX literal CHFCTX$S_CHFCTXDEF = 112; literal CHFCTX$S_CHFCTX = 112; macro CHFCTX$Q_LINKAGE_PTR = 0,0,0,0 %; literal CHFCTX$S_LINKAGE_PTR = 8; ! Linkage section pointer macro CHFCTX$Q_SIGARGLST = 8,0,0,0 %; literal CHFCTX$S_SIGARGLST = 8; ! Address of Signal array macro CHFCTX$Q_MCHARGLST = 16,0,0,0 %; literal CHFCTX$S_MCHARGLST = 8; ! Address of mechanism array macro CHFCTX$Q_EXPT_ADDR = 24,0,0,0 %; literal CHFCTX$S_EXPT_ADDR = 8; ! Address of exception frame macro CHFCTX$Q_EXPT_FP = 32,0,0,0 %; literal CHFCTX$S_EXPT_FP = 8; ! Exception FP macro CHFCTX$Q_UNWIND_SP = 40,0,0,0 %; literal CHFCTX$S_UNWIND_SP = 8; ! SP during unwind macro CHFCTX$Q_REINVOKABLE_FP = 48,0,0,0 %; literal CHFCTX$S_REINVOKABLE_FP = 8; ! End of reinvokable algorithm macro CHFCTX$Q_UNWIND_TARGET = 56,0,0,0 %; literal CHFCTX$S_UNWIND_TARGET = 8; ! Unwind target (FP) macro CHFCTX$Q_UNWIND_TARGET_PC = 64,0,0,0 %; literal CHFCTX$S_UNWIND_TARGET_PC = 8; ! Unwind target PC macro CHFCTX$Q_UNWIND_TARGET_INVO = 72,0,0,0 %; literal CHFCTX$S_UNWIND_TARGET_INVO = 8; ! Unwind target INVO macro CHFCTX$L_BYTECNT = 80,0,32,0 %; ! Byte count of exception context macro CHFCTX$L_SIG_ARGS = 84,0,32,0 %; ! Original signal array count macro CHFCTX$L_FLAGS = 88,0,32,0 %; ! Internal flags macro CHFCTX$V_SIGNAL = 88,0,1,0 %; ! Signal flag macro CHFCTX$V_STOP = 88,1,1,0 %; ! Stop flag macro CHFCTX$V_FPREGS_VALID = 88,2,1,0 %; ! Floating Point Registers valid macro CHFCTX$V_UNWIND_AST = 88,3,1,0 %; ! Unwinding from AST macro CHFCTX$V_REINVOKABLE = 88,4,1,0 %; ! Reinvokable algorithm in progress macro CHFCTX$V_FPREGS_READY = 88,5,1,0 %; ! Floating Point Registers ready macro CHFCTX$V_SYS_UNWIND = 88,6,1,0 %; ! Unwind by depth macro CHFCTX$V_GOTO_UNWIND = 88,7,1,0 %; ! GOTO unwind in progress macro CHFCTX$V_EXIT_UNWIND = 88,8,1,0 %; ! Exit unwind in progress macro CHFCTX$V_RECALL_TARGET = 88,9,1,0 %; ! Re-call target invocation's handler macro CHFCTX$V_REENABLE_ASTS = 88,10,1,0 %; ! ASTs were disabled during unwind macro CHFCTX$V_CALL_CLRAST = 88,11,1,0 %; ! Call CLRAST in CHF_RESTORE_REGS macro CHFCTX$V_SIG64 = 88,12,1,0 %; ! This is a 64-bit signal macro CHFCTX$V_TARGET_IS_REGFRAME = 88,13,1,0 %; ! Target frame of Unwind is register frame macro CHFCTX$V_SET_STACK_TO_BASE = 88,14,1,0 %; ! Reset inner mode stack to base macro CHFCTX$V_SOFTWARE_GENERATED = 88,15,1,0 %; ! Software Generated exception macro CHFCTX$V_BADSTACK = 88,16,1,0 %; ! Resumed in outer mode at BADSTACK macro CHFCTX$V_REBUILT = 88,17,1,0 %; ! This CHFCTX was converted from pre-V7.3-2 size macro CHFCTX$L_FINALSTS = 88,0,32,0 %; ! Final status macro CHFCTX$L_MSGPTR = 92,0,32,1 %; ! Address of $EXCMSG error msg macro CHFCTX$Q_UNWIND_DEPTH = 96,0,0,0 %; literal CHFCTX$S_UNWIND_DEPTH = 8; ! IA64 unwind depth macro CHFCTX$Q_SPARE1 = 104,0,0,0 %; literal CHFCTX$S_SPARE1 = 8; ! Structure length must be a multiple of 16 bytes !*** MODULE $CHPCTLDEF *** ! ! CHeck Protection ConTroL block definition. This block contains the ! information concerning the type of access check being made. ! literal CHPCTL$M_READ = %X'1'; literal CHPCTL$M_WRITE = %X'2'; literal CHPCTL$M_USEREADALL = %X'4'; literal CHPCTL$M_NOAUDIT = %X'8'; literal CHPCTL$M_NOFAILAUD = %X'10'; literal CHPCTL$M_NOSUCCAUD = %X'20'; literal CHPCTL$M_DELETE = %X'40'; literal CHPCTL$M_MANDATORY = %X'80'; literal CHPCTL$M_FLUSH = %X'100'; literal CHPCTL$M_CREATE = %X'200'; literal CHPCTL$M_INTERNAL = %X'400'; literal CHPCTL$M_SERVER = %X'800'; literal CHPCTL$K_LENGTH = 32; literal CHPCTL$C_LENGTH = 32; literal CHPCTL$S_CHPCTL = 32; macro CHPCTL$L_ACCESS = 0,0,32,0 %; ! type of access desired macro CHPCTL$L_FLAGS = 4,0,32,0 %; ! control flags macro CHPCTL$V_READ = 4,0,1,0 %; ! READ access macro CHPCTL$V_WRITE = 4,1,1,0 %; ! WRITE access macro CHPCTL$V_USEREADALL = 4,2,1,0 %; ! try for READ access via READALL macro CHPCTL$V_NOAUDIT = 4,3,1,0 %; ! do not perform any auditing macro CHPCTL$V_NOFAILAUD = 4,4,1,0 %; ! do not perform failed access audit macro CHPCTL$V_NOSUCCAUD = 4,5,1,0 %; ! do not perform successful access audit macro CHPCTL$V_DELETE = 4,6,1,0 %; ! perform audit as DELETE event macro CHPCTL$V_MANDATORY = 4,7,1,0 %; ! perform mandatory audit macro CHPCTL$V_FLUSH = 4,8,1,0 %; ! force buffer flush in audit server macro CHPCTL$V_CREATE = 4,9,1,0 %; ! perform audit as CREATE event macro CHPCTL$V_INTERNAL = 4,10,1,0 %; ! audit on behalf of VMS TCB macro CHPCTL$V_SERVER = 4,11,1,0 %; ! audit originates in TCB server process macro CHPCTL$L_MODE = 8,0,32,0 %; ! access mode of request macro CHPCTL$L_AUDIT_LIST = 12,0,32,1 %; ! address of associated auditing item list macro CHPCTL$L_DEACCESS_KEY = 16,0,32,1 %; ! deaccess audit object handle macro CHPCTL$L_MESSAGE = 20,0,32,0 %; ! associated auditing message code macro CHPCTL$L_ARB = 24,0,32,1 %; ! corresponding ARB macro CHPCTL$L_PSB = 24,0,32,1 %; ! corresponding PSB macro CHPCTL$L_ORB = 28,0,32,1 %; ! corresponding ORB !*** MODULE $CHPRETDEF *** ! + ! ! CHeck Protection ConTroL RETurn argument block. This block contains ! the information needed to return arguments from the protection check. ! ! - literal CHPRET$M_ACMODE = %X'1'; literal CHPRET$M_MAC = %X'2'; literal CHPRET$M_DAC = %X'4'; literal CHPRET$M_MATCHED_ACE = %X'8'; literal CHPRET$M_SOGW = %X'10'; literal CHPRET$M_ACL_KEYID = %X'20'; literal CHPRET$M_IVBUFLEN = %X'40'; literal CHPRET$K_LENGTH = 44; literal CHPRET$C_LENGTH = 44; literal CHPRET$S_CHPRET = 44; macro CHPRET$L_AUDITLEN = 0,0,32,0 %; ! Size of the audit ACE buffer macro CHPRET$L_AUDIT = 4,0,32,1 %; ! Address of the audit ACE buffer macro CHPRET$L_AUDITRET = 8,0,32,1 %; ! Address of word to get ACE length macro CHPRET$L_ALARMLEN = 12,0,32,0 %; ! Size of the alarm ACE buffer macro CHPRET$L_ALARM = 16,0,32,1 %; ! Address of the alarm ACE buffer macro CHPRET$L_ALARMRET = 20,0,32,1 %; ! Address of word to get ACE length macro CHPRET$L_MATCHED_ACELEN = 24,0,32,0 %; ! Size of the matched ACE buffer macro CHPRET$L_MATCHED_ACE = 28,0,32,1 %; ! Address of the matched ACE buffer macro CHPRET$L_MATCHED_ACERET = 32,0,32,1 %; ! Address of word to get ACE length macro CHPRET$L_PRIVS_USED = 36,0,32,1 %; ! Address of longword to get privileges used macro CHPRET$L_PROGRESS = 40,0,32,0 %; ! Protection check progress fl macro CHPRET$V_ACMODE = 40,0,1,0 %; ! Access mode check failed macro CHPRET$V_MAC = 40,1,1,0 %; ! MAC check failed macro CHPRET$V_DAC = 40,2,1,0 %; ! DAC check failed macro CHPRET$V_MATCHED_ACE = 40,3,1,0 %; ! matching ACE was located macro CHPRET$V_SOGW = 40,4,1,0 %; ! SOGW check was performed macro CHPRET$V_ACL_KEYID = 40,5,1,0 %; ! An identifier ACE was found in the ACL macro CHPRET$V_IVBUFLEN = 40,6,1,0 %; ! CHPRET info for auditing is incomplete !*** MODULE $CIAOLDDEF *** ! + ! CIAOLD - Compound Intrusion Analysis block ! ! Contains information about suspected and known intruders ! - literal CIAOLD$K_TERMINAL = 1; ! Unknown user at terminal literal CIAOLD$K_TERM_USER = 2; ! Known username at terminal literal CIAOLD$K_NETWORK = 3; ! Network source literal CIAOLD$K_USERNAME = 4; ! Username of parent process literal CIAOLD$M_INTRUDER = %X'1'; literal CIAOLD$K_LENGTH = 160; ! Length of CIAOLD block literal CIAOLD$C_LENGTH = 160; ! Length of CIAOLD block literal CIAOLD$S_CIAOLDDEF = 160; literal CIAOLD$S_CIAOLD = 160; macro CIAOLD$L_FLINK = 0,0,32,1 %; ! Forward link to next block macro CIAOLD$L_BLINK = 4,0,32,1 %; ! Backward link to previous block macro CIAOLD$W_SIZE = 8,0,16,0 %; ! Size of block macro CIAOLD$B_TYPE = 10,0,8,0 %; ! Structure type macro CIAOLD$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype ! Source of breakin attempt macro CIAOLD$L_FLAGS = 12,0,32,0 %; ! Breakin type flags macro CIAOLD$V_INTRUDER = 12,0,1,0 %; ! Entry is an intruder macro CIAOLD$L_COUNT = 16,0,32,0 %; ! Count of attempts macro CIAOLD$L_FILL_1 = 20,0,32,0 %; ! Make TIME naturally aligned macro CIAOLD$Q_TIME = 24,0,0,0 %; literal CIAOLD$S_TIME = 8; ! Expiration time of entry macro CIAOLD$T_DATA = 32,0,0,0 %; literal CIAOLD$S_DATA = 128; ! Data area !*** MODULE $CIBHANDEF *** ! + ! CIBHAN - CI BUFFER HANDLE FORMAT ! - literal CIBHAN$K_LENGTH = 12; ! LENGTH OF CI BUFFER HANDLE literal CIBHAN$C_LENGTH = 12; ! LENGTH OF CI BUFFER HANDLE literal CIBHAN$S_CIBHANDEF = 12; literal CIBHAN$S_CIBHAN = 12; macro CIBHAN$L_BOFF = 0,0,32,0 %; ! BYTE OFFSET IN LOCAL BUFFER macro CIBHAN$L_BNAME = 4,0,32,0 %; ! NAME OF LOCAL BUFFER macro CIBHAN$L_RCONID = 8,0,32,0 %; ! REMOTE CONNECTION ID !*** MODULE $CIFQDTDEF *** ! + ! CIFQDT - CI FREE MESSAGE/DATAGRAM QUEUE DESCRIPTOR TABLE ! ! THIS DATA STRUCTURE AND THE QUEUES IT HAS HEADERS FOR MAY BE ! SHARED AMONG ALL CI'S ON THE SYSTEM. ! - literal CIFQDT$K_LENGTH = 32; ! LENGTH OF CI FQDT literal CIFQDT$C_LENGTH = 32; ! LENGTH OF CI FQDT literal CIFQDT$S_CIFQDTDEF = 32; literal CIFQDT$S_CIFQDT = 32; macro CIFQDT$W_DGSIZ = 0,0,16,0 %; ! DATAGRAM SIZE (INCL PORT HEADER) macro CIFQDT$W_MSGSIZ = 2,0,16,0 %; ! MESSAGE SIZE (INCL PORT HEADER) macro CIFQDT$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro CIFQDT$B_TYPE = 10,0,8,0 %; ! CI STRUCTURE TYPE macro CIFQDT$B_SUBTYP = 11,0,8,0 %; ! CI STRUCT SUBTYPE FOR CI FQDT macro CIFQDT$W_DGCNT = 12,0,16,0 %; ! SUM OF INITL DG CREDITS FOR ALL CONNX macro CIFQDT$W_MSGCNT = 14,0,16,0 %; ! SUM OF INITL MSG CREDITS FOR ALL CONNX macro CIFQDT$L_DGFL = 16,0,32,1 %; ! DG FREE QUEUE FWD LINK macro CIFQDT$L_DGBL = 20,0,32,1 %; ! DG FREE QUEUE BACK LINK macro CIFQDT$L_MSGFL = 24,0,32,1 %; ! MSG FREE QUEUE FWD LINK macro CIFQDT$L_MSGBL = 28,0,32,1 %; ! MSG FREE QUEUE BACK LINK !*** MODULE $CLASSDEF *** ! ! CLASSification data block definitions ! literal CLASS$S_CLASS = 40; macro CLASS$L_FLINK = 0,0,32,1 %; ! Standard listhead forward link macro CLASS$L_BLINK = 4,0,32,1 %; ! Standard listhead backward link macro CLASS$W_SIZE = 8,0,16,0 %; ! Standard structure size, in bytes macro CLASS$B_TYPE = 10,0,8,0 %; ! Standard type code for CLASS (DYN$C_SECURITY) macro CLASS$B_SUBTYPE = 11,0,8,0 %; ! Standard subtype code (DYN$C_SECURITY_CLASS) macro CLASS$L_DEBUG_FLINK = 12,0,32,1 %; ! Forward link to CLASS (DEBUG) macro CLASS$L_DEBUG_BLINK = 16,0,32,1 %; ! Backward link to CLASS (DEBUG) macro CLASS$L_DEBUG_PID = 20,0,32,0 %; ! PID of process that allocated this CLASS (DEBUG) macro CLASS$L_REFCOUNT = 24,0,32,0 %; ! Number of attached execution contexts to this CLASS macro CLASS$AR_MINCLASS = 28,0,32,1 %; ! Pointer to minimum classification data macro CLASS$AR_MAXCLASS = 32,0,32,1 %; ! Pointer to maximum classification data macro CLASS$AR_CLASS = 36,0,32,1 %; ! Pointer to active classification data ! ! The CLS classification data structures are appended to this data block as needed ! literal CLASS$K_LENGTH = 40; ! Length of CLASS$ structure !*** MODULE $CLONEVADEF *** ! + ! Copy characteristic definitions ! - literal CLONEVA$C_COPY = 0; ! Copy literal CLONEVA$C_NOCOPY = 1; ! No copy literal CLONEVA$C_DZRO = 2; ! Demand zero literal CLONEVA$C_CW = 3; ! Copy on write literal CLONEVA$C_MAX_CHAR = 3; ! Maximum value !*** MODULE $CLUDCBDEF *** ! + ! CLUDCB - Cluster Quorum Disk Control Block ! - literal CLUDCB$M_QS_REM_INA = %X'1'; literal CLUDCB$M_QS_REM_ACT = %X'2'; literal CLUDCB$M_QS_NOT_READY = %X'4'; literal CLUDCB$M_QS_READY = %X'8'; literal CLUDCB$M_QS_ACTIVE = %X'10'; literal CLUDCB$M_QS_CLUSTER = %X'20'; literal CLUDCB$M_QS_VOTE = %X'40'; literal CLUDCB$M_QF_INQTMO = %X'1'; literal CLUDCB$M_QF_INQIP = %X'2'; literal CLUDCB$M_QF_TIM = %X'4'; literal CLUDCB$M_QF_RIP = %X'8'; literal CLUDCB$M_QF_WIP = %X'10'; literal CLUDCB$M_QF_ERROR = %X'20'; literal CLUDCB$M_QF_FIRST_ERR = %X'40'; literal CLUDCB$M_QF_WRL_ERR = %X'80'; literal CLUDCB$M_QF_NOACCESS = %X'100'; literal CLUDCB$M_CSP_ACK = %X'1'; literal CLUDCB$M_CSP_LBN_VALID = %X'2'; literal CLUDCB$M_CSP_MVHELP = %X'4'; literal CLUDCB$K_F_LENGTH = 64; ! Length of fixed portion of CLUDCB literal CLUDCB$C_F_LENGTH = 64; ! Length of fixed portion of CLUDCB literal CLUDCB$K_LENGTH = 580; ! Length of CLUDCB literal CLUDCB$C_LENGTH = 580; ! Length of CLUDCB ! The quorum disk is specified with 4 sysgen parameters. DISK_QUORUM1 literal CLUDCB$S_DISK_QUORUM = 16; literal CLUDCB$S_CLUDCB = 580; macro CLUDCB$L_CLUDCBFL = 0,0,32,1 %; ! Forward Link (not used) macro CLUDCB$L_CLUDCBBL = 4,0,32,1 %; ! Backward Link (not used) macro CLUDCB$W_SIZE = 8,0,16,0 %; ! Size of CLUDCB (bytes) macro CLUDCB$B_TYPE = 10,0,8,0 %; ! Structure type macro CLUDCB$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro CLUDCB$L_UCB = 12,0,32,1 %; ! Address of quorum disk UCB macro CLUDCB$L_IRP = 16,0,32,1 %; ! Address of IRP macro CLUDCB$L_TQE = 20,0,32,1 %; ! Address of timer queue entry macro CLUDCB$L_WATCHER_CSID = 24,0,32,0 %; ! CSID of quorum file watcher macro CLUDCB$L_ACT_COUNT = 28,0,32,0 %; ! Saved activity counter macro CLUDCB$L_QFLBN = 32,0,32,0 %; ! Quorum file logical block number macro CLUDCB$W_STATE = 40,0,16,0 %; ! Quorum disk state bits macro CLUDCB$V_QS_REM_INA = 40,0,1,0 %; ! Remote inactive macro CLUDCB$V_QS_REM_ACT = 40,1,1,0 %; ! Remote active macro CLUDCB$V_QS_NOT_READY = 40,2,1,0 %; ! Not ready macro CLUDCB$V_QS_READY = 40,3,1,0 %; ! Ready macro CLUDCB$V_QS_ACTIVE = 40,4,1,0 %; ! Active macro CLUDCB$V_QS_CLUSTER = 40,5,1,0 %; ! Active and this node is a cluster member macro CLUDCB$V_QS_VOTE = 40,6,1,0 %; ! Potential vote macro CLUDCB$W_FLAGS = 44,0,16,0 %; ! CLUDCB status bits macro CLUDCB$V_QF_INQTMO = 44,0,1,0 %; ! Status inquiry timed out macro CLUDCB$V_QF_INQIP = 44,1,1,0 %; ! Remote inquiry in progress macro CLUDCB$V_QF_TIM = 44,2,1,0 %; ! Read or write timed out macro CLUDCB$V_QF_RIP = 44,3,1,0 %; ! Read in progress macro CLUDCB$V_QF_WIP = 44,4,1,0 %; ! Write in progress macro CLUDCB$V_QF_ERROR = 44,5,1,0 %; ! Quorum disk error has been reported macro CLUDCB$V_QF_FIRST_ERR = 44,6,1,0 %; ! First error has already been seen macro CLUDCB$V_QF_WRL_ERR = 44,7,1,0 %; ! Quorum disk is write-locked macro CLUDCB$V_QF_NOACCESS = 44,8,1,0 %; ! Never access the quorum disk directly ! The interlocked flags field is in its own quadword for granulary reasons macro CLUDCB$W_CSP_FLAGS = 48,0,16,0 %; ! Flags for interlocked communication with CSP macro CLUDCB$V_CSP_ACK = 48,0,1,0 %; ! CSP request has been acknowledged macro CLUDCB$V_CSP_LBN_VALID = 48,1,1,0 %; ! CSP has found a quorum file macro CLUDCB$V_CSP_MVHELP = 48,2,1,0 %; ! Restart mount verification macro CLUDCB$B_COUNTER = 56,0,8,0 %; ! Iteration counter macro CLUDCB$T_BUFFER = 64,0,0,0 %; literal CLUDCB$S_BUFFER = 516; ! Quorum file buffer ! to DISK_QUORUM4. Each parameter can specify 4 bytes. !*** MODULE $CLUDEF *** ! + ! CLUDEF - CLUSTER DEFINITIONS ! - literal CLU$C_MAX_NODES = 256; ! MAX CLUSTER NODES literal CLU$K_MAX_NODES = 256; ! MAX CLUSTER NODES !*** MODULE $CLUEVTIDEF *** ! get the ACB def ! get the CLUEVTHNDL def literal CLUACB$K_LENGTH = 52; ! Length of block. literal CLUACB$C_LENGTH = 52; ! Length of block. literal cluacb$S_cluacb = 52; macro cluacb$r_generic_acb = 0,0,0,0 %; literal cluacb$s_generic_acb = 36; macro cluacb$r_handle = 36,0,0,0 %; literal cluacb$s_handle = 8; ! unique handle id (in case of cancellation) macro cluacb$l_event = 44,0,32,0 %; ! event type value macro cluacb$l_local_queue = 48,0,32,1 %; ! set indicates CLUACB on CLUEVT private queue literal CLUEVT$K_LENGTH = 64; ! Length of block. literal CLUEVT$C_LENGTH = 64; ! Length of block. literal cluevt$S_cluevt = 64; macro cluevt$l_reserved_1 = 0,0,32,0 %; ! set up default header macro cluevt$l_reserved_2 = 4,0,32,0 %; macro cluevt$w_size = 8,0,16,0 %; macro cluevt$b_type = 10,0,8,0 %; macro cluevt$b_subtype = 11,0,8,0 %; macro cluevt$l_seq_num = 12,0,32,0 %; ! ever increasing counter macro cluevt$l_add_qfl = 16,0,32,1 %; ! queued CLUACBs macro cluevt$l_add_qbl = 20,0,32,1 %; macro cluevt$l_rem_qfl = 24,0,32,1 %; macro cluevt$l_rem_qbl = 28,0,32,1 %; macro cluevt$l_reserved_3 = 32,0,32,0 %; ! reserved for future use macro cluevt$l_reserved_4 = 36,0,32,0 %; macro cluevt$l_reserved_5 = 40,0,32,0 %; macro cluevt$l_reserved_6 = 44,0,32,0 %; macro cluevt$l_reserved_7 = 48,0,32,0 %; macro cluevt$l_reserved_8 = 52,0,32,0 %; macro cluevt$l_reserved_9 = 56,0,32,0 %; macro cluevt$l_reserved_0 = 60,0,32,0 %; !*** MODULE $CLUICBDEF *** ! + ! CLUICB - Incarnation File Control Block ! - literal CLUICB$M_WIP = %X'1'; literal CLUICB$M_WREQ = %X'2'; literal CLUICB$K_F_LENGTH = 32; ! Length of fixed portion literal CLUICB$C_F_LENGTH = 32; ! Length of fixed portion ! End of fixed portion of the block literal CLUICB$T_BUFFER = 32; ! Start of incarnation ! file buffer area literal CLUICB$S_CLUICB = 32; ! Fixed portion macro CLUICB$L_FL = 0,0,32,1 %; ! Forward Link macro CLUICB$L_BL = 4,0,32,1 %; ! Backward Link macro CLUICB$W_SIZE = 8,0,16,0 %; ! Size of block macro CLUICB$B_TYPE = 10,0,8,0 %; ! Structure type macro CLUICB$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro CLUICB$L_IRP = 12,0,32,1 %; ! Address of IRP macro CLUICB$L_LBN = 16,0,32,0 %; ! Incarnation file logical block number macro CLUICB$W_WIP_CNT = 20,0,16,0 %; ! Write-in-progress counter macro CLUICB$W_FLAGS = 24,0,16,0 %; ! Flags macro CLUICB$V_WIP = 24,0,1,0 %; ! Write-in-progress bit macro CLUICB$V_WREQ = 24,1,1,0 %; ! Write requested bit !*** MODULE $CLUOPTDEF *** ! + ! CLUOPT - Cluster Optimal ReConfiguration Context Block ! - literal CLUOPT$K_LENGTH = 116; ! Length of CLUOPT literal CLUOPT$C_LENGTH = 116; ! Length of CLUOPT literal CLUOPT$S_CLUOPT = 116; macro CLUOPT$L_PREV = 0,0,32,1 %; ! Link to previous CLUOPT block macro CLUOPT$W_SIZE = 8,0,16,0 %; ! Size of CLUOPT (bytes) macro CLUOPT$B_TYPE = 10,0,8,0 %; ! Structure type macro CLUOPT$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro CLUOPT$L_CMERIT = 12,0,32,0 %; ! Figure of merit of nodes in CMAP macro CLUOPT$L_ACMERIT = 16,0,32,0 %; ! Figure of merit of nodes in AMAP + CMAP macro CLUOPT$B_CMAP = 20,0,0,1 %; literal CLUOPT$S_CMAP = 32; ! Map of nodes in proposed cluster macro CLUOPT$B_AMAP = 52,0,0,1 %; literal CLUOPT$S_AMAP = 32; ! Map of nodes available for cluster macro CLUOPT$B_RMAP = 84,0,0,1 %; literal CLUOPT$S_RMAP = 32; ! Map of nodes remaining for consideration !*** MODULE $CLUPBDEF *** ! + ! CLUPB - PARALLEL CONTEXT BLOCK ! ! - literal CLUPB$M_BUSY = %X'1'; literal CLUPB$K_FIX_LENGTH = 52; ! Optional extensions for user's of the service literal CLUPB$K_RBLD_LENGTH = 88; literal CLUPB$K_LENGTH = 88; ! LENGTH literal CLUPB$C_LENGTH = 88; ! LENGTH literal CLUPB$S_CLUPBDEF = 88; literal CLUPB$S_CLUPB = 88; ! This section reserved for the service itself macro CLUPB$B_FORK_BLOCK = 0,0,0,1 %; literal CLUPB$S_FORK_BLOCK = 32; ! FORK BLOCK macro CLUPB$W_FLAGS = 32,0,16,0 %; ! STATUS FLAGS macro CLUPB$V_BUSY = 32,0,1,0 %; macro CLUPB$B_THREADS = 34,0,8,0 %; ! ACTIVE THREADS macro CLUPB$B_MAX_THREADS = 35,0,8,0 %; ! MAX ACTIVE THREADS macro CLUPB$L_PARENT = 36,0,32,0 %; ! PARENT CONTEXT BLOCK ! This section filled in by user of service macro CLUPB$L_ACTION = 40,0,32,1 %; ! ACTION ROUTINE macro CLUPB$L_CPLRTN = 44,0,32,1 %; ! COMPLETION ROUTINE macro CLUPB$L_CPLPRM = 48,0,32,0 %; ! COMPLETION PARAMETER ! Lock rebuild extensions macro CLUPB$L_RTN1 = 56,0,32,0 %; ! SAVED RETURN ADDRESS macro CLUPB$B_QCNT = 60,0,8,0 %; ! QUEUE COUNTER macro CLUPB$Q_RTRSB = 64,0,0,1 %; literal CLUPB$S_RTRSB = 8; ! ROOT RSB macro CLUPB$Q_RSB_LIST = 72,0,0,1 %; literal CLUPB$S_RSB_LIST = 8; ! RSB LIST ADDRESS macro CLUPB$Q_LKB_LIST = 80,0,0,1 %; literal CLUPB$S_LKB_LIST = 8; ! LKB LIST ADDRESS ! Other extensions can go here !*** MODULE $CLURCBDEF *** ! + ! CLURCB - REMASTER CONTROL BLOCK ! ! - literal CLURCB$M_BUSY = %X'1'; literal CLURCB$M_FQ = %X'2'; literal CLURCB$M_EXP_DONE_VLD = %X'4'; literal CLURCB$M_QUOTA = %X'8'; literal CLURCB$M_OLDMST = %X'10'; literal CLURCB$M_EXPMSG = %X'20'; literal CLURCB$M_TQE = %X'40'; literal CLURCB$M_CANCEL = %X'80'; literal CLURCB$M_BXFR = %X'100'; literal CLURCB$M_BXFR_LAST = %X'200'; literal CLURCB$M_WVB_ABORT = %X'400'; literal CLURCB$K_LENGTH = 1384; ! LENGTH OF CLURCB literal CLURCB$C_LENGTH = 1384; ! LENGTH OF CLURCB literal CLURCB$S_CLURCBDEF = 1384; ! Old size name synonym literal CLURCB$S_CLURCB = 1384; macro CLURCB$L_CLURCBFL = 0,0,32,1 %; ! FORWARD LINK macro CLURCB$L_CLURCBBL = 4,0,32,1 %; ! BACKWARD LINK macro CLURCB$W_SIZE = 8,0,16,0 %; ! SIZE IN BYTES macro CLURCB$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE macro CLURCB$B_SUBTYPE = 11,0,8,0 %; ! STRUCTURE SUBTYPE macro CLURCB$W_RSEQNUM = 12,0,16,0 %; ! FULL REBUILD SEQ NUM macro CLURCB$W_PARSEQNUM = 14,0,16,0 %; ! PARTIAL REBUILD SEQ NUM ! Align the fork block macro CLURCB$B_FORK_BLOCK = 16,0,0,1 %; literal CLURCB$S_FORK_BLOCK = 64; ! FORK BLOCK / TQE TO WAIT IN macro CLURCB$L_FLAGS = 80,0,32,0 %; ! STATUS FLAGS macro CLURCB$V_BUSY = 80,0,1,0 %; ! Fork block in use macro CLURCB$V_FQ = 80,1,1,0 %; ! On fork queue macro CLURCB$V_EXP_DONE_VLD = 80,2,1,0 %; ! Expected done count valid macro CLURCB$V_QUOTA = 80,3,1,0 %; ! Quota charged macro CLURCB$V_OLDMST = 80,4,1,0 %; ! Old master macro CLURCB$V_EXPMSG = 80,5,1,0 %; ! Message expected macro CLURCB$V_TQE = 80,6,1,0 %; ! Queued as TQE macro CLURCB$V_CANCEL = 80,7,1,0 %; ! Cancel TQE thread macro CLURCB$V_BXFR = 80,8,1,0 %; ! can use block transfer macro CLURCB$V_BXFR_LAST = 80,9,1,0 %; ! bxfer - last buffer macro CLURCB$V_WVB_ABORT = 80,10,1,0 %; ! Block WVB needs to clean up macro CLURCB$B_QCNT = 84,0,8,0 %; ! LOCK QUEUE COUNTER macro CLURCB$Q_LKB_LIST = 88,0,0,1 %; literal CLURCB$S_LKB_LIST = 8; ! ADDRESS OF LKB LIST macro CLURCB$Q_RSB_LIST = 96,0,0,1 %; literal CLURCB$S_RSB_LIST = 8; ! ADDRESS OF RSB LIST macro CLURCB$Q_CNTX1 = 104,0,0,0 %; literal CLURCB$S_CNTX1 = 8; ! CONTEXT STORAGE macro CLURCB$Q_CNTX2 = 112,0,0,0 %; literal CLURCB$S_CNTX2 = 8; ! CONTEXT STORAGE macro CLURCB$L_WAITRET = 120,0,32,1 %; ! RETURN PC STORAGE macro CLURCB$L_ERRRET = 124,0,32,1 %; ! RETURN PC ON ERROR macro CLURCB$L_EXPTIME = 128,0,32,0 %; ! Expiration time macro CLURCB$W_EXP_DONE = 132,0,16,0 %; ! RBLD_DONES expected macro CLURCB$W_RCV_DONE = 134,0,16,0 %; ! RBLD_DONES received macro CLURCB$L_NEWMASTER = 136,0,32,0 %; ! NEW MASTER'S CSID macro CLURCB$L_OLDMASTER = 140,0,32,0 %; ! OLD MASTER'S CSID macro CLURCB$Q_RSB = 144,0,0,1 %; literal CLURCB$S_RSB = 8; ! ADDRESS OF ROOT RSB macro CLURCB$L_CLUB = 152,0,32,1 %; ! ADDRESS OF CLUB macro CLURCB$W_RESPCNT = 156,0,16,0 %; ! EXPECTED RESPONSE COUNT macro CLURCB$W_INDEX = 158,0,16,0 %; ! MAP INDEX macro CLURCB$L_SAVRTN = 160,0,32,1 %; ! SAVED RETURN ADDRESS macro CLURCB$L_MSGBLD = 164,0,32,1 %; ! MESSAGE BUILD ROUTINE macro CLURCB$B_NODEMAP = 168,0,0,1 %; literal CLURCB$S_NODEMAP = 32; ! NODES TO REBUILD macro CLURCB$B_SHUTMAP = 200,0,0,1 %; literal CLURCB$S_SHUTMAP = 32; ! NODES WITH TRAFFIC SHUTDOWN macro CLURCB$B_ACKMAP = 232,0,0,1 %; literal CLURCB$S_ACKMAP = 32; ! NODES RETURNING ACKS macro CLURCB$B_RESMAP = 264,0,0,1 %; literal CLURCB$S_RESMAP = 32; ! NODES NEEDING RESUMPTION macro CLURCB$L_BPTR = 296,0,32,1 %; ! Bxfer buffer pointer macro CLURCB$L_BSIZE = 300,0,32,0 %; ! Bxfer buffer allocated size macro CLURCB$L_BOFF = 304,0,32,0 %; ! current Offset in buffer macro CLURCB$L_BXFR_CDRP = 308,0,32,1 %; ! block transfer CDRP macro CLURCB$L_NRSB = 312,0,32,1 %; ! number of RSBs written to buffer macro CLURCB$L_NLKB = 316,0,32,1 %; ! number of LKBs written to buffer macro CLURCB$Q_CURRSB = 320,0,0,1 %; literal CLURCB$S_CURRSB = 8; ! current RSB during Block XFER macro CLURCB$Q_CURLKB = 328,0,0,1 %; literal CLURCB$S_CURLKB = 8; ! current LKB during Block XFER macro CLURCB$Q_RMSTART = 336,0,0,1 %; literal CLURCB$S_RMSTART = 8; ! timing extensions macro CLURCB$L_TOTRSB = 344,0,32,1 %; ! timing extensions macro CLURCB$L_TOTLKB = 348,0,32,1 %; ! timing extensions macro CLURCB$L_WVBSENT = 352,0,32,1 %; ! WVB bufs in flight macro CLURCB$L_WVBBUF = 360,0,0,1 %; literal CLURCB$S_WVBBUF = 1024; ! Write value block buf pointers !*** MODULE $CMNBDLTDEF *** literal CMNBDLT$K_RESERVED_LENGTH = 80; ! Length of Reserved area literal CMNBDLT$K_LENGTH = 128; ! Length of Header literal CMNBDLT$C_LENGTH = 128; ! Length of Header literal CMNBDLT$C_LEAF_ENTRY_SZ = 16; ! Length of one leaf pointer entry literal CMNBDLT$C_INIT_BDLT_INDEX = 7; ! Initial BDLT LAST_INDEX, used to show space occupied by BDLT header is in use literal CMNBDLT$S_CMNBDLTDEF = 144; ! Old size name - synonym literal CMNBDLT$S_CMNBDLT = 144; macro CMNBDLT$Q_PHY_ADDR = 0,0,0,0 %; literal CMNBDLT$S_PHY_ADDR = 8; ! BDLT physical address macro CMNBDLT$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro CMNBDLT$B_TYPE = 10,0,8,0 %; ! Structure Type macro CMNBDLT$B_SUBTYPE = 11,0,8,0 %; ! Structure Subtype for BDLT macro CMNBDLT$L_BD_CNT = 12,0,32,0 %; ! Current number of assigned BDs macro CMNBDLT$L_FILL = 16,0,32,0 %; ! Unused for alignment macro CMNBDLT$L_QBDLT_CNT = 20,0,32,0 %; ! Count of BDLT waits macro CMNBDLT$L_LAST_INDEX = 24,0,32,0 %; ! Highest current BDLT Index macro CMNBDLT$L_MAX_INDEX = 28,0,32,0 %; ! Maximum allowed BDLT Index macro CMNBDLT$L_FREE_BD = 32,0,32,1 %; ! Free BD list macro CMNBDLT$L_PORT_PTR = 36,0,32,1 %; ! reserved for port/port driver pointer macro CMNBDLT$L_WAITFL = 40,0,32,1 %; ! BD Wait Queue FLINK macro CMNBDLT$L_WAITBL = 44,0,32,1 %; ! BD Wait Queue BLINK macro CMNBDLT$Q_RESERVED_1 = 48,0,0,0 %; literal CMNBDLT$S_RESERVED_1 = 8; ! Reserved quadword macro CMNBDLT$Q_RESERVED_2 = 56,0,0,0 %; literal CMNBDLT$S_RESERVED_2 = 8; ! Reserved quadword macro CMNBDLT$Q_RESERVED_3 = 64,0,0,0 %; literal CMNBDLT$S_RESERVED_3 = 8; ! Reserved quadword macro CMNBDLT$Q_RESERVED_4 = 72,0,0,0 %; literal CMNBDLT$S_RESERVED_4 = 8; ! Reserved quadword macro CMNBDLT$Q_RESERVED_5 = 80,0,0,0 %; literal CMNBDLT$S_RESERVED_5 = 8; ! Reserved quadword macro CMNBDLT$Q_RESERVED_6 = 88,0,0,0 %; literal CMNBDLT$S_RESERVED_6 = 8; ! Reserved quadword macro CMNBDLT$Q_RESERVED_7 = 96,0,0,0 %; literal CMNBDLT$S_RESERVED_7 = 8; ! Reserved quadword macro CMNBDLT$Q_RESERVED_8 = 104,0,0,0 %; literal CMNBDLT$S_RESERVED_8 = 8; ! Reserved quadword macro CMNBDLT$Q_RESERVED_9 = 112,0,0,0 %; literal CMNBDLT$S_RESERVED_9 = 8; ! Reserved quadword macro CMNBDLT$Q_RESERVED_10 = 120,0,0,0 %; literal CMNBDLT$S_RESERVED_10 = 8; ! Reserved quadword macro CMNBDLT$Q_BDL_PTR0_PHY = 128,0,0,0 %; literal CMNBDLT$S_BDL_PTR0_PHY = 8; ! Buffer Descriptor 0 Leaf Physical Pointer macro CMNBDLT$Q_BDL_PTR0_VIR = 136,0,0,0 %; literal CMNBDLT$S_BDL_PTR0_VIR = 8; ! Buffer Descriptor 0 Leaf Virtual Pointer !*** MODULE $CONDEF *** ! + ! ! Console function codes (defined in SRM). ! ! - literal CON$C_SWDONE = 1; ! Software done literal CON$C_BOOTCPU = 2; ! Boot function code literal CON$C_CLRWARM = 3; ! Clear warm start flag literal CON$C_CLRCOLD = 4; ! Clear cold start flag ! + ! ! Routine specifier codes used when calling CON$ASSIST_PSWITCH ! ! - literal CON$C_START_SWITCH = 1; ! Start primary switch operation literal CON$C_ABORT_SWITCH = 2; ! Abort primary switch operation literal CON$C_FINISH_SWITCH = 3; ! Finish primary switch operation literal RXCST$M_IE = %X'40'; literal RXCST$M_RDY = %X'80'; literal RXCST$S_RXCST = 1; macro RXCST$V_IE = 0,6,1,0 %; ! Receiver Interrupt Enable macro RXCST$V_RDY = 0,7,1,0 %; ! Receiver Data Ready literal TXCST$M_IE = %X'40'; literal TXCST$M_RDY = %X'80'; literal TXCST$M_ERR = %X'8000'; literal TXCST$S_TXCST = 2; macro TXCST$V_IE = 0,6,1,0 %; ! Transmitter Interrupt Enable macro TXCST$V_RDY = 0,7,1,0 %; ! Transmitter Ready for Input macro TXCST$V_ERR = 0,15,1,0 %; ! Error sending, pls re-transmit literal RXTX$M_ERR = %X'8000'; literal RXTX$S_RXTX = 2; macro RXTX$V_DATA = 0,0,8,0 %; literal RXTX$S_DATA = 8; ! Data field of RXDB/TXDB macro RXTX$V_ID = 0,8,4,0 %; literal RXTX$S_ID = 4; ! ID field of RXDB/TXDB macro RXTX$V_ERR = 0,15,1,0 %; ! Error bit, RXDB only !*** MODULE CONFIG_TABLE *** ! ! The configuration table has a 64-bit mask prefix. This mask is used to ! strip the HW ID in the busarray prior to matching against the ID in the ! configuration entry array. ! literal iogen_cfg_tbl$S_config_header = 8; macro iogen_cfg_tbl$l_hw_id_mask_lo = 0,0,32,0 %; ! HW ID mask low 32-bits macro iogen_cfg_tbl$l_hw_id_mask_hi = 4,0,32,0 %; ! HW ID mask high 32-bits macro iogen_cfg_tbl$q_hw_id_mask = 0,0,0,0 %; literal iogen_cfg_tbl$s_hw_id_mask = 8; ! HW ID mask 64-bits literal iogen_cfg_tbl$k_header_len = 8; ! Length of the entry ! ! This structure provides a layout of the memory used by the ! config table. It is prepended to the config_table structure ! and is typically used only for creation and deletion of the ! table. ! ! The table is created from a single pool allocation. This pool ! fragment is then managed by the table creation routines as a ! private pool. This minimizes fragmentation of pool, and allows ! the entire table to be deleted by a single call. ! ! The definition has been worked to be the same size as a "normal" ! block header for VMS. The first two longword are not a flink ! and blink - since this is not part of a queue. But the size, ! type and subtype fields are all in the right places. ! literal config_memdsc$S_config_memdsc = 16; macro config_memdsc$ps_fragment = 0,0,32,1 %; ! Pointer to free memory in the fragment macro config_memdsc$w_free = 4,0,16,1 %; ! Amount of memory left in the fragment macro config_memdsc$b_refcnt = 6,0,8,1 %; ! Number of references to the fragment macro config_memdsc$B_FILL = 7,0,8,1 %; ! Spare byte macro config_memdsc$w_size = 8,0,16,1 %; ! Total size of the pool fragment or FFFF macro config_memdsc$b_type = 10,0,8,1 %; ! Block type macro config_memdsc$b_subtype = 11,0,8,1 %; ! Subtype macro config_memdsc$l_actual_size = 12,0,32,1 %; ! Actual block size if size is FFFF ! ! This structure describes an array entry in the config table. It uses the ! iogen_cfg_tbl prefix for historical reasons. The first 32 bytes (up to the ! flags) is identical in format to a hand-defined BLISS definition that was ! replaced in IOGEN_MACROS.REQ. The second 32 bytes provide additional information ! to allow boot configuration, and make the configuration extensible. ! ! If you touch this structure size, or order of the fields, you must edit ! IOGEN_MACROS.REQ as well as any *_SUPPORT.C bus modules to ensure that the dummy ! records are properly initialized. ! literal iogen_cfg_tbl$m_mscp = %X'1'; literal iogen_cfg_tbl$m_scsi = %X'2'; literal iogen_cfg_tbl$m_novector = %X'4'; literal iogen_cfg_tbl$m_disk = %X'8'; literal iogen_cfg_tbl$m_network = %X'10'; literal iogen_cfg_tbl$m_port = %X'20'; literal iogen_cfg_tbl$m_class = %X'40'; literal iogen_cfg_tbl$m_pseudo = %X'80'; literal iogen_cfg_tbl$m_boot = %X'100'; literal iogen_cfg_tbl$m_case_blind = %X'200'; literal iogen_cfg_tbl$m_no_table = %X'400'; literal iogen_cfg_tbl$m_extended_id = %X'800'; literal iogen_cfg_tbl$m_foreign = %X'1000'; literal iogen_cfg_tbl$m_fibre = %X'2000'; literal iogen_cfg_tbl$m_ulp = %X'4000'; literal iogen_cfg_tbl$m_load_drv_class = %X'8000'; literal iogen_cfg_tbl$m_nisca = %X'10000'; literal iogen_cfg_tbl$m_isa_on_eisa = %X'20000'; literal iogen_cfg_tbl$m_ciss = %X'40000'; literal iogen_cfg_tbl$m_sas = %X'80000'; literal iogen_cfg_tbl$m_sys_dev = %X'1'; literal iogen_cfg_tbl$m_remote = %X'2'; literal iogen_cfg_tbl$m_alt_prefix = %X'4'; literal iogen_cfg_tbl$m_no_ctrl_ltr = %X'8'; literal iogen_cfg_tbl$m_hw_ctrl_ltr = %X'10'; literal iogen_cfg_tbl$m_unit_0 = %X'20'; literal iogen_cfg_tbl$m_ctrl_ltr_a = %X'40'; literal iogen_cfg_tbl$m_create_dev = %X'80'; literal iogen_cfg_tbl$S_iogen_cfg_tbl = 72; macro iogen_cfg_tbl$l_hw_id_lo = 0,0,32,0 %; ! HW ID low 32-bits macro iogen_cfg_tbl$l_hw_id_hi = 4,0,32,0 %; ! HW ID high 32-bits macro iogen_cfg_tbl$q_hw_id = 0,0,0,0 %; literal iogen_cfg_tbl$s_hw_id = 8; ! HW ID as 64-bits macro iogen_cfg_tbl$b_hw_id_string = 0,0,0,1 %; literal iogen_cfg_tbl$s_hw_id_string = 8; ! HW ID as a string macro iogen_cfg_tbl$ps_driver_name = 8,0,32,1 %; ! Pointer to the device driver name (descriptor) macro iogen_cfg_tbl$ps_devnam = 12,0,32,1 %; ! Pointer to the device name (ASCIZ) macro iogen_cfg_tbl$l_vector_cnt = 16,0,32,0 %; ! Number of interrupt vectors macro iogen_cfg_tbl$l_vector_align = 20,0,32,0 %; ! Alignment for SCB vectors macro iogen_cfg_tbl$l_num_units = 24,0,32,0 %; ! Number of units macro iogen_cfg_tbl$l_flags = 28,0,32,0 %; ! Device flag word macro iogen_cfg_tbl$v_mscp = 28,0,1,0 %; ! MSCP device macro iogen_cfg_tbl$v_scsi = 28,1,1,0 %; ! SCSI device macro iogen_cfg_tbl$v_novector = 28,2,1,0 %; ! No Vector macro iogen_cfg_tbl$v_disk = 28,3,1,0 %; ! Disk macro iogen_cfg_tbl$v_network = 28,4,1,0 %; ! Network macro iogen_cfg_tbl$v_port = 28,5,1,0 %; ! Port driver macro iogen_cfg_tbl$v_class = 28,6,1,0 %; ! Class driver macro iogen_cfg_tbl$v_pseudo = 28,7,1,0 %; ! Psuedo driver macro iogen_cfg_tbl$v_boot = 28,8,1,0 %; ! Bootable device macro iogen_cfg_tbl$v_case_blind = 28,9,1,0 %; ! Match case blind macro iogen_cfg_tbl$v_no_table = 28,10,1,0 %; ! This is the dummy table macro iogen_cfg_tbl$v_extended_id = 28,11,1,0 %; ! ID check should not use the HW_MASK macro iogen_cfg_tbl$v_foreign = 28,12,1,0 %; ! Entry is from TPB file macro iogen_cfg_tbl$v_fibre = 28,13,1,0 %; ! Fibre Channel macro iogen_cfg_tbl$v_ulp = 28,14,1,0 %; ! Upper-Level Protocol macro iogen_cfg_tbl$v_load_drv_class = 28,15,1,0 %; ! Load driver class when loading driver macro iogen_cfg_tbl$v_nisca = 28,16,1,0 %; ! Identifies NISCA port driver macro iogen_cfg_tbl$v_isa_on_eisa = 28,17,1,0 %; ! Device is a ISA device on an EISA bus macro iogen_cfg_tbl$v_ciss = 28,18,1,0 %; ! CISS controller macro iogen_cfg_tbl$v_sas = 28,19,1,0 %; ! SAS controller macro iogen_cfg_tbl$ps_description = 32,0,32,1 %; ! Description of device (ASCIZ) macro iogen_cfg_tbl$l_adp_type = 36,0,32,0 %; ! Adapter type macro iogen_cfg_tbl$ps_assoc_drv = 40,0,32,1 %; ! Associated driver (ASCIZ) macro iogen_cfg_tbl$ps_dtype = 44,0,32,1 %; ! Pointer to TYPE string (ASCIZ) macro iogen_cfg_tbl$ps_boot_class = 48,0,32,1 %; ! Boot class name (ASCIZ) macro iogen_cfg_tbl$l_boot_flags = 52,0,32,0 %; ! Boot flag word macro iogen_cfg_tbl$v_sys_dev = 52,0,1,0 %; ! Device can be a system disk macro iogen_cfg_tbl$v_remote = 52,1,1,0 %; ! Remote macro iogen_cfg_tbl$v_alt_prefix = 52,2,1,0 %; ! Alternate prefix macro iogen_cfg_tbl$v_no_ctrl_ltr = 52,3,1,0 %; ! Don't assign controller letter macro iogen_cfg_tbl$v_hw_ctrl_ltr = 52,4,1,0 %; ! Needs same controller letter macro iogen_cfg_tbl$v_unit_0 = 52,5,1,0 %; ! Unit 0 macro iogen_cfg_tbl$v_ctrl_ltr_a = 52,6,1,0 %; ! Device must be unique macro iogen_cfg_tbl$v_create_dev = 52,7,1,0 %; ! Must create new device macro iogen_cfg_tbl$ps_private = 56,0,32,1 %; ! For extensions (ASCIZ) macro iogen_cfg_tbl$l_avail = 60,0,32,1 %; ! Available for extensions macro iogen_cfg_tbl$l_avail2 = 64,0,32,1 %; ! Available for extensions literal iogen_cfg_tbl$k_entry_size = 72; ! Length of the entry ! ! The config_table structure is the union of both the hw id mask, ! and the config table (iogen_cfg_tbl). This structure is pointed ! to by ADP$PS_CONFIG_TABLE. A memory descriptor for it exists at ! a negative offset. ! literal config_table$S_config_table = 80; macro config_table$r_header = 0,0,0,0 %; literal config_table$s_header = 8; ! Hardware ID mask header macro config_table$r_entries = 8,0,0,0 %; literal config_table$s_entries = 72; ! Configuration entry array starts here ! ! The config_mem structure contains the memory prefix description. Normally ! this is only use by the allocation and deallocation routines, and the table ! consumers see only the config_table or iogen_cfg_tbl structures. ! literal config_mem$S_config_mem = 96; macro config_mem$r_memdsc = 0,0,0,0 %; literal config_mem$s_memdsc = 16; ! Memory descriptor macro config_mem$r_header = 16,0,0,0 %; literal config_mem$s_header = 8; ! Hardware ID mask prefix macro config_mem$r_entries = 24,0,0,0 %; literal config_mem$s_entries = 72; ! Configuration array !*** MODULE $COREIODEF *** literal COREIO$M_LDP_DMA_PA_LO = %X'FFFE0'; literal COREIO$M_LDP_DMA_PA_HI = %X'FFF00000'; literal COREIO$M_SCOMM_TR_DMA_PA = %X'FFFFFFE0'; literal COREIO$M_SCOMM_RC_DMA_PA = %X'FFFFFFE0'; literal COREIO$M_PRINTER_TR_DMA_PA = %X'FFFFFFE0'; literal COREIO$M_PRINTER_RC_DMA_PA = %X'FFFFFFE0'; literal COREIO$M_ISDN_TR_DMA_PA = %X'FFFFFFE0'; literal COREIO$M_ISDN_TR_BUF_DMA_PA = %X'FFFFFFE0'; literal COREIO$M_ISDN_RC_DMA_PA = %X'FFFFFFE0'; literal COREIO$M_ISDN_RC_BUF_DMA_PA = %X'FFFFFFE0'; literal COREIO$M_SSR_GPO_0 = %X'1'; literal COREIO$M_SSR_GPO_1 = %X'2'; literal COREIO$M_SSR_GPO_2 = %X'4'; literal COREIO$M_SSR_GPO_3 = %X'8'; literal COREIO$M_SSR_GPO_4 = %X'10'; literal COREIO$M_SSR_GPO_5 = %X'20'; literal COREIO$M_SSR_GPO_6 = %X'40'; literal COREIO$M_SSR_GPO_7 = %X'80'; literal COREIO$M_SSR_GPO_8 = %X'100'; literal COREIO$M_SSR_GPO_9 = %X'200'; literal COREIO$M_SSR_GPO_10 = %X'400'; literal COREIO$M_SSR_GPO_11 = %X'800'; literal COREIO$M_SSR_GPO_12 = %X'1000'; literal COREIO$M_SSR_GPO_13 = %X'2000'; literal COREIO$M_SSR_GPO_14 = %X'4000'; literal COREIO$M_SSR_GPO_15 = %X'8000'; literal COREIO$M_SSR_LANCE_DMA_EN = %X'10000'; literal COREIO$M_SSR_SCSI_DMA_EN = %X'20000'; literal COREIO$M_SSR_SCSI_DMA_DIR = %X'40000'; literal COREIO$M_SSR_ISDN_RCV_EN = %X'80000'; literal COREIO$M_SSR_ISDN_TR_EN = %X'100000'; literal COREIO$M_SSR_FLOPPY_DMA_EN = %X'200000'; literal COREIO$M_SSR_FLOPPY_DMA_DIR = %X'400000'; literal COREIO$M_SSR_SCC1_RC_DMA_EN = %X'10000000'; literal COREIO$M_SSR_SCC1_TR_DMA_EN = %X'20000000'; literal COREIO$M_SSR_SCC0_RC_DMA_EN = %X'40000000'; literal COREIO$M_SSR_SCC0_TR_DMA_EN = %X'80000000'; literal COREIO$M_SSR_LEDS = %X'FF'; literal COREIO$M_SSR_LANCE_RESET = %X'100'; literal COREIO$M_SSR_RTC_RESET = %X'400'; literal COREIO$M_SSR_SSC_RESET = %X'800'; literal COREIO$M_SSR_ISDN_RESET = %X'1000'; literal COREIO$M_SSR_10BASET_SEL = %X'2000'; literal COREIO$M_SSR_NI_LOOPBACK = %X'4000'; literal COREIO$M_SSR_TXDIS = %X'8000'; literal COREIO$M_SSR_ISDN_RC_DMA_EN = %X'80000'; literal COREIO$M_SSR_ISDN_TR_DMA_EN = %X'100000'; literal COREIO$M_SSR_PRINTER_RC_DMA_EN = %X'10000000'; literal COREIO$M_SSR_PRINTER_TR_DMA_EN = %X'20000000'; literal COREIO$M_SSR_COMM_RC_DMA_EN = %X'40000000'; literal COREIO$M_SSR_COMM_TR_DMA_EN = %X'80000000'; literal COREIO$M_SSR_IO_MASK = %X'F'; literal COREIO$M_SSR_IO_MASK_EN = %X'10'; literal COREIO$M_SSR_FPE = %X'80'; literal COREIO$M_SSR_SMR0 = %X'1000000'; literal COREIO$M_SSR_SMR1 = %X'2000000'; literal COREIO$M_SSR_SMRA = %X'4000000'; literal COREIO$M_SSR_FAST_MODE = %X'8000000'; literal COREIO$M_SSR_KBD_RC_DMA_EN = %X'10000000'; literal COREIO$M_SSR_KBD_TR_DMA_EN = %X'20000000'; literal COREIO$C_SIR = 544; ! A constant for C programmers - defines offset of SIR structure literal COREIO$M_SIR_GP_INT_0 = %X'1'; literal COREIO$M_SIR_GP_INT_1 = %X'2'; literal COREIO$M_SIR_GP_INT_2 = %X'4'; literal COREIO$M_SIR_GP_INT_3 = %X'8'; literal COREIO$M_SIR_GP_INT_4 = %X'10'; literal COREIO$M_SIR_GP_INT_5 = %X'20'; literal COREIO$M_SIR_GP_INT_6 = %X'40'; literal COREIO$M_SIR_GP_INT_7 = %X'80'; literal COREIO$M_SIR_GP_INT_8 = %X'100'; literal COREIO$M_SIR_GP_INT_9 = %X'200'; literal COREIO$M_SIR_GP_INT_10 = %X'400'; literal COREIO$M_SIR_GP_INT_11 = %X'800'; literal COREIO$M_SIR_GP_INT_12 = %X'1000'; literal COREIO$M_SIR_GP_INT_13 = %X'2000'; literal COREIO$M_SIR_GP_INT_14 = %X'4000'; literal COREIO$M_SIR_GP_INT_15 = %X'8000'; literal COREIO$M_SIR_LANCE_DMA_ER = %X'10000'; literal COREIO$M_SIR_SCSI_DMA_MRE = %X'20000'; literal COREIO$M_SIR_SCSI_DMA_OV = %X'40000'; literal COREIO$M_SIR_SCSI_DMA_PTR = %X'80000'; literal COREIO$M_SIR_ISDN_DMA_MRE = %X'100000'; literal COREIO$M_SIR_ISDN_DMA_RC_INTR = %X'200000'; literal COREIO$M_SIR_ISDN_DMA_TR_INTR = %X'400000'; literal COREIO$M_SIR_FLOPPY_DMA_INT = %X'800000'; literal COREIO$M_SIR_SCC1_DMA_OV = %X'1000000'; literal COREIO$M_SIR_SCC1_RCV_INT = %X'2000000'; literal COREIO$M_SIR_SCC1_TR_DMA_ME = %X'4000000'; literal COREIO$M_SIR_SCC1_TR_INT = %X'8000000'; literal COREIO$M_SIR_SCC0_DMA_OV = %X'10000000'; literal COREIO$M_SIR_SCC0_RCV_INT = %X'20000000'; literal COREIO$M_SIR_SCC0_TR_DMA_ME = %X'40000000'; literal COREIO$M_SIR_SCC0_TR_INT = %X'80000000'; literal COREIO$M_SIR_HALT0 = %X'1'; literal COREIO$M_SIR_HALT1 = %X'2'; literal COREIO$M_SIR_ALT_CONSOLE = %X'8'; literal COREIO$M_SIR_SCC0_SI = %X'40'; literal COREIO$M_SIR_SCC1_SI = %X'80'; literal COREIO$M_SIR_NI_INTR = %X'100'; literal COREIO$M_SIR_ISDN_INTR = %X'2000'; literal COREIO$M_SIR_LANCE_DMA_RE = %X'10000'; literal COREIO$M_SIR_PP_RC_DMA_OVR = %X'1000000'; literal COREIO$M_SIR_PP_RC_HP_INTR = %X'2000000'; literal COREIO$M_SIR_PP_TR_DMA_MRE = %X'4000000'; literal COREIO$M_SIR_PP_TR_PE_INTR = %X'8000000'; literal COREIO$M_SIR_COMM_RC_DMA_OVR = %X'10000000'; literal COREIO$M_SIR_COMM_RC_HP_INTR = %X'20000000'; literal COREIO$M_SIR_COMM_TR_DMA_MRE = %X'40000000'; literal COREIO$M_SIR_COMM_TR_PE_INTR = %X'80000000'; literal COREIO$M_SIR_TC_SLOT0 = %X'4'; literal COREIO$M_SIR_TC_SLOT1 = %X'8'; literal COREIO$M_SIR_SCC0_INT = %X'40'; literal COREIO$M_SIR_SCC1_INT = %X'80'; literal COREIO$M_SIR_LANCE_INT = %X'100'; literal COREIO$M_SIR_ISDN_INT = %X'2000'; literal COREIO$M_SIR_CONS_SEL = %X'8000'; literal COREIO$C_SIMR = 576; ! A constant for C programmers - defines offset of SIMR structure literal COREIO$M_SIMR_GP_INT_0 = %X'1'; literal COREIO$M_SIMR_GP_INT_1 = %X'2'; literal COREIO$M_SIMR_GP_INT_2 = %X'4'; literal COREIO$M_SIMR_GP_INT_3 = %X'8'; literal COREIO$M_SIMR_GP_INT_4 = %X'10'; literal COREIO$M_SIMR_GP_INT_5 = %X'20'; literal COREIO$M_SIMR_GP_INT_6 = %X'40'; literal COREIO$M_SIMR_GP_INT_7 = %X'80'; literal COREIO$M_SIMR_GP_INT_8 = %X'100'; literal COREIO$M_SIMR_GP_INT_9 = %X'200'; literal COREIO$M_SIMR_GP_INT_10 = %X'400'; literal COREIO$M_SIMR_GP_INT_11 = %X'800'; literal COREIO$M_SIMR_GP_INT_12 = %X'1000'; literal COREIO$M_SIMR_GP_INT_13 = %X'2000'; literal COREIO$M_SIMR_GP_INT_14 = %X'4000'; literal COREIO$M_SIMR_GP_INT_15 = %X'8000'; literal COREIO$M_SIMR_LANCE_DMA_ER = %X'10000'; literal COREIO$M_SIMR_SCSI_DMA_MRE = %X'20000'; literal COREIO$M_SIMR_SCSI_DMA_OV = %X'40000'; literal COREIO$M_SIMR_SCSI_DMA_PTR = %X'80000'; literal COREIO$M_SIMR_ISDN_DMA_MRE = %X'100000'; literal COREIO$M_SIMR_ISDN_DMA_RC_INTR = %X'200000'; literal COREIO$M_SIMR_ISDN_DMA_TR_INTR = %X'400000'; literal COREIO$M_SIMR_FLOPPY_DMA_INT = %X'800000'; literal COREIO$M_SIMR_SCC1_DMA_OV = %X'1000000'; literal COREIO$M_SIMR_SCC1_RCV_INT = %X'2000000'; literal COREIO$M_SIMR_SCC1_TR_DMA_ME = %X'4000000'; literal COREIO$M_SIMR_SCC1_TR_INT = %X'8000000'; literal COREIO$M_SIMR_SCC0_DMA_OV = %X'10000000'; literal COREIO$M_SIMR_SCC0_RCV_INT = %X'20000000'; literal COREIO$M_SIMR_SCC0_TR_DMA_ME = %X'40000000'; literal COREIO$M_SIMR_SCC0_TR_INT = %X'80000000'; literal COREIO$M_SIMR_HALT0 = %X'1'; literal COREIO$M_SIMR_HALT1 = %X'2'; literal COREIO$M_SIMR_ALT_CONSOLE = %X'8'; literal COREIO$M_SIMR_SCC0_SI = %X'40'; literal COREIO$M_SIMR_SCC1_SI = %X'80'; literal COREIO$M_SIMR_NI_INTR = %X'100'; literal COREIO$M_SIMR_ISDN_INTR = %X'2000'; literal COREIO$M_SIMR_LANCE_DMA_RE = %X'10000'; literal COREIO$M_SIMR_PP_RC_DMA_OVR = %X'1000000'; literal COREIO$M_SIMR_PP_RC_HP_INTR = %X'2000000'; literal COREIO$M_SIMR_PP_TR_DMA_MRE = %X'4000000'; literal COREIO$M_SIMR_PP_TR_PE_INTR = %X'8000000'; literal COREIO$M_SIMR_COMM_RC_DMA_OVR = %X'10000000'; literal COREIO$M_SIMR_COMM_RC_HP_INTR = %X'20000000'; literal COREIO$M_SIMR_COMM_TR_DMA_MRE = %X'40000000'; literal COREIO$M_SIMR_COMM_TR_PE_INTR = %X'80000000'; literal COREIO$M_SIMR_TC_SLOT0 = %X'4'; literal COREIO$M_SIMR_TC_SLOT1 = %X'8'; literal COREIO$M_SIMR_SCC0_INT = %X'40'; literal COREIO$M_SIMR_SCC1_INT = %X'80'; literal COREIO$M_SIMR_LANCE_INT = %X'100'; literal COREIO$M_SIMR_ISDN_INT = %X'2000'; literal COREIO$M_SIMR_CONS_SEL = %X'8000'; literal COREIO$M_SADR_TC_ADDR = %X'1FFFFE0'; literal COREIO$M_ISDN_DATA_TR_DATA = %X'FFFFFF'; literal COREIO$M_ISDN_DATA_RC_DATA = %X'FFFFFF'; literal COREIO$M_LANCE_SLOT_CS = %X'F'; literal COREIO$M_LANCE_SLOT_HW_ADDR = %X'3F0'; literal COREIO$M_SCC0_SLOT_CS = %X'F'; literal COREIO$M_SCC0_SLOT_HW_ADDR = %X'3F0'; literal COREIO$M_SCC1_SLOT_CS = %X'F'; literal COREIO$M_SCC1_SLOT_HW_ADDR = %X'3F0'; literal COREIO$C_ISDN_AUDIO = 49152; ! A constant for C programmers - defines offset of ISDN CSR literal COREIO$Q_tc_number = 1; ! High nibble of addr literal COREIO$Q_slot0_dense_base = 0; ! base PA of TC slot 0 literal COREIO$Q_slot1_dense_base = 536870912; ! base PA of TC slot 1 literal COREIO$Q_slot2_dense_base = 1073741824; ! base PA of TC slot 2 literal COREIO$Q_slot3_dense_base = 1610612736; ! base PA of TC slot 3 literal COREIO$Q_slot4_dense_base = -2147483648; ! base PA of TC slot 4 literal COREIO$Q_slot5_dense_base = -1610612736; ! base PA of TC slot 5 literal COREIO$Q_lance_rap = 1572872; ! PA of LANCE RAP reg literal COREIO$Q_lance_rdp_dense = 786432; ! PA of LANCE RDP reg literal COREIO$Q_ni_adr_rom_dense = 524288; ! PA of NI ADR ROM literal COREIO$Q_ldp_dense = 262176; ! PA of LDP reg literal COREIO$Q_lance_slot = 524992; ! PA of lance slot literal COREIO$Q_ssr = 524800; ! SSR reg literal COREIO$Q_sir = 524832; ! SIR reg literal COREIO$Q_simr = 524848; ! SIMR reg literal COREIO$S_COREIODEF = 57344; ! Old COREIO size field for compatibility literal COREIO$S_COREIO = 57344; macro COREIO$L_IOCTL_CSR = 0,0,32,1 %; ! Core I/O base CSR address macro COREIO$L_LDP = 64,0,32,0 %; ! Ethernet Lance DMA pointer macro COREIO$V_LDP_DMA_PA_LO = 64,5,15,0 %; literal COREIO$S_LDP_DMA_PA_LO = 15; macro COREIO$V_LDP_DMA_PA_HI = 64,20,12,0 %; literal COREIO$S_LDP_DMA_PA_HI = 12; macro COREIO$L_SCOMM_TR = 96,0,32,0 %; ! Serial comm transmit port 1 DMA pointer macro COREIO$V_SCOMM_TR_DMA_PA = 96,5,27,0 %; literal COREIO$S_SCOMM_TR_DMA_PA = 27; macro COREIO$L_SCOMM_RC = 128,0,32,0 %; ! Serial comm receive port 1 DMA pointer macro COREIO$V_SCOMM_RC_DMA_PA = 128,5,27,0 %; literal COREIO$S_SCOMM_RC_DMA_PA = 27; macro COREIO$L_PRINTER_TR = 160,0,32,0 %; ! Printer transmit port DMA pointer macro COREIO$V_PRINTER_TR_DMA_PA = 160,5,27,0 %; literal COREIO$S_PRINTER_TR_DMA_PA = 27; macro COREIO$L_PRINTER_RC = 192,0,32,0 %; ! Printer receive port DMA pointer macro COREIO$V_PRINTER_RC_DMA_PA = 192,5,27,0 %; literal COREIO$S_PRINTER_RC_DMA_PA = 27; macro COREIO$L_ISDN_TR = 256,0,32,0 %; ! ISDN transmit DMA pointer macro COREIO$V_ISDN_TR_DMA_PA = 256,5,27,0 %; literal COREIO$S_ISDN_TR_DMA_PA = 27; macro COREIO$L_ISDN_TR_BUF = 288,0,32,0 %; ! ISDN transmit DMA buffer pointer macro COREIO$V_ISDN_TR_BUF_DMA_PA = 288,5,27,0 %; literal COREIO$S_ISDN_TR_BUF_DMA_PA = 27; macro COREIO$L_ISDN_RC = 320,0,32,0 %; ! ISDN receive DMA pointer macro COREIO$V_ISDN_RC_DMA_PA = 320,5,27,0 %; literal COREIO$S_ISDN_RC_DMA_PA = 27; macro COREIO$L_ISDN_RC_BUF = 352,0,32,0 %; ! ISDN receive DMA buffer pointer macro COREIO$V_ISDN_RC_BUF_DMA_PA = 352,5,27,0 %; literal COREIO$S_ISDN_RC_BUF_DMA_PA = 27; macro COREIO$L_DATA0 = 384,0,32,0 %; ! System Data Buffer 0 macro COREIO$L_DATA1 = 416,0,32,0 %; ! System Data Buffer 1 macro COREIO$L_DATA2 = 448,0,32,0 %; ! System Data Buffer 2 macro COREIO$L_DATA3 = 480,0,32,0 %; ! System Data Buffer 3 macro COREIO$L_SSR = 512,0,32,0 %; ! System support register macro COREIO$V_SSR_GPO_0 = 512,0,1,0 %; macro COREIO$V_SSR_GPO_1 = 512,1,1,0 %; macro COREIO$V_SSR_GPO_2 = 512,2,1,0 %; macro COREIO$V_SSR_GPO_3 = 512,3,1,0 %; macro COREIO$V_SSR_GPO_4 = 512,4,1,0 %; macro COREIO$V_SSR_GPO_5 = 512,5,1,0 %; macro COREIO$V_SSR_GPO_6 = 512,6,1,0 %; macro COREIO$V_SSR_GPO_7 = 512,7,1,0 %; macro COREIO$V_SSR_GPO_8 = 512,8,1,0 %; macro COREIO$V_SSR_GPO_9 = 512,9,1,0 %; macro COREIO$V_SSR_GPO_10 = 512,10,1,0 %; macro COREIO$V_SSR_GPO_11 = 512,11,1,0 %; macro COREIO$V_SSR_GPO_12 = 512,12,1,0 %; macro COREIO$V_SSR_GPO_13 = 512,13,1,0 %; macro COREIO$V_SSR_GPO_14 = 512,14,1,0 %; macro COREIO$V_SSR_GPO_15 = 512,15,1,0 %; macro COREIO$V_SSR_LANCE_DMA_EN = 512,16,1,0 %; macro COREIO$V_SSR_SCSI_DMA_EN = 512,17,1,0 %; macro COREIO$V_SSR_SCSI_DMA_DIR = 512,18,1,0 %; macro COREIO$V_SSR_ISDN_RCV_EN = 512,19,1,0 %; macro COREIO$V_SSR_ISDN_TR_EN = 512,20,1,0 %; macro COREIO$V_SSR_FLOPPY_DMA_EN = 512,21,1,0 %; macro COREIO$V_SSR_FLOPPY_DMA_DIR = 512,22,1,0 %; macro COREIO$V_SSR_SCC1_RC_DMA_EN = 512,28,1,0 %; macro COREIO$V_SSR_SCC1_TR_DMA_EN = 512,29,1,0 %; macro COREIO$V_SSR_SCC0_RC_DMA_EN = 512,30,1,0 %; macro COREIO$V_SSR_SCC0_TR_DMA_EN = 512,31,1,0 %; macro COREIO$V_SSR_LEDS = 512,0,8,0 %; literal COREIO$S_SSR_LEDS = 8; macro COREIO$V_SSR_LANCE_RESET = 512,8,1,0 %; macro COREIO$V_SSR_RTC_RESET = 512,10,1,0 %; macro COREIO$V_SSR_SSC_RESET = 512,11,1,0 %; macro COREIO$V_SSR_ISDN_RESET = 512,12,1,0 %; macro COREIO$V_SSR_10BASET_SEL = 512,13,1,0 %; macro COREIO$V_SSR_NI_LOOPBACK = 512,14,1,0 %; macro COREIO$V_SSR_TXDIS = 512,15,1,0 %; macro COREIO$V_SSR_ISDN_RC_DMA_EN = 512,19,1,0 %; macro COREIO$V_SSR_ISDN_TR_DMA_EN = 512,20,1,0 %; macro COREIO$V_SSR_PRINTER_RC_DMA_EN = 512,28,1,0 %; macro COREIO$V_SSR_PRINTER_TR_DMA_EN = 512,29,1,0 %; macro COREIO$V_SSR_COMM_RC_DMA_EN = 512,30,1,0 %; macro COREIO$V_SSR_COMM_TR_DMA_EN = 512,31,1,0 %; macro COREIO$V_SSR_IO_MASK = 512,0,4,0 %; literal COREIO$S_SSR_IO_MASK = 4; macro COREIO$V_SSR_IO_MASK_EN = 512,4,1,0 %; macro COREIO$V_SSR_FPE = 512,7,1,0 %; macro COREIO$V_SSR_SMR0 = 512,24,1,0 %; macro COREIO$V_SSR_SMR1 = 512,25,1,0 %; macro COREIO$V_SSR_SMRA = 512,26,1,0 %; macro COREIO$V_SSR_FAST_MODE = 512,27,1,0 %; macro COREIO$V_SSR_KBD_RC_DMA_EN = 512,28,1,0 %; macro COREIO$V_SSR_KBD_TR_DMA_EN = 512,29,1,0 %; macro COREIO$L_SIR = 544,0,32,0 %; ! System interrupt register macro COREIO$V_SIR_GP_INT_0 = 544,0,1,0 %; macro COREIO$V_SIR_GP_INT_1 = 544,1,1,0 %; macro COREIO$V_SIR_GP_INT_2 = 544,2,1,0 %; macro COREIO$V_SIR_GP_INT_3 = 544,3,1,0 %; macro COREIO$V_SIR_GP_INT_4 = 544,4,1,0 %; macro COREIO$V_SIR_GP_INT_5 = 544,5,1,0 %; macro COREIO$V_SIR_GP_INT_6 = 544,6,1,0 %; macro COREIO$V_SIR_GP_INT_7 = 544,7,1,0 %; macro COREIO$V_SIR_GP_INT_8 = 544,8,1,0 %; macro COREIO$V_SIR_GP_INT_9 = 544,9,1,0 %; macro COREIO$V_SIR_GP_INT_10 = 544,10,1,0 %; macro COREIO$V_SIR_GP_INT_11 = 544,11,1,0 %; macro COREIO$V_SIR_GP_INT_12 = 544,12,1,0 %; macro COREIO$V_SIR_GP_INT_13 = 544,13,1,0 %; macro COREIO$V_SIR_GP_INT_14 = 544,14,1,0 %; macro COREIO$V_SIR_GP_INT_15 = 544,15,1,0 %; macro COREIO$V_SIR_LANCE_DMA_ER = 544,16,1,0 %; macro COREIO$V_SIR_SCSI_DMA_MRE = 544,17,1,0 %; macro COREIO$V_SIR_SCSI_DMA_OV = 544,18,1,0 %; macro COREIO$V_SIR_SCSI_DMA_PTR = 544,19,1,0 %; macro COREIO$V_SIR_ISDN_DMA_MRE = 544,20,1,0 %; macro COREIO$V_SIR_ISDN_DMA_RC_INTR = 544,21,1,0 %; macro COREIO$V_SIR_ISDN_DMA_TR_INTR = 544,22,1,0 %; macro COREIO$V_SIR_FLOPPY_DMA_INT = 544,23,1,0 %; macro COREIO$V_SIR_SCC1_DMA_OV = 544,24,1,0 %; macro COREIO$V_SIR_SCC1_RCV_INT = 544,25,1,0 %; macro COREIO$V_SIR_SCC1_TR_DMA_ME = 544,26,1,0 %; macro COREIO$V_SIR_SCC1_TR_INT = 544,27,1,0 %; macro COREIO$V_SIR_SCC0_DMA_OV = 544,28,1,0 %; macro COREIO$V_SIR_SCC0_RCV_INT = 544,29,1,0 %; macro COREIO$V_SIR_SCC0_TR_DMA_ME = 544,30,1,0 %; macro COREIO$V_SIR_SCC0_TR_INT = 544,31,1,0 %; macro COREIO$V_SIR_HALT0 = 544,0,1,0 %; macro COREIO$V_SIR_HALT1 = 544,1,1,0 %; macro COREIO$V_SIR_ALT_CONSOLE = 544,3,1,0 %; macro COREIO$V_SIR_SCC0_SI = 544,6,1,0 %; macro COREIO$V_SIR_SCC1_SI = 544,7,1,0 %; macro COREIO$V_SIR_NI_INTR = 544,8,1,0 %; macro COREIO$V_SIR_ISDN_INTR = 544,13,1,0 %; macro COREIO$V_SIR_LANCE_DMA_RE = 544,16,1,0 %; macro COREIO$V_SIR_PP_RC_DMA_OVR = 544,24,1,0 %; macro COREIO$V_SIR_PP_RC_HP_INTR = 544,25,1,0 %; macro COREIO$V_SIR_PP_TR_DMA_MRE = 544,26,1,0 %; macro COREIO$V_SIR_PP_TR_PE_INTR = 544,27,1,0 %; macro COREIO$V_SIR_COMM_RC_DMA_OVR = 544,28,1,0 %; macro COREIO$V_SIR_COMM_RC_HP_INTR = 544,29,1,0 %; macro COREIO$V_SIR_COMM_TR_DMA_MRE = 544,30,1,0 %; macro COREIO$V_SIR_COMM_TR_PE_INTR = 544,31,1,0 %; macro COREIO$V_SIR_TC_SLOT0 = 544,2,1,0 %; macro COREIO$V_SIR_TC_SLOT1 = 544,3,1,0 %; macro COREIO$V_SIR_SCC0_INT = 544,6,1,0 %; macro COREIO$V_SIR_SCC1_INT = 544,7,1,0 %; macro COREIO$V_SIR_LANCE_INT = 544,8,1,0 %; macro COREIO$V_SIR_ISDN_INT = 544,13,1,0 %; macro COREIO$V_SIR_CONS_SEL = 544,15,1,0 %; macro COREIO$L_SIMR = 576,0,32,0 %; ! System interrupt mask register macro COREIO$V_SIMR_GP_INT_0 = 576,0,1,0 %; macro COREIO$V_SIMR_GP_INT_1 = 576,1,1,0 %; macro COREIO$V_SIMR_GP_INT_2 = 576,2,1,0 %; macro COREIO$V_SIMR_GP_INT_3 = 576,3,1,0 %; macro COREIO$V_SIMR_GP_INT_4 = 576,4,1,0 %; macro COREIO$V_SIMR_GP_INT_5 = 576,5,1,0 %; macro COREIO$V_SIMR_GP_INT_6 = 576,6,1,0 %; macro COREIO$V_SIMR_GP_INT_7 = 576,7,1,0 %; macro COREIO$V_SIMR_GP_INT_8 = 576,8,1,0 %; macro COREIO$V_SIMR_GP_INT_9 = 576,9,1,0 %; macro COREIO$V_SIMR_GP_INT_10 = 576,10,1,0 %; macro COREIO$V_SIMR_GP_INT_11 = 576,11,1,0 %; macro COREIO$V_SIMR_GP_INT_12 = 576,12,1,0 %; macro COREIO$V_SIMR_GP_INT_13 = 576,13,1,0 %; macro COREIO$V_SIMR_GP_INT_14 = 576,14,1,0 %; macro COREIO$V_SIMR_GP_INT_15 = 576,15,1,0 %; macro COREIO$V_SIMR_LANCE_DMA_ER = 576,16,1,0 %; macro COREIO$V_SIMR_SCSI_DMA_MRE = 576,17,1,0 %; macro COREIO$V_SIMR_SCSI_DMA_OV = 576,18,1,0 %; macro COREIO$V_SIMR_SCSI_DMA_PTR = 576,19,1,0 %; macro COREIO$V_SIMR_ISDN_DMA_MRE = 576,20,1,0 %; macro COREIO$V_SIMR_ISDN_DMA_RC_INTR = 576,21,1,0 %; macro COREIO$V_SIMR_ISDN_DMA_TR_INTR = 576,22,1,0 %; macro COREIO$V_SIMR_FLOPPY_DMA_INT = 576,23,1,0 %; macro COREIO$V_SIMR_SCC1_DMA_OV = 576,24,1,0 %; macro COREIO$V_SIMR_SCC1_RCV_INT = 576,25,1,0 %; macro COREIO$V_SIMR_SCC1_TR_DMA_ME = 576,26,1,0 %; macro COREIO$V_SIMR_SCC1_TR_INT = 576,27,1,0 %; macro COREIO$V_SIMR_SCC0_DMA_OV = 576,28,1,0 %; macro COREIO$V_SIMR_SCC0_RCV_INT = 576,29,1,0 %; macro COREIO$V_SIMR_SCC0_TR_DMA_ME = 576,30,1,0 %; macro COREIO$V_SIMR_SCC0_TR_INT = 576,31,1,0 %; macro COREIO$V_SIMR_HALT0 = 576,0,1,0 %; macro COREIO$V_SIMR_HALT1 = 576,1,1,0 %; macro COREIO$V_SIMR_ALT_CONSOLE = 576,3,1,0 %; macro COREIO$V_SIMR_SCC0_SI = 576,6,1,0 %; macro COREIO$V_SIMR_SCC1_SI = 576,7,1,0 %; macro COREIO$V_SIMR_NI_INTR = 576,8,1,0 %; macro COREIO$V_SIMR_ISDN_INTR = 576,13,1,0 %; macro COREIO$V_SIMR_LANCE_DMA_RE = 576,16,1,0 %; macro COREIO$V_SIMR_PP_RC_DMA_OVR = 576,24,1,0 %; macro COREIO$V_SIMR_PP_RC_HP_INTR = 576,25,1,0 %; macro COREIO$V_SIMR_PP_TR_DMA_MRE = 576,26,1,0 %; macro COREIO$V_SIMR_PP_TR_PE_INTR = 576,27,1,0 %; macro COREIO$V_SIMR_COMM_RC_DMA_OVR = 576,28,1,0 %; macro COREIO$V_SIMR_COMM_RC_HP_INTR = 576,29,1,0 %; macro COREIO$V_SIMR_COMM_TR_DMA_MRE = 576,30,1,0 %; macro COREIO$V_SIMR_COMM_TR_PE_INTR = 576,31,1,0 %; macro COREIO$V_SIMR_TC_SLOT0 = 576,2,1,0 %; macro COREIO$V_SIMR_TC_SLOT1 = 576,3,1,0 %; macro COREIO$V_SIMR_SCC0_INT = 576,6,1,0 %; macro COREIO$V_SIMR_SCC1_INT = 576,7,1,0 %; macro COREIO$V_SIMR_LANCE_INT = 576,8,1,0 %; macro COREIO$V_SIMR_ISDN_INT = 576,13,1,0 %; macro COREIO$V_SIMR_CONS_SEL = 576,15,1,0 %; macro COREIO$L_SADR = 608,0,32,0 %; ! System address register macro COREIO$V_SADR_TC_ADDR = 608,5,20,0 %; literal COREIO$S_SADR_TC_ADDR = 20; macro COREIO$L_ISDN_DATA_TR = 640,0,32,0 %; ! ISDN Data Transmit macro COREIO$V_ISDN_DATA_TR_DATA = 640,0,24,0 %; literal COREIO$S_ISDN_DATA_TR_DATA = 24; macro COREIO$L_ISDN_DATA_RC = 672,0,32,0 %; ! ISDN Data Receive macro COREIO$V_ISDN_DATA_RC_DATA = 672,0,24,0 %; literal COREIO$S_ISDN_DATA_RC_DATA = 24; macro COREIO$L_LANCE_SLOT = 704,0,32,0 %; ! Lance slot register macro COREIO$V_LANCE_SLOT_CS = 704,0,4,0 %; literal COREIO$S_LANCE_SLOT_CS = 4; macro COREIO$V_LANCE_SLOT_HW_ADDR = 704,4,6,0 %; literal COREIO$S_LANCE_SLOT_HW_ADDR = 6; macro COREIO$L_SCC0_SLOT = 768,0,32,0 %; ! SCC0 slot register macro COREIO$V_SCC0_SLOT_CS = 768,0,4,0 %; literal COREIO$S_SCC0_SLOT_CS = 4; macro COREIO$V_SCC0_SLOT_HW_ADDR = 768,4,6,0 %; literal COREIO$S_SCC0_SLOT_HW_ADDR = 6; macro COREIO$L_SCC1_SLOT = 800,0,32,0 %; ! SCC1 slot register macro COREIO$V_SCC1_SLOT_CS = 800,0,4,0 %; literal COREIO$S_SCC1_SLOT_CS = 4; macro COREIO$V_SCC1_SLOT_HW_ADDR = 800,4,6,0 %; literal COREIO$S_SCC1_SLOT_HW_ADDR = 6; macro COREIO$L_NI_ADR_ROM = 8192,0,32,0 %; ! Ethernet address ROM macro COREIO$L_LANCE_RDP = 16384,0,32,0 %; ! Lance ethernet CSR macro COREIO$L_LANCE_RAP = 16392,0,32,0 %; ! Lance ethernet CSR macro COREIO$L_SCC0B_COMM_RAP = 24576,0,32,0 %; ! Comm Port 1 RAP macro COREIO$L_SCC0B_COMM_DATA = 24584,0,32,0 %; ! Comm Port 1 data macro COREIO$L_SCC0A_MOUSE_RAP = 24592,0,32,0 %; ! Mouse RAP macro COREIO$L_SCC0A_MOUSE_DATA = 24600,0,32,0 %; ! Mouse port data register macro COREIO$L_SCC1B_PRINT_RAP = 32768,0,32,0 %; ! Printer Port 2 RAP macro COREIO$L_SCC1B_PRINT_DATA = 32776,0,32,0 %; ! Printer Port 2 data macro COREIO$L_SCC1A_KEY_RAP = 32784,0,32,0 %; ! Keyboard RAP macro COREIO$L_SCC1A_KEY_DATA = 32792,0,32,0 %; ! Keyboard port data register macro COREIO$L_RTC_SEC = 40960,0,32,0 %; ! TOY clock CSR--seconds macro COREIO$L_RTC_ALMS = 40968,0,32,0 %; ! TOY clock CSR--seconds alarm macro COREIO$L_RTC_MIN = 40976,0,32,0 %; ! TOY clock CSR--minutes macro COREIO$L_RTC_ALMN = 40984,0,32,0 %; ! TOY clock CSR--minutes alarm macro COREIO$L_RTC_HOUR = 40992,0,32,0 %; ! TOY clock CSR--hours macro COREIO$L_RTC_ALMH = 41000,0,32,0 %; ! TOY clock CSR--hours alarm macro COREIO$L_RTC_DOW = 41008,0,32,0 %; ! TOY clock CSR--day of week macro COREIO$L_RTC_DAY = 41016,0,32,0 %; ! TOY clock CSR--date of month macro COREIO$L_RTC_MON = 41024,0,32,0 %; ! TOY clock CSR--month macro COREIO$L_RTC_YEAR = 41032,0,32,0 %; ! TOY clock CSR--year macro COREIO$L_RTC_REGA = 41040,0,32,0 %; ! TOY clock CSR--register A macro COREIO$L_RTC_REGB = 41048,0,32,0 %; ! TOY clock CSR--register B macro COREIO$L_RTC_REGC = 41056,0,32,0 %; ! TOY clock CSR--register C macro COREIO$L_RTC_REGD = 41064,0,32,0 %; ! TOY clock CSR--register D macro COREIO$L_RTC_RAM = 41072,0,32,0 %; ! TOY clock CSR--base of BBU RAM macro COREIO$L_ISDN_AUDIO = 49152,0,32,0 %; ! ISDN audio chip CSR !*** MODULE $CPBDEF *** ! + ! ! Constants defining CPU capability numbers and flags for routines ! literal CPB$C_PRIMARY = 0; ! Primary CPU (aka TIMEKEEPER) literal CPB$C_NS = 1; ! future literal CPB$C_QUORUM = 2; ! Cluster quorum required literal CPB$C_RUN = 3; ! Run capability literal CPB$C_IMPLICIT_AFFINITY = 4; ! Implicit affinity literal CPB$C_SOFT_RAD_AFFINITY = 5; ! If set, need to check further for soft RAD affinity literal CPB$C_RAD_0 = 6; literal CPB$C_RAD_1 = 7; literal CPB$C_RAD_2 = 8; literal CPB$C_RAD_3 = 9; literal CPB$C_RAD_4 = 10; literal CPB$C_RAD_5 = 11; literal CPB$C_RAD_6 = 12; literal CPB$C_RAD_7 = 13; literal CPB$C_MAX = 32; literal CPB$C_MAX_SYSTEM_BITS = 16; literal CPB$C_MAX_USER_BITS = 16; literal CPB$C_VECTOR = 1; ! equate NS with VECTOR literal CPB$M_PRIMARY = %X'1'; literal CPB$M_VECTOR = %X'2'; literal CPB$M_QUORUM = %X'4'; literal CPB$M_RUN = %X'8'; literal CPB$M_IMPLICIT_AFFINITY = %X'10'; literal CPB$M_SOFT_RAD_AFFINITY = %X'20'; literal CPB$M_RAD_0 = %X'40'; literal CPB$M_RAD_1 = %X'80'; literal CPB$M_RAD_2 = %X'100'; literal CPB$M_RAD_3 = %X'200'; literal CPB$M_RAD_4 = %X'400'; literal CPB$M_RAD_5 = %X'800'; literal CPB$M_RAD_6 = %X'1000'; literal CPB$M_RAD_7 = %X'2000'; literal CPB$M_THDS_IDLE = %X'4000'; literal CPB$S_CPBDEF = 4; literal CPB$S_CPB = 4; macro CPB$V_PRIMARY = 0,0,1,0 %; ! Primary (timekeeper) macro CPB$V_VECTOR = 0,1,1,0 %; ! Vector processor macro CPB$V_QUORUM = 0,2,1,0 %; ! Cluster quorum required macro CPB$V_RUN = 0,3,1,0 %; ! CPU can run processes macro CPB$V_IMPLICIT_AFFINITY = 0,4,1,0 %; ! Extended cap - implicit aff macro CPB$V_SOFT_RAD_AFFINITY = 0,5,1,0 %; ! Extended cap - Soft RAD affinity macro CPB$V_RAD_0 = 0,6,1,0 %; ! RAD in which a CPU resides. MUST REMAIN IN ORDER macro CPB$V_RAD_1 = 0,7,1,0 %; macro CPB$V_RAD_2 = 0,8,1,0 %; macro CPB$V_RAD_3 = 0,9,1,0 %; macro CPB$V_RAD_4 = 0,10,1,0 %; macro CPB$V_RAD_5 = 0,11,1,0 %; macro CPB$V_RAD_6 = 0,12,1,0 %; macro CPB$V_RAD_7 = 0,13,1,0 %; macro CPB$V_THDS_IDLE = 0,14,1,0 %; ! KTB must be alone on a core. Other CPU thds must be idle. literal CPB$M_FLAG_CHECK_CPU = %X'1'; literal CPB$M_FLAG_PERMANENT = %X'2'; literal CPB$M_FLAG_PRIMARY = %X'4'; literal CPB$M_FLAG_CHECK_CPU_ACTIVE = %X'8'; literal CPB$S_CPB_FLAGSDEF = 1; literal CPB$S_CPB_FLAGS = 1; macro CPB$V_FLAG_CHECK_CPU = 0,0,1,0 %; ! Check that process can run macro CPB$V_FLAG_PERMANENT = 0,1,1,0 %; ! Affect process permanent mask macro CPB$V_FLAG_PRIMARY = 0,2,1,0 %; ! Request to run on primary cpu macro CPB$V_FLAG_CHECK_CPU_ACTIVE = 0,3,1,0 %; ! Check all selected CPUs active macro CPB$V_FLAG_FILLER = 0,4,4,0 %; literal CPB$S_FLAG_FILLER = 4; ! *** ADD ALL NEW BITFIELDS BEFORE THIS DECLARATION ! *** THIS FIELD IS USED TO ASSURE MASKS ARE WITHIN RANGE !*** MODULE $CPUCOMDEF *** literal strlck$m_locked = %X'1'; literal strlck$S_structure_lock = 64; macro strlck$q_lock = 0,0,0,0 %; literal strlck$s_lock = 8; macro strlck$l_state = 0,0,32,0 %; ! State flags longword macro strlck$v_locked = 0,0,1,0 %; ! Last untested page is being tested macro strlck$l_owner = 4,0,32,0 %; ! Partition ID of owning instance macro strlck$q_owner_incarnation = 8,0,0,0 %; literal strlck$s_owner_incarnation = 8; ! Instance life - from node block literal strlck$c_LENGTH = 64; literal strlck$k_LENGTH = 64; literal lnkhdr$S_link_header = 24; macro lnkhdr$q_flink_offset = 0,0,0,0 %; literal lnkhdr$s_flink_offset = 8; ! Forward offset link macro lnkhdr$q_blink_offset = 8,0,0,0 %; literal lnkhdr$s_blink_offset = 8; ! Backward offset link macro lnkhdr$q_size = 16,0,0,0 %; literal lnkhdr$s_size = 8; ! Size of associated structure literal lnkhdr$c_LENGTH = 24; literal lnkhdr$k_LENGTH = 24; literal glxcomhdr$S_glxcomhdr = 240; macro glxcomhdr$q_joiners = 0,0,0,0 %; literal glxcomhdr$s_joiners = 8; ! Count of members who have joined macro glxcomhdr$w_mbo = 8,0,16,0 %; ! Must be 1 - implies quad size field macro glxcomhdr$b_type = 10,0,8,0 %; ! Dynamic structure type macro glxcomhdr$b_subtype = 11,0,8,0 %; ! Dynamic structure subtype macro glxcomhdr$q_size = 16,0,0,0 %; literal glxcomhdr$s_size = 8; ! Size of communication segment header macro glxcomhdr$q_state = 24,0,0,0 %; literal glxcomhdr$s_state = 8; ! State flags quadword macro glxcomhdr$q_gmd_array_offset = 32,0,0,0 %; literal glxcomhdr$s_gmd_array_offset = 8; ! Offset to GMD array macro glxcomhdr$q_gcb_array_offset = 40,0,0,0 %; literal glxcomhdr$s_gcb_array_offset = 8; ! Offset to GCB array macro glxcomhdr$q_active_set_offset = 48,0,0,0 %; literal glxcomhdr$s_active_set_offset = 8; ! Offset to active set CBB macro glxcomhdr$r_segment_lock = 64,0,0,0 %; literal glxcomhdr$s_segment_lock = 64; ! Lock structure on cache block boundary macro glxcomhdr$r_pool_lock = 128,0,0,0 %; literal glxcomhdr$s_pool_lock = 64; ! Lock structure on cache block boundary macro glxcomhdr$r_free_pool = 192,0,0,0 %; literal glxcomhdr$s_free_pool = 24; ! Listhead for self-relative free blocks macro glxcomhdr$q_allocated_pool = 216,0,0,0 %; literal glxcomhdr$s_allocated_pool = 8; ! Bytes of pool currently allocated macro glxcomhdr$q_max_pool = 224,0,0,0 %; literal glxcomhdr$s_max_pool = 8; ! Total shmem pool space macro glxcomhdr$q_max_dynamic_pool = 232,0,0,0 %; literal glxcomhdr$s_max_dynamic_pool = 8; ! Maximum shmem to be managed literal glxcomhdr$c_LENGTH = 240; literal glxcomhdr$k_LENGTH = 240; ! + ! ! Galaxy CPU block definition. This block is allocated ! and initialized when a CPU undergoes a state transition to a sharing ! node in a Galaxy configuration. ! - literal cpu_gcb$m_notify_packet = %X'1'; literal cpu_gcb$m_cpu_in_transition = %X'1'; literal cpu_gcb$S_cpu_gcb = 152; macro cpu_gcb$q_event_bits = 0,0,0,0 %; literal cpu_gcb$s_event_bits = 8; ! CPU notification bits macro cpu_gcb$v_notify_packet = 0,0,1,0 %; ! GMP listhead contains packet macro cpu_gcb$w_size = 8,0,16,0 %; ! Structure size macro cpu_gcb$b_type = 10,0,8,0 %; ! Structure type macro cpu_gcb$b_subtype = 11,0,8,0 %; ! Structure subtype macro cpu_gcb$l_owner_id = 12,0,32,0 %; ! Owner node ID macro cpu_gcb$l_state = 16,0,32,0 %; ! State bitmask macro cpu_gcb$v_cpu_in_transition = 16,0,1,0 %; ! Restricted access macro cpu_gcb$r_gmp_listhead = 128,0,0,0 %; literal cpu_gcb$s_gmp_listhead = 24; ! Listhead for message packets literal cpu_gcb$c_LENGTH = 152; literal cpu_gcb$k_LENGTH = 152; ! + ! ! Galaxy Member Data block definition. This block is allocated ! and initialized when a node joins a Galaxy community ! - literal cpu_gmd$m_active = %X'1'; literal cpu_gmd$S_cpu_gmd = 152; macro cpu_gmd$l_state = 0,0,32,0 %; ! State flags quadword macro cpu_gmd$v_active = 0,0,1,0 %; ! Segment is in use macro cpu_gmd$l_primary_cpuid = 4,0,32,0 %; ! CPU ID for this node macro cpu_gmd$w_size = 8,0,16,0 %; ! Structure size macro cpu_gmd$b_type = 10,0,8,0 %; ! Structure type macro cpu_gmd$b_subtype = 11,0,8,0 %; ! Structure subtype macro cpu_gmd$q_gpd_offset = 16,0,0,0 %; literal cpu_gmd$s_gpd_offset = 8; ! Offset to GPD structure macro cpu_gmd$r_gmp_listhead = 128,0,0,0 %; literal cpu_gmd$s_gmp_listhead = 24; ! Listhead for message packets literal cpu_gmd$c_LENGTH = 152; literal cpu_gmd$k_LENGTH = 152; ! + ! ! Galaxy Message Packet block definition. ! - literal cpu_gmp$m_no_local_copy = %X'1'; literal cpu_gmp$S_cpu_gmp = 72; macro cpu_gmp$r_gmp_queue = 0,0,0,0 %; literal cpu_gmp$s_gmp_queue = 24; ! Listhead for message packets macro cpu_gmp$l_state = 24,0,32,0 %; ! State bitmask macro cpu_gmp$v_no_local_copy = 24,0,1,0 %; ! Don't copy packet to nonpaged pool macro cpu_gmp$l_component_id = 28,0,32,0 %; ! CPU ID for this node macro cpu_gmp$l_source_id = 32,0,32,0 %; ! Partition ID of source macro cpu_gmp$l_target_id = 36,0,32,0 %; ! Partition ID of target macro cpu_gmp$q_incarnation = 40,0,0,0 %; literal cpu_gmp$s_incarnation = 8; ! Instance incarnation of target macro cpu_gmp$q_data_length = 48,0,0,0 %; literal cpu_gmp$s_data_length = 8; ! Size of data in this GMP macro cpu_gmp$q_data_offset = 56,0,0,0 %; literal cpu_gmp$s_data_offset = 8; ! Size of data in this GMP macro cpu_gmp$A_data = 64,0,0,0 %; literal cpu_gmp$s_data = 8; ! Beginning of block data literal cpu_gmp$c_LENGTH = 72; literal cpu_gmp$k_LENGTH = 72; ! + ! ! Galaxy Packet Dispatch block definition. ! - literal cpu_gpd$S_cpu_gpd = 16; macro cpu_gpd$l_max_slots = 0,0,32,0 %; ! maximum dispatch slots in struct macro cpu_gpd$l_size = 4,0,32,0 %; ! structure size macro cpu_gpd$A_routines = 8,0,0,0 %; literal cpu_gpd$s_routines = 8; ! Array of quad routines literal cpu_gpd$c_LENGTH = 16; literal cpu_gpd$k_LENGTH = 16; !*** MODULE $CQBICDEF *** ! ++ ! CQBIC definitions ! -- ! Offsets within page containing interprocessor doorbell registers literal CQBIC$W_INTPR0 = 320; ! Arbiter doorbell literal CQBIC$W_INTPR1 = 322; ! Auxiliary #1 doorbell literal CQBIC$W_INTPR2 = 324; ! Auxiliary #2 doorbell literal CQBIC$W_INTPR3 = 326; ! Auxiliary #3 doorbell literal CQBIC$W_INTPR4 = 328; ! Auxiliary #4 doorbell literal CQBIC$W_INTPR5 = 330; ! Auxiliary #5 doorbell literal CQBIC$W_INTPR6 = 332; ! Auxiliary #6 doorbell literal CQBIC$W_INTPR7 = 334; ! Auxiliary #7 doorbell ! Offsets within page containing SCR, memory and map registers literal CQBIC$L_SCR = 0; ! System configuration literal CQBIC$L_DSER = 4; ! DMA system error literal CQBIC$L_MEAR = 8; ! DMA master error literal CQBIC$L_SEAR = 12; ! DMA slave error literal CQBIC$L_MAP_BASE = 16; ! Scatter/gather map base literal CQBIC$M_INTPR_DBIRQ = %X'1'; literal CQBIC$M_INTPR_LMEAE = %X'20'; literal CQBIC$M_INTPR_DBIIE = %X'40'; literal CQBIC$M_INTPR_AUXHLT = %X'100'; literal CQBIC$M_INTPR_TBIA = %X'4000'; literal CQBIC$M_INTPR_DMAQME = %X'8000'; literal CQBIC$S_INTPR = 2; macro CQBIC$V_INTPR_DBIRQ = 0,0,1,0 %; ! Doorbell interrupt request macro CQBIC$V_INTPR_MBZ_1 = 0,1,4,0 %; literal CQBIC$S_INTPR_MBZ_1 = 4; macro CQBIC$V_INTPR_LMEAE = 0,5,1,0 %; ! Local memory enable macro CQBIC$V_INTPR_DBIIE = 0,6,1,0 %; ! Doorbell interrupt enable macro CQBIC$V_INTPR_MBZ_2 = 0,7,1,0 %; macro CQBIC$V_INTPR_AUXHLT = 0,8,1,0 %; ! Auxiliary halt macro CQBIC$V_INTPR_MBZ_3 = 0,9,5,0 %; literal CQBIC$S_INTPR_MBZ_3 = 5; macro CQBIC$V_INTPR_TBIA = 0,14,1,0 %; ! Xlate buffer invalidate all macro CQBIC$V_INTPR_DMAQME = 0,15,1,0 %; ! DMA memory space error !*** MODULE $CRAMDEF *** ! + ! CRAM - CSR Register Access Mailbox ! ! The CSR register access mailbox describes the remote I/O CSR access to be ! performed. ! ! - literal CRAM$M_IN_USE = %X'1'; literal CRAM$M_DER = %X'2'; literal CRAM$M_CMD_VAL = %X'3FFFFFFF'; literal CRAM$M_CMD_BRIDGE = %X'40000000'; literal CRAM$M_CMD_WRITE = %X'80000000'; literal CRAM$M_MBX_DONE = %X'1'; literal CRAM$M_MBX_ERROR = %X'2'; literal CRAM$K_LENGTH = 128; ! Length of structure literal CRAM$S_CRAMDEF = 128; ! Old CRAM size field for compatibility ! Define common command indices literal CRAMCMD$K_RDQUAD32 = 1; ! Quadword read in 32 bit space literal CRAMCMD$K_RDLONG32 = 2; ! Longword " " " " " literal CRAMCMD$K_RDWORD32 = 3; ! Word " " " " " literal CRAMCMD$K_RDBYTE32 = 4; ! Byte " " " " " literal CRAMCMD$K_WTQUAD32 = 5; ! Quadword write " " " " literal CRAMCMD$K_WTLONG32 = 6; ! Longword " " " " " literal CRAMCMD$K_WTWORD32 = 7; ! Word " " " " " literal CRAMCMD$K_WTBYTE32 = 8; ! Byte " " " " " literal CRAMCMD$K_RDQUAD64 = 9; ! Quadword read in 64 bit space literal CRAMCMD$K_RDLONG64 = 10; ! Longword " " " " " literal CRAMCMD$K_RDWORD64 = 11; ! Word " " " " " literal CRAMCMD$K_RDBYTE64 = 12; ! Byte " " " " " literal CRAMCMD$K_WTQUAD64 = 13; ! Quadword write " " " " literal CRAMCMD$K_WTLONG64 = 14; ! Longword " " " " " literal CRAMCMD$K_WTWORD64 = 15; ! Word " " " " " literal CRAMCMD$K_WTBYTE64 = 16; ! Byte " " " " " literal CRAMCMD$K_RDTRIBYTE32 = 17; ! Tribyte read " 32 " " literal CRAMCMD$K_WTTRIBYTE32 = 18; ! Tribyte write " 32 " " literal CRAMCMD$K_RDTRIBYTE64 = 19; ! Tribyte read " 64 " " literal CRAMCMD$K_WTTRIBYTE64 = 20; ! Tribyte write " 64 " " literal CRAMCMD$K_MININDEX = 1; literal CRAMCMD$K_MAXINDEX = 20; literal CRAM$S_CRAM = 128; macro CRAM$L_FLINK = 0,0,32,1 %; ! Forward link macro CRAM$L_BLINK = 4,0,32,1 %; ! Backward link macro CRAM$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro CRAM$B_TYPE = 10,0,8,0 %; ! Structure type macro CRAM$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro CRAM$L_MBPR = 12,0,32,1 %; ! Address of MBPR macro CRAM$Q_HW_MBX = 16,0,0,0 %; literal CRAM$S_HW_MBX = 8; ! PA of hardward mailbox macro CRAM$Q_QUEUE_TIME = 24,0,0,0 %; literal CRAM$S_QUEUE_TIME = 8; ! Queue timeout time macro CRAM$Q_WAIT_TIME = 32,0,0,0 %; literal CRAM$S_WAIT_TIME = 8; ! Wait timeout macro CRAM$L_DRIVER = 40,0,32,0 %; ! Spare longword for driver macro CRAM$L_IDB = 44,0,32,1 %; ! Pointer to IDB macro CRAM$L_UCB = 48,0,32,1 %; ! Pointer to UCB macro CRAM$R_CRAM_FLAGS_OVERLAY = 52,0,32,0 %; macro CRAM$L_CRAM_FLAGS = 52,0,32,0 %; ! Flags bitmask macro CRAM$V_IN_USE = 52,0,1,0 %; ! CRAM is valid macro CRAM$V_DER = 52,1,1,0 %; ! Disable-error-reporting macro CRAM$L_ADP = 56,0,32,1 %; ! Pointer to ADP ! This piece must be 64 byte aligned - this is the hardware mailbox macro CRAM$L_COMMAND = 64,0,32,0 %; ! Bus command macro CRAM$L_CMD_BITS = 64,0,32,0 %; macro CRAM$V_CMD_VAL = 64,0,30,0 %; literal CRAM$S_CMD_VAL = 30; ! Remote bus command bits macro CRAM$V_CMD_BRIDGE = 64,30,1,0 %; ! BRIDGE bit macro CRAM$V_CMD_WRITE = 64,31,1,0 %; ! WRITE bit macro CRAM$B_BYTE_MASK = 68,0,8,0 %; ! Active byte mask macro CRAM$B_HOSE = 70,0,8,0 %; ! I/O bus number macro CRAM$Q_RBADR = 72,0,0,0 %; literal CRAM$S_RBADR = 8; ! Remote bus address macro CRAM$Q_WDATA = 80,0,0,0 %; literal CRAM$S_WDATA = 8; ! Data to be written macro CRAM$L_WDATA = 80,0,32,0 %; ! Data to be written macro CRAM$W_WDATA = 80,0,16,0 %; ! Data to be written macro CRAM$B_WDATA = 80,0,8,0 %; ! Data to be written macro CRAM$Q_RDATA = 96,0,0,0 %; literal CRAM$S_RDATA = 8; ! Returned read data macro CRAM$L_RDATA = 96,0,32,0 %; macro CRAM$W_RDATA = 96,0,16,0 %; macro CRAM$B_RDATA = 96,0,8,0 %; macro CRAM$W_MBX_FLAGS = 104,0,16,0 %; ! Flags bitmask macro CRAM$V_MBX_DONE = 104,0,1,0 %; ! Mailbox operation completed macro CRAM$V_MBX_ERROR = 104,1,1,0 %; ! Error in operation macro CRAM$W_ERROR_BITS = 106,0,0,0 %; ! Device specific error bits ! Mailbox data structure used by hardware and bootstrap code literal HW_CRAM$M_MBX_DONE = %X'1'; literal HW_CRAM$M_MBX_ERROR = %X'2'; literal HW_CRAM$S_HW_CRAM = 64; macro HW_CRAM$L_COMMAND = 0,0,32,0 %; ! Bus command macro HW_CRAM$B_BYTE_MASK = 4,0,8,0 %; ! Active byte mask macro HW_CRAM$B_HOSE = 6,0,8,0 %; ! I/O bus number macro HW_CRAM$Q_RBADR = 8,0,0,0 %; literal HW_CRAM$S_RBADR = 8; ! Remote bus address macro HW_CRAM$Q_WDATA = 16,0,0,0 %; literal HW_CRAM$S_WDATA = 8; ! Data to be written macro HW_CRAM$Q_RDATA = 32,0,0,0 %; literal HW_CRAM$S_RDATA = 8; ! Returned read data macro HW_CRAM$W_MBX_FLAGS = 40,0,16,0 %; ! Flags bitmask macro HW_CRAM$V_MBX_DONE = 40,0,1,0 %; ! Mailbox operation completed macro HW_CRAM$V_MBX_ERROR = 40,1,1,0 %; ! Error in operation macro HW_CRAM$W_ERROR_BITS = 42,0,0,0 %; ! Device specific error bits literal HW_CRAM$K_LENGTH = 64; ! Length of structure literal HW_CRAM$S_HW_CRAMDEF = 64; ! Old HW_CRAM size field for compatibility ! Command table definition. Note -- the order of the longwords in the ! CMDARRAY vector must be the same as the order of the constant command ! indices defined above. ! literal CMDTABLEHEADER$K_LENGTH = 12; literal CMDTABLE$S_CMDTABLE = 96; macro CMDTABLE$PS_ADP = 0,0,32,1 %; macro CMDTABLE$L_BUS_TYPE = 4,0,32,0 %; ! Bus Type macro CMDTABLE$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro CMDTABLE$B_TYPE = 10,0,8,0 %; ! Structure type macro CMDTABLE$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro CMDTABLE$L_CMD_VECTOR = 12,0,0,0 %; ! beginning of vector of commands macro CRAMCMD$L_RDQUAD32 = 16,0,32,0 %; ! Quadword read in 32 bit space macro CRAMCMD$L_RDLONG32 = 20,0,32,0 %; ! Longword " " " " " macro CRAMCMD$L_RDWORD32 = 24,0,32,0 %; ! Word " " " " " macro CRAMCMD$L_RDBYTE32 = 28,0,32,0 %; ! Byte " " " " " macro CRAMCMD$L_WTQUAD32 = 32,0,32,0 %; ! Quadword write " " " " macro CRAMCMD$L_WTLONG32 = 36,0,32,0 %; ! Longword " " " " " macro CRAMCMD$L_WTWORD32 = 40,0,32,0 %; ! Word " " " " " macro CRAMCMD$L_WTBYTE32 = 44,0,32,0 %; ! Byte " " " " " macro CRAMCMD$L_RDQUAD64 = 48,0,32,0 %; ! Quadword read in 64 bit space macro CRAMCMD$L_RDLONG64 = 52,0,32,0 %; ! Longword " " " " " macro CRAMCMD$L_RDWORD64 = 56,0,32,0 %; ! Word " " " " " macro CRAMCMD$L_RDBYTE64 = 60,0,32,0 %; ! Byte " " " " " macro CRAMCMD$L_WTQUAD64 = 64,0,32,0 %; ! Quadword write " " " " macro CRAMCMD$L_WTLONG64 = 68,0,32,0 %; ! Longword " " " " " macro CRAMCMD$L_WTWORD64 = 72,0,32,0 %; ! Word " " " " " macro CRAMCMD$L_WTBYTE64 = 76,0,32,0 %; ! Byte " " " " " macro CRAMCMD$L_RDTRIBYTE32 = 80,0,32,0 %; ! Tribyte read " 32 " " macro CRAMCMD$L_WTTRIBYTE32 = 84,0,32,0 %; ! Tribyte write " 32 " " macro CRAMCMD$L_RDTRIBYTE64 = 88,0,32,0 %; ! Tribyte read " 64 " " macro CRAMCMD$L_WTTRIBYTE64 = 92,0,32,0 %; ! Tribyte write " 64 " " literal CMDTABLE$K_LENGTH = 96; ! Length of structure literal CMDTABLE$S_CMDTABLEDEF = 96; ! Old CMDTABLE size field for compatibility !*** MODULE $CRAMHDEF *** ! + ! CRAMH - CSR Regsiter Access Mailbox Header ! ! The CSR register access mailbox header describes the page of mailboxes ! ! - literal CRAMH$S_CRAMH = 128; macro CRAMH$L_FLINK = 0,0,32,1 %; ! Forward link macro CRAMH$L_BLINK = 4,0,32,1 %; ! Backward link macro CRAMH$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro CRAMH$B_TYPE = 10,0,8,0 %; ! Structure type macro CRAMH$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro CRAMH$L_MAX = 12,0,32,0 %; ! Mailbox max index macro CRAMH$Q_PA_BASE = 16,0,0,0 %; literal CRAMH$S_PA_BASE = 8; ! Base PA of page macro CRAMH$L_AVAIL = 24,0,32,0 %; ! Mailboxes available macro CRAMH$B_MAP = 28,0,0,0 %; literal CRAMH$S_MAP = 64; ! Usage bitmap ! Sized for 64KB page max literal CRAMH$K_LENGTH = 128; ! Length of structure !*** MODULE $CRBDEF *** ! + ! CRB - CHANNEL REQUEST BLOCK ! ! THERE IS ONE CHANNEL REQUEST BLOCK FOR EACH SET OF DEVICES WHOSE ! ACCESS TO A SET OF CONTROLLERS MUST BE SYNCHRONIZED. EACH CHANNEL ! CONTROL BLOCK ALLOWS UP TO FOUR CONTROLLERS TO WHICH THE INDIVIDUAL ! DEVICES CAN BE ATTACHED. ! - literal CRB$M_XZA_CHAN0 = %X'1'; literal CRB$M_XZA_CHAN1 = %X'2'; literal CRB$M_XZA_ADPERR = %X'4'; literal CRB$M_BSY = %X'1'; literal CRB$M_UNINIT = %X'2'; literal CRB$K_VEC1_OFFSET = 112; ! Offset to first interrupt block literal CRB$K_LENGTH = 128; ! LENGTH OF STANDARD CRB literal CRB$C_LENGTH = 128; ! LENGTH OF STANDARD CRB literal CRB$K_SHR_FLINK_OFFSET = 144; literal CRB$K_SHR_BLINK_OFFSET = 148; literal CRB$M_SHARED_INT = %X'1'; literal CRB$M_DISABLE_INT = %X'2'; literal CRB$M_SHARED_QUEUE = %X'4'; literal CRB$S_CRB = 160; macro CRB$L_FQFL = 0,0,32,1 %; ! FORK QUEUE FORWARD LINK macro CRB$L_FQBL = 4,0,32,1 %; ! FORK QUEUE BACKWARD LINK macro CRB$W_SIZE = 8,0,16,0 %; ! SIZE OF CRB IN BYTES macro CRB$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE FOR CRB macro CRB$B_FLCK = 11,0,8,0 %; ! FORK LOCK NUMBER macro CRB$L_FPC = 12,0,32,1 %; ! FORK PC macro CRB$Q_FR3 = 16,0,0,1 %; literal CRB$S_FR3 = 8; ! FORK R3 macro CRB$Q_FR4 = 24,0,0,1 %; literal CRB$S_FR4 = 8; ! FORK R4 macro CRB$L_WQFL = 32,0,32,1 %; ! WAIT QUEUE FORWARD LINK macro CRB$L_WQBL = 36,0,32,1 %; ! WAIT QUEUE BACKWARD LINK macro CRB$B_TT_TYPE = 40,0,8,0 %; macro CRB$L_TT_TYPE = 40,0,32,0 %; ! controler type (DZ11, DZ32) macro CRB$L_XZA_STS = 40,0,32,0 %; ! Coordination for XZA driver macro CRB$V_XZA_CHAN0 = 40,0,1,0 %; ! Channel 0 reinit flag macro CRB$V_XZA_CHAN1 = 40,1,1,0 %; ! Channel 1 reinit flag macro CRB$V_XZA_ADPERR = 40,2,1,0 %; ! XZA error/reset flag macro CRB$L_REFC = 44,0,32,0 %; ! REFERENCE COUNT OF UCB'S macro CRB$W_REFC = 44,0,16,0 %; macro CRB$B_MASK = 48,0,8,0 %; macro CRB$L_MASK = 48,0,32,0 %; ! CHANNEL ALLOCATION MASK macro CRB$V_BSY = 48,0,1,0 %; ! CHANNEL IS BUSY (1=YES) macro CRB$V_UNINIT = 48,1,1,0 %; ! GENBI CRB is uninitialized. (1=YES) macro CRB$PS_BUSARRAY = 52,0,32,1 %; ! Bus array for SCSI ports macro CRB$Q_AUXSTRUC = 56,0,0,1 %; literal CRB$S_AUXSTRUC = 8; ! Auxiliary structure addr macro CRB$L_AUXSTRUC = 56,0,32,0 %; macro CRB$PS_AUXSTRUC = 56,0,32,1 %; macro CRB$Q_LAN_STRUC = 64,0,0,1 %; literal CRB$S_LAN_STRUC = 8; ! Auxiliary pointer for LAN drivers macro CRB$L_LAN_STRUC = 64,0,32,0 %; macro CRB$PS_LAN_STRUC = 64,0,32,1 %; macro CRB$Q_SCS_STRUC = 72,0,0,1 %; literal CRB$S_SCS_STRUC = 8; macro CRB$L_SCS_STRUC = 72,0,32,0 %; macro CRB$PS_SCS_STRUC = 72,0,32,1 %; macro CRB$L_TIMELINK = 80,0,32,1 %; ! Thread of CRB's for periodic wakeup macro CRB$L_TT_MODEM = 80,0,32,1 %; ! modem control timer thread macro CRB$L_NODE = 84,0,32,0 %; ! node number on bus macro CRB$L_DUETIME = 88,0,32,0 %; ! Due time for periodic wakeup macro CRB$PS_SYSG_DBLK = 88,0,32,1 %; ! workstation SLU port driver/DW interface macro CRB$L_TOUTROUT = 92,0,32,1 %; ! Address of periodic wakeup routine macro CRB$L_TT_TIMREFC = 92,0,32,0 %; ! lines with active modem timers macro CRB$PS_DLCK = 96,0,32,1 %; ! ADDRESS OF DEVICE SPINLOCK macro CRB$PS_CRB_LINK = 100,0,32,1 %; ! pointer to next CRB on ADP macro CRB$Q_CTRLR_SHUTDOWN = 104,0,0,1 %; literal CRB$S_CTRLR_SHUTDOWN = 8; ! Address of controller shutdown routine macro CRB$PS_CTRLR_SHUTDOWN = 104,0,32,1 %; macro CRB$L_INTD = 112,0,0,0 %; literal CRB$S_INTD = 16; ! DEFAULT TRANSFER VECTOR START macro CRB$L_INTD2 = 128,0,0,0 %; literal CRB$S_INTD2 = 16; ! 2ND DEFAULT TRANSFER VECTOR START ! ! **** NOTE **** ! The following field MUST BE quadword aligned. Any modifications to the ! fields above this point must not move this field out of quad alingment. ! This is a queue entry that will be managed using the interlocked queue ! instructions (see sys$pal_insqtil) which require the flink of the queue ! to be qud aligned. ! ! For Shared Interrupt support, CRBs whose devices must share an interrupt ! will be queued using the following fields. The interrupt dispatcher ! will walk the queue of CRBs, unpackaging each VEC to call each ISR. ! ! The offset constants are used to calculate the pointer to the top of ! the CRB structure to gain access to its other fields, since the FLINK ! and BLINK queue fields will only point to other FLINK and BLINK fields ! in the queue. ! macro CRB$R_SHR_FLINK_OVERLAY = 144,0,32,0 %; macro CRB$L_SHR_FLINK = 144,0,32,1 %; macro CRB$PS_SHR_FLINK = 144,0,32,1 %; ! Forward Queue of Shared Interrupt CRBs. macro CRB$R_SHR_BLINK_OVERLAY = 148,0,32,0 %; macro CRB$L_SHR_BLINK = 148,0,32,1 %; macro CRB$PS_SHR_BLINK = 148,0,32,1 %; ! Backward Queue of Shared Interrupt CRBs. macro CRB$R_FLAGS_OVERLAY = 152,0,0,0 %; macro CRB$Q_FLAGS = 152,0,0,0 %; literal CRB$S_FLAGS = 8; macro CRB$V_SHARED_INT = 152,0,1,0 %; ! Driver supports shared interrupts macro CRB$V_DISABLE_INT = 152,1,1,0 %; ! Device Driver does not want to be disturbed macro CRB$V_SHARED_QUEUE = 152,2,1,0 %; ! CRB is in a shared interrupt queue literal CRB$S_CRBDEF = 160; ! OLD CRB SIZE FOR COMPATIBILITY !*** MODULE $CRCTXDEF *** literal CRCTX$M_HIGH_PRIO = %X'1'; literal CRCTX$M_ITEM_VALID = %X'2'; literal CRCTX$S_CRCTX = 96; macro CRCTX$L_FLINK = 0,0,32,1 %; ! Forward link macro CRCTX$L_BLINK = 4,0,32,1 %; ! Backward link macro CRCTX$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro CRCTX$B_TYPE = 10,0,8,0 %; ! Structure type macro CRCTX$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro CRCTX$L_CRAB = 12,0,32,1 %; ! Address of CRAB macro CRCTX$B_FLCK = 16,0,8,0 %; ! FORK LOCK NUMBER macro CRCTX$L_FLCK = 16,0,32,0 %; ! FORK LOCK NUMBER macro CRCTX$L_FLAGS = 20,0,32,1 %; ! macro CRCTX$V_HIGH_PRIO = 20,0,1,0 %; ! High priority request, attempt to ! allocate resource immediately, ! without regard for whether there ! are other threads waiting. macro CRCTX$V_ITEM_VALID = 20,1,1,0 %; ! Flag to indicate that the item ! number and count fields are valid. ! Used for sanity check by DEALLOC_CNT_RES. ! ! macro CRCTX$L_WQFL = 24,0,32,1 %; ! Stalled requests are queued macro CRCTX$L_WQBL = 28,0,32,1 %; ! to CRAB wait queue with these links macro CRCTX$L_CONTEXT1 = 32,0,32,1 %; macro CRCTX$Q_CONTEXT1 = 32,0,0,1 %; literal CRCTX$S_CONTEXT1 = 8; macro CRCTX$L_CONTEXT2 = 40,0,32,1 %; macro CRCTX$Q_CONTEXT2 = 40,0,0,1 %; literal CRCTX$S_CONTEXT2 = 8; macro CRCTX$L_CONTEXT3 = 48,0,32,1 %; macro CRCTX$Q_CONTEXT3 = 48,0,0,1 %; literal CRCTX$S_CONTEXT3 = 8; macro CRCTX$L_ITEM_CNT = 56,0,32,1 %; ! Count of allocated items macro CRCTX$L_ITEM_NUM = 60,0,32,1 %; ! First allocated item num macro CRCTX$L_UP_BOUND = 64,0,32,1 %; ! Allocation upper bound macro CRCTX$L_LOW_BOUND = 68,0,32,1 %; ! Allocation lower bound macro CRCTX$L_CALLBACK = 72,0,32,1 %; ! Callback address macro CRCTX$L_SAVED_CALLBACK = 76,0,32,1 %; ! Saved callback address macro CRCTX$L_AUX_CONTEXT = 80,0,32,1 %; ! Auxiliary context longword macro CRCTX$L_RESERVED1 = 84,0,32,1 %; ! Reserved longword macro CRCTX$L_DMA_ADR = 88,0,32,1 %; ! VMS-only - DMA adr. ret'd by LOAD_MAP macro CRCTX$PS_CALLER_PC = 92,0,32,1 %; ! PC of caller of (DE)ALLOC_CNT_RES literal CRCTX$K_LENGTH = 96; ! Length of structure literal CRCTX$S_CRCTXDEF = 96; ! Old size name, synonym literal CRCTX_BUF$S_CRCTX_BUF = 32; macro CRCTX_BUF$L_XACTION = 0,0,32,0 %; ! Contains ALLO or DEAL macro CRCTX_BUF$L_ITEM_NUM = 4,0,32,0 %; ! Contains CRCTX$L_ITEM_NUM macro CRCTX_BUF$L_ITEM_CNT = 8,0,32,0 %; ! Contains CRCTX$L_ITEM_CNT macro CRCTX_BUF$PS_CRCTX = 12,0,32,1 %; ! Address of CRCTX which made called ALLOC/DEALLOC macro CRCTX_BUF$PS_CALLER_PC = 16,0,32,1 %; ! Caller's PC, comes from CRCTX CALLER_PC field. macro CRCTX_BUF$L_STATUS = 20,0,32,0 %; ! Status ret'd by (DE)ALLOC_CNT_RES. macro CRCTX_BUF$L_DMA_ADDR = 24,0,32,0 %; ! DMA-able address macro CRCTX_BUF$L_COUNT = 28,0,32,0 %; ! The number of this entry literal CRCTX_BUF$K_LENGTH = 32; literal CRCTX_BUF_H$S_CRCTX_BUF_H = 24; macro CRCTX_BUF_H$Q_FREE = 0,0,0,1 %; literal CRCTX_BUF_H$S_FREE = 8; ! Address of the next free entry macro CRCTX_BUF_H$L_SIZE = 8,0,32,0 %; ! Size of the buffer macro CRCTX_BUF_H$L_RESERVED = 12,0,32,1 %; macro CRCTX_BUF_H$L_COUNT = 16,0,32,1 %; ! Number of the next entry to be written macro CRCTX_BUF_H$L_RESERVED2 = 20,0,32,1 %; !*** MODULE $VECDEF *** ! + ! CRB INTERRUPT TRANSFER VECTOR STRUCTURE DEFINITIONS ! - literal VEC$S_VEC = 16; ! CRB INTERRUPT TRANSFER VECTOR macro VEC$PS_ISR_CODE = 0,0,32,1 %; ! address of Interrupt Service Routine Code entry macro VEC$PS_ISR_PD = 4,0,32,1 %; ! address of ISR Procedure Descriptor macro VEC$L_IDB = 8,0,32,1 %; ! ADDRESS OF ASSOCIATED IDB macro VEC$PS_ADP = 12,0,32,1 %; ! ADDRESS OF ADP literal VEC$K_LENGTH = 16; ! LENGTH OF STANDARD DISPATCHER literal VEC$C_LENGTH = 16; ! LENGTH OF STANDARD DISPATCHER literal S_VECDEF = 16; ! OLD VEC SIZE NAME FOR COMPATIBILITY !*** MODULE $CTSIDEF *** literal CTSI$K_REVISION = 1; ! CTSI Revision 1 only. literal CTSI$C_REVISION = 1; literal CTMD$K_SIZE = 8; ! Size literal CTMD$C_SIZE = 8; ! Size literal CTMD$S_CTMD = 8; ! Module descriptor in the CTSIA. macro CTMD$W_PGCOUNT = 0,0,16,0 %; ! Module length in pages macro CTMD$L_BASEADDR = 4,0,32,1 %; ! Base physical addr. literal CTCB$K_SIZE = 28; ! Length of channel block literal CTCB$C_SIZE = 28; ! Length of channel block literal CTCB$S_CTCB = 28; ! Channel block in the CTSIA. macro CTCB$B_DVATR = 0,0,8,0 %; ! Device attributes macro CTCB$B_CHATR = 1,0,8,0 %; ! Channel attributes macro CTCB$W_STATESZ = 2,0,16,0 %; ! State size macro CTCB$L_PHY_ENTRY = 4,0,32,1 %; ! Physical entry point macro CTCB$L_VIR_ENTRY = 8,0,32,1 %; ! Virtual entry point macro CTCB$L_PHY_SEGMENT = 12,0,32,1 %; ! IO segment physical addr macro CTCB$L_VIR_SEGMENT = 16,0,32,1 %; ! IO segment virtual addr macro CTCB$L_PHY_EXTEND = 20,0,32,1 %; ! Extended state phys. addr macro CTCB$L_VIR_EXTEND = 24,0,32,1 %; ! Extended state virt. addr literal CTIOS$K_SIZE = 8; ! Descriptor length literal CTIOS$C_SIZE = 8; ! Descriptor length literal CTIOS$S_CTIOS = 8; ! Console I/O segment array and descriptors macro CTIOS$W_SGMT_COUNT = 0,0,16,0 %; ! # segments for channel macro CTIOS$B_BASE_SEGMENT = 4,0,8,0 %; ! Offset for first segment dx. macro CTIOS$W_PGCOUNT = 0,0,16,0 %; ! Pages in this segment macro CTIOS$L_SEGMENT = 4,0,32,1 %; ! Physical Segment address literal CTSI$K_MODULE_COUNT = 6; literal CTSI$C_MODULE_COUNT = 6; literal CTSI$K_CHN_COUNT = 6; literal CTSI$C_CHN_COUNT = 6; literal CTSI$M_CMUSE = %X'3'; literal CTSI$M_INUSE = %X'4'; literal CTSI$M_CM = %X'10'; literal CTSI$S_CTSIDEF = 316; ! Old size name - synonym literal CTSI$S_CTSI = 316; macro CTSI$L_BASE = 0,0,32,1 %; ! Physical base address of CTSI macro CTSI$W_SIZE = 4,0,16,0 %; ! Size in bytes of CTSI macro CTSI$W_IDENT = 6,0,16,0 %; ! Indent string "CT" macro CTSI$B_SPARE0 = 8,0,8,0 %; macro CTSI$B_CHKSUM = 9,0,8,0 %; ! Checksum of first bytes macro CTSI$B_FLAGS = 10,0,8,0 %; ! Flags macro CTSI$V_CMUSE = 10,0,2,0 %; literal CTSI$S_CMUSE = 2; macro CTSI$V_INUSE = 10,2,1,0 %; ! Routine in use macro CTSI$V_SPARE0 = 10,3,1,0 %; macro CTSI$V_CM = 10,4,1,0 %; ! Console mode macro CTSI$B_REVISN = 11,0,8,0 %; ! Console revision macro CTSI$Q_MODULE_DESC = 12,0,0,0 %; literal CTSI$S_MODULE_DESC = 48; ! Module descriptors macro CTSI$L_CHNBLK = 60,0,0,0 %; literal CTSI$S_CHNBLK = 168; ! Channel blocks of size = (7 longs) macro CTSI$Q_SAVE = 228,0,0,0 %; literal CTSI$S_SAVE = 8; ! Save ptrs macro CTSI$Q_RESTORE = 236,0,0,0 %; literal CTSI$S_RESTORE = 8; ! Restore pointers macro CTSI$Q_TRANS = 244,0,0,0 %; literal CTSI$S_TRANS = 8; ! Translate ptrs macro CTSI$Q_GETCHR = 252,0,0,0 %; literal CTSI$S_GETCHR = 8; ! GET CHAR ptrs macro CTSI$L_GETCHR_STATE = 260,0,0,0 %; literal CTSI$S_GETCHR_STATE = 16; ! GET CHAR state macro CTSI$Q_PUTCHR = 276,0,0,0 %; literal CTSI$S_PUTCHR = 8; ! PUT CHAR ptrs macro CTSI$L_PUTCHR_STATE = 284,0,0,0 %; literal CTSI$S_PUTCHR_STATE = 16; ! PUT CHAR state macro CTSI$Q_PUTMSG = 300,0,0,0 %; literal CTSI$S_PUTMSG = 8; ! Put message routine macro CTSI$Q_READPROMPT = 308,0,0,0 %; literal CTSI$S_READPROMPT = 8; ! Read with prompt routine !*** MODULE $CSCHEDDEF *** ! ++ ! The following structure is the format of the records in the class ! scheduler database file. The class record is the largest record. ! The qualifying records (username, account name, and UIC) are subsets ! of the class record. ! -- literal CSCHED$K_CLASS_NUMBER_POS = 2; literal CSCHED$K_CLASS_NUMSIZE = 2; literal CSCHED$K_NODE_NAME_POS = 4; literal CSCHED$K_NODE_RECORD = 20; ! End of Node record literal CSCHED$K_USER_NAME_POS = 20; literal CSCHED$K_USERNAME_RECORD = 52; ! End of User name record literal CSCHED$K_ACCOUNT_NAME_POS = 52; literal CSCHED$K_ACCOUNT_RECORD = 84; ! End of Account record literal CSCHED$K_UIC_POS = 84; literal CSCHED$K_UIC_GRP_POS = 86; literal CSCHED$K_UIC_SIZE = 4; literal CSCHED$K_UIC_RECORD = 88; ! End of UIC record literal CSCHED$M_WINDFALL = %X'1'; literal CSCHED$M_CLUSTER = %X'2'; literal CSCHED$M_DELPND = %X'4'; literal CSCHED$M_MONDAY = %X'1'; literal CSCHED$M_TUESDAY = %X'2'; literal CSCHED$M_WEDNESDAY = %X'4'; literal CSCHED$M_THURSDAY = %X'8'; literal CSCHED$M_FRIDAY = %X'10'; literal CSCHED$M_SATURDAY = %X'20'; literal CSCHED$M_SUNDAY = %X'40'; literal CSCHED$K_CLASS_NAME_POS = 144; literal CSCHED$K_CLASS_RECORD = 160; ! End of class record literal CSCHED$S_CSCHED = 160; macro CSCHED$W_RECORD_TYPE = 0,0,16,0 %; ! Record type (class, user, account, or UIC) macro CSCHED$W_CLASS_NUMBER = 2,0,16,0 %; ! Class number (values between 0 - 8191) macro CSCHED$T_NODE_NAME = 4,0,0,0 %; literal CSCHED$S_NODE_NAME = 16; ! Node name macro CSCHED$T_USER_NAME = 20,0,0,0 %; literal CSCHED$S_USER_NAME = 32; ! User name macro CSCHED$T_ACCOUNT = 52,0,0,0 %; literal CSCHED$S_ACCOUNT = 32; ! Account name (same as in the UAF file) macro CSCHED$L_UIC = 84,0,32,0 %; ! User's UIC value macro CSCHED$W_MEM = 84,0,16,0 %; ! Member number in UIC macro CSCHED$W_GRP = 86,0,16,0 %; ! Group number in UIC macro CSCHED$B_PRIMEDAY_CPULIMIT = 88,0,0,0 %; literal CSCHED$S_PRIMEDAY_CPULIMIT = 24; ! Cpu limits per hour for primary days macro CSCHED$B_SECONDAY_CPULIMIT = 112,0,0,0 %; literal CSCHED$S_SECONDAY_CPULIMIT = 24; ! Cpu limits per hour for secondary days macro CSCHED$L_FLAGS = 136,0,32,0 %; ! Flags field macro CSCHED$V_WINDFALL = 136,0,1,0 %; ! Enable windfall if this bit is set macro CSCHED$V_CLUSTER = 136,1,1,0 %; ! Class is valid cluster-wide macro CSCHED$V_DELPND = 136,2,1,0 %; ! Class is being deleted macro CSCHED$B_DAYS = 140,0,8,0 %; ! Days of the week that the class is valid macro CSCHED$V_MONDAY = 140,0,1,0 %; ! If bit is clear, day is a primary day. macro CSCHED$V_TUESDAY = 140,1,1,0 %; ! Otherwise, it's a secondary day. macro CSCHED$V_WEDNESDAY = 140,2,1,0 %; macro CSCHED$V_THURSDAY = 140,3,1,0 %; macro CSCHED$V_FRIDAY = 140,4,1,0 %; macro CSCHED$V_SATURDAY = 140,5,1,0 %; macro CSCHED$V_SUNDAY = 140,6,1,0 %; macro CSCHED$T_CLASS_NAME = 144,0,0,0 %; literal CSCHED$S_CLASS_NAME = 16; ! Name of scheduling class literal CSCHED$K_LENGTH = 160; ! Length of structure ! Values for each Record type are: literal CSCHED$K_CLASS = 1; literal CSCHED$K_USERNAME = 2; literal CSCHED$K_UIC = 3; literal CSCHED$K_ACCOUNT = 4; literal CSCHED$K_NODE = 5; ! Define a maximum number of classes. The class scheduler database file is ! designed to support an unlimited number of classes. However, we place a ! limit of the number of classes so that we can easily determine the size of ! the in-memory class scheduler arrays. ! literal CSCHED$K_MAX_SCHED_CLASSES = 256; ! ! The following 2 constants define the actual size of the user name and account ! name fields. The size of these fields is tied to the size of these same ! fields in the sysuaf.dat file. The Authorize image limits these names to ! 12 and 8 bytes respectively despite the fact that uafdef.sdl reserves 32 ! bytes for each of these fields in the sysuaf.dat file. If Authorize ever ! increases the limit on these fields, then these constants should be adjusted ! to match the new limits. ! literal CSCHED$K_USERNAME_REAL_SIZE = 12; literal CSCHED$K_ACCOUNT_REAL_SIZE = 8; ! ! This is the class scheduler's work area. The memory for this work ! area is allocated/deallocated by the SMIserver and will be used by ! the SMI object routines. This work area holds the RMS data structures ! used when reading/writing to the class scheduler database file. ! literal SCHEDWA$K_LENGTH = 1232; literal SCHEDWA$S_SCHEDWA = 1232; macro SCHEDWA$B_FAB = 0,0,0,0 %; literal SCHEDWA$S_FAB = 80; ! FAB for database file macro SCHEDWA$B_RAB = 80,0,0,0 %; literal SCHEDWA$S_RAB = 144; ! RAB for database file macro SCHEDWA$B_CLASS_KEY0 = 224,0,0,0 %; literal SCHEDWA$S_CLASS_KEY0 = 100; ! 6 XAB's to represent 6 different macro SCHEDWA$B_CLASS_KEY1 = 324,0,0,0 %; literal SCHEDWA$S_CLASS_KEY1 = 100; ! index keys into database file. macro SCHEDWA$B_CLASS_KEY2 = 424,0,0,0 %; literal SCHEDWA$S_CLASS_KEY2 = 100; macro SCHEDWA$B_CLASS_KEY3 = 524,0,0,0 %; literal SCHEDWA$S_CLASS_KEY3 = 100; macro SCHEDWA$B_CLASS_KEY4 = 624,0,0,0 %; literal SCHEDWA$S_CLASS_KEY4 = 100; macro SCHEDWA$B_CLASS_KEY5 = 724,0,0,0 %; literal SCHEDWA$S_CLASS_KEY5 = 100; macro SCHEDWA$B_XABPRO = 824,0,0,0 %; literal SCHEDWA$S_XABPRO = 88; ! Protection XAB macro SCHEDWA$B_INPUT_BUF = 912,0,0,0 %; literal SCHEDWA$S_INPUT_BUF = 160; ! Input buffer macro SCHEDWA$B_OUTPUT_BUF = 1072,0,0,0 %; literal SCHEDWA$S_OUTPUT_BUF = 160; ! Output buffer ! Bit definitions for the flags field passed between SYSMAN and the SMIserver ! for the ADD, DELETE, and SHOW commands. Since both these images include this ! file, it is an appropriate place to include them. literal CSCHED$K_ALL = 0; ! flags for the SHOW command literal CSCHED$K_FULL = 1; literal CSCHED$K_WINDFALL = 0; ! flags for the ADD command and the cluster flag literal CSCHED$K_CLUSTER = 1; ! is also valid for the DELETE command ! Values below represent the item codes for the item list which ! contains the user data for a scheduling class. These item codes are used for ! the ADD and MODIFY functions. The item list is passed from SYSMAN to the SMI ! class scheduler object routine. literal CSCHED$K_ADD_USER = 1; literal CSCHED$K_ADD_ACCOUNT = 2; literal CSCHED$K_ADD_UIC = 3; literal CSCHED$K_REMOVE_USER = 4; literal CSCHED$K_REMOVE_ACCOUNT = 5; literal CSCHED$K_REMOVE_UIC = 6; literal CSCHED$K_NUMBER_OF_ITEMCODES = 7; !*** MODULE $CSDTDEF *** ! + ! CSDT - CLUSTER SERVER DISPATCH TABLE ! ! - ! ! CSDTE - CLUSTER SERVER DISPATCH TABLE ENTRY ! ! literal CSDTE$C_LENGTH = 64; ! LENGTH literal CSDTE$K_LENGTH = 64; ! LENGTH literal CSDTE$S_CSDTEDEF = 64; literal CSDTE$S_CSDTE = 64; macro CSDTE$Q_REQ_IQ = 0,0,0,0 %; literal CSDTE$S_REQ_IQ = 8; ! INTERLOCKED REQUEST QUEUE macro CSDTE$Q_WAITQ = 8,0,0,0 %; literal CSDTE$S_WAITQ = 8; ! WAIT QUEUE macro CSDTE$L_IPID = 16,0,32,0 %; ! SERVER IPID macro CSDTE$L_QUEUED = 20,0,32,0 %; ! NUMBER OF WAITS macro CSDTE$L_REQUESTS = 24,0,32,0 %; ! TOTAL REQUESTS MADE macro CSDTE$L_WAITCNT = 28,0,32,0 %; ! ENTRIES IN WAIT QUEUE macro CSDTE$L_MAXACTIVE = 32,0,32,0 %; ! MAXIMUM ACTIVE REQUESTS ALLOWED macro CSDTE$L_ACTIVE = 36,0,32,0 %; ! NUMBER ACTIVE REQUESTS literal CSDT$C_LENGTH = 16; ! LENGTH OF FIXED PART literal CSDT$K_LENGTH = 16; ! LENGTH OF FIXED PART literal CSDT$T_CSDTEVEC = 16; ! START OF VARIABLE PART literal CSDT$S_CSDTDEF = 16; literal CSDT$S_CSDT = 16; macro CSDT$W_SIZE = 8,0,16,0 %; ! SIZE OF IN BYTES macro CSDT$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE macro CSDT$B_SUBTYPE = 11,0,8,0 %; ! STRUCTURE SUBTYPE !*** MODULE $CTDDEF *** ! + ! ! CPU transition block definition. This block is allocated ! and initialized when a CPU undergoes a state transition and the final ! completion code is to be returned to the issuer. ! - literal CTD$S_CTD = 144; macro CTD$PQ_QLINK = 0,0,0,1 %; literal CTD$S_QLINK = 8; ! Forward link to next CTD macro CTD$W_SIZE = 8,0,16,0 %; ! Structure size macro CTD$B_TYPE = 10,0,8,0 %; ! Structure type macro CTD$B_RMOD = 11,0,8,0 %; ! Duplicate of ACB RMOD macro CTD$L_PID = 12,0,32,0 %; ! PID of owner process macro CTD$L_ACB64X = 16,0,32,0 %; ! Offset to ACB extension macro CTD$L_FLAGS = 20,0,32,0 %; ! CTD behavioral flags macro CTD$L_ACB_FLAGS = 24,0,32,0 %; ! ACB64X behavioral flags macro CTD$L_THREAD_PID = 28,0,32,0 %; ! PID of initiating thread macro CTD$L_KAST = 32,0,32,1 %; ! Internal Kernel mode xfer macro CTD$L_IMGCNT = 36,0,32,0 %; ! PHD IMGCNT value at issue macro CTD$PQ_AST = 40,0,0,1 %; literal CTD$S_AST = 8; ! 64-bit AST address macro CTD$Q_ASTPRM = 48,0,0,0 %; literal CTD$S_ASTPRM = 8; ! 64-bit ASTPRM value macro CTD$PQ_IOSB = 56,0,0,1 %; literal CTD$S_IOSB = 8; ! Quadword IOSB pointer macro CTD$Q_SOURCE_NODE = 64,0,0,1 %; literal CTD$S_SOURCE_NODE = 8; ! Node ID of source system macro CTD$Q_TARGET_NODE = 72,0,0,1 %; literal CTD$S_TARGET_NODE = 8; ! Node ID of target system macro CTD$L_PRIMARY_TRAN_CODE = 80,0,32,1 %; ! Transition type in progress macro CTD$L_CURRENT_TRAN_CODE = 84,0,32,1 %; ! Transition type in progress macro CTD$L_TRANSITION_MASK = 88,0,32,0 %; ! Bitmask of requested transitions macro CTD$L_CPU_ID = 92,0,32,1 %; ! ID of CPU under transition macro CTD$L_STATUS = 96,0,32,0 %; ! Final completion code macro CTD$L_EFN = 100,0,32,0 %; ! Event flag to set on finish macro CTD$L_TIMEOUT_TQE = 104,0,32,1 %; ! Pointer to TQE for timeout macro CTD$Q_CPU_HANDLE = 112,0,0,0 %; literal CTD$S_CPU_HANDLE = 8; ! Config tree pointer macro CTD$Q_TARGET_HANDLE = 120,0,0,0 %; literal CTD$S_TARGET_HANDLE = 8; ! Config tree pointer macro CTD$Q_START_TIME = 128,0,0,0 %; literal CTD$S_START_TIME = 8; ! Smithsonian initiation time macro CTD$Q_INTERIM_TIME = 136,0,0,0 %; literal CTD$S_INTERIM_TIME = 8; ! Smithsonian completion time literal CTD$K_LENGTH = 144; ! Total fixed structure size !*** MODULE $CTLP1FLAGSDEF *** ! + ! CTL P1 flags ! ! These are flags in the CTL p1 region to define miscellaneous things. ! There are also some definitions relating to the instruction emulator here. ! - ! ! These reside in the cell CTL$GQ_MISC_P1_FLAGS, defined in SHELL.MAR. ! The byte alignment fillers are present for historical reasons. When ! the adjacent fields were added, $GETJPI was not capable of fetching ! bitfields in CTL structures, so these fields were byte aligned and ! fetched as byte items. Of course, this practice couldn't last and we ! ran out of available bits in the quadword. $GETJPI has been fixed and ! the space in the fillers is available for use. The fillers remain so ! that existing bits do not move. ! literal CTLP1FLAGS$M_GSD_CLEAN = %X'1'; literal CTLP1FLAGS$M_IPC_CLEAN = %X'2'; literal CTLP1FLAGS$M_PSX_PML = %X'4'; literal CTLP1FLAGS$M_MKTHREADS = %X'8'; literal CTLP1FLAGS$M_UPCALLS = %X'10'; literal CTLP1FLAGS$M_PTHREAD = %X'20'; literal CTLP1FLAGS$M_MEDDLE_ENABLE = %X'40'; literal CTLP1FLAGS$M_MEDDLE = %X'80'; literal CTLP1FLAGS$M_PARSE_STYLE_PERM = %X'700'; literal CTLP1FLAGS$M_SRCH_SYMLINK_PERM = %X'1800'; literal CTLP1FLAGS$M_PARSE_STYLE_IMAGE = %X'70000'; literal CTLP1FLAGS$M_SRCH_SYMLINK_TEMP = %X'180000'; literal CTLP1FLAGS$M_CASE_LOOKUP_PERM = %X'7000000'; literal CTLP1FLAGS$M_CASE_LOOKUP_IMAGE = %X'700000000'; literal CTLP1FLAGS$M_UNITS = %X'10000000000'; literal CTLP1FLAGS$M_TOKEN = %X'1000000000000'; literal CTLP1FLAGS$S_CTLP1DEF = 8; ! Old size name - synonym literal CTLP1FLAGS$S_CTLP1 = 8; macro CTLP1FLAGS$V_GSD_CLEAN = 0,0,1,0 %; ! GSD clean-up is in progress macro CTLP1FLAGS$V_IPC_CLEAN = 0,1,1,0 %; ! $IPC association clean-up is in progress macro CTLP1FLAGS$V_PSX_PML = 0,2,1,0 %; ! POSIX user stack locked in working set macro CTLP1FLAGS$V_MKTHREADS = 0,3,1,0 %; ! Multiple kernel threads enabled macro CTLP1FLAGS$V_UPCALLS = 0,4,1,0 %; ! Upcalls enabled macro CTLP1FLAGS$V_PTHREAD = 0,5,1,0 %; ! PTHREAD$RTL has been image activated macro CTLP1FLAGS$V_MEDDLE_ENABLE = 0,6,1,0 %; ! Record fact of process logical name & symbol alterations macro CTLP1FLAGS$V_MEDDLE = 0,7,1,0 %; ! Process logical names or symbols have been altered macro CTLP1FLAGS$V_PARSE_STYLE_PERM = 0,8,3,0 %; literal CTLP1FLAGS$S_PARSE_STYLE_PERM = 3; ! Process-permanent parse_style macro CTLP1FLAGS$V_SRCH_SYMLINK_PERM = 0,11,2,0 %; literal CTLP1FLAGS$S_SRCH_SYMLINK_PERM = 2; ! Process-permanent symlink search mode macro CTLP1FLAGS$v_filler_2 = 0,13,3,0 %; literal CTLP1FLAGS$s_filler_2 = 3; ! Byte align for historical reasons macro CTLP1FLAGS$V_PARSE_STYLE_IMAGE = 0,16,3,0 %; literal CTLP1FLAGS$S_PARSE_STYLE_IMAGE = 3; ! Life-of-image parse_style macro CTLP1FLAGS$V_SRCH_SYMLINK_TEMP = 0,19,2,0 %; literal CTLP1FLAGS$S_SRCH_SYMLINK_TEMP = 2; ! Life-of-image symlink search mode macro CTLP1FLAGS$v_filler_3 = 0,21,3,0 %; literal CTLP1FLAGS$s_filler_3 = 3; ! Byte align for historical reasons macro CTLP1FLAGS$V_CASE_LOOKUP_PERM = 0,24,3,0 %; literal CTLP1FLAGS$S_CASE_LOOKUP_PERM = 3; ! Process-permanent case_lookup macro CTLP1FLAGS$v_filler_4 = 0,27,5,0 %; literal CTLP1FLAGS$s_filler_4 = 5; ! Byte align for historical reasons macro CTLP1FLAGS$V_CASE_LOOKUP_IMAGE = 4,0,3,0 %; literal CTLP1FLAGS$S_CASE_LOOKUP_IMAGE = 3; ! Life-of-image case_lookup macro CTLP1FLAGS$v_filler_5 = 4,3,5,0 %; literal CTLP1FLAGS$s_filler_5 = 5; ! Byte align for historical reasons macro CTLP1FLAGS$V_UNITS = 4,8,1,0 %; ! Use bytes or blocks macro CTLP1FLAGS$v_filler_6 = 4,9,7,0 %; literal CTLP1FLAGS$s_filler_6 = 7; ! Byte align for historical reasons macro CTLP1FLAGS$V_TOKEN = 4,16,1,0 %; ! Use small or large tokens macro CTLP1FLAGS$v_filler_7 = 4,17,15,0 %; literal CTLP1FLAGS$s_filler_7 = 15; ! Available space ! ! The following are the flags that reside in CTL$GQ_EMULATOR_FLAGS ! literal CTLEMFLAGS$M_REINIT = %X'1'; literal CTLEMFLAGS$M_GET_SIG_COUNT = %X'2'; literal CTLEMFLAGS$M_NO_NEW_IMAGE_RESET = %X'4'; literal CTLEMFLAGS$M_SIGNAL_INNER_MODE = %X'8'; literal CTLEMFLAGS$M_NO_MASK_INIT = %X'10'; literal CTLEMFLAGS$M_NO_SIGNAL_MAX_INIT = %X'20'; literal CTLEMFLAGS$M_NO_PC_RING_INIT = %X'40'; literal CTLEMFLAGS$M_NO_COUNT_INIT = %X'80'; literal CTLEMFLAGS$S_CTLEMFLAGS = 8; macro CTLEMFLAGS$V_REINIT = 0,0,1,0 %; ! A new image started: reinitialize P1 cells macro CTLEMFLAGS$V_GET_SIG_COUNT = 0,1,1,0 %; ! Get the sig count from EMULATE_DATA macro CTLEMFLAGS$V_NO_NEW_IMAGE_RESET = 0,2,1,0 %; ! Inhibit initialization macro CTLEMFLAGS$V_SIGNAL_INNER_MODE = 0,3,1,0 %; ! Signal SS$_EMULATED even for inner mode emulation ! ...(you need a condition handler else SSERVEXC bugcheck) macro CTLEMFLAGS$V_NO_MASK_INIT = 0,4,1,0 %; ! Run init in emulator, but don't init these fields... macro CTLEMFLAGS$V_NO_SIGNAL_MAX_INIT = 0,5,1,0 %; macro CTLEMFLAGS$V_NO_PC_RING_INIT = 0,6,1,0 %; macro CTLEMFLAGS$V_NO_COUNT_INIT = 0,7,1,0 %; ! ...End of "init but" bits ! ! The following are the flags that reside in the CTL$GQ_EXCEPTION_FLAGS ! literal CTLEXCFLAGS$M_SIGNAL_ACTIVE = %X'1'; literal CTLEXCFLAGS$S_CTLEXCFLAGS = 8; macro CTLEXCFLAGS$V_SIGNAL_ACTIVE = 0,0,1,0 %; ! Signal processing is in ! progress ! ! These constants relate to CTL$GQ_EMULATE_PC_RING ! literal CTL$C_EMULATE_RING_SIZE = 8; literal CTL$M_EMULATE_RING_SIZE = 7; ! Mask for valid bits to index ring !*** MODULE $CWLNMDEF *** literal CWLNM$M_CSP_BUSY = %X'1'; literal CWLNM$M_FORWARD_IP = %X'2'; literal CWLNM$M_ONWORKQ = %X'4'; literal CWLNM$K_LENGTH = 24; ! Length of header literal CWLNM$K_MAX_SIZE = 37352; ! Maximum needed buffer size in bytes literal CWLNM$K_UPDATE_SIZE = 37352; ! Target buffer size for boot update message literal CWLNM$K_STEADYSTATE_SIZE = 8168; ! Target buffer size for steady state operation literal CWLNM$K_TRANSTYPE_BEGIN = 1; literal CWLNM$K_CRELNM = 1; ! $CRELNM (create a logical name) description literal CWLNM$K_CRELNT = 2; ! $CRELNT (create log name table) description literal CWLNM$K_DELLNM = 3; ! $DELLNM (delete log name or table) description literal CWLNM$K_UPDSECPRO = 4; ! Update security profile of a table literal CWLNM$K_SND_CWLOGDB = 5; ! Update a booting node with current database literal CWLNM$K_REQ_CWLOGDB = 6; ! Request current database from another node literal CWLNM$K_TRANSTYPE_END = 7; ! Marker for end of type codes literal CWLNM$S_CWLNM = 24; macro CWLNM$L_FLINK = 0,0,32,1 %; ! Forward link in list macro CWLNM$L_BLINK = 4,0,32,1 %; ! Backward link in list macro CWLNM$W_FILL_1 = 8,0,16,0 %; ! Reserved macro CWLNM$B_TYPE = 10,0,8,0 %; ! Structure type macro CWLNM$B_SUBTYPE = 11,0,8,0 %; ! Subtype macro CWLNM$L_SIZE = 12,0,32,0 %; ! Size of CWLNM in bytes ! (On 32KB-page Alpha, could hit 64K) macro CWLNM$L_FLAGS = 16,0,32,0 %; ! Buffer status flags macro CWLNM$V_CSP_BUSY = 16,0,1,0 %; ! CSP is relocating buffer offsets - don't transmit it macro CWLNM$V_FORWARD_IP = 16,1,1,0 %; ! Fork process is forwarding buffer to out-of-date node ! following a cluster transition macro CWLNM$V_ONWORKQ = 16,2,1,0 %; ! Message buffer is on CSP's work queue macro CWLNM$L_DATASTART = 20,0,32,0 %; ! Offset to logical name transaction structure ! (73 pagelets) ! (73 pagelets) ! ** consider above number wrt VAX literal CWCRELNM$K_LENGTH = 32; ! Length of fixed format information literal CWCRELNM$K_FIXED_LENGTH = 56; literal CWCRELNM$K_NUMBER_ARGS = 5; literal CWCRELNM$S_CWCRELNM = 32; macro CWCRELNM$W_SIZE = 0,0,16,0 %; ! Size of CWCRELNM in bytes macro CWCRELNM$W_TRANSTYPE = 2,0,16,0 %; ! Transaction type macro CWCRELNM$L_RELOC_BIAS = 4,0,32,1 %; ! Amount by which "addresses" ! are biased macro CWCRELNM$L_ARGCOUNT = 8,0,32,0 %; ! Number of service arguments macro CWCRELNM$L_ATTR = 12,0,32,1 %; ! "Address" of attributes argument or 0 macro CWCRELNM$L_TABNAM = 16,0,32,1 %; ! "Address" of table name descriptor macro CWCRELNM$L_LOGNAM = 20,0,32,1 %; ! "Address" of logical name descriptor macro CWCRELNM$L_ACMODE = 24,0,32,1 %; ! "Address" of access mode argument macro CWCRELNM$L_ITMLST = 28,0,32,1 %; ! "Address" of item list or 0 literal CWCRELNT$K_LENGTH = 48; ! Length of fixed format information literal CWCRELNT$K_FIXED_LENGTH = 80; literal CWCRELNT$K_NUMBER_ARGS = 9; literal CWCRELNT$S_CWCRELNT = 48; macro CWCRELNT$W_SIZE = 0,0,16,0 %; ! Size of CWCRELNT in bytes macro CWCRELNT$W_TRANSTYPE = 2,0,16,0 %; ! Transaction type macro CWCRELNT$L_RELOC_BIAS = 4,0,32,1 %; ! Amount by which "addresses" ! are biased macro CWCRELNT$L_ARGCOUNT = 8,0,32,0 %; ! Number of service arguments macro CWCRELNT$L_ATTR = 12,0,32,1 %; ! "Address" of attributes argument macro CWCRELNT$L_RESNAM = 16,0,32,1 %; ! "Address" of resultant table name macro CWCRELNT$L_RESLEN = 20,0,32,1 %; ! "Address" of resultant table name length macro CWCRELNT$L_QUOTA = 24,0,32,1 %; ! "Address" of quota macro CWCRELNT$L_PROMSK = 28,0,32,1 %; ! "Address" of protection mask macro CWCRELNT$L_TABNAM = 32,0,32,1 %; ! "Address" of table name descriptor macro CWCRELNT$L_PARTAB = 36,0,32,1 %; ! "Address" of parent table descriptor macro CWCRELNT$L_ACMODE = 40,0,32,1 %; ! "Address" of access mode argument macro CWCRELNT$L_UIC = 44,0,32,1 %; ! "Address" of UIC argument, really a TLV pointer literal CWDELLNM$K_LENGTH = 24; ! Length of fixed format information literal CWDELLNM$K_FIXED_LENGTH = 44; literal CWDELLNM$K_NUMBER_ARGS = 3; literal CWDELLNM$S_CWDELLNM = 24; macro CWDELLNM$W_SIZE = 0,0,16,0 %; ! Size of CWDELLNM in bytes macro CWDELLNM$W_TRANSTYPE = 2,0,16,0 %; ! Transaction type macro CWDELLNM$L_RELOC_BIAS = 4,0,32,1 %; ! Amount by which "addresses" ! are biased macro CWDELLNM$L_ARGCOUNT = 8,0,32,0 %; ! Number of service arguments macro CWDELLNM$L_TABNAM = 12,0,32,1 %; ! "Address" of table name descriptor macro CWDELLNM$L_LOGNAM = 16,0,32,1 %; ! "Address" of logical name descriptor macro CWDELLNM$L_ACMODE = 20,0,32,1 %; ! "Address" of access mode argument literal CWUPDSECPRO$K_LENGTH = 24; ! Length of fixed format information literal CWUPDSECPRO$K_NUMBER_ARGS = 3; literal CWUPDSECPRO$S_CWUPDSECPRO = 24; macro CWUPDSECPRO$W_SIZE = 0,0,16,0 %; ! Size of CWUPDSECPRO in bytes macro CWUPDSECPRO$W_TRANSTYPE = 2,0,16,0 %; ! Transaction type macro CWUPDSECPRO$L_RELOC_BIAS = 4,0,32,1 %; ! Amount by which "addresses" ! are biased macro CWUPDSECPRO$L_ARGCOUNT = 8,0,32,0 %; ! Number of service arguments macro CWUPDSECPRO$L_ACMODE = 12,0,32,1 %; ! "Address" of access mode argument macro CWUPDSECPRO$L_FLAGS = 16,0,32,0 %; ! OSRCTX flags macro CWUPDSECPRO$L_TLV = 20,0,32,1 %; ! "Address" of TLV literal OSR_FLAGS_M_LNT_ACCESS_QUAL = %X'1'; literal OSR_FLAGS_S_fill_195_ = 4; macro OSR_FLAGS_l_osrctx_flags = 0,0,32,0 %; ! OSRCTX flags macro OSR_FLAGS_V_LNT_ACCESS_QUAL = 0,0,1,0 %; ! When set, means acmode must match literal CWREQDB$K_LENGTH = 12; ! Length of fixed format information literal CWREQDB$S_CWREQDB = 12; macro CWREQDB$W_SIZE = 0,0,16,0 %; ! Size of CWREQDB in bytes macro CWREQDB$W_TRANSTYPE = 2,0,16,0 %; ! Transaction type macro CWREQDB$L_CSID = 4,0,32,0 %; ! Booting node's CSID macro CWREQDB$L_REQ_BUFSIZE = 8,0,32,0 %; ! Booting node's guaranteed minimum ! buffer size literal CWSNDDB$M_LAST_MSG = %X'1'; literal CWSNDDB$K_LENGTH = 20; ! Length of fixed format information literal CWSNDDB$S_CWSNDDB = 20; macro CWSNDDB$W_SIZE = 0,0,16,0 %; ! Size of CWSNDDB in bytes macro CWSNDDB$W_TRANSTYPE = 2,0,16,0 %; ! Transaction type macro CWSNDDB$R_FLAG_BITS = 4,0,32,0 %; macro CWSNDDB$L_FLAGS = 4,0,32,0 %; ! macro CWSNDDB$R_BITS = 4,0,8,0 %; literal CWSNDDB$S_BITS = 1; macro CWSNDDB$V_LAST_MSG = 4,0,1,0 %; ! Last message macro CWSNDDB$L_PART_NO = 8,0,32,0 %; ! Ordinal number of this chunk of ! database description macro CWSNDDB$L_COUNT = 12,0,32,0 %; ! Number of structures that follow macro CWSNDDB$L_CSID = 16,0,32,0 %; ! Sender's CSID !*** MODULE $CXBDEF *** ! + ! CXB - COMPLEX CHAINED BUFFER ! ! THESE OFFSETS ARE USED IN THE HEADER OF DISJOINT SEGMENTS ! WHICH ARE TO BE PRESENTED TO THE USER AS A UNIT. ! ! - literal CXB$M_RESP = %X'1'; literal CXB$L_NI_ALTXMT = 28; ! ALTSTART XMT parameters literal CXB$C_AGENT_SCRATCH_LEN = 52; ! This marks the length of the standard CXB. literal CXB$K_LENGTH = 92; literal CXB$C_LENGTH = 92; ! Data link layer scratch space literal CXB$M_FLTR_MCA = %X'1'; literal CXB$M_FLTR_CTL = %X'2'; literal CXB$M_FLTR_SRC = %X'4'; literal CXB$M_FLTR_STARTUP = %X'1'; literal CXB$M_FLTR_INTXMIT = %X'2'; literal CXB$T_R_DATA = 128; ! Start of RCV data literal CXB$W_R_LEN_802 = 140; ! 802 length field literal CXB$T_R_USER_ETH = 142; ! Start of user ETH data literal CXB$W_R_SIZE = 142; ! Size of message if padded literal CXB$X_R_CTL = 144; ! 802 CTL field literal CXB$G_R_PID = 145; ! 5-byte Protocol Identifier literal CXB$T_R_USER_802E = 150; ! Start of user 802E data literal CXB$C_DLL = 52; ! Size of CXB$T_DLL literal CXB$C_DLL_SCRATCH_LEN = 52; ! Size of CXB$T_DLL ! ** This field must be quadword aligned for CNDRIVER. literal CXB$K_HEADER = 144; ! CXB size up to this point literal CXB$C_HEADER = 144; ! CXB size up to this point literal CXB$C_TRAILER = 4; ! Space after CXB data for CRC code literal CXB$K_OVERHEAD = 148; ! CXB$C_HEADER + CXB$C_TRAILER literal CXB$C_OVERHEAD = 148; ! CXB$C_HEADER + CXB$C_TRAILER literal CXB$S_CXB = 152; macro CXB$L_FL = 0,0,32,1 %; ! Forward queue link macro CXB$L_BL = 4,0,32,1 %; ! Backward queue link ! ...or... macro CXB$PS_PKTDATA = 0,0,32,1 %; ! Pointer to buffered data in packet macro CXB$PS_UVA32 = 4,0,32,1 %; ! 32-bit pointer to user's buffer, or BUFIO$K_64 (-1) macro CXB$W_SIZE = 8,0,16,0 %; ! Block size macro CXB$B_TYPE = 10,0,8,0 %; ! Block type macro CXB$B_FLAG = 11,0,8,0 %; ! Flag byte macro CXB$V_RESP = 11,0,1,0 %; ! Command/Response indicator macro CXB$W_BOFF = 12,0,16,0 %; ! Offset to data link data macro CXB$W_BCNT = 14,0,16,0 %; ! Size of data link data macro CXB$L_DATA_CHAIN = 16,0,32,1 %; ! Pointer to data chain buffer descriptor macro CXB$Q_STATION = 20,0,0,0 %; literal CXB$S_STATION = 8; ! Contains destination address or source address macro CXB$W_CTL = 28,0,16,0 %; ! 802.2 ctl field either byte or word value macro CXB$B_CTL_SIZE = 30,0,8,0 %; ! 802.2 ctl field value size macro CXB$B_DSAP = 31,0,8,0 %; ! 802.2 ALT/FFI XMT dest sap macro CXB$Q_RESERVED = 32,0,0,0 %; literal CXB$S_RESERVED = 8; ! Reserved for future use ! Agent specific scratch space. macro CXB$T_AGENT_SCRATCH = 40,0,0,0 %; literal CXB$S_AGENT_SCRATCH = 52; ! DECnet-VAX agent specific fields. macro CXB$T_AGENT_DECNET = 40,0,0,0 %; literal CXB$S_AGENT_DECNET = 52; macro CXB$W_LENGTH = 40,0,16,0 %; ! Length of data macro CXB$W_OFFSET = 42,0,16,0 %; ! Offset to start of nsp message macro CXB$B_CODE = 44,0,8,0 %; ! Buffer code macro CXB$B_STS = 45,0,8,0 %; ! Status fields macro CXB$W_CHANNEL = 46,0,16,0 %; ! Store channel number for AST macro CXB$L_LINK = 48,0,32,1 %; ! Link word for chained data message macro CXB$L_IRP = 52,0,32,1 %; ! IRP address for transmits macro CXB$L_END_ACTION = 56,0,32,1 %; ! Pointer to I/O done routine ! The following fields contain the context that NSP needs to process a packet ! which has been received out of order. macro CXB$L_R_NSP_MSG = 60,0,32,1 %; ! This is the address of the next ! byte in the NSP message after ! the segment number field (R1) macro CXB$L_R_DATA_SIZE = 64,0,32,0 %; ! This is the number of as yet ! unaccounted bytes in message (R2) macro CXB$W_R_SEG_NUM = 68,0,16,0 %; ! This is the messages segment number (R3) ! Backlink pointer for NSP to associate the CXB with the user's originating ! IRP. The non-agent specific field, CXB$L_IRP, cannot be used because the ! datalink drivers use this field for the same purpose, but different IRP. ! The datalink's IRP is the DECnet routing supplied IRP queued to the ! altstart interface. macro CXB$L_USER_IRP = 72,0,32,1 %; ! link to user's IRP macro CXB$L_LAST_DCB = 76,0,32,1 %; ! pointer to last DCB ! 64-bit pointer to user buffer address that's valid if and only if ! CXB$PS_UVA32 contains the value BUFIO$K_64 (-1). macro CXB$PQ_UVA64 = 80,0,0,1 %; literal CXB$S_UVA64 = 8; ! 64-bit pointer to user's buffer ! Size of the agent scratch area macro CXB$T_DLL = 92,0,0,0 %; literal CXB$S_DLL = 52; ! The following three structures define the fields used by the ! Ethernet/802 datalink drivers. macro CXB$T_DLL_NI802 = 92,0,0,0 %; literal CXB$S_DLL_NI802 = 52; macro CXB$B_NI_FUNC = 92,0,8,0 %; ! Internal function code macro CXB$B_R_FLAGS = 93,0,8,0 %; ! Flags macro CXB$W_NI_RID = 94,0,16,0 %; ! Request ID macro CXB$B_NI_SLOT = 94,0,8,0 %; ! Mapping slot number macro CXB$B_NI_RING = 95,0,8,0 %; ! Ring Entry number macro CXB$L_T_IRP = 96,0,32,1 %; ! User IRP address macro CXB$W_R_NCHAIN = 100,0,16,0 %; ! Number of buffers in chain macro CXB$W_R_LENERR = 102,0,16,0 %; ! Length and Rcv error status macro CXB$L_R_UCB = 104,0,32,1 %; ! UCB address of receiver macro CXB$W_HDR_SIZE = 108,0,16,0 %; ! Size of receive header macro CXB$B_R_FMT = 110,0,8,0 %; ! Receive packet format macro CXB$r_filter = 111,0,8,0 %; literal CXB$s_filter = 1; macro CXB$B_R_FILTER = 111,0,8,0 %; ! Receive CXB filtering mask word macro CXB$V_FLTR_MCA = 111,0,1,0 %; ! MCA filtering has been performed macro CXB$V_FLTR_CTL = 111,1,1,0 %; ! CTL filtering has been performed macro CXB$V_FLTR_SRC = 111,2,1,0 %; ! SRC filtering has been performed macro CXB$B_T_FILTER = 111,0,8,0 %; ! Transmit CXB filtering mask word macro CXB$V_FLTR_STARTUP = 111,0,1,0 %; ! Delete CXB, complete IRP macro CXB$V_FLTR_INTXMIT = 111,1,1,0 %; ! Add CXB to Receive list macro CXB$T_DLL_NI802XMT = 92,0,0,0 %; literal CXB$S_DLL_NI802XMT = 52; macro CXB$T_T_DATA = 130,0,0,0 %; literal CXB$S_T_DATA = 14; ! Start of standard XMT macro CXB$T_DLL_NI802RCV = 92,0,0,0 %; literal CXB$S_DLL_NI802RCV = 52; macro CXB$G_R_DEST = 128,0,0,0 %; literal CXB$S_R_DEST = 6; ! Destination address macro CXB$G_R_SRC = 134,0,0,0 %; literal CXB$S_R_SRC = 6; ! Source address macro CXB$W_R_PTYPE = 140,0,16,0 %; ! Protocol type macro CXB$B_R_DSAP = 142,0,8,0 %; ! 802 DSAP field macro CXB$B_R_SSAP = 143,0,8,0 %; ! 802 SSAP field ! the CRC trailer literal CXB$S_CXBDEF = 152; ! Old size name - synonym !*** MODULE $DALDEF *** ! + ! DAL - Device Allocation Lock (value block contents) ! ! This structure defines the contents of the lock value block for a ! device allocation lock. ! - literal DAL$M_NOTFIRST_MNT = %X'1'; literal DAL$M_FOREIGN = %X'2'; literal DAL$M_GROUP = %X'4'; literal DAL$M_SYSTEM = %X'8'; literal DAL$M_WRITE = %X'10'; literal DAL$M_NOQUOTA = %X'20'; literal DAL$M_OVR_PROT = %X'40'; literal DAL$M_OVR_OWNUIC = %X'80'; literal DAL$M_NOINTERLOCK = %X'100'; literal DAL$M_SHADOW_MBR = %X'200'; literal DAL$M_POOL_MBR = %X'400'; literal DAL$S_DALDEF = 16; literal DAL$S_DAL = 16; macro DAL$W_FLAGS = 0,0,16,0 %; ! Device usage flags: macro DAL$V_NOTFIRST_MNT = 0,0,1,0 %; ! not first time device mounted. macro DAL$V_FOREIGN = 0,1,1,0 %; ! device mounted /FOREIGN macro DAL$V_GROUP = 0,2,1,0 %; ! device mounted /GROUP macro DAL$V_SYSTEM = 0,3,1,0 %; ! device mounted /SYSTEM macro DAL$V_WRITE = 0,4,1,0 %; ! write access allowed macro DAL$V_NOQUOTA = 0,5,1,0 %; ! quota checking disabled macro DAL$V_OVR_PROT = 0,6,1,0 %; ! override protection macro DAL$V_OVR_OWNUIC = 0,7,1,0 %; ! override volume ownership macro DAL$V_NOINTERLOCK = 0,8,1,0 %; ! access NOT VAXcluster interlocked macro DAL$V_SHADOW_MBR = 0,9,1,0 %; ! shadow set member macro DAL$V_POOL_MBR = 0,10,1,0 %; ! snapshot-capable disk pool member macro DAL$W_PROTECTION = 2,0,16,0 %; ! Volume protection macro DAL$L_OWNER_UIC = 4,0,32,0 %; ! Volume owner UIC macro DAL$W_FIRST_MOUNTER_GROUP = 8,0,16,0 %; ! UIC group of first mounter macro DAL$L_VOLID = 12,0,32,0 %; ! Volume identifier hash !*** MODULE $DBRDEF *** ! ! Definitions for Data Breakpoint Registers (DBR) ! literal DBR$M_MASK = %X'FFFFFFFFFFFFFF'; literal DBR$M_PLM = %X'F00000000000000'; literal DBR$M_IG = %X'3000000000000000'; literal DBR$M_RW = %X'C000000000000000'; literal DBR$M_W = %X'4000000000000000'; literal DBR$M_R = %X'8000000000000000'; literal DBR$S_DBR = 8; macro DBR$R_DBR_UNION = 0,0,0,0 %; literal DBR$S_DBR_UNION = 8; macro DBR$Q_REGISTER = 0,0,0,0 %; literal DBR$S_REGISTER = 8; ! Use this for even-numbered DBR registers too macro DBR$V_MASK = 0,0,56,0 %; literal DBR$S_MASK = 56; ! Valid address bits mask macro DBR$V_PLM = 4,24,4,0 %; literal DBR$S_PLM = 4; ! Privilege level mask macro DBR$V_IG = 4,28,2,0 %; literal DBR$S_IG = 2; ! Ignored macro DBR$V_RW = 4,30,2,0 %; literal DBR$S_RW = 2; ! Read or write match enable macro DBR$V_FILL_1 = 0,0,62,0 %; literal DBR$S_FILL_1 = 62; ! ...if we want read and write as separate bits macro DBR$V_W = 4,30,1,0 %; ! Write match enable macro DBR$V_R = 4,31,1,0 %; ! Read match enable ! ! Definitions for Instruction Breakpoint Registers (IBR) ! literal IBR$M_MASK = %X'FFFFFFFFFFFFFF'; literal IBR$M_PLM = %X'F00000000000000'; literal IBR$M_IG = %X'7000000000000000'; literal IBR$M_X = %X'8000000000000000'; literal IBR$S_IBR = 8; macro IBR$R_IBR_UNION = 0,0,0,0 %; literal IBR$S_IBR_UNION = 8; macro IBR$Q_REGISTER = 0,0,0,0 %; literal IBR$S_REGISTER = 8; ! Use this for even-numbered DBR registers too macro IBR$V_MASK = 0,0,56,0 %; literal IBR$S_MASK = 56; ! Valid address bits mask macro IBR$V_PLM = 4,24,4,0 %; literal IBR$S_PLM = 4; ! Privilege level mask macro IBR$V_IG = 4,28,3,0 %; literal IBR$S_IG = 3; ! Ignored macro IBR$V_X = 4,31,1,0 %; ! Execute match enable !*** MODULE $DCBDEF *** ! + ! DCB - Data link layer chained buffer descriptor ! ! This descriptor may be used in one of two ways. The first way is to ! use this descriptor to describe a direct I/O transfer. The second ! is to use this descriptor to describe a chain of buffers to transmit ! or a chain of buffers which have been received. ! ! - literal DCB$M_TYPE_IO = %X'1'; literal DCB$K_HEADER = 32; ! DCB size up to this point literal DCB$C_HEADER = 32; ! DCB size up to this point literal DCB$S_DCBDEF = 32; literal DCB$S_DCB = 32; macro DCB$L_FLINK = 0,0,32,1 %; ! Forward link macro DCB$L_BLINK = 4,0,32,1 %; ! Backward link macro DCB$W_SIZE = 8,0,16,0 %; ! Size of block macro DCB$B_TYPE = 10,0,8,0 %; ! Type of block macro DCB$B_MODE = 11,0,8,0 %; ! Access mode of agent macro DCB$L_LINK = 12,0,32,1 %; ! Link to next buffer in chain macro DCB$W_STS = 16,0,16,0 %; ! Old word width STS field macro DCB$L_STS = 16,0,32,0 %; macro DCB$V_TYPE_IO = 16,0,1,0 %; ! If set DIRECT if clear buffered macro DCB$L_SVAPTE = 20,0,32,1 %; ! SVAPTE of buffer if not specified ! then the buffer is embedded ! in this buffer macro DCB$W_BOFF = 24,0,16,0 %; ! Offset to start of data. Data macro DCB$L_BOFF = 24,0,32,0 %; ! link headers must be back built ! from this offset. macro DCB$W_BCNT = 28,0,16,0 %; ! segment of the data. For receives macro DCB$L_BCNT = 28,0,32,0 %; ! contains the size of the segment ! of data contained in this buffer. !*** MODULE $DCPIDMSG *** literal DCPI$S_DCPID_MSG = 16; macro DCPI$W_TYPE = 0,0,16,0 %; ! message type macro DCPI$W_RESERVED = 2,0,16,0 %; ! reserved - unused macro DCPI$PQ_KFE_PTR = 8,0,0,1 %; literal DCPI$S_KFE_PTR = 8; ! address of KFE macro DCPI$PQ_IMCB_PTR = 8,0,0,1 %; literal DCPI$S_IMCB_PTR = 8; ! address of IMCB macro DCPI$PQ_LDRIMP_PTR = 8,0,0,1 %; literal DCPI$S_LDRIMP_PTR = 8; ! address of LDRIMG literal DCPI$C_LENGTH = 16; ! length of DCPID_MSG literal DCPI$K_LENGTH = 16; ! length of DCPID_MSG literal DCPI$C_PROC_SCAN = 1; ! process scan message type literal DCPI$C_PROC_RUNDOWN = 2; ! process rundown message type literal DCPI$C_PROC_IMGACT = 3; ! process image activation message type literal DCPI$C_SYS_INSTALL = 4; ! system install message type literal DCPI$C_SYS_DEINSTALL = 5; ! system uninstall message type literal DCPI$C_SYS_LOAD = 6; ! system load message type literal DCPI$C_SYS_UNLOAD = 7; ! system unload message type !*** MODULE $DCRDEF *** ! ! Definitions for Default Control Register (DCR - CR0) ! literal DCR$M_PP = %X'1'; literal DCR$M_BE = %X'2'; literal DCR$M_IC = %X'4'; literal DCR$M_MBZ0 = %X'F8'; literal DCR$M_DM = %X'100'; literal DCR$M_DP = %X'200'; literal DCR$M_DK = %X'400'; literal DCR$M_DX = %X'800'; literal DCR$M_DR = %X'1000'; literal DCR$M_DA = %X'2000'; literal DCR$M_DD = %X'4000'; literal DCR$M_DEFER_ALL = 32512; ! Defer all faults literal DCR$M_MBZ1 = %X'FFFF8000'; literal DCR$M_MBZ2 = %X'FFFFFFFF00000000'; literal DCR$S_DCR = 8; macro DCR$R_DCR_UNION = 0,0,0,0 %; literal DCR$S_DCR_UNION = 8; macro DCR$Q_DEFAULT_CONTROL = 0,0,0,0 %; literal DCR$S_DEFAULT_CONTROL = 8; macro DCR$V_PP = 0,0,1,0 %; ! Privileged Performance monitor default macro DCR$V_BE = 0,1,1,0 %; ! Big-Endian default macro DCR$V_IC = 0,2,1,0 %; ! IA-32 Lock Check enable macro DCR$V_MBZ0 = 0,3,5,0 %; literal DCR$S_MBZ0 = 5; ! Reserved DCR{7:3} (MBZ) macro DCR$V_DM = 0,8,1,0 %; ! Defer TLB Miss faults only macro DCR$V_DP = 0,9,1,0 %; ! Defer Page no Present faults only macro DCR$V_DK = 0,10,1,0 %; ! Defer Key Miss faults only macro DCR$V_DX = 0,11,1,0 %; ! Defer Key Permission faults only macro DCR$V_DR = 0,12,1,0 %; ! Defer Access Rights faults only macro DCR$V_DA = 0,13,1,0 %; ! Defer Access Bit faults only macro DCR$V_DD = 0,14,1,0 %; ! Defer Debug faults macro DCR$V_MBZ1 = 0,15,17,0 %; literal DCR$S_MBZ1 = 17; ! Reserved DCR{31:15} macro DCR$V_MBZ2 = 4,0,32,0 %; literal DCR$S_MBZ2 = 32; ! Reserved DCR{63:32} !*** MODULE $DDBDEF *** ! + ! DDB - DEVICE DATA BLOCK ! ! THERE IS ONE DEVICE DATA BLOCK FOR EACH CONTROLLER IN A SYSTEM. ! + literal DDB$M_NO_TIMEOUT = %X'1'; literal DDB$M_PAC = %X'2'; literal DDB$K_PACK = 1; ! LARGE DISK PACKS literal DDB$K_CART = 2; ! DISK CARTRIDGES literal DDB$K_SLOW = 3; ! SLOW (CHEAP) DISKS (E.G., FLOPPY) literal DDB$K_TAPE = 4; ! BLOCK STRUCTURED TAPE (E.G., TU58) literal DDB$S_DDB = 112; macro DDB$L_LINK = 0,0,32,1 %; ! ADDRESS OF NEXT DDB IN LIST (0=LAST) macro DDB$PS_LINK = 0,0,32,1 %; ! ADDRESS OF NEXT DDB IN LIST (0=LAST) macro DDB$L_UCB = 4,0,32,1 %; ! ADDRESS OF FIRST UCB FOR THIS DDB macro DDB$PS_UCB = 4,0,32,1 %; ! ADDRESS OF FIRST UCB FOR THIS DDB macro DDB$W_SIZE = 8,0,16,0 %; ! SIZE OF DDB IN BYTES macro DDB$IW_SIZE = 8,0,16,0 %; ! SIZE OF DDB IN BYTES macro DDB$B_TYPE = 10,0,8,0 %; ! TYPE OF DATA STRUCTURE FOR DDB macro DDB$IB_TYPE = 10,0,8,0 %; ! TYPE OF DATA STRUCTURE FOR DDB macro DDB$B_FLAGS = 11,0,8,0 %; macro DDB$V_NO_TIMEOUT = 11,0,1,0 %; ! No TIMEOUT handling macro DDB$V_PAC = 11,1,1,0 %; ! Using port allocation class macro DDB$L_DDT = 12,0,32,1 %; ! ADDRESS OF THE DRIVER DISPATCH TABLE macro DDB$PS_DDT = 12,0,32,1 %; ! ADDRESS OF THE DRIVER DISPATCH TABLE macro DDB$L_ACPD = 16,0,32,0 %; ! NAME OF DEFAULT ACP FOR DEVICE UNITS macro DDB$IL_ACPD = 16,0,32,0 %; ! NAME OF DEFAULT ACP FOR DEVICE UNITS macro DDB$B_ACPCLASS = 19,0,8,0 %; ! CLASS CODE OF DEFAULT ACP macro DDB$IB_ACPCLASS = 19,0,8,0 %; ! CLASS CODE OF DEFAULT ACP macro DDB$T_NAME = 20,0,0,0 %; literal DDB$S_NAME = 16; ! GENERIC PATH NAME OF DEVICE macro DDB$B_NAME_LEN = 20,0,8,0 %; ! CHARACTER COUNT macro DDB$IB_NAME_LEN = 20,0,8,0 %; ! CHARACTER COUNT macro DDB$T_NAME_STR = 21,0,0,0 %; literal DDB$S_NAME_STR = 15; ! CHARACTER STRING macro DDB$PS_DPT = 36,0,32,1 %; ! ADDR OF DRIVER DPT macro DDB$PS_DRVLINK = 40,0,32,1 %; ! ADDR OF NEXT DDB FOR THIS DRIVER macro DDB$L_SB = 44,0,32,1 %; ! ADDR OF SYSTEMBLOCK macro DDB$PS_SB = 44,0,32,1 %; ! ADDR OF SYSTEMBLOCK macro DDB$L_CONLINK = 48,0,32,1 %; ! NEXT DDB IN CONNECTION SUB-CHAIN macro DDB$PS_CONLINK = 48,0,32,1 %; ! NEXT DDB IN CONNECTION SUB-CHAIN macro DDB$L_ALLOCLS = 52,0,32,0 %; ! DEVICE ALLOCATION CLASS macro DDB$IL_ALLOCLS = 52,0,32,0 %; ! DEVICE ALLOCATION CLASS macro DDB$L_2P_UCB = 56,0,32,1 %; ! ADDRESS OF FIRST UCB ON SECONDARY PATH macro DDB$PS_2P_UCB = 56,0,32,1 %; ! ADDRESS OF FIRST UCB ON SECONDARY PATH macro DDB$L_DP_UCB = 56,0,32,1 %; ! OLD STYLE SYNONYM FOR ABOVE macro DDB$L_PORT_ID = 60,0,32,0 %; ! Reserved macro DDB$T_PORT_ID = 60,0,8,0 %; literal DDB$S_PORT_ID = 1; ! Reserved macro DDB$L_CLASS_LKID = 64,0,32,0 %; ! Reserved macro DDB$PS_2P_DDB = 68,0,32,1 %; ! Reserved macro DDB$L_SEED_UNIT = 72,0,32,0 %; ! Seed unit macro DDB$L_SEED_PTR = 76,0,32,1 %; ! Seed pointer literal DDB$K_LENGTH = 112; ! LENGTH OF STANDARD DDB literal DDB$C_LENGTH = 112; ! LENGTH OF STANDARD DDB literal DDB$S_DDBDEF = 112; ! OLD DDB SIZE FOR COMPATIBILITY !*** MODULE $DDTDEF *** ! + ! DDT - DRIVER DISPATCH TABLE ! ! EACH DEVICE DRIVER HAS A DRIVER DISPATCH TABLE. ! - literal DDT$M_DIAGBUF64 = 32768; ! Use 64-bit BUFIO for diag buffer if set in DDT$W_DIAGBUF literal DDT$K_ITCLVL_DRVR = 0; ! "Native" Driver literal DDT$K_ITCLVL_MPDEV = 4096; ! Multipath literal DDT$K_ITCLVL_HSM = 24576; ! Hierarchical Storage Manager literal DDT$K_ITCLVL_TOP = 32767; ! Top, with intercepts in place literal DDT$K_LENGTH_MIN = 120; ! Minimum DDT length since V7.0 literal DDT$S_DDT = 152; macro DDT$PS_NEXT_INTERCEPT_DDT = 0,0,32,1 %; ! Pointer to next intercept DDT macro DDT$W_SIZE = 8,0,16,0 %; ! Structure size macro DDT$IW_SIZE = 8,0,16,0 %; ! Structure size macro DDT$B_TYPE = 10,0,8,0 %; ! Nonpaged pool packet type, DYN$C_MISC macro DDT$B_SUBTYPE = 11,0,8,0 %; ! Nonpaged pool packet subtype, DYN$C_DDT macro DDT$W_DIAGBUF = 12,0,16,0 %; ! Size of diagnostic buffer in bytes (low 15-bits) macro DDT$IW_DIAGBUF = 12,0,16,0 %; ! Size of diagnostic buffer in bytes (low 15-bits) macro DDT$W_ERRORBUF = 14,0,16,0 %; ! SIZE OF ERROR LOG BUFFER IN BYTES macro DDT$IW_ERRORBUF = 14,0,16,0 %; ! SIZE OF ERROR LOG BUFFER IN BYTES macro DDT$W_FDTSIZE = 16,0,16,0 %; ! SIZE OF FDT IN BYTES macro DDT$IW_FDTSIZE = 16,0,16,0 %; ! SIZE OF FDT IN BYTES macro DDT$W_INTERCEPT_LEVEL = 18,0,16,1 %; ! Intercept level macro DDT$PS_START_2 = 20,0,32,1 %; ! STEP 2 DRIVER START I/O ROUTINE macro DDT$PS_START_JSB = 24,0,32,1 %; ! STEP 2 DRIVER JSB_START I/O ROUTINE macro DDT$PS_CTRLINIT_2 = 28,0,32,1 %; ! STEP 2 CONTROLLER INITIALIZATION ROUTINE macro DDT$PS_UNITINIT_2 = 32,0,32,1 %; ! STEP 2 UNIT INITIALIZATION ROUTINE macro DDT$PS_CLONEDUCB_2 = 36,0,32,1 %; ! STEP 2 CLONED UCB ROUTINE macro DDT$PS_FDT_2 = 40,0,32,1 %; ! ADDR OF STEP 2 FUNCTION DECISION TABLE macro DDT$PS_CANCEL_2 = 44,0,32,1 %; ! STEP 2 CANCEL I/O ROUTINE macro DDT$PS_REGDUMP_2 = 48,0,32,1 %; ! STEP 2 DEVICE REGISTER DUMP ROUTINE macro DDT$PS_ALTSTART_2 = 52,0,32,1 %; ! STEP 2 ALTERNATE START I/O ROUTINE macro DDT$PS_ALTSTART_JSB = 56,0,32,1 %; ! STEP 2 JSB ALTERNATE START I/O ROUTINE macro DDT$PS_MNTVER_2 = 60,0,32,1 %; ! STEP 2 MOUNT VERIFICATION ROUTINE macro DDT$L_MNTV_SSSC = 64,0,32,1 %; ! ADDRESS OF SHADOW SET STATE CHANGE MV ENTRY macro DDT$PS_MNTV_SSSC = 64,0,32,1 %; ! ADDRESS OF SHADOW SET STATE CHANGE MV ENTRY macro DDT$L_MNTV_FOR = 68,0,32,1 %; ! ADDRESS OF FOREIGN DEVICE MV ENTRY macro DDT$PS_MNTV_FOR = 68,0,32,1 %; ! ADDRESS OF FOREIGN DEVICE MV ENTRY macro DDT$L_MNTV_SQD = 72,0,32,1 %; ! ADDRESS OF SEQUENTIAL DEVICE MV ENTRY macro DDT$PS_MNTV_SQD = 72,0,32,1 %; ! ADDRESS OF SEQUENTIAL DEVICE MV ENTRY macro DDT$L_AUX_STORAGE = 76,0,32,1 %; ! ADDRESS OF AUXILIARY STORAGE AREA macro DDT$PS_AUX_STORAGE = 76,0,32,1 %; ! ADDRESS OF AUXILIARY STORAGE AREA macro DDT$L_AUX_ROUTINE = 80,0,32,1 %; ! ADDRESS OF AUXILIARY ROUTINE macro DDT$PS_AUX_ROUTINE = 80,0,32,1 %; ! ADDRESS OF AUXILIARY ROUTINE macro DDT$PS_CHANNEL_ASSIGN_2 = 84,0,32,1 %; ! STEP 2 ROUTINE TO CALL FROM $ASSIGN macro DDT$PS_CANCEL_SELECTIVE_2 = 88,0,32,1 %; ! STEP 2 SELECTIVE CANCEL I/O ROUTINE macro DDT$IS_STACK_BCNT = 92,0,32,0 %; ! BYTES OF KP STACK REQUIRED macro DDT$IS_REG_MASK = 96,0,32,0 %; ! KP REGISTER SAVE MASK macro DDT$PS_KP_STARTIO = 100,0,32,1 %; ! ADDRESS OF KERNEL PROCESS START I/O ROUTINE macro DDT$PS_CSR_MAPPING = 104,0,32,1 %; ! ADDRESS OF CSR MAPPING ROUTINE macro DDT$PS_FAST_FDT = 108,0,32,1 %; ! Address of Fast-IO fast-FDT routine macro DDT$PS_PENDING_IO = 112,0,32,1 %; ! Address of Pending I/O routine macro DDT$PS_CUSTOMER = 116,0,32,1 %; ! Reserved_to_customer pointer macro DDT$PS_MAKE_DEVPATH = 120,0,32,1 %; ! Address of create path infor. routine macro DDT$PS_SETPRFPATH = 124,0,32,1 %; ! Address of fastpath FDT routine macro DDT$PS_CHANGE_PREFERRED = 128,0,32,1 %; ! Address of fastpath upcall routine macro DDT$L_MPDEV_SPARE_1 = 132,0,32,0 %; ! Old QIOserver cell macro DDT$L_MPDEV_SPARE_2 = 136,0,32,0 %; ! Old QIOserver cell macro DDT$PS_MGT_REGISTER = 140,0,32,1 %; ! Address of RMdriver Object registration routine macro DDT$PS_CONFIGURE = 140,0,32,1 %; ! Address of USB configure routine macro DDT$PS_MGT_DEREGISTER = 144,0,32,1 %; ! Address of RMdriver Object deregistration routine macro DDT$PS_DECONFIGURE = 144,0,32,1 %; ! Address of USB deconfigure routine macro DDT$PS_MPDEV_PATH_SWTCH = 148,0,32,1 %; ! Address of mpdev_path_swtch routine literal DDT$K_LENGTH = 152; ! LENGTH OF DDT literal DDT$C_LENGTH = 152; ! LENGTH OF DDT literal DDT$S_DDTDEF = 152; ! OLD DDT LENGTH NAME FOR COMPATIBILITY !*** MODULE $DEADEF *** ! ! Define the layout of the Deaccess Audit Pending block. This record is ! used to store the information necessary to write a deaccess audit event ! upon object deaccess. These records are queued off a per-process queue ! (NSA$GQ_DEACCESS_AUDIT) and managed by NSA$QUEUE_DEACCESS_AUDIT, ! NSA$DEACCESS_AUDIT, and $DELPRC. ! literal DEA$K_LENGTH = 48; ! Define flags used by the NSA$DEACCESS_AUDIT routine. literal DEA$K_FLUSH_ALL = 1; ! flush all DEAs literal DEA$K_FLUSH_BY_OCB = 2; ! flush all DEAs by object class literal DEA$S_DEA = 48; macro DEA$L_FLINK = 0,0,32,1 %; ! FLINK macro DEA$L_BLINK = 4,0,32,1 %; ! BLINK macro DEA$L_SIZE = 8,0,32,0 %; ! size of DEA record macro DEA$L_TYPE = 12,0,32,0 %; ! type of structure (DYN$C_DEA) macro DEA$L_FLAGS = 16,0,32,0 %; ! flags (unused) macro DEA$L_DEACCESS_KEY = 20,0,32,0 %; ! deaccess audit key macro DEA$L_AUDIT_MASK = 24,0,32,0 %; ! alarm/audit mask macro DEA$L_OCB = 28,0,32,1 %; ! OCB address macro DEA$L_ALARM_SIZE = 32,0,32,0 %; ! size of alarm string macro DEA$L_AUDIT_SIZE = 36,0,32,0 %; ! size of audit string macro DEA$L_ALARM = 40,0,32,1 %; ! alarm string address macro DEA$L_AUDIT = 44,0,32,1 %; ! audit string address !*** MODULE $DEVCFG_CBKDEF *** ! + ! DEVCFG_CBK - Devconfig call back ! ! The routines ioc_std$devconfig_register and ioc_std$devconfig_deregister ! maintain a singly-linked list of device configure call back structure ! (DEVCFG_CBK structures). ! A new entry is added by a successful call to the registration routine and ! an existing entry can be removed by calling the deregistration routine. ! The registration routine would minimally specify a device class ! and a callback routine address. Subsequently, when a new device ! is configured of that class, the specified callback routine would be ! called. ! The head of the list is stored at IOC$GL_DEVCFG_CBK. ! - literal DEVCFG_CBK$S_DEVCFG_CBK = 40; macro DEVCFG_CBK$PS_FLINK = 0,0,32,1 %; ! Forward pointer macro DEVCFG_CBK$L_RESERVED1 = 4,0,32,0 %; ! Reserved longword macro DEVCFG_CBK$W_SIZE = 8,0,16,0 %; ! Structure size macro DEVCFG_CBK$B_TYPE = 10,0,8,0 %; ! Structure type, DYN$C_MISC macro DEVCFG_CBK$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype, DYN$C_DEVCFG_CBK macro DEVCFG_CBK$L_FLAGS = 12,0,32,0 %; ! Validated flag specified in registration call ! may contain another flag in the future macro DEVCFG_CBK$L_DEVCLASS = 16,0,32,0 %; ! Device class specified in registration call macro DEVCFG_CBK$PS_DEVCONFIGURED = 20,0,32,1 %; ! Callback routine specified ! in registration call macro DEVCFG_CBK$Q_USER_PARAM = 24,0,0,0 %; literal DEVCFG_CBK$S_USER_PARAM = 8; ! Parameter specified in registration call macro DEVCFG_CBK$L_NUM_CALLS = 32,0,32,0 %; ! Number of times this call back invoked (diagnosis) macro DEVCFG_CBK$PS_LAST_UCB = 36,0,32,1 %; ! Last UCB address for which call back invoked (diagnosis) literal DEVCFG_CBK$K_LENGTH = 40; ! Size of fixed size DEVCFG_CBK !*** MODULE $DJIDEF *** ! ! Item codes for interface from job controller to LOGINOUT. ! literal DJI$K_CPU_MAXIMUM = 1; ! (longword) CPU maximum (10 ms units) literal DJI$K_FILE_IDENTIFICATION = 2; ! (28 bytes) DVI, FID, DID of command procedure literal DJI$K_FLAGS = 3; ! (longword) flags literal DJI$K_JOB_NAME = 4; ! (string) job name literal DJI$K_LOG_QUEUE = 5; ! (string) log file queue literal DJI$K_LOG_SPECIFICATION = 6; ! (string) log file specification literal DJI$K_PARAMETER_1 = 7; ! (string) value of P1 literal DJI$K_PARAMETER_2 = 8; ! (string) value of P2 literal DJI$K_PARAMETER_3 = 9; ! (string) value of P3 literal DJI$K_PARAMETER_4 = 10; ! (string) value of P4 literal DJI$K_PARAMETER_5 = 11; ! (string) value of P5 literal DJI$K_PARAMETER_6 = 12; ! (string) value of P6 literal DJI$K_PARAMETER_7 = 13; ! (string) value of P7 literal DJI$K_PARAMETER_8 = 14; ! (string) value of P8 literal DJI$K_RESTART = 15; ! (string) value of BATCH$RESTART literal DJI$K_USERNAME = 16; ! (string) username literal DJI$K_WSDEFAULT = 17; ! (longword) working set default literal DJI$K_WSEXTENT = 18; ! (longword) working set extent literal DJI$K_WSQUOTA = 19; ! (longword) working set quota literal DJI$K_ADJUST_PRIORITY = 20; ! (longword) adjusted priority literal DJI$K_CLI = 21; ! (string) CLI name literal DJI$K_CLASS = 22; ! (20 bytes) process classification literal DJI$K_NOTE = 23; ! (string) the job's note literal DJI$K_CHARGE_CODE_NAME = 24; ! (string) account or charge code name literal DJI$K_INPUT_FLAGS = 32769; ! (longword) flags literal DJI$K_CONDITION_VECTOR = 32770; ! (1 to 3 longwords) error conditions literal DJI$K_FILE_SPECIFICATION = 32771; ! (string) filespec of failed logfile literal DJI$S_DJI_ITEM_HEADER = 4; macro DJI$W_ITEM_SIZE = 0,0,16,0 %; ! Item size macro DJI$W_ITEM_CODE = 2,0,16,0 %; ! Item code literal DJI$S_ITEM_HEADER = 4; ! Size (using prior aggregate name) ! ! Structure of FLAGS item. ! literal DJI$M_DELETE_FILE = %X'1'; literal DJI$M_LOG_DELETE = %X'2'; literal DJI$M_LOG_NULL = %X'4'; literal DJI$M_LOG_SPOOL = %X'8'; literal DJI$M_NOTIFY = %X'10'; literal DJI$M_RESTARTING = %X'20'; literal DJI$M_TERMINATE = %X'40'; literal DJI$M_USE_CPU_MAXIMUM = %X'80'; literal DJI$M_USE_WSDEFAULT = %X'100'; literal DJI$M_USE_WSEXTENT = %X'200'; literal DJI$M_USE_WSQUOTA = %X'400'; literal DJI$S_FLAGS = 4; ! Old size name synonym literal DJI$S_DJI_FLAGS = 4; macro DJI$L_FLAGS = 0,0,32,0 %; macro DJI$V_DELETE_FILE = 0,0,1,0 %; ! delete command procedure macro DJI$V_LOG_DELETE = 0,1,1,0 %; ! delete log file macro DJI$V_LOG_NULL = 0,2,1,0 %; ! log specification is NLA0: macro DJI$V_LOG_SPOOL = 0,3,1,0 %; ! spool log file macro DJI$V_NOTIFY = 0,4,1,0 %; ! spool log file with /NOTIFY macro DJI$V_RESTARTING = 0,5,1,0 %; ! job is restarting macro DJI$V_TERMINATE = 0,6,1,0 %; ! job should terminate macro DJI$V_USE_CPU_MAXIMUM = 0,7,1,0 %; ! use specified CPU_MAXIMUM macro DJI$V_USE_WSDEFAULT = 0,8,1,0 %; ! use specified WSDEFAULT macro DJI$V_USE_WSEXTENT = 0,9,1,0 %; ! use specified WSEXTENT macro DJI$V_USE_WSQUOTA = 0,10,1,0 %; ! use specified WSQUOTA ! ! Structure of INPUT_FLAGS item. ! literal DJI$M_NO_FILE = %X'1'; literal DJI$S_INPUT_FLAGS = 4; ! Old size name synonym literal DJI$S_DJI_INPUT_FLAGS = 4; macro DJI$L_INPUT_FLAGS = 0,0,32,0 %; macro DJI$V_NO_FILE = 0,0,1,0 %; ! do not return a file !*** MODULE $DMBDEF *** ! + ! DMB32 (BICOMBO) specific register definitions ! - literal DMB$M_FORCE_FAIL = %X'1'; literal DMB$M_PROGRAM_RESET = %X'2'; literal DMB$M_PTE_VALID = %X'4'; literal DMB$M_SKIP_SELFTEST = %X'8'; literal DMB$M_MAINT_LEVEL1 = %X'10'; literal DMB$M_MAINT_LEVEL2 = %X'20'; literal DMB$M_SYNC = %X'100'; literal DMB$M_ASYNC = %X'200'; literal DMB$M_PRINT = %X'400'; literal DMB$M_DIAG_FAIL = %X'800'; literal DMB$M_X21_SUPPORT = %X'1000'; literal DMB$M_CABLE_KEY = %X'2000'; literal DMB$M_TURN_CONN = %X'4000'; literal DMB$M_MANF_CONN = %X'8000'; literal DMB$M_RX_I_E = %X'100'; literal DMB$M_TX_I_E = %X'200'; literal DMB$M_SYNC_I_E = %X'800'; literal DMB$M_PR_I_E = %X'800'; literal DMB$M_PR_DAVFU_READY = %X'10000'; literal DMB$M_PR_CONNECT_VERIFY = %X'20000'; literal DMB$M_PR_OFFLINE = %X'40000'; literal DMB$M_ASYNC_RESET = %X'400'; literal DMB$M_SYNC_RESET = %X'400'; literal DMB$M_PRINTER_RESET = %X'400'; literal DMB$M_PR_DMA_START = %X'1'; literal DMB$M_PR_DMA_PTE = %X'2'; literal DMB$M_PR_DMA_PHYS = %X'4'; literal DMB$M_PR_DMA_ABORT = %X'100'; literal DMB$M_PR_FORMAT = %X'200'; literal DMB$M_PR_TAB = %X'1000000'; literal DMB$M_PR_TRUNC = %X'2000000'; literal DMB$M_PR_AUTO_RETURN = %X'4000000'; literal DMB$M_PR_AUTO_FORM = %X'8000000'; literal DMB$M_PR_NON_PRINT = %X'10000000'; literal DMB$M_PR_DAVFU = %X'20000000'; literal DMB$M_PR_WRAP = %X'40000000'; literal DMB$M_PR_UPPER = %X'80000000'; literal DMB$M_TX1_DMA_START = %X'1'; literal DMB$M_TX1_DMA_PTE = %X'2'; literal DMB$M_TX1_DMA_PHYS = %X'4'; literal DMB$M_TX1_X21 = %X'8'; literal DMB$M_TX1_PAR = %X'10'; literal DMB$M_TX1_DMA_ABORT = %X'100'; literal DMB$M_RX1_DMA_START = %X'1'; literal DMB$M_RX1_DMA_PTE = %X'2'; literal DMB$M_RX1_DMA_PHYS = %X'4'; literal DMB$M_RX1_X21 = %X'8'; literal DMB$M_RX1_DMA_ABORT = %X'100'; literal DMB$M_RX_ENABLE = %X'1'; literal DMB$M_RX_MATCH_ENA = %X'4'; literal DMB$M_RX_PRIMARY = %X'8'; literal DMB$M_X21ENABLE = %X'10'; literal DMB$M_CLOCK_CONTROL = %X'40'; literal DMB$M_CODING_TYPE = %X'80'; literal DMB$M_BAUD_RATE = %X'F00'; literal DMB$M_LOOP = %X'1000'; literal DMB$M_V35_SELECT = %X'2000'; literal DMB$M_V10_SELECT = %X'4000'; literal DMB$M_MODEM_SUPPRESS = %X'8000'; literal DMB$M_LINE_RESET = %X'80000000'; literal DMB$M_SYNC_ML1 = %X'1'; literal DMB$M_SYNC_DTR = %X'2'; literal DMB$M_SYNC_DRS = %X'4'; literal DMB$M_SYNC_ML2 = %X'8'; literal DMB$M_SYNC_RTS = %X'10'; literal DMB$M_SPARE_MODEM = %X'E0'; literal DMB$M_SYNC_RXCLOCK = %X'100'; literal DMB$M_SYNC_TXCLOCK = %X'200'; literal DMB$M_SYNC_TI = %X'400'; literal DMB$M_SYNC_CTS = %X'1000'; literal DMB$M_SYNC_DCD = %X'2000'; literal DMB$M_SYNC_RI = %X'4000'; literal DMB$M_SYNC_DSR = %X'8000'; literal DMB$M_PROTOCOL = %X'70000'; literal DMB$C_PRO_DDCMP = 0; literal DMB$C_PRO_SDLC = 1; literal DMB$C_PRO_HDLC = 2; literal DMB$C_PRO_BISYNC = 3; literal DMB$C_PRO_GENBYTE = 7; literal DMB$M_ERROR_TYPE = %X'380000'; literal DMB$C_ERR_CRC1 = 0; literal DMB$C_ERR_CRC0 = 1; literal DMB$C_ERR_LVE = 2; literal DMB$C_ERR_CRC16 = 3; literal DMB$C_ERR_LRC0 = 4; literal DMB$C_ERR_LRCE = 5; literal DMB$C_ERR_LVO = 6; literal DMB$C_NOCON = 7; literal DMB$M_RX_BPC = %X'1C00000'; literal DMB$M_TX_BPC = %X'E000000'; literal DMB$M_STRIP_SYNC = %X'10000000'; literal DMB$M_EBCDIC_CODE = %X'20000000'; literal DMB$M_IDLE_SYNC = %X'40000000'; literal DMB$M_MODEM_OVERRIDE = %X'80000000'; literal DMB$M_TX2_DMA_START = %X'1'; literal DMB$M_TX2_DMA_PTE = %X'2'; literal DMB$M_TX2_DMA_PHYS = %X'4'; literal DMB$M_TX2_X21 = %X'8'; literal DMB$M_TX2_PAR = %X'10'; literal DMB$M_TX2_DMA_ABORT = %X'100'; literal DMB$M_RX2_DMA_START = %X'1'; literal DMB$M_RX2_DMA_PTE = %X'2'; literal DMB$M_RX2_DMA_PHYS = %X'4'; literal DMB$M_RX2_X21 = %X'8'; literal DMB$M_RX2_DMA_ABORT = %X'100'; literal DMB$M_SYNC_CABLE = %X'F000000'; literal DMB$M_SYNC_LOOP = %X'20000000'; literal DMB$M_SYNC_VALID = %X'40000000'; literal DMB$M_SYNC_X21 = %X'80000000'; literal DMB$M_PREEMPT_GO = %X'8000'; literal DMB$M_ML = %X'1'; literal DMB$M_DTR = %X'2'; literal DMB$M_DRS = %X'4'; literal DMB$M_RTS = %X'10'; literal DMB$M_TX_INT_DELAY = %X'200'; literal DMB$M_RX_ENA = %X'400'; literal DMB$M_BREAK = %X'800'; literal DMB$M_MAINT = %X'3000'; literal DMB$M_REPORT_MODEM = %X'4000'; literal DMB$M_DISCARD_FLOW = %X'8000'; literal DMB$M_CHAR_LENGTH = %X'30000'; literal DMB$M_PARITY_ENAB = %X'40000'; literal DMB$M_EVEN_PARITY = %X'80000'; literal DMB$M_STOP_CODE = %X'100000'; literal DMB$M_USE_CTS = %X'200000'; literal DMB$M_IAUTO_FLOW = %X'400000'; literal DMB$M_OAUTO_FLOW = %X'800000'; literal DMB$M_RX_SPEED = %X'F000000'; literal DMB$M_TX_SPEED = %X'F0000000'; literal DMB$M_TX_DMA_START = %X'1'; literal DMB$M_TX_DMA_PTE = %X'2'; literal DMB$M_TX_DMA_PHYS = %X'4'; literal DMB$M_TX_OUT_ABORT = %X'100'; literal DMB$M_ML2 = %X'400'; literal DMB$M_CTS = %X'1000'; literal DMB$M_DCD = %X'2000'; literal DMB$M_RI = %X'4000'; literal DMB$M_DSR = %X'8000'; literal DMB$M_SNDOFF = %X'800000'; literal DMB$M_TX_ENA = %X'80000000'; literal DMB$M_TX_PREEMPT = %X'100'; literal DMB$M_TX_FIFO_DONE = %X'200'; literal DMB$M_TX_ACT = %X'80000000'; literal DMB$M_SYNC_MODEM = %X'100'; literal DMB$M_SYNC_TX_ACT = %X'200'; literal DMB$M_SYNC_SECOND_BUFFER = %X'400'; literal DMB$M_PARITY_ERR = %X'1000'; literal DMB$M_FRAME_ERR = %X'2000'; literal DMB$M_OVERRUN_ERR = %X'4000'; literal DMB$M_NON_CHAR = %X'8000'; literal DMB$M_DATA_VALID = %X'80000000'; literal DMB$C_NO_ERROR = 0; literal DMB$C_DMA_ERROR = 1; literal DMB$C_MSG_ERROR = 2; literal DMB$C_LAST_CHAR_ERROR = 3; literal DMB$C_BUFFER_ERROR = 4; literal DMB$C_MODEM_ERROR = 5; literal DMB$C_ABORT_ERROR = 6; literal DMB$C_X21_ERROR = 7; literal DMB$C_OFFLINE_ERROR = 8; literal DMB$C_INTERNAL_ERROR = 9; literal DMB$C_HEADER_CRC_ERROR = 1; literal DMB$C_DATA_CRC_ERROR = 2; literal DMB$C_LENGTH_ERROR = 3; literal DMB$C_LENGTH_AND_CRC_ERROR = 4; literal DMB$C_ABORT_CHARACTER_ERROR = 5; literal DMB$C_INVALID_CHARACTER_ERROR = 6; literal DMB$C_HOST_ABORT_ERROR = 1; literal DMB$C_DMB_ABORT_ERROR = 2; literal DMB$C_RX_OVERRUN_ERROR = 1; literal DMB$C_TX_UNDERRUN_ERROR = 2; literal DMB$S_DMBDEF = 528; ! Old size name - synonym literal DMB$S_DMB = 528; macro DMB$L_MAINT = 256,0,32,0 %; ! Maintenance register macro DMB$V_FORCE_FAIL = 256,0,1,0 %; ! Force failure macro DMB$V_PROGRAM_RESET = 256,1,1,0 %; ! Programmed reset macro DMB$V_PTE_VALID = 256,2,1,0 %; ! Page tables valid macro DMB$V_SKIP_SELFTEST = 256,3,1,0 %; ! Skip self test macro DMB$V_MAINT_LEVEL1 = 256,4,1,0 %; ! Maintenance level 1 macro DMB$V_MAINT_LEVEL2 = 256,5,1,0 %; ! Maintenance level 2 macro DMB$V_SYNC = 256,8,1,0 %; ! Sync lines present macro DMB$V_ASYNC = 256,9,1,0 %; ! Async lines present macro DMB$V_PRINT = 256,10,1,0 %; ! Printer present macro DMB$V_DIAG_FAIL = 256,11,1,0 %; ! Diagnostic error macro DMB$V_X21_SUPPORT = 256,12,1,0 %; ! X21 firmware support present macro DMB$V_CABLE_KEY = 256,13,1,0 %; ! Cable key signal present macro DMB$V_TURN_CONN = 256,14,1,0 %; ! stag. loopback conn. present macro DMB$V_MANF_CONN = 256,15,1,0 %; ! Mfg. loopback conn. present ! ! The following 3 registers are the Control Status Registers (CSRs) for ! the Async, Sync, and Printer ports in that order. ! macro DMB$L_ACSR = 260,0,32,0 %; ! Async Control Status Register macro DMB$B_ASYNC_IND_ADD = 260,0,8,1 %; ! Indirect Addr. Register Ptr. macro DMB$V_RX_I_E = 260,8,1,0 %; ! Receive Interrupt Enable macro DMB$V_TX_I_E = 260,9,1,0 %; ! Transmit Interrupt Enable macro DMB$L_SCSR = 264,0,32,0 %; ! Sync Control Status Register macro DMB$B_SYNC_IND_ADD = 264,0,8,1 %; ! Indirect Addr. Register Ptr. macro DMB$V_SYNC_I_E = 264,11,1,0 %; ! Sync Interrupt Enable macro DMB$L_PCSR = 268,0,32,0 %; ! Printer Control Status Register macro DMB$V_PR_I_E = 268,11,1,0 %; ! Printer Interrupt Enable macro DMB$V_PR_DAVFU_READY = 268,16,1,0 %; ! DAVFU ready macro DMB$V_PR_CONNECT_VERIFY = 268,17,1,0 %; ! Connect verify macro DMB$V_PR_OFFLINE = 268,18,1,0 %; ! Line printer error ! ! Configuration of devices on DMB32. ! macro DMB$L_CONFIG = 276,0,32,0 %; ! Device Configuration macro DMB$B_ASYNC_LINES = 276,0,8,1 %; ! Number of async lines macro DMB$B_SYNC_LINES = 277,0,8,1 %; ! Number of sync lines macro DMB$B_PRINTER_LINES = 278,0,8,1 %; ! Number of printer ports ! ! The following 3 registers are the 2nd Control Status Registers for ! each of the ports on the DMB32 (Async, Sync, and Printer). ! macro DMB$L_ACSR2 = 280,0,32,1 %; ! 2ND Async Control Status Register macro DMB$V_ASYNC_RESET = 280,10,1,0 %; ! Async Port reset macro DMB$B_RX_TIMER = 282,0,8,1 %; ! Rcv Interrupt delay timer macro DMB$L_SCSR2 = 284,0,32,1 %; ! 2ND Sync Control Status Register macro DMB$V_SYNC_RESET = 284,10,1,0 %; ! Sync Port reset macro DMB$L_PCSR2 = 288,0,32,0 %; ! 2ND Printer Control Status Register macro DMB$V_PRINTER_RESET = 288,10,1,0 %; ! Printer Port reset macro DMBDEF$$_FILL_11 = 292,0,0,1 %; literal DMBDEFS_FILL_11 = 44; macro DMB$L_SPTE = 336,0,32,0 %; ! SPTE system page table register macro DMB$L_SPTS = 340,0,32,0 %; ! System page table size register macro DMB$L_GPTE = 344,0,32,0 %; ! Global page table register macro DMB$L_GPTS = 348,0,32,0 %; ! Global page table size register ! ! The following 6 registers are specific to the printer port on the ! DMB32. ! macro DMB$L_PFIX = 352,0,32,0 %; ! Printer prefix/suffix control macro DMB$B_PREFIX_COUNT = 352,0,8,1 %; ! Prefix count macro DMB$B_PREFIX_CHAR = 353,0,8,1 %; ! Prefix character macro DMB$B_SUFFIX_COUNT = 354,0,8,1 %; ! Suffix count macro DMB$B_SUFFIX_CHAR = 355,0,8,1 %; ! Suffix character macro DMB$L_PBUFAD = 356,0,32,1 %; ! Printer Buffer Address macro DMB$L_PBUFCT = 360,0,32,0 %; ! Printer Buffer count/offset macro DMB$W_PR_BUFF_OFF = 360,0,16,1 %; ! printer buffer offset macro DMB$W_PR_BUFF_CT = 362,0,16,1 %; ! transmit DMA char. count macro DMB$L_PCTRL = 364,0,32,0 %; ! Printer Control Register macro DMB$V_PR_DMA_START = 364,0,1,0 %; ! Start a DMA transfer macro DMB$V_PR_DMA_PTE = 364,1,1,0 %; ! PTE address macro DMB$V_PR_DMA_PHYS = 364,2,1,0 %; ! Physical address macro DMB$V_PR_DMA_ABORT = 364,8,1,0 %; ! Abort a DMA transfer macro DMB$V_PR_FORMAT = 364,9,1,0 %; ! Format control macro DMB$B_PR_ERROR = 366,0,8,1 %; ! Error code macro DMB$V_PR_TAB = 364,24,1,0 %; ! Tab expansion macro DMB$V_PR_TRUNC = 364,25,1,0 %; ! Truncation of Data macro DMB$V_PR_AUTO_RETURN = 364,26,1,0 %; ! Auto CR insert macro DMB$V_PR_AUTO_FORM = 364,27,1,0 %; ! Auto FF to LF convert macro DMB$V_PR_NON_PRINT = 364,28,1,0 %; ! Non printing char. accept macro DMB$V_PR_DAVFU = 364,29,1,0 %; ! DAVFU macro DMB$V_PR_WRAP = 364,30,1,0 %; ! Line Wrap macro DMB$V_PR_UPPER = 364,31,1,0 %; ! Convert to upper case macro DMB$L_PCAR = 368,0,32,0 %; ! Printer Carriage Counter macro DMB$W_PR_LINE = 368,0,16,1 %; ! Lines printed macro DMB$W_PR_CHAR = 370,0,16,1 %; ! Characters transmitted macro DMB$L_PSIZE = 372,0,32,0 %; ! Printer page size macro DMB$W_PR_WIDTH = 372,0,16,1 %; ! Line Width macro DMB$W_PR_PAGE = 374,0,16,1 %; ! Page size ! ! The next 16 registers are specific to the SYNC port on the DMB32. ! macro DMB$L_TBUFFAD1 = 384,0,32,1 %; ! Transmit Buffer Address 1 macro DMB$L_TBUFFCT1 = 388,0,32,0 %; ! Transmit Buffer Count/offset 1 macro DMB$W_TX_BUFF_OFF1 = 388,0,16,1 %; ! Transmit buffer offset macro DMB$W_TX_CHAR_CT1 = 390,0,16,1 %; ! Transmit DMA character count macro DMB$L_RBUFFAD1 = 392,0,32,1 %; ! Receive Buffer Address 1 macro DMB$L_RBUFFCT1 = 396,0,32,0 %; ! Receive Buffer Count/offset 1 macro DMB$W_RX_BUFF_OFF1 = 396,0,16,1 %; ! Receive buffer offset macro DMB$W_RX_CHAR_CT1 = 398,0,16,1 %; ! Receive DMA character count macro DMB$L_TLNCTRL1 = 400,0,32,0 %; ! Buffer 1 Transmit Control macro DMB$V_TX1_DMA_START = 400,0,1,0 %; ! Start a DMA transfer macro DMB$V_TX1_DMA_PTE = 400,1,1,0 %; ! PTE address macro DMB$V_TX1_DMA_PHYS = 400,2,1,0 %; ! Physical address macro DMB$V_TX1_X21 = 400,3,1,0 %; ! X.21 mode macro DMB$V_TX1_PAR = 400,4,1,0 %; ! Parameter change macro DMB$V_TX1_DMA_ABORT = 400,8,1,0 %; ! Transmitter DMA abort macro DMB$B_TX1_ERROR = 403,0,8,1 %; ! Transmitter Error bits macro DMB$L_RLNCTRL1 = 404,0,32,0 %; ! Buffer 1 Receive Control macro DMB$V_RX1_DMA_START = 404,0,1,0 %; ! Start a DMA transfer macro DMB$V_RX1_DMA_PTE = 404,1,1,0 %; ! PTE address macro DMB$V_RX1_DMA_PHYS = 404,2,1,0 %; ! Physical address macro DMB$V_RX1_X21 = 404,3,1,0 %; ! X.21 mode macro DMB$V_RX1_DMA_ABORT = 404,8,1,0 %; ! Receiver DMA abort macro DMB$B_RX1_ERROR = 407,0,8,1 %; ! Receiver error bits macro DMB$L_LPR1 = 408,0,32,0 %; ! Sync line parameters 1 macro DMB$V_RX_ENABLE = 408,0,1,0 %; ! Receiver Enable macro DMB$V_RX_MATCH_ENA = 408,2,1,0 %; ! Receiver Match character enable macro DMB$V_RX_PRIMARY = 408,3,1,0 %; ! Primary-Secondary Station macro DMB$V_X21ENABLE = 408,4,1,0 %; ! X21 Protocol Enable macro DMB$V_CLOCK_CONTROL = 408,6,1,0 %; ! Clock control bit macro DMB$V_CODING_TYPE = 408,7,1,0 %; ! Data coding type macro DMB$V_BAUD_RATE = 408,8,4,0 %; literal DMB$S_BAUD_RATE = 4; ! Internal B.R. Generator speed macro DMB$V_LOOP = 408,12,1,0 %; ! Maintenance Loop back macro DMB$V_V35_SELECT = 408,13,1,0 %; ! V.35 select macro DMB$V_V10_SELECT = 408,14,1,0 %; ! V.10 select macro DMB$V_MODEM_SUPPRESS = 408,15,1,0 %; ! Supress modem change ints macro DMB$B_NUMBER_SYNC = 410,0,8,1 %; ! Number of sync characters macro DMB$V_LINE_RESET = 408,31,1,0 %; ! Line reset request macro DMB$L_LPR2 = 412,0,32,0 %; ! Sync line parameters 2 macro DMB$V_SYNC_ML1 = 412,0,1,0 %; ! Modem loop output macro DMB$V_SYNC_DTR = 412,1,1,0 %; ! Data terminal ready output macro DMB$V_SYNC_DRS = 412,2,1,0 %; ! Data rate select output macro DMB$V_SYNC_ML2 = 412,3,1,0 %; ! 2nd modem loop output macro DMB$V_SYNC_RTS = 412,4,1,0 %; ! Request to send output macro DMB$V_SPARE_MODEM = 412,5,3,0 %; literal DMB$S_SPARE_MODEM = 3; ! macro DMB$V_SYNC_RXCLOCK = 412,8,1,0 %; ! Receive clock running macro DMB$V_SYNC_TXCLOCK = 412,9,1,0 %; ! Transmit clock running macro DMB$V_SYNC_TI = 412,10,1,0 %; ! Test indicator macro DMB$V_SYNC_CTS = 412,12,1,0 %; ! Clear to send input macro DMB$V_SYNC_DCD = 412,13,1,0 %; ! Data carrier detect input macro DMB$V_SYNC_RI = 412,14,1,0 %; ! Ring indicator input macro DMB$V_SYNC_DSR = 412,15,1,0 %; ! Data set ready input macro DMB$V_PROTOCOL = 412,16,3,0 %; literal DMB$S_PROTOCOL = 3; ! Protocol type macro DMB$V_ERROR_TYPE = 412,19,3,0 %; literal DMB$S_ERROR_TYPE = 3; macro DMB$V_RX_BPC = 412,22,3,0 %; literal DMB$S_RX_BPC = 3; ! #of receive bits per char. macro DMB$V_TX_BPC = 412,25,3,0 %; literal DMB$S_TX_BPC = 3; ! # of transmit bits per char. macro DMB$V_STRIP_SYNC = 412,28,1,0 %; ! Strip Sync macro DMB$V_EBCDIC_CODE = 412,29,1,0 %; ! Character code macro DMB$V_IDLE_SYNC = 412,30,1,0 %; ! Idle Sync macro DMB$V_MODEM_OVERRIDE = 412,31,1,0 %; ! Modem control override macro DMB$L_TBUFFAD2 = 416,0,32,1 %; ! Transmit Buffer Address 2 macro DMB$L_TBUFFCT2 = 420,0,32,0 %; ! Transmit Buffer count/offset 1 macro DMB$W_TX_BUFF_OFF2 = 420,0,16,1 %; ! Transmit buffer offset macro DMB$W_TX_CHAR_CT2 = 422,0,16,1 %; ! Transmit DMA character count macro DMB$L_RBUFFAD2 = 424,0,32,1 %; ! Receive Buffer Address 2 macro DMB$L_RBUFFCT2 = 428,0,32,0 %; ! Receive Buffer count/offset 2 macro DMB$W_RX_BUFF_OFF2 = 428,0,16,1 %; ! Receive buffer offset macro DMB$W_RX_CHAR_CT2 = 430,0,16,1 %; ! Receive DMA character count macro DMB$L_TLNCTRL2 = 432,0,32,0 %; ! Buffer 2 Transmit Control macro DMB$V_TX2_DMA_START = 432,0,1,0 %; ! Start a DMA transfer macro DMB$V_TX2_DMA_PTE = 432,1,1,0 %; ! PTE address macro DMB$V_TX2_DMA_PHYS = 432,2,1,0 %; ! Physical address macro DMB$V_TX2_X21 = 432,3,1,0 %; ! X.21 mode macro DMB$V_TX2_PAR = 432,4,1,0 %; ! Parameter change macro DMB$V_TX2_DMA_ABORT = 432,8,1,0 %; ! Transmitter DMA abort macro DMB$B_TX2_ERROR = 435,0,8,1 %; ! Transmitter error bits macro DMB$L_RLNCTRL2 = 436,0,32,0 %; ! Buffer 2 Receive control macro DMB$V_RX2_DMA_START = 436,0,1,0 %; ! Start a DMA transfer macro DMB$V_RX2_DMA_PTE = 436,1,1,0 %; ! PTE address macro DMB$V_RX2_DMA_PHYS = 436,2,1,0 %; ! Physical address macro DMB$V_RX2_X21 = 436,3,1,0 %; ! X.21 mode macro DMB$V_RX2_DMA_ABORT = 436,8,1,0 %; ! Receiver DMA abort macro DMB$B_RX2_ERROR = 439,0,8,1 %; ! Receiver error bits macro DMB$L_LPR3 = 440,0,32,0 %; ! Sync Line parameters 3 macro DMB$B_SYNC_CHAR = 440,0,8,1 %; ! Sync character macro DMB$B_RX_MATCH = 441,0,8,1 %; ! Receive match character macro DMB$B_ADDRESS1 = 442,0,8,1 %; ! First address character macro DMB$B_ADDRESS2 = 443,0,8,1 %; ! Second address character macro DMB$L_BUFCTRL = 444,0,32,0 %; ! Sync Buffer Control Bits macro DMB$B_TX_BUFF_PRIO = 444,0,8,1 %; ! Transmitter Buf. Priority macro DMB$B_RX_BUFF_PRIO = 445,0,8,1 %; ! Receiver Buffer Priority macro DMB$B_SYNC_TEST_INPUT = 446,0,8,1 %; ! Test inputs macro DMB$V_SYNC_CABLE = 444,24,4,0 %; literal DMB$S_SYNC_CABLE = 4; ! Electrical Configuration macro DMB$V_SYNC_LOOP = 444,29,1,0 %; ! Loopback present macro DMB$V_SYNC_VALID = 444,30,1,0 %; ! Valid cable macro DMB$V_SYNC_X21 = 444,31,1,0 %; ! X.21 Mode ! ! The next 10 registers are for the async port on the DMB32 ! macro DMB$L_PREEMPT = 448,0,32,0 %; ! Preempt Buffer macro DMB$B_PREEMPT_CHAR = 448,0,8,1 %; ! Character to Transmit macro DMB$V_PREEMPT_GO = 448,15,1,0 %; ! Start Preempt macro DMB$L_TBUFFAD = 452,0,32,1 %; ! Transmit Buffer Address macro DMB$L_TBUFFCT = 456,0,32,0 %; ! Transmit Buffer Count-Offset macro DMB$W_TX_BUFF_OFF = 456,0,16,1 %; ! Transmit Buffer Offset macro DMB$W_TX_CHAR_CT = 458,0,16,1 %; ! Transmit Buffer Count macro DMB$L_LPR = 460,0,32,0 %; ! Line parameter register macro DMB$V_ML = 460,0,1,0 %; ! Modem Loop macro DMB$V_DTR = 460,1,1,0 %; ! Data Terminal Ready macro DMB$V_DRS = 460,2,1,0 %; ! Data Rate Select macro DMB$V_RTS = 460,4,1,0 %; ! Request to Send macro DMB$V_TX_INT_DELAY = 460,9,1,0 %; ! Transmit Interrupt Control macro DMB$V_RX_ENA = 460,10,1,0 %; ! Receiver Enable macro DMB$V_BREAK = 460,11,1,0 %; ! Break control macro DMB$V_MAINT = 460,12,2,0 %; literal DMB$S_MAINT = 2; ! Maintenance Mode macro DMB$V_REPORT_MODEM = 460,14,1,0 %; ! Report Modem changes macro DMB$V_DISCARD_FLOW = 460,15,1,0 %; ! Discard flow contr. characters macro DMB$V_CHAR_LENGTH = 460,16,2,0 %; literal DMB$S_CHAR_LENGTH = 2; ! character length macro DMB$V_PARITY_ENAB = 460,18,1,0 %; ! Parity enable macro DMB$V_EVEN_PARITY = 460,19,1,0 %; ! Even parity macro DMB$V_STOP_CODE = 460,20,1,0 %; ! Stop code macro DMB$V_USE_CTS = 460,21,1,0 %; ! CTS controls output macro DMB$V_IAUTO_FLOW = 460,22,1,0 %; ! Auto f.c. of incoming data macro DMB$V_OAUTO_FLOW = 460,23,1,0 %; ! Auto f.c. of outgoing data macro DMB$V_RX_SPEED = 460,24,4,0 %; literal DMB$S_RX_SPEED = 4; ! Received data speed macro DMB$V_TX_SPEED = 460,28,4,0 %; literal DMB$S_TX_SPEED = 4; ! Transmitted data rate macro DMB$L_LNCTRL = 464,0,32,0 %; ! Line Control macro DMB$V_TX_DMA_START = 464,0,1,0 %; ! Start a DMA transfer macro DMB$V_TX_DMA_PTE = 464,1,1,0 %; ! PTE address macro DMB$V_TX_DMA_PHYS = 464,2,1,0 %; ! Physical address macro DMB$V_TX_OUT_ABORT = 464,8,1,0 %; ! Transmitter output abort macro DMB$B_TX_ERROR = 466,0,8,1 %; ! Transmitter error bits macro DMB$L_LSTAT = 468,0,32,0 %; ! Line status register macro DMB$V_ML2 = 468,10,1,0 %; ! Spare modem control lead macro DMB$V_CTS = 468,12,1,0 %; ! Clear to send macro DMB$V_DCD = 468,13,1,0 %; ! Data carrier detected macro DMB$V_RI = 468,14,1,0 %; ! Ring indicator macro DMB$V_DSR = 468,15,1,0 %; ! Data set ready macro DMB$V_SNDOFF = 468,23,1,0 %; ! Send XOFF macro DMB$V_TX_ENA = 468,31,1,0 %; ! Transmitter enable macro DMB$L_FLOWC = 472,0,32,0 %; ! Flow control characters macro DMB$B_SENT_XOFF = 472,0,8,1 %; ! Transmitted XOFF macro DMB$B_SENT_XON = 473,0,8,1 %; ! Transmitted XON macro DMB$B_RECEIVED_XOFF = 474,0,8,1 %; ! Received XOFF macro DMB$B_RECEIVED_XON = 475,0,8,1 %; ! Received XON macro DMB$L_TBUF = 516,0,32,0 %; ! Transmit completion fifo macro DMB$B_TX_LINE = 516,0,8,1 %; ! Transmit line number macro DMB$V_TX_PREEMPT = 516,8,1,0 %; ! Preempt completed macro DMB$V_TX_FIFO_DONE = 516,9,1,0 %; ! fifo empty macro DMB$B_TX_DMA_ERROR = 518,0,8,1 %; ! Transmit error code macro DMB$V_TX_ACT = 516,31,1,0 %; ! Transmitter action macro DMB$L_SBUF = 520,0,32,0 %; ! Sync line completion fifo macro DMB$B_SYNC_LINE = 520,0,8,1 %; ! Sync line number macro DMB$V_SYNC_MODEM = 520,8,1,0 %; ! Modem change macro DMB$V_SYNC_TX_ACT = 520,9,1,0 %; ! Sync Transmit complete macro DMB$V_SYNC_SECOND_BUFFER = 520,10,1,0 %; ! buffer number macro DMB$V_SBUF_SPARE = 520,11,5,0 %; literal DMB$S_SBUF_SPARE = 5; ! macro DMB$R_SBUF_X = 522,0,8,0 %; literal DMB$S_SBUF_X = 1; ! macro DMB$B_SYNC_MODEM_STATUS = 522,0,8,1 %; ! Sync line new modem status macro DMB$B_SYNC_ERROR = 522,0,8,1 %; ! Sync line error code macro DMB$L_RBUF = 524,0,32,0 %; ! Async Receiver Buffer macro DMB$B_RXCHAR = 524,0,8,1 %; ! Received character macro DMB$V_PARITY_ERR = 524,12,1,0 %; ! Parity error macro DMB$V_FRAME_ERR = 524,13,1,0 %; ! Framing error macro DMB$V_OVERRUN_ERR = 524,14,1,0 %; ! Overrun error macro DMB$V_NON_CHAR = 524,15,1,0 %; ! non character data macro DMB$B_RX_LINE = 526,0,8,1 %; ! Receive line number macro DMB$V_DATA_VALID = 524,31,1,0 %; ! Data valid !*** MODULE $DIAGDEF *** ! * ! ! Constants defining literals used in $DIAGNOSE system service ! literal DIAG$C_SETAFF = 1; ! request to set affinity -- Set/Release ! explicit process affinity to any CPU. literal DIAG$C_ACTVCPUS = 2; ! request to read SMP$GL_ACTIVE_CPUS literal DIAG$C_DISABLAFF = 0; ! disable explicit affinity to a CPU literal DIAG$C_ENABLAFF = 1; ! enable explicit affinity to a CPU !*** MODULE $DPTDEF *** ! + ! DPT - DRIVER PROLOGUE TABLE ! ! EACH DEVICE DRIVER HAS A DRIVER PROLOGUE TABLE. ! - literal DPT$K_STEP_1 = 1; ! A STEP 1 DRIVER literal DPT$K_STEP_2 = 2; ! A STEP 2 DRIVER literal DPT$K_STEP1_V1 = 1; ! STEP 1 VERSION 1 literal DPT$K_STEP1_V2 = 2; ! STEP 1 VERSION 2 literal DPT$K_STEP2_V1 = 1; ! STEP 2 VERSION 1 literal DPT$K_STEP2_V2 = 2; ! STEP 2 VERSION 2 (CSR mapping) literal DPT$K_STEP2_V3 = 3; ! STEP 2 VERSION 3 (early Theta, pre-IFT) literal DPT$K_STEP2_V4 = 4; ! STEP 2 VERSION 4 (Theta IFT: 64-bits, Fast I/O) literal DPT$K_STEP2_V5 = 5; ! STEP 2 VERSION 5 (Theta EFT: DDT, UCB changes) literal DPT$K_IOGEN_REQ_STEP2VER = 5; literal DPT$M_SUBCNTRL = %X'1'; literal DPT$M_SVP = %X'2'; literal DPT$M_NOUNLOAD = %X'4'; literal DPT$M_SCS = %X'8'; literal DPT$M_DUSHADOW = %X'10'; literal DPT$M_SCSCI = %X'20'; literal DPT$M_BVPSUBS = %X'40'; literal DPT$M_UCODE = %X'80'; literal DPT$M_SMPMOD = %X'100'; literal DPT$M_DECW_DECODE = %X'200'; literal DPT$M_TPALLOC = %X'400'; literal DPT$M_SNAPSHOT = %X'800'; literal DPT$M_NO_IDB_DISPATCH = %X'1000'; literal DPT$M_SCSI_PORT = %X'2000'; literal DPT$M_ATM = %X'4000'; literal DPT$M_CSMACD = %X'8000'; literal DPT$M_FDDI = %X'10000'; literal DPT$M_TR = %X'20000'; literal DPT$M_SHARED_INT = %X'40000'; literal DPT$M_DEVPATH_SUP = %X'80000'; literal DPT$M_MULTIPATH_SUP = %X'100000'; literal DPT$M_ATM_FORE = %X'400000'; literal DPT$M_USB_SUP = %X'800000'; literal DPT$M_HOTSWAP_SUP = %X'1000000'; literal DPT$M_MAX_UNIT = %X'2000000'; literal DPT$K_BASE_LEN = 160; ! LENGTH OF PRE IMAGE NAME DRIVER PROLOGUE literal DPT$C_BASE_LEN = 160; ! LENGTH OF PRE IMAGE NAME DRIVER PROLOGUE literal DPT$S_DPT = 168; macro DPT$L_FLINK = 0,0,32,1 %; ! FORWARD LINK TO NEXT DPT macro DPT$PS_FLINK = 0,0,32,1 %; ! FORWARD LINK TO NEXT DPT macro DPT$L_BLINK = 4,0,32,1 %; ! BACKWARD LINK TO PREVIOUS DPT macro DPT$PS_BLINK = 4,0,32,1 %; ! BACKWARD LINK TO PREVIOUS DPT macro DPT$W_SIZE = 8,0,16,0 %; ! SIZE OF DRIVER macro DPT$IW_SIZE = 8,0,16,0 %; ! SIZE OF DRIVER macro DPT$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE macro DPT$IB_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE macro DPT$IW_STEP = 12,0,16,0 %; ! DRIVER STEP NUMBER macro DPT$IW_STEPVER = 14,0,16,0 %; ! VERSION WITHIN A DRIVER STEP macro DPT$W_DEFUNITS = 16,0,16,0 %; ! DEFAULT NUMBER OF UNITS macro DPT$IW_DEFUNITS = 16,0,16,0 %; ! DEFAULT NUMBER OF UNITS macro DPT$W_MAXUNITS = 18,0,16,0 %; ! MAXIMUM UNITS THAT CAN BE CONNECTED macro DPT$IW_MAXUNITS = 18,0,16,0 %; ! MAXIMUM UNITS THAT CAN BE CONNECTED macro DPT$W_UCBSIZE = 20,0,16,0 %; ! SIZE OF UCB macro DPT$IW_UCBSIZE = 20,0,16,0 %; ! SIZE OF UCB macro DPT$IW_IOHANDLES = 22,0,16,0 %; ! Number of IOHANDLES that driver needs macro DPT$IW_IDB_CRAMS = 24,0,16,0 %; ! Number of CRAMS to allocate for the IDB macro DPT$IW_UCB_CRAMS = 26,0,16,0 %; ! Number of CRAMS to allocate for the UCB macro DPT$L_FLAGS = 28,0,32,0 %; ! DRIVER LOADER FLAGS macro DPT$IL_FLAGS = 28,0,32,0 %; ! DRIVER LOADER FLAGS macro DPT$B_FLAGS = 28,0,8,0 %; ! an old-world synonym for the above macro DPT$V_SUBCNTRL = 28,0,1,0 %; ! DEVICE IS A SUB-CONTROLLER macro DPT$V_SVP = 28,1,1,0 %; ! DEVICE REQUIRES A SYSTEM PAGE macro DPT$V_NOUNLOAD = 28,2,1,0 %; ! DRIVER IS NOT TO BE UNLOADED macro DPT$V_SCS = 28,3,1,0 %; ! Load common SCS code with driver macro DPT$V_DUSHADOW = 28,4,1,0 %; ! SHADOWING DISK CLASS DRIVER macro DPT$V_SCSCI = 28,5,1,0 %; ! Load common SCS/CI subroutines with driver macro DPT$V_BVPSUBS = 28,6,1,0 %; ! Load common BVP subroutines with driver macro DPT$V_UCODE = 28,7,1,0 %; ! Driver has associated microcode image macro DPT$V_SMPMOD = 28,8,1,0 %; ! Driver has been modified for SMP macro DPT$V_DECW_DECODE = 28,9,1,0 %; ! DECwindows decoder (class) driver macro DPT$V_TPALLOC = 28,10,1,0 %; ! Use tape allocation class parameter macro DPT$V_SNAPSHOT = 28,11,1,0 %; ! Driver has been certified for system snapshot macro DPT$V_NO_IDB_DISPATCH = 28,12,1,0 %; ! Don't use IDB$L_UCBLST for UCB vectors macro DPT$V_SCSI_PORT = 28,13,1,0 %; ! Driver is an SCSI port driver macro DPT$V_ATM = 28,14,1,0 %; ! Driver is an LAN ATM port driver macro DPT$V_CSMACD = 28,15,1,0 %; ! Driver is an LAN CSMAD port driver macro DPT$V_FDDI = 28,16,1,0 %; ! Driver is an LAN FDDI port driver macro DPT$V_TR = 28,17,1,0 %; ! Driver is an LAN TR port driver macro DPT$V_SHARED_INT = 28,18,1,0 %; ! Driver supports Shared Interrupts macro DPT$V_DEVPATH_SUP = 28,19,1,0 %; ! Driver supports device path information macro DPT$V_MULTIPATH_SUP = 28,20,1,0 %; ! Driver supports multipath macro DPT$V_ATM_FORE = 28,22,1,0 %; ! Driver is a LAN FORE ATM port driver macro DPT$V_USB_SUP = 28,23,1,0 %; ! Driver supports USB macro DPT$V_HOTSWAP_SUP = 28,24,1,0 %; ! Driver supports PCI I/O hotswap macro DPT$V_MAX_UNIT = 28,25,1,0 %; ! Driver has specified a MAX_UNIT value macro DPT$IL_ADPTYPE = 32,0,32,0 %; ! ADAPTER TYPE CODE macro DPT$IL_REFC = 36,0,32,0 %; ! COUNT OF DDB'S THAT REFERENCE DRIVER macro DPT$PS_INIT_PD = 40,0,32,1 %; ! STRUCTURE INIT ROUTINE DESC ADDRESS macro DPT$PS_REINIT_PD = 44,0,32,1 %; ! STRUCTURE RE-INIT ROUTINE DESC ADDRESS macro DPT$PS_DELIVER_2 = 48,0,32,1 %; ! STEP 2 UNIT DELIVERY ROUTINE DESC ADDRESS macro DPT$PS_UNLOAD = 52,0,32,1 %; ! UNLOAD ROUTINE DESC ADDRESS macro DPT$PS_DDT = 56,0,32,1 %; ! POINTER TO DRIVER'S DDT ADDRESS macro DPT$PS_DDB_LIST = 60,0,32,1 %; ! POINTER TO FIRST DDB IN LIST FOR THIS DRIVER macro DPT$IS_BTORDER = 64,0,32,1 %; ! BOOTTIME INIT CALL ORDERING NUMBER macro DPT$L_VECTOR = 68,0,32,1 %; ! POINTER TO VECTOR TABLE (IN TTDRIVER) macro DPT$PS_VECTOR = 68,0,32,1 %; ! POINTER TO VECTOR TABLE (IN TTDRIVER) macro DPT$T_NAME = 72,0,0,0 %; literal DPT$S_NAME = 16; ! AUTHOR'S NAME FOR THE DRIVER macro DPT$B_NAME_LEN = 72,0,8,0 %; ! CHARACTER COUNT macro DPT$IB_NAME_LEN = 72,0,8,0 %; ! CHARACTER COUNT macro DPT$T_NAME_STR = 73,0,0,0 %; literal DPT$S_NAME_STR = 15; ! CHARACTER STRING macro DPT$L_ECOLEVEL = 88,0,32,0 %; ! ECO LEVEL FROM IMAGE HEADER macro DPT$IL_ECOLEVEL = 88,0,32,0 %; ! ECO LEVEL FROM IMAGE HEADER macro DPT$L_UCODE = 92,0,32,0 %; ! ASSOCIATED MICROCODE IMAGE macro DPT$Q_LINKTIME = 96,0,0,0 %; literal DPT$S_LINKTIME = 8; ! LINK DATE AND TIME FROM IMAGE HEADER macro DPT$IQ_IMAGE_NAME = 104,0,0,0 %; literal DPT$S_IMAGE_NAME = 8; ! STRING DESCRIPTOR FOR DRIVER'S IMAGE NAME macro DPT$IW_INAME_LEN = 104,0,16,0 %; ! -- IMAGE NAME LENGTH macro DPT$IB_INAME_TYPE = 106,0,8,0 %; ! -- IMAGE NAME DESC TYPE macro DPT$IB_INAME_CLASS = 107,0,8,0 %; ! -- IMAGE NAME DESC TYPE macro DPT$PS_INAME_PTR = 108,0,32,1 %; ! -- IMAGE NAME DESC POINTER macro DPT$IL_LOADER_HANDLE = 112,0,0,0 %; literal DPT$S_LOADER_HANDLE = 16; ! EXECLET LOADER HANDLE macro DPT$L_DECW_SNAME = 128,0,32,1 %; ! POINTER TO COUNTED ASCII STRING macro DPT$PS_DECW_SNAME = 128,0,32,1 %; ! POINTER TO COUNTED ASCII STRING macro DPT$PS_CUSTOMER = 132,0,32,1 %; ! Reserved_to_customer macro DPT$IL_DEVPATH_SIZE = 136,0,32,0 %; ! SIZE OF THE PATH INFORMATION BLOCK WITHIN UCB macro DPT$IL_DEVPATH_UCB_OFS = 140,0,32,0 %; ! OFFSET OF THE PATH INFORMATION BLOCK WITHIN UCB macro DPT$IL_DSPLYPATH_SIZE = 144,0,32,0 %; ! MAX. SIZE OF THE DISPLAY PATH STRING WITHIN UCB macro DPT$IL_DSPLYPATH_UCB_OFS = 148,0,32,0 %; ! OFFSET OF THE DISPLAY PATH STRING WITHIN UCB macro DPT$L_MAX_UNIT = 152,0,32,0 %; ! Number of maximum device units macro DPT$T_IMAGE_NAME = 160,0,8,0 %; literal DPT$S_DPTDEF = 168; ! OLD DPT SIZE NAME FOR COMPATIBILITY !*** MODULE $DSRVDEF *** ! + ! DSRV ( ) Definitions ! ! This module defines the main data structure of the MSCP ! server. This structure contains the values specified in ! the start up qualifiers when the server was loaded, the ! UQB vector table, and statistics that are kept for server ! performance measurements. ! ! <<== !NOTICE! ==>> ! ! DO NOT change offsets of the top part of the data structure. ! If new fields have to be added please add them to the ! end of the structure. ! - ! Max number of served units literal DSRV$M_LOG_ENABLD = %X'1'; literal DSRV$M_LOG_PRESENT = %X'2'; literal DSRV$M_PKT_LOGGED = %X'4'; literal DSRV$M_PKT_LOST = %X'8'; literal DSRV$M_LBSTEP1 = %X'10'; literal DSRV$M_LBSTEP2 = %X'20'; literal DSRV$M_LBEVENT = %X'40'; literal DSRV$M_HULB_DEL = %X'80'; literal DSRV$M_MON_ACTIVE = %X'100'; literal DSRV$M_LB_REQ = %X'200'; literal DSRV$M_CONFIG_WAIT = %X'400'; literal DSRV$C_LENGTH = 41452; literal DSRV$K_LENGTH = 41452; literal DSRV$K_AR_ADD = 2; ! Action routine code literal DSRV$K_MAX_UNITS = 9999; literal DSRV$S_DSRVDEF = 41452; ! Old size name synonym literal DSRV$S_DSRV = 41452; macro DSRV$L_FLINK = 0,0,32,1 %; ! Field maintained for macro DSRV$L_BLINK = 4,0,32,1 %; ! compatability macro DSRV$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro DSRV$B_TYPE = 10,0,8,0 %; ! MSCP type structure macro DSRV$B_SUBTYPE = 11,0,8,0 %; ! with a DSRV subtype (1) macro DSRV$W_STATE = 12,0,16,0 %; ! Current state of the server macro DSRV$V_LOG_ENABLD = 12,0,1,0 %; ! Logging is enabled macro DSRV$V_LOG_PRESENT = 12,1,1,0 %; ! Logging code is present macro DSRV$V_PKT_LOGGED = 12,2,1,0 %; ! A packet has been logged macro DSRV$V_PKT_LOST = 12,3,1,0 %; ! One or more packets over- ! written since last read macro DSRV$V_LBSTEP1 = 12,4,1,0 %; ! Load balancing step1 active macro DSRV$V_LBSTEP2 = 12,5,1,0 %; ! Load balancing step2 active macro DSRV$V_LBEVENT = 12,6,1,0 %; ! An event of interest to LB has ! occured while STEP1 was active macro DSRV$V_HULB_DEL = 12,7,1,0 %; ! One or more HULBs to be deleted macro DSRV$V_MON_ACTIVE = 12,8,1,0 %; ! The load monitor thread is active macro DSRV$V_LB_REQ = 12,9,1,0 %; ! A load balance request has been sent macro DSRV$V_CONFIG_WAIT = 12,10,1,0 %; ! Waiting for STACONFIG to complete macro DSRV$W_BUFWAIT = 14,0,16,0 %; ! I/Os that had to wait macro DSRV$L_LOG_BUF_START = 16,0,32,1 %; ! Address of start of buffer macro DSRV$L_LOG_BUF_END = 20,0,32,1 %; ! Address of end of buffer macro DSRV$L_NEXT_READ = 24,0,32,1 %; ! Adrs of next packet to read macro DSRV$L_NEXT_WRITE = 28,0,32,1 %; ! Adrs of next packet to write macro DSRV$W_INC_LOLIM = 32,0,16,0 %; ! Low unit number to log macro DSRV$W_INC_HILIM = 34,0,16,0 %; ! High unit number to log macro DSRV$W_EXC_LOLIM = 36,0,16,0 %; ! Low unit number not to log macro DSRV$W_EXC_HILIM = 38,0,16,0 %; ! High unit number not to log macro DSRV$L_SRVBUF = 40,0,32,1 %; ! Address of preallocated pool macro DSRV$L_FREE_LIST = 44,0,32,1 %; ! Pointer to head of free pool macro DSRV$L_AVAIL = 48,0,32,0 %; ! Sum of bytes available in buffer macro DSRV$L_BUFFER_MIN = 52,0,32,0 %; ! Min xfer size based on buffer macro DSRV$L_SPLITXFER = 56,0,32,0 %; ! Fragmented I/O count macro DSRV$W_VERSION = 60,0,16,0 %; ! Server software version macro DSRV$W_CFLAGS = 62,0,16,0 %; ! Controller flags macro DSRV$W_CTIMO = 64,0,16,0 %; ! Controller timeout macro DSRV$Q_CTRL_ID = 68,0,0,0 %; literal DSRV$S_CTRL_ID = 8; ! Unique MSCP device identifier macro DSRV$L_MEMW_TOT = 76,0,32,0 %; ! Number of I/Os that had to wait macro DSRV$W_MEMW_CNT = 80,0,16,0 %; ! Requests in memory wait queue macro DSRV$W_MEMW_MAX = 82,0,16,0 %; ! Most requests ever in MEMWAIT macro DSRV$L_MEMW_FL = 84,0,32,1 %; ! Queue listhead for requests macro DSRV$L_MEMW_BL = 88,0,32,1 %; ! in memory wait state macro DSRV$W_NUM_HOST = 92,0,16,0 %; ! Count of hosts being served macro DSRV$W_NUM_UNIT = 94,0,16,0 %; ! Count of disks being served macro DSRV$L_HQB_FL = 96,0,32,1 %; ! Host queue block list head macro DSRV$L_HQB_BL = 100,0,32,1 %; ! macro DSRV$L_UQB_FL = 104,0,32,1 %; ! Unit queue block list head macro DSRV$L_UQB_BL = 108,0,32,1 %; ! ! ! Server Load Balancing fields ! ! The following fields containing working information and statistics ! for the server load balancing function. Load balancing status bits ! are defined in DSRV$STATE above. Time fields are in EXE$GL_ABSTIM ! format. ! macro DSRV$W_LOAD_AVAIL = 112,0,16,0 %; ! Current load available macro DSRV$W_LOAD_CAPACITY = 114,0,16,0 %; ! Server load capacity macro DSRV$W_LBLOAD = 116,0,16,0 %; ! Target load for LB request macro DSRV$W_LBRESP = 118,0,16,0 %; ! Load available from other server macro DSRV$W_LM_LOAD1 = 120,0,16,0 %; ! previous interval load 1 macro DSRV$W_LM_LOAD2 = 122,0,16,0 %; ! previous interval load 2 macro DSRV$W_LM_LOAD3 = 124,0,16,0 %; ! previous interval load 3 macro DSRV$W_LM_LOAD4 = 126,0,16,0 %; ! previous interval load 4 macro DSRV$W_LBINIT_CNT = 128,0,16,0 %; ! Count of LB requests we have sent macro DSRV$W_LBFAIL_CNT = 130,0,16,0 %; ! Count of LB requests that failed macro DSRV$W_LBREQ_CNT = 132,0,16,0 %; ! Count of LB requests from other servers macro DSRV$W_LBRESP_CNT = 134,0,16,0 %; ! Count of LB requests we to which we responded macro DSRV$L_LBREQ_TIME = 136,0,32,0 %; ! Time last LB request was sent macro DSRV$L_LBMON_TIME = 140,0,32,0 %; ! Time of last LB monitor pass macro DSRV$L_LM_FKB = 144,0,32,1 %; ! Address of load monitor thread FKB macro DSRV$L_LB_FKB = 148,0,32,1 %; ! Address of load balance thread FKB macro DSRV$W_LM_INTERVAL = 152,0,16,0 %; ! Load monitoring interval macro DSRV$B_LB_COUNT1 = 154,0,8,0 %; ! Counter for load balancing thread macro DSRV$B_LB_COUNT2 = 155,0,8,0 %; ! Counter for load balancing thread macro DSRV$L_HULB_FL = 156,0,32,1 %; ! HULB queue listhead macro DSRV$L_HULB_BL = 160,0,32,1 %; ! macro DSRV$B_HOSTS = 164,0,0,0 %; literal DSRV$S_HOSTS = 32; ! Bit array of hosts served macro DSRV$L_UNITS = 208,0,0,1 %; literal DSRV$S_UNITS = 39996; ! Table of UQB addresses ! ! Statistics gathering fields ! ! Two tables are maintained below. The first table is made up of the ! frequency count for each of the opcodes received since the server ! was loaded. The opcode is used as an index into the table to its own ! frequency count (the zeroeth element contains a total count). The ! second table is made up of the frequency counters for all the ! different sized block transfers. For this table, the size of the ! transfer is the index into the table. ! macro DSRV$L_OPCOUNT = 40208,0,32,0 %; ! Total operations count macro DSRV$L_ABORT_CNT = 40212,0,32,0 %; ! - 1 - macro DSRV$L_GET_CMD_CNT = 40216,0,32,0 %; ! - 2 - macro DSRV$L_GET_UNT_CNT = 40220,0,32,0 %; ! - 3 - macro DSRV$L_SET_CON_CNT = 40224,0,32,0 %; ! - 4 - macro DSRV$L_ACC_NVM_CNT = 40228,0,32,0 %; ! - 5 - macro DSRV$L_DISPLAY_CNT = 40232,0,32,0 %; ! - 6 - macro DSRV$L_GET_UNN_CNT = 40236,0,32,0 %; ! - 7 - macro DSRV$L_AVAIL_CNT = 40240,0,32,0 %; ! - 8 - macro DSRV$L_ONLIN_CNT = 40244,0,32,0 %; ! - 9 - macro DSRV$L_SET_UNT_CNT = 40248,0,32,0 %; ! - 10 - macro DSRV$L_DET_ACC_CNT = 40252,0,32,0 %; ! - 11 - macro DSRV$L_MOVE_CNT = 40256,0,32,0 %; ! - 12 - macro DSRV$L_DCD_CNT = 40260,0,32,0 %; ! - 13 - macro DSRV$L_ACCES_CNT = 40272,0,32,0 %; ! - 16 - macro DSRV$L_CMP_CON_CNT = 40276,0,32,0 %; ! - 17 - macro DSRV$L_ERASE_CNT = 40280,0,32,0 %; ! - 18 - macro DSRV$L_FLUSH_CNT = 40284,0,32,0 %; ! - 19 - macro DSRV$L_REPLC_CNT = 40288,0,32,0 %; ! - 20 - macro DSRV$L_ERASEG_CNT = 40296,0,32,0 %; ! - 22 - macro DSRV$L_FORMAT_CNT = 40304,0,32,0 %; ! - 24 - macro DSRV$L_WRI_HIS_CNT = 40308,0,32,0 %; ! - 25 - macro DSRV$L_CMP_HST_CNT = 40336,0,32,0 %; ! - 32 - macro DSRV$L_READ_CNT = 40340,0,32,0 %; ! - 33 - macro DSRV$L_WRITE_CNT = 40344,0,32,0 %; ! - 34 - macro DSRV$L_REA_CED_CNT = 40348,0,32,0 %; ! - 35 - macro DSRV$L_WRI_TM_CNT = 40352,0,32,0 %; ! - 36 - macro DSRV$L_REPOS_CNT = 40356,0,32,0 %; ! - 37 - macro DSRV$L_TERCO_CNT = 40400,0,32,0 %; ! - 48 - macro DSRV$L_VCFAIL_CNT = 40408,0,32,0 %; ! Count of VC failures macro DSRV$L_BLKCOUNT = 40412,0,0,0 %; literal DSRV$S_BLKCOUNT = 1028; ! Counters for block xfer reqs macro DSRV$L_PCB = 41440,0,32,0 %; ! Pointer to simulated PCB macro DSRV$L_HRB_TMO_CNTR = 41444,0,32,0 %; ! Counter for timed out HRB's macro DSRV$L_SEED = 41448,0,32,0 %; ! Seed for next host number. !*** MODULE $DTNDEF *** literal DTN$K_BASE_LENGTH = 24; ! length of fixed portion of DTN literal DTN$K_LENGTH = 52; ! standard length of DTN literal DTN$K_NAMELEN_MAX = 27; ! max length of name string literal DTN$S_DTN = 52; macro DTN$PS_FLINK = 0,0,32,1 %; ! flink to next DTN macro DTN$PS_BLINK = 4,0,32,1 %; ! blink to previous DTN macro DTN$W_SIZE = 8,0,16,0 %; ! size of DTN in bytes macro DTN$B_TYPE = 10,0,8,0 %; ! structure type of DTN macro DTN$B_SUBTYPE = 11,0,8,0 %; ! structure subtype macro DTN$L_FLAGS = 12,0,32,0 %; ! various flag bits macro DTN$B_DEVTYPE = 16,0,8,0 %; ! copy of UCB$B_DEVTYPE macro DTN$B_DEVCLASS = 17,0,8,0 %; ! copy of UCB$B_DEVCLASS macro DTN$PS_UCBLIST = 20,0,32,1 %; ! pointer to list of UCBs macro DTN$T_DTNAME = 24,0,0,0 %; literal DTN$S_DTNAME = 28; ! name stored in ASCIC format macro DTN$IB_DTNAME_LEN = 24,0,8,0 %; ! length of the device name macro DTN$T_DTNAME_STR = 25,0,0,0 %; literal DTN$S_DTNAME_STR = 27; ! actual string !*** MODULE $DTSSDEF *** ! + ! ! Bit definitions for EXE$GL_DTSSFLAGS - flags for Distributed Time Service ! ! - literal DTSS$M_ACTIVE = %X'1'; literal DTSS$M_CALCULATE_CLOCK = %X'2'; literal DTSS$S_DTSSDEF = 1; literal DTSS$S_DTSS = 1; macro DTSS$V_ACTIVE = 0,0,1,0 %; ! Time service active macro DTSS$V_CALCULATE_CLOCK = 0,1,1,0 %; ! Service wants to synch clock !*** MODULE $DXRDEF *** ! ! This defines a DXR -- a Dump eXclusion Region. ! DXRs are elements in a singly-linked list. ! Each DXR describes a region of virtual address space ! that is to be excluded from selective crash dumps. ! literal DXR$K_LENGTH = 40; literal DXR$C_LENGTH = 40; literal DXR$S_DXR = 40; macro DXR$PQ_LINK = 0,0,0,1 %; literal DXR$S_LINK = 8; ! Link to next element -- 0 means end of list ! DXR only has flinks, so make room for a quadword ! pointer. macro DXR$W_SIZE = 8,0,16,0 %; ! Size of DXR in bytes macro DXR$B_TYPE = 10,0,8,0 %; ! Structure type for DXR (to be filled in with DYN$C_MISC) macro DXR$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype for DXR (to be filled in with DYN$C_DXR) macro DXR$L_CHECKSUM = 12,0,32,0 %; ! Checksum macro DXR$PQ_START_VA = 16,0,0,1 %; literal DXR$S_START_VA = 8; ! Start System VA of Excluded Region macro DXR$Q_BYTECOUNT = 24,0,0,0 %; literal DXR$S_BYTECOUNT = 8; ! Size of Excluded Region in Bytes macro DXR$Q_CALLERS_PC = 32,0,0,1 %; literal DXR$S_CALLERS_PC = 8; ! Caller's PC !*** MODULE $DYNDEF *** ! + ! DATA STRUCTURE TYPE DEFINITIONS ! ! EACH DATA STRUCTURE THAT IS ALLOCATED FROM THE DYNAMIC MEMORY ! POOL SHOULD HAVE A VALID TYPE IN ITS 11TH BYTE. ! - ! BASE AND OFFSET OF 1 literal DYN$C_ADP = 1; ! UNIBUS ADAPTER CONTROL BLOCK literal DYN$C_ACB = 2; ! AST CONTROL BLOCK literal DYN$C_AQB = 3; ! ACP QUEUE BLOCK literal DYN$C_CEB = 4; ! COMMON EVENT BLOCK literal DYN$C_CRB = 5; ! CHANNEL REQUEST BLOCK literal DYN$C_DDB = 6; ! DEVICE DESCRIPTOR BLOCK literal DYN$C_FCB = 7; ! FILE CONTROL BLOCK literal DYN$C_FRK = 8; ! FORK BLOCK literal DYN$C_IDB = 9; ! INTERRUPT DISPATCH BLOCK literal DYN$C_IRP = 10; ! I/O REQUEST PACKET literal DYN$C_LOG = 11; ! LOGICAL NAME BLOCK literal DYN$C_PCB = 12; ! PROCESS CONTROL BLOCK literal DYN$C_PQB = 13; ! PROCESS QUOTA BLOCK literal DYN$C_RVT = 14; ! RELATIVE VOLUME TABLE literal DYN$C_TQE = 15; ! TIMER QUEUE ENTRY literal DYN$C_UCB = 16; ! UNIT CONTROL BLOCK literal DYN$C_VCB = 17; ! VOLUME CONTROL BLOCK literal DYN$C_WCB = 18; ! WINDOW CONTROL BLOCK literal DYN$C_BUFIO = 19; ! BUFFERED I/O BLOCK literal DYN$C_TYPAHD = 20; ! TERMINAL TYPEAHEAD BUFFER literal DYN$C_GSD = 21; ! GLOBAL SECTION DESCRIPTOR BLOCK literal DYN$C_MVL = 22; ! MAGNETIC TAPE VOLUME LIST literal DYN$C_NET = 23; ! NETWORK MESSAGE BLOCK literal DYN$C_KFE = 24; ! KNOWN FILE ENTRY literal DYN$C_MTL = 25; ! MOUNTED VOLUME LIST ENTRY literal DYN$C_BRDCST = 26; ! BROADCAST MESSAGE BLOCK literal DYN$C_CXB = 27; ! COMPLEX CHAINED BUFFER literal DYN$C_NDB = 28; ! NETWORK NODE DESCRIPTOR BLOCK literal DYN$C_SSB = 29; ! LOGICAL LINK SUBCHANNEL STATUS BLOCK literal DYN$C_DPT = 30; ! DRIVER PROLOGUE TABLE literal DYN$C_JPB = 31; ! JOB PARAMETER BLOCK literal DYN$C_PBH = 32; ! PERFORMANCE BUFFER HEADER literal DYN$C_PDB = 33; ! PERFORMANCE DATA BLOCK literal DYN$C_PIB = 34; ! PERFORMANCE INFORMATION BLOCK literal DYN$C_PFL = 35; ! PAGE FILE CONTROL BLOCK literal DYN$C_PFLMAP = 36; ! Page file mapping window literal DYN$C_PTR = 37; ! POINTER CONTROL BLOCK literal DYN$C_KFRH = 38; ! KNOWN FILE IMAGE HEADER literal DYN$C_DCCB = 39; ! Data Cache Control Block literal DYN$C_EXTGSD = 40; ! EXTENDED GLOBAL SECTION DESCRIPTOR literal DYN$C_SHMGSD = 41; ! SHARED MEMORY GLOBAL SECTION DESCRIPTOR literal DYN$C_SHB = 42; ! SHARED MEMORY CONTROL BLOCK literal DYN$C_MBX = 43; ! MAILBOX CONTROL BLOCK literal DYN$C_IRPE = 44; ! I/O REQUEST PACKET EXTENSION literal DYN$C_SLAVCEB = 45; ! SLAVE COMMON EVENT BLOCK literal DYN$C_SHMCEB = 46; ! SHARED MEMORY MASTER COMMON EVENT BLOCK literal DYN$C_JIB = 47; ! JOB INFORMATION BLOCK literal DYN$C_TWP = 48; ! Terminal driver write packet literal DYN$C_RBM = 49; ! Realtime SPT bit map literal DYN$C_VCA = 50; ! Disk volume cache block literal DYN$C_CDB = 51; ! X25 LES CHANNEL DATA BLOCK literal DYN$C_LPD = 52; ! X25 LES PROCESS DESCRIPTOR literal DYN$C_LKB = 53; ! LOCK BLOCK literal DYN$C_RSB = 54; ! RESOURCE BLOCK literal DYN$C_LCKRQ = 55; ! Lock Manager Request Block literal DYN$C_RSHT = 56; ! RESOURCE HASH TABLE literal DYN$C_CDRP = 57; ! CLASS DRIVER REQUEST PACKET literal DYN$C_ERP = 58; ! ERRORLOG PACKET literal DYN$C_CIDG = 59; ! DATAGRAM BUFFER FOR CI PORT literal DYN$C_CIMSG = 60; ! MESSAGE BUFFER FOR CI PORT literal DYN$C_XWB = 61; ! DECNET LOGICAL LINK CONTEXT BLOCK ! (REPLACES "NDB" BLOCK) literal DYN$C_WQE = 62; ! DECNET WORK QUEUE BLOCK ! (REPLACES "NET" BLOCK) literal DYN$C_ACL = 63; ! ACCESS CONTROL LIST QUEUE ENTRY literal DYN$C_LNM = 64; ! LOGICAL NAME BLOCK literal DYN$C_FLK = 65; ! Fork Lock Request Block literal DYN$C_RIGHTSLIST = 66; ! RIGHTS LIST literal DYN$C_KFD = 67; ! Known File Device Directory block literal DYN$C_KFPB = 68; ! Known File list Pointer Block literal DYN$C_CIA = 69; ! Compound Intrusion Analysis block literal DYN$C_PMB = 70; ! Page Fault Monitor Control Block literal DYN$C_PFB = 71; ! Page Fault Monitor Buffer literal DYN$C_CHIP = 72; ! Internal CHKPRO block literal DYN$C_ORB = 73; ! Objects Rights Block literal DYN$C_FKB = 74; ! Fork block literal DYN$C_MVWB = 75; ! Mount Verification work buffer literal DYN$C_UNC = 76; ! Universal Context Block literal DYN$C_DCB = 77; ! DCB, for DECnet chained I/O literal DYN$C_VCRP = 78; ! VAX Communication Request Packet literal DYN$C_SPL = 79; ! Spinlock control block literal DYN$C_ARB = 80; ! Access Rights Block literal DYN$C_LCKCTX = 81; ! Lock context block literal DYN$C_BOD = 82; ! Buffer object descriptor literal DYN$C_FTRD = 83; ! FTDRIVER read request packet literal DYN$C_DDTM_EVENT = 84; ! DDTM Event Notification block literal DYN$C_DFLB = 85; ! Dump File Locator Block literal DYN$C_PTC = 86; ! Posix Terminal Control literal DYN$C_OCB = 87; ! Object Class Block (Security) literal DYN$C_CPCB = 88; ! Common Process Control Block literal DYN$C_HWPCB = 89; ! Hardware Process Control Block literal DYN$C_GCB = 90; ! Glyph Control Block literal DYN$C_RDPB = 91; ! Resource Domain Pointer Block literal DYN$C_RDDB = 92; ! Resource Domain Data Block literal DYN$C_SCDRP = 93; ! SCSI Class Driver Request Packet literal DYN$C_TQE_ACB = 94; ! TQE-ACB block literal DYN$C_NSAB = 95; ! Security Audit Block literal DYN$C_DEA = 96; ! DEaccess Audit pending block ! This first region is full, do not add more types. ! ! ! THE FOLLOWING CODES ARE SUBTYPABLE, THAT IS EACH CODE REFERS TO A GENERIC ! FUNCTION AND WITHIN THAT FUNCTION THERE MAY BE MANY DIFFERENT SUB-TYPES ! OF BLOCKS. THIS SCHEME WAS ADOPTED TO PRESERVE TYPES. THE SUB-TYPE IS ! IN THE 12TH BYTE. ! literal DYN$C_SUBTYPE = 96; ! START OF SUBTYPABLES literal DYN$C_SCS = 96; ! SYSTEM COMMUNICATION SERVICES literal DYN$C_SCS_CDL = 1; ! CONNECT DISPATCH LIST literal DYN$C_SCS_CDT = 2; ! CONNECT DISPATCH TABLE literal DYN$C_SCS_DIR = 3; ! DIRECTORY BLOCK literal DYN$C_SCS_PB = 4; ! PATH BLOCK literal DYN$C_SCS_PDT = 5; ! PORT DESCRIPTOR TABLE literal DYN$C_SCS_RDT = 6; ! REQUEST DESCRIPTOR TABLE literal DYN$C_SCS_SB = 7; ! SYSTEM BLOCK literal DYN$C_SCS_SPPB = 8; ! SCA POLLER PROCESS BLOCK literal DYN$C_SCS_SPNB = 9; ! SCA POLLER NAME BLOCK literal DYN$C_SCS_SBNB = 10; ! SCS LOAD SHARE NAME BLOCK literal DYN$C_SCS_PLVEC = 11; ! SCS PORT LOAD VECTOR literal DYN$C_SCS_PDTLIST = 12; ! (TYC 14-Feb-89) SCS PDT LIST literal DYN$C_SCS_BD = 13; ! Buffer Descriptor Entry literal DYN$C_SCS_CMNBDLT = 14; ! Buffer Descriptor Leaf Table literal DYN$C_SCS_RBUN = 15; ! Resource bundle literal DYN$C_SCS_CRRR = 16; ! Carrier for Nport adapters literal DYN$C_SCS_TYP1 = 17; ! TYP1 mapping structure literal DYN$C_SCS_SDA = 18; ! CLUSTER_CRASH structure literal DYN$C_SCS_IPCI_CFG = 19; ! IPCI early load structure literal DYN$C_SCS_IPCI_IPINTERFACE = 20; ! IPCI SCS enabled IP interface literal DYN$C_SCS_IPCI_UNICAST = 21; ! IPCI unicast address literal DYN$C_CI = 97; ! CI PORT SPECIFIC literal DYN$C_CI_BDT = 1; ! BUFFER DESCRIPTOR TABLE literal DYN$C_CI_FQDT = 2; ! FREE QUE DESCRIPTOR TABLE literal DYN$C_CI_CRRR = 3; ! Carrier for Nport adapters literal DYN$C_LOADCODE = 98; ! LOADABLE CODE literal DYN$C_NON_PAGED = 1; ! NON PAGED CODE literal DYN$C_PAGED = 2; ! PAGED CODE literal DYN$C_LC_MP = 3; ! MULTIPROCESSOR CODE literal DYN$C_LC_SCS = 4; ! SCS CODE literal DYN$C_LC_CLS = 5; ! CLUSTER CODE literal DYN$C_LC_CHREML = 6; ! CHAR/DECIMAL INS EMUL literal DYN$C_LC_FPEMUL = 7; ! FLOAT PNT EMULATOR literal DYN$C_LC_MSCP = 8; ! MSCP SERVER literal DYN$C_LC_SYSL = 9; ! SYSLOA literal DYN$C_LDRIMG = 10; ! Execlet data structure literal DYN$C_INIT = 99; ! STRUCTURES SET UP BY INIT OR INIT'N ROUTINES literal DYN$C_PCBVEC = 1; ! PROCESS CONTROL BLOCK VECTOR literal DYN$C_PHVEC = 2; ! PROCESS HEADER VECTOR literal DYN$C_SWPMAP = 3; ! SWAPPER MAP literal DYN$C_MPWMAP = 4; ! MODIFIED PAGE WRITER MAP literal DYN$C_PRCMAP = 5; ! PROCESS BITMAP literal DYN$C_BOOTCB = 6; ! BOOT CONTROL BLOCK literal DYN$C_CONF = 7; ! CONFIGURATION ARRAYS literal DYN$C_CST = 8; ! CLUSTER SYSTEM TABLE literal DYN$C_COLOR_ARRAYS = 9; ! PFN COLOR ARRAYS literal DYN$C_PHREFC = 10; ! PROCESS HEADER REF COUNT ARRAY literal DYN$C_POOL_STATS = 11; ! POOL STATS ARRAYS (ALLOCS, FAILS, DEALLOCS, ETC.) literal DYN$C_CLASSDRV = 100; ! CLASS DRIVER MAJOR STRUCTURE TYPE CODE literal DYN$C_CD_CDDB = 1; ! CLASS DRIVER DATA BLOCK literal DYN$C_CD_BBRPG = 2; ! BAD BLOCK REPLACEMENT PAGE literal DYN$C_CD_SHDW_WRK = 3; ! SHADOW SET WORK BUFFER literal DYN$C_CD_LDB = 4; ! LOAD DRIVER DATA BLOCK literal DYN$C_CLU = 101; ! CLUSTER MAJOR STRUCTURE TYPE CODE literal DYN$C_CLU_CSB = 1; ! CONNECTION STATUS BLOCK literal DYN$C_CLU_CLUVEC = 2; ! CLUSTER SYSTEM VECTOR literal DYN$C_CLU_CLUB = 3; ! CLUSTER BLOCK literal DYN$C_CLU_BTX = 4; ! CLUSTER BLOCK TRANSFER EXTENSION literal DYN$C_CLU_CLUDCB = 5; ! CLUSTER DISK QUORUM CONTROL BLOCK literal DYN$C_CLU_CLUOPT = 6; ! CLUSTER OPTIMAL RECONFIGURATION CONTEXT BLOCK literal DYN$C_CLU_LCKDIR = 7; ! LOCK MANAGER DISTRIBUTED DIRECTORY VECTOR literal DYN$C_CLU_ICB = 8; ! INCARNATION FILE CONTROL BLOCK literal DYN$C_CLU_CLURCB = 9; ! REMASTER CONTROL BLOCK literal DYN$C_CLU_NTE = 10; ! NOTIFICATION TABLE ENTRY literal DYN$C_CLU_CSDT = 11; ! SERVER DISPATCH TABLE literal DYN$C_CLU_CWLNM = 12; ! CLUSTERWIDE LOGICAL NAME MESSAGE BUFFER literal DYN$C_CLU_CLUEVT = 13; ! CLUSTER EVENT BLOCK literal DYN$C_PGD = 102; ! PAGED DYNAMIC MEMORY literal DYN$C_PGD_F11BC = 1; ! F11BXQP BUFFER CACHE. literal DYN$C_KFERES = 2; ! KFE resident sections literal DYN$C_IMRE = 3; ! track imgreg_pages VA allcation [INSTAL] literal DYN$C_KFERES64 = 4; ! KFERES64 resident sections literal DYN$C_P0_POOL = 5; ! P0 Pool allocation header literal DYN$C_IMCB = 6; ! Image control block literal DYN$C_FREE_IMCB = 7; ! Image control block on lookaside list literal DYN$C_IMGACT_POOL = 8; ! process pool page used by image activator literal DYN$C_IMGDMP = 9; ! process pool reserved for image dump work literal DYN$C_DECW = 103; ! DECWINDOWS literal DYN$C_DECW_GPB = 1; ! GPX Packet Buffer literal DYN$C_DECW_GPD = 2; ! GPX Physical Data literal DYN$C_DECW_INB = 3; ! Input Buffer descriptor literal DYN$C_DECW_DVI = 4; ! Device Info block literal DYN$C_VWS = 104; ! UIS Structure ! UIS subtypes literal DYN$C_UIS_ARD = 1; ! Allocation region literal DYN$C_UIS_VDB = 2; ! Virtual display control block literal DYN$C_UIS_WDB = 3; ! Display window control block literal DYN$C_UIS_SEG = 4; ! Segment control block literal DYN$C_UIS_ATB = 5; ! Attribute block literal DYN$C_UIS_OTP = 6; ! Output primitive literal DYN$C_UIS_APD = 7; ! Application-specific data literal DYN$C_UIS_SEGEND = 8; ! Segment "end" marker (really part of SEG) literal DYN$C_UIS_URG = 9; ! User region AST request block literal DYN$C_UIS_VDT = 10; ! Display transformation literal DYN$C_UIS_MENU = 11; ! Window options menu or menu items literal DYN$C_UIS_KBB = 12; ! Virtual keyboard control block literal DYN$C_UIS_RES = 13; ! Resize/rescale information block literal DYN$C_UIS_VCMD = 14; ! Virtual color map descriptor literal DYN$C_UIS_VCMS = 15; ! Virtual color map section literal DYN$C_UIS_CMSD = 16; ! Color map segment descriptor literal DYN$C_UIS_CMSB = 17; ! Color map segment allocation control block literal DYN$C_UIS_CMS = 18; ! Color map segment literal DYN$C_UIS_FNT = 19; ! Font block literal DYN$C_UIS_FNTH = 20; ! Font header -- extra memory at head of a font literal DYN$C_UIS_VPD = 21; ! Viewport descriptor block literal DYN$C_UIS_VRD = 22; ! Viewport region descriptor literal DYN$C_UIS_BMD = 23; ! literal DYN$C_UIS_OFF_MEM = 24; ! Offscreen memory descriptor literal DYN$C_UIS_USB = 25; ! UIS system-wide storage literal DYN$C_UIS_QBE = 26; ! QVSS block extension literal DYN$C_UIS_MEM = 27; ! Video scanline allocation block literal DYN$C_UIS_VSL_MEM = 28; ! VAX scanline storage literal DYN$C_UIS_SL_TEMP = 29; ! Scanline temporary storage literal DYN$C_UIS_ERROR = 30; ! Error handler "spare" memory ! VPS subtypes literal DYN$C_VPS_FM = 86; ! literal DYN$C_VPS_CTX = 87; ! literal DYN$C_VPS_PPD = 88; ! Per-process data structure literal DYN$C_VPS_SDB = 89; ! Scan descriptor block literal DYN$C_VPS_BTD = 90; ! Bitmap descriptor ! VWS subtypes literal DYN$C_VWS_REGIS = 170; ! ReGIS buffer literal DYN$C_VWS_VT200 = 171; ! VT200 emulator buffer literal DYN$C_VWS_CHR_ARR = 172; ! Character array literal DYN$C_VWS_CLIP = 173; ! Clipping region desc literal DYN$C_VWS_CUR = 174; ! literal DYN$C_VWS_FNTD = 175; ! Font descriptor literal DYN$C_VWS_SCR = 176; ! literal DYN$C_VWS_UPD = 177; ! literal DYN$C_VWS_UPDE = 178; ! UPD extension literal DYN$C_VWS_VIEW = 179; ! Driver Viewport control block literal DYN$C_VWS_DOP = 180; ! Device output primative packet literal DYN$C_VWS_GLYB = 181; ! Glyph storage block literal DYN$C_DSRV = 105; ! Disk Server structure type ! Server subtypes literal DYN$C_DSRV_DSRV = 1; ! Disk server structure literal DYN$C_DSRV_HQB = 2; ! Host Queue Block literal DYN$C_DSRV_HRB = 3; ! Host Request Block literal DYN$C_DSRV_IOBUF = 4; ! Server local I/O Buffer literal DYN$C_DSRV_UQB = 5; ! Unit Queue Block literal DYN$C_DSRV_HULB = 6; ! Host-Unit Load Block literal DYN$C_MP = 106; ! MP related structure ! MP subtypes literal DYN$C_MP_MPB = 1; ! Logical Console Block literal DYN$C_MP_CPU = 2; ! Per-CPU database literal DYN$C_NSA = 107; ! Non-discretionary Security Audit literal DYN$C_NSA_EVENT = 1; ! Event enable vectors literal DYN$C_NSA_FAILURE = 2; ! Failure mode vectors literal DYN$C_NSA_ALARM = 3; ! Security alarm packet list literal DYN$C_CWPS = 108; ! Cluster-Wide Process Services ! CWPS subtypes for process control service codes literal DYN$C_CWPS_CANWAK = 1; ! $CANWAK service literal DYN$C_CWPS_DELPRC = 2; ! $DELPRC service literal DYN$C_CWPS_FORCEX = 3; ! $FORCEX service literal DYN$C_CWPS_RESUME = 4; ! $RESUME service literal DYN$C_CWPS_SCHDWK = 5; ! $SCHDWK service literal DYN$C_CWPS_SETPRI = 6; ! $SETPRI service literal DYN$C_CWPS_SUSPND = 7; ! $SUSPND service literal DYN$C_CWPS_WAKE = 8; ! $WAKE service ! CWPS subtypes for other services literal DYN$C_CWPS_GETJPI = 20; ! $GETJPI service literal DYN$C_CWPS_CREPRC = 21; ! $CREPRC service literal DYN$C_CWPS_TERMIN = 22; ! process termination message ! CWPS subtypes for security service codes literal DYN$C_CWPS_GRANTID = 28; ! $GRANTID service literal DYN$C_CWPS_REVOKID = 29; ! $WAKE service ! CWPS subtypes for miscellaneous structures literal DYN$C_CWPSACB = 64; ! CWPSACB$ structure literal DYN$C_CWPSNODI = 65; ! CWPSNODI$ structure literal DYN$C_CWPSSQH = 66; ! CWPSSQH$ structure literal DYN$C_PSCANBUF = 67; ! PSCAN JPI buffer literal DYN$C_PSCANCTX = 68; ! PSCAN context literal DYN$C_PSCANITM = 69; ! PSCAN JPI itemlist literal DYN$C_VP = 109; ! Vector processing support ! Vector processing subtypes literal DYN$C_VP_VCTX = 1; ! Vector context block literal DYN$C_VP_VEXC = 2; ! Vector saved exception block literal DYN$C_SHAD = 110; ! Volume Shadowing structure type literal DYN$C_VCC = 111; ! VAXcluster cache ! VCC subtypes literal DYN$C_VCC_CL = 1; ! Cache Line literal DYN$C_VCC_CPT = 2; ! Cache Page Table literal DYN$C_VCC_HT = 3; ! Hash Table ! for VCC_CFCB SUBTYPE and RMOD overlap so force correct RMOD bits literal DYN$C_VCC_CFCB = 32; ! Cache FCB ! XFC Data structures are subtypes of VCC. literal DYN$C_VCC_CFB = 64; ! Cache File Block literal DYN$C_VCC_CVB = 65; ! Cache Volume Block literal DYN$C_VCC_PECB = 66; ! Primary Extent Cache Block literal DYN$C_VCC_SECB = 67; ! Secondary Extent Cache Block literal DYN$C_VCC_EFB = 68; ! Extent File Block literal DYN$C_VCC_FHT = 69; ! File Hash Table literal DYN$C_VCC_EHT = 70; ! Extent Hash Table literal DYN$C_VCC_ANCHOR = 71; ! Anchor data structure literal DYN$C_VCC_SFBAR = 72; ! Single File Barrier literal DYN$C_VCC_IFBAR = 73; ! Interfile barrier literal DYN$C_VCC_DIRBAR = 74; ! Directed side of interfile barrier literal DYN$C_VCC_DEPBAR = 75; ! Dependent side of interfile barrier literal DYN$C_VCC_FLUSHBAR = 76; ! Flush Barrier literal DYN$C_VCC_WTB = 77; ! Writer-thread control block literal DYN$C_VCC_CTX = 78; ! I/O Context literal DYN$C_VCC_MTX = 79; ! Mutex structure literal DYN$C_VCC_CVS = 80; ! Cache Volume Statistics literal DYN$C_VCC_HWMBAR = 81; ! Deferred highwater mark update barrier literal DYN$C_VCC_VHT = 82; ! Volume Hash Table literal DYN$C_VCC_LCKCTX = 83; ! Lock Context literal DYN$C_VCC_CFS = 84; ! Cache File Statistics literal DYN$C_OVRS = 112; ! Open VMS NT Registry Server ! OVRS subtypes ! Subtypes for the Registry Client literal DYN$C_OVRS_RCB = 1; ! Registry Control Block literal DYN$C_OVRS_RRB = 2; ! Registry Request Block literal DYN$C_OVRS_OKH = 3; ! Open Key Header literal DYN$C_OVRS_OKE = 4; ! Open Key Entry literal DYN$C_OVRS_PKE = 5; ! Predefined Key Entry literal DYN$C_OVRS_CRED = 6; ! Credentials Block literal DYN$C_OVRS_RTB = 7; ! Rights Block ! Subtypes for the Registry Server literal DYN$C_OVRS_SSB = 8; ! Server Status Block literal DYN$C_OVRS_LSB = 9; ! Lock Status Block literal DYN$C_OVRS_TCB = 10; ! Thread Control Block literal DYN$C_OVRS_TRB = 11; ! Thread Request Block literal DYN$C_OVRS_WIT = 12; ! Work Item ! Subtypes for Communication literal DYN$C_OVRS_CDS = 13; ! Connection Descriptor literal DYN$C_OVRS_ICCB = 14; ! Inter-Cluster Communications Block literal DYN$C_OVRS_NP = 15; ! Network Packet literal DYN$C_OVRS_NPH = 16; ! Network Packet Header literal DYN$C_OVRS_RPH = 17; ! Request Packet Header literal DYN$C_OVRS_SIB = 18; ! Security Information Block ! Subtypes for the Registry Database literal DYN$C_OVRS_RRT = 19; ! Registry Root Table literal DYN$C_OVRS_FLE = 20; ! File List Entry literal DYN$C_OVRS_FTH = 21; ! File Table Header literal DYN$C_OVRS_FTB = 22; ! File Table Block literal DYN$C_OVRS_FTE = 23; ! File Table Entry literal DYN$C_OVRS_LTB = 24; ! Logical File Table literal DYN$C_OVRS_LTE = 25; ! Logical file Table Entry literal DYN$C_OVRS_DFH = 26; ! Database File Header literal DYN$C_OVRS_SGH = 27; ! Segment Header literal DYN$C_OVRS_STH = 28; ! Segment Table Header literal DYN$C_OVRS_STE = 29; ! Segment Table Entry literal DYN$C_OVRS_FSO = 30; ! File/Segment/Offset literal DYN$C_OVRS_CTE = 31; ! Category Table Entry literal DYN$C_OVRS_KEY = 32; ! Key literal DYN$C_OVRS_VAL = 33; ! Value literal DYN$C_OVRS_STR = 34; ! String literal DYN$C_OVRS_DAT = 35; ! Data literal DYN$C_OVRS_SEC = 36; ! Security Descriptor literal DYN$C_OVRS_KCN = 37; ! Key Change Notification literal DYN$C_OVRS_SLS = 38; ! Shared Library Structure literal DYN$C_OVRS_TKE = 39; ! To be clean Key Entry literal DYN$C_OVRS_SPA = 40; ! Search path structure literal DYN$C_OVRS_OUT = 41; ! Output Parameters ! Subtypes for the Logging literal DYN$C_OVRS_WPK = 42; ! Write Packet literal DYN$C_OVRS_WUN = 43; ! Write Unit literal DYN$C_OVRS_RBQ = 44; ! Rollback structure literal DYN$C_OVRS_CTESAV = 45; ! CTE Structure Save literal DYN$C_OVRS_LOCKSAV = 46; ! Lock Structure Save literal DYN$C_OVRS_DLH = 47; ! Database Log File Header literal DYN$C_OVRS_MLH = 48; ! Master Log File Header literal DYN$C_OVRS_RLH = 49; ! Reply Log File Header literal DYN$C_OVRS_LRH = 50; ! Log Record Header literal DYN$C_OVRS_LGR = 51; ! Log Record literal DYN$C_OVRS_RPR = 52; ! Reply Log Record literal DYN$C_OVRS_CMR = 53; ! Commit Record literal DYN$C_OVRS_MCR = 54; ! Master Commit Record ! Add new types here so as not to create database incompatibilities literal DYN$C_OVRS_CNX = 55; ! Connection Block literal DYN$C_OVRS_CSB = 56; ! Connection Status Block literal DYN$C_OVRS_WCB = 57; ! Work Context Block literal DYN$C_DDTM = 113; ! Digital Distributed Transaction Mgr ! DDTM subtypes literal DYN$C_DDTM_XCB = 1; ! Transaction Control Block literal DYN$C_DDTM_XSCB = 2; ! Transaction Segment Control Block literal DYN$C_DDTM_XPCB = 3; ! Transaction Participant Control Block literal DYN$C_DDTM_CDCB = 4; ! Commit Domain Control Block literal DYN$C_DDTM_CMDB = 5; ! Communication Manager Definition Block literal DYN$C_DDTM_CMCB = 6; ! Communication Manager Control Block literal DYN$C_DDTM_RMCB = 7; ! Resource Manager Control Block literal DYN$C_DDTM_NDCB = 8; ! V1 DDTM Communication Manager Block literal DYN$C_DDTM_DGCB = 9; ! TPCom Dialogue Control Block literal DYN$C_DDTM_LGCB = 10; ! Log Control Block literal DYN$C_DDTM_NNCB = 11; ! Node Name Cache Block literal DYN$C_DDTM_DDTMTXT = 12; ! DECdtm text block ! Subtypes for the Log Manager (LM) literal DYN$C_LM_LBDB = 13; ! Log Buffer Descriptor Block literal DYN$C_LM_LMLINK = 14; ! Log Server Link Message literal DYN$C_LM_LMOPCB = 15; ! Parameter Block for LM$OPEN call literal DYN$C_LM_LMRCB = 16; ! Read Control Block literal DYN$C_LM_LMTRCB = 17; ! Transition Control Block literal DYN$C_LM_LMREAD = 18; ! Read Return literal DYN$C_LM_LCB = 19; ! Log Control Block literal DYN$C_LM_LMTREE = 20; ! TID Tree Entry literal DYN$C_LM_LMHT = 21; ! Hash Table literal DYN$C_LM_LMTE = 22; ! Hash Table Entry ! Additional subtypes for DECdtm (DDTM) literal DYN$C_DDTM_XTCB = 23; ! Thread Control Block literal DYN$C_DDTM_XTCBLW = 24; ! "Lightweight" Thread Control Block literal DYN$C_DDTM_STACK = 25; ! Thread Stack Control Block literal DYN$C_DDTM_XBID = 26; ! Transaction Brand Id Control Block literal DYN$C_DDTM_XSBID = 27; literal DYN$C_DDTM_XDCB = 28; ! Default Transaction Control Block literal DYN$C_DDTM_XCBX = 29; ! Transaction Control Block Extension literal DYN$C_DDTM_XPCBX = 30; ! Transaction Participant Control Block Extension ! Additional subtypes for the Log Manager (LM) extended structures literal DYN$C_LM_LMOPCBX = 31; ! Open Control Block literal DYN$C_LM_LMRCBX = 32; ! Read Control Block literal DYN$C_LM_LMTRCBX = 33; ! Transition Control Block literal DYN$C_SMI = 114; ! System Management Integrator ! SMI subtypes literal DYN$C_SMI_CSCB = 1; ! Cluster/System Communications Block literal DYN$C_SMI_CTX = 2; ! Internal context block literal DYN$C_SMI_SUPB = 3; ! Server User Profile Block literal DYN$C_SMI_RTTB = 4; ! RouTine Table Block literal DYN$C_TSRV = 115; ! Tape Server structure type ! Server subtypes literal DYN$C_TSRV_TSRV = 1; ! Tape server structure literal DYN$C_TSRV_HQB = 2; ! Host Queue Block literal DYN$C_TSRV_HRB = 3; ! Host Request Block literal DYN$C_TSRV_UQB = 4; ! Unit Queue Block literal DYN$C_TSRV_TBUFF = 5; ! Tape local Buffer literal DYN$C_LAVC = 116; ! Local Area VAX Cluster structures. ! LAVC subtypes literal DYN$C_LAVC_ROOT = 1; ! ROOT block data structure. literal DYN$C_LAVC_PORT = 2; ! PORT block data structure. literal DYN$C_LAVC_VC = 3; ! Virtual Circuit data structure. literal DYN$C_LAVC_CH = 4; ! Channel Block data structure. literal DYN$C_LAVC_BUS = 5; ! BUS block data structure. literal DYN$C_LAVC_COMP = 6; ! Network component description data structure. literal DYN$C_LAVC_CLST = 7; ! Network component list data structure. literal DYN$C_LAVC_ID_TABLE = 8; ! Network component ID table structure. literal DYN$C_LAVC_NIT = 9; ! NIsca Timer structure literal DYN$C_LAVC_TRACE_CONTEXT = 10; ! PEDRIVER trace context structure literal DYN$C_LAVC_TRACE = 11; ! PEDRIVER trace buffer literal DYN$C_DECNET = 117; ! DECNET structures ! ! DECNET subtype definitions. Each component gets a multiple of 8 ! entries; except the first (which gets 7 because we wanted 0 to be ! the unknown entry). ! ! Note that the DECNET subtypes break the SUBTYPE NAME RESTRICTIONS ! and the format code in SDA special cases for ! this occurance. ! literal DYN$C_NET_UNK = 0; ! Unknown subtype of zero ! ! Base image vectors (2-8) ! literal DYN$C_NET_NBI_NDVEC = 2; ! Network Data Vectors literal DYN$C_NET_NBI_NBIRV = 3; ! Global Routine Vectors literal DYN$C_NET_NBI_GRVH = 4; ! Global routine init vector header literal DYN$C_NET_NBI_GRVE = 5; ! Global routine init vector entry ! ! Common trace support data structures (9-16) ! literal DYN$C_NET_CTF_TB = 9; ! Trace block literal DYN$C_NET_CTF_TR = 10; ! Trace record literal DYN$C_NET_CTF_MH = 11; ! Module header literal DYN$C_NET_CTF_REQ = 12; ! Trace requests ! ! EMAA support structures (17-24) ! literal DYN$C_NET_EMAA_MRCP = 17; ! Management request control packet literal DYN$C_NET_EMAA_IVK = 18; ! Invoke block literal DYN$C_NET_EMAA_EMAA = 19; ! Misc dynamic EMAA structures literal DYN$C_NET_EMAA_EIB = 20; ! Entity information block literal DYN$C_NET_EMAA_EISDB = 21; ! Entity semantic block literal DYN$C_NET_EMAA_EAB = 22; ! Entity access block literal DYN$C_NET_EMAA_IVKIDTBL = 23; ! Invoke Block ID Table literal DYN$C_NET_EMAA_ERTTBL = 24; ! Entity Registration Table ! ! Loader support data structures (25-32) ! literal DYN$C_NET_LDR_LIE = 25; ! Loaded Image Entry block ! ! Task support data structures (33-40) ! literal DYN$C_NET_TSK_NTK = 33; ! Network task scheduler database literal DYN$C_NET_TSK_TCX = 34; ! Task context block literal DYN$C_NET_TSK_TPB = 35; ! Task parameter block literal DYN$C_NET_TSK_SQX = 36; ! Scheduler queue block literal DYN$C_NET_TSK_SCX = 37; ! Scheduler control block ! ! Timer support data structures (41-48) ! literal DYN$C_NET_TIM_NTM = 41; ! Network timer database literal DYN$C_NET_TIM_NTEB = 42; ! Network timer element block ! ! VCI support data structures (49-56) ! literal DYN$C_NET_VCI_VRT = 49; ! VCI Registration Table literal DYN$C_NET_VCI_VID = 50; ! VCI Identification Table literal DYN$C_NET_VCI_VCIB = 51; ! VCI Communication Info Block ! ! EVL support data structures (57-64) ! literal DYN$C_NET_EVL_EVT = 57; ! EVL Event Report ! ! Itemlist support structure (65-72) ! literal DYN$C_NET_ITEM = 65; ! Network Itemlist ! ! Session control support structure (73-88 = 16 entries) ! literal DYN$C_NET_SCL_SESSID = 73; ! Session Connection Id Table literal DYN$C_NET_SCL_SPB = 74; ! Session Port Block literal DYN$C_NET_SCL_SCLSVP = 75; ! Session VCI Port data block literal DYN$C_NET_SCL_SCLATTR = 76; ! Session VCI port attribute block literal DYN$C_NET_SCL_BUFFER = 77; ! Generic session buffer literal DYN$C_NET_SCL_CRPROC = 78; ! Create process block literal DYN$C_NET_SCL_CRPROCNCB = 79; ! Create process NCB block literal DYN$C_NET_SCL_USER_CRPROC = 80; ! Create process usermode block ! ! NSP support data structures (89-96) ! literal DYN$C_NET_NSP_ATB = 89; ! NSP Association Table literal DYN$C_NET_NSP_TCTB = 90; ! NSP Transport Connection Table literal DYN$C_NET_NSP_NSP = 91; ! NSP service blk subtype literal DYN$C_NET_NSP_LSP = 92; ! LSP service blk subtype literal DYN$C_NET_NSP_RSP = 93; ! RSP service blk subtype literal DYN$C_NET_NSP_PORT = 94; ! PORT service blk subtype ! ! LAN support data structures (97-104) ! literal DYN$C_NET_LAN_LAN = 97; ! LAN LAN Entity Block literal DYN$C_NET_LAN_LSB = 98; ! LAN Station Block literal DYN$C_NET_LAN_LPB = 99; ! LAN Port Block ! ! Thread support data structures (105-112) ! literal DYN$C_NET_THREAD = 105; ! Thread Block ! ! Network Routing Layer data structures (113-144 = 32 entries) ! literal DYN$C_NET_NRL_NRD = 113; ! Global database literal DYN$C_NET_NRL_HTB = 114; ! Hash table header literal DYN$C_NET_NRL_CKT = 115; ! Circuit database entry literal DYN$C_NET_NRL_ADJ = 116; ! Adjacency database entry literal DYN$C_NET_NRL_PSB = 117; ! Protocol service block literal DYN$C_NET_NRL_TP = 118; ! Transport database entry literal DYN$C_NET_NRL_CKTEVT = 119; ! Circuit event block ! ! Node agent data structures (145-152) ! literal DYN$C_NET_NODE_IDS = 145; ! ID table header literal DYN$C_NET_NODE_DATABASE = 146; ! Permanent database ! ! OSITP support data structures (153-168 = 16 Entries) ! literal DYN$C_NET_OSITP_ATB = 153; ! OSI Association Table literal DYN$C_NET_OSITP_TCTB = 154; ! OSI Transport Connection Table literal DYN$C_NET_OSITP_NCCB = 155; ! OSI Transport ! Network Connection Block literal DYN$C_NET_OSITP_ILB = 156; ! OSI Transport ! Itemlist Block literal DYN$C_NET_OSITP_TLB = 157; ! OSI Transport ! Timer List Block literal DYN$C_NET_OSITP_TMP = 158; ! OSI Transport ! Template Name Block literal DYN$C_NET_OSITP_OSI = 159; ! OSI Transport ! OSI Block literal DYN$C_NET_OSITP_PORT = 160; ! OSI Transport ! port Block literal DYN$C_NET_OSITP_LSP = 161; ! OSI Transport ! LSP Block literal DYN$C_NET_OSITP_RSP = 162; ! OSI Transport ! RSP Block ! ! QIO data structures (169-176) ! literal DYN$C_NET_QIO_DAB = 169; ! Declared Application Block literal DYN$C_NET_QIO_QLB = 170; ! QIO Link Block ! ! MOP data structures (177-192) ! literal DYN$C_NET_MOP_MRCPIN = 177; ! MRCP Inbound from management literal DYN$C_NET_MOP_MRCPOUT = 178; ! MRCP Outbound to management literal DYN$C_NET_MOP_MANAGEMENTABORT = 179; ! Management Abort Block literal DYN$C_NET_MOP_CPRPIN = 180; ! Create Port Request Packet Inbound literal DYN$C_NET_MOP_CPRPOUT = 181; ! Create Port Request Packet Outbound literal DYN$C_NET_MOP_DPRPIN = 182; ! Delete Port Request Packet Inbound literal DYN$C_NET_MOP_DPRPOUT = 183; ! Delete Port Request Packet Outbound literal DYN$C_NET_MOP_VCRPIN = 184; ! VCRP Inbound from Datalink literal DYN$C_NET_MOP_VCRPOUT = 185; ! VCRP Outbound to Datalink literal DYN$C_NET_MOP_ENPIN = 186; ! Event Notification Packet Inbound literal DYN$C_NET_MOP_ENPOUT = 187; ! Event Notification Packet Outbound literal DYN$C_NET_MOP_PDUOUT = 188; ! PDU Outbound to Datalink literal DYN$C_NET_MOP_SUBPDU = 189; ! Sub PDU literal DYN$C_NET_MOP_CPB = 190; ! Console Carrier Connect Parameter Block literal DYN$C_NET_MOP_WORK = 191; ! Thread Work BLock literal DYN$C_NET_MOP_TRC = 192; ! Tracepoint substructure literal DYN$C_NET_MOP_TIMER = 193; ! Timer block ! ! End of DECNET subtype definitions ! literal DYN$C_PSX = 118; ! Generic type code for Posix structures literal DYN$C_PSX_XCTX = 1; ! System Service Context Area literal DYN$C_PSX_XPCB = 2; ! Extended PCB literal DYN$C_PSX_XSIG = 3; ! Signal Block literal DYN$C_PSX_PXSB = 4; ! Session Block literal DYN$C_PSX_PXPG = 5; ! Process Group Block literal DYN$C_PSX_SHSH = 6; ! Semaphore hash table literal DYN$C_PSX_SIDT = 7; ! Semaphore Id table literal DYN$C_PSX_SOB = 8; ! semaphore Operation block literal DYN$C_PSX_SMB = 9; ! semaphore block literal DYN$C_PSX_FCCB = 10; ! fork_callbacks control block literal DYN$C_PSX_FCDB = 11; ! fork_callbacks dispatch block literal DYN$C_PSX_PSXHDR = 12; ! POSIX SID/PGID header structure literal DYN$C_PSX_PSXMEM = 13; ! POSIX SID/PGID individual member structure literal DYN$C_QMAN = 119; ! Generic type code for Queue Manager structures literal DYN$C_QMAN_QDB = 1; ! Queue Data block literal DYN$C_QMAN_QMANMSG = 2; ! Queue manager message header literal DYN$C_QMAN_GQC = 3; ! Queue manager GETQUI context block literal DYN$C_SM = 120; ! Storage Management Subtypes literal DYN$C_SM_MMECB = 1; ! MME control block literal DYN$C_SM_MCB = 2; ! Mount context block literal DYN$C_MISC = 121; ! Miscellaneous types ! Miscellaneous data structures literal DYN$C_CRAM = 1; ! Controller Register Access Mailbox literal DYN$C_CRAMH = 2; ! Page header for CRAM literal DYN$C_KPB = 3; ! Kernel Process Block literal DYN$C_CRAB = 4; ! Counted resouce allocation block literal DYN$C_CRCTX = 5; ! Counted resouce context block literal DYN$C_BUSARRAY = 6; ! Bus Array literal DYN$C_VLE = 7; ! Vector List Extension literal DYN$C_CMDTABLE = 8; ! Bus Command Table literal DYN$C_CAR = 9; ! XZA/SCSI Carrier structure literal DYN$C_QBUF = 10; ! XZA/SCSI Q_Buffer structure literal DYN$C_PADBLK = 11; ! XZA/SCSI Pad Buffer structure literal DYN$C_SGMAP = 12; ! XZA/SCSI Scatter-Gather Map struct. literal DYN$C_C710S = 13; ! Cobra NCR 53C710 SCSI Port literal DYN$C_SPDT = 14; ! SCSI Port Descriptor Table literal DYN$C_SCDT = 15; ! SCSI Connection Descriptor Table literal DYN$C_PRCEVT = 16; ! Process event block literal DYN$C_PRCSTR = 17; ! Alternate procstrt literal DYN$C_ECB = 18; ! A1742A/SCSI Enhanced Control Block struct literal DYN$C_ASB = 19; ! A1742A/SCSI Status Block structure literal DYN$C_SGL = 20; ! A1742A/SCSI Scatter/Gather List Struct literal DYN$C_ICDB = 21; ! A1742A/SCSI Init. Configuration Data Block literal DYN$C_FDT_CONTEXT = 22; ! FDT Context Structure literal DYN$C_DTN = 23; ! Dynamic Type Name structure literal DYN$C_SSI_BLOCK = 24; ! System Service Intercept Control block literal DYN$C_IOHANDLE = 25; ! IOHANDLE structure for platform independent mapping literal DYN$C_STDT = 26; ! SCSI Target Descriptor Table RCL0001 literal DYN$C_MCJ = 27; ! Magic Cookie Jar to hold IOHANDLEs literal DYN$C_ISACFG = 28; ! ISA Config Data Blocks literal DYN$C_SCSICLS = 29; ! SCSI Class driver random data blocks literal DYN$C_RDE = 30; ! Region descriptor entry literal DYN$C_DIOBM = 31; ! Direct I/O Buffer Map literal DYN$C_FANDLEVEC = 32; ! Fandle vector literal DYN$C_MC_PDT = 33; ! Memory Channel Port Descriptor Table literal DYN$C_CONFIG_TABLE = 34; ! Adapter Configuration table literal DYN$C_RMD = 35; ! Reserved Memory Descriptor literal DYN$C_TTSTR = 36; ! Site-specific terminal text strings literal DYN$C_PRVPFN = 37; ! Private PFN list head literal DYN$C_MMAP = 38; ! Memory map data structure literal DYN$C_GBL_MAP = 39; ! Global section mapping structure literal DYN$C_SUD = 40; ! Supplemental UCB Data structure literal DYN$C_CBB = 41; ! Common Bitmask Block literal DYN$C_DXR = 42; ! Dump eXclusion Record (Bugcheck) literal DYN$C_MPDEV = 43; ! Multipath data structure literal DYN$C_FP = 44; ! Fastpath data structure ! ! [X-78] Subtypes defined for FibreChannel ! literal DYN$C_ACTX = 45; ! Adapter Context literal DYN$C_CHS = 46; ! PCI Configuration Header Space CSRs literal DYN$C_FCCD = 47; ! Fibre Channel Command Descriptor [X-79] literal DYN$C_CSR = 48; ! Other CSRs literal DYN$C_CTR = 49; ! Counter Set literal DYN$C_LSDB = 50; ! Link State Data Block literal DYN$C_MBD = 51; ! Mapped Buffer Descriptor literal DYN$C_PCTX = 52; ! Protocol Context literal DYN$C_RBD = 53; ! Ring Buffer Descriptor literal DYN$C_RCTX = 54; ! Emulex Ring Context literal DYN$C_SCTX = 55; ! Shell Context literal DYN$C_UCTX = 56; ! Unit Context ! ! [X-78] End ! literal DYN$C_DDT = 57; ! Driver Dispatch Table literal DYN$C_MPDEV_PPB = 58; ! Multipath poller block literal DYN$C_RIH = 59; ! RAD Info Header literal DYN$C_DEV_WWID_DUPLE = 60; ! Fibre Channel device/WWID data literal DYN$C_AMDS_REG_SEG = 61; ! AM/DECamds registration segment literal DYN$C_SDP = 62; ! System dump priority data structure. literal DYN$C_IOCNT = 63; ! IOCNT data literal DYN$C_RAD = 64; ! Per-RAD data structure literal DYN$C_TQEIDX = 65; ! TQE index block literal DYN$C_SSENTRY = 66; ! IPF system service entry frame literal DYN$C_INTSTK = 67; ! IPF interrupt frame literal DYN$C_ADB = 68; ! IPF Ast Dispatch Block literal DYN$C_OCLA = 69; ! Marvel On-Chip Logic Analyzer data structure literal DYN$C_INDICTREQ = 70; ! Indictment data request structure literal DYN$C_INDICTDEF = 71; ! Indictment data head structure literal DYN$C_DEVCFG_CBK = 72; ! Device configure call back structure literal DYN$C_ICRD = 73; ! Invo context region descriptor literal DYN$C_STALE_SSENTRY = 74; ! Stale IPF system service entry frame literal DYN$C_STALE_INTSTK = 75; ! Stale IPF interrupt frame literal DYN$C_KPSTACK = 76; ! IPF KP Stack context literal DYN$C_HBMM_EP = 77; ! HBMM evaluate policy structure literal DYN$C_WTID = 78; ! FibreChannel WWID Throttle IO Descriptor literal DYN$C_FCPROT = 79; ! FibreChannel protocol connection block literal DYN$C_PSXROO = 80; ! Posix ROOT definition structure literal DYN$C_DBGIBR = 81; ! Debug inst break register array (hung off PCB) literal DYN$C_DBGDBR = 82; ! Debug data break register array (hung off PCB) literal DYN$C_MBOX_MSG = 83; ! Mailbox Driver message packet (writes) literal DYN$C_MBOX_BUF = 84; ! Mailbox Driver system buffer (reads) literal DYN$C_BUGLOG = 85; ! Bugcheck Log additional crash info structure literal DYN$C_RHA = 86; ! RAD Hint Array for global sections (hung off RIH) literal DYN$C_RC = 122; ! Generic type code for RAID control structures literal DYN$C_IPC = 123; ! Generic type code for IPC structures ! System Service Data Structure Subtypes literal DYN$C_IPC_AB = 1; ! Association Block literal DYN$C_IPC_CB = 2; ! Connection Block literal DYN$C_IPC_IPCBUF = 3; ! Buffer Descriptor ! SYSIPC Data Structure Subtypes literal DYN$C_IPC_NT = 4; ! Name Table literal DYN$C_IPC_TDB = 5; ! Transport Descriptor Block literal DYN$C_IPC_TPCB = 6; ! Transport Control Block literal DYN$C_IPC_LCB = 7; ! Link Control Block literal DYN$C_IPC_LIST = 8; ! List (generic table) Header literal DYN$C_IPC_PHL = 9; ! Physical Link Block ! Local Transport data structure subtypes literal DYN$C_IPC_LCCB = 10; ! Local Copy Control Block ! DECnet NSP Transport data structure subtypes literal DYN$C_IPC_IPC_CCB = 11; ! ACP Channel Control Block literal DYN$C_IPC_IPC_ACP = 12; ! Global ACP Data Cell Block ! SCA Transport data structure subtypes literal DYN$C_IPC_TLTB = 13; ! Transport Logical Link Table literal DYN$C_IPC_TLCB = 14; ! Transport Logical Link Control Block literal DYN$C_IPC_TVCB = 15; ! Transport Virtual Circuit Block literal DYN$C_IPC_TCB = 16; ! Transport Control Block literal DYN$C_IPC_TPBTX = 17; ! SCA Transport Block Transfer CDRP Extension ! Shared data structure subtypes literal DYN$C_IPC_IPST = 18; ! IPST literal DYN$C_IPC_IPLK = 19; ! IPLK literal DYN$C_IPC_IPB = 20; ! IPB literal DYN$C_IPC_IPC = 21; ! ACP Work Block literal DYN$C_IPC_POOL = 22; ! Pool header - structure follows literal DYN$C_FILE_SYSTEM = 124; ! File system structures literal DYN$C_SQE = 1; ! XQP serialization queue entry ! ! Dollar File system types ! literal DYN$C_F64 = 125; ! Generic type code for Files-64 structures literal DYN$C_F64_XQPDATA = 1; literal DYN$C_F64_FDB = 2; literal DYN$C_F64_CDESC = 3; literal DYN$C_F64_MCB = 4; literal DYN$C_F64_DIRENTRY = 5; literal DYN$C_F64_F64VPI_PATH = 6; literal DYN$C_F64_F64VPI_PATHCOMP = 7; literal DYN$C_F64_F64VPI_MCB = 8; literal DYN$C_F64_F64VPI_FDB = 9; literal DYN$C_F64_RES1 = 10; literal DYN$C_F64_RES2 = 11; literal DYN$C_F64_RES3 = 12; ! ! Types for Snapshot-capable disk ! literal DYN$C_F64_SDANCHOR = 13; literal DYN$C_F64_SDCB = 14; literal DYN$C_F64_SDMB = 15; literal DYN$C_F64_MIRP = 16; literal DYN$C_F64_SLE = 17; literal DYN$C_F64_SL = 18; literal DYN$C_F64_CRASH = 19; literal DYN$C_F64_FAMTAB = 20; literal DYN$C_F64_FAMTABSUM = 21; literal DYN$C_F64_FREEMAP = 22; literal DYN$C_F64_FREEMAPSUM = 23; literal DYN$C_F64_HASH = 24; literal DYN$C_F64_HASHSUM = 25; literal DYN$C_F64_HOWF = 26; literal DYN$C_F64_HOWFSUM = 27; literal DYN$C_F64_NAMTAB = 28; literal DYN$C_F64_NAMTABSUM = 29; literal DYN$C_F64_ROOTMAP = 30; literal DYN$C_F64_ROOTMAPSUM = 31; literal DYN$C_F64_SEGBASE = 32; literal DYN$C_F64_SEGBASESUM = 33; literal DYN$C_F64_SEGMAP = 34; literal DYN$C_F64_SEGMAPSUM = 35; literal DYN$C_F64_NAMETABLE = 36; literal DYN$C_FILES_64 = 126; ! Generic type code for all Dollar facilities literal DYN$C_FILES_64_F64DATA = 1; ! KERNEL DOLLAR THREADS literal DYN$C_FILES_64_THD_GL_DATA = 2; ! Global Data literal DYN$C_FILES_64_THD_DTCB = 3; ! Thread Control Block literal DYN$C_FILES_64_THD_SEMA = 4; ! Semaphore structure literal DYN$C_FILES_64_THD_STACKDSC = 5; ! Stack Descriptor literal DYN$C_FILES_64_THD_RES1 = 6; ! Reserved literal DYN$C_FILES_64_THD_RES2 = 7; ! Reserved ! KERNEL DOLLAR LOCK MANAGER literal DYN$C_FILES_64_LCK_HANDLE = 8; ! Lock Handle literal DYN$C_FILES_64_LCK_EVQ = 9; ! Lock Event Queue literal DYN$C_FILES_64_LCK_ACC_EVT = 10; ! Lock Request Acceptance Event literal DYN$C_FILES_64_LCK_QUED_EVT = 11; ! Lock Queued Event literal DYN$C_FILES_64_LCK_BLK_EVT = 12; ! Lock Blocking Event literal DYN$C_FILES_64_LCK_RES1 = 13; ! Reserved literal DYN$C_FILES_64_LCK_RES2 = 14; ! Reserved ! KERNEL CONTAINER MANAGER literal DYN$C_FILES_64_CM_IRPX = 15; ! IRP extension literal DYN$C_FILES_64_CM_AICB = 16; ! Asynchronous IO control block literal DYN$C_FILES_64_CM_GL_DATA = 17; ! Global Data literal DYN$C_FILES_64_CM_RES2 = 18; ! Reserved literal DYN$C_FILES_64_CM_RES3 = 19; ! Reserved literal DYN$C_SECURITY = 127; ! Security data block type ! and its subtypes ... literal DYN$C_SECURITY_CLASS = 1; ! Classification block ($CLASSDEF) literal DYN$C_SECURITY_PSB = 2; ! Persona Security Block ($PSBDEF) literal DYN$C_SECURITY_RIGHTS = 3; ! RightsBlock ($RIGHTSDEF) literal DYN$C_SECURITY_PXRB = 4; ! Persona Security Extension registration Block ($PXBDEF) literal DYN$C_SECURITY_PXBNT = 5; ! Persona Security Extension NT Block ($PXBDEF) literal DYN$C_SECURITY_DELEGATE_BLOCK = 6; ! Persona Security Extension Delegation Block ($PXBDEF) literal DYN$C_SECURITY_PXB_ARRAY = 7; ! Persona Security Extension Array ($PXBDEF) literal DYN$C_SECURITY_RESERVE_BLOCK = 8; ! Persona Security Delegation Reservation Block ($PSBDEF) literal DYN$C_SECURITY_PSB_ARRAY = 9; ! Persona Security Block Array ($PSBDEF) literal DYN$C_SECURITY_PSB_RINGBUFFER = 10; ! Persona Security Ringbuffer ($PSBDEF) literal DYN$C_SECURITY_PXB_GENERIC = 11; ! Persona Security Extension Block (not VMS or NT) ($PXBDEF) literal DYN$C_SECURITY_ACMESDB = 12; ! ACME server data block literal DYN$C_SECURITY_ACMEADB = 13; ! ACME agent data block literal DYN$C_SECURITY_ACMECH = 14; ! ACME configuration header literal DYN$C_SECURITY_ACMERM = 15; ! ACME request/response message ! ! Special dynamic memory type. On VAX, this used to be mark the start of ! the types handled specially by EXE$DALONONPAGED. Now we don't use them ! and we do need more non-special types, so this is just a type code with ! no additional significance. ! literal DYN$C_SPECIAL = 128; ! SPECIAL TYPE = 128 literal DYN$C_SHRBUFIO = 128; ! SHARED MEMORY BUFFERED I/O literal DYN$C_LNMC = 129; ! Logical-name cache block ! ! ICC data types ! literal DYN$C_ICC = 130; ! ICC structure typ cd literal DYN$C_ICCPDB = 1; ! ICC Process Data Blk literal DYN$C_ICCP1B = 2; ! P1-space data literal DYN$C_ICCPAB = 3; ! Association Data Blk literal DYN$C_ICCPCB = 4; ! Connection Data Blk literal DYN$C_ICCPSB = 5; ! Send Data Block literal DYN$C_ICCPRB = 6; ! Receive Data Block ! ! Galaxy specific data types ! literal DYN$C_GLX = 131; ! GLX structure type literal DYN$C_GMDB = 1; ! Galaxy management database literal DYN$C_SHM_CPP = 2; ! Shared memory common property partition literal DYN$C_SHM_REG = 3; ! Shared memory region structure literal DYN$C_SHM_DESC = 4; ! Shared memory descriptor literal DYN$C_SHMEM = 5; ! Shared memory management structure literal DYN$C_CPU_GCB = 6; ! Galaxy CPU Block literal DYN$C_CPU_GMD = 7; ! Galaxy Member Data Block literal DYN$C_GMP = 8; ! Galaxy Message Packet literal DYN$C_GLOCK = 9; ! Galaxy lock literal DYN$C_MEMCBK = 10; ! Galaxy member callback literal DYN$C_NODEB = 11; ! Galaxy management database node block ! ! Galaxy data type that requires compatibility with ACB64 structure ! literal DYN$C_CTD = 132; ! Type code for for CTD structure ! ! Lock Manager specific data types ! literal DYN$C_LCK = 133; ! Lock manager structure type literal DYN$C_LCKCPU = 1; ! per-CPU counter block literal DYN$C_LCK_POOLZONE = 2; ! poolzone header block literal DYN$C_LCKSTR = 3; ! lock manager struct block literal DYN$C_LCK_TRACE = 4; ! lock manager debug and trace literal DYN$C_RMCTX = 5; ! fast remastering block xfer context ! ! QIOServer specific structure types ! literal DYN$C_QSRVR = 134; ! QIOserver structure type UNUSED ! ! System event data structure type ! literal DYN$C_SYS_EVENT = 135; ! System event structure type ! ! Shared Memory Cluster Interconnect ! literal DYN$C_SMCI = 136; ! Shared Memory Cluster Interconnect literal DYN$C_SMCH = 1; ! SMCI Channel structure literal DYN$C_SMND = 2; ! SMCI Node structure literal DYN$C_SMH = 3; ! SMCI Handle literal DYN$C_NB = 4; ! SMCI Negotiation Block literal DYN$C_PBFKB = 5; ! SMCI IPint FKB literal DYN$C_SMWE = 6; ! SMCI Work Entry ! ! Spinlock Share Array Element ! literal DYN$C_SPLX = 137; ! Spinlock Extensions literal DYN$C_SPL_SHR = 1; ! Spinlock Share Array Element literal DYN$C_SPL_TRACE = 2; ! Spinlock Trace literal DYN$C_SPLDBG = 3; ! Spinlock debug structure literal DYN$C_SPLTRH = 4; ! spinlock trace header literal DYN$C_SPLPTR = 5; ! Array of spinlock addresses for SDA ! ! Write bitmap ! literal DYN$C_WBM = 138; ! Write Bitmap literal DYN$C_WBM_WBMB = 1; ! Write Bitmap Block - basic tracking struct for WBM literal DYN$C_WBM_BITMAP = 2; ! Actual bitmap header and bits structure literal DYN$C_WBM_DATA = 3; ! Global data for tracking WBM information literal DYN$C_WBM_WBMH_ARRAY = 4; ! Bitmap handle array literal DYN$C_WBM_WBMCD_ARRAY = 5; ! Bitmap connection descriptor array literal DYN$C_WBM_CTX = 6; ! To store the context during Asynchronous "setbit" operation ! ! Universal Serial Bus ! literal DYN$C_USB = 139; ! Universal Serial Bus literal DYN$C_USB_BUS = 1; ! Bus structure literal DYN$C_USB_DEVICE = 2; ! Device structure literal DYN$C_USB_INTERFACE = 3; ! Interface structure literal DYN$C_USB_PIPE = 4; ! Pipe structure literal DYN$C_USB_REQUEST = 5; ! Request structure literal DYN$C_USB_ENDPOINT = 6; ! Endpoint structure literal DYN$C_USB_HUB = 7; ! Hub structure literal DYN$C_USB_FUNCTION = 8; ! Function structure literal DYN$C_USB_BUFFER = 9; ! I/O buffer ! ! LAN facility specific structure types ! literal DYN$C_LAN = 140; ! LAN structure type literal DYN$C_LAN_LSB = 1; ! The LSB Structure literal DYN$C_LAN_FCRB = 2; ! Fibre Channel Request Block literal DYN$C_LAN_FCARP = 3; ! Fibre Channel Address Resolution Table ! ! TCPip facility specific structure types ! literal DYN$C_TCPIP = 141; ! TCPIP structure type ! ! ACPI facility specific structure types ! literal DYN$C_ACPI = 142; ! ACPI structure type ! ! Pshared specific data types ! literal DYN$C_PSH = 143; ! Pshared structure type literal DYN$C_PSH_ARY = 1; ! pshared array structure type literal DYN$C_PSH_MAS = 2; ! pshared master structure type literal DYN$C_PSH_OBJ = 3; ! pshared object structure type literal DYN$C_PSH_TIM = 4; ! pshared timeout structure type literal DYN$C_PSH_WT = 5; ! pshared wait structure type literal DYN$C_PSH_GBL = 6; ! pshared global structure type literal DYN$C_PSH_OWN = 7; ! pshared owner structure type literal DYN$C_PSH_STA = 8; ! pshared state structure type literal DYN$C_PSH_LCK = 9; ! pshared lock structure type literal DYN$C_PSH_DAT = 10; ! pshared data tag structure type ! ! Poolzones specific data types ! literal DYN$C_PZ = 144; ! Poolzones structure type literal DYN$C_PZ_PSH = 1; ! pshared poolzone literal DYN$C_PZ_LCK = 2; ! lock manager poolzone literal DYN$C_PZ_XFC = 3; ! XFC poolzone ! ! Calibration specific data types ! literal DYN$C_CAL = 145; ! CAL structure type ! ! Memory Mgt Structures ! literal DYN$C_MMG = 146; ! Memory Management Structure literal DYN$C_MMG_DEL = 1; ! DELPAG Control Structure !*** MODULE $EFIDEF *** ! ++ ! A GUID ! -- literal EFI$S_EFI_GUID = 16; macro EFI$l_data1 = 0,0,32,0 %; macro EFI$w_data2 = 4,0,16,0 %; macro EFI$w_data3 = 6,0,16,0 %; macro EFI$b_data4 = 8,0,0,0 %; literal EFI$s_data4 = 8; ! ++ ! EFI table header ! -- literal EFI$S_EFI_TABLE_HEADER = 24; macro EFI$q_signature = 0,0,0,0 %; literal EFI$s_signature = 8; ! Signature macro EFI$l_revision = 8,0,32,0 %; ! Revision macro EFI$l_headersize = 12,0,32,0 %; ! Size of header in bytes macro EFI$l_crc32 = 16,0,32,0 %; ! CRC macro EFI$l_reserved_1 = 20,0,32,0 %; ! Reserved literal EFI$S_EFI_RUNTIME_SERVICES = 112; macro EFI$r_runtime_services_hdr = 0,0,0,0 %; literal EFI$s_runtime_services_hdr = 24; ! Table header macro EFI$pq_get_time = 24,0,0,1 %; literal EFI$s_get_time = 8; ! Get time macro EFI$pq_set_time = 32,0,0,1 %; literal EFI$s_set_time = 8; ! Set time macro EFI$pq_get_wakeup_time = 40,0,0,1 %; literal EFI$s_get_wakeup_time = 8; ! Get wakeup time macro EFI$pq_set_wakeup_time = 48,0,0,1 %; literal EFI$s_set_wakeup_time = 8; ! Set wakeup time macro EFI$pq_set_virtual_address_map = 56,0,0,1 %; literal EFI$s_set_virtual_address_map = 8; ! Set virtual address map macro EFI$pq_convert_pointer = 64,0,0,1 %; literal EFI$s_convert_pointer = 8; ! Convert pointer macro EFI$pq_get_variable = 72,0,0,1 %; literal EFI$s_get_variable = 8; ! Get variable macro EFI$pq_get_next_variable_name = 80,0,0,1 %; literal EFI$s_get_next_variable_name = 8; ! Get next variable name macro EFI$pq_set_variable = 88,0,0,1 %; literal EFI$s_set_variable = 8; ! Set variable macro EFI$pq_get_next_high_mon_count = 96,0,0,1 %; literal EFI$s_get_next_high_mon_count = 8; macro EFI$pq_reset_system = 104,0,0,1 %; literal EFI$s_reset_system = 8; ! ++ ! EFI Boot Services ! -- literal EFI$S_EFI_BOOT_SERVICES = 264; macro EFI$r_boot_services_hdr = 0,0,0,0 %; literal EFI$s_boot_services_hdr = 24; ! Table header macro EFI$pq_raise_tpl = 24,0,0,1 %; literal EFI$s_raise_tpl = 8; macro EFI$pq_restore_tpl = 32,0,0,1 %; literal EFI$s_restore_tpl = 8; macro EFI$pq_allocate_pages = 40,0,0,1 %; literal EFI$s_allocate_pages = 8; macro EFI$pq_free_pages = 48,0,0,1 %; literal EFI$s_free_pages = 8; macro EFI$pq_get_memory_map = 56,0,0,1 %; literal EFI$s_get_memory_map = 8; macro EFI$pq_allocate_pool = 64,0,0,1 %; literal EFI$s_allocate_pool = 8; macro EFI$pq_free_pool = 72,0,0,1 %; literal EFI$s_free_pool = 8; macro EFI$pq_create_event = 80,0,0,1 %; literal EFI$s_create_event = 8; macro EFI$pq_set_timer = 88,0,0,1 %; literal EFI$s_set_timer = 8; macro EFI$pq_wait_for_event = 96,0,0,1 %; literal EFI$s_wait_for_event = 8; macro EFI$pq_signal_event = 104,0,0,1 %; literal EFI$s_signal_event = 8; macro EFI$pq_close_event = 112,0,0,1 %; literal EFI$s_close_event = 8; macro EFI$pq_check_event = 120,0,0,1 %; literal EFI$s_check_event = 8; macro EFI$pq_install_proto_interface = 128,0,0,1 %; literal EFI$s_install_proto_interface = 8; macro EFI$pq_reinst_proto_interface = 136,0,0,1 %; literal EFI$s_reinst_proto_interface = 8; macro EFI$pq_uninst_proto_interface = 144,0,0,1 %; literal EFI$s_uninst_proto_interface = 8; macro EFI$pq_handle_protocol = 152,0,0,1 %; literal EFI$s_handle_protocol = 8; macro EFI$pq_pc_handle_protocol = 160,0,0,1 %; literal EFI$s_pc_handle_protocol = 8; macro EFI$pq_register_protocol_notify = 168,0,0,1 %; literal EFI$s_register_protocol_notify = 8; macro EFI$pq_locate_handle = 176,0,0,1 %; literal EFI$s_locate_handle = 8; macro EFI$pq_locate_device_path = 184,0,0,1 %; literal EFI$s_locate_device_path = 8; macro EFI$pq_install_config_table = 192,0,0,1 %; literal EFI$s_install_config_table = 8; macro EFI$pq_image_load = 200,0,0,1 %; literal EFI$s_image_load = 8; macro EFI$pq_image_start = 208,0,0,1 %; literal EFI$s_image_start = 8; macro EFI$pq_exit = 216,0,0,1 %; literal EFI$s_exit = 8; macro EFI$pq_image_unload = 224,0,0,1 %; literal EFI$s_image_unload = 8; macro EFI$pq_exit_boot_services = 232,0,0,1 %; literal EFI$s_exit_boot_services = 8; macro EFI$pq_get_next_monotonic_count = 240,0,0,1 %; literal EFI$s_get_next_monotonic_count = 8; macro EFI$pq_stall = 248,0,0,1 %; literal EFI$s_stall = 8; macro EFI$pq_set_watchdog_timer = 256,0,0,1 %; literal EFI$s_set_watchdog_timer = 8; ! ++ ! EFI Configuration Table ! -- literal EFI$S_EFI_CONFIGURATION_TABLE = 24; macro EFI$r_vendor_guid = 0,0,0,0 %; literal EFI$s_vendor_guid = 16; macro EFI$pq_vendor_table = 16,0,0,1 %; literal EFI$s_vendor_table = 8; ! ++ ! EFI system table ! -- literal EFI$S_EFI_SYSTEM_TABLE = 120; macro EFI$r_system_table_hdr = 0,0,0,0 %; literal EFI$s_system_table_hdr = 24; macro EFI$pq_firmware_vendor = 24,0,0,1 %; literal EFI$s_firmware_vendor = 8; macro EFI$l_firmware_revision = 32,0,32,1 %; macro EFI$l_reserved_2 = 36,0,32,1 %; macro EFI$pq_console_in_handle = 40,0,0,1 %; literal EFI$s_console_in_handle = 8; macro EFI$pq_con_in = 48,0,0,1 %; literal EFI$s_con_in = 8; macro EFI$pq_console_out_handle = 56,0,0,1 %; literal EFI$s_console_out_handle = 8; macro EFI$pq_con_out = 64,0,0,1 %; literal EFI$s_con_out = 8; macro EFI$pq_standard_error_handle = 72,0,0,1 %; literal EFI$s_standard_error_handle = 8; macro EFI$pq_std_err = 80,0,0,1 %; literal EFI$s_std_err = 8; macro EFI$pq_runtime_services = 88,0,0,1 %; literal EFI$s_runtime_services = 8; macro EFI$pq_boot_services = 96,0,0,1 %; literal EFI$s_boot_services = 8; macro EFI$q_number_of_table_entries = 104,0,0,1 %; literal EFI$s_number_of_table_entries = 8; macro EFI$pq_configuration_table = 112,0,0,1 %; literal EFI$s_configuration_table = 8; ! ++ ! ESI (Estensible SAL Interface) entry pointer descriptor ! -- literal EFI$S_ESI_ENTRY = 48; macro EFI$b_esi_entry_type = 0,0,8,0 %; ! type == 0 macro EFI$b_esi_entry_reserved0 = 1,0,0,1 %; literal EFI$s_esi_entry_reserved0 = 7; ! reserved macro EFI$q_esi_entry_reserved1 = 8,0,0,1 %; literal EFI$s_esi_entry_reserved1 = 8; ! reserved macro EFI$q_esi_entry_proc_addr = 16,0,0,0 %; literal EFI$s_esi_entry_proc_addr = 8; ! Procedure code address macro EFI$q_esi_entry_global_ptr = 24,0,0,0 %; literal EFI$s_esi_entry_global_ptr = 8; ! Procedure gp macro EFI$r_esi_entry_guid = 32,0,0,0 %; literal EFI$s_esi_entry_guid = 16; ! GUID ! ++ ! ESI (Extensible SAL Interface) table ! -- literal EFI$S_ESI_TABLE = 144; macro EFI$l_esi_signature = 0,0,32,0 %; ! Signature macro EFI$l_esi_length = 4,0,32,0 %; ! Length of entire structure macro EFI$w_esi_revision = 8,0,16,0 %; ! Revision macro EFI$w_esi_entry_count = 10,0,16,0 %; ! Number of array entries macro EFI$b_esi_check_sum = 12,0,8,0 %; ! CRC macro EFI$b_esi_reserved_1 = 13,0,0,1 %; literal EFI$s_esi_reserved_1 = 7; ! Reserved macro EFI$w_esi_sal_a_ver = 20,0,16,0 %; ! SAL_A version macro EFI$w_esi_sal_b_ver = 22,0,16,0 %; ! SAL_B version macro EFI$t_esi_oem_id = 24,0,0,0 %; literal EFI$s_esi_oem_id = 32; ! OEM ID macro EFI$t_esi_product_id = 56,0,0,0 %; literal EFI$s_esi_product_id = 32; ! Product ID macro EFI$b_esi_reserved_2 = 88,0,0,1 %; literal EFI$s_esi_reserved_2 = 8; ! Reserved macro EFI$r_esi_entries = 96,0,0,0 %; literal EFI$s_esi_entries = 48; ! Array of ESI entries ! ++ ! EFI memory descriptor ! -- literal EFI$m_memory_uc = %X'1'; literal EFI$m_memory_wc = %X'2'; literal EFI$m_memory_wt = %X'4'; literal EFI$m_memory_wb = %X'8'; literal EFI$m_memory_uce = %X'10'; literal EFI$m_undefined = %X'7FFFFFFFFFFFFFE0'; literal EFI$m_memory_runtime = %X'8000000000000000'; literal EFI$S_EFI_MEMORY_DESCRIPTOR = 48; macro EFI$l_type = 0,0,32,0 %; macro EFI$l_reserved_3 = 4,0,32,0 %; macro EFI$q_physical_start = 8,0,0,0 %; literal EFI$s_physical_start = 8; macro EFI$pq_virtual_start = 16,0,0,1 %; literal EFI$s_virtual_start = 8; macro EFI$q_number_of_pages = 24,0,0,0 %; literal EFI$s_number_of_pages = 8; macro EFI$R_ATTR_UNION = 32,0,0,0 %; literal EFI$S_ATTR_UNION = 8; macro EFI$q_attribute = 32,0,0,0 %; literal EFI$s_attribute = 8; macro EFI$v_memory_uc = 32,0,1,0 %; macro EFI$v_memory_wc = 32,1,1,0 %; macro EFI$v_memory_wt = 32,2,1,0 %; macro EFI$v_memory_wb = 32,3,1,0 %; macro EFI$v_memory_uce = 32,4,1,0 %; macro EFI$v_memory_runtime = 36,31,1,0 %; macro EFI$q_reserved_4 = 40,0,0,0 %; literal EFI$s_reserved_4 = 8; literal EFI$C_RESERVED_MEMORY_TYPE = 0; literal EFI$C_LOADER_CODE = 1; literal EFI$C_LOADER_DATA = 2; literal EFI$C_BOOT_SERVICES_CODE = 3; literal EFI$C_BOOT_SERVICES_DATA = 4; literal EFI$C_RUNTIME_SERVICES_CODE = 5; literal EFI$C_RUNTIME_SERVICES_DATA = 6; literal EFI$C_CONVENTIONAL_MEMORY = 7; literal EFI$C_UNUSABLE_MEMORY = 8; literal EFI$C_ACPI_RECLAIM_MEMORY = 9; literal EFI$C_ACPI_MEMORY_NVS = 10; literal EFI$C_MEMORY_MAPPED_IO = 11; literal EFI$C_MEM_MAP_IO_PORT_SPACE = 12; literal EFI$C_PAL_CODE = 13; literal EFI$C_MAX_MEMORY_TYPE = 14; ! ++ ! Time ! -- literal EFI$m_time_adjust_daylight = %X'1'; literal EFI$m_time_in_daylight = %X'2'; literal EFI$S_EFI_TIME = 16; macro EFI$w_year = 0,0,16,0 %; ! 1998 - 20XX macro EFI$b_month = 2,0,8,0 %; ! 1-12 macro EFI$b_day = 3,0,8,0 %; ! 1-31 macro EFI$b_hour = 4,0,8,0 %; ! 0-23 macro EFI$b_minute = 5,0,8,0 %; ! 0-59 macro EFI$b_second = 6,0,8,0 %; ! 0-59 macro EFI$l_nanosecond = 8,0,32,0 %; ! 0-999,999,999 macro EFI$w_time_zone = 12,0,16,1 %; ! -1440 to 1440 or 2047 macro EFI$r_dl_union = 14,0,8,0 %; literal EFI$s_dl_union = 1; macro EFI$b_day_light = 14,0,8,0 %; macro EFI$v_time_adjust_daylight = 14,0,1,0 %; macro EFI$v_time_in_daylight = 14,1,1,0 %; literal EFI$C_unspecified_timezone = 2047; literal EFI$C_all_handles = 0; literal EFI$C_by_register_notify = 1; literal EFI$C_by_protocol = 2; ! ++ ! Generic return status used by EFI calls ! -- literal EFI$C_SUCCESS = 0; literal EFI$C_LOAD_ERROR = 1; literal EFI$C_INVALID_PARAMETER = 2; literal EFI$C_UNSUPPORTED = 3; literal EFI$C_BAD_BUFFER_SIZE = 4; literal EFI$C_BUFFER_TOO_SMALL = 5; literal EFI$C_NOT_READY = 6; literal EFI$C_DEVICE_ERROR = 7; !*** MODULE $EIAFDEF *** ! + ! EIAF - EXTENDED IMAGE ACTIVATOR FIXUP SECTION ! ! THE IMAGE ACTIVATOR FIXUP SECTION IS AN IMAGE SECTION THAT IS CREATED ! BY THE LINKER AND USED BY THE IMAGE ACTIVATOR TO MODIFY THE IMAGE AS ! IT IS ACTIVATED. THIS IS DONE TO MAINTAIN THE POSITION INDEPENDENCE ! OF EXTERNAL REFERENCES. ! - literal EIAF$K_LENGTH = 84; ! Length of fixed area (should be quadword aligned) literal EIAF$C_LENGTH = 84; ! Length of fixed area literal EIAF$S_EIAFDEF = 84; literal EIAF$S_EIAF = 84; macro EIAF$R_VERSION = 0,0,0,0 %; literal EIAF$S_VERSION = 8; ! Version of this EIAF macro EIAF$L_MAJORID = 0,0,32,0 %; ! Major ID macro EIAF$L_MINORID = 4,0,32,0 %; ! Minor ID macro EIAF$L_IAFLINK = 8,0,32,1 %; macro EIAF$Q_IAFLINK = 8,0,0,1 %; literal EIAF$S_IAFLINK = 8; macro EIAF$L_FIXUPLNK = 16,0,32,1 %; macro EIAF$Q_FIXUPLNK = 16,0,0,1 %; literal EIAF$S_FIXUPLNK = 8; macro EIAF$L_SIZE = 24,0,32,1 %; ! Size of fixed part of EIAF macro EIAF$L_FLAGS = 28,0,32,0 %; ! Flags macro EIAF$V_SHR = 28,0,1,0 %; ! This is in a shareable image macro EIAF$L_QRELFIXOFF = 32,0,32,1 %; ! Offset to quadword relocation fixup data macro EIAF$L_LRELFIXOFF = 36,0,32,1 %; ! Offset to longword relocation fixup data macro EIAF$L_QDOTADROFF = 40,0,32,1 %; ! Offset to quadword .address fixup data macro EIAF$L_LDOTADROFF = 44,0,32,1 %; ! Offset to longword .address fixup data macro EIAF$L_CODEADROFF = 48,0,32,1 %; ! Offset to code address fixup data macro EIAF$L_LPFIXOFF = 52,0,32,1 %; ! Offset to linkage pair fixup data macro EIAF$L_CHGPRTOFF = 56,0,32,1 %; ! Offset to isect change prot. data macro EIAF$L_SHLSTOFF = 60,0,32,1 %; ! Offset to shareable image list macro EIAF$L_SHRIMGCNT = 64,0,32,1 %; ! Number of shareable images in shlst macro EIAF$L_SHLEXTRA = 68,0,32,1 %; ! Number of extra shareable images allowed macro EIAF$L_PERMCTX = 72,0,32,1 %; ! Permanent sharable image context macro EIAF$L_BASE_VA = 76,0,32,1 %; ! Base address of the image itself macro EIAF$L_LPPSBFIXOFF = 80,0,32,1 %; ! Offset to "linkage pair with procedure signature" fixups !*** MODULE $EICPDEF *** ! + ! EICP - EXTENDED CHANGE IMAGE SECTION PROTECTION DATA ! ! THIS STRUCTURE IS USED IN THE IMAGE FIXUP SECTION BY THE LINKER ! TO INFORM THE IMAGE ACTIVATOR OF THE IMAGE SECTIONS THAT NEED ! THEIR PROTECTION CHANGED. ! - literal EICP$K_LENGTH = 16; ! size of one section's data literal EICP$C_LENGTH = 16; ! size of one section's data literal EICP$S_EICPDEF = 16; literal EICP$S_EICP = 16; macro EICP$L_BASEVA = 0,0,32,0 %; macro EICP$Q_BASEVA = 0,0,0,0 %; literal EICP$S_BASEVA = 8; macro EICP$L_SIZE = 8,0,32,0 %; ! size in bytes of the image section macro EICP$L_NEWPRT = 12,0,32,0 %; ! new protection !*** MODULE $EIHADEF *** ! + ! EXTENDED IMAGE HEADER ACTIVATION SECTION OFFSETS ! - literal EIHA$K_LENGTH = 48; ! SIZE OF ACTIVATION SECTION literal EIHA$C_LENGTH = 48; ! SIZE OF ACTIVATION SECTION literal EIHA$S_EIHADEF = 48; literal EIHA$S_EIHA = 48; macro EIHA$L_SIZE = 0,0,32,0 %; ! Size in bytes of EIHA(#transfers = size/8) macro EIHA$L_SPARE = 4,0,32,0 %; ! Spare macro EIHA$Q_TFRADR1 = 8,0,0,0 %; literal EIHA$S_TFRADR1 = 8; macro EIHA$L_TFRADR1 = 8,0,32,0 %; macro EIHA$L_TFRADR1_H = 12,0,32,0 %; macro EIHA$Q_TFRADR2 = 16,0,0,0 %; literal EIHA$S_TFRADR2 = 8; macro EIHA$L_TFRADR2 = 16,0,32,0 %; macro EIHA$L_TFRADR2_H = 20,0,32,0 %; macro EIHA$Q_TFRADR3 = 24,0,0,0 %; literal EIHA$S_TFRADR3 = 8; macro EIHA$L_TFRADR3 = 24,0,32,0 %; macro EIHA$L_TFRADR3_H = 28,0,32,0 %; macro EIHA$Q_TFRADR4 = 32,0,0,0 %; literal EIHA$S_TFRADR4 = 8; macro EIHA$L_TFRADR4 = 32,0,32,0 %; macro EIHA$L_TFRADR4_H = 36,0,32,0 %; macro EIHA$L_INISHR = 40,0,32,0 %; ! (valid if IHD$V_INISHR set) macro EIHA$Q_INISHR = 40,0,0,0 %; literal EIHA$S_INISHR = 8; !*** MODULE $EIHDDEF *** ! + ! EXTENDED IMAGE HEADER RECORD DEFINITIONS - FIRST RECORD OF THE EXTENDED IMAGE HEADER ! - literal EIHD$K_MAJORID = 3; ! Major id constant literal EIHD$K_MINORID = 0; ! Minor id constant literal EIHD$K_MINORID_64 = 1; ! Alt Minor id constant literal EIHD$K_EXE = 1; ! Executable image literal EIHD$K_LIM = 2; ! Linkable image literal EIHD$C_MINCODE = 0; ! Low bound of ALIAS values literal EIHD$C_NATIVE = 0; ! Alpha native mode image literal EIHD$C_CLI = 1; ! Image is a CLI, run LOGINOUT literal EIHD$C_MAXCODE = 1; ! High bound of ALIAS values literal EIHD$M_LNKDEBUG = %X'1'; literal EIHD$M_LNKNOTFR = %X'2'; literal EIHD$M_NOP0BUFS = %X'4'; literal EIHD$M_PICIMG = %X'8'; literal EIHD$M_P0IMAGE = %X'10'; literal EIHD$M_DBGDMT = %X'20'; literal EIHD$M_INISHR = %X'40'; literal EIHD$M_XLATED = %X'80'; literal EIHD$M_BIND_CODE_SEC = %X'100'; literal EIHD$M_BIND_DATA_SEC = %X'200'; literal EIHD$M_MKTHREADS = %X'400'; literal EIHD$M_UPCALLS = %X'800'; literal EIHD$M_OMV_READY = %X'1000'; literal EIHD$M_EXT_BIND_SECT = %X'2000'; literal EIHD$K_LENGTH = 104; ! Length of fixed area literal EIHD$C_LENGTH = 104; ! Length of fixed area literal EIHD$K_LENGTH_97 = 112; ! Length of fixed area literal EIHD$K_ALIAS_MINCODE = -1; ! Low bound of ALIAS values ! Following are reserved but not used by the Alpha linker literal EIHD$K_VAX = -1; ! Native mode image literal EIHD$K_RSX = 0; ! RSX image produced by TKB literal EIHD$K_BPA = 1; ! BASIC plus analog literal EIHD$K_ALIAS = 2; ! Last 126 bytes contains ASCIC of image to activate literal EIHD$K_VAX_CLI = 3; ! Image is a CLI, run LOGINOUT literal EIHD$K_PMAX = 4; ! PMAX system image ! Alpha linker writes this value into last word of 1st header block for system images only literal EIHD$K_ALPHA = 5; literal EIHD$K_ALIAS_MAXCODE = 5; ! High bound of ALIAS values literal EIHD$S_EIHDDEF = 512; ! Old size name - synonym literal EIHD$S_EIHD = 512; macro EIHD$R_VERSION = 0,0,0,0 %; literal EIHD$S_VERSION = 8; ! Version of this EIHD macro EIHD$L_MAJORID = 0,0,32,0 %; ! Major id macro EIHD$L_MINORID = 4,0,32,0 %; ! Minor id macro EIHD$L_SIZE = 8,0,32,0 %; ! Size in bytes of image header macro EIHD$L_ISDOFF = 12,0,32,0 %; ! Byte offset to ISD list macro EIHD$L_ACTIVOFF = 16,0,32,0 %; ! Byte offset to activation data macro EIHD$L_SYMDBGOFF = 20,0,32,0 %; ! Byte offset to symbol table and debug data macro EIHD$L_IMGIDOFF = 24,0,32,0 %; ! Byte offset to image ident data macro EIHD$L_PATCHOFF = 28,0,32,0 %; ! Byte offset to patch data macro EIHD$L_IAFVA = 32,0,32,1 %; macro EIHD$Q_IAFVA = 32,0,0,1 %; literal EIHD$S_IAFVA = 8; macro EIHD$L_SYMVVA = 40,0,32,1 %; macro EIHD$Q_SYMVVA = 40,0,0,1 %; literal EIHD$S_SYMVVA = 8; macro EIHD$L_VERSION_ARRAY_OFF = 48,0,32,0 %; ! Byte offset to version number array macro EIHD$L_IMGTYPE = 52,0,32,0 %; ! Image type ! ! IMAGE TYPE CODES ! macro EIHD$L_SUBTYPE = 56,0,32,0 %; ! Code to use secondary image name ! ***************************************** ! ! Define legal range of SUBTYPE constants. MINCODE must be equal to the ! lowest value and MAXCODE must be equal to the highest value. ! macro EIHD$L_IMGIOCNT = 60,0,32,0 %; ! size in bytes of image i/o section requested ! 0 if default macro EIHD$L_IOCHANCNT = 64,0,32,0 %; ! # channels requested macro EIHD$Q_PRIVREQS = 68,0,0,0 %; literal EIHD$S_PRIVREQS = 8; ! requested privelege mask macro EIHD$L_HDRBLKCNT = 76,0,32,0 %; ! # header diskblocks macro EIHD$R_LNKFLAGS_OVERLAY = 80,0,32,0 %; macro EIHD$L_LNKFLAGS = 80,0,32,0 %; ! Linker produced image flags macro EIHD$R_LNKFLAGS_BITS = 80,0,16,0 %; macro EIHD$V_LNKDEBUG = 80,0,1,0 %; ! Full debugging requested macro EIHD$V_LNKNOTFR = 80,1,1,0 %; ! First transfer address missing macro EIHD$V_NOP0BUFS = 80,2,1,0 %; ! RMS use of P0 for image i/o disabled macro EIHD$V_PICIMG = 80,3,1,0 %; ! Image is position independent macro EIHD$V_P0IMAGE = 80,4,1,0 %; ! Image is in P0 space only macro EIHD$V_DBGDMT = 80,5,1,0 %; ! Image header has dmt fields macro EIHD$V_INISHR = 80,6,1,0 %; ! Transfer array contains valid IHA$L_INISHR macro EIHD$V_XLATED = 80,7,1,0 %; ! Translated image macro EIHD$V_BIND_CODE_SEC = 80,8,1,0 %; ! EXE image sections can be put into S0 if set macro EIHD$V_BIND_DATA_SEC = 80,9,1,0 %; ! DATA image sections can be put into S0 if set macro EIHD$V_MKTHREADS = 80,10,1,0 %; ! Multiple kernel threads enabled macro EIHD$V_UPCALLS = 80,11,1,0 %; ! Upcalls enabled macro EIHD$V_OMV_READY = 80,12,1,0 %; ! image may be correctly processed by OMV macro EIHD$V_EXT_BIND_SECT = 80,13,1,0 %; ! isects may be moved, if extended fixups applied. ! this applies to both code and data sections. macro EIHD$L_IDENT = 84,0,32,0 %; ! GBL SEC ident value for linkable image macro EIHD$L_SYSVER = 88,0,32,0 %; ! SYS$K_VERSION or 0 if not linked with exec macro EIHD$R_CONTROL = 92,0,0,0 %; literal EIHD$S_CONTROL = 12; ! Linker control fields macro EIHD$B_MATCHCTL = 92,0,8,0 %; ! Linker match control macro EIHD$B_FILL_1 = 93,0,8,0 %; ! Spares macro EIHD$B_FILL_2 = 94,0,8,0 %; ! Spares macro EIHD$B_FILL_3 = 95,0,8,0 %; ! Spares macro EIHD$L_SYMVECT_SIZE = 96,0,32,0 %; ! Size of the symbol vector in bytes macro EIHD$L_VIRT_MEM_BLOCK_SIZE = 100,0,32,0 %; ! Virtual memory size used for link (value given to /BPAGE, power of 2 ! from 9 to 16) macro EIHD$L_EXT_FIXUP_OFF = 104,0,32,0 %; ! Byte offset to extended fixup data macro EIHD$L_NOOPT_PSECT_OFF = 108,0,32,0 %; ! Byte offset to no_optimize psect table macro EIHD$T_SKIP = 112,0,0,0 %; literal EIHD$S_SKIP = 398; ! ALIAS is last word in 512 byte block of system image macro EIHD$W_ALIAS = 510,0,16,0 %; ! CODE identifies image type to MOM ! ***************************************** ! ! Define legal range of ALIAS constants. ALIAS_MINCODE must be equal to the ! lowest value and ALIAS_MAXCODE must be equal to the highest value. ! !*** MODULE $EIHEFDEF *** ! + ! IMAGE HEADER EXTENDED FIXUP POINTER ! - literal EIHEF$K_MAJORID = 1; literal EIHEF$K_MINORID = 0; literal EIHEF$K_LENGTH = 12; ! LENGTH OF TABLE literal EIHEF$S_EIHEF = 12; macro EIHEF$R_VERSION = 0,0,32,0 %; literal EIHEF$S_VERSION = 4; ! Version of this STRUCTURE macro EIHEF$W_MAJORID = 0,0,16,0 %; ! Major ID macro EIHEF$W_MINORID = 2,0,16,0 %; ! Minor ID macro EIHEF$L_VBN = 4,0,32,0 %; ! EXTENDED FIXUP TABLE VIRTUAL BLOCK NUMBER macro EIHEF$L_SIZE = 8,0,32,0 %; ! EXTENDED FIXUP SIZE IN BYTES !*** MODULE $EIHIDEF *** ! + ! EXTENDED IMAGE HEADER IDENTIFICATION SECTION OFFSETS ! - literal EIHI$K_MAJORID = 1; literal EIHI$K_MINORID = 2; literal EIHI$K_LENGTH = 104; ! LENGTH OF IMAGE HEADER IDENT SECTION literal EIHI$C_LENGTH = 104; ! LENGTH OF IMAGE HEADER IDENT SECTION literal EIHI$S_EIHIDEF = 104; ! Old size name - synonym literal EIHI$S_EIHI = 104; macro EIHI$R_VERSION = 0,0,0,0 %; literal EIHI$S_VERSION = 8; ! Version of this EIHP macro EIHI$L_MAJORID = 0,0,32,0 %; ! Major ID macro EIHI$L_MINORID = 4,0,32,0 %; ! Minor ID macro EIHI$Q_LINKTIME = 8,0,0,0 %; literal EIHI$S_LINKTIME = 8; ! DATE AND TIME THIS IMAGE WAS LINKED ! STANDARD SYSTEM QUADWORD FORMAT macro EIHI$T_IMGNAM = 16,0,0,0 %; literal EIHI$S_IMGNAM = 40; ! IMAGE NAME STRING macro EIHI$T_IMGID = 56,0,0,0 %; literal EIHI$S_IMGID = 16; ! IMAGE IDENT STRING macro EIHI$T_LINKID = 72,0,0,0 %; literal EIHI$S_LINKID = 16; ! LINKER IDENT STRING macro EIHI$T_IMGBID = 88,0,0,0 %; literal EIHI$S_IMGBID = 16; ! IMAGE BUILD IDENT STRING !*** MODULE $EIHNPDEF *** ! + ! IMAGE HEADER NO-OPTIMIZE PSECT TABLE POINTER BLOCK ! - literal EIHNP$K_MAJORID = 1; literal EIHNP$K_MINORID = 0; literal EIHNP$K_LENGTH = 12; ! LENGTH OF TABLE literal EIHNP$S_EIHNP = 12; macro EIHNP$R_VERSION = 0,0,32,0 %; literal EIHNP$S_VERSION = 4; ! Version of this STRUCTURE macro EIHNP$W_MAJORID = 0,0,16,0 %; ! Major ID macro EIHNP$W_MINORID = 2,0,16,0 %; ! Minor ID macro EIHNP$L_VBN = 4,0,32,0 %; ! NO-OPTIMIZE PSECT TABLE VIRTUAL BLOCK NUMBER macro EIHNP$L_SIZE = 8,0,32,0 %; ! NO-OPTIMIZE PSECT SIZE IN BYTES !*** MODULE $EIHPDEF *** ! + ! EXTENDED IMAGE HEADER PATCH SECTION OFFSETS ! - literal EIHP$K_LENGTH = 60; ! LENGTH OF PATCH HEADER SECTION literal EIHP$C_LENGTH = 60; ! LENGTH OF PATCH HEADER SECTION literal EIHP$S_EIHPDEF = 60; literal EIHP$S_EIHP = 60; macro EIHP$R_VERSION = 0,0,0,0 %; literal EIHP$S_VERSION = 8; ! Version of this EIHP macro EIHP$L_MAJORID = 0,0,32,0 %; ! Major ID macro EIHP$L_MINORID = 4,0,32,0 %; ! Minor ID macro EIHP$L_ECO1 = 8,0,32,0 %; ! DEC ECO LEVELS 1-32 macro EIHP$L_ECO2 = 12,0,32,0 %; ! DEC ECO LEVELS 33-64 macro EIHP$L_ECO3 = 16,0,32,0 %; ! DEC ECO LEVELS 65-98 macro EIHP$L_ECO4 = 20,0,32,0 %; ! USER ECO LEVELS 99-132 macro EIHP$L_PATCOMTXT = 24,0,32,0 %; ! PATCH COMMAND TEXT VIRTUAL BLOCK NUMBER macro EIHP$L_RW_PATSIZ = 28,0,32,0 %; ! SIZE OF FREE RW PATCH AREA macro EIHP$L_RW_PATADR = 32,0,32,0 %; macro EIHP$Q_RW_PATADR = 32,0,0,0 %; literal EIHP$S_RW_PATADR = 8; macro EIHP$L_RO_PATSIZ = 40,0,32,0 %; ! SIZE OF FREE RO PATCH AREA macro EIHP$L_RO_PATADR = 44,0,32,0 %; macro EIHP$Q_RO_PATADR = 44,0,0,0 %; literal EIHP$S_RO_PATADR = 8; macro EIHP$Q_PATDATE = 52,0,0,0 %; literal EIHP$S_PATDATE = 8; ! DATE OF MOST RECENT PATCH !*** MODULE $EIHSDEF *** ! + ! IMAGE HEADER SYMBOL TABLE AND DEBUG SECTION OFFSETS ! - literal EIHS$K_MAJORID = 1; literal EIHS$K_MINORID = 1; literal EIHS$K_LENGTH = 32; ! LENGTH OF SYMBOL TABLE SECTION literal EIHS$C_LENGTH = 32; ! LENGTH OF SYMBOL TABLE SECTION literal EIHS$S_EIHSDEF = 32; literal EIHS$S_EIHS = 32; macro EIHS$R_VERSION = 0,0,0,0 %; literal EIHS$S_VERSION = 8; ! Version of this EIHP macro EIHS$L_MAJORID = 0,0,32,0 %; ! Major ID macro EIHS$L_MINORID = 4,0,32,0 %; ! Minor ID macro EIHS$L_DSTVBN = 8,0,32,0 %; ! DEBUG SYMBOL TABLE VIRTUAL BLOCK NUMBER macro EIHS$L_DSTSIZE = 12,0,32,0 %; ! DEBUG SYMBOL SIZE IN BYTES macro EIHS$L_GSTVBN = 16,0,32,0 %; ! GLOBAL SYMBOL TABLE VIRTUAL BLOCK NUMBER macro EIHS$L_GSTSIZE = 20,0,32,0 %; ! GLOBAL SYMBOL TABLE RECORD COUNT macro EIHS$L_DMTVBN = 24,0,32,0 %; ! VBN OF DMT INFORMATION macro EIHS$L_DMTBYTES = 28,0,32,0 %; ! LENGTH OF DMT INFO !*** MODULE $EIHVNDEF *** literal EIHVN$M_SUBVERSION_MINOR_ID = %X'FFFF'; literal EIHVN$M_SUBVERSION_MAJOR_ID = %X'FFFF0000'; literal EIHVN$S_EIMG_VERSION_ARRAY = 8; macro EIHVN$L_SUBSYSTEM_MASK = 0,0,32,0 %; ! Bit mask of nonzero version numbers macro EIHVN$L_SUBVERSION_ARRAY = 4,0,32,0 %; ! First array element macro EIHVN$V_SUBVERSION_MINOR_ID = 4,0,16,0 %; literal EIHVN$S_SUBVERSION_MINOR_ID = 16; ! Minor ID for each component macro EIHVN$V_SUBVERSION_MAJOR_ID = 4,16,16,0 %; literal EIHVN$S_SUBVERSION_MAJOR_ID = 16; ! Major ID for each component literal EIHVN$M_VERSION_MINOR_ID = %X'FFFFFF'; literal EIHVN$M_VERSION_MAJOR_ID = %X'FF000000'; literal EIHVN$S_EIMG_OVERALL_VERSION = 4; macro EIHVN$V_VERSION_MINOR_ID = 0,0,24,0 %; literal EIHVN$S_VERSION_MINOR_ID = 24; ! Minor ID of SYS.STB macro EIHVN$V_VERSION_MAJOR_ID = 0,24,8,0 %; literal EIHVN$S_VERSION_MAJOR_ID = 8; ! Major ID of SYS.STB literal EIHVN$K_LENGTH = 132; literal EIHVN$C_LENGTH = 132; !*** MODULE $EISABUSDEF *** ! ! This file describes the layout of EISA CSR space. It is based ! on the EISA spec, V3.10 BCPR Service, INC. ! literal EISA$M_PIC_L_ICW1_ICW4 = %X'1'; literal EISA$M_PIC_L_ICW1_SNGL = %X'2'; literal EISA$M_PIC_L_OCW2_L0 = %X'1'; literal EISA$M_PIC_L_OCW2_L1 = %X'2'; literal EISA$M_PIC_L_OCW2_L2 = %X'4'; literal EISA$M_PIC_L_OCW2_EOI = %X'20'; literal EISA$M_PIC_L_OCW2_SL = %X'40'; literal EISA$M_PIC_L_OCW2_R = %X'80'; literal EISA$M_PIC_L_OCW3_RIS = %X'1'; literal EISA$M_PIC_L_OCW3_RR = %X'2'; literal EISA$M_PIC_L_OCW3_P = %X'4'; literal EISA$M_PIC_L_OCW3_SMM = %X'20'; literal EISA$M_PIC_L_OCW3_ESMM = %X'40'; literal EISA$M_PIC_L_ICW2_ZEROES = %X'7'; literal EISA$M_PIC_L_ICW2_VEC = %X'F8'; literal EISA$M_PIC_L_ICW3_IRQ0_SLAVE = %X'1'; literal EISA$M_PIC_L_ICW3_IRQ1_SLAVE = %X'2'; literal EISA$M_PIC_L_ICW3_IRQ2_SLAVE = %X'4'; literal EISA$M_PIC_L_ICW3_IRQ3_SLAVE = %X'8'; literal EISA$M_PIC_L_ICW3_IRQ4_SLAVE = %X'10'; literal EISA$M_PIC_L_ICW3_IRQ5_SLAVE = %X'20'; literal EISA$M_PIC_L_ICW3_IRQ6_SLAVE = %X'40'; literal EISA$M_PIC_L_ICW3_IRQ7_SLAVE = %X'80'; literal EISA$M_PIC_L_ICW4_MODE = %X'1'; literal EISA$M_PIC_L_ICW4_AEOI = %X'2'; literal EISA$M_PIC_L_ICW4_BUFF = %X'18'; literal EISA$M_PIC_L_ICW4_NEST = %X'20'; literal EISA$M_PIC_L_OCW1_MASK = %X'FF'; literal EISA$M_PIC_L_T1_SYSTIM_BCD = %X'1'; literal EISA$M_PIC_L_T1_SYSTIM_MODE = %X'E'; literal EISA$M_PIC_L_T1_SYSTIM_RW = %X'30'; literal EISA$M_PIC_L_T1_SYSTIM_STAT = %X'40'; literal EISA$M_PIC_L_T1_SYSTIM_OUT = %X'80'; literal EISA$M_PIC_L_T1_REF_BCD = %X'1'; literal EISA$M_PIC_L_T1_REF_MODE = %X'E'; literal EISA$M_PIC_L_T1_REF_RW = %X'30'; literal EISA$M_PIC_L_T1_REF_STAT = %X'40'; literal EISA$M_PIC_L_T1_REF_OUT = %X'80'; literal EISA$M_PIC_L_T1_SPKR_BCD = %X'1'; literal EISA$M_PIC_L_T1_SPKR_MODE = %X'E'; literal EISA$M_PIC_L_T1_SPKR_RW = %X'30'; literal EISA$M_PIC_L_T1_SPKR_STAT = %X'40'; literal EISA$M_PIC_L_T1_SPKR_OUT = %X'80'; literal EISA$M_PIC_L_T1_CTRL_BCD = %X'1'; literal EISA$M_PIC_L_T1_CTRL_MODE = %X'E'; literal EISA$M_PIC_L_T1_CTRL_CNTLAT = %X'30'; literal EISA$M_PIC_L_T1_CTRL_CNTSEL = %X'C0'; literal EISA$M_PIC_L_T2_FLSF_BCD = %X'1'; literal EISA$M_PIC_L_T2_FLSF_MODE = %X'E'; literal EISA$M_PIC_L_T2_FLSF_RW = %X'30'; literal EISA$M_PIC_L_T2_FLSF_STAT = %X'40'; literal EISA$M_PIC_L_T2_FLSF_OUT = %X'80'; literal EISA$M_PIC_L_T2_CPUSPD_BCD = %X'1'; literal EISA$M_PIC_L_T2_CPUSPD_MODE = %X'E'; literal EISA$M_PIC_L_T2_CPUSPD_RW = %X'30'; literal EISA$M_PIC_L_T2_CPUSPD_STAT = %X'40'; literal EISA$M_PIC_L_T2_CPUSPD_OUT = %X'80'; literal EISA$M_PIC_L_T2_CTRL_BCD = %X'1'; literal EISA$M_PIC_L_T2_CTRL_MODE = %X'E'; literal EISA$M_PIC_L_T2_CTRL_CNTLAT = %X'30'; literal EISA$M_PIC_L_T2_CTRL_CNTSEL = %X'C0'; literal EISA$M_PIC_L_NMICSR_T1 = %X'1'; literal EISA$M_PIC_L_NMICSR_SPKR = %X'2'; literal EISA$M_PIC_L_NMICSR_PE = %X'4'; literal EISA$M_PIC_L_NMICSR_IOCHK = %X'8'; literal EISA$M_PIC_L_NMICSR_REF = %X'10'; literal EISA$M_PIC_L_NMICSR_INTM1 = %X'20'; literal EISA$M_PIC_L_NMICSR_NMIINT = %X'40'; literal EISA$M_PIC_L_NMICSR_PAR = %X'80'; literal EISA$M_PIC_L_NMIRTC_CLKADR = %X'7F'; literal EISA$M_PIC_L_NMIRTC_ENDIS = %X'80'; literal EISA$M_PIC_H_ICW1_ICW4 = %X'1'; literal EISA$M_PIC_H_ICW1_SNGL = %X'2'; literal EISA$M_PIC_H_OCW2_L0 = %X'1'; literal EISA$M_PIC_H_OCW2_L1 = %X'2'; literal EISA$M_PIC_H_OCW2_L2 = %X'4'; literal EISA$M_PIC_H_OCW2_EOI = %X'20'; literal EISA$M_PIC_H_OCW2_SL = %X'40'; literal EISA$M_PIC_H_OCW2_R = %X'80'; literal EISA$M_PIC_H_OCW3_RIS = %X'1'; literal EISA$M_PIC_H_OCW3_RR = %X'2'; literal EISA$M_PIC_H_OCW3_P = %X'4'; literal EISA$M_PIC_H_OCW3_SMM = %X'20'; literal EISA$M_PIC_H_OCW3_ESMM = %X'40'; literal EISA$M_PIC_H_ICW2_ZEROES = %X'7'; literal EISA$M_PIC_H_ICW2_VEC = %X'F8'; literal EISA$M_PIC_H_ICW3_IRQ0_SLAVE = %X'1'; literal EISA$M_PIC_H_ICW3_IRQ1_SLAVE = %X'2'; literal EISA$M_PIC_H_ICW3_IRQ2_SLAVE = %X'4'; literal EISA$M_PIC_H_ICW3_IRQ3_SLAVE = %X'8'; literal EISA$M_PIC_H_ICW3_IRQ4_SLAVE = %X'10'; literal EISA$M_PIC_H_ICW3_IRQ5_SLAVE = %X'20'; literal EISA$M_PIC_H_ICW3_IRQ6_SLAVE = %X'40'; literal EISA$M_PIC_H_ICW3_IRQ7_SLAVE = %X'80'; literal EISA$M_PIC_H_ICW4_MODE = %X'1'; literal EISA$M_PIC_H_ICW4_AEOI = %X'2'; literal EISA$M_PIC_H_ICW4_BUFF = %X'18'; literal EISA$M_PIC_H_ICW4_NEST = %X'20'; literal EISA$M_PIC_H_OCW1_MASK = %X'FF'; literal EISA$M_PIC_EXNMICSR_BUSRST = %X'1'; literal EISA$M_PIC_EXNMICSR_ENIO = %X'2'; literal EISA$M_PIC_EXNMICSR_FSEN = %X'4'; literal EISA$M_PIC_EXNMICSR_TOEN = %X'8'; literal EISA$M_PIC_EXNMICSR_IOP = %X'20'; literal EISA$M_PIC_EXNMICSR_BT = %X'40'; literal EISA$M_PIC_EXNMICSR_FSINT = %X'80'; literal EISA$M_PIC_EISA_BUSMAS_SL1 = %X'1'; literal EISA$M_PIC_EISA_BUSMAS_SL2 = %X'2'; literal EISA$M_PIC_EISA_BUSMAS_SL3 = %X'4'; literal EISA$M_PIC_EISA_BUSMAS_SL4 = %X'8'; literal EISA$M_PIC_EISA_BUSMAS_SL5 = %X'10'; literal EISA$M_PIC_EISA_BUSMAS_SL6 = %X'20'; literal EISA$M_PIC_EISA_BUSMAS_SL7 = %X'40'; literal EISA$M_PIC_CTRL1_EDGE_INT3 = %X'8'; literal EISA$M_PIC_CTRL1_EDGE_INT4 = %X'10'; literal EISA$M_PIC_CTRL1_EDGE_INT5 = %X'20'; literal EISA$M_PIC_CTRL1_EDGE_INT6 = %X'40'; literal EISA$M_PIC_CTRL1_EDGE_INT7 = %X'80'; literal EISA$M_PIC_CTRL2_EDGE_INT9 = %X'2'; literal EISA$M_PIC_CTRL2_EDGE_INT10 = %X'4'; literal EISA$M_PIC_CTRL2_EDGE_INT11 = %X'8'; literal EISA$M_PIC_CTRL2_EDGE_INT12 = %X'10'; literal EISA$M_PIC_CTRL2_EDGE_INT14 = %X'40'; literal EISA$M_PIC_CTRL2_EDGE_INT15 = %X'80'; literal EISA$M_SLOT1_PID_CHAR2 = %X'3'; literal EISA$M_SLOT1_PID_CHAR1 = %X'7C'; literal EISA$M_SLOT1_PID_CHAR3 = %X'1F00'; literal EISA$M_SLOT1_PID_CHAR2_CONT = %X'E000'; literal EISA$M_SLOT1_PID_PROD_NUM1 = %X'F0000'; literal EISA$M_SLOT1_PID_PROD_NUM2 = %X'F00000'; literal EISA$M_SLOT1_PID_REV_NUM1 = %X'F000000'; literal EISA$M_SLOT1_PID_PROD_NUM3 = %X'F0000000'; literal EISA$M_SLOT2_PID_CHAR2 = %X'3'; literal EISA$M_SLOT2_PID_CHAR1 = %X'7C'; literal EISA$M_SLOT2_PID_CHAR3 = %X'1F00'; literal EISA$M_SLOT2_PID_CHAR2_CONT = %X'E000'; literal EISA$M_SLOT2_PID_PROD_NUM1 = %X'F0000'; literal EISA$M_SLOT2_PID_PROD_NUM2 = %X'F00000'; literal EISA$M_SLOT2_PID_REV_NUM1 = %X'F000000'; literal EISA$M_SLOT2_PID_PROD_NUM3 = %X'F0000000'; literal EISA$M_SLOT3_PID_CHAR2 = %X'3'; literal EISA$M_SLOT3_PID_CHAR1 = %X'7C'; literal EISA$M_SLOT3_PID_CHAR3 = %X'1F00'; literal EISA$M_SLOT3_PID_CHAR2_CONT = %X'E000'; literal EISA$M_SLOT3_PID_PROD_NUM1 = %X'F0000'; literal EISA$M_SLOT3_PID_PROD_NUM2 = %X'F00000'; literal EISA$M_SLOT3_PID_REV_NUM1 = %X'F000000'; literal EISA$M_SLOT3_PID_PROD_NUM3 = %X'F0000000'; literal EISA$M_SLOT4_PID_CHAR2 = %X'3'; literal EISA$M_SLOT4_PID_CHAR1 = %X'7C'; literal EISA$M_SLOT4_PID_CHAR3 = %X'1F00'; literal EISA$M_SLOT4_PID_CHAR2_CONT = %X'E000'; literal EISA$M_SLOT4_PID_PROD_NUM1 = %X'F0000'; literal EISA$M_SLOT4_PID_PROD_NUM2 = %X'F00000'; literal EISA$M_SLOT4_PID_REV_NUM1 = %X'F000000'; literal EISA$M_SLOT4_PID_PROD_NUM3 = %X'F0000000'; literal EISA$M_SLOT5_PID_CHAR2 = %X'3'; literal EISA$M_SLOT5_PID_CHAR1 = %X'7C'; literal EISA$M_SLOT5_PID_CHAR3 = %X'1F00'; literal EISA$M_SLOT5_PID_CHAR2_CONT = %X'E000'; literal EISA$M_SLOT5_PID_PROD_NUM1 = %X'F0000'; literal EISA$M_SLOT5_PID_PROD_NUM2 = %X'F00000'; literal EISA$M_SLOT5_PID_REV_NUM1 = %X'F000000'; literal EISA$M_SLOT5_PID_PROD_NUM3 = %X'F0000000'; literal EISA$M_SLOT6_PID_CHAR2 = %X'3'; literal EISA$M_SLOT6_PID_CHAR1 = %X'7C'; literal EISA$M_SLOT6_PID_CHAR3 = %X'1F00'; literal EISA$M_SLOT6_PID_CHAR2_CONT = %X'E000'; literal EISA$M_SLOT6_PID_PROD_NUM1 = %X'F0000'; literal EISA$M_SLOT6_PID_PROD_NUM2 = %X'F00000'; literal EISA$M_SLOT6_PID_REV_NUM1 = %X'F000000'; literal EISA$M_SLOT6_PID_PROD_NUM3 = %X'F0000000'; literal EISA$M_SLOT7_PID_CHAR2 = %X'3'; literal EISA$M_SLOT7_PID_CHAR1 = %X'7C'; literal EISA$M_SLOT7_PID_CHAR3 = %X'1F00'; literal EISA$M_SLOT7_PID_CHAR2_CONT = %X'E000'; literal EISA$M_SLOT7_PID_PROD_NUM1 = %X'F0000'; literal EISA$M_SLOT7_PID_PROD_NUM2 = %X'F00000'; literal EISA$M_SLOT7_PID_REV_NUM1 = %X'F000000'; literal EISA$M_SLOT7_PID_PROD_NUM3 = %X'F0000000'; literal EISA$M_SLOT8_PID_CHAR2 = %X'3'; literal EISA$M_SLOT8_PID_CHAR1 = %X'7C'; literal EISA$M_SLOT8_PID_CHAR3 = %X'1F00'; literal EISA$M_SLOT8_PID_CHAR2_CONT = %X'E000'; literal EISA$M_SLOT8_PID_PROD_NUM1 = %X'F0000'; literal EISA$M_SLOT8_PID_PROD_NUM2 = %X'F00000'; literal EISA$M_SLOT8_PID_REV_NUM1 = %X'F000000'; literal EISA$M_SLOT8_PID_PROD_NUM3 = %X'F0000000'; literal EISA$M_SLOT9_PID_CHAR2 = %X'3'; literal EISA$M_SLOT9_PID_CHAR1 = %X'7C'; literal EISA$M_SLOT9_PID_CHAR3 = %X'1F00'; literal EISA$M_SLOT9_PID_CHAR2_CONT = %X'E000'; literal EISA$M_SLOT9_PID_PROD_NUM1 = %X'F0000'; literal EISA$M_SLOT9_PID_PROD_NUM2 = %X'F00000'; literal EISA$M_SLOT9_PID_REV_NUM1 = %X'F000000'; literal EISA$M_SLOT9_PID_PROD_NUM3 = %X'F0000000'; literal EISA$M_SLOT10_PID_CHAR2 = %X'3'; literal EISA$M_SLOT10_PID_CHAR1 = %X'7C'; literal EISA$M_SLOT10_PID_CHAR3 = %X'1F00'; literal EISA$M_SLOT10_PID_CHAR2_CONT = %X'E000'; literal EISA$M_SLOT10_PID_PROD_NUM1 = %X'F0000'; literal EISA$M_SLOT10_PID_PROD_NUM2 = %X'F00000'; literal EISA$M_SLOT10_PID_REV_NUM1 = %X'F000000'; literal EISA$M_SLOT10_PID_PROD_NUM3 = %X'F0000000'; literal EISA$M_SLOT11_PID_CHAR2 = %X'3'; literal EISA$M_SLOT11_PID_CHAR1 = %X'7C'; literal EISA$M_SLOT11_PID_CHAR3 = %X'1F00'; literal EISA$M_SLOT11_PID_CHAR2_CONT = %X'E000'; literal EISA$M_SLOT11_PID_PROD_NUM1 = %X'F0000'; literal EISA$M_SLOT11_PID_PROD_NUM2 = %X'F00000'; literal EISA$M_SLOT11_PID_REV_NUM1 = %X'F000000'; literal EISA$M_SLOT11_PID_PROD_NUM3 = %X'F0000000'; literal EISA$M_SLOT12_PID_CHAR2 = %X'3'; literal EISA$M_SLOT12_PID_CHAR1 = %X'7C'; literal EISA$M_SLOT12_PID_CHAR3 = %X'1F00'; literal EISA$M_SLOT12_PID_CHAR2_CONT = %X'E000'; literal EISA$M_SLOT12_PID_PROD_NUM1 = %X'F0000'; literal EISA$M_SLOT12_PID_PROD_NUM2 = %X'F00000'; literal EISA$M_SLOT12_PID_REV_NUM1 = %X'F000000'; literal EISA$M_SLOT12_PID_PROD_NUM3 = %X'F0000000'; literal EISA$M_SLOT13_PID_CHAR2 = %X'3'; literal EISA$M_SLOT13_PID_CHAR1 = %X'7C'; literal EISA$M_SLOT13_PID_CHAR3 = %X'1F00'; literal EISA$M_SLOT13_PID_CHAR2_CONT = %X'E000'; literal EISA$M_SLOT13_PID_PROD_NUM1 = %X'F0000'; literal EISA$M_SLOT13_PID_PROD_NUM2 = %X'F00000'; literal EISA$M_SLOT13_PID_REV_NUM1 = %X'F000000'; literal EISA$M_SLOT13_PID_PROD_NUM3 = %X'F0000000'; literal EISA$M_SLOT14_PID_CHAR2 = %X'3'; literal EISA$M_SLOT14_PID_CHAR1 = %X'7C'; literal EISA$M_SLOT14_PID_CHAR3 = %X'1F00'; literal EISA$M_SLOT14_PID_CHAR2_CONT = %X'E000'; literal EISA$M_SLOT14_PID_PROD_NUM1 = %X'F0000'; literal EISA$M_SLOT14_PID_PROD_NUM2 = %X'F00000'; literal EISA$M_SLOT14_PID_REV_NUM1 = %X'F000000'; literal EISA$M_SLOT14_PID_PROD_NUM3 = %X'F0000000'; literal EISA$M_SLOT15_PID_CHAR2 = %X'3'; literal EISA$M_SLOT15_PID_CHAR1 = %X'7C'; literal EISA$M_SLOT15_PID_CHAR3 = %X'1F00'; literal EISA$M_SLOT15_PID_CHAR2_CONT = %X'E000'; literal EISA$M_SLOT15_PID_PROD_NUM1 = %X'F0000'; literal EISA$M_SLOT15_PID_PROD_NUM2 = %X'F00000'; literal EISA$M_SLOT15_PID_REV_NUM1 = %X'F000000'; literal EISA$M_SLOT15_PID_PROD_NUM3 = %X'F0000000'; literal EISA$k_NODE_SPACE_LENGTH = 131072; literal EISA$S_EISABUSDEF = 131072; ! Old size name - synonym literal EISA$S_EISABUS = 131072; macro EISA$B_DMA1_CH0_BASE_ADDR = 0,0,8,0 %; macro EISA$B_DMA1_CH0_BASE_CNT = 1,0,8,0 %; macro EISA$B_DMA1_CH1_BASE_ADDR = 2,0,8,0 %; macro EISA$B_DMA1_CH1_BASE_CNT = 3,0,8,0 %; macro EISA$B_DMA1_CH2_BASE_ADDR = 4,0,8,0 %; macro EISA$B_DMA1_CH2_BASE_CNT = 5,0,8,0 %; macro EISA$B_DMA1_CH3_BASE_ADDR = 6,0,8,0 %; macro EISA$B_DMA1_CH3_BASE_CNT = 7,0,8,0 %; macro EISA$B_DMA1_STAT_CMD = 8,0,8,0 %; macro EISA$B_DMA1_WRREQ = 9,0,8,0 %; macro EISA$B_DMA1_WRMASK = 10,0,8,0 %; macro EISA$B_DMA1_WRMODE = 11,0,8,0 %; macro EISA$B_DMA1_CLRBYT = 12,0,8,0 %; macro EISA$B_DMA1_MASTER_CLR = 13,0,8,0 %; macro EISA$B_DMA1_CLR_MASK = 14,0,8,0 %; macro EISA$B_DMA1_MASK_REG = 15,0,8,0 %; macro EISA$b_fill4 = 16,0,0,1 %; literal EISA$s_fill4 = 16; macro EISA$B_PIC_L_ICW1 = 32,0,8,0 %; macro EISA$V_PIC_L_ICW1_ICW4 = 32,0,1,0 %; macro EISA$V_PIC_L_ICW1_SNGL = 32,1,1,0 %; macro EISA$V_PIC_L_OCW2_L0 = 32,0,1,0 %; macro EISA$V_PIC_L_OCW2_L1 = 32,1,1,0 %; macro EISA$V_PIC_L_OCW2_L2 = 32,2,1,0 %; macro EISA$V_PIC_L_OCW2_EOI = 32,5,1,0 %; macro EISA$V_PIC_L_OCW2_SL = 32,6,1,0 %; macro EISA$V_PIC_L_OCW2_R = 32,7,1,0 %; macro EISA$V_PIC_L_OCW3_RIS = 32,0,1,0 %; macro EISA$V_PIC_L_OCW3_RR = 32,1,1,0 %; macro EISA$V_PIC_L_OCW3_P = 32,2,1,0 %; macro EISA$V_PIC_L_OCW3_SMM = 32,5,1,0 %; macro EISA$V_PIC_L_OCW3_ESMM = 32,6,1,0 %; macro EISA$B_PIC_L_ICW2 = 33,0,8,0 %; macro EISA$V_PIC_L_ICW2_ZEROES = 33,0,3,0 %; literal EISA$S_PIC_L_ICW2_ZEROES = 3; macro EISA$V_PIC_L_ICW2_VEC = 33,3,5,0 %; literal EISA$S_PIC_L_ICW2_VEC = 5; macro EISA$V_PIC_L_ICW3_IRQ0_SLAVE = 33,0,1,0 %; macro EISA$V_PIC_L_ICW3_IRQ1_SLAVE = 33,1,1,0 %; macro EISA$V_PIC_L_ICW3_IRQ2_SLAVE = 33,2,1,0 %; macro EISA$V_PIC_L_ICW3_IRQ3_SLAVE = 33,3,1,0 %; macro EISA$V_PIC_L_ICW3_IRQ4_SLAVE = 33,4,1,0 %; macro EISA$V_PIC_L_ICW3_IRQ5_SLAVE = 33,5,1,0 %; macro EISA$V_PIC_L_ICW3_IRQ6_SLAVE = 33,6,1,0 %; macro EISA$V_PIC_L_ICW3_IRQ7_SLAVE = 33,7,1,0 %; macro EISA$V_PIC_L_ICW4_MODE = 33,0,1,0 %; macro EISA$V_PIC_L_ICW4_AEOI = 33,1,1,0 %; macro EISA$V_PIC_L_ICW4_BUFF = 33,3,2,0 %; literal EISA$S_PIC_L_ICW4_BUFF = 2; macro EISA$V_PIC_L_ICW4_NEST = 33,5,1,0 %; macro EISA$V_PIC_L_OCW1_MASK = 33,0,8,0 %; literal EISA$S_PIC_L_OCW1_MASK = 8; macro EISA$b_fill5 = 35,0,0,1 %; literal EISA$s_fill5 = 29; macro EISA$B_PIC_L_T1_SYSTIM = 64,0,8,0 %; macro EISA$V_PIC_L_T1_SYSTIM_BCD = 64,0,1,0 %; macro EISA$V_PIC_L_T1_SYSTIM_MODE = 64,1,3,0 %; literal EISA$S_PIC_L_T1_SYSTIM_MODE = 3; macro EISA$V_PIC_L_T1_SYSTIM_RW = 64,4,2,0 %; literal EISA$S_PIC_L_T1_SYSTIM_RW = 2; macro EISA$V_PIC_L_T1_SYSTIM_STAT = 64,6,1,0 %; macro EISA$V_PIC_L_T1_SYSTIM_OUT = 64,7,1,0 %; macro EISA$B_PIC_L_T1_REF = 65,0,8,0 %; macro EISA$V_PIC_L_T1_REF_BCD = 65,0,1,0 %; macro EISA$V_PIC_L_T1_REF_MODE = 65,1,3,0 %; literal EISA$S_PIC_L_T1_REF_MODE = 3; macro EISA$V_PIC_L_T1_REF_RW = 65,4,2,0 %; literal EISA$S_PIC_L_T1_REF_RW = 2; macro EISA$V_PIC_L_T1_REF_STAT = 65,6,1,0 %; macro EISA$V_PIC_L_T1_REF_OUT = 65,7,1,0 %; macro EISA$B_PIC_L_T1_SPKR = 66,0,8,0 %; macro EISA$V_PIC_L_T1_SPKR_BCD = 66,0,1,0 %; macro EISA$V_PIC_L_T1_SPKR_MODE = 66,1,3,0 %; literal EISA$S_PIC_L_T1_SPKR_MODE = 3; macro EISA$V_PIC_L_T1_SPKR_RW = 66,4,2,0 %; literal EISA$S_PIC_L_T1_SPKR_RW = 2; macro EISA$V_PIC_L_T1_SPKR_STAT = 66,6,1,0 %; macro EISA$V_PIC_L_T1_SPKR_OUT = 66,7,1,0 %; macro EISA$B_PIC_L_T1_CTRL = 67,0,8,0 %; macro EISA$V_PIC_L_T1_CTRL_BCD = 67,0,1,0 %; macro EISA$V_PIC_L_T1_CTRL_MODE = 67,1,3,0 %; literal EISA$S_PIC_L_T1_CTRL_MODE = 3; macro EISA$V_PIC_L_T1_CTRL_CNTLAT = 67,4,2,0 %; literal EISA$S_PIC_L_T1_CTRL_CNTLAT = 2; macro EISA$V_PIC_L_T1_CTRL_CNTSEL = 67,6,2,0 %; literal EISA$S_PIC_L_T1_CTRL_CNTSEL = 2; macro EISA$b_fill6 = 68,0,32,1 %; literal EISA$s_fill6 = 4; macro EISA$B_PIC_L_T2_FLSF = 72,0,8,0 %; macro EISA$V_PIC_L_T2_FLSF_BCD = 72,0,1,0 %; macro EISA$V_PIC_L_T2_FLSF_MODE = 72,1,3,0 %; literal EISA$S_PIC_L_T2_FLSF_MODE = 3; macro EISA$V_PIC_L_T2_FLSF_RW = 72,4,2,0 %; literal EISA$S_PIC_L_T2_FLSF_RW = 2; macro EISA$V_PIC_L_T2_FLSF_STAT = 72,6,1,0 %; macro EISA$V_PIC_L_T2_FLSF_OUT = 72,7,1,0 %; macro EISA$b_fill7 = 73,0,8,1 %; literal EISA$s_fill7 = 1; macro EISA$B_PIC_L_T2_CPUSPD = 74,0,8,0 %; macro EISA$V_PIC_L_T2_CPUSPD_BCD = 74,0,1,0 %; macro EISA$V_PIC_L_T2_CPUSPD_MODE = 74,1,3,0 %; literal EISA$S_PIC_L_T2_CPUSPD_MODE = 3; macro EISA$V_PIC_L_T2_CPUSPD_RW = 74,4,2,0 %; literal EISA$S_PIC_L_T2_CPUSPD_RW = 2; macro EISA$V_PIC_L_T2_CPUSPD_STAT = 74,6,1,0 %; macro EISA$V_PIC_L_T2_CPUSPD_OUT = 74,7,1,0 %; macro EISA$B_PIC_L_T2_CTRL = 75,0,8,0 %; macro EISA$V_PIC_L_T2_CTRL_BCD = 75,0,1,0 %; macro EISA$V_PIC_L_T2_CTRL_MODE = 75,1,3,0 %; literal EISA$S_PIC_L_T2_CTRL_MODE = 3; macro EISA$V_PIC_L_T2_CTRL_CNTLAT = 75,4,2,0 %; literal EISA$S_PIC_L_T2_CTRL_CNTLAT = 2; macro EISA$V_PIC_L_T2_CTRL_CNTSEL = 75,6,2,0 %; literal EISA$S_PIC_L_T2_CTRL_CNTSEL = 2; macro EISA$b_fill8 = 76,0,0,1 %; literal EISA$s_fill8 = 21; macro EISA$B_PIC_L_NMICSR = 97,0,8,0 %; macro EISA$V_PIC_L_NMICSR_T1 = 97,0,1,0 %; macro EISA$V_PIC_L_NMICSR_SPKR = 97,1,1,0 %; macro EISA$V_PIC_L_NMICSR_PE = 97,2,1,0 %; macro EISA$V_PIC_L_NMICSR_IOCHK = 97,3,1,0 %; macro EISA$V_PIC_L_NMICSR_REF = 97,4,1,0 %; macro EISA$V_PIC_L_NMICSR_INTM1 = 97,5,1,0 %; macro EISA$V_PIC_L_NMICSR_NMIINT = 97,6,1,0 %; macro EISA$V_PIC_L_NMICSR_PAR = 97,7,1,0 %; macro EISA$b_fill9 = 98,0,0,1 %; literal EISA$s_fill9 = 14; macro EISA$B_PIC_L_NMIRTC = 112,0,8,0 %; macro EISA$V_PIC_L_NMIRTC_CLKADR = 112,0,7,0 %; literal EISA$S_PIC_L_NMIRTC_CLKADR = 7; macro EISA$V_PIC_L_NMIRTC_ENDIS = 112,7,1,0 %; macro EISA$b_fill10 = 113,0,0,1 %; literal EISA$s_fill10 = 16; macro EISA$B_DMA_PAGE_CH2 = 129,0,8,0 %; macro EISA$B_DMA_PAGE_CH3 = 130,0,8,0 %; macro EISA$B_DMA_PAGE_CH1 = 131,0,8,0 %; macro EISA$b_fill10a = 132,0,24,1 %; literal EISA$s_fill10a = 3; macro EISA$B_DMA_PAGE_CH0 = 135,0,8,0 %; macro EISA$b_fill10b = 136,0,8,1 %; literal EISA$s_fill10b = 1; macro EISA$B_DMA_PAGE_CH6 = 137,0,8,0 %; macro EISA$B_DMA_PAGE_CH7 = 138,0,8,0 %; macro EISA$B_DMA_PAGE_CH5 = 139,0,8,0 %; macro EISA$b_fill10c = 140,0,24,1 %; literal EISA$s_fill10c = 3; macro EISA$B_DMA_PAGE_REF = 143,0,8,0 %; macro EISA$b_fill10d = 144,0,0,1 %; literal EISA$s_fill10d = 16; macro EISA$B_PIC_H_ICW1 = 160,0,8,0 %; macro EISA$V_PIC_H_ICW1_ICW4 = 160,0,1,0 %; macro EISA$V_PIC_H_ICW1_SNGL = 160,1,1,0 %; macro EISA$V_PIC_H_OCW2_L0 = 160,0,1,0 %; macro EISA$V_PIC_H_OCW2_L1 = 160,1,1,0 %; macro EISA$V_PIC_H_OCW2_L2 = 160,2,1,0 %; macro EISA$V_PIC_H_OCW2_EOI = 160,5,1,0 %; macro EISA$V_PIC_H_OCW2_SL = 160,6,1,0 %; macro EISA$V_PIC_H_OCW2_R = 160,7,1,0 %; macro EISA$V_PIC_H_OCW3_RIS = 160,0,1,0 %; macro EISA$V_PIC_H_OCW3_RR = 160,1,1,0 %; macro EISA$V_PIC_H_OCW3_P = 160,2,1,0 %; macro EISA$V_PIC_H_OCW3_SMM = 160,5,1,0 %; macro EISA$V_PIC_H_OCW3_ESMM = 160,6,1,0 %; macro EISA$B_PIC_H_ICW2 = 161,0,8,0 %; macro EISA$V_PIC_H_ICW2_ZEROES = 161,0,3,0 %; literal EISA$S_PIC_H_ICW2_ZEROES = 3; macro EISA$V_PIC_H_ICW2_VEC = 161,3,5,0 %; literal EISA$S_PIC_H_ICW2_VEC = 5; macro EISA$V_PIC_H_ICW3_IRQ0_SLAVE = 161,0,1,0 %; macro EISA$V_PIC_H_ICW3_IRQ1_SLAVE = 161,1,1,0 %; macro EISA$V_PIC_H_ICW3_IRQ2_SLAVE = 161,2,1,0 %; macro EISA$V_PIC_H_ICW3_IRQ3_SLAVE = 161,3,1,0 %; macro EISA$V_PIC_H_ICW3_IRQ4_SLAVE = 161,4,1,0 %; macro EISA$V_PIC_H_ICW3_IRQ5_SLAVE = 161,5,1,0 %; macro EISA$V_PIC_H_ICW3_IRQ6_SLAVE = 161,6,1,0 %; macro EISA$V_PIC_H_ICW3_IRQ7_SLAVE = 161,7,1,0 %; macro EISA$V_PIC_H_ICW4_MODE = 161,0,1,0 %; macro EISA$V_PIC_H_ICW4_AEOI = 161,1,1,0 %; macro EISA$V_PIC_H_ICW4_BUFF = 161,3,2,0 %; literal EISA$S_PIC_H_ICW4_BUFF = 2; macro EISA$V_PIC_H_ICW4_NEST = 161,5,1,0 %; macro EISA$V_PIC_H_OCW1_MASK = 161,0,8,0 %; literal EISA$S_PIC_H_OCW1_MASK = 8; macro EISA$b_fill10e = 162,0,0,1 %; literal EISA$s_fill10e = 30; macro EISA$B_DMA2_CH0_BASE_ADDR = 192,0,8,0 %; macro EISA$b_fill010 = 193,0,8,1 %; literal EISA$s_fill010 = 1; macro EISA$B_DMA2_CH0_BASE_CNT = 194,0,8,0 %; macro EISA$b_fill010a = 195,0,8,1 %; literal EISA$s_fill010a = 1; macro EISA$B_DMA2_CH1_BASE_ADDR = 196,0,8,0 %; macro EISA$b_fill010b = 197,0,8,1 %; literal EISA$s_fill010b = 1; macro EISA$B_DMA2_CH1_BASE_CNT = 198,0,8,0 %; macro EISA$b_fill110 = 199,0,8,1 %; literal EISA$s_fill110 = 1; macro EISA$B_DMA2_CH2_BASE_ADDR = 200,0,8,0 %; macro EISA$b_fill210 = 201,0,8,1 %; literal EISA$s_fill210 = 1; macro EISA$B_DMA2_CH2_BASE_CNT = 202,0,8,0 %; macro EISA$b_fill210a = 203,0,8,1 %; literal EISA$s_fill210a = 1; macro EISA$B_DMA2_CH3_BASE_ADDR = 204,0,8,0 %; macro EISA$b_fill310 = 205,0,8,1 %; literal EISA$s_fill310 = 1; macro EISA$B_DMA2_CH3_BASE_CNT = 206,0,8,0 %; macro EISA$b_fill310a = 207,0,8,1 %; literal EISA$s_fill310a = 1; macro EISA$B_DMA2_STAT_WR = 208,0,8,0 %; macro EISA$b_fill410 = 209,0,8,1 %; literal EISA$s_fill410 = 1; macro EISA$B_DMA2_WR_REQ = 210,0,8,0 %; macro EISA$b_fill410a = 211,0,8,1 %; literal EISA$s_fill410a = 1; macro EISA$B_DMA2_SMASK = 212,0,8,0 %; macro EISA$b_fill410b = 213,0,8,1 %; literal EISA$s_fill410b = 1; macro EISA$B_DMA2_WRMODE = 214,0,8,0 %; macro EISA$b_fill510 = 215,0,8,1 %; literal EISA$s_fill510 = 1; macro EISA$B_DMA2_CLRBYT = 216,0,8,0 %; macro EISA$b_fill610 = 217,0,8,1 %; literal EISA$s_fill610 = 1; macro EISA$B_DMA2_MASTER_CLR = 218,0,8,0 %; macro EISA$b_fill710 = 219,0,8,1 %; literal EISA$s_fill710 = 1; macro EISA$B_DMA2_CLR_MASK = 220,0,8,0 %; macro EISA$b_fill810 = 221,0,8,1 %; literal EISA$s_fill810 = 1; macro EISA$B_DMA2_MASK_REG = 222,0,8,0 %; macro EISA$b_fill910 = 223,0,0,1 %; literal EISA$s_fill910 = 802; macro EISA$B_DMA1_CH0_CNT = 1025,0,8,0 %; macro EISA$b_fillabc = 1026,0,8,1 %; literal EISA$s_fillabc = 1; macro EISA$B_DMA1_CH1_CNT = 1027,0,8,0 %; macro EISA$b_fillabc1 = 1028,0,8,1 %; literal EISA$s_fillabc1 = 1; macro EISA$B_DMA1_CH2_CNT = 1029,0,8,0 %; macro EISA$b_fillabc2 = 1030,0,8,1 %; literal EISA$s_fillabc2 = 1; macro EISA$B_DMA1_CH3_CNT = 1031,0,8,0 %; macro EISA$b_fillabc21 = 1032,0,16,1 %; literal EISA$s_fillabc21 = 2; macro EISA$B_DMA1_CHN_MODE = 1034,0,8,0 %; macro EISA$B_DMA1_WRT_MODE = 1035,0,8,0 %; macro EISA$B_DMA1_BUF_CTRL = 1036,0,8,0 %; macro EISA$B_DMA1_STP_LVL = 1037,0,8,0 %; macro EISA$b_fillabc3 = 1038,0,0,1 %; literal EISA$s_fillabc3 = 83; macro EISA$B_PIC_EXNMICSR = 1121,0,8,0 %; macro EISA$V_PIC_EXNMICSR_BUSRST = 1121,0,1,0 %; macro EISA$V_PIC_EXNMICSR_ENIO = 1121,1,1,0 %; macro EISA$V_PIC_EXNMICSR_FSEN = 1121,2,1,0 %; macro EISA$V_PIC_EXNMICSR_TOEN = 1121,3,1,0 %; macro EISA$V_PIC_EXNMICSR_IOP = 1121,5,1,0 %; macro EISA$V_PIC_EXNMICSR_BT = 1121,6,1,0 %; macro EISA$V_PIC_EXNMICSR_FSINT = 1121,7,1,0 %; macro EISA$B_PIC_NMIGEN = 1122,0,8,0 %; macro EISA$b_fill11 = 1123,0,8,1 %; literal EISA$s_fill11 = 1; macro EISA$B_PIC_EISA_BUSMAS = 1124,0,8,0 %; macro EISA$V_PIC_EISA_BUSMAS_SL1 = 1124,0,1,0 %; macro EISA$V_PIC_EISA_BUSMAS_SL2 = 1124,1,1,0 %; macro EISA$V_PIC_EISA_BUSMAS_SL3 = 1124,2,1,0 %; macro EISA$V_PIC_EISA_BUSMAS_SL4 = 1124,3,1,0 %; macro EISA$V_PIC_EISA_BUSMAS_SL5 = 1124,4,1,0 %; macro EISA$V_PIC_EISA_BUSMAS_SL6 = 1124,5,1,0 %; macro EISA$V_PIC_EISA_BUSMAS_SL7 = 1124,6,1,0 %; macro EISA$b_fill12 = 1125,0,0,1 %; literal EISA$s_fill12 = 28; macro EISA$B_DMA_CH2_PAGE_HIGH = 1153,0,8,0 %; macro EISA$B_DMA_CH3_PAGE_HIGH = 1154,0,8,0 %; macro EISA$B_DMA_CH1_PAGE_HIGH = 1155,0,8,0 %; macro EISA$b_fill12a = 1156,0,24,1 %; literal EISA$s_fill12a = 3; macro EISA$B_DMA_CH0_PAGE_HIGH = 1159,0,8,0 %; macro EISA$b_fill12b = 1160,0,8,1 %; literal EISA$s_fill12b = 1; macro EISA$B_DMA_CH6_PAGE_HIGH = 1161,0,8,0 %; macro EISA$B_DMA_CH7_PAGE_HIGH = 1162,0,8,0 %; macro EISA$B_DMA_CH5_PAGE_HIGH = 1163,0,8,0 %; macro EISA$b_fill12c = 1164,0,24,1 %; literal EISA$s_fill12c = 3; macro EISA$B_DMA_REG_REF_HIGH = 1167,0,8,0 %; macro EISA$b_fill12d = 1168,0,0,1 %; literal EISA$s_fill12d = 54; macro EISA$B_DMA2_CH5_CNT = 1222,0,8,0 %; macro EISA$b_fill12e = 1223,0,24,1 %; literal EISA$s_fill12e = 3; macro EISA$B_DMA2_CH6_CNT = 1226,0,8,0 %; macro EISA$b_fill12e1 = 1227,0,24,1 %; literal EISA$s_fill12e1 = 3; macro EISA$B_DMA2_CH7_CNT = 1230,0,8,0 %; macro EISA$b_fill12f = 1231,0,8,1 %; literal EISA$s_fill12f = 1; macro EISA$B_PIC_CTRL1_EDGE = 1232,0,8,0 %; macro EISA$V_PIC_CTRL1_EDGE_INT3 = 1232,3,1,0 %; macro EISA$V_PIC_CTRL1_EDGE_INT4 = 1232,4,1,0 %; macro EISA$V_PIC_CTRL1_EDGE_INT5 = 1232,5,1,0 %; macro EISA$V_PIC_CTRL1_EDGE_INT6 = 1232,6,1,0 %; macro EISA$V_PIC_CTRL1_EDGE_INT7 = 1232,7,1,0 %; macro EISA$B_PIC_CTRL2_EDGE = 1233,0,8,0 %; macro EISA$V_PIC_CTRL2_EDGE_INT9 = 1233,1,1,0 %; macro EISA$V_PIC_CTRL2_EDGE_INT10 = 1233,2,1,0 %; macro EISA$V_PIC_CTRL2_EDGE_INT11 = 1233,3,1,0 %; macro EISA$V_PIC_CTRL2_EDGE_INT12 = 1233,4,1,0 %; macro EISA$V_PIC_CTRL2_EDGE_INT14 = 1233,6,1,0 %; macro EISA$V_PIC_CTRL2_EDGE_INT15 = 1233,7,1,0 %; macro EISA$b_fill13 = 1234,0,16,1 %; literal EISA$s_fill13 = 2; macro EISA$B_DMA2_CHN_MODE = 1236,0,8,0 %; macro EISA$b_fill13a = 1237,0,8,1 %; literal EISA$s_fill13a = 1; macro EISA$B_DMA2_WRT_MODE = 1238,0,8,0 %; macro EISA$b_fill13b = 1239,0,0,1 %; literal EISA$s_fill13b = 9; macro EISA$B_DMA_CH0_SRB7_2 = 1248,0,8,0 %; macro EISA$B_DMA_CH0_SRB15_8 = 1249,0,8,0 %; macro EISA$B_DMA_CH0_SRB23_16 = 1250,0,8,0 %; macro EISA$b_fill13c = 1251,0,8,1 %; literal EISA$s_fill13c = 1; macro EISA$B_DMA_CH1_SRB7_2 = 1252,0,8,0 %; macro EISA$B_DMA_CH1_SRB15_8 = 1253,0,8,0 %; macro EISA$B_DMA_CH1_SRB23_16 = 1254,0,8,0 %; macro EISA$b_fill13d = 1255,0,8,1 %; literal EISA$s_fill13d = 1; macro EISA$B_DMA_CH2_SRB7_2 = 1256,0,8,0 %; macro EISA$B_DMA_CH2_SRB15_8 = 1257,0,8,0 %; macro EISA$B_DMA_CH2_SRB23_16 = 1258,0,8,0 %; macro EISA$b_fill13e = 1259,0,8,1 %; literal EISA$s_fill13e = 1; macro EISA$B_DMA_CH3_SRB7_2 = 1260,0,8,0 %; macro EISA$B_DMA_CH3_SRB15_8 = 1261,0,8,0 %; macro EISA$B_DMA_CH3_SRB23_16 = 1262,0,8,0 %; macro EISA$b_fill13f = 1263,0,0,1 %; literal EISA$s_fill13f = 5; macro EISA$B_DMA_CH5_SRB7_2 = 1268,0,8,0 %; macro EISA$B_DMA_CH5_SRB15_8 = 1269,0,8,0 %; macro EISA$B_DMA_CH5_SRB23_16 = 1270,0,8,0 %; macro EISA$b_fill13f1 = 1271,0,8,1 %; literal EISA$s_fill13f1 = 1; macro EISA$B_DMA_CH6_SRB7_2 = 1272,0,8,0 %; macro EISA$B_DMA_CH6_SRB15_8 = 1273,0,8,0 %; macro EISA$B_DMA_CH6_SRB23_16 = 1274,0,8,0 %; macro EISA$b_fill13f2 = 1275,0,8,1 %; literal EISA$s_fill13f2 = 1; macro EISA$B_DMA_CH7_SRB7_2 = 1276,0,8,0 %; macro EISA$B_DMA_CH7_SRB15_8 = 1277,0,8,0 %; macro EISA$B_DMA_CH7_SRB23_16 = 1278,0,8,0 %; macro EISA$b_fill13g = 1279,0,0,1 %; literal EISA$s_fill13g = 6913; macro EISA$B_SLOT1_BASE = 8192,0,8,0 %; macro EISA$b_fill14 = 8193,0,0,1 %; literal EISA$s_fill14 = 3199; macro EISA$L_SLOT1_PID = 11392,0,32,0 %; macro EISA$V_SLOT1_PID_CHAR2 = 11392,0,2,0 %; literal EISA$S_SLOT1_PID_CHAR2 = 2; macro EISA$V_SLOT1_PID_CHAR1 = 11392,2,5,0 %; literal EISA$S_SLOT1_PID_CHAR1 = 5; macro EISA$V_SLOT1_PID_CHAR3 = 11392,8,5,0 %; literal EISA$S_SLOT1_PID_CHAR3 = 5; macro EISA$V_SLOT1_PID_CHAR2_CONT = 11392,13,3,0 %; literal EISA$S_SLOT1_PID_CHAR2_CONT = 3; macro EISA$V_SLOT1_PID_PROD_NUM1 = 11392,16,4,0 %; literal EISA$S_SLOT1_PID_PROD_NUM1 = 4; macro EISA$V_SLOT1_PID_PROD_NUM2 = 11392,20,4,0 %; literal EISA$S_SLOT1_PID_PROD_NUM2 = 4; macro EISA$V_SLOT1_PID_REV_NUM1 = 11392,24,4,0 %; literal EISA$S_SLOT1_PID_REV_NUM1 = 4; macro EISA$V_SLOT1_PID_PROD_NUM3 = 11392,28,4,0 %; literal EISA$S_SLOT1_PID_PROD_NUM3 = 4; macro EISA$b_fill14a = 11396,0,0,1 %; literal EISA$s_fill14a = 4988; macro EISA$B_SLOT2_BASE = 16384,0,8,0 %; macro EISA$b_fill15 = 16385,0,0,1 %; literal EISA$s_fill15 = 3199; macro EISA$L_SLOT2_PID = 19584,0,32,0 %; macro EISA$V_SLOT2_PID_CHAR2 = 19584,0,2,0 %; literal EISA$S_SLOT2_PID_CHAR2 = 2; macro EISA$V_SLOT2_PID_CHAR1 = 19584,2,5,0 %; literal EISA$S_SLOT2_PID_CHAR1 = 5; macro EISA$V_SLOT2_PID_CHAR3 = 19584,8,5,0 %; literal EISA$S_SLOT2_PID_CHAR3 = 5; macro EISA$V_SLOT2_PID_CHAR2_CONT = 19584,13,3,0 %; literal EISA$S_SLOT2_PID_CHAR2_CONT = 3; macro EISA$V_SLOT2_PID_PROD_NUM1 = 19584,16,4,0 %; literal EISA$S_SLOT2_PID_PROD_NUM1 = 4; macro EISA$V_SLOT2_PID_PROD_NUM2 = 19584,20,4,0 %; literal EISA$S_SLOT2_PID_PROD_NUM2 = 4; macro EISA$V_SLOT2_PID_REV_NUM1 = 19584,24,4,0 %; literal EISA$S_SLOT2_PID_REV_NUM1 = 4; macro EISA$V_SLOT2_PID_PROD_NUM3 = 19584,28,4,0 %; literal EISA$S_SLOT2_PID_PROD_NUM3 = 4; macro EISA$b_fill15a = 19588,0,0,1 %; literal EISA$s_fill15a = 4988; macro EISA$B_SLOT3_BASE = 24576,0,8,0 %; macro EISA$b_fill16 = 24577,0,0,1 %; literal EISA$s_fill16 = 3199; macro EISA$L_SLOT3_PID = 27776,0,32,0 %; macro EISA$V_SLOT3_PID_CHAR2 = 27776,0,2,0 %; literal EISA$S_SLOT3_PID_CHAR2 = 2; macro EISA$V_SLOT3_PID_CHAR1 = 27776,2,5,0 %; literal EISA$S_SLOT3_PID_CHAR1 = 5; macro EISA$V_SLOT3_PID_CHAR3 = 27776,8,5,0 %; literal EISA$S_SLOT3_PID_CHAR3 = 5; macro EISA$V_SLOT3_PID_CHAR2_CONT = 27776,13,3,0 %; literal EISA$S_SLOT3_PID_CHAR2_CONT = 3; macro EISA$V_SLOT3_PID_PROD_NUM1 = 27776,16,4,0 %; literal EISA$S_SLOT3_PID_PROD_NUM1 = 4; macro EISA$V_SLOT3_PID_PROD_NUM2 = 27776,20,4,0 %; literal EISA$S_SLOT3_PID_PROD_NUM2 = 4; macro EISA$V_SLOT3_PID_REV_NUM1 = 27776,24,4,0 %; literal EISA$S_SLOT3_PID_REV_NUM1 = 4; macro EISA$V_SLOT3_PID_PROD_NUM3 = 27776,28,4,0 %; literal EISA$S_SLOT3_PID_PROD_NUM3 = 4; macro EISA$b_fill16a = 27780,0,0,1 %; literal EISA$s_fill16a = 4988; macro EISA$B_SLOT4_BASE = 32768,0,8,0 %; macro EISA$b_fill17 = 32769,0,0,1 %; literal EISA$s_fill17 = 3199; macro EISA$L_SLOT4_PID = 35968,0,32,0 %; macro EISA$V_SLOT4_PID_CHAR2 = 35968,0,2,0 %; literal EISA$S_SLOT4_PID_CHAR2 = 2; macro EISA$V_SLOT4_PID_CHAR1 = 35968,2,5,0 %; literal EISA$S_SLOT4_PID_CHAR1 = 5; macro EISA$V_SLOT4_PID_CHAR3 = 35968,8,5,0 %; literal EISA$S_SLOT4_PID_CHAR3 = 5; macro EISA$V_SLOT4_PID_CHAR2_CONT = 35968,13,3,0 %; literal EISA$S_SLOT4_PID_CHAR2_CONT = 3; macro EISA$V_SLOT4_PID_PROD_NUM1 = 35968,16,4,0 %; literal EISA$S_SLOT4_PID_PROD_NUM1 = 4; macro EISA$V_SLOT4_PID_PROD_NUM2 = 35968,20,4,0 %; literal EISA$S_SLOT4_PID_PROD_NUM2 = 4; macro EISA$V_SLOT4_PID_REV_NUM1 = 35968,24,4,0 %; literal EISA$S_SLOT4_PID_REV_NUM1 = 4; macro EISA$V_SLOT4_PID_PROD_NUM3 = 35968,28,4,0 %; literal EISA$S_SLOT4_PID_PROD_NUM3 = 4; macro EISA$b_fill17a = 35972,0,0,1 %; literal EISA$s_fill17a = 4988; macro EISA$B_SLOT5_BASE = 40960,0,8,0 %; macro EISA$b_fill18 = 40961,0,0,1 %; literal EISA$s_fill18 = 3199; macro EISA$L_SLOT5_PID = 44160,0,32,0 %; macro EISA$V_SLOT5_PID_CHAR2 = 44160,0,2,0 %; literal EISA$S_SLOT5_PID_CHAR2 = 2; macro EISA$V_SLOT5_PID_CHAR1 = 44160,2,5,0 %; literal EISA$S_SLOT5_PID_CHAR1 = 5; macro EISA$V_SLOT5_PID_CHAR3 = 44160,8,5,0 %; literal EISA$S_SLOT5_PID_CHAR3 = 5; macro EISA$V_SLOT5_PID_CHAR2_CONT = 44160,13,3,0 %; literal EISA$S_SLOT5_PID_CHAR2_CONT = 3; macro EISA$V_SLOT5_PID_PROD_NUM1 = 44160,16,4,0 %; literal EISA$S_SLOT5_PID_PROD_NUM1 = 4; macro EISA$V_SLOT5_PID_PROD_NUM2 = 44160,20,4,0 %; literal EISA$S_SLOT5_PID_PROD_NUM2 = 4; macro EISA$V_SLOT5_PID_REV_NUM1 = 44160,24,4,0 %; literal EISA$S_SLOT5_PID_REV_NUM1 = 4; macro EISA$V_SLOT5_PID_PROD_NUM3 = 44160,28,4,0 %; literal EISA$S_SLOT5_PID_PROD_NUM3 = 4; macro EISA$b_fill18a = 44164,0,0,1 %; literal EISA$s_fill18a = 4988; macro EISA$B_SLOT6_BASE = 49152,0,8,0 %; macro EISA$b_fill19 = 49153,0,0,1 %; literal EISA$s_fill19 = 3199; macro EISA$L_SLOT6_PID = 52352,0,32,0 %; macro EISA$V_SLOT6_PID_CHAR2 = 52352,0,2,0 %; literal EISA$S_SLOT6_PID_CHAR2 = 2; macro EISA$V_SLOT6_PID_CHAR1 = 52352,2,5,0 %; literal EISA$S_SLOT6_PID_CHAR1 = 5; macro EISA$V_SLOT6_PID_CHAR3 = 52352,8,5,0 %; literal EISA$S_SLOT6_PID_CHAR3 = 5; macro EISA$V_SLOT6_PID_CHAR2_CONT = 52352,13,3,0 %; literal EISA$S_SLOT6_PID_CHAR2_CONT = 3; macro EISA$V_SLOT6_PID_PROD_NUM1 = 52352,16,4,0 %; literal EISA$S_SLOT6_PID_PROD_NUM1 = 4; macro EISA$V_SLOT6_PID_PROD_NUM2 = 52352,20,4,0 %; literal EISA$S_SLOT6_PID_PROD_NUM2 = 4; macro EISA$V_SLOT6_PID_REV_NUM1 = 52352,24,4,0 %; literal EISA$S_SLOT6_PID_REV_NUM1 = 4; macro EISA$V_SLOT6_PID_PROD_NUM3 = 52352,28,4,0 %; literal EISA$S_SLOT6_PID_PROD_NUM3 = 4; macro EISA$b_fill19a = 52356,0,0,1 %; literal EISA$s_fill19a = 4988; macro EISA$B_SLOT7_BASE = 57344,0,8,0 %; macro EISA$b_fill19a01 = 57345,0,0,1 %; literal EISA$s_fill19a01 = 3199; macro EISA$L_SLOT7_PID = 60544,0,32,0 %; macro EISA$V_SLOT7_PID_CHAR2 = 60544,0,2,0 %; literal EISA$S_SLOT7_PID_CHAR2 = 2; macro EISA$V_SLOT7_PID_CHAR1 = 60544,2,5,0 %; literal EISA$S_SLOT7_PID_CHAR1 = 5; macro EISA$V_SLOT7_PID_CHAR3 = 60544,8,5,0 %; literal EISA$S_SLOT7_PID_CHAR3 = 5; macro EISA$V_SLOT7_PID_CHAR2_CONT = 60544,13,3,0 %; literal EISA$S_SLOT7_PID_CHAR2_CONT = 3; macro EISA$V_SLOT7_PID_PROD_NUM1 = 60544,16,4,0 %; literal EISA$S_SLOT7_PID_PROD_NUM1 = 4; macro EISA$V_SLOT7_PID_PROD_NUM2 = 60544,20,4,0 %; literal EISA$S_SLOT7_PID_PROD_NUM2 = 4; macro EISA$V_SLOT7_PID_REV_NUM1 = 60544,24,4,0 %; literal EISA$S_SLOT7_PID_REV_NUM1 = 4; macro EISA$V_SLOT7_PID_PROD_NUM3 = 60544,28,4,0 %; literal EISA$S_SLOT7_PID_PROD_NUM3 = 4; macro EISA$b_fill19a1 = 60548,0,0,1 %; literal EISA$s_fill19a1 = 4988; macro EISA$B_SLOT8_BASE = 65536,0,8,0 %; macro EISA$b_fill19b = 65537,0,0,1 %; literal EISA$s_fill19b = 3199; macro EISA$L_SLOT8_PID = 68736,0,32,0 %; macro EISA$V_SLOT8_PID_CHAR2 = 68736,0,2,0 %; literal EISA$S_SLOT8_PID_CHAR2 = 2; macro EISA$V_SLOT8_PID_CHAR1 = 68736,2,5,0 %; literal EISA$S_SLOT8_PID_CHAR1 = 5; macro EISA$V_SLOT8_PID_CHAR3 = 68736,8,5,0 %; literal EISA$S_SLOT8_PID_CHAR3 = 5; macro EISA$V_SLOT8_PID_CHAR2_CONT = 68736,13,3,0 %; literal EISA$S_SLOT8_PID_CHAR2_CONT = 3; macro EISA$V_SLOT8_PID_PROD_NUM1 = 68736,16,4,0 %; literal EISA$S_SLOT8_PID_PROD_NUM1 = 4; macro EISA$V_SLOT8_PID_PROD_NUM2 = 68736,20,4,0 %; literal EISA$S_SLOT8_PID_PROD_NUM2 = 4; macro EISA$V_SLOT8_PID_REV_NUM1 = 68736,24,4,0 %; literal EISA$S_SLOT8_PID_REV_NUM1 = 4; macro EISA$V_SLOT8_PID_PROD_NUM3 = 68736,28,4,0 %; literal EISA$S_SLOT8_PID_PROD_NUM3 = 4; macro EISA$b_fill19b1 = 68740,0,0,1 %; literal EISA$s_fill19b1 = 4988; macro EISA$B_SLOT9_BASE = 73728,0,8,0 %; macro EISA$b_fill19c = 73729,0,0,1 %; literal EISA$s_fill19c = 3199; macro EISA$L_SLOT9_PID = 76928,0,32,0 %; macro EISA$V_SLOT9_PID_CHAR2 = 76928,0,2,0 %; literal EISA$S_SLOT9_PID_CHAR2 = 2; macro EISA$V_SLOT9_PID_CHAR1 = 76928,2,5,0 %; literal EISA$S_SLOT9_PID_CHAR1 = 5; macro EISA$V_SLOT9_PID_CHAR3 = 76928,8,5,0 %; literal EISA$S_SLOT9_PID_CHAR3 = 5; macro EISA$V_SLOT9_PID_CHAR2_CONT = 76928,13,3,0 %; literal EISA$S_SLOT9_PID_CHAR2_CONT = 3; macro EISA$V_SLOT9_PID_PROD_NUM1 = 76928,16,4,0 %; literal EISA$S_SLOT9_PID_PROD_NUM1 = 4; macro EISA$V_SLOT9_PID_PROD_NUM2 = 76928,20,4,0 %; literal EISA$S_SLOT9_PID_PROD_NUM2 = 4; macro EISA$V_SLOT9_PID_REV_NUM1 = 76928,24,4,0 %; literal EISA$S_SLOT9_PID_REV_NUM1 = 4; macro EISA$V_SLOT9_PID_PROD_NUM3 = 76928,28,4,0 %; literal EISA$S_SLOT9_PID_PROD_NUM3 = 4; macro EISA$b_fill19c1 = 76932,0,0,1 %; literal EISA$s_fill19c1 = 4988; macro EISA$B_SLOT10_BASE = 81920,0,8,0 %; macro EISA$b_fill19d = 81921,0,0,1 %; literal EISA$s_fill19d = 3199; macro EISA$L_SLOT10_PID = 85120,0,32,0 %; macro EISA$V_SLOT10_PID_CHAR2 = 85120,0,2,0 %; literal EISA$S_SLOT10_PID_CHAR2 = 2; macro EISA$V_SLOT10_PID_CHAR1 = 85120,2,5,0 %; literal EISA$S_SLOT10_PID_CHAR1 = 5; macro EISA$V_SLOT10_PID_CHAR3 = 85120,8,5,0 %; literal EISA$S_SLOT10_PID_CHAR3 = 5; macro EISA$V_SLOT10_PID_CHAR2_CONT = 85120,13,3,0 %; literal EISA$S_SLOT10_PID_CHAR2_CONT = 3; macro EISA$V_SLOT10_PID_PROD_NUM1 = 85120,16,4,0 %; literal EISA$S_SLOT10_PID_PROD_NUM1 = 4; macro EISA$V_SLOT10_PID_PROD_NUM2 = 85120,20,4,0 %; literal EISA$S_SLOT10_PID_PROD_NUM2 = 4; macro EISA$V_SLOT10_PID_REV_NUM1 = 85120,24,4,0 %; literal EISA$S_SLOT10_PID_REV_NUM1 = 4; macro EISA$V_SLOT10_PID_PROD_NUM3 = 85120,28,4,0 %; literal EISA$S_SLOT10_PID_PROD_NUM3 = 4; macro EISA$b_fill19d1 = 85124,0,0,1 %; literal EISA$s_fill19d1 = 4988; macro EISA$B_SLOT11_BASE = 90112,0,8,0 %; macro EISA$b_fill19e = 90113,0,0,1 %; literal EISA$s_fill19e = 3199; macro EISA$L_SLOT11_PID = 93312,0,32,0 %; macro EISA$V_SLOT11_PID_CHAR2 = 93312,0,2,0 %; literal EISA$S_SLOT11_PID_CHAR2 = 2; macro EISA$V_SLOT11_PID_CHAR1 = 93312,2,5,0 %; literal EISA$S_SLOT11_PID_CHAR1 = 5; macro EISA$V_SLOT11_PID_CHAR3 = 93312,8,5,0 %; literal EISA$S_SLOT11_PID_CHAR3 = 5; macro EISA$V_SLOT11_PID_CHAR2_CONT = 93312,13,3,0 %; literal EISA$S_SLOT11_PID_CHAR2_CONT = 3; macro EISA$V_SLOT11_PID_PROD_NUM1 = 93312,16,4,0 %; literal EISA$S_SLOT11_PID_PROD_NUM1 = 4; macro EISA$V_SLOT11_PID_PROD_NUM2 = 93312,20,4,0 %; literal EISA$S_SLOT11_PID_PROD_NUM2 = 4; macro EISA$V_SLOT11_PID_REV_NUM1 = 93312,24,4,0 %; literal EISA$S_SLOT11_PID_REV_NUM1 = 4; macro EISA$V_SLOT11_PID_PROD_NUM3 = 93312,28,4,0 %; literal EISA$S_SLOT11_PID_PROD_NUM3 = 4; macro EISA$b_fill19e1 = 93316,0,0,1 %; literal EISA$s_fill19e1 = 4988; macro EISA$B_SLOT12_BASE = 98304,0,8,0 %; macro EISA$b_fill19f = 98305,0,0,1 %; literal EISA$s_fill19f = 3199; macro EISA$L_SLOT12_PID = 101504,0,32,0 %; macro EISA$V_SLOT12_PID_CHAR2 = 101504,0,2,0 %; literal EISA$S_SLOT12_PID_CHAR2 = 2; macro EISA$V_SLOT12_PID_CHAR1 = 101504,2,5,0 %; literal EISA$S_SLOT12_PID_CHAR1 = 5; macro EISA$V_SLOT12_PID_CHAR3 = 101504,8,5,0 %; literal EISA$S_SLOT12_PID_CHAR3 = 5; macro EISA$V_SLOT12_PID_CHAR2_CONT = 101504,13,3,0 %; literal EISA$S_SLOT12_PID_CHAR2_CONT = 3; macro EISA$V_SLOT12_PID_PROD_NUM1 = 101504,16,4,0 %; literal EISA$S_SLOT12_PID_PROD_NUM1 = 4; macro EISA$V_SLOT12_PID_PROD_NUM2 = 101504,20,4,0 %; literal EISA$S_SLOT12_PID_PROD_NUM2 = 4; macro EISA$V_SLOT12_PID_REV_NUM1 = 101504,24,4,0 %; literal EISA$S_SLOT12_PID_REV_NUM1 = 4; macro EISA$V_SLOT12_PID_PROD_NUM3 = 101504,28,4,0 %; literal EISA$S_SLOT12_PID_PROD_NUM3 = 4; macro EISA$b_fill19f1 = 101508,0,0,1 %; literal EISA$s_fill19f1 = 4988; macro EISA$B_SLOT13_BASE = 106496,0,8,0 %; macro EISA$b_fill19aa = 106497,0,0,1 %; literal EISA$s_fill19aa = 3199; macro EISA$L_SLOT13_PID = 109696,0,32,0 %; macro EISA$V_SLOT13_PID_CHAR2 = 109696,0,2,0 %; literal EISA$S_SLOT13_PID_CHAR2 = 2; macro EISA$V_SLOT13_PID_CHAR1 = 109696,2,5,0 %; literal EISA$S_SLOT13_PID_CHAR1 = 5; macro EISA$V_SLOT13_PID_CHAR3 = 109696,8,5,0 %; literal EISA$S_SLOT13_PID_CHAR3 = 5; macro EISA$V_SLOT13_PID_CHAR2_CONT = 109696,13,3,0 %; literal EISA$S_SLOT13_PID_CHAR2_CONT = 3; macro EISA$V_SLOT13_PID_PROD_NUM1 = 109696,16,4,0 %; literal EISA$S_SLOT13_PID_PROD_NUM1 = 4; macro EISA$V_SLOT13_PID_PROD_NUM2 = 109696,20,4,0 %; literal EISA$S_SLOT13_PID_PROD_NUM2 = 4; macro EISA$V_SLOT13_PID_REV_NUM1 = 109696,24,4,0 %; literal EISA$S_SLOT13_PID_REV_NUM1 = 4; macro EISA$V_SLOT13_PID_PROD_NUM3 = 109696,28,4,0 %; literal EISA$S_SLOT13_PID_PROD_NUM3 = 4; macro EISA$b_fill19aa1 = 109700,0,0,1 %; literal EISA$s_fill19aa1 = 4988; macro EISA$B_SLOT14_BASE = 114688,0,8,0 %; macro EISA$b_fill19ab = 114689,0,0,1 %; literal EISA$s_fill19ab = 3199; macro EISA$L_SLOT14_PID = 117888,0,32,0 %; macro EISA$V_SLOT14_PID_CHAR2 = 117888,0,2,0 %; literal EISA$S_SLOT14_PID_CHAR2 = 2; macro EISA$V_SLOT14_PID_CHAR1 = 117888,2,5,0 %; literal EISA$S_SLOT14_PID_CHAR1 = 5; macro EISA$V_SLOT14_PID_CHAR3 = 117888,8,5,0 %; literal EISA$S_SLOT14_PID_CHAR3 = 5; macro EISA$V_SLOT14_PID_CHAR2_CONT = 117888,13,3,0 %; literal EISA$S_SLOT14_PID_CHAR2_CONT = 3; macro EISA$V_SLOT14_PID_PROD_NUM1 = 117888,16,4,0 %; literal EISA$S_SLOT14_PID_PROD_NUM1 = 4; macro EISA$V_SLOT14_PID_PROD_NUM2 = 117888,20,4,0 %; literal EISA$S_SLOT14_PID_PROD_NUM2 = 4; macro EISA$V_SLOT14_PID_REV_NUM1 = 117888,24,4,0 %; literal EISA$S_SLOT14_PID_REV_NUM1 = 4; macro EISA$V_SLOT14_PID_PROD_NUM3 = 117888,28,4,0 %; literal EISA$S_SLOT14_PID_PROD_NUM3 = 4; macro EISA$b_fill19ab1 = 117892,0,0,1 %; literal EISA$s_fill19ab1 = 4988; macro EISA$B_SLOT15_BASE = 122880,0,8,0 %; macro EISA$b_fill19ac = 122881,0,0,1 %; literal EISA$s_fill19ac = 3199; macro EISA$L_SLOT15_PID = 126080,0,32,0 %; macro EISA$V_SLOT15_PID_CHAR2 = 126080,0,2,0 %; literal EISA$S_SLOT15_PID_CHAR2 = 2; macro EISA$V_SLOT15_PID_CHAR1 = 126080,2,5,0 %; literal EISA$S_SLOT15_PID_CHAR1 = 5; macro EISA$V_SLOT15_PID_CHAR3 = 126080,8,5,0 %; literal EISA$S_SLOT15_PID_CHAR3 = 5; macro EISA$V_SLOT15_PID_CHAR2_CONT = 126080,13,3,0 %; literal EISA$S_SLOT15_PID_CHAR2_CONT = 3; macro EISA$V_SLOT15_PID_PROD_NUM1 = 126080,16,4,0 %; literal EISA$S_SLOT15_PID_PROD_NUM1 = 4; macro EISA$V_SLOT15_PID_PROD_NUM2 = 126080,20,4,0 %; literal EISA$S_SLOT15_PID_PROD_NUM2 = 4; macro EISA$V_SLOT15_PID_REV_NUM1 = 126080,24,4,0 %; literal EISA$S_SLOT15_PID_REV_NUM1 = 4; macro EISA$V_SLOT15_PID_PROD_NUM3 = 126080,28,4,0 %; literal EISA$S_SLOT15_PID_PROD_NUM3 = 4; macro EISA$b_fill19ac1 = 126084,0,0,1 %; literal EISA$s_fill19ac1 = 4988; ! the following constants are useful for bus probing. literal EISA$k_NODE0_BASE_CSR = 0; ! this is the system ! board slot. literal EISA$k_NODE1_BASE_CSR = 4096; ! this is slot 1 literal EISA$k_NODE2_BASE_CSR = 8192; ! this is slot 2 literal EISA$k_NODE3_BASE_CSR = 12288; ! this is slot 3 literal EISA$k_NODE4_BASE_CSR = 16384; ! this is slot 4 literal EISA$k_NODE5_BASE_CSR = 20480; ! this is slot 5 literal EISA$k_NODE6_BASE_CSR = 24576; ! this is slot 6 literal EISA$k_NODE7_BASE_CSR = 28672; ! this is slot 7 literal EISA$k_NODE8_BASE_CSR = 32768; ! this is slot 8 literal EISA$k_NODE9_BASE_CSR = 36864; ! this is slot 9 literal EISA$k_NODE10_BASE_CSR = 40960; ! this is slot 10 literal EISA$k_NODE11_BASE_CSR = 45056; ! this is slot 11 literal EISA$k_NODE12_BASE_CSR = 49152; ! this is slot 12 literal EISA$k_NODE13_BASE_CSR = 53248; ! this is slot 13 literal EISA$k_NODE14_BASE_CSR = 57344; ! this is slot 14 literal EISA$k_NODE15_BASE_CSR = 61440; ! this is slot 15 literal EISA$k_PRODUCT_ID_REG_OFFSET = 3200; ! offset from the slot base ! to the PID reg literal EISA$k_MAX_NODE_NUMBER = 15; ! max slots is 15 literal EISA$k_DIGITAL_VENDOR_ID = 524331; ! enet prefix literal EISACFGHDR$S_CONFIGDATAHEADER = 20; macro EISACFGHDR$W_VERSION = 0,0,16,0 %; macro EISACFGHDR$W_REVISION = 2,0,16,0 %; macro EISACFGHDR$L_PTYPE = 4,0,32,1 %; macro EISACFGHDR$L_PVENDOR = 8,0,32,1 %; macro EISACFGHDR$L_PNAME = 12,0,32,1 %; macro EISACFGHDR$L_PSERIAL_NUM = 16,0,32,1 %; literal EISASLOTINFO$M_CFG_REV = %X'F'; literal EISASLOTINFO$M_SLOT_TYPE = %X'30'; literal EISASLOTINFO$M_READ_ID = %X'40'; literal EISASLOTINFO$M_DUP_ID = %X'80'; literal EISASLOTINFO$M_TYPE_ENTRY = %X'1'; literal EISASLOTINFO$M_MEM_ENTRY = %X'2'; literal EISASLOTINFO$M_IRQ_ENTRY = %X'4'; literal EISASLOTINFO$M_DMA_ENTRY = %X'8'; literal EISASLOTINFO$M_PORT_RANGE_ENTRY = %X'10'; literal EISASLOTINFO$M_PORT_INIT_ENTRY = %X'20'; literal EISASLOTINFO$m_char_2_msb = %X'3'; literal EISASLOTINFO$m_char_1 = %X'7C'; literal EISASLOTINFO$m_char_3_msb = %X'1F'; literal EISASLOTINFO$m_char_2_lsb = %X'E0'; literal EISASLOTINFO$m_hex_2 = %X'F'; literal EISASLOTINFO$m_hex_1 = %X'F0'; literal EISASLOTINFO$m_hex_4 = %X'F'; literal EISASLOTINFO$m_hex_3 = %X'F0'; literal EISASLOTINFO$S_EISASLOTINFO = 11; macro EISASLOTINFO$B_SLOTID = 0,0,8,0 %; macro EISASLOTINFO$V_CFG_REV = 0,0,4,0 %; literal EISASLOTINFO$S_CFG_REV = 4; macro EISASLOTINFO$V_SLOT_TYPE = 0,4,2,0 %; literal EISASLOTINFO$S_SLOT_TYPE = 2; macro EISASLOTINFO$V_READ_ID = 0,6,1,0 %; macro EISASLOTINFO$V_DUP_ID = 0,7,1,0 %; macro EISASLOTINFO$B_MAJOR_CFG_REV = 1,0,8,0 %; macro EISASLOTINFO$B_MINOR_CFG_REV = 2,0,8,0 %; macro EISASLOTINFO$B_CFG_CHKSUM_1 = 3,0,8,0 %; macro EISASLOTINFO$B_CFG_CHKSUM_2 = 4,0,8,0 %; macro EISASLOTINFO$B_NUM_DEV_FUNC = 5,0,8,0 %; macro EISASLOTINFO$b_func_info = 6,0,8,0 %; macro EISASLOTINFO$V_TYPE_ENTRY = 6,0,1,0 %; macro EISASLOTINFO$V_MEM_ENTRY = 6,1,1,0 %; macro EISASLOTINFO$V_IRQ_ENTRY = 6,2,1,0 %; macro EISASLOTINFO$V_DMA_ENTRY = 6,3,1,0 %; macro EISASLOTINFO$V_PORT_RANGE_ENTRY = 6,4,1,0 %; macro EISASLOTINFO$V_PORT_INIT_ENTRY = 6,5,1,0 %; macro EISASLOTINFO$B_PID_byte = 7,0,8,0 %; macro EISASLOTINFO$v_char_2_msb = 7,0,2,0 %; literal EISASLOTINFO$s_char_2_msb = 2; ! bits <1:0> (2 msb's) macro EISASLOTINFO$v_char_1 = 7,2,5,0 %; literal EISASLOTINFO$s_char_1 = 5; ! bits <6:2> macro EISASLOTINFO$B_PID_byte1 = 8,0,8,0 %; macro EISASLOTINFO$v_char_3_msb = 8,0,5,0 %; literal EISASLOTINFO$s_char_3_msb = 5; ! bits <4:0> macro EISASLOTINFO$v_char_2_lsb = 8,5,3,0 %; literal EISASLOTINFO$s_char_2_lsb = 3; ! bits <7:5> macro EISASLOTINFO$B_PID_byte2 = 9,0,8,0 %; macro EISASLOTINFO$v_hex_2 = 9,0,4,0 %; literal EISASLOTINFO$s_hex_2 = 4; macro EISASLOTINFO$v_hex_1 = 9,4,4,0 %; literal EISASLOTINFO$s_hex_1 = 4; macro EISASLOTINFO$B_PID_byte3 = 10,0,8,0 %; macro EISASLOTINFO$v_hex_4 = 10,0,4,0 %; literal EISASLOTINFO$s_hex_4 = 4; macro EISASLOTINFO$v_hex_3 = 10,4,4,0 %; literal EISASLOTINFO$s_hex_3 = 4; literal EISACONFIG$m_char_2_msb = %X'3'; literal EISACONFIG$m_char_1 = %X'7C'; literal EISACONFIG$m_char_3_msb = %X'1F'; literal EISACONFIG$m_char_2_lsb = %X'E0'; literal EISACONFIG$m_hex_2 = %X'F'; literal EISACONFIG$m_hex_1 = %X'F0'; literal EISACONFIG$m_hex_4 = %X'F'; literal EISACONFIG$m_hex_3 = %X'F0'; literal EISACONFIG$M_CFG_REV = %X'F'; literal EISACONFIG$M_SLOT_TYPE = %X'30'; literal EISACONFIG$M_READ_ID = %X'40'; literal EISACONFIG$M_DUP_ID = %X'80'; literal EISACONFIG$M_EISA_ENABLE = %X'1'; literal EISACONFIG$M_IOCHKERR = %X'2'; literal EISACONFIG$M_CFG_DONE = %X'80'; literal EISACONFIG$M_TYPE_ENTRY = %X'1'; literal EISACONFIG$M_MEM_ENTRY = %X'2'; literal EISACONFIG$M_IRQ_ENTRY = %X'4'; literal EISACONFIG$M_DMA_ENTRY = %X'8'; literal EISACONFIG$M_PORT_RANGE_ENTRY = %X'10'; literal EISACONFIG$M_PORT_INIT_ENTRY = %X'20'; literal EISACONFIG$M_CFG_FREE_FORM = %X'40'; literal EISACONFIG$M_FUNC_ENB = %X'80'; literal EISACONFIG$m_rom_ram = %X'1'; literal EISACONFIG$m_mem_cached = %X'2'; literal EISACONFIG$m_mem_type = %X'18'; literal EISACONFIG$m_shared_mem = %X'20'; literal EISACONFIG$m_more_mem_entries = %X'80'; literal EISACONFIG$m_mem_access_size = %X'3'; literal EISACONFIG$m_mem_decode_size = %X'C'; literal EISACONFIG$m_int_0_F = %X'F'; literal EISACONFIG$M_INT_EDGE_LVL = %X'20'; literal EISACONFIG$M_INT_SHARED = %X'40'; literal EISACONFIG$M_INT_LAST_ENTRY = %X'80'; literal EISACONFIG$M_DMA_LAST_ENTRY = %X'1'; literal EISACONFIG$M_DMA_SHARED = %X'2'; literal EISACONFIG$M_DMA_CHAN = %X'E0'; literal EISACONFIG$M_DMA_TIMING = %X'C'; literal EISACONFIG$M_DMA_XFER_SIZE = %X'30'; literal EISACONFIG$M_PORT_IO_LAST_ENTRY = %X'1'; literal EISACONFIG$M_PORT_IO_SHARED = %X'2'; literal EISACONFIG$M_NUM_IO_PORT_BYTES = %X'F8'; literal EISACONFIG$S_EISACONFIGDEF = 320; macro EISACONFIG$B_PID_byte = 0,0,8,0 %; macro EISACONFIG$v_char_2_msb = 0,0,2,0 %; literal EISACONFIG$s_char_2_msb = 2; ! bits <1:0> (2 msb's) macro EISACONFIG$v_char_1 = 0,2,5,0 %; literal EISACONFIG$s_char_1 = 5; ! bits <6:2> macro EISACONFIG$B_PID_byte1 = 1,0,8,0 %; macro EISACONFIG$v_char_3_msb = 1,0,5,0 %; literal EISACONFIG$s_char_3_msb = 5; ! bits <4:0> macro EISACONFIG$v_char_2_lsb = 1,5,3,0 %; literal EISACONFIG$s_char_2_lsb = 3; ! bits <7:5> macro EISACONFIG$B_PID_byte2 = 2,0,8,0 %; macro EISACONFIG$v_hex_2 = 2,0,4,0 %; literal EISACONFIG$s_hex_2 = 4; macro EISACONFIG$v_hex_1 = 2,4,4,0 %; literal EISACONFIG$s_hex_1 = 4; macro EISACONFIG$B_PID_byte3 = 3,0,8,0 %; macro EISACONFIG$v_hex_4 = 3,0,4,0 %; literal EISACONFIG$s_hex_4 = 4; macro EISACONFIG$v_hex_3 = 3,4,4,0 %; literal EISACONFIG$s_hex_3 = 4; macro EISACONFIG$B_SLOTID = 4,0,8,0 %; macro EISACONFIG$V_CFG_REV = 4,0,4,0 %; literal EISACONFIG$S_CFG_REV = 4; macro EISACONFIG$V_SLOT_TYPE = 4,4,2,0 %; literal EISACONFIG$S_SLOT_TYPE = 2; macro EISACONFIG$V_READ_ID = 4,6,1,0 %; macro EISACONFIG$V_DUP_ID = 4,7,1,0 %; macro EISACONFIG$B_CONFIG_ERR = 5,0,8,0 %; macro EISACONFIG$V_EISA_ENABLE = 5,0,1,0 %; macro EISACONFIG$V_IOCHKERR = 5,1,1,0 %; macro EISACONFIG$V_CFG_DONE = 5,7,1,0 %; macro EISACONFIG$B_MINOR_CFG_REV = 6,0,8,0 %; macro EISACONFIG$B_MAJOR_CFG_REV = 7,0,8,0 %; macro EISACONFIG$B_SELECTION_FIELD = 8,0,0,1 %; literal EISACONFIG$S_SELECTION_FIELD = 26; macro EISACONFIG$B_FUNC_INFO = 34,0,8,0 %; macro EISACONFIG$V_TYPE_ENTRY = 34,0,1,0 %; macro EISACONFIG$V_MEM_ENTRY = 34,1,1,0 %; macro EISACONFIG$V_IRQ_ENTRY = 34,2,1,0 %; macro EISACONFIG$V_DMA_ENTRY = 34,3,1,0 %; macro EISACONFIG$V_PORT_RANGE_ENTRY = 34,4,1,0 %; macro EISACONFIG$V_PORT_INIT_ENTRY = 34,5,1,0 %; macro EISACONFIG$V_CFG_FREE_FORM = 34,6,1,0 %; macro EISACONFIG$V_FUNC_ENB = 34,7,1,0 %; macro EISACONFIG$B_TYPE_STYPE_STRING = 35,0,0,0 %; literal EISACONFIG$S_TYPE_STYPE_STRING = 80; ! the memory config region can contain up to 9 7 byte descriptions of ! assigned memory regions. In general, only ! one of the regions is used, but, for instance, some VGA cards require ! 4 buffers. These buffers would be specified in the first 4 7-byte blocks. ! Only one of the 7 byte regions has offsets defined here, the remaining 56 ! bytes of memory config information should be accessed using the defined offsets ! plus an offset of 7*#mem_config_block_being_returned. ie, to access the 1st byte ! of the ith config block being returned for this card, the bliss code would be ! mem_config_byte = .ptr_to_1st_mem_config_block[$byteoffset(eisaconfig$b_mem_config)+(i*7),0,8,0]; ! In order to reference the interior bits of these bytes, use the $bitposition macro similarly. ! these macros are all defined in starlet. ! macro EISACONFIG$B_MEM_CONFIG = 115,0,8,0 %; macro EISACONFIG$v_rom_ram = 115,0,1,0 %; macro EISACONFIG$v_mem_cached = 115,1,1,0 %; macro EISACONFIG$v_mem_type = 115,3,2,0 %; literal EISACONFIG$s_mem_type = 2; macro EISACONFIG$v_shared_mem = 115,5,1,0 %; macro EISACONFIG$v_more_mem_entries = 115,7,1,0 %; macro EISACONFIG$B_MEM_DATA_SIZE = 116,0,8,0 %; macro EISACONFIG$v_mem_access_size = 116,0,2,0 %; literal EISACONFIG$s_mem_access_size = 2; macro EISACONFIG$v_mem_decode_size = 116,2,2,0 %; literal EISACONFIG$s_mem_decode_size = 2; macro EISACONFIG$B_MEM_ADDR_BYTE1 = 117,0,8,0 %; ! this 3 byte field should be multiplied macro EISACONFIG$B_MEM_ADDR_BYTE2 = 118,0,8,0 %; ! by 100h to get the true starting address macro EISACONFIG$B_MEM_ADDR_BYTE3 = 119,0,8,0 %; macro EISACONFIG$B_MEM_SIZE_BYTE1 = 120,0,8,0 %; ! this field needs to be multiplied by 400h macro EISACONFIG$B_MEM_SIZE_BYTE2 = 121,0,8,0 %; ! to get the true size, if byte1=0, size = 64M ! now we need the fill to leave space for the remaining 56 bytes of mem config data macro EISACONFIG$b_fill3a = 122,0,0,1 %; literal EISACONFIG$s_fill3a = 56; ! the following byte specifies the interrupt request information needed by the device ! each block is 2 bytes long, and there can be up to 7 blocks. Apparently some cards can ! have a function which needs several irq's. Again, the offsets for a single ! interrupt definition are defined here, to access multiple interrupt definitions, use the ! starlet macros $byteoffset, $bitposition, $fieldwidth, $extension and an index into the ! interrupt definition blocks. See the mem config block example above. macro EISACONFIG$B_INTERR = 178,0,8,0 %; macro EISACONFIG$v_int_0_F = 178,0,4,0 %; literal EISACONFIG$s_int_0_F = 4; macro EISACONFIG$V_INT_EDGE_LVL = 178,5,1,0 %; macro EISACONFIG$V_INT_SHARED = 178,6,1,0 %; macro EISACONFIG$V_INT_LAST_ENTRY = 178,7,1,0 %; ! now leave the space for the remaining 13 potential blocks of IRQ info. macro EISACONFIG$b_fill3b = 179,0,0,1 %; literal EISACONFIG$s_fill3b = 13; ! the following byte specifies the dma channel information needed by the device ! each block is 2 bytes long, and there can be up to 4 blocks. Apparently some cards can ! have a function which needs several dma channels. Again, the offsets for a single ! block definition are defined here, to access multiple blocks, use the ! starlet macros $byteoffset, $bitposition, $fieldwidth, $extension and an index into the ! definition blocks. See the mem config block example above. macro EISACONFIG$B_DMA_BYTE0 = 192,0,8,0 %; macro EISACONFIG$V_DMA_LAST_ENTRY = 192,0,1,0 %; macro EISACONFIG$V_DMA_SHARED = 192,1,1,0 %; macro EISACONFIG$V_DMA_CHAN = 192,5,3,0 %; literal EISACONFIG$S_DMA_CHAN = 3; macro EISACONFIG$B_DMA_BYTE1 = 193,0,8,0 %; macro EISACONFIG$V_DMA_TIMING = 193,2,2,0 %; literal EISACONFIG$S_DMA_TIMING = 2; macro EISACONFIG$V_DMA_XFER_SIZE = 193,4,2,0 %; literal EISACONFIG$S_DMA_XFER_SIZE = 2; macro EISACONFIG$b_fill6 = 194,0,0,1 %; literal EISACONFIG$s_fill6 = 6; ! the following block contains the necessary information specifying which IO ports ! a board has been assigned to use. Each entry consists of 3 bytes, and there can be ! as many as 20 entries, for a total size of 60 bytes. The first byte specifies if there ! are more entries to follow, and the number of ports-1 defined.(ie how many sequential bytes ! has the board been reserved) ! the second and third bytes specify the starting address. As per the above blocks, there are ! not 60 entries defined here. Instead a single entry is defined and the user needs to use the ! starlett macros $byteoffset, $bitposition, etc. and an index into the IO port config data to ! reference IO port block definitions 2-20. See mem config example above. macro EISACONFIG$B_PORT_IO_BYTE0 = 200,0,8,0 %; macro EISACONFIG$V_PORT_IO_LAST_ENTRY = 200,0,1,0 %; macro EISACONFIG$V_PORT_IO_SHARED = 200,1,1,0 %; macro EISACONFIG$V_NUM_IO_PORT_BYTES = 200,3,5,0 %; literal EISACONFIG$S_NUM_IO_PORT_BYTES = 5; macro EISACONFIG$B_PORT_IO_ADDR_L = 201,0,8,0 %; macro EISACONFIG$B_PORT_IO_ADDR_H = 202,0,8,0 %; macro EISACONFIG$b_fill7 = 203,0,0,1 %; literal EISACONFIG$s_fill7 = 57; ! now leave space for the remaining port io blocks ! a major contribution of the ECU is it's ability to initialize board CSR with predefined ! information. This aspect of the ECU is utilized before boot, and the following information ! is not of importance to the VMS Bus Support code, so nothing is defined for it, space is simply ! reserved. macro EISACONFIG$B_INIT_DATA = 260,0,0,1 %; literal EISACONFIG$S_INIT_DATA = 60; literal eisa_hw_id_mask_lo = -1; literal eisa_hw_id_mask_hi = -1; !*** MODULE $EISDDEF *** ! + ! EXTENDED IMAGE SECTION DESCRIPTOR DEFINITIONS ! - literal EISD$K_MAJORID = 1; literal EISD$K_MINORID = 1; literal EISD$M_GBL = %X'1'; literal EISD$M_CRF = %X'2'; literal EISD$M_DZRO = %X'4'; literal EISD$M_WRT = %X'8'; literal EISD$M_INITALCODE = %X'10'; literal EISD$M_BASED = %X'20'; literal EISD$M_FIXUPVEC = %X'40'; literal EISD$M_RESIDENT = %X'80'; literal EISD$M_VECTOR = %X'100'; literal EISD$M_PROTECT = %X'200'; literal EISD$M_LASTCLU = %X'400'; literal EISD$M_EXE = %X'800'; literal EISD$M_NONSHRADR = %X'1000'; literal EISD$M_QUAD_LENGTH = %X'2000'; literal EISD$M_ALLOC_64BIT = %X'4000'; literal EISD$K_LENDZRO = 36; ! LENGTH OF DEMAND ZERO ISD (OR STACK ISD) literal EISD$C_LENDZRO = 36; ! LENGTH OF DEMAND ZERO ISD (OR STACK ISD) literal EISD$K_LENPRIV = 36; ! LENGTH OF PRIVATE ISD literal EISD$C_LENPRIV = 36; ! LENGTH OF PRIVATE ISD literal EISD$K_LENGLBL = 56; ! LENGTH OF OLD GLOBAL ISD literal EISD$C_LENGLBL = 56; ! LENGTH OF OLD GLOBAL ISD literal EISD$K_MAXLENGLBL = 84; ! MAX LENGTH OF NEW GLOBAL ISD literal EISD$C_MAXLENGLBL = 84; ! MAX LENGTH OF NEW GLOBAL ISD ! + literal EISD$K_MATALL = 0; ! MATCH ALWAYS, USE GLOBAL SECTION literal EISD$K_MATEQU = 1; ! MATCH IF ISD$L_IDENT EQU GBL ID literal EISD$K_MATLEQ = 2; ! MATCH IF ISD$L_IDENT LEQ GBL ID literal EISD$K_MATNEV = 3; ! MATCH NEVER, USE PRIVATE COPY ! + literal EISD$K_NORMAL = 0; ! NORMAL PROGRAM IMAGE SECTION ! NO SPECIAL ACTION REQUIRED literal EISD$K_SHRFXD = 1; ! SHAREABLE FIXED SECTION literal EISD$K_PRVFXD = 2; ! PRIVATE FIXED SECTION literal EISD$K_SHRPIC = 3; ! SHAREABLE PIC SECTION literal EISD$K_PRVPIC = 4; ! PRIVATE PIC SECTION literal EISD$K_USRSTACK = 253; ! USER STACK SECTION literal EISD$S_EISDDEF = 84; ! Old size name - synonym literal EISD$S_EISD = 84; macro EISD$R_VERSION = 0,0,0,0 %; literal EISD$S_VERSION = 8; ! Version of this EISD macro EISD$L_MAJORID = 0,0,32,0 %; ! Major ID macro EISD$L_MINORID = 4,0,32,0 %; ! Minor ID macro EISD$L_EISDSIZE = 8,0,32,0 %; ! SIZE IN BYTES OF THIS EISD macro EISD$L_SECSIZE = 12,0,32,0 %; ! SIZE OF SECTION IN BYTES DESCRIBED BY THIS ISD macro EISD$Q_VIRT_ADDR = 16,0,0,0 %; literal EISD$S_VIRT_ADDR = 8; ! Virtual address of section macro EISD$L_VIRT_ADDR = 16,0,32,1 %; ! low 32 bits of virtual address macro EISD$V_VADDR = 16,0,30,0 %; literal EISD$S_VADDR = 30; ! Virtual address in region macro EISD$V_P1 = 16,30,1,0 %; ! P1 SPACE macro EISD$V_SYSTEM = 16,31,1,0 %; ! SYSTEM SPACE macro EISD$L_FLAGS = 24,0,32,0 %; ! FLAGS AND ISD TYPE macro EISD$V_GBL = 24,0,1,0 %; ! GLOBAL macro EISD$V_CRF = 24,1,1,0 %; ! COPY ON REFERENCE macro EISD$V_DZRO = 24,2,1,0 %; ! DEMAND ZERO PAGE macro EISD$V_WRT = 24,3,1,0 %; ! WRITABLE macro EISD$V_INITALCODE = 24,4,1,0 %; ! ISD IS PART OF INITIALIZATION CODE macro EISD$V_BASED = 24,5,1,0 %; ! ISECT IS BASED macro EISD$V_FIXUPVEC = 24,6,1,0 %; ! ISECT IS FIXUP SECTION macro EISD$V_RESIDENT = 24,7,1,0 %; ! ISECT IS MEMORY-RESIDENT macro EISD$V_VECTOR = 24,8,1,0 %; ! VECTOR CONTAINED IN IMAGE SECTION macro EISD$V_PROTECT = 24,9,1,0 %; ! IMAGE SECTION IS PROTECTED macro EISD$V_LASTCLU = 24,10,1,0 %; ! LAST CLUSTER macro EISD$V_EXE = 24,11,1,0 %; ! IF SET, THIS IS A CODE IMAGE SECTION macro EISD$V_NONSHRADR = 24,12,1,0 %; ! IF SET, SECTION CONTAINS NON-SHAREABLE ADDRESS DATA macro EISD$V_QUAD_LENGTH = 24,13,1,0 %; ! If set, quad length field (eisd$q_secsize) is valid macro EISD$V_ALLOC_64BIT = 24,14,1,0 %; ! If set, allocate in 64-bit space macro EISD$L_VBN = 28,0,32,0 %; ! BASE VIRTUAL BLOCK NUMBER macro EISD$B_PFC = 32,0,8,0 %; ! Page faule cluster macro EISD$B_MATCHCTL = 33,0,8,0 %; ! Linker match control macro EISD$B_TYPE = 34,0,8,0 %; ! Section type macro EISD$B_FILL_1 = 35,0,8,0 %; ! filler macro EISD$L_IDENT = 36,0,32,0 %; ! IDENT FOR GLOBAL SECTION macro EISD$T_GBLNAM = 40,0,0,0 %; literal EISD$S_GBLNAM = 44; ! GLOBAL NAME COUNTED STRING macro EISD$Q_SECSIZE = 40,0,0,0 %; literal EISD$S_SECSIZE = 8; ! Quadword size for 64-bit sections ! MATCH CONTROL VIELD VALUES ! - ! BASE OF ZERO , INCR 1 ! ISD TYPE FIELD DEFINITIONS ! - !*** MODULE $EMBINDICTDEF *** ! ! INDICTMENT BUFFER FORMAT ! literal EMB$K_INDICT_ISUB_CLASS = 9; ! INDICT ISUB class literal EMB$C_INDICT_ISUB_CLASS = 9; ! INDICT ISUB class literal EMB$K_INDICT_ISUB_TYPE = 3; ! INDICT ISUB type literal EMB$C_INDICT_ISUB_TYPE = 3; ! INDICT ISUB type literal EMB$K_INDICT_ISUB_REV = 1; ! INDICT ISUB revision literal EMB$C_INDICT_ISUB_REV = 1; ! INDICT ISUB revision literal EMB$K_INDICT_ISUB_LENGTH = 536; ! INDICT ISUB size literal EMB$C_INDICT_ISUB_LENGTH = 536; ! INDICT ISUB size literal EMB$K_INDICT_TSUB_LENGTH = 8; ! INDICT TSUB class literal EMB$C_INDICT_TSUB_LENGTH = 8; ! INDICT TSUB class literal EMB$K_INDICT_TSUB_CLASS = 0; ! INDICT TSUB class literal EMB$C_INDICT_TSUB_CLASS = 0; ! INDICT TSUB class literal EMB$K_INDICT_TSUB_TYPE = 0; ! INDICT TSUB type literal EMB$C_INDICT_TSUB_TYPE = 0; ! INDICT TSUB type literal EMB$K_INDICT_TSUB_REV = 1; ! INDICT TSUB revision literal EMB$C_INDICT_TSUB_REV = 1; ! INDICT TSUB revision literal EMB$K_INDICT_ERL_LENGTH = 640; ! INDICT ERL size literal EMB$C_INDICT_ERL_LENGTH = 640; ! INDICT ERL size literal EMB$S_EMBINDICTDEF = 640; ! Old size name - synonym literal EMB$S_EMBINDICT = 640; macro EMB$L_INDT_SID = 0,0,32,0 %; ! SYSTEM ID macro EMB$W_INDT_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_INDT_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_INDT_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_INDT_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_INDT_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$B_INDT_SCS_NAME = 16,0,0,0 %; literal EMB$S_INDT_SCS_NAME = 16; ! SCS node name in ASCIC macro EMB$W_INDT_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_INDT_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_INDT_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_INDT_ENTRY = 36,0,16,0 %; ! ENTRY TYPE macro EMB$Q_INDT_TIME = 38,0,0,0 %; literal EMB$S_INDT_TIME = 8; ! TIME IN 64 BIT FORMAT macro EMB$W_INDT_ERRSEQ = 46,0,16,0 %; ! ERROR SEQUENCE NUMBER macro EMB$Q_INDT_SWVERS = 48,0,0,0 %; literal EMB$S_INDT_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_INDT_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_INDT_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_INDT_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_INDT_HW_NAME = 65,0,0,0 %; literal EMB$S_INDT_HW_NAME = 31; ! marketing name of this system macro EMB$W_INDICT_ISUB_LEN = 96,0,16,0 %; ! Indictment subpak length macro EMB$W_INDICT_ISUB_CLASS = 98,0,16,0 %; ! Indictment subpak class macro EMB$W_INDICT_ISUB_TYPE = 100,0,16,0 %; ! Indictment subpak type macro EMB$W_INDICT_ISUB_REV = 102,0,16,0 %; ! Indictment subpak rev macro EMB$L_INDICT_STATUS = 104,0,32,0 %; ! Status of this entry macro EMB$L_INDICT_OBJECT_TYPE = 108,0,32,0 %; ! Type: Component/PFN/OS macro EMB$Q_INDICT_PFN_OS_HANDLE = 112,0,0,0 %; literal EMB$S_INDICT_PFN_OS_HANDLE = 8; ! Failing PFN or OS HWR ID macro EMB$IQ_INDICT_COMP_ID = 120,0,0,0 %; literal EMB$S_INDICT_COMP_ID = 8; ! Component Handle ID macro EMB$B_INDICT_COMP_TYPE = 128,0,8,0 %; ! Component Handle Type macro EMB$B_INDICT_COMP_SUBTYPE = 129,0,8,0 %; ! Component Handle Subtype macro EMB$IQ_INDICT_MODULE_ID = 136,0,0,0 %; literal EMB$S_INDICT_MODULE_ID = 8; ! Module Handle ID macro EMB$B_INDICT_MODULE_TYPE = 144,0,8,0 %; ! Module Handle Type macro EMB$B_INDICT_MODULE_SUBTYPE = 145,0,8,0 %; ! Module Handle Subtype macro EMB$L_INDICT_URGENCY = 152,0,32,0 %; ! Urgency of indictment request macro EMB$L_INDICT_PROBABILITY = 156,0,32,0 %; ! Probability of correct fault macro EMB$L_TOTAL_INDICTMENTS = 160,0,32,0 %; ! Total number to be indicted macro EMB$L_INDICT_DESCRIP_SIZE = 164,0,32,0 %; ! Size of descriptor string macro EMB$L_INDICT_INITIATOR_SIZE = 168,0,32,0 %; ! Size of initiator string macro EMB$L_INDICT_REPORT_SIZE = 172,0,32,0 %; ! Size of report handle string macro EMB$B_INDICT_DESCRIPTION = 176,0,0,1 %; literal EMB$S_INDICT_DESCRIPTION = 256; ! Readable descr. of problem macro EMB$B_INDICT_INITIATOR = 440,0,0,1 %; literal EMB$S_INDICT_INITIATOR = 32; ! Who called us macro EMB$B_INDICT_REPORT_HANDLE = 480,0,0,1 %; literal EMB$S_INDICT_REPORT_HANDLE = 128; ! report handle program name macro EMB$W_INDICT_TSUB_LEN = 632,0,16,0 %; ! Termination subpak length macro EMB$W_INDICT_TSUB_CLASS = 634,0,16,0 %; ! Termination subpak class macro EMB$W_INDICT_TSUB_TYPE = 636,0,16,0 %; ! Termination subpak type macro EMB$W_INDICT_TSUB_REV = 638,0,16,0 %; ! Termination subpak rev !*** MODULE $EMBINFODEF *** ! ! INFORMATIONAL MESSAGE BUFFER FORMAT ! literal EMB$S_EMBINFODEF = 101; ! Old size name - synonym literal EMB$S_EMBINFO = 101; macro EMB$L_INFO_MSG_TYPE = 96,0,32,0 %; ! Informational msg type macro EMB$B_INFO_MSG_DATA = 100,0,8,0 %; ! Device dependent data !*** MODULE $EMBBCDEF *** ! ! BUGCHECK ERROR MESSAGE BUFFER FORMAT (SYSTEM AND USER) ! literal EMB$K_BC_LENGTH = 416; ! SIZE OF FIXED PART OF BUGCHECK MESSAGE literal EMB$C_BC_LENGTH = 416; ! SIZE OF FIXED PART OF BUGCHECK MESSAGE literal EMB$S_EMBBCDEF = 416; ! Old size name - synonym literal EMB$S_EMBBC = 416; macro EMB$L_BC_SID = 0,0,32,0 %; ! SYSTEM ID macro EMB$W_BC_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_BC_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_BC_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_BC_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_BC_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$R_BC_SCS_NAME = 16,0,0,0 %; literal EMB$S_BC_SCS_NAME = 16; ! SCS node name ASCIC macro EMB$W_BC_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_BC_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_BC_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_BC_ENTRY = 36,0,16,0 %; ! ENTRY TYPE macro EMB$Q_BC_TIME = 38,0,0,0 %; literal EMB$S_BC_TIME = 8; ! TIME IN 64 BITS macro EMB$W_BC_ERRSEQ = 46,0,16,0 %; ! ERROR SEQUENCE NUMBER macro EMB$Q_BC_SWVERS = 48,0,0,0 %; literal EMB$S_BC_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_BC_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_BC_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_BC_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_BC_HW_NAME = 65,0,0,0 %; literal EMB$S_BC_HW_NAME = 31; ! marketing name of this system macro EMB$Q_BC_KSP = 96,0,0,0 %; literal EMB$S_BC_KSP = 8; ! KERNEL STACK POINTER macro EMB$Q_BC_ESP = 104,0,0,0 %; literal EMB$S_BC_ESP = 8; ! EXECUTIVE STACK POINTER macro EMB$Q_BC_SSP = 112,0,0,0 %; literal EMB$S_BC_SSP = 8; ! SUPERVISOR STACK POINTER macro EMB$Q_BC_USP = 120,0,0,0 %; literal EMB$S_BC_USP = 8; ! USER STACK POINTER macro EMB$Q_BC_R0 = 128,0,0,0 %; literal EMB$S_BC_R0 = 8; ! REGISTER R0 macro EMB$Q_BC_R1 = 136,0,0,0 %; literal EMB$S_BC_R1 = 8; ! REGISTER R1 macro EMB$Q_BC_R2 = 144,0,0,0 %; literal EMB$S_BC_R2 = 8; ! REGISTER R2 macro EMB$Q_BC_R3 = 152,0,0,0 %; literal EMB$S_BC_R3 = 8; ! REGISTER R3 macro EMB$Q_BC_R4 = 160,0,0,0 %; literal EMB$S_BC_R4 = 8; ! REGISTER R4 macro EMB$Q_BC_R5 = 168,0,0,0 %; literal EMB$S_BC_R5 = 8; ! REGISTER R5 macro EMB$Q_BC_R6 = 176,0,0,0 %; literal EMB$S_BC_R6 = 8; ! REGISTER R6 macro EMB$Q_BC_R7 = 184,0,0,0 %; literal EMB$S_BC_R7 = 8; ! REGISTER R7 macro EMB$Q_BC_R8 = 192,0,0,0 %; literal EMB$S_BC_R8 = 8; ! REGISTER R8 macro EMB$Q_BC_R9 = 200,0,0,0 %; literal EMB$S_BC_R9 = 8; ! REGISTER R9 macro EMB$Q_BC_R10 = 208,0,0,0 %; literal EMB$S_BC_R10 = 8; ! REGISTER R10 macro EMB$Q_BC_R11 = 216,0,0,0 %; literal EMB$S_BC_R11 = 8; ! REGISTER R11 macro EMB$Q_BC_R12 = 224,0,0,0 %; literal EMB$S_BC_R12 = 8; ! REGISTER R12 macro EMB$Q_BC_R13 = 232,0,0,0 %; literal EMB$S_BC_R13 = 8; ! REGISTER R13 macro EMB$Q_BC_R14 = 240,0,0,0 %; literal EMB$S_BC_R14 = 8; ! REGISTER R14 macro EMB$Q_BC_R15 = 248,0,0,0 %; literal EMB$S_BC_R15 = 8; ! REGISTER R15 macro EMB$Q_BC_R16 = 256,0,0,0 %; literal EMB$S_BC_R16 = 8; ! REGISTER R16 macro EMB$Q_BC_R17 = 264,0,0,0 %; literal EMB$S_BC_R17 = 8; ! REGISTER R17 macro EMB$Q_BC_R18 = 272,0,0,0 %; literal EMB$S_BC_R18 = 8; ! REGISTER R18 macro EMB$Q_BC_R19 = 280,0,0,0 %; literal EMB$S_BC_R19 = 8; ! REGISTER R19 macro EMB$Q_BC_R20 = 288,0,0,0 %; literal EMB$S_BC_R20 = 8; ! REGISTER R20 macro EMB$Q_BC_R21 = 296,0,0,0 %; literal EMB$S_BC_R21 = 8; ! REGISTER R21 macro EMB$Q_BC_R22 = 304,0,0,0 %; literal EMB$S_BC_R22 = 8; ! REGISTER R22 macro EMB$Q_BC_R23 = 312,0,0,0 %; literal EMB$S_BC_R23 = 8; ! REGISTER R23 macro EMB$Q_BC_R24 = 320,0,0,0 %; literal EMB$S_BC_R24 = 8; ! REGISTER R24 macro EMB$Q_BC_R25 = 328,0,0,0 %; literal EMB$S_BC_R25 = 8; ! REGISTER R25 macro EMB$Q_BC_R26 = 336,0,0,0 %; literal EMB$S_BC_R26 = 8; ! REGISTER R26 macro EMB$Q_BC_R27 = 344,0,0,0 %; literal EMB$S_BC_R27 = 8; ! REGISTER R27 macro EMB$Q_BC_R28 = 352,0,0,0 %; literal EMB$S_BC_R28 = 8; ! REGISTER R28 macro EMB$Q_BC_FP = 360,0,0,0 %; literal EMB$S_BC_FP = 8; ! FRAME POINTER macro EMB$Q_BC_SP = 368,0,0,0 %; literal EMB$S_BC_SP = 8; ! CURRENT STACK POINTER macro EMB$Q_BC_PC = 376,0,0,0 %; literal EMB$S_BC_PC = 8; ! PROGRAM COUNTER macro EMB$Q_BC_PSL = 384,0,0,0 %; literal EMB$S_BC_PSL = 8; ! PROCESSOR STATUS macro EMB$L_BC_CODE = 392,0,32,0 %; ! BUGCHECK CODE macro EMB$L_BC_PID = 396,0,32,0 %; ! CURRENT PROCESS ID macro EMB$T_BC_LNAME = 400,0,0,0 %; literal EMB$S_BC_LNAME = 16; ! CURRENT PROCESS NAME !*** MODULE $EMBDVDEF *** ! ! DEVICE ERROR MESSAGE BUFFER FORMAT (ERROR AND TIMEOUT) ! literal EMB$K_DV_LENGTH = 222; literal EMB$C_DV_LENGTH = 222; literal EMB$S_EMBDVDEF = 222; ! Old size name - synonym literal EMB$S_EMBDV = 222; macro EMB$L_DV_SID = 0,0,32,0 %; ! SYSTEM ID macro EMB$W_DV_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_DV_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_DV_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_DV_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_DV_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$B_DV_SCS_NAME = 16,0,0,0 %; literal EMB$S_DV_SCS_NAME = 16; ! SCS node name in ASCIC macro EMB$W_DV_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_DV_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_DV_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_DV_ENTRY = 36,0,16,0 %; ! ENTRY TYPE (1=ERROR, 96=TIMEOUT) macro EMB$Q_DV_TIME = 38,0,0,0 %; literal EMB$S_DV_TIME = 8; ! TIME OF ERROR macro EMB$W_DV_ERRSEQ = 46,0,16,0 %; ! ERROR SEQUENCE NUMBER macro EMB$Q_DV_SWVERS = 48,0,0,0 %; literal EMB$S_DV_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_DV_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_DV_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_DV_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_DV_HW_NAME = 65,0,0,0 %; literal EMB$S_DV_HW_NAME = 31; ! marketing name of this system macro EMB$L_DV_ERTCNT = 96,0,32,0 %; ! REMAINING NUMBER OF ERROR RETRIES macro EMB$L_DV_ERTMAX = 100,0,32,0 %; ! MAXIMUM NUMBER OF ERROR RETRIES macro EMB$Q_DV_IOSB = 104,0,0,0 %; literal EMB$S_DV_IOSB = 8; ! FINAL I/O STATUS macro EMB$L_DV_STS = 112,0,32,0 %; ! FINAL DEVICE STATUS macro EMB$B_DV_CLASS = 116,0,8,0 %; ! DEVICE CLASS macro EMB$B_DV_TYPE = 117,0,8,0 %; ! DEVICE TYPE macro EMB$L_DV_RQPID = 118,0,32,0 %; ! REQUESTER PROCESS ID macro EMB$L_DV_BOFF = 122,0,32,0 %; ! BYTE OFFSET IN PAGE macro EMB$L_DV_BCNT = 126,0,32,0 %; ! TRANSFER BYTE COUNT macro EMB$L_DV_MEDIA = 130,0,32,1 %; ! STARTING MEDIA ADDRESS macro EMB$W_DV_UNIT = 134,0,16,0 %; ! PHYSICAL UNIT NUMBER macro EMB$L_DV_ERRCNT = 136,0,32,0 %; ! UNIT ERROR COUNT macro EMB$L_DV_OPCNT = 140,0,32,0 %; ! UNIT OPERATION COUNT macro EMB$L_DV_OWNUIC = 144,0,32,0 %; ! VOLUME OWNER UIC macro EMB$L_DV_CHAR = 148,0,32,0 %; ! DEVICE CHARACTERISTICS macro EMB$B_DV_SLAVE = 152,0,8,0 %; ! SLAVE CONTROLLER NUMBER macro EMB$L_DV_FUNC = 154,0,32,0 %; ! I/O FUNCTION VALUE macro EMB$T_DV_NAME = 158,0,0,0 %; literal EMB$S_DV_NAME = 32; ! DEVICE NAME macro EMB$T_DV_DTNAME = 190,0,0,0 %; literal EMB$S_DV_DTNAME = 28; ! Device type name ! counted string macro EMB$L_DV_REGSAV = 218,0,32,1 %; ! START OF REGISTER SAVE AREA ! EMB$K_PWR layout: ! ! 0: +----------------------+ ! | | ! | Standard EMB header | ! | 64 bytes | ! +----------------------+ ! 64: | | ! | Power regulator | ! | summary 4 bytes | ! +----------------------+ ! 68: | | ! | LASER_POWER version | ! | 8 bytes | ! +----------------------+ ! 76: | | ! | Record sub-type | ! | 4 bytes | ! +----------------------+ ! ! Sub-type=EMB$K_pwr_state_event Sub-type=EMB$K_pwr_history_event Sub-type=EMB$K_pwr_bad_event Sub-type=EMB$K_pwr_gbus ! ! +----------------------+ +---------------------+ +-------------------------+ +---------------------+ ! 80: | Center cabinet | 80: | Center Cabinet | 80: | | 80: | | ! |Regulator A time-stamp| | Regulator A "H" msg | | Regulator id | | GBUS$HALT register | ! | 8 bytes | | 54 bytes | | 8 bytes | | 4 bytes | ! +----------------------+ +---------------------+ +-------------------------+ +---------------------+ ! 88: | Center cabinet | 134: | | 88: | | 84: | previous | ! |Regulator B time-stamp| | 2 bytes padding | | Problem type | | GBUS$HALT register | ! | 8 bytes | | | | 4 bytes | | 4 bytes | ! +----------------------+ +---------------------+ +-------------------------+ +---------------------+ ! 96: | Center cabinet | 136: | Center Cabinet | 92: | | 88: ! |Regulator C time-stamp| | Regulator B "H" msg | | Regulator "B" msg | ! | 8 bytes | | 54 bytes | | 9 bytes | ! +----------------------+ +---------------------+ +-------------------------+ ! 104: | Left cabinet | 190: | | 101: ! |Regulator A time-stamp| | 2 bytes padding | ! | 8 bytes | | | ! +----------------------+ +---------------------+ ! 112: | Left cabinet | 192: | Center Cabinet | ! |Regulator B time-stamp| | Regulator C "H" msg | ! | 8 bytes | | 54 bytes | ! +----------------------+ +---------------------+ ! 120: | Left cabinet | 246: | | ! |Regulator C time-stamp| | 2 bytes padding | ! | 8 bytes | | | ! +----------------------+ +---------------------+ ! 128: | Right cabinet | 248: | Left Cabinet | ! |Regulator A time-stamp| | Regulator A "H" msg | ! | 8 bytes | | 54 bytes | ! +----------------------+ +---------------------+ ! 136: | Right cabinet | 302: | | ! |Regulator B time-stamp| | 2 bytes padding | ! | 8 bytes | | | ! +----------------------+ +---------------------+ ! 144: | Right cabinet | 304: | Left Cabinet | ! |Regulator C time-stamp| | Regulator B "H" msg | ! | 8 bytes | | 54 bytes | ! +----------------------+ +---------------------+ ! 152: | Center cabinet | 358: | | ! | Regulator A "B" msg | | 2 bytes padding | ! | 9 bytes | | | ! +----------------------+ +---------------------+ ! 161: | | 360: | Left Cabinet | ! | 3 bytes padding | | Regulator C "H" msg | ! | | | 54 bytes | ! +----------------------+ +---------------------+ ! 164: | Center cabinet | 414: | | ! | Regulator B "B" msg | | 2 bytes padding | ! | 9 bytes | | | ! +----------------------+ +---------------------+ ! 173: | | 416: | Right Cabinet | ! | 3 bytes padding | | Regulator A "H" msg | ! | | | 54 bytes | ! +----------------------+ +---------------------+ ! 176: | Center cabinet | 470: | | ! | Regulator C "B" msg | | 2 bytes padding | ! | 9 bytes | | | ! +----------------------+ +---------------------+ ! 185: | | 472: | Right Cabinet | ! | 3 bytes padding | | Regulator B "H" msg | ! | | | 54 bytes | ! +----------------------+ +---------------------+ ! 188: | Center cabinet | 526: | | ! | Regulator A "B" msg | | 2 bytes padding | ! | 9 bytes | | | ! +----------------------+ +---------------------+ ! 197: | | 528: | Right Cabinet | ! | 3 bytes padding | | Regulator C "H" msg | ! | | | 54 bytes | ! +----------------------+ +---------------------+ ! 200: | Center cabinet | 582: | | ! | Regulator B "B" msg | | 2 bytes padding | ! | 9 bytes | | | ! +----------------------+ +---------------------+ ! 209: | | 584: ! | 3 bytes padding | ! | | ! +----------------------+ ! 212: | Center cabinet | ! | Regulator C "B" msg | ! | 9 bytes | ! +----------------------+ ! 221: | | ! | 3 bytes padding | ! | | ! +----------------------+ ! 224: | Center cabinet | ! | Regulator A "B" msg | ! | 9 bytes | ! +----------------------+ ! 233: | | ! | 3 bytes padding | ! | | ! +----------------------+ ! 236: | Center cabinet | ! | Regulator B "B" msg | ! | 9 bytes | ! +----------------------+ ! 245: | | ! | 3 bytes padding | ! | | ! +----------------------+ ! 248: | Center cabinet | ! | Regulator C "B" msg | ! | 9 bytes | ! +----------------------+ ! 257: | | ! | 3 bytes padding | ! | | ! +----------------------+ ! 260: | Event regulator | ! | Id | ! | 8 bytes | ! +----------------------+ ! 268: | Event regulator | ! | "S" messages | ! | 54 bytes | ! +----------------------+ ! 322: ! !*** MODULE $EMBPWRDEF *** ! ! Power event message ! literal EMB$K_PWR_STATE_LENGTH = 354; literal EMB$C_PWR_STATE_LENGTH = 354; literal EMB$K_PWR_HISTORY_LENGTH = 616; literal EMB$C_PWR_HISTORY_LENGTH = 616; literal EMB$K_PWR_BAD_LENGTH = 133; literal EMB$C_PWR_BAD_LENGTH = 133; literal EMB$K_PWR_GBUS_LENGTH = 120; literal EMB$C_PWR_GBUS_LENGTH = 120; literal EMB$S_EMBPWRDEF = 616; ! Old size name - synonym literal EMB$S_EMBPWR = 616; macro EMB$L_PWR_SID = 0,0,32,0 %; ! SYSTEM ID macro EMB$W_PWR_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_PWR_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_PWR_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_PWR_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_PWR_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$B_PWR_SCS_NAME = 16,0,0,0 %; literal EMB$S_PWR_SCS_NAME = 16; ! SCS node name in ASCIC macro EMB$W_PWR_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_PWR_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_PWR_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_PWR_ENTRY = 36,0,16,0 %; ! ENTRY TYPE macro EMB$Q_PWR_TIME = 38,0,0,0 %; literal EMB$S_PWR_TIME = 8; ! TIME IN 64 BITS macro EMB$W_PWR_ERRSEQ = 46,0,16,0 %; ! ERROR SEQ ! macro EMB$Q_PWR_SWVERS = 48,0,0,0 %; literal EMB$S_PWR_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_PWR_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_PWR_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_PWR_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_PWR_HW_NAME = 65,0,0,0 %; literal EMB$S_PWR_HW_NAME = 31; ! marketing name of this system ! ! Header common to all power events ! macro EMB$L_PWR_SUMMARY = 96,0,32,0 %; ! Summary of regulators found macro EMB$Q_PWR_VERSION = 100,0,0,0 %; literal EMB$S_PWR_VERSION = 8; ! The version of laser_power.bli macro EMB$L_PWR_TYPE = 108,0,32,0 %; ! Type of power event ! ! 4 possible sub typers in the union ! ! ! This is the type EMB$K_pwr_state_event specific layout ! macro EMB$Q_PWR_STATE_TIME_CENTER_A = 112,0,0,0 %; literal EMB$S_PWR_STATE_TIME_CENTER_A = 8; ! Timestamp regulator A center cabinet macro EMB$Q_PWR_STATE_TIME_CENTER_B = 120,0,0,0 %; literal EMB$S_PWR_STATE_TIME_CENTER_B = 8; ! Timestamp regulator B center cabinet macro EMB$Q_PWR_STATE_TIME_CENTER_C = 128,0,0,0 %; literal EMB$S_PWR_STATE_TIME_CENTER_C = 8; ! Timestamp regulator C center cabinet macro EMB$Q_PWR_STATE_TIME_LEFT_A = 136,0,0,0 %; literal EMB$S_PWR_STATE_TIME_LEFT_A = 8; ! Timestamp regulator A left cabinet macro EMB$Q_PWR_STATE_TIME_LEFT_B = 144,0,0,0 %; literal EMB$S_PWR_STATE_TIME_LEFT_B = 8; ! Timestamp regulator B left cabinet macro EMB$Q_PWR_STATE_TIME_LEFT_C = 152,0,0,0 %; literal EMB$S_PWR_STATE_TIME_LEFT_C = 8; ! Timestamp regulator C left cabinet macro EMB$Q_PWR_STATE_TIME_RIGHT_A = 160,0,0,0 %; literal EMB$S_PWR_STATE_TIME_RIGHT_A = 8; ! Timestamp regulator A right cabinet macro EMB$Q_PWR_STATE_TIME_RIGHT_B = 168,0,0,0 %; literal EMB$S_PWR_STATE_TIME_RIGHT_B = 8; ! Timestamp regulator B right cabinet macro EMB$Q_PWR_STATE_TIME_RIGHT_C = 176,0,0,0 %; literal EMB$S_PWR_STATE_TIME_RIGHT_C = 8; ! Timestamp regulator C right cabinet macro EMB$T_PWR_STATE_BMSG_CENTER_A = 184,0,0,0 %; literal EMB$S_PWR_STATE_BMSG_CENTER_A = 9; ! B message regulator A center cabinet macro EMB$T_PWR_STATE_BMSG_CENTER_B = 196,0,0,0 %; literal EMB$S_PWR_STATE_BMSG_CENTER_B = 9; ! B message regulator B center cabinet macro EMB$T_PWR_STATE_BMSG_CENTER_C = 208,0,0,0 %; literal EMB$S_PWR_STATE_BMSG_CENTER_C = 9; ! B message regulator C center cabinet macro EMB$T_PWR_STATE_BMSG_LEFT_A = 220,0,0,0 %; literal EMB$S_PWR_STATE_BMSG_LEFT_A = 9; ! B message regulator A left cabinet macro EMB$T_PWR_STATE_BMSG_LEFT_B = 232,0,0,0 %; literal EMB$S_PWR_STATE_BMSG_LEFT_B = 9; ! B message regulator B left cabinet macro EMB$T_PWR_STATE_BMSG_LEFT_C = 244,0,0,0 %; literal EMB$S_PWR_STATE_BMSG_LEFT_C = 9; ! B message regulator C left cabinet macro EMB$T_PWR_STATE_BMSG_RIGHT_A = 256,0,0,0 %; literal EMB$S_PWR_STATE_BMSG_RIGHT_A = 9; ! B message regulator A right cabinet macro EMB$T_PWR_STATE_BMSG_RIGHT_B = 268,0,0,0 %; literal EMB$S_PWR_STATE_BMSG_RIGHT_B = 9; ! B message regulator B right cabinet macro EMB$T_PWR_STATE_BMSG_RIGHT_C = 280,0,0,0 %; literal EMB$S_PWR_STATE_BMSG_RIGHT_C = 9; ! B message regulator C right cabinet macro EMB$R_PWR_STATE_ID = 292,0,0,0 %; literal EMB$S_PWR_STATE_ID = 8; macro EMB$L_PWR_STATE_ID_CABINET = 292,0,32,0 %; ! Event cabinet id macro EMB$L_PWR_STATE_ID_REGULATOR = 296,0,32,0 %; ! Event regulator id macro EMB$T_PWR_STATE_SMSG = 300,0,0,0 %; literal EMB$S_PWR_STATE_SMSG = 54; ! S message from event regulator ! ! This is the type EMB$K_pwr_history_event specific layout ! macro EMB$R_HISTORY = 112,0,0,0 %; literal EMB$S_HISTORY = 504; macro EMB$T_PWR_HISTORY_HMSG_CENTER_A = 112,0,0,0 %; literal EMB$S_PWR_HISTORY_HMSG_CENTER_A = 54; ! H message regulator A center cabinet macro EMB$T_PWR_HISTORY_HMSG_CENTER_B = 168,0,0,0 %; literal EMB$S_PWR_HISTORY_HMSG_CENTER_B = 54; ! H message regulator B center cabinet macro EMB$T_PWR_HISTORY_HMSG_CENTER_C = 224,0,0,0 %; literal EMB$S_PWR_HISTORY_HMSG_CENTER_C = 54; ! H message regulator C center cabinet macro EMB$T_PWR_HISTORY_HMSG_LEFT_A = 280,0,0,0 %; literal EMB$S_PWR_HISTORY_HMSG_LEFT_A = 54; ! H message regulator A left cabinet macro EMB$T_PWR_HISTORY_HMSG_LEFT_B = 336,0,0,0 %; literal EMB$S_PWR_HISTORY_HMSG_LEFT_B = 54; ! H message regulator B left cabinet macro EMB$T_PWR_HISTORY_HMSG_LEFT_C = 392,0,0,0 %; literal EMB$S_PWR_HISTORY_HMSG_LEFT_C = 54; ! H message regulator C left cabinet macro EMB$T_PWR_HISTORY_HMSG_RIGHT_A = 448,0,0,0 %; literal EMB$S_PWR_HISTORY_HMSG_RIGHT_A = 54; ! H message regulator A right cabinet macro EMB$T_PWR_HISTORY_HMSG_RIGHT_B = 504,0,0,0 %; literal EMB$S_PWR_HISTORY_HMSG_RIGHT_B = 54; ! H message regulator B right cabinet macro EMB$T_PWR_HISTORY_HMSG_RIGHT_C = 560,0,0,0 %; literal EMB$S_PWR_HISTORY_HMSG_RIGHT_C = 54; ! H message regulator C right cabinet ! ! This is the type EMB$K_pwr_bad_event specific layout ! macro EMB$R_BAD = 112,0,0,0 %; literal EMB$S_BAD = 21; macro EMB$R_PWR_BAD_ID = 112,0,0,0 %; literal EMB$S_PWR_BAD_ID = 8; macro EMB$L_PWR_BAD_ID_CABINET = 112,0,32,0 %; ! Event cabinet id macro EMB$L_PWR_BAD_ID_REGULATOR = 116,0,32,0 %; ! Event regulator id macro EMB$L_PWR_BAD_TYPE = 120,0,32,0 %; ! Bad event type macro EMB$T_PWR_BAD_BMSG = 124,0,0,0 %; literal EMB$S_PWR_BAD_BMSG = 9; ! B message from event regulator ! ! This is the type EMB$K_gbus specific layout ! macro EMB$R_GBUS = 112,0,0,0 %; literal EMB$S_GBUS = 8; macro EMB$L_PWR_GBUS_HALT = 112,0,32,0 %; ! current GBUS$HALT register macro EMB$L_PWR_LAST_GBUS = 116,0,32,0 %; ! previous GBUS$HALT register ! ! Values in PWR_TYPE. ! literal EMB$K_PWR_state_event = 1; ! State change event literal EMB$K_PWR_history_event = 2; ! Initial history event literal EMB$K_PWR_bad_event = 3; ! Bad checksum or no ans literal EMB$K_PWR_GBUS_event = 4; ! GBUS had some bits set !*** MODULE $EMBTSDEF *** ! ! TIME STAMP MSG FORMAT ! literal EMB$K_TS_LENGTH = 96; ! LENGTH OF TIME STAMP MSG literal EMB$C_TS_LENGTH = 96; ! LENGTH OF TIME STAMP MSG literal EMB$S_EMBTSDEF = 96; ! Old size name - synonym literal EMB$S_EMBTS = 96; macro EMB$L_TS_SID = 0,0,32,0 %; ! SYSTEM ID macro EMB$W_TS_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_TS_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_TS_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_TS_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_TS_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$B_TS_SCS_NAME = 16,0,0,0 %; literal EMB$S_TS_SCS_NAME = 16; ! SCS node name in ASCIC macro EMB$W_TS_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_TS_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_TS_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_TS_ENTRY = 36,0,16,0 %; ! ENTRY TYPE macro EMB$Q_TS_TIME = 38,0,0,0 %; literal EMB$S_TS_TIME = 8; ! TIME IN 64 BITS macro EMB$W_TS_ERRSEQ = 46,0,16,0 %; ! ERROR SEQ ! macro EMB$Q_TS_SWVERS = 48,0,0,0 %; literal EMB$S_TS_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_TS_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_TS_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_TS_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_TS_HW_NAME = 65,0,0,0 %; literal EMB$S_TS_HW_NAME = 31; ! marketing name of this system !*** MODULE $EMBSSDEF *** ! ! SYSTEM SERVICE MESSAGE ! ! NOTE: SYSTEM SERVICE MESSAGE COVERS: ! ! 1) THE MESSAGES FROM THE SERVICE ! 2) OPERATOR MESSAGES ! 3) NETWORK MESSAGES ! ! ONLY THE TYPE FIELD IS DIFERENT ! literal EMB$K_SS_LENGTH = 98; ! LENGTH OF CONSTANT PART literal EMB$C_SS_LENGTH = 98; ! LENGTH OF CONSTANT PART literal EMB$S_EMBSSDEF = 99; ! Old size name - synonym literal EMB$S_EMBSS = 99; macro EMB$L_SS_SID = 0,0,32,0 %; ! SYSTEM ID macro EMB$W_SS_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_SS_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_SS_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_SS_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_SS_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$B_SS_SCS_NAME = 16,0,0,0 %; literal EMB$S_SS_SCS_NAME = 16; ! SCS node name in ASCIC macro EMB$W_SS_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_SS_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_SS_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_SS_ENTRY = 36,0,16,0 %; ! ENTRY TYPE macro EMB$Q_SS_TIME = 38,0,0,0 %; literal EMB$S_SS_TIME = 8; ! TIME IN 64 BITS macro EMB$W_SS_ERRSEQ = 46,0,16,0 %; ! ERROR SEQUENCE NUMBER macro EMB$Q_SS_SWVERS = 48,0,0,0 %; literal EMB$S_SS_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_SS_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_SS_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_SS_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_SS_HW_NAME = 65,0,0,0 %; literal EMB$S_SS_HW_NAME = 31; ! marketing name of this system macro EMB$W_SS_MSGSZ = 96,0,16,0 %; ! MESSAGE TEXT SIZE IN BYTES macro EMB$B_SS_MSGTXT = 98,0,8,0 %; ! FIRST BYTE OF MESSAGE TEXT !*** MODULE $EMBVMDEF *** ! ! VOLUME MOUNT/DISMOUNT MESSAGE TYPE ! literal EMB$K_VM_LENGTH = 158; ! LENGTH OF BUFFER literal EMB$C_VM_LENGTH = 158; ! LENGTH OF BUFFER literal EMB$S_EMBVMDEF = 158; ! Old size name - synonym literal EMB$S_EMBVM = 158; macro EMB$L_VM_SID = 0,0,32,0 %; ! SYSTEM ID macro EMB$W_VM_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_VM_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_VM_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_VM_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_VM_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$B_VM_SCS_NAME = 16,0,0,0 %; literal EMB$S_VM_SCS_NAME = 16; ! SCS node name in ASCIC macro EMB$W_VM_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_VM_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_VM_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_VM_ENTRY = 36,0,16,0 %; ! ENTRY TYPE = EMB$K_VM OR EMB$K_VD macro EMB$Q_VM_TIME = 38,0,0,0 %; literal EMB$S_VM_TIME = 8; ! TIME IN 64 BIT FORMAT macro EMB$W_VM_ERRSEQ = 46,0,16,0 %; ! ERROR SEQUENCE NUMBER macro EMB$Q_VM_SWVERS = 48,0,0,0 %; literal EMB$S_VM_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_VM_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_VM_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_VM_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_VM_HW_NAME = 65,0,0,0 %; literal EMB$S_VM_HW_NAME = 31; ! marketing name of this system macro EMB$L_VM_OWNUIC = 96,0,32,0 %; ! OWNER UIC OF THE VOLUME macro EMB$L_VM_ERRCNT = 100,0,32,0 %; ! UNIT ERROR COUNT FROM UCB macro EMB$L_VM_OPRCNT = 104,0,32,0 %; ! UNIT OPERATION COUNT FROM UCB macro EMB$W_VM_UNIT = 108,0,16,0 %; ! DEVICE UNIT NUMBER macro EMB$B_VM_NAMLNG = 110,0,8,0 %; ! LENGTH OF DEVICE GENERIC NAME macro EMB$T_VM_NAMTXT = 111,0,0,0 %; literal EMB$S_VM_NAMTXT = 31; ! DEVICE GENERIC NAME macro EMB$W_VM_VOLNUM = 142,0,16,0 %; ! VOLUME NUMBER WITHIN SET macro EMB$W_VM_NUMSET = 144,0,16,0 %; ! NUMBER OF VOLUMES WITHIN SET macro EMB$T_VM_LABEL = 146,0,0,0 %; literal EMB$S_VM_LABEL = 12; ! VOLUME LABEL !*** MODULE $EMBSUDEF *** ! ! SYSTEM STARTUP MESSAGE ! literal EMB$K_SU_LENGTH = 100; ! LENGTH OF MESSAGE literal EMB$C_SU_LENGTH = 100; ! LENGTH OF MESSAGE literal EMB$S_EMBSUDEF = 100; ! Old size name - synonym literal EMB$S_EMBSU = 100; macro EMB$L_SU_SID = 0,0,32,0 %; ! SYSTEM ID macro EMB$W_SU_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_SU_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_SU_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_SU_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_SU_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$B_SU_SCS_NAME = 16,0,0,0 %; literal EMB$S_SU_SCS_NAME = 16; ! SCS node name in ASCIC macro EMB$W_SU_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_SU_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_SU_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_SU_ENTRY = 36,0,16,0 %; ! ENTRY TYPE (IE: BOOT OR POWER RECOVERY) macro EMB$Q_SU_TIME = 38,0,0,0 %; literal EMB$S_SU_TIME = 8; ! CONTENTS OF SYSTEM TIME QUADWORD macro EMB$W_SU_ERRSEQ = 46,0,16,0 %; ! ERROR SEQUENCE NUMBER macro EMB$Q_SU_SWVERS = 48,0,0,0 %; literal EMB$S_SU_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_SU_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_SU_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_SU_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_SU_HW_NAME = 65,0,0,0 %; literal EMB$S_SU_HW_NAME = 31; ! marketing name of this system macro EMB$L_SU_DAYTIM = 96,0,32,0 %; ! CONTENTS OF TIME OF DAY CLOCK !*** MODULE $EMBMCDEF *** ! ! MACHINE CHECK LOG BUFFER FORMAT ! literal EMB$K_MC_LENGTH = 144; ! LENGTH OF MACHINE CHECK FRAME literal EMB$C_MC_LENGTH = 144; ! LENGTH OF MACHINE CHECK FRAME literal EMB$S_EMBMCDEF = 144; ! Old size name - synonym literal EMB$S_EMBMC = 144; macro EMB$L_MC_SID = 0,0,32,0 %; ! SYSTEM ID macro EMB$W_MC_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_MC_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_MC_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_MC_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_MC_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$B_MC_SCS_NAME = 16,0,0,0 %; literal EMB$S_MC_SCS_NAME = 16; ! SCS node name in ASCIC macro EMB$W_MC_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_MC_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_MC_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_MC_ENTRY = 36,0,16,0 %; ! ENTRY TYPE macro EMB$Q_MC_TIME = 38,0,0,0 %; literal EMB$S_MC_TIME = 8; ! TIME IN 64 BITS macro EMB$W_MC_ERRSEQ = 46,0,16,0 %; ! ERROR SEQUENCE NUMBER macro EMB$Q_MC_SWVERS = 48,0,0,0 %; literal EMB$S_MC_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_MC_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_MC_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_MC_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_MC_HW_NAME = 65,0,0,0 %; literal EMB$S_MC_HW_NAME = 31; ! marketing name of this system macro EMB$B_MC_SUMCOD = 96,0,8,0 %; ! SUMMARY CODE macro EMB$B_MC_TOPF = 97,0,8,0 %; ! TIME OUT PENDING FLAG macro EMB$B_MC_OPCODE = 98,0,8,0 %; ! OPCODE OF INSTRUCTION CAUSING CHECK macro EMB$B_MC_CACHEF = 99,0,8,0 %; ! CACHE DISABLE FLAG, 1=GROUP 0, 2=G 1 macro EMB$L_MC_CES = 100,0,32,0 %; ! CPU ERROR STATUS macro EMB$L_MC_UPC = 104,0,32,1 %; ! MICRO-PC AT FAULT TIME macro EMB$L_MC_VA = 108,0,32,1 %; ! VIRTUAL ADDRESS AT FAULT TIME macro EMB$L_MC_D = 112,0,32,0 %; ! CPU D REGISTER AT FAULT TIME macro EMB$L_MC_TBER0 = 116,0,32,0 %; ! TRANSLATION BUFFER STATUS REG 0 macro EMB$L_MC_TBER1 = 120,0,32,0 %; ! TRANSLATION BUFFER STATUS REG 1 macro EMB$L_MC_TIMOAD = 124,0,32,1 %; ! PHYSICAL ADDRESS CAUSING SBI TIMEOUT macro EMB$L_MC_PARITY = 128,0,32,0 %; ! CACHE STATUS REGISTER macro EMB$L_MC_SBIERR = 132,0,32,0 %; ! SBI ERROR REGISTER macro EMB$L_MC_PC = 136,0,32,1 %; ! PC OF INSTRUCTION CAUSING CHECK macro EMB$L_MC_PSL = 140,0,32,0 %; ! PSL OF MACHINE AT FAULT TIME ! ++ ! ! +---------------------+ <- R2, after call to ALLOCEMB ! | | ^ ! | EMB Header | | ! | | v ! +---------------------+ - #EMB$K_HD_LENGTH ! |(user portion of EMB)| ! | | ! | EMBSE header | ! | | ! +- - - - - - - - - - -+ ! | XXX | <- EMB$L_SE_MEMDSC_OFFSET ! +- - - - - - - - - - -+ ! | | ! | | ! +- - - - - - - - - - -+ ! | YYY | <- EMB$L_SE_FPRINT_OFFSET ! +---------------------+ <- #EMB$K_SE_FIXED_HD_LENGTH ! | memory descriptor | <- Start of memdsc = XXX(R2) ! | | ! +---------------------+ <- Start of fprints = YYY(R2) ! | footprints | ! | | ! | | ! | | ! +---------------------+ ! ! ! Depending on the entry that is logged, it is possible that one or both of the ! memory descriptor and footprints are absent from the errorlog entry. If ! EMB$L_SE_MEMDSC_OFFSET is zero, this indicates there is no memory descriptor ! in this errorlog entry. Likewise, if EMB$L_SE_FPRINT_OFFSET is zero, there ! is no footprint section. ! ! The memory descriptor is system-dependent and represent the ! memory configuration unique to each system. For example, VAX 6000 systems ! use a memory descriptor that describes each memory controller (MS62A, MS65A) ! in the system. Eight longwords of descriptor may be used to describe EACH ! controller in the system. ! ! See note in header comments, but note that it is possible that the memory ! descriptor and/or the footprint sections are not present in the errorlog ! entry. SE$L_MEMDSC_OFFSET = 0 indicates there is no memory ! descriptor present -- likewise if SE$L_FPRINT_OFFSET = 0, there ! are no footprints supplied. ! -- !*** MODULE $EMBSEDEF *** ! ! SOFT ECC DETECTED ERRORS ! literal EMB$K_SE_REVISION = 3; ! Revision field literal EMB$C_SE_REVISION = 3; ! Revision field literal EMB$M_SE_CRD_FLG_DISABLED = %X'1'; literal EMB$M_SE_CRD_FLG_LOST_INFO = %X'2'; literal EMB$M_SE_RSN_INIT_ERR = %X'1'; literal EMB$M_SE_RSN_FPRINTS_FULL = %X'2'; literal EMB$M_SE_RSN_SHUTDOWN = %X'4'; literal EMB$M_SE_RSN_DOMAIN_GREW = %X'8'; literal EMB$M_SE_RSN_BADPGS = %X'10'; literal EMB$K_SE_FIXED_HD_LENGTH = 128; ! Size of FIXED ERL HEADER literal EMB$C_SE_FIXED_HD_LENGTH = 128; ! Size of FIXED ERL HEADER literal EMB$S_EMBSEDEF = 128; ! Old size name - synonym ! ++ literal EMB$S_EMBSE = 128; macro EMB$L_SE_SID = 0,0,32,0 %; ! SYSTEM ID macro EMB$W_SE_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_SE_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_SE_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_SE_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_SE_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$B_SE_SCS_NAME = 16,0,0,0 %; literal EMB$S_SE_SCS_NAME = 16; ! SCS node name in ASCIC macro EMB$W_SE_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_SE_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_SE_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_SE_ENTRY = 36,0,16,0 %; ! ENTRY TYPE macro EMB$Q_SE_TIME = 38,0,0,0 %; literal EMB$S_SE_TIME = 8; ! TIME IN 64 BITS macro EMB$W_SE_ERRSEQ = 46,0,16,0 %; ! ERROR SEQUENCE NUMBER macro EMB$Q_SE_SWVERS = 48,0,0,0 %; literal EMB$S_SE_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_SE_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_SE_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_SE_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_SE_HW_NAME = 65,0,0,0 %; literal EMB$S_SE_HW_NAME = 31; ! marketing name of this system ! ! Start of CRD info ! macro EMB$W_SE_REVISION = 96,0,16,0 %; ! ERL revision field macro EMB$W_SE_CRD_FLAGS = 98,0,16,0 %; ! ERL flags macro EMB$V_SE_CRD_FLG_DISABLED = 98,0,1,0 %; ! Indicates CRD init processing is not complete. ! No scrubbing/replacement til flag is cleared macro EMB$V_SE_CRD_FLG_LOST_INFO = 98,1,1,0 %; ! Lost information ! ! LOG_REASON corresponds to the field CRD_FOOT$W_LOG_REASON defined in ! $CRD_FOOT. If this field is ever changed, appropriate action must ! be taken in CRD_FOOT as well. ! macro EMB$W_SE_LOG_REASON = 100,0,16,0 %; ! Reason for this ERL entry macro EMB$V_SE_RSN_INIT_ERR = 100,0,1,0 %; ! Error occurred during CRDERR initialization macro EMB$V_SE_RSN_FPRINTS_FULL = 100,1,1,0 %; ! Entries logged because all footprints in use macro EMB$V_SE_RSN_SHUTDOWN = 100,2,1,0 %; ! Entries logged at shutdown macro EMB$V_SE_RSN_DOMAIN_GREW = 100,3,1,0 %; ! Set when ADDR_CUM in a fprint goes non-zero macro EMB$V_SE_RSN_BADPGS = 100,4,1,0 %; ! Indicates a non-zero RPB bad page count macro EMB$W_SE_N_OF_M = 102,0,16,0 %; ! "N of M" field. Ie., packet "1" of "3" macro EMB$L_SE_HWRPB_BADPGS = 104,0,32,0 %; ! RPB bad page count macro EMB$L_SE_MEMDSC_SIZE = 108,0,32,0 %; ! variable SYSLOA memdsc size macro EMB$L_SE_MEMDSC_OFFSET = 112,0,32,0 %; ! Offset from beg. of EMB to start of memdsc macro EMB$L_SE_NUM_FPRINTS = 116,0,32,0 %; ! Number of footprints in this EMB macro EMB$L_SE_FPRINT_SIZE = 120,0,32,0 %; ! Size, in bytes, of each fprint macro EMB$L_SE_FPRINT_OFFSET = 124,0,32,0 %; ! Offset from beg. of EMB to start of fprints ! End of *Fixed portion* of the SE$ header ! -- literal CRD_FOOT$K_MAX_FOOTPRINTS = 16; ! Max # of fprints literal CRD_FOOT$M_SFLAGS_BUSY = %X'1'; literal CRD_FOOT$M_SFLAGS_SW_SCRUBBED = %X'2'; literal CRD_FOOT$M_CALLER_NOSCRUB = %X'1'; literal CRD_FOOT$M_CALLER_NOREPLACE = %X'2'; literal CRD_FOOT$M_CALLER_MULE = %X'4'; literal CRD_FOOT$M_SCRMSK_PFNTOOBIG = %X'1'; literal CRD_FOOT$M_SCRMSK_MCHK = %X'2'; literal CRD_FOOT$M_SCRMSK_MAPFAILED = %X'4'; literal CRD_FOOT$M_SCRMSK_UNMAPFAILED = %X'8'; literal CRD_FOOT$M_SCRMSK_TOOMANYRETRY = %X'10'; literal CRD_FOOT$K_LENGTH = 80; ! Length of argument area literal CRD_FOOT$C_LENGTH = 80; ! Length of argument area literal CRD_FOOT$S_CRD_FOOTDEF = 80; ! Old size name - synonym literal CRD_FOOT$S_CRD_FOOT = 80; macro CRD_FOOT$Q_FOOTPRINT = 0,0,0,0 %; literal CRD_FOOT$S_FOOTPRINT = 8; ! 64-bits of error syndrome macro CRD_FOOT$Q_SYSTIME = 8,0,0,0 %; literal CRD_FOOT$S_SYSTIME = 8; ! System time of the CRD macro CRD_FOOT$Q_ADDR_LOW = 16,0,0,0 %; literal CRD_FOOT$S_ADDR_LOW = 8; ! 64-bit lowest address associated with this CRD macro CRD_FOOT$Q_ADDR_HIGH = 24,0,0,0 %; literal CRD_FOOT$S_ADDR_HIGH = 8; ! 64-bit highest address associated with this CRD macro CRD_FOOT$Q_ADDR_CUM = 32,0,0,0 %; literal CRD_FOOT$S_ADDR_CUM = 8; ! 64-bit bitmask of lowest address XORed, then ORed with all new addresses macro CRD_FOOT$L_SCRUB_BLKSIZ = 40,0,32,0 %; ! Size, in bytes, of area to scrub macro CRD_FOOT$W_STATIC_FLAGS = 44,0,16,0 %; ! Footprint flags macro CRD_FOOT$V_SFLAGS_BUSY = 44,0,1,0 %; ! Indicates this CRD_FOOT in use macro CRD_FOOT$V_SFLAGS_SW_SCRUBBED = 44,1,1,0 %; ! CRD scrubbed ! The CRD_FOOT$W_LOG_REASON contains a bitmask of reasons for logging a ! particular footprint. These bit definitions must line up with those in ! $CRD_EMBDEF. In particular, the field CRD_EMB$W_LOG_REASON defines the ! acceptable log reason bits. [LIB]CRD_EMBDEF.SDL should be updated if new ! reasons need to be defined. ! macro CRD_FOOT$W_LOG_REASON = 46,0,16,0 %; ! Reasons for logging this fprint macro CRD_FOOT$L_CALLER_FLAGS = 48,0,32,0 %; ! Status bits for this CALLER macro CRD_FOOT$V_CALLER_NOSCRUB = 48,0,1,0 %; ! Only update the footprint info - do not attempt scrub macro CRD_FOOT$V_CALLER_NOREPLACE = 48,1,1,0 %; ! Only update the footprint info - do not attempt replace macro CRD_FOOT$V_CALLER_MULE = 48,2,1,0 %; ! multiple error found macro CRD_FOOT$L_SCRUB_FAILMSK = 52,0,32,0 %; ! Contains collective reasons why page couldn't be scrubbed macro CRD_FOOT$V_SCRMSK_PFNTOOBIG = 52,0,1,0 %; ! Footprint PFN was greater than the system maximum. macro CRD_FOOT$V_SCRMSK_MCHK = 52,1,1,0 %; ! Machine check occurred during scrub macro CRD_FOOT$V_SCRMSK_MAPFAILED = 52,2,1,0 %; ! Mapping the physical addr failed macro CRD_FOOT$V_SCRMSK_UNMAPFAILED = 52,3,1,0 %; ! Unmapping the physical addr failed macro CRD_FOOT$V_SCRMSK_TOOMANYRETRY = 52,4,1,0 %; ! Too many retries macro CRD_FOOT$L_MATCH_CNT = 56,0,32,0 %; ! Total CRDs which match this footprint macro CRD_FOOT$L_SCRUB_CNT = 60,0,32,0 %; ! Number of times a page was scrubbed macro CRD_FOOT$Q_FIRSTSCRUB_TIME = 64,0,0,0 %; literal CRD_FOOT$S_FIRSTSCRUB_TIME = 8; ! Time at which first scrubbed CRD matched footprint macro CRD_FOOT$Q_LASTSCRUB_TIME = 72,0,0,0 %; literal CRD_FOOT$S_LASTSCRUB_TIME = 8; ! Time at which last CRD matched footprint after scrubbing literal CRD_ARG$K_LENGTH = 32; literal CRD_ARG$C_LENGTH = 32; literal CRD_ARG$S_CRD_ARGDEF = 32; ! Old size name - synonym literal CRD_ARG$S_CRD_ARG = 32; macro CRD_ARG$Q_FOOTPRINT = 0,0,0,0 %; literal CRD_ARG$S_FOOTPRINT = 8; ! 64-bits of error syndrome macro CRD_ARG$Q_SYSTIME = 8,0,0,0 %; literal CRD_ARG$S_SYSTIME = 8; ! System time of the CRD macro CRD_ARG$Q_ADDRESS = 16,0,0,0 %; literal CRD_ARG$S_ADDRESS = 8; ! 64-bit address macro CRD_ARG$L_FLAGS = 24,0,32,0 %; ! flags macro CRD_ARG$L_SCRUB_BLKSIZ = 28,0,32,0 %; ! Size, in bytes, of area to scrub literal CRD$K_SCRUB_RETRY = 3; ! Number of retries ! Define fields in EXE$GL_CRD_CONTROL literal CRD_CONTROL$M_CRD_ENABLE = %X'1'; literal CRD_CONTROL$M_SCRUB_ENABLE = %X'2'; literal CRD_CONTROL$M_PAGE_REPLACE_ENABLE = %X'4'; literal CRD_CONTROL$M_FORCE_ALL_PFNDB = %X'8'; literal CRD_CONTROL$M_EXT_CRD_ONLY = %X'10'; literal CRD_CONTROL$M_LOAD_SMDRIVER = %X'20'; literal CRD_CONTROL$M_THROTTLE_DISABLE = %X'40'; literal CRD_CONTROL$M_SEL_DISABLE = %X'80'; literal CRD_CONTROL$S_CRD_CONTROL = 4; macro CRD_CONTROL$L_CRD_CONTROL = 0,0,32,1 %; macro CRD_CONTROL$V_CRD_ENABLE = 0,0,1,0 %; ! Enable CRD processing macro CRD_CONTROL$V_SCRUB_ENABLE = 0,1,1,0 %; ! CRD scrubbing enabled macro CRD_CONTROL$V_PAGE_REPLACE_ENABLE = 0,2,1,0 %; ! Enable bad page replacement macro CRD_CONTROL$V_FORCE_ALL_PFNDB = 0,3,1,0 %; ! Force all pages in PFN db macro CRD_CONTROL$V_EXT_CRD_ONLY = 0,4,1,0 %; ! Log only Extended CRDs macro CRD_CONTROL$V_LOAD_SMDRIVER = 0,5,1,0 %; ! Load SMDRIVER macro CRD_CONTROL$V_THROTTLE_DISABLE = 0,6,1,0 %; ! Disable CRD throttling when set macro CRD_CONTROL$V_SEL_DISABLE = 0,7,1,0 %; ! Disable SEL Polling when set macro CRD_CONTROL$W_SYS_SPECIFIC = 2,0,16,0 %; ! Reserved for system-specific bits !*** MODULE $EMBSBDEF *** ! ! SBI FAULT BUFFER FORMAT AND ASYNCHRONOUS WRITE ERROR FORMAT ! literal EMB$K_SB_LENGTH = 252; ! LENGTH OF SBI ERROR BUFFER literal EMB$C_SB_LENGTH = 252; ! LENGTH OF SBI ERROR BUFFER literal EMB$S_EMBSBDEF = 252; ! Old size name - synonym literal EMB$S_EMBSB = 252; macro EMB$L_SB_SID = 0,0,32,0 %; ! SYSTEM ID macro EMB$W_SB_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_SB_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_SB_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_SB_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_SB_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$B_SB_SCS_NAME = 16,0,0,0 %; literal EMB$S_SB_SCS_NAME = 16; ! SCS node name in ASCIC macro EMB$W_SB_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_SB_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_SB_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_SB_ENTRY = 36,0,16,0 %; ! ENTRY TYPE macro EMB$Q_SB_TIME = 38,0,0,0 %; literal EMB$S_SB_TIME = 8; ! TIME IN 64 BITS macro EMB$W_SB_ERRSEQ = 46,0,16,0 %; ! ERROR SEQUENCE NUMBER macro EMB$Q_SB_SWVERS = 48,0,0,0 %; literal EMB$S_SB_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_SB_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_SB_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_SB_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_SB_HW_NAME = 65,0,0,0 %; literal EMB$S_SB_HW_NAME = 31; ! marketing name of this system macro EMB$L_SB_FAULT = 96,0,32,0 %; ! SBI FAULT/STATUS REGISTER macro EMB$L_SB_SILCMP = 100,0,32,0 %; ! SBI SILO COMPARATOR macro EMB$L_SB_MAINT = 104,0,32,0 %; ! SBI MAINTENANCE macro EMB$L_SB_ERROR = 108,0,32,0 %; ! SBI ERROR REG macro EMB$L_SB_TIMOUT = 112,0,32,0 %; ! SBI TIMEOUT REG macro EMB$L_SB_SILO = 116,0,0,0 %; literal EMB$S_SB_SILO = 64; ! SBI SILO REG macro EMB$L_SB_SBIRGS = 180,0,0,0 %; literal EMB$S_SB_SBIRGS = 64; ! REGISTER A'S ON BUS (OR 0) macro EMB$L_SB_PC = 244,0,32,1 %; ! PC OF INSTRUCTION AT FAULT TIME macro EMB$L_SB_PSL = 248,0,32,0 %; ! PSL OF MACHINE AT FAULT TIME !*** MODULE $EMBUIDEF *** ! ! UNDEFINED ADAPTER INTERRUPT BUFFER FORMAT ! literal EMB$K_UI_LENGTH = 104; ! LENGTH OF MESSAGE literal EMB$C_UI_LENGTH = 104; ! LENGTH OF MESSAGE literal EMB$S_EMBUIDEF = 104; ! Old size name - synonym literal EMB$S_EMBUI = 104; macro EMB$L_UI_SID = 0,0,32,0 %; ! SYSTEM ID macro EMB$W_UI_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_UI_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_UI_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_UI_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_UI_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$B_UI_SCS_NAME = 16,0,0,0 %; literal EMB$S_UI_SCS_NAME = 16; ! SCS node name in ASCIC macro EMB$W_UI_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_UI_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_UI_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_UI_ENTRY = 36,0,16,0 %; ! ENTRY TYPE macro EMB$Q_UI_TIME = 38,0,0,0 %; literal EMB$S_UI_TIME = 8; ! TIME IN 64 BITS macro EMB$W_UI_ERRSEQ = 46,0,16,0 %; ! ERROR SEQUENCE NUMBER macro EMB$Q_UI_SWVERS = 48,0,0,0 %; literal EMB$S_UI_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_UI_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_UI_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_UI_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_UI_HW_NAME = 65,0,0,0 %; literal EMB$S_UI_HW_NAME = 31; ! marketing name of this system macro EMB$L_UI_TR = 96,0,32,0 %; ! ADAPTER TR NUMBER macro EMB$L_UI_CSR = 100,0,32,0 %; ! ADAPTER CONGIGURATION STATUS REGISTER !*** MODULE $EMBUEDEF *** ! ! ERROR BUFFER FORMAT FOR UNIBUS ERROR SUMMARY REGISTER ! ***** USED ONLY BY 11/730 **** ! literal EMB$K_UE_LENGTH = 100; ! LENGTH OF MESSAGE literal EMB$C_UE_LENGTH = 100; ! LENGTH OF MESSAGE literal EMB$S_EMBUEDEF = 100; ! Old size name - synonym literal EMB$S_EMBUE = 100; macro EMB$L_UE_SID = 0,0,32,0 %; ! SYSTEM ID macro EMB$W_UE_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_UE_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_UE_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_UE_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_UE_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$B_UE_SCS_NAME = 16,0,0,0 %; literal EMB$S_UE_SCS_NAME = 16; ! SCS node name in ASCIC macro EMB$W_UE_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_UE_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_UE_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_UE_ENTRY = 36,0,16,0 %; ! ENTRY TYPE macro EMB$Q_UE_TIME = 38,0,0,0 %; literal EMB$S_UE_TIME = 8; ! TIME IN 64 BITS macro EMB$W_UE_ERRSEQ = 46,0,16,0 %; ! ERROR SEQUENCE NUMBER macro EMB$Q_UE_SWVERS = 48,0,0,0 %; literal EMB$S_UE_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_UE_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_UE_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_UE_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_UE_HW_NAME = 65,0,0,0 %; literal EMB$S_UE_HW_NAME = 31; ! marketing name of this system macro EMB$L_UE_UBERR = 96,0,32,0 %; ! UNIBUS ERROR REGISTER !*** MODULE $EMBSPDEF *** ! ! ERROR BUFFER FORMAT FOR SAVING SOFTWARE PARAMETERS FOR CLASS DRIVER THAT ! CORRESPOND TO A LOGGED MESSAGE (SEE EMBLMDEF BELOW) ORIGINATING ! IN AN INTELLIGENT MASS STORAGE CONTROLLER. ! literal EMB$K_SP_LENGTH = 184; literal EMB$C_SP_LENGTH = 184; literal EMB$S_EMBSPDEF = 184; ! Old size name - synonym literal EMB$S_EMBSP = 184; macro EMB$L_SP_SID = 0,0,32,0 %; ! System ID macro EMB$W_SP_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_SP_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_SP_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_SP_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_SP_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$B_SP_SCS_NAME = 16,0,0,0 %; literal EMB$S_SP_SCS_NAME = 16; ! SCS node name in ASCIC macro EMB$W_SP_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_SP_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_SP_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_SP_ENTRY = 36,0,16,0 %; ! Entry type (of this errorlog buffer) macro EMB$Q_SP_TIME = 38,0,0,0 %; literal EMB$S_SP_TIME = 8; ! Time this entry created macro EMB$W_SP_ERRSEQ = 46,0,16,0 %; ! Error Sequence Number macro EMB$Q_SP_SWVERS = 48,0,0,0 %; literal EMB$S_SP_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_SP_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_SP_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_SP_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_SP_HW_NAME = 65,0,0,0 %; literal EMB$S_SP_HW_NAME = 31; ! marketing name of this system macro EMB$B_SP_CLASS = 96,0,8,0 %; ! Device Class macro EMB$B_SP_TYPE = 97,0,8,0 %; ! Device Type macro EMB$L_SP_BOFF = 98,0,32,0 %; ! Byte OFFset of data transfer macro EMB$L_SP_BCNT = 102,0,32,0 %; ! Byte Count of data transfer macro EMB$L_SP_MEDIA = 106,0,32,0 %; ! Media address (LBN) of data transfer macro EMB$L_SP_RQPID = 110,0,32,0 %; ! Requesting PID macro EMB$Q_SP_IOSB = 114,0,0,0 %; literal EMB$S_SP_IOSB = 8; ! Final I/O status macro EMB$L_SP_FUNC = 122,0,32,0 %; ! I/O function code macro EMB$W_SP_UNIT = 126,0,16,0 %; ! Unit number of drive macro EMB$L_SP_OPCNT = 128,0,32,0 %; ! Cummulative operation count this unit macro EMB$L_SP_ERRCNT = 132,0,32,0 %; ! Cummulative error count for this unit macro EMB$L_SP_UCBSTS = 136,0,32,0 %; ! Copy of UCB$W_STS field macro EMB$L_SP_OWNUIC = 140,0,32,0 %; ! Unit's owner's UIC macro EMB$L_SP_CHAR = 144,0,32,0 %; ! Device Characteristics macro EMB$L_SP_CMDREF = 148,0,32,0 %; ! Command Reference number (RSPID) macro EMB$T_SP_DEVNAM = 152,0,0,0 %; literal EMB$S_SP_DEVNAM = 32; ! Device name !*** MODULE $EMBLMDEF *** ! ! LOGGED MESSAGE (DEVICE DEPENDENT CONTENTS). DRIVER LOGS MESSAGE ! WHICH MAY COME DIRECT FROM INTELLIGENT MASS STORAGE CONTROLLER. ! literal EMB$K_LM_LENGTH = 162; literal EMB$C_LM_LENGTH = 162; literal EMB$S_EMBLMDEF = 162; ! Old size name - synonym literal EMB$S_EMBLM = 162; macro EMB$L_LM_SID = 0,0,32,0 %; ! System ID macro EMB$W_LM_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_LM_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_LM_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_LM_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_LM_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$B_LM_SCS_NAME = 16,0,0,0 %; literal EMB$S_LM_SCS_NAME = 16; ! SCS node name in ASCIC macro EMB$W_LM_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_LM_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_LM_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_LM_ENTRY = 36,0,16,0 %; ! Entry type (i.e. Logged Message) macro EMB$Q_LM_TIME = 38,0,0,0 %; literal EMB$S_LM_TIME = 8; ! Time this entry created macro EMB$W_LM_ERRSEQ = 46,0,16,0 %; ! Error sequence number macro EMB$Q_LM_SWVERS = 48,0,0,0 %; literal EMB$S_LM_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_LM_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_LM_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_LM_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_LM_HW_NAME = 65,0,0,0 %; literal EMB$S_LM_HW_NAME = 31; ! marketing name of this system macro EMB$B_LM_CLASS = 96,0,8,0 %; ! Device Class macro EMB$B_LM_TYPE = 97,0,8,0 %; ! Device Type macro EMB$W_LM_UNIT = 98,0,16,0 %; ! Device unit number macro EMB$T_LM_DEVNAM = 100,0,0,0 %; literal EMB$S_LM_DEVNAM = 32; ! Device name macro EMB$W_LM_MSGTYP = 132,0,16,0 %; ! Type of logged message macro EMB$T_LM_DTNAME = 134,0,0,0 %; literal EMB$S_LM_DTNAME = 28; ! Device type name ! counted string !*** MODULE $EMBLTDEF *** ! ! LOGGED MESSAGE MESSAGE TYPES ! literal EMB$C_DM = 1; ! Disk MSCP message literal EMB$K_DM = 1; ! Disk MSCP message literal EMB$C_TM = 2; ! Tape MSCP message literal EMB$K_TM = 2; ! Tape MSCP message literal EMB$C_PM = 3; ! Port (CI) message literal EMB$K_PM = 3; ! Port (CI) message literal EMB$C_UM = 4; ! Port (UDA) message literal EMB$K_UM = 4; ! Port (UDA) message literal EMB$C_AVATN = 5; ! Available Attention Message literal EMB$K_AVATN = 5; ! Available Attention Message literal EMB$C_DUPUN = 6; ! Duplicate Unit ! Attention Message literal EMB$K_DUPUN = 6; ! Duplicate Unit ! Attention Message literal EMB$C_IVCMD = 7; ! Invalid Command Log message. literal EMB$K_IVCMD = 7; ! Invalid Command Log message. literal EMB$C_ACPTH = 8; ! Access Path Attention Message literal EMB$K_ACPTH = 8; ! Access Path Attention Message literal EMB$C_INVSTS = 9; ! Invalid Status in End Message literal EMB$K_INVSTS = 9; ! Invalid Status in End Message literal EMB$C_INVATT = 10; ! Invalid Attention Message literal EMB$K_INVATT = 10; ! Invalid Attention Message literal EMB$C_NOUNIT_DG = 11; ! No unit in Datagram literal EMB$K_NOUNIT_DG = 11; ! No unit in Datagram literal EMB$C_SSTFAIL = 12; ! Self test failed. literal EMB$K_SSTFAIL = 12; ! Self test failed. literal EMB$C_KDB50 = 13; ! KDB50 error detected. literal EMB$K_KDB50 = 13; ! KDB50 error detected. ! ! The CTLRES_x fields below indicate that an MSCP controller was ! told to reset itself by a class driver because the controller ! is broken or confused. (To an HSC, this will cause a reboot.) ! The first three (INIT, INVMSG and IMTMO) do not have an MSCP end ! message logged with them. ! literal EMB$C_CTLRES_INIT = 14; ! An error occurred during or the connection vanished before completing literal EMB$K_CTLRES_INIT = 14; ! the initial handshake with the class driver. literal EMB$C_CTLRES_INVMSG = 15; ! An invalid message was received from the controller. The offending literal EMB$K_CTLRES_INVMSG = 15; ! message has been previously logged as INVATT or INVSTS. literal EMB$C_CTLRES_IMTMO = 16; ! An immediate mode command has failed to complete within the timeout literal EMB$K_CTLRES_IMTMO = 16; ! period, indicating a broken or wedged controller. literal EMB$C_CTLRES_TMO = 17; ! No progress was made on a command during the timeout period. The MSCP literal EMB$K_CTLRES_TMO = 17; ! GET COMMAND STATUS end message which determined this is included. ! literal EMB$C_BADRSPID = 18; ! A message with an invalid RSPID was received by the class driver. literal EMB$K_BADRSPID = 18; ! The offending MSCP message is included. ! literal EMB$C_BVPSSP = 19; ! Port message for BVP Storage Systems Port literal EMB$K_BVPSSP = 19; ! Port message for BVP Storage Systems Port literal EMB$C_NIPM = 20; ! Port (NI) message literal EMB$K_NIPM = 20; ! Port (NI) message literal EMB$C_LDR_ERR = 21; ! Media Loader error message literal EMB$K_LDR_ERR = 21; ! Media Loader error message !*** MODULE $EMBETDEF *** ! ! ERROR MESSAGE ENTRY TYPE DEFINITIONS ! literal EMB$C_DE = 1; ! I/A/V Device Error literal EMB$K_DE = 1; ! I/A/V Device Error literal EMB$C_MC = 2; ! A/V Machine Check 670 - Processor UCE literal EMB$K_MC = 2; ! A/V Machine Check 670 - Processor UCE literal EMB$C_MCHECK_670 = 2; ! A Machine Check 670 - Processor UCE literal EMB$K_MCHECK_670 = 2; ! A Machine Check 670 - Processor UCE literal EMB$C_MCA_CPU = 2; ! I Machine Check Abort - Processor literal EMB$K_MCA_CPU = 2; ! I Machine Check Abort - Processor literal EMB$C_SYNERR = 3; ! V Syndrome Error literal EMB$K_SYNERR = 3; ! V Syndrome Error literal EMB$C_BE = 4; ! V Bus Error literal EMB$K_BE = 4; ! V Bus Error literal EMB$C_SA = 5; ! V SBI Alert literal EMB$K_SA = 5; ! V SBI Alert literal EMB$C_SE = 6; ! A/V Soft ECC Error literal EMB$K_SE = 6; ! A/V Soft ECC Error literal EMB$C_MCHECK_620 = 6; ! A Machine Check 620 - System CE literal EMB$K_MCHECK_620 = 6; ! A Machine Check 620 - System CE literal EMB$C_CPE = 6; ! I Corrected Platform Error literal EMB$K_CPE = 6; ! I Corrected Platform Error literal EMB$C_AW = 7; ! V Asynchronous Write Error literal EMB$K_AW = 7; ! V Asynchronous Write Error literal EMB$C_HE = 8; ! A/V Hard ECC Error literal EMB$K_HE = 8; ! A/V Hard ECC Error literal EMB$C_UBA = 9; ! V 11/780 Unibus Adapter Error literal EMB$K_UBA = 9; ! V 11/780 Unibus Adapter Error literal EMB$C_SI = 10; ! V 11/750 Fault through SBI Vector literal EMB$K_SI = 10; ! V 11/750 Fault through SBI Vector literal EMB$C_UE = 11; ! V 11/730 Unibus Error literal EMB$K_UE = 11; ! V 11/730 Unibus Error literal EMB$C_MBA = 12; ! V 11/780 Massbus Adapter Error literal EMB$K_MBA = 12; ! V 11/780 Massbus Adapter Error literal EMB$C_SBIA = 13; ! V 11/790 SBIA Error literal EMB$K_SBIA = 13; ! V 11/790 SBIA Error literal EMB$C_CRD = 14; ! A/V 11/790 CRD Log literal EMB$K_CRD = 14; ! A/V 11/790 CRD Log literal EMB$C_EMM = 15; ! V 11/790 Environmental Monitor literal EMB$K_EMM = 15; ! V 11/790 Environmental Monitor literal EMB$C_HLT = 16; ! A/V 11/790 Processor Error Halt literal EMB$K_HLT = 16; ! A/V 11/790 Processor Error Halt literal EMB$C_CRBT = 17; ! V 11/790 Console Reboot literal EMB$K_CRBT = 17; ! V 11/790 Console Reboot literal EMB$C_BIADPERR = 18; ! V BI Adapter Error literal EMB$K_BIADPERR = 18; ! V BI Adapter Error literal EMB$C_BIBUSERR = 19; ! V BI Bus Error literal EMB$K_BIBUSERR = 19; ! V BI Bus Error literal EMB$C_NMIFLT = 20; ! V NMI Fault literal EMB$K_NMIFLT = 20; ! V NMI Fault literal EMB$C_CTO = 21; ! V Console Timeout literal EMB$K_CTO = 21; ! V Console Timeout literal EMB$C_NBW = 22; ! V NBW literal EMB$K_NBW = 22; ! V NBW literal EMB$C_CACHERR = 23; ! A/V Cache Error literal EMB$K_CACHERR = 23; ! A/V Cache Error literal EMB$C_CVAX_CB = 24; ! V CVAX Cache/Bus Error literal EMB$K_CVAX_CB = 24; ! V CVAX Cache/Bus Error literal EMB$C_MEMSCAN = 25; ! V Calypso Memory Error by scanning literal EMB$K_MEMSCAN = 25; ! V Calypso Memory Error by scanning literal EMB$C_INT54 = 26; ! A/V Calypso SCB 54 Error literal EMB$K_INT54 = 26; ! A/V Calypso SCB 54 Error literal EMB$C_MCHECK_630 = 26; ! A Machine Check 630 - Processor CE literal EMB$K_MCHECK_630 = 26; ! A Machine Check 630 - Processor CE literal EMB$C_CMC = 26; ! I Corrected Machine Check literal EMB$K_CMC = 26; ! I Corrected Machine Check literal EMB$C_INT60 = 27; ! A/V Calypso SCB 60 Error literal EMB$K_INT60 = 27; ! A/V Calypso SCB 60 Error literal EMB$C_MCHECK_660 = 27; ! A Machine Check 660 - System UCE literal EMB$K_MCHECK_660 = 27; ! A Machine Check 660 - System UCE literal EMB$C_MCA_SYS = 27; ! I Machine Check Abort - Platform literal EMB$K_MCA_SYS = 27; ! I Machine Check Abort - Platform literal EMB$C_ADPERR = 28; ! A/V Adapter Error literal EMB$K_ADPERR = 28; ! A/V Adapter Error literal EMB$C_LASTFAIL = 29; ! V Calypso Lastfail literal EMB$K_LASTFAIL = 29; ! V Calypso Lastfail literal EMB$C_CONSOLE = 30; ! V Console Entry literal EMB$K_CONSOLE = 30; ! V Console Entry literal EMB$C_INFO = 31; ! V Informational Message literal EMB$K_INFO = 31; ! V Informational Message literal EMB$C_CS = 32; ! I/A/V Cold Start literal EMB$K_CS = 32; ! I/A/V Cold Start literal EMB$C_CLKERR = 33; ! V Clock Module Error literal EMB$K_CLKERR = 33; ! V Clock Module Error literal EMB$C_SCAN = 34; ! V Scan Error literal EMB$K_SCAN = 34; ! V Scan Error literal EMB$K_NF = 35; ! I/A/V New File Created literal EMB$C_NF = 35; ! I/A/V New File Created literal EMB$C_WS = 36; ! I/A/V Warm Start literal EMB$K_WS = 36; ! I/A/V Warm Start literal EMB$C_CR = 37; ! I/A/V Crash Restart literal EMB$K_CR = 37; ! I/A/V Crash Restart literal EMB$C_TS = 38; ! I/A/V Time Stamp literal EMB$K_TS = 38; ! I/A/V Time Stamp literal EMB$C_SS = 39; ! I/A/V System Service Message literal EMB$K_SS = 39; ! I/A/V System Service Message literal EMB$C_SBC = 40; ! I/A/V System Bugcheck literal EMB$K_SBC = 40; ! I/A/V System Bugcheck literal EMB$C_OM = 41; ! I/A/V Operator Message literal EMB$K_OM = 41; ! I/A/V Operator Message literal EMB$C_NM = 42; ! I/A/V Network Message literal EMB$K_NM = 42; ! I/A/V Network Message literal EMB$C_CONFIG = 43; ! A System Configuration literal EMB$K_CONFIG = 43; ! A System Configuration literal EMB$C_POLL_ERR = 44; ! V Polled Error literal EMB$K_POLL_ERR = 44; ! V Polled Error literal EMB$C_VM = 64; ! I/A/V Volume Mount literal EMB$K_VM = 64; ! I/A/V Volume Mount literal EMB$C_VD = 65; ! I/A/V Volume Dismount literal EMB$K_VD = 65; ! I/A/V Volume Dismount literal EMB$C_DT = 96; ! I/A/V Device Timeout literal EMB$K_DT = 96; ! I/A/V Device Timeout literal EMB$C_UI = 97; ! V Undefined Interrupt literal EMB$K_UI = 97; ! V Undefined Interrupt literal EMB$C_DA = 98; ! I/A/V Asynchronous Device Attention literal EMB$K_DA = 98; ! I/A/V Asynchronous Device Attention literal EMB$C_SP = 99; ! I/A/V Software Parameters literal EMB$K_SP = 99; ! I/A/V Software Parameters literal EMB$C_LM = 100; ! I/A/V Logged Message literal EMB$K_LM = 100; ! I/A/V Logged Message literal EMB$C_LOGMSCP = 101; ! I/A/V Logged MSCP Message literal EMB$K_LOGMSCP = 101; ! I/A/V Logged MSCP Message literal EMB$C_PWR = 102; ! A Laser Power Event literal EMB$K_PWR = 102; ! A Laser Power Event literal EMB$C_UBC = 112; ! I/A/V User Bugcheck literal EMB$K_UBC = 112; ! I/A/V User Bugcheck literal EMB$C_HALT_FRAME = 113; ! I/A Console Data Log literal EMB$K_HALT_FRAME = 113; ! I/A Console Data Log literal EMB$C_INIT = 114; ! I Processor INIT literal EMB$K_INIT = 114; ! I Processor INIT literal EMB$C_MCHECK_680 = 115; ! A Machine Check 680 - System Event literal EMB$K_MCHECK_680 = 115; ! A Machine Check 680 - System Event literal EMB$C_MCHECK_RUE = 116; ! A Machine Check 6A0/6B0 - RUE literal EMB$K_MCHECK_RUE = 116; ! A Machine Check 6A0/6B0 - RUE literal EMB$C_THROTTLE_CRD = 120; ! I/A CE Throttling Notification literal EMB$K_THROTTLE_CRD = 120; ! I/A CE Throttling Notification literal EMB$C_INDICT = 124; ! I/A Indictment Event literal EMB$K_INDICT = 124; ! I/A Indictment Event literal EMB$C_SEL = 126; ! I System Event Log literal EMB$K_SEL = 126; ! I System Event Log ! The following are minor class (DEVCLS) codes for the MCHECK_680 major class code. literal EMB$C_MCHECK_680_CORRECTABLE = 6; ! Correctable literal EMB$K_MCHECK_680_CORRECTABLE = 6; ! Correctable literal EMB$C_MCHECK_680_UNCORRECTABLE = 2; ! Uncorrectable literal EMB$K_MCHECK_680_UNCORRECTABLE = 2; ! Uncorrectable ! The following are minor class (DEVCLS) codes for the MCHECK_RUE major class code. literal EMB$C_MCHECK_RUE_6A0 = 1; ! System literal EMB$K_MCHECK_RUE_6A0 = 1; ! System literal EMB$C_MCHECK_RUE_6B0 = 2; ! Processor literal EMB$K_MCHECK_RUE_6B0 = 2; ! Processor ! The following are minor class (DEVCLS) codes for the CONFIG major class code. literal EMB$C_CONFIG_ORIG = 0; ! A/V Original FRU config literal EMB$K_CONFIG_ORIG = 0; ! A/V Original FRU config literal EMB$C_CONFIG_SDR_FRU = 1; ! I SDR FRU eeprom config literal EMB$K_CONFIG_SDR_FRU = 1; ! I SDR FRU eeprom config literal EMB$C_CONFIG_PCI = 2; ! I PCI config literal EMB$K_CONFIG_PCI = 2; ! I PCI config !*** MODULE $EMBCEHDEF *** ! Define some constants that are useful. ! Major HDR REVISIONS literal EMB$K_HD_REV_V2 = 2; ! First rev of new header ! Major HDR REVISIONS literal EMB$C_HD_REV_V2 = 2; ! Minor HDR REVISIONS literal EMB$K_HD_MINOR_REV_V1 = 1; ! First minor rev of new header literal EMB$K_OS_ALPHA_VMS = 2; ! Hardware type literal EMB$K_HW_PDP11 = 1; literal EMB$K_HW_VAX = 2; literal EMB$K_HW_MIPS = 3; literal EMB$K_HW_ALPHA = 4; literal EMB$K_HW_X86 = 5; literal EMB$K_HW_IA64 = 6; literal EMB$K_EMB_IDENT = -2; literal EMB$K_TLV_UNNAMED = 1; literal EMB$K_TLV_UNUSED = 33; literal EMB$K_TLV_TIME = 65; literal EMB$K_TLV_DSR = 97; literal EMB$K_TLV_OSV = 129; literal EMB$K_TLV_OSB = 161; literal EMB$K_TLV_SSN = 193; literal EMB$K_TLV_DDR = 225; literal EMB$K_TLV_PATCH = 257; literal EMB$K_TLV_SCSNAME = 289; literal EMB$K_TLV_RBS = 321; literal EMB$K_TLV_DEV_SN = 1025; literal EMB$K_TLV_DEV_PROD_ID = 1057; literal EMB$K_TLV_DEV_PROD_REV = 1089; literal EMB$K_TLV_SCSI_CHAN = 1121; literal EMB$K_CEH_LENGTH = 284; ! LENGTH OF PART COMMON TO ALL MESSAGES literal EMB$C_CEH_LENGTH = 284; ! LENGTH OF PART COMMON TO ALL MESSAGES literal EMB$S_EMBCEH = 284; ! ! ! macro EMB$L_CEH_IDENT = 0,0,32,1 %; ! New header ident macro EMB$L_CEH_HEADER_LENGTH = 4,0,32,1 %; ! distance to event ! body macro EMB$L_CEH_EVENT_LENGTH = 8,0,32,1 %; ! total length of record macro EMB$W_CEH_HDR_REV = 12,0,16,0 %; ! Major header rev macro EMB$W_CEH_HDR_MINOR = 14,0,16,0 %; ! Minor header rev macro EMB$W_CEH_OS_ID = 16,0,16,0 %; ! Id of OS macro EMB$W_CEH_HW_ARCH = 18,0,16,0 %; ! Hardware architecture macro EMB$L_CEH_VENDOR = 20,0,32,0 %; ! Hardware vendor macro EMB$L_CEH_SYSTYPE = 24,0,32,0 %; ! SYSTEM TYPE REGISTER macro EMB$L_CEH_SYSTYPE_H = 28,0,32,0 %; ! macro EMB$L_CEH_LOG_CPU = 32,0,32,0 %; ! ID of reporting CPU macro EMB$L_CEH_TOTAL_CPUS = 36,0,32,0 %; ! total Active CPUS macro EMB$W_CEH_ENTRY = 40,0,16,0 %; ! ERROR MESSAGE ENTRY TYPE macro EMB$W_CEH_DEVCLS = 42,0,16,0 %; ! Device class macro EMB$L_CEH_SMM = 44,0,32,0 %; ! SMM number macro EMB$W_CEH_DEVTYP = 48,0,16,0 %; ! Device type macro EMB$W_CEH_FLAGS = 50,0,16,0 %; ! MISC. FLAGS macro EMB$L_CEH_ERRMSK = 52,0,32,0 %; ! ERROR MASK macro EMB$L_CEH_ABSTIM = 56,0,32,0 %; ! LOGGED CONTENTS OF EXE$GL_ABSTIM macro EMB$L_CEH_CPUID = 60,0,32,0 %; ! UNIQUE CPU ID macro EMB$L_CEH_DeviceID0 = 64,0,32,0 %; ! Used by unix macro EMB$L_CEH_DeviceID1 = 68,0,32,0 %; ! Used by unix macro EMB$L_CEH_DeviceID2 = 72,0,32,0 %; ! Used by unix macro EMB$L_CEH_GROUP = 76,0,32,0 %; ! Use sequence number macro EMB$W_CEH_ERRSEQ = 76,0,16,0 %; ! ERROR SEQUENCE FOR MESSAGE macro EMB$W_CEH_UUID = 78,0,16,0 %; ! Universal Unique ID macro EMB$L_CEH_EVENT_BODY_LENGTH = 80,0,32,1 %; ! exact length of the event body macro EMB$T_CEH_RESERVED = 84,0,0,0 %; literal EMB$S_CEH_RESERVED = 36; ! reserved for expansion macro EMB$L_CEH_NUM_TLV = 120,0,32,0 %; ! Number of TLV strings. macro EMB$W_CEH_DSR_TAG = 124,0,16,0 %; ! String type of DSR macro EMB$W_CEH_DSR_LENGTH = 126,0,16,0 %; ! String length of DSR macro EMB$T_CEH_DSR_STRING = 128,0,0,0 %; literal EMB$S_CEH_DSR_STRING = 32; ! marketing name of this system macro EMB$W_CEH_DDR_TAG = 160,0,16,0 %; ! String type of ddr string macro EMB$W_CEH_DDR_LENGTH = 162,0,16,0 %; ! String length of dynamic device name macro EMB$T_CEH_DDR_STRING = 164,0,0,0 %; literal EMB$S_CEH_DDR_STRING = 32; ! Dynamic device recognition string macro EMB$W_CEH_SSN_TAG = 196,0,16,0 %; ! String type of system serial number macro EMB$W_CEH_SSN_LENGTH = 198,0,16,0 %; ! String length of system serial number macro EMB$T_CEH_SSN_STRING = 200,0,0,0 %; literal EMB$S_CEH_SSN_STRING = 20; ! System serial number macro EMB$W_CEH_TIME_TAG = 220,0,16,0 %; ! String type time macro EMB$W_CEH_TIME_LENGTH = 222,0,16,0 %; ! String length of time macro EMB$T_CEH_TIME_STRING = 224,0,0,0 %; literal EMB$S_CEH_TIME_STRING = 24; ! time macro EMB$W_CEH_OSV_TAG = 248,0,16,0 %; ! String type of os version macro EMB$W_CEH_OSV_LENGTH = 250,0,16,0 %; ! String length of os version macro EMB$Q_CEH_SWVERS = 252,0,0,0 %; literal EMB$S_CEH_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_CEH_SWVERS_FILL = 260,0,32,0 %; ! For nulls. macro EMB$W_CEH_SCS_TAG = 264,0,16,0 %; ! Computer name macro EMB$W_CEH_SCS_LENGTH = 266,0,16,0 %; ! String length of computer name macro EMB$T_CEH_SCS_NAME = 268,0,0,0 %; literal EMB$S_CEH_SCS_NAME = 16; ! SCS Node name ASCIC literal EMB$K_TRAIL_LENGTH = 8; ! LENGTH OF TRAILER literal EMB$S_TRAILER_FIELDS = 8; macro EMB$L_TRAILING_LENGTH = 0,0,32,1 %; macro EMB$L_EVENT_TRAILER = 4,0,32,1 %; !*** MODULE $EO1DEF *** ! + ! EOF1 ANSI MAGNETIC TAPE LABEL ! THIS IS THE FIRST LABEL IN FILE TRAILER LABEL SET. IT IS EQUIVALENT TO ! HDR1 EXCEPT FOR THE FOLLOWING FIELDS. ! - literal EO1$S_EO1DEF = 80; literal EO1$S_EO1 = 80; macro EO1$L_EO1LID = 0,0,32,0 %; ! LABEL IDENTIFIER AND NUMBER 'EOF1' macro EO1$T_BLOCKCNT = 54,0,0,0 %; literal EO1$S_BLOCKCNT = 6; ! BLOCK COUNT macro EO1$T_HIBLOCKCNT = 76,0,32,0 %; literal EO1$S_HIBLOCKCNT = 4; ! HIGH BLOCK COUNT !*** MODULE $EO2DEF *** ! + ! EOF2 ANSI MAGNETIC TAPE LABEL ! THIS IS THE SECOND LABEL IN THE FILE TRAILER LABEL SET. IT IS EQUIVALENT ! TO HDR2 EXCEPT FOR THE FOLLOWING FIELDS. ! - literal EO2$S_EO2DEF = 4; literal EO2$S_EO2 = 4; macro EO2$L_EO2LID = 0,0,32,0 %; ! LABEL IDENTIFIER AND NUMBER 'EOF2' !*** MODULE $EO3DEF *** ! + ! EOF3 ANSI MAGNETIC TAPE LABEL ! THIS IS THE THIRD LABEL IN THE FILE TRAILER LABEL SET. IT IS EQUIVALENT ! TO HDR3 EXCEPT FOR THE FOLLOWING FIELDS. ! - literal EO3$S_EO3DEF = 4; literal EO3$S_EO3 = 4; macro EO3$L_EO3LID = 0,0,32,0 %; ! LABEL IDENTIFIER AND NUMBER 'EOF3' !*** MODULE $EO4DEF *** ! + ! EOF4 ANSI MAGNETIC TAPE LABEL ! THIS IS THE FOURTH LABEL IN THE FILE TRAILER LABEL SET. IT IS EQUIVALENT ! TO HDR4 EXCEPT FOR THE FOLLOWING FIELDS. ! - literal EO4$S_EO4DEF = 4; literal EO4$S_EO4 = 4; macro EO4$L_EO4LID = 0,0,32,0 %; ! LABEL IDENTIFIER AND NUMBER 'EOF4' !*** MODULE $ERBDEF *** ! ! Error Log Recovery Block Header ! literal ERB$S_ERB = 24; macro ERB$L_BUFPAGES = 0,0,32,0 %; ! V5.1 and + : pages / buffer macro ERB$L_BUFCNT = 4,0,32,0 %; ! # buffers, not incl crash buf macro ERB$L_BLOCK_SIZE = 8,0,32,0 %; ! Returned by allocation macro ERB$L_ALLOCATED = 12,0,32,0 %; ! Bytes alloc'd for this block macro ERB$L_HEAD = 16,0,32,0 %; ! Ring head index at crash macro ERB$L_TAIL = 20,0,32,0 %; ! Ring tail index at crash literal ERB$C_LENGTH = 24; literal ERB$K_LENGTH = 24; literal S_ERBDEF = 24; !*** MODULE $ERLDEF *** ! ! Error Log Buffer Header ! literal ERL$M_LOCK = %X'1'; literal ERL$M_TIMER = %X'2'; literal ERL$S_ERL = 40; macro ERL$B_BUSY = 0,0,8,0 %; ! For compatibility purposes macro ERL$B_MSGCNT = 1,0,8,0 %; ! For compatibility purposes macro ERL$B_BUFIND = 2,0,8,0 %; ! For compatibility purposes macro ERL$B_FLAGS = 3,0,8,0 %; ! Buffer control flags macro ERL$V_LOCK = 3,0,1,0 %; ! Buffer allocation interlock macro ERL$V_TIMER = 3,1,1,0 %; ! Timer active macro ERL$L_NEXT = 4,0,32,1 %; ! For compatibility purposes macro ERL$L_COMPAT = 4,0,32,0 %; ! Used for compatibility determination macro ERL$L_END = 8,0,32,1 %; ! For compatibility purposes macro ERL$L_BUSY = 12,0,32,0 %; ! Number of busy messages in buffer macro ERL$L_MSGCNT = 16,0,32,0 %; ! Number of completed messages in buffer macro ERL$L_BUFIND = 20,0,32,0 %; ! Buffer indicator of respective buffer macro ERL$Q_NEXT = 24,0,0,1 %; literal ERL$S_NEXT = 8; ! Address of next available space in buffer macro ERL$Q_END = 32,0,0,1 %; literal ERL$S_END = 8; ! Address of end of buffer + 1 literal ERL$C_LENGTH = 40; literal ERL$K_LENGTH = 40; literal S_ERLDEF = 40; !*** MODULE $ERLMBXDEF *** ! ! ERROR LOG MAILBOX SYSTEM DATA CELL STRUCTURE AND MAILBOX COUNT ! literal ERL$K_MAILBOX_COUNT = 5; ! NUMBER OF MAILBOXES literal ERL$C_MAILBOX_COUNT = 5; ! NUMBER OF MAILBOXES literal ERL$K_MBX_LENGTH = 8; ! LENGTH OF STRUCTURE literal ERL$C_MBX_LENGTH = 8; ! LENGTH OF STRUCTURE literal ERL$S_ERLMBX = 8; macro ERL$L_MBX_UNT = 0,0,32,0 %; ! MAILBOX UNIT NUMBER macro ERL$L_MBX_PID = 4,0,32,0 %; ! MBX OWNER PID !*** MODULE $ERFMBXDEF *** ! ! COMPLEMENTARY STRUCTURES FOR ERRFMT DIAGNOSTIC MAILBOX CONTROL ! literal ERF$K_MBX_LENGTH = 8; ! LENGTH OF STRUCTURE literal ERF$C_MBX_LENGTH = 8; ! LENGTH OF STRUCTURE literal ERF$S_ERFMBX = 8; macro ERF$W_MBX_CHANNEL = 0,0,16,0 %; ! MBX CHANNEL NUMBER macro ERF$W_MBX_SIZE = 2,0,16,0 %; ! MBX SIZE macro ERF$L_MBX_UNIT = 4,0,32,0 %; ! MBX UNIT NUMBER !*** MODULE $EV4DEF *** literal EV4$M_SWC = %X'4'; literal EV4$M_INV = %X'8'; literal EV4$M_DZE = %X'10'; literal EV4$M_FOV = %X'20'; literal EV4$M_UNF = %X'40'; literal EV4$M_INE = %X'80'; literal EV4$M_IOV = %X'100'; literal EV4$M_MSK = %X'200000000'; literal EV4$M_WR = %X'1'; literal EV4$M_ACV = %X'2'; literal EV4$M_FOR = %X'4'; literal EV4$M_FOW = %X'8'; literal EV4$M_RA_OPERAND = %X'1F0'; literal EV4$M_OPCODE = %X'7E00'; literal EV4$M_BIU_HERR = %X'1'; literal EV4$M_BIU_SERR = %X'2'; literal EV4$M_BC_TPERR = %X'4'; literal EV4$M_BC_TCPERR = %X'8'; literal EV4$M_BIU_CMD = %X'70'; literal EV4$M_BIU_SEO = %X'80'; literal EV4$M_FILL_ECC = %X'100'; literal EV4$M_BIU_DPERR = %X'400'; literal EV4$M_FILL_IRD = %X'800'; literal EV4$M_FILL_QW = %X'3000'; literal EV4$M_FILL_SEO = %X'4000'; literal EV4$M_DC_HIT = %X'8'; literal EV4$M_DC_ERR = %X'10'; literal EV4$M_IC_ERR = %X'20'; literal EV4$S_EV4DEF = 8; ! Old size name - synonym literal EV4$S_EV4 = 8; macro EV4$Q_EXC_SUM = 0,0,0,0 %; literal EV4$S_EXC_SUM = 8; macro EV4$v_fill_1 = 0,0,2,0 %; literal EV4$s_fill_1 = 2; macro EV4$V_SWC = 0,2,1,0 %; macro EV4$V_INV = 0,3,1,0 %; macro EV4$V_DZE = 0,4,1,0 %; macro EV4$V_FOV = 0,5,1,0 %; macro EV4$V_UNF = 0,6,1,0 %; macro EV4$V_INE = 0,7,1,0 %; macro EV4$V_IOV = 0,8,1,0 %; macro EV4$v_fill_2 = 0,9,24,0 %; literal EV4$s_fill_2 = 24; macro EV4$V_MSK = 4,1,1,0 %; macro EV4$v_fill_3 = 4,2,30,0 %; literal EV4$s_fill_3 = 30; macro EV4$Q_MM_CSR = 0,0,0,0 %; literal EV4$S_MM_CSR = 8; macro EV4$V_WR = 0,0,1,0 %; macro EV4$V_ACV = 0,1,1,0 %; macro EV4$V_FOR = 0,2,1,0 %; macro EV4$V_FOW = 0,3,1,0 %; macro EV4$V_RA_OPERAND = 0,4,5,0 %; literal EV4$S_RA_OPERAND = 5; macro EV4$V_OPCODE = 0,9,6,0 %; literal EV4$S_OPCODE = 6; macro EV4$Q_BIU_STAT = 0,0,0,0 %; literal EV4$S_BIU_STAT = 8; macro EV4$V_BIU_HERR = 0,0,1,0 %; macro EV4$V_BIU_SERR = 0,1,1,0 %; macro EV4$V_BC_TPERR = 0,2,1,0 %; macro EV4$V_BC_TCPERR = 0,3,1,0 %; macro EV4$V_BIU_CMD = 0,4,3,0 %; literal EV4$S_BIU_CMD = 3; macro EV4$V_BIU_SEO = 0,7,1,0 %; macro EV4$V_FILL_ECC = 0,8,1,0 %; macro EV4$v_fill_5 = 0,9,1,0 %; macro EV4$V_BIU_DPERR = 0,10,1,0 %; macro EV4$V_FILL_IRD = 0,11,1,0 %; macro EV4$V_FILL_QW = 0,12,2,0 %; literal EV4$S_FILL_QW = 2; macro EV4$V_FILL_SEO = 0,14,1,0 %; macro EV4$Q_DC_STAT = 0,0,0,0 %; literal EV4$S_DC_STAT = 8; macro EV4$V_CHIP_ID = 0,0,3,0 %; literal EV4$S_CHIP_ID = 3; macro EV4$V_DC_HIT = 0,3,1,0 %; macro EV4$V_DC_ERR = 0,4,1,0 %; macro EV4$V_IC_ERR = 0,5,1,0 %; !*** MODULE $EV5DEF *** literal ev5$M_SWC = %X'400'; literal ev5$M_INV = %X'800'; literal ev5$M_DZE = %X'1000'; literal ev5$M_FOV = %X'2000'; literal ev5$M_UNF = %X'4000'; literal ev5$M_INE = %X'8000'; literal ev5$M_IOV = %X'10000'; literal ev5$M_WR = %X'1'; literal ev5$M_ACV = %X'2'; literal ev5$M_FOR = %X'4'; literal ev5$M_FOW = %X'8'; literal ev5$M_DTB_MISS = %X'10'; literal ev5$M_BAD_VA = %X'20'; literal ev5$M_RA_OPERAND = %X'7C0'; literal ev5$M_OPCODE = %X'1F800'; literal ev5$M_CHIP_ID = %X'F000000'; literal ev5$M_BC_TPERR = %X'10000000'; literal ev5$M_BC_TC_PERR = %X'20000000'; literal ev5$M_EI_ES = %X'40000000'; literal ev5$M_COR_ECC_ERR = %X'80000000'; literal ev5$M_UNC_ECC_ERR = %X'1'; literal ev5$M_EI_PAR_ERR = %X'2'; literal ev5$M_FIL_IRD = %X'4'; literal ev5$M_SEO_HRD_ERR = %X'8'; literal ev5$M_DPE = %X'800'; literal ev5$M_TPE = %X'1000'; literal ev5$M_TMR = %X'2000'; literal ev5$M_SEO = %X'1'; literal ev5$M_LOCK = %X'2'; literal ev5$M_DP0 = %X'4'; literal ev5$M_DP1 = %X'8'; literal ev5$M_TP0 = %X'10'; literal ev5$M_TP1 = %X'20'; literal ev5$S_ev5DEF = 8; ! Old size name - synonym literal ev5$S_ev5 = 8; macro ev5$Q_EXC_SUM = 0,0,0,0 %; literal ev5$S_EXC_SUM = 8; macro ev5$V_SWC = 0,10,1,0 %; macro ev5$V_INV = 0,11,1,0 %; macro ev5$V_DZE = 0,12,1,0 %; macro ev5$V_FOV = 0,13,1,0 %; macro ev5$V_UNF = 0,14,1,0 %; macro ev5$V_INE = 0,15,1,0 %; macro ev5$V_IOV = 0,16,1,0 %; macro ev5$Q_MM_STAT = 0,0,0,0 %; literal ev5$S_MM_STAT = 8; macro ev5$V_WR = 0,0,1,0 %; macro ev5$V_ACV = 0,1,1,0 %; macro ev5$V_FOR = 0,2,1,0 %; macro ev5$V_FOW = 0,3,1,0 %; macro ev5$V_DTB_MISS = 0,4,1,0 %; macro ev5$V_BAD_VA = 0,5,1,0 %; macro ev5$V_RA_OPERAND = 0,6,5,0 %; literal ev5$S_RA_OPERAND = 5; macro ev5$V_OPCODE = 0,11,6,0 %; literal ev5$S_OPCODE = 6; macro ev5$Q_EI_STAT = 0,0,0,0 %; literal ev5$S_EI_STAT = 8; macro ev5$L_L = 0,0,32,1 %; macro ev5$V_CHIP_ID = 0,24,4,0 %; literal ev5$S_CHIP_ID = 4; macro ev5$V_BC_TPERR = 0,28,1,0 %; macro ev5$V_BC_TC_PERR = 0,29,1,0 %; macro ev5$V_EI_ES = 0,30,1,0 %; macro ev5$V_COR_ECC_ERR = 0,31,1,0 %; macro ev5$L_H = 4,0,32,1 %; macro ev5$V_UNC_ECC_ERR = 4,0,1,0 %; macro ev5$V_EI_PAR_ERR = 4,1,1,0 %; macro ev5$V_FIL_IRD = 4,2,1,0 %; macro ev5$V_SEO_HRD_ERR = 4,3,1,0 %; macro ev5$Q_ICPERR_STAT = 0,0,0,1 %; literal ev5$S_ICPERR_STAT = 8; macro ev5$V_DPE = 0,11,1,0 %; macro ev5$V_TPE = 0,12,1,0 %; macro ev5$V_TMR = 0,13,1,0 %; macro ev5$Q_DCPERR_STAT = 0,0,0,1 %; literal ev5$S_DCPERR_STAT = 8; macro ev5$V_SEO = 0,0,1,0 %; macro ev5$V_LOCK = 0,1,1,0 %; macro ev5$V_DP0 = 0,2,1,0 %; macro ev5$V_DP1 = 0,3,1,0 %; macro ev5$V_TP0 = 0,4,1,0 %; macro ev5$V_TP1 = 0,5,1,0 %; !*** MODULE $EVTDEF *** ! ! EVENT CODE DEFINITIONS ! literal EVT$_AST = 0; literal EVT$_COLPGA = 0; literal EVT$_EVENT = 1; literal EVT$_CEF = 2; literal EVT$_LEFO = 3; literal EVT$_FPGA = 4; literal EVT$_WAKE = 5; literal EVT$_RESUME = 6; literal EVT$_PFCOM = 7; literal EVT$_SETPRI = 8; literal EVT$_SWPOUT = 9; literal EVT$_SWPOUTE = 10; literal EVT$_SWPIN = 11; literal EVT$_SWPINC = 12; literal EVT$_MAXEVT = 13; !*** MODULE $EWDATADEF *** ! + ! $EWDATADEF - Symbolic offsets within the exec-writable page ! ! An exec-writable page is allocated when the system is bootstrapped. ! The fields within this page are being defined below. These data cells ! were originally defined in the system (i.e. in SYS.EXE) with the form: ! ! PMS$xL_cellname. ! ! Now that this cell resides in a seperate exec-writable page that is ! pointed by a cell in the system's base image, the symbolic offset from ! the base of the exec-writable page to this cell has the form: ! ! EW_PMS$xL_cellname. ! ! ! NOTE: The PMS Arrays (COUNT, MCNT, WRITE, CACHE, CPU, PFA) must immediately ! follow FCP and FCP2 fields. ! ! - literal EW$K_LENGTH = 378; literal EW$C_LENGTH = 378; literal EW$S_EWDATADEF = 378; ! Old size name - synonym literal EW$S_EWDATA = 378; macro EW$R_PMSEWDATA = 0,0,0,0 %; literal EW_PMS$S_PMSEWDATA = 376; macro EW_PMS$GL_FCP = 0,0,0,0 %; ! start of the FCP counters macro EW_PMS$GL_FCP2 = 0,0,0,0 %; ! start of the FCP2 counters macro EW_PMS$AL_COUNT = 0,0,0,0 %; literal EW_PMS$S_COUNT = 40; ! number of operations macro EW_PMS$AL_MCNT = 40,0,0,0 %; literal EW_PMS$S_MCNT = 40; ! number of modifiers macro EW_PMS$AL_READ = 80,0,0,0 %; literal EW_PMS$S_READ = 40; ! number of disk reads macro EW_PMS$AL_WRITE = 120,0,0,0 %; literal EW_PMS$S_WRITE = 40; ! number of disk writes macro EW_PMS$AL_CACHE = 160,0,0,0 %; literal EW_PMS$S_CACHE = 40; ! number of cache hits macro EW_PMS$AL_CPU = 200,0,0,0 %; literal EW_PMS$S_CPU = 40; ! accumulated cpu times macro EW_PMS$AL_PFA = 240,0,0,0 %; literal EW_PMS$S_PFA = 40; ! accumulated page faults macro EW_PMS$GL_TURN = 280,0,32,0 %; ! number of window turns macro EW_PMS$GL_DIRHIT = 284,0,32,0 %; ! count of directory LRU hits macro EW_PMS$GL_DIRMISS = 288,0,32,0 %; ! count of directory LRU misses macro EW_PMS$GL_QUOHIT = 292,0,32,0 %; ! count of quota cache hits macro EW_PMS$GL_QUOMISS = 296,0,32,0 %; ! count of quota cache misses macro EW_PMS$GL_FIDHIT = 300,0,32,0 %; ! count of file ID cache hits macro EW_PMS$GL_FIDMISS = 304,0,32,0 %; ! count of file ID cache misses macro EW_PMS$GL_EXTHIT = 308,0,32,0 %; ! count of extent cache hits macro EW_PMS$GL_EXTMISS = 312,0,32,0 %; ! count of extent cache misses macro EW_PMS$GL_FILHDR_HIT = 316,0,32,0 %; ! count of file header cache hits macro EW_PMS$GL_FILHDR_MISS = 320,0,32,0 %; ! count of file header cache misses macro EW_PMS$GL_DIRDATA_HIT = 324,0,32,0 %; ! count of directory data block hits macro EW_PMS$GL_DIRDATA_MISS = 328,0,32,0 %; ! count of directory data block misses macro EW_PMS$GL_STORAGMAP_HIT = 332,0,32,0 %; ! count of storage bit map cache hits macro EW_PMS$GL_STORAGMAP_MISS = 336,0,32,0 %; ! count of storage bit map cache misses macro EW_PMS$GL_OPEN = 340,0,32,0 %; ! number of currently open files macro EW_PMS$GL_OPENS = 344,0,32,0 %; ! total count of opens macro EW_PMS$GL_ERASEIO = 348,0,32,0 %; ! total count of erase QIO's issued macro EW_PMS$GL_VOLLCK = 352,0,32,0 %; ! count of XQP volume synch locks macro EW_PMS$GL_VOLWAIT = 356,0,32,0 %; ! # of times XQP had to wait for a ! volume synch lock macro EW_PMS$GL_SYNCHLCK = 360,0,32,0 %; ! count of XQP directory and ! file synch locks macro EW_PMS$GL_SYNCHWAIT = 364,0,32,0 %; ! # of times XQP had to wait for a ! directory or file synch lock macro EW_PMS$GL_ACCLCK = 368,0,32,0 %; ! count of XQP access locks macro EW_PMS$GL_XQPCACHEWAIT = 372,0,32,0 %; ! # of times XQP had to wait for free ! space in a cache macro EW$R_RMSEWDATA = 376,0,16,0 %; literal EW_RMS$S_RMSEWDATA = 2; macro EW_RMS$GW_GBLBUFQUO = 376,0,16,0 %; ! current global buffer quota remaining !*** MODULE $EXEDEF *** literal EXE$C_SYSEFN = 31; ! Common system event flag literal EXE$C_CMSTKSZ = 20; ! Number of longwords in dispatch call frame literal EXE$M_NPAGGRNMSK = 63; ! Allocation granularity mask for nonpaged pool literal EXE$M_PAGGRNMSK = 15; ! Allocation granularity mask for paged pool literal EXE$M_P1GRNMSK = 15; ! Allocation granularity mask for P1 region literal EXE$M_DEFGRNMSK = 15; ! Allocation granularity mask default literal EXE$M_MMG_FLAG_ZDONE = %X'1'; literal EXE$M_MMG_FLAG_UDONE = %X'2'; literal EXE$S_MMG_FLAGS = 4; macro EXE$L_MMG_FLAGS = 0,0,32,0 %; ! Reserved memory flags macro EXE$V_MMG_FLAG_ZDONE = 0,0,1,0 %; ! Page zeroing in reserved memory registry is done macro EXE$V_MMG_FLAG_UDONE = 0,1,1,0 %; ! Testing untested memory is done !*** MODULE $SYSEVTIDEF *** ! get the ACB def ! get the spinlock definitions ! This system ACB structure is created when the $SET_SYSTEM_EVENT system ! service is invoked. ! literal SYSEVT_ACB$K_LENGTH = 84; ! Length of block. literal SYSEVT_ACB$C_LENGTH = 84; ! Length of block. literal sysevt_acb$S_SYSEVT_ACB = 84; macro sysevt_acb$r_imbedded_acb64 = 0,0,0,0 %; literal sysevt_acb$s_imbedded_acb64 = 64; macro sysevt_acb$Q_HANDLE = 64,0,0,0 %; literal sysevt_acb$S_HANDLE = 8; macro sysevt_acb$l_sysevt_acb = 64,0,32,1 %; macro sysevt_acb$l_seq_num = 68,0,32,1 %; macro sysevt_acb$l_events = 72,0,32,0 %; ! mask of events for which process is to be notified macro sysevt_acb$l_local_queue = 76,0,32,0 %; ! set indicates SYSEVT_ACB on SYSEVT private queue macro sysevt_acb$l_imgcnt = 80,0,32,0 %; ! image count taken from the PHD literal sysevt$m_galaxy_registered = %X'1'; literal SYSEVT$K_LENGTH = 40; ! Length of block. literal SYSEVT$C_LENGTH = 40; ! Length of block. literal sysevt$S_SYSEVT = 40; ! ! This is the system event data structure. This data struture contains ! an AST queue listhead, a lock to synchronize access to the queue, and a ! sequence number field. Each time a process requests notification of a system ! event (or set of events), an AST is queued. Then when the event occurs, the ! AST is removed from this queue and delivered to the target process. ! macro sysevt$q_event_mask = 0,0,0,0 %; literal sysevt$s_event_mask = 8; ! Bitmask of events which indicate that ! something may be in the queue for this event. macro sysevt$w_size = 8,0,16,0 %; ! Size of data structure macro sysevt$b_type = 10,0,8,0 %; ! Type is DYN$C_SYSEVT macro sysevt$b_subtype = 11,0,8,0 %; ! Subtype field to further qualify type macro sysevt$ps_lock = 12,0,32,1 %; ! Pointer to dynamic spinlock macro sysevt$q_flags = 16,0,0,0 %; literal sysevt$s_flags = 8; ! interlocked flags macro sysevt$v_galaxy_registered = 16,0,1,0 %; ! Galaxy membership callback routine registered macro sysevt$q_seq_num = 24,0,0,0 %; literal sysevt$s_seq_num = 8; ! ever increasing counter macro sysevt$l_ast_qfl = 32,0,32,1 %; ! queued SYSEVT_ACBs macro sysevt$l_ast_qbl = 36,0,32,1 %; !*** MODULE $F11BCDEF *** ! + ! F11BC - Files 11 Block Cache ! ! Header area which describes block cache used by F11BXQP. ! ! - ! ! The next four constants are to do with minimum cache allowances for XQP activity ! per process. These minima control not ionly minimum cache size but also ! stalling for XQP activity. ! literal F11BC$K_MAPCACHE_MIN = 1; ! Bitmap.sys buffers per process literal F11BC$K_HDRCACHE_MIN = 4; ! Indexf.sys buffers per process literal F11BC$K_DIRCACHE_MIN = 2; ! Dir/quota buffers per process literal F11BC$K_DINDXCACHE_MIN = 1; ! Directory index `buffers' per process ! The next four constants are to control the minimum number of fluid buffers a ! process can hold in the XQP cache. (Fluid buffers == buffers that are not pinned in cache) ! literal F11BC$K_MAPCACHE_FLUIDMIN = 1; ! Bitmap.sys buffers per process literal F11BC$K_HDRCACHE_FLUIDMIN = 3; ! Indexf.sys buffers per process literal F11BC$K_DIRCACHE_FLUIDMIN = 2; ! Dir/quota buffers per process literal F11BC$K_DINDXCACHE_FLUIDMIN = 1; ! Directory index `buffers' per process literal F11BC$K_NUM_POOLS = 4; ! Number of buffer pools. literal F11BC$S_F11BCDEF = 240; ! Old size name - synonym literal F11BC$S_F11BC = 240; macro F11BC$L_BUFBASE = 0,0,32,1 %; ! Base address of buffer area. macro F11BC$L_BUFSIZE = 4,0,32,0 %; ! Size of buffer area in bytes. macro F11BC$W_SIZE = 8,0,16,0 %; ! Standard size field. macro F11BC$B_TYPE = 10,0,8,0 %; ! Standard type field. macro F11BC$B_SUBTYPE = 11,0,8,0 %; ! Standard subtype field. macro F11BC$L_FILL1 = 12,0,32,1 %; ! Position of old size field (Now Reserved) macro F11BC$Q_QREALSIZE = 16,0,0,0 %; literal F11BC$S_QREALSIZE = 8; ! Structure size as a quadword. macro F11BC$L_REALSIZE = 16,0,32,0 %; ! Structure size as a longword. macro F11BC$L_LBNHSHBAS = 24,0,32,1 %; ! Base of LBN hash table. macro F11BC$L_LBNHSHCNT = 28,0,32,0 %; ! Count of entries in LBN hash tbl. macro F11BC$L_BFRCNT = 32,0,32,0 %; ! Total buffer count. macro F11BC$L_BFRDBAS = 36,0,32,1 %; ! Buffer descriptor base address. macro F11BC$L_BFRLDBAS = 40,0,32,1 %; ! Buffer lock descriptor base addr. macro F11BC$L_BLHSHBAS = 44,0,32,1 %; ! Base addr of buffer lock hash tbl. macro F11BC$L_BLHSHCNT = 48,0,32,0 %; ! Num entries in buff lock hash tbl. macro F11BC$A_FREEBFRL = 52,0,32,0 %; ! Address of first free buffer lock block. macro F11BC$Q_POOL_LRU = 56,0,0,1 %; literal F11BC$S_POOL_LRU = 32; ! Per pool LRU listhead. macro F11BC$Q_POOL_WAITQ = 88,0,0,1 %; literal F11BC$S_POOL_WAITQ = 32; ! Per pool cache wait listhead. macro F11BC$L_WAITCNT = 120,0,0,1 %; literal F11BC$S_WAITCNT = 16; ! Count of waiters per pool. macro F11BC$L_POOLAVAIL = 136,0,0,1 %; literal F11BC$S_POOLAVAIL = 16; ! Available buffers per pool. macro F11BC$L_POOLCNT = 152,0,0,1 %; literal F11BC$S_POOLCNT = 16; ! Count of buffers per pool. macro F11BC$L_AMBIGQFL = 168,0,32,1 %; ! Ambiguity queue forward link. macro F11BC$L_AMBIGQBL = 172,0,32,1 %; ! Ambiguity queue back link. ! ! Cache performance counters. ! macro F11BC$L_PROCESS_HITS = 176,0,32,0 %; ! In-process buffer hits. macro F11BC$L_VALID_HITS = 180,0,32,0 %; ! Valid buffer cache hits. macro F11BC$L_INVALID_HITS = 184,0,32,0 %; ! Buffer found but invalid contents. macro F11BC$L_MISSES = 188,0,32,0 %; ! Buffer not in cache at all. macro F11BC$L_DISK_READS = 192,0,32,0 %; ! Buffer reads from disk. macro F11BC$L_DISK_WRITES = 196,0,32,0 %; ! Buffer writes to disk. macro F11BC$L_CACHE_SERIAL = 200,0,32,0 %; ! Cache serialization calls. macro F11BC$L_CACHE_STALLS = 204,0,32,0 %; ! Cache serialization stalls. macro F11BC$L_BUFFER_STALLS = 208,0,32,0 %; ! Stalls for lack of buffers. macro F11BC$T_CACHENAME = 212,0,0,0 %; literal F11BC$S_CACHENAME = 24; ! Name of this cache (display only). macro F11BC$L_LOG_BUFFER = 236,0,32,1 %; ! Pointer to activity log buffer ! ! Buffer descriptors. ! literal BFRD$M_DIRTY = %X'4'; literal BFRD$M_VALID = %X'8'; literal BFRD$M_NOPURGE = %X'10'; literal BFRD$M_ASYNCH_IN_PROG = %X'20'; literal BFRD$M_PINNED = %X'40'; literal BFRD$S_BFRDDEF = 48; ! Old size name - synonym literal BFRD$S_BFRD = 48; macro BFRD$L_QFL = 0,0,32,1 %; ! Queue forward link. macro BFRD$L_QBL = 4,0,32,1 %; ! Queue back link. macro BFRD$L_LBN = 8,0,32,0 %; ! LBN of buffer. macro BFRD$L_UCB = 12,0,32,1 %; ! UCB of buffer. macro BFRD$L_LOCKBASIS = 16,0,32,0 %; ! Unique file identifier. macro BFRD$L_SEQNUM = 20,0,32,0 %; ! Buffer validation sequence number. macro BFRD$B_FLAGS = 24,0,8,0 %; ! Status flags. macro BFRD$V_POOL = 24,0,2,0 %; literal BFRD$S_POOL = 2; ! Pool number of this buffer. macro BFRD$V_DIRTY = 24,2,1,0 %; ! Buffer has been modified. macro BFRD$V_VALID = 24,3,1,0 %; ! Buffer has been read from disk. macro BFRD$V_NOPURGE = 24,4,1,0 %; ! Do not purge from process cache macro BFRD$V_ASYNCH_IN_PROG = 24,5,1,0 %; ! This buffer has an outstanding deferred write macro BFRD$V_PINNED = 24,6,1,0 %; ! Buffer is pinned in cache macro BFRD$B_BTYPE = 25,0,8,0 %; ! Buffer type. macro BFRD$L_CURPID = 28,0,32,0 %; ! Index of current process. macro BFRD$L_NXTBFRD = 32,0,32,0 %; ! Index of next BFRD (hash chain). macro BFRD$A_BFRL = 36,0,32,0 %; ! Address of buffer lock descriptor. macro BFRD$L_SAME_BFRL = 40,0,32,0 %; ! Index to next BFRD under same BFRL macro BFRD$L_THREAD = 44,0,32,0 %; ! Thread number ! ! Buffer lock descriptor blocks. ! literal BFRL$S_BFRLDEF = 24; ! Old size name - synonym literal BFRL$S_BFRL = 24; macro BFRL$A_NXTBFRL = 0,0,32,0 %; ! Address of next BFRL in hash chain. macro BFRL$L_BFRD = 4,0,32,0 %; ! Index to first BFRD under this lock macro BFRL$L_REFCNT = 8,0,32,0 %; ! Number of buffers backed by this lock. macro BFRL$L_LKID = 12,0,32,0 %; ! Lock ID of buffer lock. macro BFRL$L_LCKBASIS = 16,0,32,0 %; ! Unique file identifier. macro BFRL$L_PARLKID = 20,0,32,0 %; ! Unique volume set identifier. !*** MODULE $FBICDEF *** ! ++ ! Define FBIC offsets and registers for Firefox systems ! -- literal FBIC$L_MODTYPE = 508; ! Module type literal FBIC$L_BUSCSR = 504; ! MBUS error status literal FBIC$L_BUSCTL = 500; ! MBUS error control signal log literal FBIC$L_BUSADR = 496; ! MBUS error address signal log literal FBIC$L_BUSDAT = 492; ! MBUS error data signal log literal FBIC$L_FBICSR = 488; ! FBIC CSR literal FBIC$L_RANGE = 484; ! I/O Space range deco=e literal FBIC$L_IPDVINT = 480; ! IP/Device interrupt literal FBIC$L_WHAMI = 476; ! Unique software ID literal FBIC$L_CPUID = 472; ! Unique hardware ID literal FBIC$L_IADR1 = 468; ! Interlock 1 address literal FBIC$L_IADR2 = 464; ! Interlock 2 address literal FBIC$L_SAVGPR = 452; ! Scratch register literal FMDC$L_FMDCSR = 488; ! FMDC CSR literal FMDC$L_BASEADDR = 484; ! Memory space base address literal FMDC$L_ECCADDR0 = 480; ! ECC error address (QW0) literal FMDC$L_ECCADDR1 = 476; ! ECC error address (QW1) literal FMDC$L_ECCSYND0 = 472; ! ECC error status (QW0) literal FMDC$L_ECCSYND1 = 468; ! ECC error status (QW1) literal FMDC$L_MSECTERR = 464; ! Memory section literal FMDC$L_MBUSSIG = 460; ! MBUS control signature literal FMDC$L_DRAMSIG = 456; ! DRAM control signature literal FMDC$L_SELFSIG = 452; ! Self test signature literal FMDC$L_LEDLATCH = 448; ! Diagnostic LED latch literal FBIC$S_MODTYPE = 4; macro FBIC$V_MODTYPE_CLASS = 0,0,8,0 %; literal FBIC$S_MODTYPE_CLASS = 8; ! Class of module macro FBIC$V_MODTYPE_SUBCLASS = 0,8,8,0 %; literal FBIC$S_MODTYPE_SUBCLASS = 8; ! Low bit echoes TYPDUAL macro FBIC$V_MODTYPE_INTERFACE = 0,16,8,0 %; literal FBIC$S_MODTYPE_INTERFACE = 8; ! FBIC interface == 1 macro FBIC$V_MODTYPE_REVISION = 0,24,8,0 %; literal FBIC$S_MODTYPE_REVISION = 8; ! FBIC hardware revision literal KA60$K_MODTYPE_FBIC = 1; ! 1 FBIC interface literal KA60$K_MODTYPE_FMDC = 2; ! 2 FMDC interface literal KA60$K_MODTYPE_FMCM = 254; literal FBIC$M_BUSCSR_DBLE = %X'10000'; literal FBIC$M_BUSCSR_SERR = %X'20000'; literal FBIC$M_BUSCSR_CTPE = %X'40000'; literal FBIC$M_BUSCSR_CDPE = %X'80000'; literal FBIC$M_BUSCSR_CTO = %X'100000'; literal FBIC$M_BUSCSR_NOS = %X'200000'; literal FBIC$M_BUSCSR_MTO = %X'400000'; literal FBIC$M_BUSCSR_ILCK = %X'800000'; literal FBIC$M_BUSCSR_MCPE = %X'1000000'; literal FBIC$M_BUSCSR_MSPE = %X'2000000'; literal FBIC$M_BUSCSR_MDPE = %X'4000000'; literal FBIC$M_BUSCSR_MTPE = %X'8000000'; literal FBIC$M_BUSCSR_IDAT = %X'10000000'; literal FBIC$M_BUSCSR_ICMD = %X'20000000'; literal FBIC$M_BUSCSR_ARB = %X'40000000'; literal FBIC$M_BUSCSR_FRZN = %X'80000000'; literal FBIC$S_BUSCSR = 4; macro FBIC$V_BUSCSR_DBLE = 0,16,1,0 %; ! MBUS double error bit macro FBIC$V_BUSCSR_SERR = 0,17,1,0 %; ! SERR macro FBIC$V_BUSCSR_CTPE = 0,18,1,0 %; ! CDAL tag store parity error macro FBIC$V_BUSCSR_CDPE = 0,19,1,0 %; ! CDAL parity error macro FBIC$V_BUSCSR_CTO = 0,20,1,0 %; ! CDAL timeout macro FBIC$V_BUSCSR_NOS = 0,21,1,0 %; ! MBUS no slave response macro FBIC$V_BUSCSR_MTO = 0,22,1,0 %; ! MBUS slave timeout macro FBIC$V_BUSCSR_ILCK = 0,23,1,0 %; ! MBUS interlock violation macro FBIC$V_BUSCSR_MCPE = 0,24,1,0 %; ! MBUS MCMD parity error macro FBIC$V_BUSCSR_MSPE = 0,25,1,0 %; ! MBUS MSTATUS parity error macro FBIC$V_BUSCSR_MDPE = 0,26,1,0 %; ! MBUS MDAL parity error macro FBIC$V_BUSCSR_MTPE = 0,27,1,0 %; ! MBUS tag parity error macro FBIC$V_BUSCSR_IDAT = 0,28,1,0 %; ! MBUS invalid data supplied macro FBIC$V_BUSCSR_ICMD = 0,29,1,0 %; ! MBUS invalid MCMD encoding macro FBIC$V_BUSCSR_ARB = 0,30,1,0 %; ! MBUS arbitration error macro FBIC$V_BUSCSR_FRZN = 0,31,1,0 %; ! MBUS error logging frozen literal FBIC$M_BUSCTL_MBRM = %X'7F'; literal FBIC$M_BUSCTL_MBRP = %X'80'; literal FBIC$M_BUSCTL_MBRQ = %X'100'; literal FBIC$M_BUSCTL_MCMD = %X'1E00'; literal FBIC$M_BUSCTL_MCPAR = %X'2000'; literal FBIC$M_BUSCTL_MSTATUS = %X'C000'; literal FBIC$M_BUSCTL_MSPAR = %X'10000'; literal FBIC$M_BUSCTL_MDPAR = %X'20000'; literal FBIC$M_BUSCTL_MBUSY = %X'40000'; literal FBIC$M_BUSCTL_MSHARED = %X'80000'; literal FBIC$M_BUSCTL_MDATINV = %X'100000'; literal FBIC$M_BUSCTL_MABORT = %X'200000'; literal FBIC$M_BUSCTL_MHALT = %X'400000'; literal FBIC$M_BUSCTL_PHASE = %X'3800000'; literal FBIC$M_BUSCTL_SLAVE = %X'4000000'; literal FBIC$M_BUSCTL_MASTER = %X'8000000'; literal FBIC$M_BUSCTL_SVDMCMD = %X'F0000000'; literal FBIC$S_BUSCTL = 4; macro FBIC$V_BUSCTL_MBRM = 0,0,7,0 %; literal FBIC$S_BUSCTL_MBRM = 7; ! MBRM signals macro FBIC$V_BUSCTL_MBRP = 0,7,1,0 %; ! MBRP signal macro FBIC$V_BUSCTL_MBRQ = 0,8,1,0 %; ! MBRQ signal macro FBIC$V_BUSCTL_MCMD = 0,9,4,0 %; literal FBIC$S_BUSCTL_MCMD = 4; ! MCMD signals macro FBIC$V_BUSCTL_MCPAR = 0,13,1,0 %; ! MCPAR signal macro FBIC$V_BUSCTL_MSTATUS = 0,14,2,0 %; literal FBIC$S_BUSCTL_MSTATUS = 2; ! MSTATUS signal macro FBIC$V_BUSCTL_MSPAR = 0,16,1,0 %; ! MSPAR macro FBIC$V_BUSCTL_MDPAR = 0,17,1,0 %; ! MDPAR macro FBIC$V_BUSCTL_MBUSY = 0,18,1,0 %; ! MBUSY macro FBIC$V_BUSCTL_MSHARED = 0,19,1,0 %; ! MSHARED macro FBIC$V_BUSCTL_MDATINV = 0,20,1,0 %; ! MDATINV macro FBIC$V_BUSCTL_MABORT = 0,21,1,0 %; ! MABORT macro FBIC$V_BUSCTL_MHALT = 0,22,1,0 %; ! MHALT macro FBIC$V_BUSCTL_PHASE = 0,23,3,0 %; literal FBIC$S_BUSCTL_PHASE = 3; ! BUS PHASE macro FBIC$V_BUSCTL_SLAVE = 0,26,1,0 %; ! SLAVE macro FBIC$V_BUSCTL_MASTER = 0,27,1,0 %; ! MASTER macro FBIC$V_BUSCTL_SVDMCMD = 0,28,4,0 %; literal FBIC$S_BUSCTL_SVDMCMD = 4; ! MCMD signal literal FBIC$M_FBICSR_CDPE = %X'1'; literal FBIC$M_FBICSR_TSTFNC = %X'3E'; literal FBIC$M_FBICSR_HALTEN = %X'80'; literal FBIC$M_FBICSR_LEDS = %X'3F00'; literal FBIC$M_FBICSR_IRQC2M = %X'F0000'; literal FBIC$M_FBICSR_IRQEN = %X'F00000'; literal FBIC$M_FBICSR_RESET = %X'1000000'; literal FBIC$M_FBICSR_HALTCPU = %X'2000000'; literal FBIC$M_FBICSR_EXCAEN = %X'4000000'; literal FBIC$M_FBICSR_CMISS = %X'8000000'; literal FBIC$M_FBICSR_MFMD = %X'C0000000'; literal FBIC$S_FBICSR = 4; macro FBIC$V_FBICSR_CDPE = 0,0,1,0 %; ! CBUS parity check enable macro FBIC$V_FBICSR_TSTFNC = 0,1,5,0 %; literal FBIC$S_FBICSR_TSTFNC = 5; ! Diagnostic test function macro FBIC$V_FBICSR_HALTEN = 0,7,1,0 %; ! Enable CPU halts macro FBIC$V_FBICSR_LEDS = 0,8,6,0 %; literal FBIC$S_FBICSR_LEDS = 6; ! FBIC LED output macro FBIC$V_FBICSR_IRQC2M = 0,16,4,0 %; literal FBIC$S_FBICSR_IRQC2M = 4; ! Interrupt request direction macro FBIC$V_FBICSR_IRQEN = 0,20,4,0 %; literal FBIC$S_FBICSR_IRQEN = 4; ! Interrupt request enable macro FBIC$V_FBICSR_RESET = 0,24,1,0 %; ! CBUS RESET macro FBIC$V_FBICSR_HALTCPU = 0,25,1,0 %; ! CBUS halt control macro FBIC$V_FBICSR_EXCAEN = 0,26,1,0 %; ! External cache enable macro FBIC$V_FBICSR_CMISS = 0,27,1,0 %; ! CBUS cache miss occurred macro FBIC$V_FBICSR_MFMD = 0,30,2,0 %; literal FBIC$S_FBICSR_MFMD = 2; ! Manufacturing mode literal FBIC$M_RANGE_MASK = %X'7FFF'; literal FBIC$M_RANGE_ENABLE = %X'8000'; literal FBIC$M_RANGE_MATCH = %X'FFFF0000'; literal FBIC$S_RANGE = 4; macro FBIC$V_RANGE_MASK = 0,0,15,0 %; literal FBIC$S_RANGE_MASK = 15; ! I/O space address range mask macro FBIC$V_RANGE_ENABLE = 0,15,1,0 %; ! I/O space address range enable macro FBIC$V_RANGE_MATCH = 0,16,16,0 %; literal FBIC$S_RANGE_MATCH = 16; ! I/O space address range match literal FBIC$M_IPDVINT_VECTOR = %X'FFFF'; literal FBIC$M_IPDVINT_DEVUNIT = %X'10000'; literal FBIC$M_IPDVINT_IPUNIT = %X'20000'; literal FBIC$M_IPDVINT_IPL14 = %X'1000000'; literal FBIC$M_IPDVINT_IPL15 = %X'2000000'; literal FBIC$M_IPDVINT_IPL16 = %X'4000000'; literal FBIC$M_IPDVINT_IPL17 = %X'8000000'; literal FBIC$S_IPDVINT = 4; macro FBIC$V_IPDVINT_VECTOR = 0,0,16,0 %; literal FBIC$S_IPDVINT_VECTOR = 16; ! Interrupt vector macro FBIC$V_IPDVINT_DEVUNIT = 0,16,1,0 %; ! Device interrupt unit macro FBIC$V_IPDVINT_IPUNIT = 0,17,1,0 %; ! I/P interrupt unit macro FBIC$V_IPDVINT_IPL14 = 0,24,1,0 %; ! Generate IPL 14 interrupt macro FBIC$V_IPDVINT_IPL15 = 0,25,1,0 %; ! Generate IPL 15 interrupt macro FBIC$V_IPDVINT_IPL16 = 0,26,1,0 %; ! Generate IPL 16 interrupt macro FBIC$V_IPDVINT_IPL17 = 0,27,1,0 %; ! Generate IPL 17 interrupt literal FBIC$M_CPUID_PROC = %X'3'; literal FBIC$M_CPUID_MID = %X'C'; literal FBIC$S_CPUID = 1; macro FBIC$V_CPUID_PROC = 0,0,2,0 %; literal FBIC$S_CPUID_PROC = 2; ! Processor identifier macro FBIC$V_CPUID_MID = 0,2,2,0 %; literal FBIC$S_CPUID_MID = 2; ! Module slot identifier literal FMDC$M_FMDCSR_RAS_CNT = %X'FF'; literal FMDC$M_FMDCSR_ST_START = %X'100'; literal FMDC$M_FMDCSR_ST_DONE = %X'200'; literal FMDC$M_FMDCSR_DTCB = %X'400'; literal FMDC$M_FMDCSR_DIS_REFRESH = %X'1000'; literal FMDC$M_FMDCSR_RPS = %X'2000'; literal FMDC$M_FMDCSR_DRS = %X'4000'; literal FMDC$M_FMDCSR_EDM = %X'18000'; literal FMDC$M_FMDCSR_FESC = %X'60000'; literal FMDC$M_FMDCSR_FEC = %X'380000'; literal FMDC$M_FMDCSR_ISR = %X'400000'; literal FMDC$M_FMDCSR_ISML = %X'800000'; literal FMDC$M_FMDCSR_MOL = %X'40000000'; literal FMDC$M_FMDCSR_EFS = %X'80000000'; literal FMDC$S_FMDCSR = 4; macro FMDC$V_FMDCSR_RAS_CNT = 0,0,8,0 %; literal FMDC$S_FMDCSR_RAS_CNT = 8; ! Refresh counter macro FMDC$V_FMDCSR_ST_START = 0,8,1,0 %; ! Self test start macro FMDC$V_FMDCSR_ST_DONE = 0,9,1,0 %; ! Self test complete macro FMDC$V_FMDCSR_DTCB = 0,10,1,0 %; ! Data to check bits macro FMDC$V_FMDCSR_DIS_REFRESH = 0,12,1,0 %; ! Disable refresh macro FMDC$V_FMDCSR_RPS = 0,13,1,0 %; ! Refresh period select macro FMDC$V_FMDCSR_DRS = 0,14,1,0 %; ! Diagnostic refresh start macro FMDC$V_FMDCSR_EDM = 0,15,2,0 %; literal FMDC$S_FMDCSR_EDM = 2; ! ECC diagnostic mode macro FMDC$V_FMDCSR_FESC = 0,17,2,0 %; literal FMDC$S_FMDCSR_FESC = 2; ! Force error sub category macro FMDC$V_FMDCSR_FEC = 0,19,3,0 %; literal FMDC$S_FMDCSR_FEC = 3; ! Force error category macro FMDC$V_FMDCSR_ISR = 0,22,1,0 %; ! Inhibit SBE reporting macro FMDC$V_FMDCSR_ISML = 0,23,1,0 %; ! Inhibit SBE MSECTERR log macro FMDC$V_FMDCSR_MOL = 0,30,1,0 %; ! Module on-line macro FMDC$V_FMDCSR_EFS = 0,31,1,0 %; ! Error flag summary literal FMDC$M_BASEADDR_STARTADDR = %X'7FF00000'; literal FMDC$M_BASEADDR_MEMSPEN = %X'80000000'; literal FMDC$S_BASEADDR = 4; macro FMDC$V_BASEADDR_STARTADDR = 0,20,11,0 %; literal FMDC$S_BASEADDR_STARTADDR = 11; ! Starting memory address macro FMDC$V_BASEADDR_MEMSPEN = 0,31,1,0 %; ! Memory space enable literal FMDC$M_ECCADDR_RAMERRADDR0 = %X'7FFFFF0'; literal FMDC$S_ECCADDR = 4; macro FMDC$V_ECCADDR_RAMERRADDR0 = 0,4,23,0 %; literal FMDC$S_ECCADDR_RAMERRADDR0 = 23; ! ECC Error address literal FMDC$M_ECCSYND_SYND0 = %X'FF'; literal FMDC$M_ECCSYND_SBE = %X'100'; literal FMDC$M_ECCSYND_MBE = %X'200'; literal FMDC$M_ECCSYND_ERROVFL = %X'1C00'; literal FMDC$M_ECCSYND_SUBCB = %X'FF0000'; literal FMDC$M_ECCSYND_READCB = %X'FF000000'; literal FMDC$S_ECCSYND = 4; macro FMDC$V_ECCSYND_SYND0 = 0,0,8,0 %; literal FMDC$S_ECCSYND_SYND0 = 8; ! ECC syndronme macro FMDC$V_ECCSYND_SBE = 0,8,1,0 %; ! Single bit error macro FMDC$V_ECCSYND_MBE = 0,9,1,0 %; ! Multiple bit error macro FMDC$V_ECCSYND_ERROVFL = 0,10,3,0 %; literal FMDC$S_ECCSYND_ERROVFL = 3; ! Error overflow field macro FMDC$V_ECCSYND_SUBCB = 0,16,8,0 %; literal FMDC$S_ECCSYND_SUBCB = 8; ! Substitute check bits macro FMDC$V_ECCSYND_READCB = 0,24,8,0 %; literal FMDC$S_ECCSYND_READCB = 8; ! Read check bits !*** MODULE $FBUSDEF *** ! + ! This file describes the layout of Futurebus CSR space. The information is ! based on the IEEE Futurebus specification 896.2 and IEEE CSR Architecture ! specification P1212. ! - literal FBUS$M_TEST_STATUS_FAILED = %X'1'; literal FBUS$M_TEST_STATUS_TIMEOUT = %X'2'; literal FBUS$M_TEST_STATUS_IMPLEMENTED = %X'4'; literal FBUS$M_TEST_STATUS_LOOPING = %X'8'; literal FBUS$M_TEST_STATUS_ACTIVE = %X'10'; literal FBUS$M_TEST_STATUS_reserved = %X'20'; literal FBUS$M_TEST_STATUS_STEP = %X'3FFFC0'; literal FBUS$M_TEST_STATUS_FRU = %X'FC00000'; literal FBUS$M_TEST_STATUS_CAT = %X'F0000000'; literal FBUS$M_ROM_BASE_CRC_VALUE = %X'FFFF'; literal FBUS$M_ROM_BASE_CRC_LENGTH = %X'FF0000'; literal FBUS$M_ROM_BASE_BUS_INFO_LENGTH = %X'FF000000'; literal FBUS$M_ROOT_DIR_BASE_CRC = %X'FFFF'; literal FBUS$M_ROOT_DIR_BASE_LENGTH = %X'FFFF0000'; literal FBUS$K_NODE_SPACE_LENGTH = 4096; literal FBUS$S_FBUSDEF = 4096; ! Old size name, synonym for FBUS$S_FBUS literal FBUS$S_FBUS = 4096; ! The following definitions are for CORE CSR space, required by a all Futurebus ! nodes. macro FBUS$L_CSR_CORE = 0,0,0,0 %; ! CSR Core base offset macro FBUS$L_STATE_CLEAR = 0,0,32,0 %; macro FBUS$L_STATE_SET = 4,0,32,0 %; macro FBUS$L_NODE_IDS = 8,0,32,0 %; macro FBUS$L_RESET_START = 12,0,32,0 %; macro FBUS$L_INDIRECT_ADDRESS = 16,0,32,0 %; macro FBUS$L_INDIRECT_DATA = 20,0,32,0 %; macro FBUS$L_SPLIT_TIMEOUT_HI = 24,0,32,0 %; macro FBUS$L_SPLIT_TIMEOUT_LO = 28,0,32,0 %; macro FBUS$L_ARGUMENT_HI = 32,0,32,0 %; macro FBUS$L_ARGUMENT_LO = 36,0,32,0 %; macro FBUS$L_TEST_START = 40,0,32,0 %; macro FBUS$L_TEST_STATUS = 44,0,32,0 %; macro FBUS$V_TEST_STATUS_FAILED = 44,0,1,0 %; macro FBUS$V_TEST_STATUS_TIMEOUT = 44,1,1,0 %; macro FBUS$V_TEST_STATUS_IMPLEMENTED = 44,2,1,0 %; macro FBUS$V_TEST_STATUS_LOOPING = 44,3,1,0 %; macro FBUS$V_TEST_STATUS_ACTIVE = 44,4,1,0 %; macro FBUS$V_TEST_STATUS_reserved = 44,5,1,0 %; macro FBUS$V_TEST_STATUS_STEP = 44,6,16,0 %; literal FBUS$S_TEST_STATUS_STEP = 16; macro FBUS$V_TEST_STATUS_FRU = 44,22,6,0 %; literal FBUS$S_TEST_STATUS_FRU = 6; macro FBUS$V_TEST_STATUS_CAT = 44,28,4,0 %; literal FBUS$S_TEST_STATUS_CAT = 4; macro FBUS$L_UNITS_BASE_HI = 48,0,32,0 %; macro FBUS$L_UNITS_BASE_LO = 52,0,32,0 %; macro FBUS$L_UNITS_BOUND_HI = 56,0,32,0 %; macro FBUS$L_UNITS_BOUND_LO = 60,0,32,0 %; macro FBUS$L_MEMORY_BASE_HI = 64,0,32,0 %; macro FBUS$L_MEMORY_BASE_LO = 68,0,32,0 %; macro FBUS$L_MEMORY_BOUND_HI = 72,0,32,0 %; macro FBUS$L_MEMORY_BOUND_LO = 76,0,32,0 %; macro FBUS$L_INTERRUPT_TARGET = 80,0,32,0 %; macro FBUS$L_INTERRUPT_MASK = 84,0,32,0 %; macro FBUS$L_CLOCK_VALUE_HI = 88,0,32,0 %; macro FBUS$L_CLOCK_VALUE_MID = 92,0,32,0 %; macro FBUS$L_CLOCK_TICK_PERIOD_MID = 96,0,32,0 %; macro FBUS$L_CLOCK_TICK_PERIOD_LO = 100,0,32,0 %; macro FBUS$L_CLOCK_STROBE_ARRIVED_HI = 104,0,32,0 %; macro FBUS$L_CLOCK_STROBE_ARRIVED_MID = 108,0,32,0 %; macro FBUS$L_CLOCK_STROBE = 112,0,32,0 %; macro FBUS$L_CLOCK_INFO1 = 116,0,32,0 %; macro FBUS$L_CLOCK_REFERENCE = 120,0,32,0 %; macro FBUS$L_CLOCK_INFO3 = 124,0,32,0 %; macro FBUS$L_MESSAGE_REQUEST = 128,0,0,0 %; literal FBUS$S_MESSAGE_REQUEST = 64; ! Message Request area macro FBUS$L_MESSAGE_RESPONSE = 192,0,0,0 %; literal FBUS$S_MESSAGE_RESPONSE = 64; ! Message Response area macro FBUS$L_P1212_RESERVED = 256,0,0,0 %; literal FBUS$S_P1212_RESERVED = 128; ! Reserved by P1212 macro FBUS$L_ERROR_HI = 384,0,32,0 %; macro FBUS$L_ERROR_LO = 388,0,32,0 %; macro FBUS$L_FADR_HI = 392,0,32,0 %; macro FBUS$L_FADR_LO = 396,0,32,0 %; macro FBUS$L_ERROR_LOG_BUFFER = 400,0,0,0 %; literal FBUS$S_ERROR_LOG_BUFFER = 112; ! The following definitions describe the Futurebus dependent CSR area macro FBUS$L_BUS_DEPENDENT = 512,0,0,0 %; ! Bus Dependent CSR base offset macro FBUS$L_LOGICAL_COMMON_CONTROL = 512,0,32,0 %; macro FBUS$L_LOGICAL_MODULE_CONTROL = 516,0,32,0 %; macro FBUS$L_BUS_PROP_DELAY = 520,0,32,0 %; macro FBUS$L_COMP_SETTLING_TIME = 524,0,32,0 %; macro FBUS$L_TRANSACTION_TIMEOUT = 528,0,32,0 %; macro FBUS$L_MSG_SELECT_MASK_HI = 532,0,32,0 %; macro FBUS$L_MSG_SELECT_MASK_LO = 536,0,32,0 %; macro FBUS$L_BSY_RTRY_COUNTER = 540,0,32,0 %; macro FBUS$L_BSY_RTRY_DELAY = 544,0,32,0 %; macro FBUS$L_ERR_RTRY_COUNTER = 548,0,32,0 %; macro FBUS$L_ERR_RTRY_DELAY = 552,0,32,0 %; macro FBUS$L_BUS_DEPENDENT_RESERVED = 556,0,0,0 %; literal FBUS$S_BUS_DEPENDENT_RESERVED = 212; macro FBUS$L_VENDOR_DEPENDENT = 768,0,0,0 %; literal FBUS$S_VENDOR_DEPENDENT = 256; ! The following definitions describe the Futurebus ROM area. macro FBUS$L_ROM_BASE = 1024,0,32,0 %; macro FBUS$V_ROM_BASE_CRC_VALUE = 1024,0,16,0 %; literal FBUS$S_ROM_BASE_CRC_VALUE = 16; macro FBUS$V_ROM_BASE_CRC_LENGTH = 1024,16,8,0 %; literal FBUS$S_ROM_BASE_CRC_LENGTH = 8; macro FBUS$V_ROM_BASE_BUS_INFO_LENGTH = 1024,24,8,0 %; literal FBUS$S_ROM_BASE_BUS_INFO_LENGTH = 8; macro FBUS$L_BUS_ID = 1028,0,32,0 %; macro FBUS$L_PROFILE_ID_HI = 1032,0,32,0 %; macro FBUS$L_PROFILE_ID_LO = 1036,0,32,0 %; macro FBUS$L_MOD_LOG_CAP = 1040,0,32,0 %; macro FBUS$L_NODE_CAP_EXT = 1044,0,32,0 %; macro FBUS$L_COMP_INT_DELAY = 1048,0,32,0 %; macro FBUS$L_PACKET_SPEED = 1052,0,32,0 %; macro FBUS$L_MSG_FRAME_SIZE = 1056,0,32,0 %; macro FBUS$L_BSY_RTRY_COUNTER_CAP = 1060,0,32,0 %; macro FBUS$L_BSY_RTRY_DELAY_CAP = 1064,0,32,0 %; macro FBUS$L_ERR_RTRY_COUNTER_CAP = 1068,0,32,0 %; macro FBUS$L_ERR_RTRY_DELAY_CAP = 1072,0,32,0 %; macro FBUS$L_BUS_INFO_RESERVED = 1076,0,0,0 %; literal FBUS$S_BUS_INFO_RESERVED = 12; macro FBUS$L_ROOT_DIR_BASE = 1088,0,32,0 %; macro FBUS$V_ROOT_DIR_BASE_CRC = 1088,0,16,0 %; literal FBUS$S_ROOT_DIR_BASE_CRC = 16; macro FBUS$V_ROOT_DIR_BASE_LENGTH = 1088,16,16,0 %; literal FBUS$S_ROOT_DIR_BASE_LENGTH = 16; macro FBUS$L_INITIAL_UNITS_SPACE_BASE = 2048,0,0,0 %; ! Initial Units Space base offset macro FBUS$L_INITIAL_UNITS_SPACE_fill = 2048,0,0,0 %; literal FBUS$S_INITIAL_UNITS_SPACE_fill = 2048; ! The following definitions describe the format of entries in root directories, ! subdirectories, and leaves. Root directories, subdirectories, and leaves are ! basically all the same thing -- an area of ROM space containing information ! about the module, node, or unit. See P1212 for the gory details on directory entry ! specification. Briefly, each type of directory contains an initial entry which ! indicates the size of the directory followed by one or more entries. ! All entries in a directory contain a key in byte 0, which identifies ! the type of entry, and a value in bytes 1, 2, and 3. The value can be an ! immediate value or a pointer, depending on the key value. ! Directory base entry format literal FBUS$M_DIR_BASE_CRC = %X'FFFF'; literal FBUS$M_DIR_BASE_LENGTH = %X'FFFF0000'; literal FBUS$S_DIR_BASE_DEF = 4; ! Old size name, synonym for FBUS$S_DIR_BASE literal FBUS$S_DIR_BASE = 4; macro FBUS$L_DIR_BASE = 0,0,32,0 %; macro FBUS$V_DIR_BASE_CRC = 0,0,16,0 %; literal FBUS$S_DIR_BASE_CRC = 16; macro FBUS$V_DIR_BASE_LENGTH = 0,16,16,0 %; literal FBUS$S_DIR_BASE_LENGTH = 16; literal FBUS$M_DIR_ENTRY_VALUE = %X'FFFFFF'; literal FBUS$M_DIR_ENTRY_KEY = %X'FF000000'; literal FBUS$S_DIR_ENTRY_DEF = 4; ! Old size name, synonym for FBUS$S_DIR_ENTRY literal FBUS$S_DIR_ENTRY = 4; ! Directory entry format macro FBUS$L_DIR_ENTRY = 0,0,32,0 %; macro FBUS$V_DIR_ENTRY_VALUE = 0,0,24,0 %; literal FBUS$S_DIR_ENTRY_VALUE = 24; macro FBUS$V_DIR_ENTRY_KEY = 0,24,8,0 %; literal FBUS$S_DIR_ENTRY_KEY = 8; ! The following definition describes the Digital implementation of ROM ! directory entry MODULE_SW_VERSION literal FBUS$M_DIGITAL_SW_VERSION_NODE = %X'1'; literal FBUS$M_DIGITAL_SW_VERSION_UNIT = %X'3E'; literal FBUS$M_DIGITAL_SW_VERSION_VAR = %X'3FC0'; literal FBUS$M_DIGITAL_SW_VERSION_NUM = %X'FFC000'; literal FBUS$M_DIGITAL_SW_VERSION_KEY = %X'FF000000'; literal FBUS$S_DIGITAL_SW_VERSION_DEF = 4; ! Old size name, synonym for FBUS$S_DIGITAL_SW_VERSION literal FBUS$S_DIGITAL_SW_VERSION = 4; macro FBUS$L_DIGITAL_SW_VERSION = 0,0,32,0 %; macro FBUS$V_DIGITAL_SW_VERSION_NODE = 0,0,1,0 %; macro FBUS$V_DIGITAL_SW_VERSION_UNIT = 0,1,5,0 %; literal FBUS$S_DIGITAL_SW_VERSION_UNIT = 5; macro FBUS$V_DIGITAL_SW_VERSION_VAR = 0,6,8,0 %; literal FBUS$S_DIGITAL_SW_VERSION_VAR = 8; macro FBUS$V_DIGITAL_SW_VERSION_NUM = 0,14,10,0 %; literal FBUS$S_DIGITAL_SW_VERSION_NUM = 10; macro FBUS$V_DIGITAL_SW_VERSION_KEY = 0,24,8,0 %; literal FBUS$S_DIGITAL_SW_VERSION_KEY = 8; ! Format of Bus Array entry hardware_id quadword. When we probe the ! Futurebus, we concatenate the vendor_id and the sw_version (which are both ! read from the Fbus ROM area) and store the resulting quadword in a bus array ! entry. The following structure defines the format of the hardware id ! quadword in the bus array entry. literal DEC_FBUS$S_HW_ID_DEF = 8; ! Old size name, synonym for DEC_FBUS$S_HW_ID literal DEC_FBUS$S_FBUS_HW_ID = 8; macro DEC_FBUS$Q_HW_ID = 0,0,0,0 %; literal DEC_FBUS$S_HW_ID = 8; macro DEC_FBUS$L_HW_ID_SW_VERSION = 0,0,32,0 %; macro DEC_FBUS$L_HW_ID_VENDOR_ID = 4,0,32,0 %; ! The following key types are defined by IEEE 1212. literal FBUS_KEY$K_TEX_LEAF = 129; literal FBUS_KEY$K_TEX_SUBD = 193; literal FBUS_KEY$K_BUS_DEP_INFO_LEAF = 130; literal FBUS_KEY$K_BUS_DEP_INFO_SUBD = 194; literal FBUS_KEY$K_MODULE_VENDOR_ID = 3; literal FBUS_KEY$K_MODULE_HW_VERSION = 4; literal FBUS_KEY$K_MODULE_SPEC_ID = 5; literal FBUS_KEY$K_MODULE_SW_VERSION = 6; literal FBUS_KEY$K_MODULE_DEP_INFO_LEAF = 135; literal FBUS_KEY$K_MODULE_DEP_INFO_SUBD = 199; literal FBUS_KEY$K_NODE_VENDOR_ID = 8; literal FBUS_KEY$K_NODE_HW_VERSION = 9; literal FBUS_KEY$K_NODE_SPEC_ID = 10; literal FBUS_KEY$K_NODE_SW_VERSION = 11; literal FBUS_KEY$K_NODE_CAPABILITIES = 12; literal FBUS_KEY$K_NODE_UNIQUE_ID_LEAF = 141; literal FBUS_KEY$K_NODE_UNITS_EXTENT = 14; literal FBUS_KEY$K_NODE_UNITS_EXTENT_OF = 78; literal FBUS_KEY$K_NODE_MEM_EXTENT = 15; literal FBUS_KEY$K_NODE_MEM_EXTENT_OF = 79; literal FBUS_KEY$K_NODE_DEP_INFO_LEAF = 144; literal FBUS_KEY$K_NODE_DEP_INFO_SUBD = 208; literal FBUS_KEY$K_UNIT_SUB = 209; literal FBUS_KEY$K_UNIT_SPEC_ID = 18; literal FBUS_KEY$K_UNIT_SW_VERSION = 19; literal FBUS_KEY$K_UNIT_DEP_INFO_LEAF = 148; literal FBUS_KEY$K_UNIT_DEP_INFO_SUBD = 212; literal FBUS_KEY$K_UNIT_LOCATION = 149; literal FBUS_KEY$K_UNIT_POLL_MASK = 149; ! The following constants are useful for bus probing literal FBUS$K_NODE0_BASE_CSR = -262144; literal FBUS$K_MAX_NODE_NUMBER = 63; literal FBUS$K_DIGITAL_VENDOR_ID = 524331; ! Create constants to represent Futurebus commands. These are the ! values that will be copied to the command field of the hardware mailbox ! for Futurebus register access. ! ! The following encodings for the Futurebus command field are taken ! from the Cobra I/O Module spec. These encodings should be the same ! for a Futurebus on any platform. ! ! 7 6 5 4 3 2 1 0 ! +---+---+---+---+---+---+---+---+ ! |AW | 0 |DW |WR | transaction | ! +---+---+---+---+---+---+---+---+ ! ! Bit Meaning ! --- ------- ! AW = 0 32 bit addressing ! AW = 1 64 bit addressing ! DW = 0 32 bit data width ! DW = 1 64 bit data width ! WR = 0 read transaction ! WR = 1 write transaction ! transaction = 0 unlocked transaction ! transaction = 2 partial (masked) transaction ! ! Bit 31 of the mailbox command field is defined by the Alpha SRM to ! mean that the command is a write. This bit is not passed onto the ! Futurebus--it is intended as a performance assist for a local side ! module. ! literal FBUS$K_RDQUAD32 = 32; ! Read, unlocked, AW=32, DW=64 literal FBUS$K_RDLONG32 = 0; ! Read, unlocked, AW=32, DW=32 literal FBUS$K_RDWORD32 = 2; ! Read, partial, AW=32, DW=32 literal FBUS$K_RDBYTE32 = 2; ! Read, partial, AW=32, DW=32 literal FBUS$K_WTQUAD32 = 48; ! write, unlocked, AW=32, DW=64 literal FBUS$K_WTLONG32 = 16; ! write, unlocked, AW=32, DW=32 literal FBUS$K_WTWORD32 = 18; ! write, partial, AW=32, DW=32 literal FBUS$K_WTBYTE32 = 18; ! write, partial, AW=32, DW=32 literal FBUS$K_RDQUAD64 = 160; ! Read, unlocked, AW=64, DW=64 literal FBUS$K_RDLONG64 = 128; ! Read, unlocked, AW=64, DW=32 literal FBUS$K_RDWORD64 = 130; ! Read, partial, AW=64, DW=32 literal FBUS$K_RDBYTE64 = 130; ! Read, partial, AW=64, DW=32 literal FBUS$K_WTQUAD64 = 176; ! Write, unlocked, AW=64, DW=64 literal FBUS$K_WTLONG64 = 144; ! Write, unlocked, AW=64, DW=32 literal FBUS$K_WTWORD64 = 146; ! Write, partial, AW=64, DW=32 literal FBUS$K_WTBYTE64 = 146; ! Write, partial , AW=64, DW=32 !*** MODULE $FCBDEF *** ! + ! FCB - FILE CONTROL BLOCK ! ! THERE IS ONE FILE CONTROL BLOCK FOR EACH UNIQUELY ACCESSED FILE ON A ! VOLUME. THE FILE CONTROL BLOCK PROVIDES THE VEHICLE WHEREBY SHARED ! ACCESS TO A FILE MAY BE CONTROLLED. ! Note LBN and volume size related fields have been promoted to quadwords. ! ODS-II/V will never support volumes larger than 1TB; the promotions are ! in anticipation of a new file system that will use the FCB in common. ! - literal FCB$M_FILE_ATTRIBUTES = %X'F'; literal FCB$M_FILE_CONTENTS = %X'F0'; literal FCB$M_FLUSH_ON_CLOSE = %X'F00'; literal FCB$M_CACHING_OPTIONS_MBZ = %X'FFFFF000'; literal FCB$C_DEFAULT = 0; ! Use default caching policy literal FCB$C_WRITETHROUGH = 1; ! Use writethrough caching literal FCB$C_WRITEBEHIND = 2; ! Use writebehind caching literal FCB$C_NOCACHING = 3; ! Do not cache file literal FCB$C_FLUSH = 1; ! Flush file from cache when file closed literal FCB$C_NOFLUSH = 2; ! Retain file in cache when file closed literal FCB$M_VCC_STATE = %X'7'; literal FCB$K_LENGTH = 376; ! LENGTH OF STANDARD FCB literal FCB$C_LENGTH = 376; ! LENGTH OF STANDARD FCB literal FCB$S_FCBDEF = 376; ! Old size name - synonym literal FCB$S_FCB = 376; macro FCB$L_FCBFL = 0,0,32,1 %; ! FCB LIST FORWARD LINK macro FCB$L_FCBBL = 4,0,32,1 %; ! FCB LIST BACKWARD LINK macro FCB$W_SIZE = 8,0,16,0 %; ! SIZE OF FCB IN BYTES macro FCB$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE OF FCB macro FCB$B_ACCLKMODE = 11,0,8,0 %; ! Access lock mode. macro FCB$L_EXFCB = 12,0,32,1 %; ! ADDRESS OF EXTENSION FCB macro FCB$L_PRIMFCB = 16,0,32,1 %; ! Pointer to Primary FCB if ! this is an extension FCB ! else zero macro FCB$L_ORB = 20,0,32,1 %; ! Address of file ORB macro FCB$L_WLFL = 24,0,32,1 %; ! WINDOW LISTHEAD FORWARD LINK macro FCB$L_WLBL = 28,0,32,1 %; ! WINDOW LISTHEAD BACKWARD LINK macro FCB$L_REFCNT = 32,0,32,0 %; ! Total references to this FCB. macro FCB$L_ACNT = 36,0,32,0 %; ! FILE ACCESS COUNT macro FCB$L_WCNT = 40,0,32,0 %; ! FILE WRITER COUNT macro FCB$L_LCNT = 44,0,32,0 %; ! FILE LOCK COUNT macro FCB$L_TCNT = 48,0,32,0 %; ! COUNT OF TRUNCATE LOCKS macro FCB$L_STATUS = 52,0,32,0 %; ! FILE STATUS macro FCB$V_DIR = 52,0,1,0 %; ! FCB IS A DIRECTORY LRU ENTRY macro FCB$V_MARKDEL = 52,1,1,0 %; ! FILE IS MARKED FOR DELETE macro FCB$V_BADBLK = 52,2,1,0 %; ! BAD BLOCK ENCOUNTERED IN FILE macro FCB$V_EXCL = 52,3,1,0 %; ! FILE IS EXCLUSIVELY ACCESSED macro FCB$V_SPOOL = 52,4,1,0 %; ! FILE IS AN INTERMEDIATE SPOOL FILE macro FCB$V_RMSLOCK = 52,5,1,0 %; ! FILE IS OPEN WITH RMS RECORD LOCKING macro FCB$V_ERASE = 52,6,1,0 %; ! ERASE DATA WHEN BLOCKS REMOVED FROM FILE macro FCB$V_BADACL = 52,7,1,0 %; ! ACL IS CORRUPT macro FCB$V_STALE = 52,8,1,0 %; ! Reconstruct FCB from header. macro FCB$V_DELAYTRNC = 52,9,1,0 %; ! Delay truncation. macro FCB$V_LIMBO = 52,10,1,0 %; ! FCB is linked into the LIMBO queue macro FCB$V_ISDIR = 52,11,1,0 %; ! This FCB is a directory FCB macro FCB$V_NOMOVE = 52,12,1,0 %; ! This file is NOT to be MOVEFILE'ed macro FCB$V_SHELVED = 52,13,1,0 %; ! This file is shelved macro FCB$V_NOSHELVABLE = 52,14,1,0 %; ! This file is NOT to be SHELVED'ed macro FCB$V_PRESHELVED = 52,15,1,0 %; ! This file has been shelved, but ! the data has not been erased from disk macro FCB$Q_OPENTIME = 56,0,0,0 %; literal FCB$S_OPENTIME = 8; ! Creation time of FCB macro FCB$L_READS = 64,0,32,0 %; ! Total count of read I/Os macro FCB$L_WRITES = 68,0,32,0 %; ! Total count of write I/Os macro FCB$L_SPLIT_IO = 72,0,32,0 %; ! Total count of split I/Os macro FCB$L_ASSIST_IO = 76,0,32,0 %; ! Total count of file system assisted I/Os macro FCB$W_FID = 80,0,0,0 %; literal FCB$S_FID = 6; ! FILE IDENTIFICATION macro FCB$W_FID_NUM = 80,0,16,0 %; ! FILE NUMBER macro FCB$W_FID_SEQ = 82,0,16,0 %; ! FILE SEQUENCE NUMBER macro FCB$W_FID_RVN = 84,0,16,0 %; ! RELATIVE VOLUME NUMBER macro FCB$B_FID_RVN = 84,0,8,0 %; ! SHORT FORM RVN macro FCB$B_FID_NMX = 85,0,8,0 %; ! EXTENDED FILE NUMBER macro FCB$W_FID_DIRNUM = 80,0,16,0 %; ! Directory number of File-Id macro FCB$L_FID_RECNUM = 82,0,32,0 %; ! Record number of File-ID macro FCB$W_SEGN = 86,0,16,0 %; ! FILE SEGMENT NUMBER macro FCB$L_STVBN = 88,0,32,0 %; macro FCB$Q_STVBN = 88,0,0,0 %; literal FCB$S_STVBN = 8; macro FCB$L_STLBN = 96,0,32,0 %; macro FCB$Q_STLBN = 96,0,0,0 %; literal FCB$S_STLBN = 8; macro FCB$L_HDLBN = 104,0,32,0 %; macro FCB$Q_HDLBN = 104,0,0,0 %; literal FCB$S_HDLBN = 8; macro FCB$L_FILESIZE = 112,0,32,0 %; macro FCB$Q_FILESIZE = 112,0,0,0 %; literal FCB$S_FILESIZE = 8; macro FCB$L_EFBLK = 120,0,32,0 %; macro FCB$Q_EFBLK = 120,0,0,0 %; literal FCB$S_EFBLK = 8; macro FCB$L_VERSIONS = 128,0,32,0 %; ! MAXIMUM NUMBER OF VERSIONS IN DIRECTORY macro FCB$L_DIRSEQ = 132,0,32,0 %; ! DIRECTORY USE SEQUENCE NUMBER macro FCB$L_DIRINDX = 136,0,32,0 %; ! Directory index pointer macro FCB$L_ACCLKID = 140,0,32,0 %; ! Access lock ID. macro FCB$L_LOCKBASIS = 144,0,32,0 %; ! Lock basis for this FCB. macro FCB$L_TRUNCVBN = 148,0,32,0 %; ! VBN for delayed truncation. (Files-11 B) macro FCB$L_NUMEXTENTS = 148,0,32,0 %; ! Number of extents recorded (Files-11 C/D) macro FCB$L_CACHELKID = 152,0,32,0 %; ! Cache interlock lock ID macro FCB$L_DIRLCKID = 156,0,32,0 %; ! Support for directory cache invalidation macro FCB$L_HIGHWATER = 160,0,32,0 %; macro FCB$Q_HIGHWATER = 160,0,0,0 %; literal FCB$S_HIGHWATER = 8; macro FCB$L_NEWHIGHWATER = 168,0,32,0 %; macro FCB$Q_NEWHIGHWATER = 168,0,0,0 %; literal FCB$S_NEWHIGHWATER = 8; macro FCB$L_HWM_UPDATE = 176,0,32,0 %; ! Count of writes past highwater mark macro FCB$L_HWM_ERASE = 180,0,32,0 %; ! Count of writes starting past highwater mark macro FCB$L_HWM_PARTIAL = 184,0,32,0 %; ! Count of partially validated erase operations macro FCB$L_REVISION = 188,0,32,0 %; ! File revision macro FCB$Q_HWMQHD = 192,0,0,0 %; literal FCB$S_HWMQHD = 8; ! High water mark queue header macro FCB$L_HWM_WAITFL = 192,0,32,1 %; ! Highwater mark update queue macro FCB$L_HWM_WAITBL = 196,0,32,1 %; ! Highwater mark update queue macro FCB$Q_LIMBOQHD = 192,0,0,0 %; literal FCB$S_LIMBOQHD = 8; ! LIMBO queue header macro FCB$L_LIMBOFL = 192,0,32,1 %; ! Highwater mark update queue macro FCB$L_LIMBOBL = 196,0,32,1 %; ! Highwater mark update queue ! ! NOTA BENE: ! ! The following is an embedded ORB. This structure should only be referenced ! through the FCB$L_ORB pointer (using ORB$ field names). The existing (FCB) ! fields are left for source code and binary compatibility in privileged ! software that thinks it knows what an FCB and its ORB look like. ! ! Third-party developers would be well advised to remove all references to ! these FCB symbols as soon as possible. You have been warned! ! macro FCB$R_ORB = 200,0,0,0 %; literal FCB$S_ORB = 124; ! Object's Rights Block macro FCB$L_FILEOWNER = 200,0,32,0 %; ! FILE OWNER UIC macro FCB$W_UICMEMBER = 200,0,16,0 %; ! MEMBER NUMBER macro FCB$W_UICGROUP = 202,0,16,0 %; ! GROUP NUMBER macro FCB$Q_ACMODE = 216,0,0,0 %; literal FCB$S_ACMODE = 8; ! Access mode protection vector macro FCB$L_SYS_PROT = 224,0,32,0 %; ! Protection word/vector macro FCB$W_FILEPROT = 224,0,16,0 %; ! FILE PROTECTION MASK macro FCB$L_OWN_PROT = 228,0,32,0 %; ! Owner protection macro FCB$L_GRP_PROT = 232,0,32,0 %; ! Group protection macro FCB$L_WOR_PROT = 236,0,32,0 %; ! World protection macro FCB$L_ACLFL = 240,0,32,1 %; ! ACCESS CONTROL LIST FORWARD LINK macro FCB$L_ACLBL = 244,0,32,1 %; ! ACCESS CONTROL LIST BACKWARD LINK macro FCB$R_MIN_CLASS_PROT = 248,0,0,0 %; literal FCB$S_MIN_CLASS_PROT = 20; ! Minimum security classification mask macro FCB$R_MAX_CLASS_PROT = 268,0,0,0 %; literal FCB$S_MAX_CLASS_PROT = 20; ! Maximum security classification mask ! ! End of embedded ORB ! ! ! Define fields and constant values for FCB$L_CACHING_OPTIONS ! longword. These must match [STARLET]FIBDEF.SDL exactly. ! macro FCB$L_CACHING_OPTIONS = 336,0,32,0 %; macro FCB$V_FILE_ATTRIBUTES = 336,0,4,0 %; literal FCB$S_FILE_ATTRIBUTES = 4; ! File attributes caching field macro FCB$V_FILE_CONTENTS = 336,4,4,0 %; literal FCB$S_FILE_CONTENTS = 4; ! File contents caching field macro FCB$V_FLUSH_ON_CLOSE = 336,8,4,0 %; literal FCB$S_FLUSH_ON_CLOSE = 4; ! Flush file on close field macro FCB$V_CACHING_OPTIONS_MBZ = 336,12,20,0 %; literal FCB$S_CACHING_OPTIONS_MBZ = 20; ! Must be zero macro FCB$L_STATUS2 = 340,0,32,0 %; ! Additional file status macro FCB$V_VCC_STATE = 340,0,3,0 %; literal FCB$S_VCC_STATE = 3; ! Replicated caching attribute (see FH2DEF) macro FCB$Q_CFB = 344,0,0,0 %; literal FCB$S_CFB = 8; macro FCB$L_CFCB = 352,0,32,1 %; ! VBN Cache pointer macro FCB$Q_ACCDATE = 360,0,0,0 %; literal FCB$S_ACCDATE = 8; ! access date macro FCB$Q_MODDATE = 368,0,0,0 %; literal FCB$S_MODDATE = 8; ! modification date !*** MODULE $FCPDEF IDENT X-1 *** literal FCP_CNTL$M_WRITE_DATA = %X'1'; literal FCP_CNTL$M_READ_DATA = %X'2'; literal FCP_CNTL$M_RESERVED1 = %X'1'; literal FCP_CNTL$M_ABORT_TASK_SET = %X'2'; literal FCP_CNTL$M_CLEAR_TASK_SET = %X'4'; literal FCP_CNTL$M_RESERVED2 = %X'18'; literal FCP_CNTL$M_TARGET_RESET = %X'20'; literal FCP_CNTL$M_CLEAR_ACA = %X'40'; literal FCP_CNTL$M_TERMINATE_TASK = %X'80'; literal FCP_CNTL$M_TASK_ATTRIBUTE = %X'7'; literal FCP_CNTL$K_SIMPLE = 0; ! Simple tag literal FCP_CNTL$K_HEAD = 1; ! Head of Queue tag literal FCP_CNTL$K_ORDERED = 2; ! Ordered Queue tag literal FCP_CNTL$K_ACA = 4; ! ACA tag literal FCP_CNTL$K_UNTAGGED = 5; ! Untagged literal FCP_CNTL$S_FCP_CNTL_T = 4; macro FCP_CNTL$L_FCP_CNTL_BITS = 0,0,32,1 %; macro FCP_CNTL$R_EXE_MGT_CODE_OVERLAY = 0,0,8,0 %; ! Execution management codes macro FCP_CNTL$B_EXE_MGT_CODE = 0,0,8,0 %; macro FCP_CNTL$B_EXE_MGT_CODE_BITS = 0,0,8,1 %; macro FCP_CNTL$V_WRITE_DATA = 0,0,1,0 %; ! SCSI write operation macro FCP_CNTL$V_READ_DATA = 0,1,1,0 %; ! SCSI read operation macro FCP_CNTL$R_TASK_MGT_FLAGS_OVERLAY = 1,0,8,0 %; ! Task management flags macro FCP_CNTL$B_TASK_MGT_FLAGS = 1,0,8,0 %; macro FCP_CNTL$B_TASK_MGT_FLAGS_BITS = 1,0,8,1 %; macro FCP_CNTL$V_RESERVED1 = 1,0,1,0 %; ! Reserved macro FCP_CNTL$V_ABORT_TASK_SET = 1,1,1,0 %; ! ABORT TASK SET request macro FCP_CNTL$V_CLEAR_TASK_SET = 1,2,1,0 %; ! CLEAR TASK SET request macro FCP_CNTL$V_RESERVED2 = 1,3,2,0 %; literal FCP_CNTL$S_RESERVED2 = 2; ! Reserved macro FCP_CNTL$V_TARGET_RESET = 1,5,1,0 %; ! TARGET RESET request macro FCP_CNTL$V_CLEAR_ACA = 1,6,1,0 %; ! CLEAR ACA request macro FCP_CNTL$V_TERMINATE_TASK = 1,7,1,0 %; ! TERMINATE TASK request ! Task codes macro FCP_CNTL$R_TASK_CODE_OVERLAY = 2,0,8,0 %; macro FCP_CNTL$B_TASK_CODE = 2,0,8,0 %; macro FCP_CNTL$B_TASK_CODE_BITS = 2,0,8,1 %; macro FCP_CNTL$V_TASK_ATTRIBUTE = 2,0,3,0 %; literal FCP_CNTL$S_TASK_ATTRIBUTE = 3; ! Task attribute values: macro FCP_CNTL$B_RESERVED4 = 3,0,8,0 %; ! Reserved ! X-4 Define CDB length consistently literal FCP_CMND$S_FCP_CMND = 32; macro FCP_CMND$Q_FCP_LUN = 0,0,0,0 %; literal FCP_CMND$S_FCP_LUN = 8; macro FCP_CMND$R_FCP_CNTL = 8,0,32,0 %; literal FCP_CMND$S_FCP_CNTL = 4; macro FCP_CMND$B_FCP_CDB = 12,0,0,0 %; literal FCP_CMND$S_FCP_CDB = 16; macro FCP_CMND$L_FCP_DL = 28,0,32,0 %; ! X-4 Define an SDA-accessible symbol for the size of this structure literal FCP_STATUS$M_FCP_RSP_LEN_VALID = %X'1'; literal FCP_STATUS$M_FCP_SNS_LEN_VALID = %X'2'; literal FCP_STATUS$M_FCP_RESID_OVER = %X'4'; literal FCP_STATUS$M_FCP_RESID_UNDER = %X'8'; literal FCP_STATUS$M_RESERVED1 = %X'F0'; literal FCP_STATUS$S_FCP_STATUS_T = 4; macro FCP_STATUS$B_SCSI_STATUS = 0,0,8,0 %; ! SCSI status byte macro FCP_STATUS$R_STATUS_FLAGS_OVERLAY = 1,0,8,0 %; macro FCP_STATUS$B_STATUS_FLAGS = 1,0,8,0 %; macro FCP_STATUS$B_STATUS_FLAGS_BITS = 1,0,8,1 %; macro FCP_STATUS$V_FCP_RSP_LEN_VALID = 1,0,1,0 %; ! FCP_RSP_LEN is valid macro FCP_STATUS$V_FCP_SNS_LEN_VALID = 1,1,1,0 %; ! FCP_SNS_LEN is valid macro FCP_STATUS$V_FCP_RESID_OVER = 1,2,1,0 %; ! Overflow occurred macro FCP_STATUS$V_FCP_RESID_UNDER = 1,3,1,0 %; ! Underflow occurred macro FCP_STATUS$V_RESERVED1 = 1,4,4,0 %; literal FCP_STATUS$S_RESERVED1 = 4; macro FCP_STATUS$B_RESERVED2 = 2,0,8,0 %; ! Reserved macro FCP_STATUS$B_RESERVED3 = 3,0,8,0 %; ! Reserved literal FCP_RSP_INFO$K_SUCCESS = 0; ! Function complete literal FCP_RSP_INFO$K_DATA_LEN_MISMATCH = 1; ! FCP_DATA <> BURST_LEN literal FCP_RSP_INFO$K_INVALID_CMD = 2; ! FCP_CMND fields invalid literal FCP_RSP_INFO$K_DATA_RO_MISMATCH = 3; ! FCP_DATA RO <> FCP_XFER_RDY DATA_RO literal FCP_RSP_INFO$K_UNSUPPORTED_FUNC = 4; ! Tsk mgt function not supported literal FCP_RSP_INFO$K_FUNC_FAILED = 5; ! Tsk mgt function failed literal FCP_RSP_INFO$S_FCP_RSP_INFO_T = 8; macro FCP_RSP_INFO$B_RESERVED1 = 0,0,32,0 %; literal FCP_RSP_INFO$S_RESERVED1 = 4; macro FCP_RSP_INFO$B_RSP_CODE = 4,0,8,0 %; ! Response codes (p. 34) macro FCP_RSP_INFO$B_RESERVED2 = 5,0,24,0 %; literal FCP_RSP_INFO$S_RESERVED2 = 3; ! Reserved literal FCP_RSP$S_FCP_RSP = 288; macro FCP_RSP$B_RESERVED1 = 0,0,0,0 %; literal FCP_RSP$S_RESERVED1 = 8; ! Reserved macro FCP_RSP$R_FCP_STATUS = 8,0,32,0 %; literal FCP_RSP$S_FCP_STATUS = 4; ! FCP status macro FCP_RSP$L_FCP_RESID = 12,0,32,0 %; ! Residual count macro FCP_RSP$L_FCP_SNS_LEN = 16,0,32,0 %; ! No. of valid FCP_SNS_INFO bytes macro FCP_RSP$L_FCP_RSP_LEN = 20,0,32,0 %; ! No. of valid FCP_RSP_INFO btyes macro FCP_RSP$R_SCSI_RSP_INFO = 24,0,0,0 %; literal FCP_RSP$S_SCSI_RSP_INFO = 8; ! Info on FCP protocol failures ! X-4 Define an SDA-accessible symbol for the size of this structure up to the SCSI Sense Info macro FCP_RSP$B_SCSI_SNS_INFO = 32,0,0,0 %; literal FCP_RSP$S_SCSI_SNS_INFO = 256; ! Sense data (following a Check Condition) literal FCP_LPP$M_RSPNDR_PROC_ASSOC_VALID = %X'4000'; literal FCP_LPP$M_ORIG_PROC_ASSOC_VALID = %X'8000'; literal FCP_LPP$S_LOGOUT_PARAM_PAGE_T = 16; ! Longword 0 macro FCP_LPP$L_LPP_FLAGS = 0,0,32,1 %; macro FCP_LPP$V_RESERVED1 = 0,0,8,0 %; literal FCP_LPP$S_RESERVED1 = 8; macro FCP_LPP$V_RSP_CODE = 0,8,4,0 %; literal FCP_LPP$S_RSP_CODE = 4; macro FCP_LPP$V_RESERVED2 = 0,12,2,0 %; literal FCP_LPP$S_RESERVED2 = 2; macro FCP_LPP$V_RSPNDR_PROC_ASSOC_VALID = 0,14,1,0 %; macro FCP_LPP$V_ORIG_PROC_ASSOC_VALID = 0,15,1,0 %; macro FCP_LPP$V_RESERVED3 = 0,16,16,0 %; literal FCP_LPP$S_RESERVED3 = 16; ! Longword 1 macro FCP_LPP$L_ORIG_PROC_ASSOC = 4,0,32,1 %; ! Longword 2 macro FCP_LPP$L_RSPNDR_PROC_ASSOC = 8,0,32,1 %; ! Longword 3 macro FCP_LPP$L_RESERVED4 = 12,0,32,1 %; literal FCP_SPP$M_RESERVED1 = %X'FF'; literal FCP_SPP$M_ACC_RSP_CODE = %X'F00'; literal FCP_SPP$K_SUCCESS = 1; ! Request executed literal FCP_SPP$K_INSUFF_RESOURCES = 2; ! Target has no resources to establish img pair literal FCP_SPP$K_INIT_INCOMPLETE = 3; ! Initialization incomplete for target image literal FCP_SPP$K_NONEXISTENT_TARGET = 4; ! The specified target image does not exist literal FCP_SPP$K_CONFIG_RESTRICTION = 5; ! Target image's predefined config precluded this img pr literal FCP_SPP$K_CONDITIONAL_SUCCESS = 6; ! Some requested service parameters were not set literal FCP_SPP$K_MULTIPAGE_DISALLOWED = 7; ! Destination N_Port cannot process multipage requests literal FCP_SPP$M_RESERVED2 = %X'1000'; literal FCP_SPP$M_ESTABLISHED_IMAGE_PAIR = %X'2000'; literal FCP_SPP$M_RSPNDR_PROC_ASSOC_VALID = %X'4000'; literal FCP_SPP$M_ORIG_PROC_ASSOC_VALID = %X'8000'; literal FCP_SPP$M_WRITE_XFER_RDY_DISABLED = %X'1'; literal FCP_SPP$M_READ_XFER_RDY_DISABLED = %X'2'; literal FCP_SPP$M_DATA_RSP_MIX_ALLOWED = %X'4'; literal FCP_SPP$M_CMD_DATA_MIX_ALLOWED = %X'8'; literal FCP_SPP$M_TARGET_FUNCTION = %X'10'; literal FCP_SPP$M_INITIATOR_FUNCTION = %X'20'; literal FCP_SPP$M_DATA_OVERLAY_ALLOWED = %X'40'; literal FCP_SPP$M_RESERVED3 = %X'FFFFFF80'; literal FCP_SPP$S_SERVICE_PARAM_PAGE_T = 16; macro FCP_SPP$L_SPP_ASSOCIATOR_FLAGS = 0,0,32,1 %; macro FCP_SPP$V_RESERVED1 = 0,0,8,0 %; literal FCP_SPP$S_RESERVED1 = 8; ! Reserved macro FCP_SPP$V_ACC_RSP_CODE = 0,8,4,0 %; literal FCP_SPP$S_ACC_RSP_CODE = 4; ! Accept response codes (PRLI: p. 43, PRLO: p. 49) macro FCP_SPP$V_RESERVED2 = 0,12,1,0 %; ! Reserved macro FCP_SPP$V_ESTABLISHED_IMAGE_PAIR = 0,13,1,0 %; ! Image pair established macro FCP_SPP$V_RSPNDR_PROC_ASSOC_VALID = 0,14,1,0 %; ! Responder process associator valid macro FCP_SPP$V_ORIG_PROC_ASSOC_VALID = 0,15,1,0 %; ! Originator process associator valid macro FCP_SPP$B_TYPE_CODE_EXTENSION = 2,0,8,1 %; ! Type code extension macro FCP_SPP$B_TYPE_CODE = 3,0,8,1 %; ! Type code (eg., SCSI FCP = 08) macro FCP_SPP$L_ORIG_PROC_ASSOC = 4,0,32,1 %; ! Originator process associator macro FCP_SPP$L_RSPNDR_PROC_ASSOC = 8,0,32,1 %; ! Responder process associator macro FCP_SPP$R_SPP_LONGWORD_3 = 12,0,32,0 %; literal FCP_SPP$S_SPP_LONGWORD_3 = 4; macro FCP_SPP$L_COMMON_SERVICE_PARAMETER = 12,0,32,1 %; macro FCP_SPP$L_SPP_FUNCTION_FLAGS = 12,0,32,1 %; ! Service parameters (p. 17) macro FCP_SPP$V_WRITE_XFER_RDY_DISABLED = 12,0,1,0 %; ! FCP_XFER_RDY disallowed on write macro FCP_SPP$V_READ_XFER_RDY_DISABLED = 12,1,1,0 %; ! FCP_XFER_RDY disallowed on read macro FCP_SPP$V_DATA_RSP_MIX_ALLOWED = 12,2,1,0 %; ! FCP_DATA and FCP_RSP may be combined in one IU macro FCP_SPP$V_CMD_DATA_MIX_ALLOWED = 12,3,1,0 %; ! FCP_CMND and FCP_DATA may be combined in one IU macro FCP_SPP$V_TARGET_FUNCTION = 12,4,1,0 %; ! Functioning as a target macro FCP_SPP$V_INITIATOR_FUNCTION = 12,5,1,0 %; ! Functioning as an initiator macro FCP_SPP$V_DATA_OVERLAY_ALLOWED = 12,6,1,0 %; ! Data overlays allowed macro FCP_SPP$V_RESERVED3 = 12,7,25,0 %; literal FCP_SPP$S_RESERVED3 = 25; ! Reserved ! This structure was added in revision X-4 literal FER$K_FCP_CDB_LENGTH = 16; ! Calculate the number of quadwords in the array literal FER$K_FCP_CMND_QUADS = 4; ! Create a quadword-aligned array of quadwords literal FER$K_SCSI_SNS_INFO_LENGTH = 16; ! Calculate the number of quadwords in the array literal FER$K_FCP_RSP_QUADS = 6; ! Create a quadword-aligned array of quadwords literal FER$S_FCP_EVENT_RECORD = 136; ! -------------------- ! I/O Request Section ! -------------------- ! System time of request completion macro FER$Q_SYSTIME = 0,0,0,0 %; literal FER$S_SYSTIME = 8; ! Restart sequence number macro FER$L_FER_SEQNUM = 8,0,32,0 %; ! Class driver UCB address from SCDT macro FER$PS_CLASS_UCB = 12,0,32,1 %; ! Requested Byte Count macro FER$L_REQUESTED_BCNT = 16,0,32,0 %; ! IRP sequence number (identifies I/O request) macro FER$L_SEQNUM = 20,0,32,0 %; ! --------------------------- ! I/O Request Status Section ! --------------------------- ! KPB or fork thread restart (by FC-AD) status macro FER$L_RESTART_STATUS = 24,0,32,0 %; ! FC-AD status mapped to an OpenVMS status - this will usually be the ! same as the RESTART_STATUS, but there are cases (at least one: when ! a request times out) when a KPB is restarted by the FC-AD with a ! special status which will differ from PORT_STATUS macro FER$L_PORT_STATUS = 28,0,32,0 %; ! Additional data (if any) associated with the FC-AD status macro FER$L_EXTENDED_STATUS = 32,0,32,0 %; ! VMS status returned by protocol driver macro FER$L_PROTOCOL_STATUS = 36,0,32,0 %; ! Returned Byte Count macro FER$L_RETURNED_BCNT = 40,0,32,0 %; ! -------------------- ! FCP Command Section ! -------------------- ! ! This array will be loaded with quadword copies. When an SDA ! extension references it for output it can copy the array ! address to an FCP_CMND structure and use FCP_CMND$ symbols ! ! Define language-specific symbols for the CDB length ! Define language-specific symbols for the number of quadwords macro FER$Q_FCP_CMND_QUAD = 48,0,0,0 %; literal FER$S_FCP_CMND_QUAD = 32; ! --------------------- ! FCP Response Section ! --------------------- ! ! This array will be loaded with quadword copies. When an SDA ! extension references it for output it can copy the array ! address to an FCP_RSP structure and use FCP_RSP$ symbols ! ! Define the number of bytes of sense data we want in this array ! Define language-specific symbols for sense info length ! Define language-specific symbols for the number of quadwords macro FER$Q_FCP_RSP_QUAD = 80,0,0,0 %; literal FER$S_FCP_RSP_QUAD = 48; ! SCSI Connection Descriptor Table address macro FER$PS_SCDT = 128,0,32,1 %; ! FibreChannel Logical Address (FC-LA) macro FER$L_FC_LA = 132,0,32,1 %; ! Current FC_PROT version literal FCPROT$C_STRUCTURE_VERSION = 1; ! Supported protocol count literal FCPROT$C_SUPPORTED_PROTOCOL_COUNT = 3; ! Supported devices-per-protocol protocol count literal FCPROT$C_DEVICES_PER_PROTOCOL = 26; ! FC protcol connection vectors literal FCPROT$C_LENGTH = 40; literal FCPROT$S_FC_PROT = 40; ! Pointer to next FCPROT macro FCPROT$PS_FCPROT_FLINK = 0,0,32,1 %; ! Pointer to previous FCPROT macro FCPROT$PS_FCPROT_BLINK = 4,0,32,1 %; ! Structure size macro FCPROT$W_SIZE = 8,0,16,0 %; ! Structure type (DYN$C_MISC) macro FCPROT$B_TYPE = 10,0,8,0 %; ! Structure sub-type (DYN$C_FCPROT) macro FCPROT$B_SUBTYPE = 11,0,8,0 %; ! Version of this structure macro FCPROT$L_STRUCTURE_VERSION = 12,0,32,0 %; ! Protocol count macro FCPROT$Q_PROTOCOL_COUNT = 16,0,0,0 %; literal FCPROT$S_PROTOCOL_COUNT = 8; ! Pointers to protocol vector blocks macro FCPROT$PS_PROTOCOLS = 24,0,0,1 %; literal FCPROT$S_PROTOCOLS = 12; ! ***************************************** ! Define the length of the structure. ! ***************************************** ! Quadword align the length ! FCPROT length ! FC protcol connection vectors literal FCPROT_VECTAB$S_FCPROT_VECTAB = 104; ! Pointers to protocol descriptors macro FCPROT_VECTAB$PS_DESCRIP = 0,0,0,1 %; literal FCPROT_VECTAB$S_DESCRIP = 104; ! FC protcol descriptors literal FCPROT_DESCRIP$S_FCPROT_DESCRIP = 8; ! Pointer to UCB of driver associated with protocol macro FCPROT_DESCRIP$PS_UCB = 0,0,32,1 %; ! Pointers to protocol vector macro FCPROT_DESCRIP$PS_VECTOR = 4,0,32,1 %; !*** MODULE FCPHDEF IDENT X-6 *** ! + ! FCPHDEF - ! - ! + ! ! Extended Link Service codes ! ! If the code represents an Extended Link Service request, and not ! a response (what the documents above call a reply), then it will ! appear in bits 31:24 of word 0 of the payload sent with the ! following frame header control bits: ! ! * Routing, Word 0, bits 31:28 = 0x02 (R_CTL) ! * Information Category, Word 0, bits 27:24 = 0x02 (Unsolicited Control) ! * Type, Word 1, bits 31:24 = 0x01 ! ! If the code represents a response, the following values appear: ! ! * Routing, Word 0 (R_CTL), bits 31:28 = 0x02 ! * Information Category, Word 0, bits 27:24 = 0x02 (Solicited Control) ! * Type, Word 1, bits 31:24 = 0x01 ! ! Ref: Fibre Channel Physical & Signaling Interface-2 (FC-PH-2) Rev 7.3 ! Working draft of 5-January-1996 ! Page 36, table 61 ! ! - literal ELS$K_LS_RJT = 1; ! 0x01 Link Service Reject (response) literal ELS$K_ACC = 2; ! 0x02 Accept (response) literal ELS$K_PLOGI = 3; ! 0x03 N_Port Login literal ELS$K_FLOGI = 4; ! 0x04 F_Port Login literal ELS$K_LOGO = 5; ! 0x05 Logout literal ELS$K_ABTX = 6; ! 0x06 Abort Exchange literal ELS$K_RSC = 7; ! 0x07 Read Connection Status literal ELS$K_RES = 8; ! 0x08 Read Exchange Status Block literal ELS$K_RSS = 9; ! 0x09 Read Sequence Status Block literal ELS$K_RSI = 10; ! 0x0A Request Sequence Initiative literal ELS$K_ESTS = 11; ! 0x0B Establish Streaming literal ELS$K_ESTC = 12; ! 0x0C Estimate Credit literal ELS$K_ADVC = 13; ! 0x0D Advise Credit literal ELS$K_RTV = 14; ! 0x0E Read Time-Out Value literal ELS$K_RLS = 15; ! 0x0F Read Link Status literal ELS$K_ECHO = 16; ! 0x10 Echo literal ELS$K_TEST = 17; ! 0x11 Test literal ELS$K_RRQ = 18; ! 0x12 Reinstate Recovery Qualifier literal ELS$K_ELP = 16; literal ELS$K_PRLI = 32; ! 0x20 Process Login literal ELS$K_PRLO = 33; ! 0x21 Process Logout literal ELS$K_SCN = 34; ! 0x22 State Change Notification literal ELS$K_TPLS = 35; ! 0x23 Test Process Login State literal ELS$K_TPRLO = 36; ! 0x24 Third Party Logout State literal ELS$K_GAID = 48; ! 0x30 Get Alias_ID literal ELS$K_FACT = 49; ! 0x31 Fabric Activate Alias_ID literal ELS$K_FDACT = 50; ! 0x32 Fabric Deactivate Alias_ID literal ELS$K_NACT = 51; ! 0x33 N_Port Activate Alias_ID literal ELS$K_NDACT = 52; ! 0x34 N_Port Deactivate Alias_ID literal ELS$K_QOSR = 64; ! 0x40 Quality of Service Request literal ELS$K_RVCS = 65; ! 0x41 Read Virtual Circuit Status literal ELS$K_PDISC = 80; ! 0x50 Discover N_Port Service Parameters literal ELS$K_FDISC = 81; ! 0x51 Discover F_Port Service Parameters literal ELS$K_ADISC = 82; ! 0x52 Discover Address literal ELS$K_RNC = 83; ! 0x53 Report Node Capability literal ELS$K_FARP_REQ = 84; ! 0X54 Fibre Channel Addr resolution proto rq literal ELS$K_FARP_REPLY = 85; ! 0x55 Fibre Channel Addr resolution proto reply literal ELS$K_RPS = 86; ! 0x56 Read Port Status Block literal ELS$K_RPL = 87; ! 0X57 Read Port List literal ELS$K_FAN = 96; ! 0x60 Fabric Address Notification literal ELS$K_RSCN = 97; ! 0x61 Registered State Change Notification literal ELS$K_SCR = 98; ! 0x62 State Change Request literal ELS$K_RNFT = 99; ! 0x63 Report node FC-4 types literal ELS$K_RNID = 120; ! 0x78 Request Node Identification data literal ELS$K_RLIR = 121; ! 0x79 Registered Link Incident Report literal ELS$K_LIRR = 122; ! 0x7A Link Incident Record Registration literal ELS$K_SRL = 123; ! 0x7B Scan Remote Loop ! + ! ! Frame Header type codes for when routing bits are set to ! FC-4 Device Data or FC-4 Link Data. ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of June 1, 1994 ! Page 100 table 36 ! ! - literal FCPH$K_ISO_8802_2_LLC = 4; ! 0x04 ISO/IEC 8802-2 LLC literal FCPH$K_ISO_8802_2_LLC_SNAP = 5; ! 0x05 ISO/IEC 8802-2 LLC/SNAP literal FCPH$K_RESERVED_1 = 6; ! 0x06 Reserved literal FCPH$K_RESERVED_2 = 7; ! 0x07 Reserved literal FCPH$K_SCSI_FCP = 8; ! 0x08 SCSI FCP literal FCPH$K_SCSI_GPP = 9; ! 0x09 SCSI GPP literal FCPH$K_IPI_3 = 16; literal FCPH$K_IPI_MASTER = 17; literal FCPH$K_IPI_SLAVE = 18; literal FCPH$K_IPI_PEER = 19; literal FCPH$K_CP_IPI_MASTER = 21; literal FCPH$K_CP_IPI_SLAVE = 22; literal FCPH$K_CP_IPI_PEER = 23; literal FCPH$K_SBCCS_CHANNEL = 25; literal FCPH$K_SBCCS_CONTROL_UNIT = 26; literal FCPH$K_FIBRE_CHANNEL_SERVICES = 32; ! + ! ! Frame Header type codes for when routing bits are set to ! Basic or Extended Link Data. ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of June 1, 1994 ! Page 100 table 34 ! ! - literal FCPH$K_BASIC_LINK_SRVC_TYPE = 0; literal FCPH$K_EXTENDED_LINK_SRVC_TYPE = 1; literal FCPH$K_ALL_ONES_MASK = 255; ! + ! ! Information Categories used in the R_CTL frame header ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of June 1, 1994 ! Page 98 table 29 ! ! - literal FCPH$K_UNCAT_INFO = 0; ! Uncategorized information literal FCPH$K_SOLICITED_DATA = 1; literal FCPH$K_UNSOLICITED_CONTROL = 2; literal FCPH$K_SOLICITED_CONTROL = 3; literal FCPH$K_UNSOLICITED_DATA = 4; literal FCPH$K_DATA_DESCRIPTOR = 5; literal FCPH$K_UNSOLICITED_COMMAND = 6; literal FCPH$K_COMMAND_STATUS = 7; ! + ! ! Routing Bits used in the R_CTL frame header field ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of June 1, 1994 ! Page 97 table 28 ! ! - literal FCPH$K_DEVICE_DATA = 0; ! 0x00 FC-4 Device data frame literal FCPH$K_RESERVED_3 = 1; ! 0x01 literal FCPH$K_EXTENDED_LINK_SRVC = 2; ! 0x02 literal FCPH$K_LINK_DATA = 3; ! 0x03 FC-4 Link Data literal FCPH$K_VIDEO_DATA = 4; ! 0x04 literal FCPH$K_RESERVED_4 = 5; ! 0x05 literal FCPH$K_RESERVED_5 = 6; ! 0x06 literal FCPH$K_RESERVED_6 = 7; ! 0x07 literal FCPH$K_BASIC_LINK_SRVC = 8; ! 0x08 literal FCPH$K_RESERVED_7 = 9; ! 0x09 literal FCPH$K_RESERVED_8 = 10; ! 0x0A literal FCPH$K_RESERVED_9 = 11; ! 0x0B literal FCPH$K_LINK_CONTROL = 12; ! 0x0C literal FCPH$K_FC4_DEVICE_DATA = 0; ! + ! ! BA_RJT (Basic Reject) Reason Codes ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 140, table 59 ! ! - literal BA_RJT$K_INVALID = 1; ! 0x01 Invalid Command Code literal BA_RJT$K_LOGICAL_ERR = 3; ! 0x03 Logical Error literal BA_RJT$K_LOGICAL_BSY = 5; ! 0x05 Logical Busy literal BA_RJT$K_PROTOCOL_ERR = 7; ! 0x07 Protocol Error literal BA_RJT$K_UNABLE = 9; ! 0x09 Unable to Perform Command Request ! + ! ! BA_RJT Type ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 139, figure 57 ! ! - literal BA_RJT$S_BA_RJT_T = 4; macro BA_RJT$B_VENDOR_UNIQUE = 0,0,8,1 %; macro BA_RJT$B_REASON_EXP = 1,0,8,1 %; macro BA_RJT$B_REASON = 2,0,8,1 %; macro BA_RJT$B_RESERVED = 3,0,8,1 %; ! + ! ! BA_RJT (Basic Reject) Reason Code Explanations ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 140, table 60 ! ! - literal BA_RJT_EXP$K_NO_MORE_INFO = 0; ! 0x00 No Additional Explanation literal BA_RJT_EXP$K_INVALID_ID_COMBO = 3; ! 0x03 Invalid OX_ID - RX_ID Combination literal BA_RJT_EXP$K_SEQUENCE_ABORTED = 5; ! 0x05 Sequence Aborted, No Sequence Information Provided ! + ! ! LS_RJT_RSN Type ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 156, figure 58 ! ! - literal LS_RJT_RSN$S_LS_RJT_RSN_T = 4; macro LS_RJT_RSN$B_VENDOR_UNIQUE = 0,0,8,1 %; macro LS_RJT_RSN$B_REASON_EXP = 1,0,8,1 %; macro LS_RJT_RSN$B_REASON = 2,0,8,1 %; macro LS_RJT_RSN$B_RESERVED = 3,0,8,1 %; ! + ! ! LS_RJT Type ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 155, section 21.5.2 ! ! - literal LS_RJT$M_RESERVED1 = %X'FFFFFF'; literal LS_RJT$S_LS_RJT = 8; ! ELS command code field macro LS_RJT$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro LS_RJT$V_RESERVED1 = 0,0,24,0 %; literal LS_RJT$S_RESERVED1 = 24; macro LS_RJT$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! Reason the request is being rejected macro LS_RJT$R_REASON = 4,0,32,0 %; literal LS_RJT$S_REASON = 4; ! + ! ! LS_RJT (Link Service Reject) Reason Codes ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 156, table 90 ! ! - literal LS_RJT$K_INVALID_LA = 1; ! 0x01 Invalid LA Command Code literal LS_RJT$K_LOGICAL_ERR = 3; ! 0x03 Logical Error literal LS_RJT$K_LOGICAL_BSY = 5; ! 0x05 Logical Busy literal LS_RJT$K_PROTOCOL_ERR = 7; ! 0x07 Protocol Error literal LS_RJT$K_UNABLE = 9; ! 0x09 Unable to Perform Command Request literal LS_RJT$K_CMD_UNSUPPORTED = 11; ! 0x0B Command Not Supported ! + ! ! LS_RJT (Link Service Reject) Reason Code Explanations ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 157, table 91 ! ! - literal LS_RJT_EXP$K_NO_MORE_INFO = 0; ! 0x00 No Additional Explanation literal LS_RJT_EXP$K_SPARM_OPTS = 1; ! 0x01 Service Parameter Error - Options literal LS_RJT_EXP$K_SPARM_INI_CTL = 3; ! 0x03 Service Parameter Error - Initiator Control literal LS_RJT_EXP$K_SPARM_REC_CTL = 5; ! 0x05 Service Parameter Error - Recipient Control literal LS_RJT_EXP$K_SPARM_RDAT_FLD_SZ = 7; ! 0x07 Service Parameter Error - Receive Data Field Size literal LS_RJT_EXP$K_SPARM_CONCUR_SEQ = 9; ! 0x09 Service Parameter Error - Concurrent Sequences literal LS_RJT_EXP$K_SPARM_CREDIT = 11; ! 0x0B Service Parameter Error - Credit literal LS_RJT_EXP$K_INV_PORT_NAME = 13; ! 0x0D Invalid N-Port or F-Port Name literal LS_RJT_EXP$K_INV_NAME = 14; ! 0x0E Invalid Node or Fabric Name literal LS_RJT_EXP$K_INV_COMMON_SPARMS = 15; ! 0x0F Invalid Common Service Parameters literal LS_RJT_EXP$K_INV_ASSOC_HDR = 17; ! 0x11 Invalid Association Header literal LS_RJT_EXP$K_ASSOC_HDR_REQ = 19; ! 0x13 Association Header Required literal LS_RJT_EXP$K_INV_ORIG_S_ID = 21; ! 0x15 Invalid Originator S_ID literal LS_RJT_EXP$K_INV_ID_COMBO = 23; ! 0x17 Invalid OX_ID + RX_ID Combination literal LS_RJT_EXP$K_CMD_REQ_IN_PROG = 25; ! 0x19 Command or Request Already in Progress literal LS_RJT_EXP$K_INV_N_PORT_ID = 31; ! 0x1F Invalid N-Port Identifier literal LS_RJT_EXP$K_INV_SEQ_ID = 33; ! 0x21 Invalid Sequence Identifier (SEQ_ID) literal LS_RJT_EXP$K_INV_EXC_ABORT = 35; ! 0x23 Attempt to Abort an Invalid Exchange literal LS_RJT_EXP$K_INACT_EXC_ABORT = 37; ! 0x25 Attempt to Abort an Inactive Exchange literal LS_RJT_EXP$K_REC_QUAL_REQ = 39; ! 0x27 Recovery Qualifier Required literal LS_RJT_EXP$K_INSF_RES_FOR_LOGIN = 41; ! 0x29 Insufficent Resources to Support Login literal LS_RJT_EXP$K_UNABLE_REQ_DAT = 42; ! 0x2A Unable to Supply Requested Data literal LS_RJT_EXP$K_REQ_UNSUP = 44; ! 0x2C Request Not Supported ! + ! ! F_BSY Type ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 126, figure 54 ! ! - literal F_BSY$M_REASON = %X'F'; literal F_BSY$M_LINK_CONTROL = %X'F0'; literal F_BSY$S_F_BSY_T = 1; macro F_BSY$V_REASON = 0,0,4,0 %; literal F_BSY$S_REASON = 4; macro F_BSY$V_LINK_CONTROL = 0,4,4,0 %; literal F_BSY$S_LINK_CONTROL = 4; ! + ! ! F_BSY Reason codes ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 126, table 51 ! ! - literal F_BSY_RSN$K_FABRIC_BSY = 1; literal F_BSY_RSN$K_N_PORT_BSY = 3; ! + ! ! P_BSY Type ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 127, figure 55 ! ! - literal P_BSY$S_P_BSY_T = 4; macro P_BSY$B_VENDOR_UNIQUE = 0,0,8,1 %; macro P_BSY$B_RESERVED1 = 1,0,8,1 %; macro P_BSY$B_REASON = 2,0,8,1 %; macro P_BSY$B_ACTION = 3,0,8,1 %; ! + ! ! P_BSY Action codes ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 127, table 52 ! ! - literal P_BSY_ACTION$K_SEQ_TERM = 1; literal P_BSY_ACTION$K_SEQ_ACT = 2; ! + ! ! P_BSY Reason codes ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 128, table 53 ! ! - literal P_BSY_RSN$K_PHYS_N_PORT_BSY = 1; literal P_BSY_RSN$K_N_PORT_RES_BSY = 3; literal P_BSY_RSN$K_VENDOR_UNIQUE_BSY = 255; ! + ! ! P_BSY Type ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 128, figure 56 ! ! - literal RJT$S_RJT_T = 4; macro RJT$B_VENDOR_UNIQUE = 0,0,8,1 %; macro RJT$B_RESERVED1 = 1,0,8,1 %; macro RJT$B_REASON = 2,0,8,1 %; macro RJT$B_ACTION = 3,0,8,1 %; ! + ! ! Reject Action codes ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 129, table 54 ! ! - literal RJT_ACTION$K_RETRYABLE_ERR = 1; literal RJT_ACTION$K_NON_RETRYABLE_ERR = 2; ! + ! ! Reject Reason codes ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Pages 129-130, table 55 ! ! - literal RJT_RSN$K_INV_D_ID = 1; ! 0x01 Invalid D_ID literal RJT_RSN$K_INV_S_ID = 2; ! 0x02 Invalid S_ID literal RJT_RSN$K_PORT_UNAVAIL_TEMP = 3; ! 0x03 N-Port Not Available, Temporary literal RJT_RSN$K_PORT_UNAVAIL_PERM = 4; ! 0x04 N-Port Not Available, Permanent literal RJT_RSN$K_CLASS_UNSUP = 5; ! 0x05 Class Not Supported literal RJT_RSN$K_DELIM_USE_ERR = 6; ! 0x06 Delimiter Usage Error literal RJT_RSN$K_TYPE_UNSUP = 7; ! 0x07 TYPE Not Supported literal RJT_RSN$K_INV_LINK_CTL = 8; ! 0x08 Invalid Link Control literal RJT_RSN$K_INV_R_CTL = 9; ! 0x09 Invalid R_CTL Field literal RJT_RSN$K_INV_F_CTL = 10; ! 0x0A Invalid F_CTL Field literal RJT_RSN$K_INV_OX_ID = 11; ! 0x0B Invalid OX_ID literal RJT_RSN$K_INV_RX_ID = 12; ! 0x0C Invalid RX_ID literal RJT_RSN$K_INV_SEQ_ID = 13; ! 0x0D Invalid SEQ_ID literal RJT_RSN$K_INV_DF_CTL = 14; ! 0x0E Invalid DF_CTL literal RJT_RSN$K_INV_SEQ_CNT = 15; ! 0x0F Invalid SEQ_CNT literal RJT_RSN$K_INV_PARM_FLD = 16; ! 0x10 Invalid Parameter Field literal RJT_RSN$K_EXC_ERR = 17; ! 0x11 Exchange Error literal RJT_RSN$K_PROTOCOL_ERR = 18; ! 0x12 Protocol Error literal RJT_RSN$K_INCORRECT_LEN = 19; ! 0x13 Incorrect Length literal RJT_RSN$K_UNEXPECTED_ACK = 20; ! 0x14 Unexpected ACK literal RJT_RSN$K_RESERVED_0x15 = 21; ! 0x15 Reserved literal RJT_RSN$K_LOGIN_REQUIRED = 22; ! 0x16 Login Required literal RJT_RSN$K_EXCESS_SEQ_ATTEMPT = 23; ! 0x17 Excessive Sequences Attempted literal RJT_RSN$K_UNABLE_EST_EXC = 24; ! 0x18 Unable to Establish Exchange literal RJT_RSN$K_EXP_SEC_HDR_UNSUP = 25; ! 0x19 Expiration Security Header Not Supported literal RJT_RSN$K_FABRIC_PATH_UNAVAIL = 26; ! 0x1A Fabric Path Not Available literal RJT_RSN$K_VENDOR_UNIQUE_ERR = 255; ! 0xFF Vendor Unique Error ! + ! ! A single structure is used to define Service Parameters for each of ! the classes of service, with the understanding that some parameters ! are meaningless for some classes. The following data structure defines ! the format of the Service Parameters. Note that this is not the same ! as the Common Service Parameters structure which is used to define ! values which do apply to a N-Port or F-Port Login regardless of the ! class of service used to perform any particular Exchange. ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 185, figure 62 ! ! Table 101 on page 186 of the same reference is used to determine ! which Service Parameter fields are valid for a particular class ! of service for both N-Port and F-Port Logins. ! ! - literal SPR$M_INI_CTL_RESERVED = %X'3FF'; literal SPR$M_INI_ACK_N_SUPPORTED = %X'400'; literal SPR$M_INI_ACK_0_SUPPORTED = %X'800'; literal SPR$M_INI_RSP_PRC_ASSOC = %X'3000'; literal SPR$M_INI_X_ID_REASGN_REQ = %X'C000'; literal SPR$M_SRV_OPT_RESERVED = %X'7FF'; literal SPR$M_SEQ_DELIVERY = %X'800'; literal SPR$M_STACKED_CON_REQ = %X'3000'; literal SPR$M_INTERMIX_MODE = %X'4000'; literal SPR$M_CLASS_VALID = %X'8000'; literal SPR$M_RECEIVE_DATA_FIELD_SIZE = %X'FFF'; literal SPR$M_RESERVED_FOR_FABRIC = %X'F'; literal SPR$M_RESERVED1 = %X'F0'; literal SPR$M_R_CATEGORIES_PER_SEQUENCE = %X'300'; literal SPR$M_RESERVED2 = %X'400'; literal SPR$M_R_ERROR_POLICIES_SUPPORTED = %X'1800'; literal SPR$M_R_X_ID_INTERLOCK = %X'2000'; literal SPR$M_R_ACK_N_SUPPORTED = %X'4000'; literal SPR$M_R_ACK_0_SUPPORTED = %X'8000'; literal SPR$M_N_PORT_END_TO_END_CREDIT = %X'7FFF'; literal SPR$M_RESERVED3 = %X'8000'; literal SPR$S_SERVICE_PARAMETERS = 16; macro SPR$L_LONGWORD_0_OVERLAY = 0,0,32,1 %; ! ! Initiator Control Flags ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 190, figure 65 ! macro SPR$W_INITIATOR_CONTROL_FLAGS_OVER = 0,0,16,1 %; macro SPR$V_INI_CTL_RESERVED = 0,0,10,0 %; literal SPR$S_INI_CTL_RESERVED = 10; macro SPR$V_INI_ACK_N_SUPPORTED = 0,10,1,0 %; macro SPR$V_INI_ACK_0_SUPPORTED = 0,11,1,0 %; macro SPR$V_INI_RSP_PRC_ASSOC = 0,12,2,0 %; literal SPR$S_INI_RSP_PRC_ASSOC = 2; macro SPR$V_INI_X_ID_REASGN_REQ = 0,14,2,0 %; literal SPR$S_INI_X_ID_REASGN_REQ = 2; ! ! Service Options ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 190, figure 64 ! ! The Class Valid bit is not shown in this figure but is ! described in the section in which the table appears. ! Note that at least in this revision of the standard ! the options defined for N-Port Login (figure 64) are ! the same as those defined for F-Port Login (figure 63) ! macro SPR$W_SERVICE_OPTIONS_OVERLAY = 2,0,16,1 %; macro SPR$V_SRV_OPT_RESERVED = 2,0,11,0 %; literal SPR$S_SRV_OPT_RESERVED = 11; macro SPR$V_SEQ_DELIVERY = 2,11,1,0 %; macro SPR$V_STACKED_CON_REQ = 2,12,2,0 %; literal SPR$S_STACKED_CON_REQ = 2; macro SPR$V_INTERMIX_MODE = 2,14,1,0 %; macro SPR$V_CLASS_VALID = 2,15,1,0 %; macro SPR$L_LONGWORD_1_OVERLAY = 4,0,32,1 %; ! Receive Data Field Size macro SPR$W_RECEIVE_DATA_FIELD_SIZE_OVER = 4,0,16,1 %; macro SPR$V_RECEIVE_DATA_FIELD_SIZE = 4,0,12,0 %; literal SPR$S_RECEIVE_DATA_FIELD_SIZE = 12; ! ! Recipient Control ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 193, figure 66 ! macro SPR$W_RECIPIENT_CONTROL_OVERLAY = 6,0,16,1 %; macro SPR$V_RESERVED_FOR_FABRIC = 6,0,4,0 %; literal SPR$S_RESERVED_FOR_FABRIC = 4; macro SPR$V_RESERVED1 = 6,4,4,0 %; literal SPR$S_RESERVED1 = 4; macro SPR$V_R_CATEGORIES_PER_SEQUENCE = 6,8,2,0 %; literal SPR$S_R_CATEGORIES_PER_SEQUENCE = 2; macro SPR$V_RESERVED2 = 6,10,1,0 %; macro SPR$V_R_ERROR_POLICIES_SUPPORTED = 6,11,2,0 %; literal SPR$S_R_ERROR_POLICIES_SUPPORTED = 2; macro SPR$V_R_X_ID_INTERLOCK = 6,13,1,0 %; macro SPR$V_R_ACK_N_SUPPORTED = 6,14,1,0 %; macro SPR$V_R_ACK_0_SUPPORTED = 6,15,1,0 %; macro SPR$L_LONGWORD_2_OVERLAY = 8,0,32,1 %; macro SPR$V_N_PORT_END_TO_END_CREDIT = 8,0,15,0 %; literal SPR$S_N_PORT_END_TO_END_CREDIT = 15; macro SPR$V_RESERVED3 = 8,15,1,0 %; macro SPR$W_CONCURRENT_SEQUENCES = 10,0,16,1 %; macro SPR$L_LONGWORD_3_OVERLAY = 12,0,32,1 %; macro SPR$W_RESERVED4 = 12,0,16,1 %; macro SPR$B_OPEN_SEQUENCES_PER_EXCHANGE = 14,0,8,1 %; macro SPR$B_RESERVED5 = 15,0,8,1 %; ! + ! ! Common Service Parameters used in N-Port and F-Port Login ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 181, table 98 ! ! NOTE: The Alternate Credit Model bit below is not described in the ! referenced document, it was taken from a booklet which came ! with a Seagate FC disk ! ! - literal CSP$M_BB_RCV_DATA_FLD_SIZE = %X'FFFF'; literal CSP$M_RESERVED1 = %X'3FF0000'; literal CSP$M_E_D_TOV_NS = %X'4000000'; literal CSP$M_ALT_CREDIT_MODEL = %X'8000000'; literal CSP$M_F_PORT_LOGIN = %X'10000000'; literal CSP$M_VENDOR_VERSION = %X'20000000'; literal CSP$M_RANDOM_RELATIVE_OFFSET = %X'40000000'; literal CSP$M_CONTINUOUSLY_INCREASING = %X'80000000'; literal CSP$S_COMMON_SERVICE_PARAMETERS = 16; macro CSP$W_BB_CREDIT = 0,0,16,0 %; macro CSP$B_LOW_FC_PH_REV = 2,0,8,0 %; macro CSP$B_HIGH_FC_PH_REV = 3,0,8,0 %; macro CSP$R_COMMON_FEATURES = 4,0,32,0 %; literal CSP$S_COMMON_FEATURES = 4; macro CSP$V_BB_RCV_DATA_FLD_SIZE = 4,0,16,0 %; literal CSP$S_BB_RCV_DATA_FLD_SIZE = 16; ! Bits 00 to 15 macro CSP$V_RESERVED1 = 4,16,10,0 %; literal CSP$S_RESERVED1 = 10; ! Bits 16 to 25 macro CSP$V_E_D_TOV_NS = 4,26,1,0 %; ! Bit 26 macro CSP$V_ALT_CREDIT_MODEL = 4,27,1,0 %; ! Bit 27 macro CSP$V_F_PORT_LOGIN = 4,28,1,0 %; ! Bit 28 macro CSP$V_VENDOR_VERSION = 4,29,1,0 %; ! Bit 29 macro CSP$V_RANDOM_RELATIVE_OFFSET = 4,30,1,0 %; ! Bit 30 macro CSP$V_CONTINUOUSLY_INCREASING = 4,31,1,0 %; ! Bit 31 macro CSP$R_N_F_PORT_OVERLAY = 8,0,32,0 %; macro CSP$R_F_PORT_FIELDS = 8,0,32,0 %; macro CSP$L_R_A_TOV = 8,0,32,0 %; macro CSP$R_N_PORT_FIELDS = 8,0,32,0 %; macro CSP$W_OFFSET_BY_INFO = 8,0,16,0 %; macro CSP$W_TOTAL_SEQUENCES = 10,0,16,0 %; macro CSP$L_E_D_TOV = 12,0,32,0 %; ! + ! ! Placeholder definition for an IEEE address ! ! - literal IEEE$S_IEEE_ADDRESS_T = 8; macro IEEE$B_ADDRESS = 0,0,0,0 %; literal IEEE$S_ADDRESS = 8; literal IEEE$SZ_LENGTH = 8; ! length of structure ! + ! ! This structure is used to simplify reference to the block of data ! which is passed in several ELS requests. It is not used in the ! ELS request structures themselves because that would complicate ! referencing individual fields in it ! ! - literal PORT_DATA$S_PORT_DATA = 112; macro PORT_DATA$R_COMMON_SPARM = 0,0,0,0 %; literal PORT_DATA$S_COMMON_SPARM = 16; macro PORT_DATA$R_PORT_NAME = 16,0,0,0 %; literal PORT_DATA$S_PORT_NAME = 8; macro PORT_DATA$R_NODE_FABRIC_NAME = 24,0,0,0 %; literal PORT_DATA$S_NODE_FABRIC_NAME = 8; macro PORT_DATA$R_CLASS_1_SPARM = 32,0,0,0 %; literal PORT_DATA$S_CLASS_1_SPARM = 16; macro PORT_DATA$R_CLASS_2_SPARM = 48,0,0,0 %; literal PORT_DATA$S_CLASS_2_SPARM = 16; macro PORT_DATA$R_CLASS_3_SPARM = 64,0,0,0 %; literal PORT_DATA$S_CLASS_3_SPARM = 16; macro PORT_DATA$B_RESERVED2 = 80,0,0,0 %; literal PORT_DATA$S_RESERVED2 = 16; macro PORT_DATA$B_VENDOR_VERSION_LEVEL = 96,0,0,0 %; literal PORT_DATA$S_VENDOR_VERSION_LEVEL = 16; ! ! Network Address Authority identifiers ! literal NAA$K_IGNORED = 0; literal NAA$K_IEEE = 1; literal NAA$K_IEEE_EXTENDED = 2; literal NAA$K_LOCALLY_ASSIGNED = 3; literal NAA$K_IP = 4; literal NAA$K_CCITT_INDIVIDUAL_ADDRESS = 12; literal NAA$K_CCITT_GROUP_ADDRESS = 14; ! + ! ! N Port Login Request ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 148, table 71 ! ! - literal PLOGI_REQ$M_RESERVED1 = %X'FFFFFF'; literal PLOGI_REQ$S_PLOGI_REQ_T = 116; macro PLOGI_REQ$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro PLOGI_REQ$V_RESERVED1 = 0,0,24,0 %; literal PLOGI_REQ$S_RESERVED1 = 24; macro PLOGI_REQ$B_ELS_COMMAND_CODE = 3,0,8,0 %; macro PLOGI_REQ$R_COMMON_SPARM = 4,0,0,0 %; literal PLOGI_REQ$S_COMMON_SPARM = 16; macro PLOGI_REQ$R_PORT_NAME = 20,0,0,0 %; literal PLOGI_REQ$S_PORT_NAME = 8; macro PLOGI_REQ$R_NODE_FABRIC_NAME = 28,0,0,0 %; literal PLOGI_REQ$S_NODE_FABRIC_NAME = 8; macro PLOGI_REQ$R_CLASS_1_SPARM = 36,0,0,0 %; literal PLOGI_REQ$S_CLASS_1_SPARM = 16; macro PLOGI_REQ$R_CLASS_2_SPARM = 52,0,0,0 %; literal PLOGI_REQ$S_CLASS_2_SPARM = 16; macro PLOGI_REQ$R_CLASS_3_SPARM = 68,0,0,0 %; literal PLOGI_REQ$S_CLASS_3_SPARM = 16; macro PLOGI_REQ$B_RESERVED2 = 84,0,0,0 %; literal PLOGI_REQ$S_RESERVED2 = 16; macro PLOGI_REQ$B_VENDOR_VERSION_LEVEL = 100,0,0,0 %; literal PLOGI_REQ$S_VENDOR_VERSION_LEVEL = 16; ! + ! ! N Port Login Response ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 148, table 72 ! ! - literal PLOGI_RSP$M_RESERVED1 = %X'FFFFFF'; literal PLOGI_RSP$S_PLOGI_RSP_T = 116; macro PLOGI_RSP$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro PLOGI_RSP$V_RESERVED1 = 0,0,24,0 %; literal PLOGI_RSP$S_RESERVED1 = 24; macro PLOGI_RSP$B_ELS_COMMAND_CODE = 3,0,8,0 %; macro PLOGI_RSP$R_COMMON_SPARM = 4,0,0,0 %; literal PLOGI_RSP$S_COMMON_SPARM = 16; macro PLOGI_RSP$R_PORT_NAME = 20,0,0,0 %; literal PLOGI_RSP$S_PORT_NAME = 8; macro PLOGI_RSP$R_NODE_FABRIC_NAME = 28,0,0,0 %; literal PLOGI_RSP$S_NODE_FABRIC_NAME = 8; macro PLOGI_RSP$R_CLASS_1_SPARM = 36,0,0,0 %; literal PLOGI_RSP$S_CLASS_1_SPARM = 16; macro PLOGI_RSP$R_CLASS_2_SPARM = 52,0,0,0 %; literal PLOGI_RSP$S_CLASS_2_SPARM = 16; macro PLOGI_RSP$R_CLASS_3_SPARM = 68,0,0,0 %; literal PLOGI_RSP$S_CLASS_3_SPARM = 16; macro PLOGI_RSP$B_RESERVED2 = 84,0,0,0 %; literal PLOGI_RSP$S_RESERVED2 = 16; macro PLOGI_RSP$B_VENDOR_VERSION_LEVEL = 100,0,0,0 %; literal PLOGI_RSP$S_VENDOR_VERSION_LEVEL = 16; ! + ! ! Discover N-Port Parameters Request ! ! Ref: Fibre Channel Physical & Signaling Interface 2 (FC-PH-2) Rev 7.3 ! Working draft of 5-January-1996 ! Section 21.19.1 ! ! - literal PDISC_REQ$M_RESERVED1 = %X'FFFFFF'; literal PDISC_REQ$S_PDISC_REQ_T = 116; macro PDISC_REQ$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro PDISC_REQ$V_RESERVED1 = 0,0,24,0 %; literal PDISC_REQ$S_RESERVED1 = 24; macro PDISC_REQ$B_ELS_COMMAND_CODE = 3,0,8,0 %; macro PDISC_REQ$R_COMMON_SPARM = 4,0,0,0 %; literal PDISC_REQ$S_COMMON_SPARM = 16; macro PDISC_REQ$R_PORT_NAME = 20,0,0,0 %; literal PDISC_REQ$S_PORT_NAME = 8; macro PDISC_REQ$R_NODE_FABRIC_NAME = 28,0,0,0 %; literal PDISC_REQ$S_NODE_FABRIC_NAME = 8; macro PDISC_REQ$R_CLASS_1_SPARM = 36,0,0,0 %; literal PDISC_REQ$S_CLASS_1_SPARM = 16; macro PDISC_REQ$R_CLASS_2_SPARM = 52,0,0,0 %; literal PDISC_REQ$S_CLASS_2_SPARM = 16; macro PDISC_REQ$R_CLASS_3_SPARM = 68,0,0,0 %; literal PDISC_REQ$S_CLASS_3_SPARM = 16; macro PDISC_REQ$B_RESERVED2 = 84,0,0,0 %; literal PDISC_REQ$S_RESERVED2 = 16; macro PDISC_REQ$B_VENDOR_VERSION_LEVEL = 100,0,0,0 %; literal PDISC_REQ$S_VENDOR_VERSION_LEVEL = 16; ! + ! ! Discover N-Port Parameters Response ! ! Ref: Fibre Channel Physical & Signaling Interface 2 (FC-PH-2) Rev 7.3 ! Working draft of 5-January-1996 ! Section 21.19.1 ! ! - literal PDISC_RSP$M_RESERVED1 = %X'FFFFFF'; literal PDISC_RSP$S_PDISC_RSP_T = 116; macro PDISC_RSP$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro PDISC_RSP$V_RESERVED1 = 0,0,24,0 %; literal PDISC_RSP$S_RESERVED1 = 24; macro PDISC_RSP$B_ELS_COMMAND_CODE = 3,0,8,0 %; macro PDISC_RSP$R_COMMON_SPARM = 4,0,0,0 %; literal PDISC_RSP$S_COMMON_SPARM = 16; macro PDISC_RSP$R_PORT_NAME = 20,0,0,0 %; literal PDISC_RSP$S_PORT_NAME = 8; macro PDISC_RSP$R_NODE_FABRIC_NAME = 28,0,0,0 %; literal PDISC_RSP$S_NODE_FABRIC_NAME = 8; macro PDISC_RSP$R_CLASS_1_SPARM = 36,0,0,0 %; literal PDISC_RSP$S_CLASS_1_SPARM = 16; macro PDISC_RSP$R_CLASS_2_SPARM = 52,0,0,0 %; literal PDISC_RSP$S_CLASS_2_SPARM = 16; macro PDISC_RSP$R_CLASS_3_SPARM = 68,0,0,0 %; literal PDISC_RSP$S_CLASS_3_SPARM = 16; macro PDISC_RSP$B_RESERVED2 = 84,0,0,0 %; literal PDISC_RSP$S_RESERVED2 = 16; macro PDISC_RSP$B_VENDOR_VERSION_LEVEL = 100,0,0,0 %; literal PDISC_RSP$S_VENDOR_VERSION_LEVEL = 16; ! + ! ! Abort Exchange Request ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 144, table 62 ! ! - literal ABTX_REQ$M_RESERVED1 = %X'FFFFFF'; literal ABTX_REQ$S_ABTX_REQ_T = 4; macro ABTX_REQ$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro ABTX_REQ$V_RESERVED1 = 0,0,24,0 %; literal ABTX_REQ$S_RESERVED1 = 24; macro ABTX_REQ$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! + ! ! Abort Exchange Response ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 145, table 63 ! ! - literal ABTX_RSP$M_RESERVED1 = %X'FFFFFF'; literal ABTX_RSP$S_ABTX_RSP_T = 4; macro ABTX_RSP$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro ABTX_RSP$V_RESERVED1 = 0,0,24,0 %; literal ABTX_RSP$S_RESERVED1 = 24; macro ABTX_RSP$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! + ! ! Advise Credit Request ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 145, table 64 ! ! - literal ADVC_REQ$M_RESERVED1 = %X'FFFFFF'; literal ADVC_REQ$S_ADVC_REQ_T = 4; macro ADVC_REQ$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro ADVC_REQ$V_RESERVED1 = 0,0,24,0 %; literal ADVC_REQ$S_RESERVED1 = 24; macro ADVC_REQ$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! + ! ! Advise Credit Response ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 146, table 65 ! ! - literal ADVC_RSP$M_RESERVED1 = %X'FFFFFF'; literal ADVC_RSP$S_ADVC_RSP_T = 4; macro ADVC_RSP$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro ADVC_RSP$V_RESERVED1 = 0,0,24,0 %; literal ADVC_RSP$S_RESERVED1 = 24; macro ADVC_RSP$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! + ! ! Logout Request ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 149, table 73 ! ! - literal LOGO_REQ$M_RESERVED1 = %X'FFFFFF'; literal LOGO_REQ$S_LOGO_REQ_T = 16; macro LOGO_REQ$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro LOGO_REQ$V_RESERVED1 = 0,0,24,0 %; literal LOGO_REQ$S_RESERVED1 = 24; macro LOGO_REQ$B_ELS_COMMAND_CODE = 3,0,8,0 %; macro LOGO_REQ$R_N_PORT_ID_STRUCTURE = 4,0,32,0 %; literal LOGO_REQ$S_N_PORT_ID_STRUCTURE = 4; macro LOGO_REQ$V_D_ID = 4,0,24,0 %; literal LOGO_REQ$S_D_ID = 24; macro LOGO_REQ$V_RSVD = 4,24,8,0 %; literal LOGO_REQ$S_RSVD = 8; ! Port Name macro LOGO_REQ$R_PORT_NAME = 8,0,0,0 %; literal LOGO_REQ$S_PORT_NAME = 8; ! + ! ! Logout Response ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 149, table 74 ! ! - literal LOGO_RSP$M_RESERVED1 = %X'FFFFFF'; literal LOGO_RSP$S_LOGO_RSP_T = 4; macro LOGO_RSP$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro LOGO_RSP$V_RESERVED1 = 0,0,24,0 %; literal LOGO_RSP$S_RESERVED1 = 24; macro LOGO_RSP$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! + ! ! Generic ACC ! ! - literal LS_ACC$M_RESERVED1 = %X'FFFFFF'; literal LS_ACC$S_LS_ACC = 4; macro LS_ACC$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro LS_ACC$V_RESERVED1 = 0,0,24,0 %; literal LS_ACC$S_RESERVED1 = 24; macro LS_ACC$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! + ! ! Read Link Error Status Block Request ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 151, table 79 ! ! - literal RLS_REQ$M_RESERVED1 = %X'FFFFFF'; literal RLS_REQ$S_RLS_REQ_T = 4; macro RLS_REQ$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro RLS_REQ$V_RESERVED1 = 0,0,24,0 %; literal RLS_REQ$S_RESERVED1 = 24; macro RLS_REQ$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! + ! ! Read Link Error Status Block Response ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 151, table 80 ! ! - literal RLS_RSP$M_RESERVED1 = %X'FFFFFF'; literal RLS_RSP$S_RLS_RSP_T = 4; macro RLS_RSP$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro RLS_RSP$V_RESERVED1 = 0,0,24,0 %; literal RLS_RSP$S_RESERVED1 = 24; macro RLS_RSP$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! + ! ! An Extended Link Service request or response is built by appending the ! appropriate payload to a longword which contains an Extended Link ! Service code. The structure being defined here can be used to create ! a buffer of a size which will contain any of the Basic or Extended ! Link Service payloads defined above. It can also be used as a ! type-independent pointer to a structure so the command code can be ! interpreted. ! ! - literal ELS$M_RESERVED1 = %X'FFFFFF'; literal ELS$S_ELS_T = 116; macro ELS$R_ELS_COMMAND_CODE_STRUCTURE = 0,0,32,0 %; literal ELS$S_ELS_COMMAND_CODE_STRUCTURE = 4; macro ELS$V_RESERVED1 = 0,0,24,0 %; literal ELS$S_RESERVED1 = 24; macro ELS$B_ELS_COMMAND_CODE = 3,0,8,0 %; macro ELS$R_ELS_COMMAND_UNION = 0,0,0,0 %; literal ELS$S_ELS_COMMAND_UNION = 116; macro ELS$R_PLOGI_REQ_DATA = 0,0,0,0 %; literal ELS$S_PLOGI_REQ_DATA = 116; macro ELS$R_LOGI_RSP_DATA = 0,0,0,0 %; literal ELS$S_LOGI_RSP_DATA = 116; macro ELS$R_ABTX_REQ_DATA = 0,0,32,0 %; literal ELS$S_ABTX_REQ_DATA = 4; macro ELS$R_ABTX_RSP_DATA = 0,0,32,0 %; literal ELS$S_ABTX_RSP_DATA = 4; macro ELS$R_ADVC_REQ_DATA = 0,0,32,0 %; literal ELS$S_ADVC_REQ_DATA = 4; macro ELS$R_ADVC_RSP_DATA = 0,0,32,0 %; literal ELS$S_ADVC_RSP_DATA = 4; macro ELS$R_LOGO_REQ_DATA = 0,0,0,0 %; literal ELS$S_LOGO_REQ_DATA = 16; macro ELS$R_LOGO_RSP_DATA = 0,0,32,0 %; literal ELS$S_LOGO_RSP_DATA = 4; macro ELS$R_RLS_REQ_DATA = 0,0,32,0 %; literal ELS$S_RLS_REQ_DATA = 4; macro ELS$R_RLS_RSP_DATA = 0,0,32,0 %; literal ELS$S_RLS_RSP_DATA = 4; ! + ! ! Maximum Number of Participating NL-Ports on an Arbitrated Loop ! ! Ref: Fibre Channel Arbitrated Loop (FC-AL-2) Rev 6.1 ! Working draft of 16-Feb-1998 ! Page 13, section 5.1.1 ! ! Note that this is a count of NL-Ports, and does not include ! the special AL-PA of 00, which is reserved for the single ! FL-Port which may or may not be present on the Arbitrated ! Loop ! ! - literal FCAL$K_AL_PA_COUNT = 126; ! ! PRLI Request Payload ! ! Ref: Fibre Channel Protocol for SCSI (SCSI-FCP) Rev 12 ! Draft proposal of 4-Dec-1995 ! Table A.3, page 39 ! literal PRLI_REQ$S_PRLI_REQ = 20; macro PRLI_REQ$W_PAYLOAD_LENGTH = 0,0,16,1 %; ! Total length of payload (typically 20.) macro PRLI_REQ$B_PAGE_LENGTH = 2,0,8,1 %; ! Length of each service paramter page macro PRLI_REQ$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! Extended Link service command code macro PRLI_REQ$R_SERVICE_PARAMETER_PAGE = 4,0,0,0 %; literal PRLI_REQ$S_SERVICE_PARAMETER_PAGE = 16; ! Service parameter page ! ! PRLI ACC Payload ! ! Ref: Fibre Channel Protocol for SCSI (SCSI-FCP) Rev 12 ! Draft proposal of 4-Dec-1995 ! Table A.5, page 41 ! literal PRLI_ACC$S_PRLI_ACC = 20; macro PRLI_ACC$W_PAYLOAD_LENGTH = 0,0,16,1 %; ! Total length of payload (typically 20.) macro PRLI_ACC$B_PAGE_LENGTH = 2,0,8,1 %; ! Length of each service paramter page macro PRLI_ACC$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! Extended Link service command code macro PRLI_ACC$R_SERVICE_PARAMETER_PAGE = 4,0,0,0 %; literal PRLI_ACC$S_SERVICE_PARAMETER_PAGE = 16; ! Service parameter page ! ! PRLO Request Payload ! ! Ref: Fibre Channel Protocol for SCSI (SCSI-FCP) Rev 12 ! Draft proposal of 4-Dec-1995 ! Table A.8, page 46 ! literal PRLO_REQ$S_PRLO_REQ = 20; macro PRLO_REQ$W_PAYLOAD_LENGTH = 0,0,16,1 %; ! Total length of payload (typically 20.) macro PRLO_REQ$B_PAGE_LENGTH = 2,0,8,1 %; ! Length of each service paramter page macro PRLO_REQ$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! Extended Link service command code macro PRLO_REQ$R_LOGOUT_PARAMETER_PAGE = 4,0,0,0 %; literal PRLO_REQ$S_LOGOUT_PARAMETER_PAGE = 16; ! Logout parameter page ! ! PRLO ACC Payload ! ! Ref: Fibre Channel Protocol for SCSI (SCSI-FCP) Rev 12 ! Draft proposal of 4-Dec-1995 ! Table A.10, page 48 ! literal PRLO_ACC$S_PRLO_ACC = 20; macro PRLO_ACC$W_PAYLOAD_LENGTH = 0,0,16,1 %; ! Total length of payload (typically 20.) macro PRLO_ACC$B_PAGE_LENGTH = 2,0,8,1 %; ! Length of each service paramter page macro PRLO_ACC$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! Extended Link service command code macro PRLO_ACC$R_SERVICE_PARAMETER_PAGE = 4,0,0,0 %; literal PRLO_ACC$S_SERVICE_PARAMETER_PAGE = 16; ! Service parameter page ! ! Common Transport Information Unit (IU) ! FC-GS-2 R5.1 - Tables 1-3, 6 ! literal CTIU$M_RESERVED2 = %X'7F'; literal CTIU$M_XBIT_EXCHANGE = %X'80'; literal CTIU$K_BIDIRECT = 0; literal CTIU$K_MULTIPLE = 1; literal CTIU$K_ALIAS_SERVER = 248; ! F8: Alias server application literal CTIU$K_RESERVED1 = 249; ! F9: (reserved) literal CTIU$K_MGMT_SERVER = 250; ! FA: Management service application literal CTIU$K_TIME_SERVER = 251; ! FB: Time service application literal CTIU$K_DIRECTORY_SERVER = 252; ! FC: Directory service application literal CTIU$K_FABRIC = 253; ! FD: Fabric controller service appl. ! Longword 2 literal CTIU$K_NON_FC_IU = 0; literal CTIU$K_FS_RJT_IU = 32769; literal CTIU$K_FS_ACC_IU = 32770; ! Longowrd 3 literal CTIU$K_NS_NO_ADDITIONAL_EXPL = 0; ! 00: No additional explanation literal CTIU$K_NS_PORT_ID_NOT_REG = 1; ! 01: Port identifier not registered literal CTIU$K_NS_PORT_NAME_NOT_REG = 2; ! 02: Port name not registered literal CTIU$K_NS_NODE_NAME_NOT_REG = 3; ! 03: Node name not registered literal CTIU$K_NS_CLASS_SRV_NOT_REG = 4; ! 04: Class of service not registered literal CTIU$K_NS_IP_ADDR_NODE_NOT_REG = 5; ! 05: IP address (node) not registered literal CTIU$K_NS_IPA_NOT_REG = 6; ! 06: Initial Process Associator not registered literal CTIU$K_NS_FC4_NOT_REG = 7; ! 07: FC-4 Types not registered literal CTIU$K_NS_SYM_PORT_NAME_NOT_REG = 8; ! 08: Symbolic port name not registered literal CTIU$K_NS_SYM_NODE_NAME_NOT_REG = 9; ! 09: Symbolic node name not registered literal CTIU$K_NS_PORT_TYPE_NOT_REG = 10; ! 0A: Port type not registered literal CTIU$K_NS_IP_ADDR_PORT_NOT_REG = 11; ! 0B: IP address (port) not registered literal CTIU$K_NS_FAB_PORT_NAME_NOT_REG = 12; ! 0C: Fabric port name not registered literal CTIU$K_NS_HARD_ADDR_NOT_REG = 13; ! 0D: Hard address not registered literal CTIU$K_NS_RESERVED1 = 14; ! 0E: (reserved) literal CTIU$K_NS_RESERVED2 = 15; ! 0F: (reserved) literal CTIU$K_NS_ACCESS_DENIED = 16; ! 10: Access denied literal CTIU$K_NS_UNACCEPTABLE_PORT_ID = 17; ! 11: Unacceptable port identifier literal CTIU$K_NS_DATA_BASE_EMPTY = 18; ! 12: Data base empty literal CTIU$K_NS_NO_OBJ_REG_IN_SCOPE = 19; ! 13: No object registered in specified scope literal CTIU$K_INVALID_COMMAND = 1; ! 01: Invalid command code literal CTIU$K_INVALID_VERSION = 2; ! 02: Invalid version level literal CTIU$K_LOGICAL_ERROR = 3; ! 03: Logical error literal CTIU$K_INVALID_IU_SIZE = 4; ! 04: Invalid IU size literal CTIU$K_LOGICAL_BUSY = 5; ! 05: Logical busy literal CTIU$K_RESERVED5 = 6; ! 06: (reserved) literal CTIU$K_PROTOCOL_ERROR = 7; ! 07: Protocol error literal CTIU$K_RESERVED6 = 8; ! 08: (reserved) literal CTIU$K_CANT_DO_IT = 9; ! 09: Unable to perform request literal CTIU$K_RESERVED7 = 10; ! 0A: (reserved) literal CTIU$K_NOT_SUPPORTED = 11; ! 0B: Command not supported literal CTIU$S_CTIU = 16; macro CTIU$R_CT_HDR = 0,0,0,0 %; literal CTIU$S_CT_HDR = 16; ! Longword 0 macro CTIU$B_IN_ID = 0,0,24,1 %; literal CTIU$S_IN_ID = 3; macro CTIU$B_REVISION = 3,0,8,1 %; ! Longword 1 macro CTIU$B_RESERVED = 4,0,8,1 %; macro CTIU$B_OPTIONS = 5,0,8,1 %; macro CTIU$R_FS_SUBTYPE = 6,0,8,0 %; literal CTIU$S_FS_SUBTYPE = 1; macro CTIU$B_FS_SUBTYPE = 6,0,8,1 %; macro CTIU$R_FS_SUBTYPE_BITS = 6,0,8,0 %; macro CTIU$V_RESERVED2 = 6,0,7,0 %; literal CTIU$S_RESERVED2 = 7; macro CTIU$V_XBIT_EXCHANGE = 6,7,1,0 %; macro CTIU$B_FCS_TYPE = 7,0,8,1 %; ! - Service types - macro CTIU$W_MAX_RESID_SIZE = 8,0,16,0 %; macro CTIU$W_COMMAND_RESPONSE = 10,0,16,0 %; ! - Command/Response codes - macro CTIU$B_VENDOR_UNIQUE = 12,0,8,1 %; macro CTIU$B_RJT_EXPLANATION = 13,0,8,1 %; ! Reject explanation constants added with revision X-6 ! FS_RJT name server reason code explanations macro CTIU$B_RJT_REASON = 14,0,8,1 %; ! - FS_RJT reason codes - macro CTIU$B_RESERVED4 = 15,0,8,1 %; ! ! Directory Service Subtypes ! FC-GS-2 R5.1, Table 7 ! literal DIR$K_RESERVED1 = 1; literal DIR$K_NAME_SERVICE = 2; ! ! Name Server Request Command Codes ! FC-GS-2 R5.1, Table 10 ! literal NSREQ$K_GA_NXT = 256; ! Get all next literal NSREQ$K_GPN_ID = 274; ! Get port name literal NSREQ$K_GNN_ID = 275; ! Get node name using port ID literal NSREQ$K_GCS_ID = 276; ! Get class of service literal NSREQ$K_GFT_ID = 279; ! Get FC-4 TYPEs literal NSREQ$K_GSPN_ID = 280; ! Get symbolic port name literal NSREQ$K_GPT_ID = 282; ! Get port type literal NSREQ$K_GID_PN = 289; ! Get port ID using port name literal NSREQ$K_GID_NN = 305; ! Get port ID using node name literal NSREQ$K_GIP_NN = 309; ! Get IP address literal NSREQ$K_GIPA_NN = 310; ! Get proc. associator using node name literal NSREQ$K_GSNN_NN = 313; ! Get symbolic node name literal NSREQ$K_GNN_IP = 339; ! Get node name using IP address literal NSREQ$K_GIPA_IP = 342; ! Get proc. associator using IP address literal NSREQ$K_GID_FT = 369; ! Get port IDs using FC-4 TYPE literal NSREQ$K_GID_PT = 417; ! Get port IDs using port type literal NSREQ$K_RPN_ID = 530; ! Register port name literal NSREQ$K_RNN_ID = 531; ! Register node name literal NSREQ$K_RCS_ID = 532; ! Register class of service literal NSREQ$K_RFT_ID = 535; ! Register FC-4 TYPEs literal NSREQ$K_RSPN_ID = 536; ! Register symbolic port name literal NSREQ$K_RPT_ID = 538; ! Register port type literal NSREQ$K_RIP_NN = 565; ! Register IP address literal NSREQ$K_RIPA_NN = 566; ! Register proc. associator literal NSREQ$K_RSNN_NN = 569; ! Register symbolic node name literal NSREQ$K_DA_ID = 768; ! Deregister all ! ! GID_PN (Get port identifier for specified port) Request Payload ! FC-GS-2 R5.1 - Table 28 ! literal GID_PN_REQ$S_GID_PN_REQ = 8; macro GID_PN_REQ$B_PORT_NAME = 0,0,0,1 %; literal GID_PN_REQ$S_PORT_NAME = 8; ! ! GID_PN (Get port identifier for specified port) Reply ! FC-GS-2 R5.1 - Table 29 ! literal GID_PN_ACC$S_GID_PN_ACC = 4; macro GID_PN_ACC$L_PORT_IDENT = 0,0,32,0 %; ! X-9a macro GID_PN_ACC$R_RSVD0 = 0,0,32,0 %; literal GID_PN_ACC$S_RSVD0 = 4; macro GID_PN_ACC$B_RESERVED1 = 0,0,8,1 %; macro GID_PN_ACC$B_PORT_IDENT = 1,0,24,1 %; literal GID_PN_ACC$S_PORT_IDENT = 3; ! ! GID_NN (Get port identifiers for specified node) Request Payload ! FC-GS-2 R5.1 - Table 30 ! literal GID_NN_REQ$S_GID_NN_REQ = 8; macro GID_NN_REQ$B_NODE_NAME = 0,0,0,1 %; literal GID_NN_REQ$S_NODE_NAME = 8; ! ! GID_NN (Get port identifiers for specified node) Reply ! FC-GS-2 R5.1 - Table 31 ! literal GID_NN_ACC$M_RESERVED = %X'7F00'; literal GID_NN_ACC$M_LAST_IDENT = %X'8000'; literal GID_NN_ACC$S_GID_NN_ACC = 8; macro GID_NN_ACC$B_CONTROL = 0,0,8,1 %; macro GID_NN_ACC$V_RESERVED = 0,8,7,0 %; literal GID_NN_ACC$S_RESERVED = 7; macro GID_NN_ACC$V_LAST_IDENT = 0,15,1,0 %; macro GID_NN_ACC$B_PORT_IDENT = 2,0,24,1 %; literal GID_NN_ACC$S_PORT_IDENT = 3; ! ! GID_FT (Get port identifiers for specified FC-4 type) Request Payload ! FC-GS-2 R5.1 - Table 42 ! literal GID_FT_REQ$S_GID_FT_REQ = 4; macro GID_FT_REQ$B_FC4_TYPE = 0,0,8,0 %; macro GID_FT_REQ$B_AREA = 1,0,8,0 %; ! X-9b macro GID_FT_REQ$B_DOMAIN = 2,0,8,0 %; ! X-9b macro GID_FT_REQ$B_RESERVED = 3,0,8,0 %; ! ! GID_FT (Get port identifiers for specified FC-4 type) Reply ! FC-GS-2 R5.1 - Table 43 ! literal GID_FT_ACC$M_RESERVED = %X'7F'; literal GID_FT_ACC$M_LAST_IDENT = %X'80'; literal GID_FT_ACC$S_GID_FT_ACC = 4; macro GID_FT_ACC$B_PORT_IDENT = 0,0,24,1 %; literal GID_FT_ACC$S_PORT_IDENT = 3; macro GID_FT_ACC$R_CONTROL_STRUCTURE = 3,0,8,0 %; literal GID_FT_ACC$S_CONTROL_STRUCTURE = 1; macro GID_FT_ACC$V_RESERVED = 3,0,7,0 %; literal GID_FT_ACC$S_RESERVED = 7; macro GID_FT_ACC$V_LAST_IDENT = 3,7,1,0 %; ! ! GID_PT (Get Port Identifiers) Request Payload ! FC-GS-2 R5.1 - Table 44 ! literal GID_PT_REQ$S_GID_PT_REQ = 4; macro GID_PT_REQ$B_RESERVED = 0,0,8,1 %; macro GID_PT_REQ$B_AREA_ID_SCOPE = 1,0,8,1 %; ! X-6 macro GID_PT_REQ$B_DOMAIN_ID_SCOPE = 2,0,8,1 %; ! X-6 macro GID_PT_REQ$B_PORT_TYPE = 3,0,8,1 %; ! ! GID_PT (Get Port Identifiers) Reply ! FC-GS-2 R5.1 - Table 45 ! literal GID_PT_ACC$M_PORT_IDENT = %X'FFFFFF'; literal GID_PT_ACC$M_RESERVED = %X'7F'; literal GID_PT_ACC$M_LAST_IDENT = %X'80'; literal GID_PT_ACC$S_GID_PT_ACC = 4; macro GID_PT_ACC$R_PORT_STRUCTURE = 0,0,32,0 %; literal GID_PT_ACC$S_PORT_STRUCTURE = 4; macro GID_PT_ACC$V_PORT_IDENT = 0,0,24,0 %; literal GID_PT_ACC$S_PORT_IDENT = 24; macro GID_PT_ACC$R_CONTROL_STRUCTURE = 3,0,8,0 %; literal GID_PT_ACC$S_CONTROL_STRUCTURE = 1; macro GID_PT_ACC$V_RESERVED = 3,0,7,0 %; literal GID_PT_ACC$S_RESERVED = 7; macro GID_PT_ACC$V_LAST_IDENT = 3,7,1,0 %; ! ! GPN_ID - Get Port Name by (Port) ID request ! FC-GS-4 5.2.5.4 Table 34 ! literal GPN_ID_REQ$M_PORT_ID = %X'FFFFFF'; literal GPN_ID_REQ$S_GPN_ID_REQ = 4; macro GPN_ID_REQ$V_PORT_ID = 0,0,24,0 %; literal GPN_ID_REQ$S_PORT_ID = 24; ! ! GPN_ID - Get Port Name by (Port) ID response ! FC-GS-4 5.2.5.4 Table 35 ! literal GPN_ID_ACC$S_GPN_ID_ACC = 8; macro GPN_ID_ACC$B_PORT_NAME = 0,0,0,0 %; literal GPN_ID_ACC$S_PORT_NAME = 8; literal NS_GID_PT$K_PT_UNIDENTIFIED = 0; literal NS_GID_PT$K_PT_N_PORT = 1; literal NS_GID_PT$K_PT_NL_PORT = 2; literal NS_GID_PT$K_PT_F_NL_PORT = 3; literal NS_GID_PT$K_PT_NX_PORT = 127; literal NS_GID_PT$K_PT_F_PORT = 129; literal NS_GID_PT$K_PT_FL_PORT = 130; literal NS_GID_PT$K_PT_E_PORT = 132; ! ! Well-known addresses for Fibre Channel Services ! FC-FLA R2.7 - Table 28 ! literal WLKN_ADR$K_SYNCH_SERVER = 16777206; literal WLKN_ADR$K_SECURITY_SERVER = 16777207; literal WLKN_ADR$K_ALIAS_SERVER = 16777208; literal WLKN_ADR$K_QOS_FACIL = 16777209; literal WLKN_ADR$K_MGMT_SERVER = 16777210; literal WLKN_ADR$K_TIME_SERVER = 16777211; literal WLKN_ADR$K_DIRECTORY_SERVER = 16777212; literal WLKN_ADR$K_FABRIC_CTRLR = 16777213; literal WLKN_ADR$K_FABRIC_FPORT = 16777214; literal WLKN_ADR$K_BROADCAST = 16777215; ! ! RSCN (Registered State Change Notification) Payload ! FC-FLA R2.7 - Tables A.14-A.19 ! literal RSCN_REQ$K_PORT_ADDRESS = 0; literal RSCN_REQ$K_AREA_ADDRESS_GROUP = 1; literal RSCN_REQ$K_DOMAIN_ADDRESS_GROUP = 2; literal RSCN_REQ$K_FABRIC_ADDRESS_GROUP = 3; ! X-6 literal RSCN_REQ$M_ADDRESS = %X'FFFFFF'; literal RSCN_REQ$M_ADDRESS_FORMAT_BITS = %X'3'; literal RSCN_REQ$M_EVENT_QUALIFIER_BITS = %X'3C'; literal RSCN_REQ$M_RESERVED_BITS = %X'C0'; literal RSCN_REQ$S_RSCN_REQ = 8; ! Longword 0 macro RSCN_REQ$W_PAYLOAD_LENGTH = 0,0,16,1 %; macro RSCN_REQ$B_PAGE_LENGTH = 2,0,8,1 %; macro RSCN_REQ$B_ELS_COMMAND_CODE = 3,0,8,1 %; ! Longword 1 macro RSCN_REQ$R_AFFECTED_PAGE = 4,0,32,0 %; literal RSCN_REQ$S_AFFECTED_PAGE = 4; macro RSCN_REQ$R_ADDRESS_UNION = 4,0,24,0 %; literal RSCN_REQ$S_ADDRESS_UNION = 3; macro RSCN_REQ$V_ADDRESS = 4,0,24,0 %; literal RSCN_REQ$S_ADDRESS = 24; macro RSCN_REQ$R_ADDRESS_STRUCTURE = 4,0,24,0 %; literal RSCN_REQ$S_ADDRESS_STRUCTURE = 3; macro RSCN_REQ$B_PORT = 4,0,8,1 %; macro RSCN_REQ$B_AREA = 5,0,8,1 %; macro RSCN_REQ$B_DOMAIN = 6,0,8,1 %; macro RSCN_REQ$R_ADDR_FMT_UNION = 7,0,8,0 %; literal RSCN_REQ$S_ADDR_FMT_UNION = 1; ! X-14 macro RSCN_REQ$R_ADDR_FMT_STRUCTURE = 7,0,8,0 %; literal RSCN_REQ$S_ADDR_FMT_STRUCTURE = 1; ! X-14 macro RSCN_REQ$V_ADDRESS_FORMAT_BITS = 7,0,2,0 %; macro RSCN_REQ$V_EVENT_QUALIFIER_BITS = 7,2,4,0 %; macro RSCN_REQ$V_RESERVED_BITS = 7,6,2,0 %; macro RSCN_REQ$B_ADDRESS_FORMAT = 7,0,8,1 %; ! ! RSCN (Registered State Change Notification) Accept Reply ! FC-FLA R2.7 - Table A.20 ! literal RSCN_ACC$M_RESERVED1 = %X'FFFFFF'; literal RSCN_ACC$S_RSCN_ACC = 4; macro RSCN_ACC$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro RSCN_ACC$V_RESERVED1 = 0,0,24,0 %; literal RSCN_ACC$S_RESERVED1 = 24; macro RSCN_ACC$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! ! Affected N_Port ID Page - Port Address Format ! literal IDPAGE$K_PORT_ADDRESS = 0; literal PORTPG$S_PORTPG = 4; macro PORTPG$B_FORMAT = 0,0,8,1 %; macro PORTPG$B_PORT_ID = 1,0,24,1 %; literal PORTPG$S_PORT_ID = 3; ! ! Affected N_Port ID Page - Area Address Format ! literal IDPAGE$K_AREA_ADDRESS = 1; literal AREAPG$S_AREAPG = 4; macro AREAPG$B_FORMAT = 0,0,8,1 %; macro AREAPG$B_PORT_DOMAIN = 1,0,8,1 %; macro AREAPG$B_PORT_AREA = 2,0,8,1 %; macro AREAPG$B_RESERVED1 = 3,0,8,1 %; ! ! Affected N_Port ID Page - Domain Address Format ! literal IDPAGE$K_DOMN_ADDRESS = 2; literal DOMNPG$S_DOMNPG = 4; macro DOMNPG$B_FORMAT = 0,0,8,1 %; macro DOMNPG$B_PORT_DOMAIN = 1,0,8,1 %; macro DOMNPG$W_RESERVED1 = 2,0,16,1 %; ! ! FAN (Fabric Address Notification) Payload ! FC-FLA R2.7 - Table A.1 ! literal FAN$M_RESERVED1 = %X'FFFFFF'; literal FAN$S_FAN = 24; macro FAN$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro FAN$V_RESERVED1 = 0,0,24,0 %; literal FAN$S_RESERVED1 = 24; macro FAN$B_ELS_COMMAND_CODE = 3,0,8,0 %; macro FAN$B_RESERVED1 = 4,0,8,1 %; macro FAN$B_FABRIC_ADRS = 5,0,24,1 %; literal FAN$S_FABRIC_ADRS = 3; macro FAN$B_PORT_NAME = 8,0,0,1 %; literal FAN$S_PORT_NAME = 8; macro FAN$B_FABRIC_NAME = 16,0,0,1 %; literal FAN$S_FABRIC_NAME = 8; ! ! SCR (State Change Request) Payload ! FC-FLA R2.7 - Tables A.21, A.22 ! literal SCR_REQ$M_RESERVED1 = %X'FFFFFF'; literal SCR_RF$K_RESERVED = 0; literal SCR_RF$K_FABRIC = 1; literal SCR_RF$K_N_PORT = 2; literal SCR_RF$K_FULL = 3; literal SCR_RF$K_CLEAR_REG = 255; literal SCR_REQ$S_SCR_REQ = 8; macro SCR_REQ$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro SCR_REQ$V_RESERVED1 = 0,0,24,0 %; literal SCR_REQ$S_RESERVED1 = 24; macro SCR_REQ$B_ELS_COMMAND_CODE = 3,0,8,0 %; macro SCR_REQ$B_REG_FUNCTION = 4,0,8,1 %; macro SCR_REQ$B_RESERVED2 = 5,0,24,1 %; literal SCR_REQ$S_RESERVED2 = 3; ! ! SCR (State Change Request) Accept Reply ! FC-FLA R2.7 - Table A.23 ! literal SCR_ACC$M_RESERVED1 = %X'FFFFFF'; literal SCR_ACC$S_SCR_ACC = 4; macro SCR_ACC$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro SCR_ACC$V_RESERVED1 = 0,0,24,0 %; literal SCR_ACC$S_RESERVED1 = 24; macro SCR_ACC$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! ! ELP (Exchange Link Parameters) Payload ! FC-SW R3.3 - Table 6 ! literal ELP$M_RESERVED1 = %X'FFFFFF'; literal ELP$S_ELP = 4; macro ELP$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro ELP$V_RESERVED1 = 0,0,24,0 %; literal ELP$S_RESERVED1 = 24; macro ELP$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! + ! ! Fabric Login Request ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 148, table 71 ! ! - literal FLOGI_REQ$M_RESERVED1 = %X'FFFFFF'; literal FLOGI_REQ$S_FLOGI_REQ_T = 116; macro FLOGI_REQ$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro FLOGI_REQ$V_RESERVED1 = 0,0,24,0 %; literal FLOGI_REQ$S_RESERVED1 = 24; macro FLOGI_REQ$B_ELS_COMMAND_CODE = 3,0,8,0 %; macro FLOGI_REQ$R_COMMON_SPARM = 4,0,0,0 %; literal FLOGI_REQ$S_COMMON_SPARM = 16; macro FLOGI_REQ$R_PORT_NAME = 20,0,0,0 %; literal FLOGI_REQ$S_PORT_NAME = 8; macro FLOGI_REQ$R_NODE_FABRIC_NAME = 28,0,0,0 %; literal FLOGI_REQ$S_NODE_FABRIC_NAME = 8; macro FLOGI_REQ$R_CLASS_1_SPARM = 36,0,0,0 %; literal FLOGI_REQ$S_CLASS_1_SPARM = 16; macro FLOGI_REQ$R_CLASS_2_SPARM = 52,0,0,0 %; literal FLOGI_REQ$S_CLASS_2_SPARM = 16; macro FLOGI_REQ$R_CLASS_3_SPARM = 68,0,0,0 %; literal FLOGI_REQ$S_CLASS_3_SPARM = 16; macro FLOGI_REQ$B_RESERVED2 = 84,0,0,0 %; literal FLOGI_REQ$S_RESERVED2 = 16; macro FLOGI_REQ$B_VENDOR_VERSION_LEVEL = 100,0,0,0 %; literal FLOGI_REQ$S_VENDOR_VERSION_LEVEL = 16; ! + ! ! Fabric Login Response ! ! Ref: Fibre Channel Physical & Signaling Interface (FC-PH) Rev 4.3 ! Working draft of 5-January-1996 ! Page 148, table 72 ! ! - literal FLOGI_RSP$M_RESERVED1 = %X'FFFFFF'; literal FLOGI_RSP$S_FLOGI_RSP_T = 116; macro FLOGI_RSP$R_ELS_COMMAND_UNION = 0,0,32,0 %; literal FLOGI_RSP$S_ELS_COMMAND_UNION = 4; macro FLOGI_RSP$L_ELS_COMMAND_LONGWORD = 0,0,32,1 %; macro FLOGI_RSP$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro FLOGI_RSP$V_RESERVED1 = 0,0,24,0 %; literal FLOGI_RSP$S_RESERVED1 = 24; macro FLOGI_RSP$B_ELS_COMMAND_CODE = 3,0,8,0 %; macro FLOGI_RSP$R_COMMON_SPARM = 4,0,0,0 %; literal FLOGI_RSP$S_COMMON_SPARM = 16; macro FLOGI_RSP$R_PORT_NAME = 20,0,0,0 %; literal FLOGI_RSP$S_PORT_NAME = 8; macro FLOGI_RSP$R_NODE_FABRIC_NAME = 28,0,0,0 %; literal FLOGI_RSP$S_NODE_FABRIC_NAME = 8; macro FLOGI_RSP$R_CLASS_1_SPARM = 36,0,0,0 %; literal FLOGI_RSP$S_CLASS_1_SPARM = 16; macro FLOGI_RSP$R_CLASS_2_SPARM = 52,0,0,0 %; literal FLOGI_RSP$S_CLASS_2_SPARM = 16; macro FLOGI_RSP$R_CLASS_3_SPARM = 68,0,0,0 %; literal FLOGI_RSP$S_CLASS_3_SPARM = 16; macro FLOGI_RSP$B_RESERVED2 = 84,0,0,0 %; literal FLOGI_RSP$S_RESERVED2 = 16; macro FLOGI_RSP$B_VENDOR_VERSION_LEVEL = 100,0,0,0 %; literal FLOGI_RSP$S_VENDOR_VERSION_LEVEL = 16; ! + ! ! Discover F-Port Parameters Request ! ! Ref: Fibre Channel Physical & Signaling Interface 2 (FC-PH-2) Rev 7.3 ! Working draft of 5-January-1996 ! Section 21.19.1 ! ! - literal FDISC_REQ$M_RESERVED1 = %X'FFFFFF'; literal FDISC_REQ$S_FDISC_REQ_T = 116; macro FDISC_REQ$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro FDISC_REQ$V_RESERVED1 = 0,0,24,0 %; literal FDISC_REQ$S_RESERVED1 = 24; macro FDISC_REQ$B_ELS_COMMAND_CODE = 3,0,8,0 %; macro FDISC_REQ$R_COMMON_SPARM = 4,0,0,0 %; literal FDISC_REQ$S_COMMON_SPARM = 16; macro FDISC_REQ$R_PORT_NAME = 20,0,0,0 %; literal FDISC_REQ$S_PORT_NAME = 8; macro FDISC_REQ$R_NODE_FABRIC_NAME = 28,0,0,0 %; literal FDISC_REQ$S_NODE_FABRIC_NAME = 8; macro FDISC_REQ$R_CLASS_1_SPARM = 36,0,0,0 %; literal FDISC_REQ$S_CLASS_1_SPARM = 16; macro FDISC_REQ$R_CLASS_2_SPARM = 52,0,0,0 %; literal FDISC_REQ$S_CLASS_2_SPARM = 16; macro FDISC_REQ$R_CLASS_3_SPARM = 68,0,0,0 %; literal FDISC_REQ$S_CLASS_3_SPARM = 16; macro FDISC_REQ$B_RESERVED2 = 84,0,0,0 %; literal FDISC_REQ$S_RESERVED2 = 16; macro FDISC_REQ$B_VENDOR_VERSION_LEVEL = 100,0,0,0 %; literal FDISC_REQ$S_VENDOR_VERSION_LEVEL = 16; ! + ! ! Discover F-Port Parameters Response ! ! Ref: Fibre Channel Physical & Signaling Interface 2 (FC-PH-2) Rev 7.3 ! Working draft of 5-January-1996 ! Section 21.19.1 ! ! - literal FDISC_RSP$M_RESERVED1 = %X'FFFFFF'; literal FDISC_RSP$S_FDISC_RSP_T = 116; macro FDISC_RSP$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro FDISC_RSP$V_RESERVED1 = 0,0,24,0 %; literal FDISC_RSP$S_RESERVED1 = 24; macro FDISC_RSP$B_ELS_COMMAND_CODE = 3,0,8,0 %; macro FDISC_RSP$R_COMMON_SPARM = 4,0,0,0 %; literal FDISC_RSP$S_COMMON_SPARM = 16; macro FDISC_RSP$R_PORT_NAME = 20,0,0,0 %; literal FDISC_RSP$S_PORT_NAME = 8; macro FDISC_RSP$R_NODE_FABRIC_NAME = 28,0,0,0 %; literal FDISC_RSP$S_NODE_FABRIC_NAME = 8; macro FDISC_RSP$R_CLASS_1_SPARM = 36,0,0,0 %; literal FDISC_RSP$S_CLASS_1_SPARM = 16; macro FDISC_RSP$R_CLASS_2_SPARM = 52,0,0,0 %; literal FDISC_RSP$S_CLASS_2_SPARM = 16; macro FDISC_RSP$R_CLASS_3_SPARM = 68,0,0,0 %; literal FDISC_RSP$S_CLASS_3_SPARM = 16; macro FDISC_RSP$B_RESERVED2 = 84,0,0,0 %; literal FDISC_RSP$S_RESERVED2 = 16; macro FDISC_RSP$B_VENDOR_VERSION_LEVEL = 100,0,0,0 %; literal FDISC_RSP$S_VENDOR_VERSION_LEVEL = 16; ! ! ADISC (Discover Address) Payload ! FC-PH-2 R7.4 - Table 147 ! literal ADISC_REQ$M_RESERVED1 = %X'FFFFFF'; literal ADISC_REQ$S_ADISC_REQ = 20; macro ADISC_REQ$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro ADISC_REQ$V_RESERVED1 = 0,0,24,0 %; literal ADISC_REQ$S_RESERVED1 = 24; macro ADISC_REQ$B_ELS_COMMAND_CODE = 3,0,8,0 %; macro ADISC_REQ$B_RESERVED1 = 4,0,8,1 %; macro ADISC_REQ$B_ORIG_ADRS = 5,0,24,1 %; literal ADISC_REQ$S_ORIG_ADRS = 3; macro ADISC_REQ$L_ORIG_PORT = 8,0,32,1 %; macro ADISC_REQ$L_ORIG_NODE = 12,0,32,1 %; macro ADISC_REQ$B_RESERVED2 = 16,0,8,1 %; macro ADISC_REQ$B_ORIG_PORT_ID = 17,0,24,1 %; literal ADISC_REQ$S_ORIG_PORT_ID = 3; ! ! ADISC (Discover Address) Reply ! FC-PH-2 R7.4 - Table 148 ! literal ADISC_ACC$M_RESERVED1 = %X'FFFFFF'; literal ADISC_ACC$S_ADISC_ACC = 20; macro ADISC_ACC$R_ELS_COMMAND_OVERLAY = 0,0,32,0 %; macro ADISC_ACC$V_RESERVED1 = 0,0,24,0 %; literal ADISC_ACC$S_RESERVED1 = 24; macro ADISC_ACC$B_ELS_COMMAND_CODE = 3,0,8,0 %; macro ADISC_ACC$B_RESERVED1 = 4,0,8,1 %; macro ADISC_ACC$B_RESP_ADRS = 5,0,24,1 %; literal ADISC_ACC$S_RESP_ADRS = 3; macro ADISC_ACC$L_RESP_PORT = 8,0,32,1 %; macro ADISC_ACC$L_RESP_NODE = 12,0,32,1 %; macro ADISC_ACC$B_RESERVED2 = 16,0,8,1 %; macro ADISC_ACC$B_RESP_PORT_ID = 17,0,24,1 %; literal ADISC_ACC$S_RESP_PORT_ID = 3; ! ! RSPN_ID (Register Symbolic Port Name) Request Payload ! FC-GS-2 ANSI NCITS 288-1999 - Table 68 ! ! Note: This command has no command-specific objects in ! its accept payload. ! ! Added with revision X-6 ! literal RSPN_ID_REQ$M_PORT_IDENT = %X'FFFFFF'; literal RSPN_ID_REQ$S_RSPN_ID_REQ = 260; macro RSPN_ID_REQ$V_PORT_IDENT = 0,0,24,0 %; literal RSPN_ID_REQ$S_PORT_IDENT = 24; macro RSPN_ID_REQ$B_STRING_LENGTH = 4,0,8,1 %; macro RSPN_ID_REQ$B_PORT_NAME = 5,0,0,1 %; literal RSPN_ID_REQ$S_PORT_NAME = 255; ! ! FC4_ENTRY (List of FC4 entries returned by RNFT) ! Ref: Fibre Channel Framing and Signaling (FC-FS) REV 1.90 ! Draft proposal of 09-APR-2003 ! Table 194, page 303 ! literal FC4_ENTRY$S_FC4_ENTRY_T = 4; macro FC4_ENTRY$B_QUALIFIER = 0,0,24,1 %; literal FC4_ENTRY$S_QUALIFIER = 3; macro FC4_ENTRY$B_TYPE = 3,0,8,1 %; ! ! RNFT Request Payload ! ! Ref: Fibre Channel Framing and Signaling (FC-FS) REV 1.90 ! Draft proposal of 09-APR-2003 ! Table 192, page 302 ! literal RNFT_REQ$S_RNFT_REQ = 8; macro RNFT_REQ$W_PAYLOAD_LENGTH = 0,0,16,1 %; ! Total length of payload (typically 20.) macro RNFT_REQ$b_reserved = 2,0,8,0 %; ! Unused macro RNFT_REQ$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! Extended Link service command code macro RNFT_REQ$B_INDEX = 4,0,8,0 %; ! First FC-4 Entry to be returned ! ! RNFT ACC Payload ! ! Ref: Fibre Channel Framing and Signaling (FC-FS) REV 1.90 ! Draft proposal of 09-APR-2003 ! Table 193, page 303 ! literal RNFT_ACC$S_RNFT_ACC = 1024; macro RNFT_ACC$W_PAYLOAD_LENGTH = 0,0,16,1 %; ! Total length of payload (typically 20.) macro RNFT_ACC$B_RESERVED = 2,0,8,0 %; ! reserved macro RNFT_ACC$B_ELS_COMMAND_CODE = 3,0,8,0 %; ! Extended Link service command code macro RNFT_ACC$R_FC4_ENTRY = 4,0,0,0 %; literal RNFT_ACC$S_FC4_ENTRY = 1020; ! List of FC4 protocols ! + ! X-7 Define topology constants ! - ! Tell whether a switch is present (1) or not (0) literal FC$M_TOPOLOGY_FABRIC = 1; ! Tell whether the topology is Arbitrated Loop (1) or not (0) literal FC$M_TOPOLOGY_FC_AL = 2; ! There are 2 bits in the topology mask literal FC$V_TOPOLOGY = 0; literal FC$S_TOPOLOGY = 2; literal FC$M_TOPOLOGY = 3; ! Each topology gets it's own constant based on the bits defined above literal FC$C_TOPOLOGY_P2P = 0; literal FC$C_TOPOLOGY_FABRIC = 1; literal FC$C_TOPOLOGY_PRIVATE_LOOP = 2; literal FC$C_TOPOLOGY_PUBLIC_LOOP = 3; ! ! RFT_ID (Register FC-4 Types) Request Payload ! FC-GS-4 Rev 7.6 19-Dec-02 - Table 98 ! ! 1) Start with a zero'd 8-LW (32-byte) map ! 2) Each legal FC-4 type value fits into 8 bits: ! LW = high 3 bits (0 to 7) of FC-4 type value ! bit# = low 5 bits (0 to 31) of FC-4 type value ! 3) Using C notation, for each supported FC-4 type: ! map [LW] |= (1 << bit#) ! ! See Table 25 for a formal description of the FC-4 Types map format ! !*** MODULE $FCP_QIODEF IDENT X-5 *** ! IO$ACCESS command codes for FibreChannel drivers ! Maximum number of filter parameters allowed ! (maximum value of the counts defined below) ! Make SDL-local constant public literal FC$K_EV_FLTR_MAXIMUM_CNT = 32; ! Maximum number of FCP status filter bytes literal FC$K_EV_FLTR_FCP_STAT_CNT = 8; ! Maximum number of extended status filter bytes literal FC$K_EV_FLTR_ESTAT_CNT = 8; ! Maximum number of SCSI command filter bytes literal FC$K_EV_FLTR_SCSI_COMM_CNT = 8; ! Maximum number of ASC filter bytes literal FC$K_EV_FLTR_ASC_CNT = 8; ! Maximum number of WWID filter bytes literal FC$K_EV_FLTR_WWID_CNT = 32; ! ! QIO Function Codes ! literal FC$C_QIO_QFULL = 0; literal FC$C_QIO_FC_LA_DATA = 1; literal FC$C_QIO_FLTR_WRITE = 2; literal FC$C_QIO_FLTR_READ = 3; literal FC$C_QIO_FCP_RING_SIZE = 4; literal FC$C_QIO_SET_WTID = 5; literal FC$C_QIO_IC = 6; literal FC$C_QIO_RING_SIZE = 7; literal FC$C_QIO_FASTPATH_RING_SIZE = 8; literal FC$C_QIO_SLOW_RING_SIZE = 9; literal FC$C_QIO_ERROR_RING_SIZE = 10; literal FC$C_QIO_INTERRUPTS_RING_SIZE = 11; literal FC$C_QIO_MBX_RING_SIZE = 12; literal FC$C_QIO_IOCB_RING_SIZE = 13; literal FC$C_QIO_PM_CLEAR = 14; literal FC$C_QIO_PM_READ_ALL = 15; literal FC$C_QIO_PM_RSCC = 16; literal FC$C_QIO_PM_SYSTIME = 17; literal FC$C_QIO_SET_ERL_ENTRY = 18; literal FC$C_QIO_PM_READ_COUNTERS = 19; literal FC$C_QIO_SNIA_REQUEST = 20; literal FC$C_QIO_NS_GID_PT = 21; ! Get Port IDs using the port type literal FC$C_QIO_NS_GPN_ID = 22; ! Get Port Name literal FC$C_QIO_NS_GSPN_ID = 23; ! Get Symbolic Port Name literal FC$C_QIO_PM_ALLOC = 24; ! X-8a Allocate performance data literal FC$C_QIO_PM_DEALLOC = 26; ! X-8a Deallocate performance data literal FC$C_QIO_GET_WWIDS = 27; ! X-9a Select WWIDs by wildcard literal FC$C_QIO_GET_WTID = 28; ! X-9a Read a WWID_TID structure literal FC$C_QIO_SET_WTIDS = 29; ! X-9a Modify selected WWID_TID characteristics literal FC$C_QIO_SUB_FLTR_SCSI_COMM = 0; literal FC$C_QIO_SUB_FLTR_FCP_STATUS = 1; literal FC$C_QIO_SUB_FLTR_ESTATUS = 2; literal FC$C_QIO_SUB_FLTR_ASC = 3; literal FC$C_QIO_SUB_FLTR_WWID = 4; literal FC$C_QIO_SUB_FLTR_MATCH = 5; literal QFULL$S_QFULL = 48; macro QFULL$Q_COMMAND_CODE = 0,0,0,1 %; literal QFULL$S_COMMAND_CODE = 8; ! FC$C_QFULL macro QFULL$Q_QW_COUNT = 8,0,0,1 %; literal QFULL$S_QW_COUNT = 8; ! QW parameters (not counting this one) macro QFULL$Q_FC_LA = 16,0,0,1 %; literal QFULL$S_FC_LA = 8; ! FibreChannel Logical Address macro QFULL$Q_STEP_DIVISOR = 24,0,0,1 %; literal QFULL$S_STEP_DIVISOR = 8; ! Step size based on Queue Full depth macro QFULL$Q_DRAIN_MULTIPLIER = 32,0,0,1 %; literal QFULL$S_DRAIN_MULTIPLIER = 8; ! Drain count based on step size macro QFULL$Q_PROBATION_FACTOR = 40,0,0,1 %; literal QFULL$S_PROBATION_FACTOR = 8; ! Probation period based on Queue Full depth literal FC_LA_DATA$S_FC_LA_DATA = 56; macro FC_LA_DATA$Q_COMMAND_CODE = 0,0,0,1 %; literal FC_LA_DATA$S_COMMAND_CODE = 8; ! FC$C_FC_LA_DATA macro FC_LA_DATA$Q_QW_COUNT = 8,0,0,1 %; literal FC_LA_DATA$S_QW_COUNT = 8; ! QW parameters (not counting this one) macro FC_LA_DATA$Q_FC_LA = 16,0,0,1 %; literal FC_LA_DATA$S_FC_LA = 8; ! FibreChannel Logical Address macro FC_LA_DATA$Q_FC_ADDRESS = 24,0,0,1 %; literal FC_LA_DATA$S_FC_ADDRESS = 8; ! Current FibreChannel address macro FC_LA_DATA$Q_PORT_NAME = 32,0,0,1 %; literal FC_LA_DATA$S_PORT_NAME = 8; ! FC-LA's port name macro FC_LA_DATA$Q_NODE_NAME = 40,0,0,1 %; literal FC_LA_DATA$S_NODE_NAME = 8; ! FC-LA's node name macro FC_LA_DATA$Q_STATE = 48,0,0,1 %; literal FC_LA_DATA$S_STATE = 8; ! FC-LA's state as ELS code literal FC$C_NO_APPEND = 0; literal FC$C_APPEND = 1; literal FC$C_OR = 0; literal FC$C_AND = 1; literal FC$C_NOR = 2; literal FC$C_NO_CHANGE = 3; literal FILTER_DATA_WRITE$S_FILTER_DATA_WRITE = 296; macro FILTER_DATA_WRITE$Q_COMMAND_CODE = 0,0,0,1 %; literal FILTER_DATA_WRITE$S_COMMAND_CODE = 8; ! FC$C_QIO_FLTR_WRITE macro FILTER_DATA_WRITE$Q_QW_COUNT = 8,0,0,1 %; literal FILTER_DATA_WRITE$S_QW_COUNT = 8; ! QW parameters (not counting this one) macro FILTER_DATA_WRITE$Q_SUB_COMMAND = 16,0,0,1 %; literal FILTER_DATA_WRITE$S_SUB_COMMAND = 8; ! Sub-command FC$C_QIO_SUB_FLTR_* macro FILTER_DATA_WRITE$Q_APPEND = 24,0,0,1 %; literal FILTER_DATA_WRITE$S_APPEND = 8; ! Append flag (0=no, 1=yes) macro FILTER_DATA_WRITE$Q_MATCH = 32,0,0,1 %; literal FILTER_DATA_WRITE$S_MATCH = 8; ! Match flag (0=or, 1=and, 2=no change) macro FILTER_DATA_WRITE$Q_DATA = 40,0,0,1 %; literal FILTER_DATA_WRITE$S_DATA = 256; ! Data for specified filter function literal FILTER_DATA_READ$S_FILTER_DATA_READ = 24; macro FILTER_DATA_READ$Q_COMMAND_CODE = 0,0,0,1 %; literal FILTER_DATA_READ$S_COMMAND_CODE = 8; ! FC$C_QIO_FLTR_READ macro FILTER_DATA_READ$Q_QW_COUNT = 8,0,0,1 %; literal FILTER_DATA_READ$S_QW_COUNT = 8; ! QW parameters (not counting this one) macro FILTER_DATA_READ$Q_SUB_COMMAND = 16,0,0,1 %; literal FILTER_DATA_READ$S_SUB_COMMAND = 8; ! Sub-command FC$C_QIO_SUB_FLTR_* literal FILTER_DATA_RSP$S_FILTER_DATA_RSP = 264; macro FILTER_DATA_RSP$Q_QW_COUNT = 0,0,0,1 %; literal FILTER_DATA_RSP$S_QW_COUNT = 8; ! QW parameters (not counting this one) macro FILTER_DATA_RSP$Q_DATA = 8,0,0,1 %; literal FILTER_DATA_RSP$S_DATA = 256; ! Data for specified filter function literal FLTR_IOSB$M_ALREADY_EXISTS = %X'1'; literal FLTR_IOSB$M_TOO_MANY_VALUES = %X'2'; literal FLTR_IOSB$S_FLTR_IOSB = 8; macro FLTR_IOSB$W_STATUS = 0,0,16,0 %; ! Error word macro FLTR_IOSB$W_ERROR_WORD = 6,0,16,0 %; macro FLTR_IOSB$V_ALREADY_EXISTS = 6,0,1,0 %; macro FLTR_IOSB$V_TOO_MANY_VALUES = 6,1,1,0 %; literal RING_SIZE_DATA$S_RING_SIZE_DATA = 24; macro RING_SIZE_DATA$Q_COMMAND_CODE = 0,0,0,1 %; literal RING_SIZE_DATA$S_COMMAND_CODE = 8; ! FC$C_QIO_RING_SIZE macro RING_SIZE_DATA$Q_QW_COUNT = 8,0,0,1 %; literal RING_SIZE_DATA$S_QW_COUNT = 8; ! QW parameters (not counting this one) macro RING_SIZE_DATA$Q_RING_SIZE = 16,0,0,1 %; literal RING_SIZE_DATA$S_RING_SIZE = 8; ! Number of ring entries requested literal IC$S_IC = 40; macro IC$Q_COMMAND_CODE = 0,0,0,1 %; literal IC$S_COMMAND_CODE = 8; ! FC$C_QIO_IC macro IC$Q_QW_COUNT = 8,0,0,1 %; literal IC$S_QW_COUNT = 8; ! QW parameters (not counting this one) macro IC$Q_RSP_INT = 16,0,0,1 %; literal IC$S_RSP_INT = 8; macro IC$Q_DELAY_MS = 24,0,0,1 %; literal IC$S_DELAY_MS = 8; macro IC$Q_RSP_CNT = 32,0,0,1 %; literal IC$S_RSP_CNT = 8; literal FC$C_MAX_QFULL_WAIT = 1; ! Minimum allowed user-specified IO cap literal FC$C_USER_IO_CAP_MIN = 8; ! Minimum allowed user-specified IO cap literal FC$C_USER_IO_CAP_MAX = 65535; ! Queue Full processing types literal FC$C_QFULL_LOAD = 0; literal FC$C_QFULL_TIMED = 1; ! Default Queue Full delay time (for Timed processing) literal FC$C_QFULL_TIMED_DELAY_DEF = 500; ! Minimum Queue Full delay time (for Timed processing) literal FC$C_QFULL_TIMED_DELAY_MIN = 1; ! Maximum Queue Full delay time (for Timed processing) literal FC$C_QFULL_TIMED_DELAY_MAX = 6000; literal SET_WTID$S_SET_WTID = 56; macro SET_WTID$Q_COMMAND_CODE = 0,0,0,1 %; literal SET_WTID$S_COMMAND_CODE = 8; ! FC$C_QIO_SET_WTID macro SET_WTID$Q_BYTE_COUNT = 8,0,0,1 %; literal SET_WTID$S_BYTE_COUNT = 8; ! Number of bytes following this quadword macro SET_WTID$Q_IO_CAP = 16,0,0,1 %; literal SET_WTID$S_IO_CAP = 8; ! IO cap value macro SET_WTID$Q_QFULL_WAIT = 24,0,0,1 %; literal SET_WTID$S_QFULL_WAIT = 8; ! Initiate cap after queue full seen macro SET_WTID$Q_QFULL_TYPE = 32,0,0,1 %; literal SET_WTID$S_QFULL_TYPE = 8; ! Queue-full processing type macro SET_WTID$Q_QFULL_TIME = 40,0,0,1 %; literal SET_WTID$S_QFULL_TIME = 8; ! Queue-full delay time (for time-based processing) macro SET_WTID$Q_WWID = 48,0,0,1 %; literal SET_WTID$S_WWID = 8; ! WWID literal SET_ERL_ENTRY$S_SET_ERL_ENTRY = 24; macro SET_ERL_ENTRY$Q_COMMAND_CODE = 0,0,0,1 %; literal SET_ERL_ENTRY$S_COMMAND_CODE = 8; ! FC$C_SET_ERL_ENTRY macro SET_ERL_ENTRY$Q_QW_COUNT = 8,0,0,1 %; literal SET_ERL_ENTRY$S_QW_COUNT = 8; ! QW parameters (not counting this one) macro SET_ERL_ENTRY$Q_ENTRY_COUNT = 16,0,0,0 %; literal SET_ERL_ENTRY$S_ENTRY_COUNT = 8; ! Number of error log entries requested literal PM_QIO$S_PM_QIO = 24; macro PM_QIO$Q_COMMAND_CODE = 0,0,0,1 %; literal PM_QIO$S_COMMAND_CODE = 8; ! FC$C_PM_* commands macro PM_QIO$Q_DEVICE_CLASS = 8,0,0,1 %; literal PM_QIO$S_DEVICE_CLASS = 8; ! X-7 DC$_TAPE, DC$_DISK, etc. macro PM_QIO$Q_DEVICE_ID = 16,0,0,1 %; literal PM_QIO$S_DEVICE_ID = 8; ! X-7 Unit number, or 0 for all devices literal PM_COUNTERS$S_PM_COUNTERS = 32; macro PM_COUNTERS$Q_READ_TIME_ACC = 0,0,0,0 %; literal PM_COUNTERS$S_READ_TIME_ACC = 8; ! Accumulated read time macro PM_COUNTERS$Q_WRITE_TIME_ACC = 8,0,0,0 %; literal PM_COUNTERS$S_WRITE_TIME_ACC = 8; ! Accumulated write time macro PM_COUNTERS$L_READS = 16,0,32,0 %; ! Number of reads macro PM_COUNTERS$L_WRITES = 20,0,32,0 %; ! Number of writes macro PM_COUNTERS$L_BLOCKS_READ = 24,0,32,0 %; ! Accumulated number of blocks read macro PM_COUNTERS$L_BLOCKS_WRITTEN = 28,0,32,0 %; ! Accumulated number of blocks written ! Nameserver Support literal NS_QIO$S_NS_QIO = 16; macro NS_QIO$Q_COMMAND_CODE = 0,0,0,1 %; literal NS_QIO$S_COMMAND_CODE = 8; ! FC$C_NS_* commands macro NS_QIO$Q_PORT = 8,0,0,1 %; literal NS_QIO$S_PORT = 8; ! Port ID ! SNIA support literal FC$C_QIO_SUB_SNIA_ADP_ATTR = 0; literal FC$C_QIO_SUB_SNIA_PORT_ATTR = 1; literal FC$C_QIO_SUB_SNIA_PORTSTAT = 2; literal FC$C_QIO_SUB_SNIA_DISCPORTATTR = 3; literal FC$C_QIO_SUB_SNIA_RNIDMGMT = 4; literal FC$C_QIO_SUB_SNIA_DISCWWPNATTR = 5; literal FC$C_QIO_SUB_SNIA_FCPSTAT = 6; ! Put this header on a specific SNIA structure literal SNIA_RQ_HDR$S_SNIA_REQUEST_HEADER = 40; macro SNIA_RQ_HDR$Q_COMMAND_CODE = 0,0,0,1 %; literal SNIA_RQ_HDR$S_COMMAND_CODE = 8; ! FGE$C_QIO_SNIA_REQUEST macro SNIA_RQ_HDR$Q_QW_COUNT = 8,0,0,1 %; literal SNIA_RQ_HDR$S_QW_COUNT = 8; ! QW parameters (not counting this one) macro SNIA_RQ_HDR$Q_SUB_COMMAND = 16,0,0,1 %; literal SNIA_RQ_HDR$S_SUB_COMMAND = 8; ! Specific SNIA command macro SNIA_RQ_HDR$Q_PORT_ID = 24,0,0,1 %; literal SNIA_RQ_HDR$S_PORT_ID = 8; ! Specific PORT identifier WWID or index macro SNIA_RQ_HDR$Q_DATA = 32,0,0,1 %; literal SNIA_RQ_HDR$S_DATA = 8; ! Parameter for command literal SNIA$K_MAX_CDB_SIZE = 12; literal SNIA_PATH$S_PATH_CDB = 32; macro SNIA_PATH$Q_LUN = 0,0,0,1 %; literal SNIA_PATH$S_LUN = 8; ! LUN macro SNIA_PATH$IS_TARGET = 8,0,32,1 %; ! Target FC_LA macro SNIA_PATH$L_LENGTH = 12,0,32,0 %; ! True length of CDB. macro SNIA_PATH$B_CDB = 16,0,0,0 %; literal SNIA_PATH$S_CDB = 12; ! CDB bytes ! X-10 !*** MODULE $FDTDEF *** ! + ! FDT - FUNCTION DECISION TABLE FOR STEP 2 I/O DEVICE DRIVERS ! ! EACH I/O DEVICE DRIVER HAS A FUNCTION DECISION TABLE. ! - literal FDT$S_FDT = 272; macro FDT$Q_BUFFERED = 0,0,0,1 %; literal FDT$S_BUFFERED = 8; ! 64 bit map set for buffered I/O function codes macro FDT$PS_FUNC_RTN = 8,0,0,1 %; literal FDT$S_FUNC_RTN = 256; ! Pointers to upper level FDT routines macro FDT$Q_OK64BIT = 264,0,0,1 %; literal FDT$S_OK64BIT = 8; ! Corresponding bit set if function supports 64-bit $QIO P1 literal FDT$K_LENGTH = 272; ! Length constant !*** MODULE $FDT_CONTEXTDEF *** ! + ! FDT_CONTEXT - FUNCTION DECISION TABLE CONTEXT STRUCTURE FOR STEP 2 I/O ! DEVICE DRIVERS ! ! EACH $QIO INVOCATION HAS A FUNCTION DECISION TABLE CONTEXT STRUCTURE ! THAT IS ALLOCATED ON THE STACK. ! - literal FDT_CONTEXT$S_FDT_CONTEXT = 16; macro FDT_CONTEXT$Q_QIO_R1_VALUE = 0,0,0,1 %; literal FDT_CONTEXT$S_QIO_R1_VALUE = 8; ! VA of faulting page if SS$QIO_CROCK set macro FDT_CONTEXT$W_SIZE = 8,0,16,0 %; ! FDT_CONTEXT$K_LENGTH macro FDT_CONTEXT$B_TYPE = 10,0,8,0 %; ! DYN$C_MISC macro FDT_CONTEXT$B_SUBTYPE = 11,0,8,0 %; ! DYN$C_FDT_CONTEXT macro FDT_CONTEXT$L_QIO_STATUS = 12,0,32,0 %; ! Final $QIO system service status ! Pad size to quadword multiple so ! EXE$QIO stack is QW aligned. This ! structure is the first to be ! allocated on the $QIO stack. literal FDT_CONTEXT$K_LENGTH = 16; !*** MODULE $FIXDEF *** ! ! DEFINE FIXUP RECORD ! literal FIX$K_FIXLST = 8; ! OFFSET OF FIXUP LIST literal FIX$S_FIXREC = 8; macro FIX$L_COUNT = 0,0,32,0 %; ! NUMBER OF FIXUPS macro FIX$L_SHLX = 4,0,32,0 %; ! SHAREABLE IMAGE LIST INDEX !*** MODULE $FKBDEF *** ! + ! FKB - FORK BLOCK ! ! A FORK BLOCK DESCRIBES THE CONTEXT OF A FORK PROCESS. EACH UNIT CONTROL ! BLOCK CONTAINS A FORK BLOCK AS ITS FIRST SIX LONGWORDS. ! - literal FKB$S_FKB = 48; macro FKB$L_FQFL = 0,0,32,1 %; ! FORK QUEUE FORWARD LINK macro FKB$L_FQBL = 4,0,32,1 %; ! FORK QUEUE BACKWARD LINK macro FKB$W_SIZE = 8,0,16,0 %; ! SIZE OF FKB IN BYTES macro FKB$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE OF FKB macro FKB$B_FLCK = 11,0,8,0 %; ! FORK LOCK NUMBER macro FKB$L_FPC = 12,0,32,1 %; ! FORK PC macro FKB$Q_FR3 = 16,0,0,1 %; literal FKB$S_FR3 = 8; ! FORK R3 macro FKB$Q_FR4 = 24,0,0,1 %; literal FKB$S_FR4 = 8; ! FORK R4 macro FKB$L_SPINLOCK = 32,0,32,1 %; ! Spinlock address (only used if FLCK is SPL$_DYNAMIC) literal FKB$K_LENGTH = 48; ! STANDARD LENGTH OF FKB literal FKB$C_LENGTH = 48; ! STANDARD LENGTH OF FKB literal FKB$S_FKBDEF = 48; ! Old size name, synonym for FKB$S_FKB !*** MODULE $FPDEF *** ! ! Define the I/O Fastpath Function codes ! literal FP$K_BALANCE_PORTS = 1; literal FP$K_CPU_CONFIGURED = 2; literal FP$K_CPU_STARTING = 3; literal FP$K_CPU_STOPPING = 4; literal FP$K_CPU_STOP_FAILED = 5; ! ! Define flags for call to exe$fp_select_hwint() ! literal HWINT$M_CPU_SELECTED = %X'1'; literal HWINT$M_CPU_NOT_IN_RAD = %X'2'; literal HWINT$M_PRIMARY = %X'4'; literal HWINT$S_HWINT_FLAGS = 8; macro HWINT$L_FLAGS = 0,0,32,0 %; macro HWINT$V_CPU_SELECTED = 0,0,1,0 %; macro HWINT$V_CPU_NOT_IN_RAD = 0,1,1,0 %; macro HWINT$V_PRIMARY = 0,2,1,0 %; ! ! This structure maintains parameters required for each RAD (Resource ! Affinity Domain). The FP struct maintains a pointer to an array of ! this structure and the number of these structures in the array. ! An array of this structure will be allocated at FP init time ! for the number of RADs in the system. The minimum number of RADs ! in any system is 1. ! literal FPRAD$S_FPRAD = 16; macro FPRAD$L_CURRENT_FP_CPU = 0,0,32,1 %; macro FPRAD$L_CURRENT_HWINT_CPU = 4,0,32,1 %; macro FPRAD$L_RADMASK = 8,0,32,1 %; ! ! FP - I/O Fastpath block ! literal FP$M_SPL_HOLD = %X'1'; literal FP$K_LENGTH = 96; ! Length of FP_BLK literal FP$C_LENGTH = 96; ! Length of FP_BLK literal FP$S_FP = 96; macro FP$L_DLCK = 0,0,32,1 %; ! pointer to spinlock macro FP$L_DIPL = 4,0,32,1 %; ! device ipl macro FP$W_MBO = 8,0,16,0 %; ! must-be-one field macro FP$B_TYPE = 10,0,8,0 %; ! structure type macro FP$B_SUBTYPE = 11,0,8,0 %; ! structure sub-type macro FP$L_FLAGS = 12,0,32,0 %; macro FP$V_SPL_HOLD = 12,0,1,0 %; ! set if already holding FP SPinLock macro FP$Q_SIZE = 16,0,0,0 %; literal FP$S_SIZE = 8; ! structure size ! pointer to mask of available CPUs macro FP$Q_USEABLE_CPUS = 24,0,0,1 %; literal FP$S_USEABLE_CPUS = 8; ! Pointer to mask which tries as much as possible to favor ! the CPUs in the RAD in which the IO port lives. macro FP$Q_FAVORED_CPUS = 32,0,0,1 %; literal FP$S_FAVORED_CPUS = 8; ! cells to support assignable ports: macro FP$L_PORTS_LINK = 40,0,32,1 %; ! link to SUD macro FP$L_NUM_PORTS = 44,0,32,1 %; ! total number of assignable ports macro FP$L_NUM_USER_PORTS = 48,0,32,1 %; ! total number of user-assigned ports ! cells to support distributed hardware interrupts: macro FP$L_HWINT_PORTS_LINK = 52,0,32,1 %; ! link to SUD ! Total number of distributed hardware interrupt ports. macro FP$L_NUM_HWINT_PORTS = 56,0,32,1 %; ! Total number of distributed hardware interrupt ports with ! user-assigned interrupt CPU targets. macro FP$L_NUM_USER_HWINT_PORTS = 60,0,32,1 %; ! Last hardware interrupt CPU assigned, absolute number, not a mask. macro FP$L_LAST_HWINT_CPU_ASSIGNED = 64,0,32,1 %; ! Pointer to array of FPRAD structures for RAD housekeeping macro FP$PS_FPRAD = 68,0,32,1 %; ! The number of RADs in this system, which determines the size of the ! array of FPRAD structures. The minimum is 1. macro FP$L_RAD_COUNT = 72,0,32,1 %; ! Unique Identifier of FP spinlock owner. This field is used to prevent ! any routine other than the spinlock owner from clearing the lock. macro FP$L_SPL_OWNER = 76,0,32,1 %; ! Contingency/debug cells: macro FP$L_SPARE1 = 80,0,32,1 %; macro FP$L_SPARE2 = 84,0,32,1 %; macro FP$L_SPARE3 = 88,0,32,1 %; macro FP$L_SPARE4 = 92,0,32,1 %; !*** MODULE $FP_STATEDEF *** ! ++ ! Floating Point State ! -- literal FP_STATE$S_FP_STATE = 48; macro FP_STATE$Q_BITMASK_LOW64 = 0,0,0,0 %; literal FP_STATE$S_BITMASK_LOW64 = 8; ! Bitmask of low 64 FP registers saved macro FP_STATE$Q_BITMASK_HIGH64 = 8,0,0,0 %; literal FP_STATE$S_BITMASK_HIGH64 = 8; ! Bitmask of high 64 FP registers saved macro FP_STATE$PQ_LOW_PRESERVED = 16,0,0,1 %; literal FP_STATE$S_LOW_PRESERVED = 8; macro FP_STATE$PQ_LOW_VOLATILE = 24,0,0,1 %; literal FP_STATE$S_LOW_VOLATILE = 8; macro FP_STATE$PQ_HIGH_PRESERVED = 32,0,0,1 %; literal FP_STATE$S_HIGH_PRESERVED = 8; macro FP_STATE$PQ_HIGH_VOLATILE = 40,0,0,1 %; literal FP_STATE$S_HIGH_VOLATILE = 8; ! ++ ! 128 bit integer type ! -- literal INT128$S_INT128 = 16; macro INT128$Q_LOW_QUAD = 0,0,0,0 %; literal INT128$S_LOW_QUAD = 8; macro INT128$Q_HIGH_QUAD = 8,0,0,0 %; literal INT128$S_HIGH_QUAD = 8; ! ++ ! Floating Point State - low preserved registers ! -- literal FP_STATE$S_FP_STATE_LOW_PRESERVED = 64; macro FP_STATE$R_LP = 0,0,0,0 %; literal FP_STATE$S_LP = 64; ! FP registers F2-F5 ! ++ ! Floating Point State - low volatile registers ! -- literal FP_STATE$S_FP_STATE_LOW_VOLATILE = 160; macro FP_STATE$R_LV = 0,0,0,0 %; literal FP_STATE$S_LV = 160; ! FP registers F6-F15 ! ++ ! Floating Point State - high preserved registers ! -- literal FP_STATE$S_FP_STATE_HIGH_PRESERVED = 256; macro FP_STATE$R_HP = 0,0,0,0 %; literal FP_STATE$S_HP = 256; ! FP registers F16-F31 ! ++ ! Floating Point State - high volatile registers ! -- literal FP_STATE$S_FP_STATE_HIGH_VOLATILE = 1536; macro FP_STATE$R_HV = 0,0,0,0 %; literal FP_STATE$S_HV = 1536; ! FP registers F32 - F127 !*** MODULE $FMDEF *** literal FM$M_SOF = %X'7F'; literal FM$M_SOL = %X'3F80'; literal FM$M_SOR = %X'3C000'; literal FM$M_RRBFR = %X'FE000000'; literal FM$M_RRBPR = %X'3F00000000'; literal FM$S_FM = 8; ! ! Previous Function State Register ! *************************************** macro FM$IQ_FRAME_MARKER = 0,0,0,0 %; literal FM$S_FRAME_MARKER = 8; macro FM$V_SOF = 0,0,7,0 %; literal FM$S_SOF = 7; ! Size of frame macro FM$V_SOL = 0,7,7,0 %; literal FM$S_SOL = 7; ! Size of locals macro FM$V_SOR = 0,14,4,0 %; literal FM$S_SOR = 4; ! Size of rotating (# regs = SOR * 8) macro FM$V_RRBGR = 0,18,7,0 %; literal FM$S_RRBGR = 7; ! Register rename base for general regs macro FM$V_RRBFR = 0,25,7,0 %; literal FM$S_RRBFR = 7; ! Register Rename Base for FP regs macro FM$V_RRBPR = 4,0,6,0 %; literal FM$S_RRBPR = 6; ! Register Rename Base for predicate regs !*** MODULE $FPSRDEF *** ! ! Floating Point Status Field ! ! This structure defines the contents of the SF0, SF1, SF2, SF3 fields in the FPSR below ! *************************************** literal FPSF$M_FTZ = %X'1'; literal FPSF$M_WRE = %X'2'; literal FPSF$M_PC = %X'C'; literal FPSF$M_RC = %X'30'; literal FPSF$M_TD = %X'40'; literal FPSF$M_V = %X'80'; literal FPSF$M_D = %X'100'; literal FPSF$M_Z = %X'200'; literal FPSF$M_O = %X'400'; literal FPSF$M_U = %X'800'; literal FPSF$M_I = %X'1000'; literal FPSF$S_FPSF = 8; ! Control fields macro FPSF$V_FTZ = 0,0,1,0 %; macro FPSF$V_WRE = 0,1,1,0 %; macro FPSF$V_PC = 0,2,2,0 %; literal FPSF$S_PC = 2; macro FPSF$V_RC = 0,4,2,0 %; literal FPSF$S_RC = 2; macro FPSF$V_TD = 0,6,1,0 %; ! Flags fields macro FPSF$V_V = 0,7,1,0 %; macro FPSF$V_D = 0,8,1,0 %; macro FPSF$V_Z = 0,9,1,0 %; macro FPSF$V_O = 0,10,1,0 %; macro FPSF$V_U = 0,11,1,0 %; macro FPSF$V_I = 0,12,1,0 %; literal FPSR$M_VD = %X'1'; literal FPSR$M_DD = %X'2'; literal FPSR$M_ZD = %X'4'; literal FPSR$M_OD = %X'8'; literal FPSR$M_UD = %X'10'; literal FPSR$M_ID = %X'20'; literal FPSR$M_TRAPS = %X'3F'; literal FPSR$M_SF0 = %X'7FFC0'; literal FPSR$M_SF1 = %X'FFF80000'; literal FPSR$M_SF2 = %X'1FFF00000000'; literal FPSR$M_SF3 = %X'3FFE00000000000'; literal FPSR$M_TRAPS_0_6 = %X'3F'; literal FPSR$M_SF0_FTZ = %X'40'; literal FPSR$M_SF0_WRE = %X'80'; literal FPSR$M_SF0_PC = %X'300'; literal FPSR$M_SF0_RC = %X'C00'; literal FPSR$M_SF0_TD = %X'1000'; literal FPSR$M_SF0_V = %X'2000'; literal FPSR$M_SF0_D = %X'4000'; literal FPSR$M_SF0_Z = %X'8000'; literal FPSR$M_SF0_O = %X'10000'; literal FPSR$M_SF0_U = %X'20000'; literal FPSR$M_SF0_I = %X'40000'; literal FPSR$M_SF1_FTZ = %X'80000'; literal FPSR$M_SF1_WRE = %X'100000'; literal FPSR$M_SF1_PC = %X'600000'; literal FPSR$M_SF1_RC = %X'1800000'; literal FPSR$M_SF1_TD = %X'2000000'; literal FPSR$M_SF1_V = %X'4000000'; literal FPSR$M_SF1_D = %X'8000000'; literal FPSR$M_SF1_Z = %X'10000000'; literal FPSR$M_SF1_O = %X'20000000'; literal FPSR$M_SF1_U = %X'40000000'; literal FPSR$M_SF1_I = %X'80000000'; literal FPSR$M_SF2_FTZ = %X'100000000'; literal FPSR$M_SF2_WRE = %X'200000000'; literal FPSR$M_SF2_PC = %X'C00000000'; literal FPSR$M_SF2_RC = %X'3000000000'; literal FPSR$M_SF2_TD = %X'4000000000'; literal FPSR$M_SF2_V = %X'8000000000'; literal FPSR$M_SF2_D = %X'10000000000'; literal FPSR$M_SF2_Z = %X'20000000000'; literal FPSR$M_SF2_O = %X'40000000000'; literal FPSR$M_SF2_U = %X'80000000000'; literal FPSR$M_SF2_I = %X'100000000000'; literal FPSR$M_SF3_FTZ = %X'200000000000'; literal FPSR$M_SF3_WRE = %X'400000000000'; literal FPSR$M_SF3_PC = %X'1800000000000'; literal FPSR$M_SF3_RC = %X'6000000000000'; literal FPSR$M_SF3_TD = %X'8000000000000'; literal FPSR$M_SF3_V = %X'10000000000000'; literal FPSR$M_SF3_D = %X'20000000000000'; literal FPSR$M_SF3_Z = %X'40000000000000'; literal FPSR$M_SF3_O = %X'80000000000000'; literal FPSR$M_SF3_U = %X'100000000000000'; literal FPSR$M_SF3_I = %X'200000000000000'; literal FPSR$S_FPSR = 8; ! ! Floating Point Control and Status Register ! *************************************** macro FPSR$IQ_FLOAT_STATUS = 0,0,0,0 %; literal FPSR$S_FLOAT_STATUS = 8; macro FPSR$V_VD = 0,0,1,0 %; macro FPSR$V_DD = 0,1,1,0 %; macro FPSR$V_ZD = 0,2,1,0 %; macro FPSR$V_OD = 0,3,1,0 %; macro FPSR$V_UD = 0,4,1,0 %; macro FPSR$V_ID = 0,5,1,0 %; macro FPSR$V_TRAPS = 0,0,6,0 %; literal FPSR$S_TRAPS = 6; macro FPSR$V_SF0 = 0,6,13,0 %; literal FPSR$S_SF0 = 13; macro FPSR$V_SF1 = 0,19,13,0 %; literal FPSR$S_SF1 = 13; macro FPSR$V_SF2 = 4,0,13,0 %; literal FPSR$S_SF2 = 13; macro FPSR$V_SF3 = 4,13,13,0 %; literal FPSR$S_SF3 = 13; macro FPSR$V_RV2 = 4,26,6,0 %; literal FPSR$S_RV2 = 6; ! Reserved field above SF3. (Do not change location or name. Used by SWIS_EXCEPTION) macro FPSR$V_TRAPS_0_6 = 0,0,6,0 %; literal FPSR$S_TRAPS_0_6 = 6; macro FPSR$V_SF0_FTZ = 0,6,1,0 %; macro FPSR$V_SF0_WRE = 0,7,1,0 %; macro FPSR$V_SF0_PC = 0,8,2,0 %; literal FPSR$S_SF0_PC = 2; macro FPSR$V_SF0_RC = 0,10,2,0 %; literal FPSR$S_SF0_RC = 2; macro FPSR$V_SF0_TD = 0,12,1,0 %; macro FPSR$V_SF0_V = 0,13,1,0 %; macro FPSR$V_SF0_D = 0,14,1,0 %; macro FPSR$V_SF0_Z = 0,15,1,0 %; macro FPSR$V_SF0_O = 0,16,1,0 %; macro FPSR$V_SF0_U = 0,17,1,0 %; macro FPSR$V_SF0_I = 0,18,1,0 %; macro FPSR$V_SF1_FTZ = 0,19,1,0 %; macro FPSR$V_SF1_WRE = 0,20,1,0 %; macro FPSR$V_SF1_PC = 0,21,2,0 %; literal FPSR$S_SF1_PC = 2; macro FPSR$V_SF1_RC = 0,23,2,0 %; literal FPSR$S_SF1_RC = 2; macro FPSR$V_SF1_TD = 0,25,1,0 %; macro FPSR$V_SF1_V = 0,26,1,0 %; macro FPSR$V_SF1_D = 0,27,1,0 %; macro FPSR$V_SF1_Z = 0,28,1,0 %; macro FPSR$V_SF1_O = 0,29,1,0 %; macro FPSR$V_SF1_U = 0,30,1,0 %; macro FPSR$V_SF1_I = 0,31,1,0 %; macro FPSR$V_SF2_FTZ = 4,0,1,0 %; macro FPSR$V_SF2_WRE = 4,1,1,0 %; macro FPSR$V_SF2_PC = 4,2,2,0 %; literal FPSR$S_SF2_PC = 2; macro FPSR$V_SF2_RC = 4,4,2,0 %; literal FPSR$S_SF2_RC = 2; macro FPSR$V_SF2_TD = 4,6,1,0 %; macro FPSR$V_SF2_V = 4,7,1,0 %; macro FPSR$V_SF2_D = 4,8,1,0 %; macro FPSR$V_SF2_Z = 4,9,1,0 %; macro FPSR$V_SF2_O = 4,10,1,0 %; macro FPSR$V_SF2_U = 4,11,1,0 %; macro FPSR$V_SF2_I = 4,12,1,0 %; macro FPSR$V_SF3_FTZ = 4,13,1,0 %; macro FPSR$V_SF3_WRE = 4,14,1,0 %; macro FPSR$V_SF3_PC = 4,15,2,0 %; literal FPSR$S_SF3_PC = 2; macro FPSR$V_SF3_RC = 4,17,2,0 %; literal FPSR$S_SF3_RC = 2; macro FPSR$V_SF3_TD = 4,19,1,0 %; macro FPSR$V_SF3_V = 4,20,1,0 %; macro FPSR$V_SF3_D = 4,21,1,0 %; macro FPSR$V_SF3_Z = 4,22,1,0 %; macro FPSR$V_SF3_O = 4,23,1,0 %; macro FPSR$V_SF3_U = 4,24,1,0 %; macro FPSR$V_SF3_I = 4,25,1,0 %; literal FPSR$K_INITIAL_VALUE_L = 40895295; ! Low half: sf0=0x0c sf1=0x4e,sf2=sf3=4c traps set to 0x3f literal FPSR$K_INITIAL_VALUE_H = 622668; ! Upper half !*** MODULE $FQAMDEF *** ! ++ ! Define FQAM CSR offsets and registers for Firefox systems ! -- literal FQAM$L_CSR = 0; ! FQAM II CSR literal FQAM$M_CSR_QBUSARB = %X'1'; literal FQAM$M_CSR_DUMPERROR = %X'2'; literal FQAM$M_CSR_TESTMODE = %X'4'; literal FQAM$S_CSR = 4; macro FQAM$V_CSR_QBUSARB = 0,0,1,0 %; ! QBUS arbitration enable macro FQAM$V_CSR_DUMPERROR = 0,1,1,0 %; ! Dump error macro FQAM$V_CSR_TESTMODE = 0,2,1,0 %; ! Test mode enable diags !*** MODULE $FREDDEF *** literal FRED$M_ASTEN = %X'F'; literal FRED$M_ASTSR = %X'F0'; literal FRED$M_ASTEN_KEN = %X'1'; literal FRED$M_ASTEN_EEN = %X'2'; literal FRED$M_ASTEN_SEN = %X'4'; literal FRED$M_ASTEN_UEN = %X'8'; literal FRED$M_ASTSR_KPD = %X'10'; literal FRED$M_ASTSR_EPD = %X'20'; literal FRED$M_ASTSR_SPD = %X'40'; literal FRED$M_ASTSR_UPD = %X'80'; literal FRED$M_PME = %X'4'; literal FRED$M_AC = %X'8'; literal FRED$M_MFL = %X'10'; literal FRED$M_MFH = %X'20'; literal FRED$M_DFH = %X'80000'; literal FRED$C_HWPCBLEN = 352; ! Length of HWPCB literal FRED$K_HWPCBLEN = 352; ! Length of HWPCB ! literal FRED$M_SW_FEN = %X'1'; literal FRED$M_BORROWED_QUANTUM = %X'2'; literal FRED$M_PREEMPT_AVOIDED = %X'4'; literal FRED$M_AST_PENDING = %X'80000000'; literal FRED$C_KTB_KT_ID = 2304; ! integer offset to this field literal FRED$C_KTB = 2304; ! integer offset to this field literal FRED$C_KT_ID = 2312; ! integer offset to this field literal FRED$S_FRED = 4096; ! ! Hardware Privileged Context Block (HWPCB) - This structure must be aligned to ! a 128 byte boundary. Natural alignment prevents the structure from crossing a ! page boundary. ! ! NOTE WELL: There are bit symbols defined here for accessing the saved ASTEN, ! ASTSR, FEN and DATFX/AC values in the HWPCB. These symbols are NOT to be used when ! interfacing to the ASTEN, ASTSR, FEN or DATFX/AC internal processor registers directly. ! See the specific internal register definitions for bitmasks and constants ! to be used when interfacing to the IPRs directly. ! macro FRED$Q_KSP = 0,0,0,1 %; literal FRED$S_KSP = 8; ! Kernel stack pointer macro FRED$Q_ESP = 8,0,0,1 %; literal FRED$S_ESP = 8; ! Executive stack pointer macro FRED$Q_SSP = 16,0,0,1 %; literal FRED$S_SSP = 8; ! Supervisor stack pointer macro FRED$Q_USP = 24,0,0,1 %; literal FRED$S_USP = 8; ! User stack pointer ! Verified for IA64 port - KLN macro FRED$Q_KPFS = 32,0,0,0 %; literal FRED$S_KPFS = 8; ! PFS of thread switched out macro FRED$Q_KRNAT = 40,0,0,0 %; literal FRED$S_KRNAT = 8; ! RNAT of thread switched out macro FRED$PQ_KBSP = 48,0,0,1 %; literal FRED$S_KBSP = 8; ! Kernel Backing Store Pointer macro FRED$PQ_EBSP = 56,0,0,1 %; literal FRED$S_EBSP = 8; ! Exec Backing Store Pointer macro FRED$PQ_SBSP = 64,0,0,1 %; literal FRED$S_SBSP = 8; ! Supervisor Backing Store Pointer macro FRED$PQ_UBSP = 72,0,0,1 %; literal FRED$S_UBSP = 8; ! User Backing Store Pointer ! Verified for IA64 port - KLN macro FRED$Q_PTBR = 80,0,0,0 %; literal FRED$S_PTBR = 128; ! Page table PFN (Only VRNX 0,15 are used) macro FRED$Q_ASN = 208,0,0,0 %; literal FRED$S_ASN = 64; ! ASN/Region IDs (only VRN 0,7 used) macro FRED$Q_ASTSR_ASTEN = 272,0,0,0 %; literal FRED$S_ASTSR_ASTEN = 8; ! ASTSR / ASTEN quadword macro FRED$V_ASTEN = 272,0,4,0 %; literal FRED$S_ASTEN = 4; ! AST Enable Register macro FRED$V_ASTSR = 272,4,4,0 %; literal FRED$S_ASTSR = 4; ! AST Pending Summary Register macro FRED$V_ASTEN_KEN = 272,0,1,0 %; ! Kernel AST Enable = 1 macro FRED$V_ASTEN_EEN = 272,1,1,0 %; ! Executive AST Enable = 1 macro FRED$V_ASTEN_SEN = 272,2,1,0 %; ! Supervisor AST Enable = 1 macro FRED$V_ASTEN_UEN = 272,3,1,0 %; ! User AST Enable = 1 macro FRED$V_ASTSR_KPD = 272,4,1,0 %; ! Kernel AST Pending = 1 macro FRED$V_ASTSR_EPD = 272,5,1,0 %; ! Executive AST Pending = 1 macro FRED$V_ASTSR_SPD = 272,6,1,0 %; ! Supervisor AST Pending = 1 macro FRED$V_ASTSR_UPD = 272,7,1,0 %; ! User AST Pending = 1 ! Process Attributes Section replaces Alpha FEN quadword macro FRED$IQ_PAS = 280,0,0,0 %; literal FRED$S_PAS = 8; ! Floating Point Disable / modified / PME / AC macro FRED$IL_PAS_L = 280,0,32,0 %; macro FRED$IL_PAS_H = 284,0,32,0 %; macro FRED$V_PME = 280,2,1,0 %; ! Performance Monitor Enable macro FRED$V_AC = 280,3,1,0 %; ! Data Alignment Check Enable macro FRED$V_MFL = 280,4,1,0 %; ! Low FPRs modified macro FRED$V_MFH = 280,5,1,0 %; ! High FPRs modified macro FRED$V_DFH = 280,19,1,0 %; ! High Floating Point Disable ! fill_44 bitfield length 44 fill; macro FRED$Q_CC = 288,0,0,0 %; literal FRED$S_CC = 8; ! Cycle Counter macro FRED$Q_UNQ = 296,0,0,0 %; literal FRED$S_UNQ = 8; ! Thread unique value (IA64 R13) macro FRED$B_PMOD = 304,0,8,0 %; ! Previous mode macro FRED$b_reserved_1 = 305,0,0,1 %; literal FRED$s_reserved_1 = 7; macro FRED$Q_PAL_RSVD = 312,0,0,1 %; literal FRED$S_PAL_RSVD = 40; ! Reserved for PAL Scratch ! End of Hardware Privileged Context Block (HWPCB). ! ! ! Floating Point Register Save Area. There is space for 32 floating ! point registers, F0 through F30, and the FPCR. Note that F31 is a ! fixed sink register that doesn't need to be saved. ! macro FRED$Q_FPR = 352,0,0,1 %; literal FRED$S_FPR = 1936; ! Space for 120 FP regs plus FP status and alignment macro FRED$Q_FPSR = 352,0,0,0 %; literal FRED$S_FPSR = 8; ! ar.fpsr, floating point status register macro FRED$q_reserved_2 = 360,0,0,0 %; literal FRED$s_reserved_2 = 8; ! alignment macro FRED$Q_F2 = 368,0,0,0 %; literal FRED$S_F2 = 16; ! F2 macro FRED$Q_F3 = 384,0,0,0 %; literal FRED$S_F3 = 16; ! F3 macro FRED$Q_F4 = 400,0,0,0 %; literal FRED$S_F4 = 16; ! F4 macro FRED$Q_F5 = 416,0,0,0 %; literal FRED$S_F5 = 16; ! F5 macro FRED$Q_F12 = 432,0,0,0 %; literal FRED$S_F12 = 16; ! F12 macro FRED$Q_F13 = 448,0,0,0 %; literal FRED$S_F13 = 16; ! F13 macro FRED$Q_F14 = 464,0,0,0 %; literal FRED$S_F14 = 16; ! F14 macro FRED$Q_F15 = 480,0,0,0 %; literal FRED$S_F15 = 16; ! F15 macro FRED$Q_F16 = 496,0,0,0 %; literal FRED$S_F16 = 16; ! F16 macro FRED$Q_F17 = 512,0,0,0 %; literal FRED$S_F17 = 16; ! F17 macro FRED$Q_F18 = 528,0,0,0 %; literal FRED$S_F18 = 16; ! F18 macro FRED$Q_F19 = 544,0,0,0 %; literal FRED$S_F19 = 16; ! F19 macro FRED$Q_F20 = 560,0,0,0 %; literal FRED$S_F20 = 16; ! F20 macro FRED$Q_F21 = 576,0,0,0 %; literal FRED$S_F21 = 16; ! F21 macro FRED$Q_F22 = 592,0,0,0 %; literal FRED$S_F22 = 16; ! F22 macro FRED$Q_F23 = 608,0,0,0 %; literal FRED$S_F23 = 16; ! F23 macro FRED$Q_F24 = 624,0,0,0 %; literal FRED$S_F24 = 16; ! F24 macro FRED$Q_F25 = 640,0,0,0 %; literal FRED$S_F25 = 16; ! F25 macro FRED$Q_F26 = 656,0,0,0 %; literal FRED$S_F26 = 16; ! F26 macro FRED$Q_F27 = 672,0,0,0 %; literal FRED$S_F27 = 16; ! F27 macro FRED$Q_F28 = 688,0,0,0 %; literal FRED$S_F28 = 16; ! F28 macro FRED$Q_F29 = 704,0,0,0 %; literal FRED$S_F29 = 16; ! F29 macro FRED$Q_F30 = 720,0,0,0 %; literal FRED$S_F30 = 16; ! F30 macro FRED$Q_F31 = 736,0,0,0 %; literal FRED$S_F31 = 16; ! High Bank of floating registers are stored here: ! There are any number of schemes possible to avoid saving and restoring under ! various situations. For example, there is no reason to save these if we got ! context switched after making a system service call, since they are scratch regs. ! For now, however, we will save them if and only if MFH is set. macro FRED$Q_F32 = 752,0,0,0 %; literal FRED$S_F32 = 16; macro FRED$Q_F33 = 768,0,0,0 %; literal FRED$S_F33 = 16; macro FRED$Q_F34 = 784,0,0,0 %; literal FRED$S_F34 = 16; macro FRED$Q_F35 = 800,0,0,0 %; literal FRED$S_F35 = 16; macro FRED$Q_F36 = 816,0,0,0 %; literal FRED$S_F36 = 16; macro FRED$Q_F37 = 832,0,0,0 %; literal FRED$S_F37 = 16; macro FRED$Q_F38 = 848,0,0,0 %; literal FRED$S_F38 = 16; macro FRED$Q_F39 = 864,0,0,0 %; literal FRED$S_F39 = 16; macro FRED$Q_F40 = 880,0,0,0 %; literal FRED$S_F40 = 16; macro FRED$Q_F41 = 896,0,0,0 %; literal FRED$S_F41 = 16; macro FRED$Q_F42 = 912,0,0,0 %; literal FRED$S_F42 = 16; macro FRED$Q_F43 = 928,0,0,0 %; literal FRED$S_F43 = 16; macro FRED$Q_F44 = 944,0,0,0 %; literal FRED$S_F44 = 16; macro FRED$Q_F45 = 960,0,0,0 %; literal FRED$S_F45 = 16; macro FRED$Q_F46 = 976,0,0,0 %; literal FRED$S_F46 = 16; macro FRED$Q_F47 = 992,0,0,0 %; literal FRED$S_F47 = 16; macro FRED$Q_F48 = 1008,0,0,0 %; literal FRED$S_F48 = 16; macro FRED$Q_F49 = 1024,0,0,0 %; literal FRED$S_F49 = 16; macro FRED$Q_F50 = 1040,0,0,0 %; literal FRED$S_F50 = 16; macro FRED$Q_F51 = 1056,0,0,0 %; literal FRED$S_F51 = 16; macro FRED$Q_F52 = 1072,0,0,0 %; literal FRED$S_F52 = 16; macro FRED$Q_F53 = 1088,0,0,0 %; literal FRED$S_F53 = 16; macro FRED$Q_F54 = 1104,0,0,0 %; literal FRED$S_F54 = 16; macro FRED$Q_F55 = 1120,0,0,0 %; literal FRED$S_F55 = 16; macro FRED$Q_F56 = 1136,0,0,0 %; literal FRED$S_F56 = 16; macro FRED$Q_F57 = 1152,0,0,0 %; literal FRED$S_F57 = 16; macro FRED$Q_F58 = 1168,0,0,0 %; literal FRED$S_F58 = 16; macro FRED$Q_F59 = 1184,0,0,0 %; literal FRED$S_F59 = 16; macro FRED$Q_F60 = 1200,0,0,0 %; literal FRED$S_F60 = 16; macro FRED$Q_F61 = 1216,0,0,0 %; literal FRED$S_F61 = 16; macro FRED$Q_F62 = 1232,0,0,0 %; literal FRED$S_F62 = 16; macro FRED$Q_F63 = 1248,0,0,0 %; literal FRED$S_F63 = 16; macro FRED$Q_F64 = 1264,0,0,0 %; literal FRED$S_F64 = 16; macro FRED$Q_F65 = 1280,0,0,0 %; literal FRED$S_F65 = 16; macro FRED$Q_F66 = 1296,0,0,0 %; literal FRED$S_F66 = 16; macro FRED$Q_F67 = 1312,0,0,0 %; literal FRED$S_F67 = 16; macro FRED$Q_F68 = 1328,0,0,0 %; literal FRED$S_F68 = 16; macro FRED$Q_F69 = 1344,0,0,0 %; literal FRED$S_F69 = 16; macro FRED$Q_F70 = 1360,0,0,0 %; literal FRED$S_F70 = 16; macro FRED$Q_F71 = 1376,0,0,0 %; literal FRED$S_F71 = 16; macro FRED$Q_F72 = 1392,0,0,0 %; literal FRED$S_F72 = 16; macro FRED$Q_F73 = 1408,0,0,0 %; literal FRED$S_F73 = 16; macro FRED$Q_F74 = 1424,0,0,0 %; literal FRED$S_F74 = 16; macro FRED$Q_F75 = 1440,0,0,0 %; literal FRED$S_F75 = 16; macro FRED$Q_F76 = 1456,0,0,0 %; literal FRED$S_F76 = 16; macro FRED$Q_F77 = 1472,0,0,0 %; literal FRED$S_F77 = 16; macro FRED$Q_F78 = 1488,0,0,0 %; literal FRED$S_F78 = 16; macro FRED$Q_F79 = 1504,0,0,0 %; literal FRED$S_F79 = 16; macro FRED$Q_F80 = 1520,0,0,0 %; literal FRED$S_F80 = 16; macro FRED$Q_F81 = 1536,0,0,0 %; literal FRED$S_F81 = 16; macro FRED$Q_F82 = 1552,0,0,0 %; literal FRED$S_F82 = 16; macro FRED$Q_F83 = 1568,0,0,0 %; literal FRED$S_F83 = 16; macro FRED$Q_F84 = 1584,0,0,0 %; literal FRED$S_F84 = 16; macro FRED$Q_F85 = 1600,0,0,0 %; literal FRED$S_F85 = 16; macro FRED$Q_F86 = 1616,0,0,0 %; literal FRED$S_F86 = 16; macro FRED$Q_F87 = 1632,0,0,0 %; literal FRED$S_F87 = 16; macro FRED$Q_F88 = 1648,0,0,0 %; literal FRED$S_F88 = 16; macro FRED$Q_F89 = 1664,0,0,0 %; literal FRED$S_F89 = 16; macro FRED$Q_F90 = 1680,0,0,0 %; literal FRED$S_F90 = 16; macro FRED$Q_F91 = 1696,0,0,0 %; literal FRED$S_F91 = 16; macro FRED$Q_F92 = 1712,0,0,0 %; literal FRED$S_F92 = 16; macro FRED$Q_F93 = 1728,0,0,0 %; literal FRED$S_F93 = 16; macro FRED$Q_F94 = 1744,0,0,0 %; literal FRED$S_F94 = 16; macro FRED$Q_F95 = 1760,0,0,0 %; literal FRED$S_F95 = 16; macro FRED$Q_F96 = 1776,0,0,0 %; literal FRED$S_F96 = 16; macro FRED$Q_F97 = 1792,0,0,0 %; literal FRED$S_F97 = 16; macro FRED$Q_F98 = 1808,0,0,0 %; literal FRED$S_F98 = 16; macro FRED$Q_F99 = 1824,0,0,0 %; literal FRED$S_F99 = 16; macro FRED$Q_F100 = 1840,0,0,0 %; literal FRED$S_F100 = 16; macro FRED$Q_F101 = 1856,0,0,0 %; literal FRED$S_F101 = 16; macro FRED$Q_F102 = 1872,0,0,0 %; literal FRED$S_F102 = 16; macro FRED$Q_F103 = 1888,0,0,0 %; literal FRED$S_F103 = 16; macro FRED$Q_F104 = 1904,0,0,0 %; literal FRED$S_F104 = 16; macro FRED$Q_F105 = 1920,0,0,0 %; literal FRED$S_F105 = 16; macro FRED$Q_F106 = 1936,0,0,0 %; literal FRED$S_F106 = 16; macro FRED$Q_F107 = 1952,0,0,0 %; literal FRED$S_F107 = 16; macro FRED$Q_F108 = 1968,0,0,0 %; literal FRED$S_F108 = 16; macro FRED$Q_F109 = 1984,0,0,0 %; literal FRED$S_F109 = 16; macro FRED$Q_F110 = 2000,0,0,0 %; literal FRED$S_F110 = 16; macro FRED$Q_F111 = 2016,0,0,0 %; literal FRED$S_F111 = 16; macro FRED$Q_F112 = 2032,0,0,0 %; literal FRED$S_F112 = 16; macro FRED$Q_F113 = 2048,0,0,0 %; literal FRED$S_F113 = 16; macro FRED$Q_F114 = 2064,0,0,0 %; literal FRED$S_F114 = 16; macro FRED$Q_F115 = 2080,0,0,0 %; literal FRED$S_F115 = 16; macro FRED$Q_F116 = 2096,0,0,0 %; literal FRED$S_F116 = 16; macro FRED$Q_F117 = 2112,0,0,0 %; literal FRED$S_F117 = 16; macro FRED$Q_F118 = 2128,0,0,0 %; literal FRED$S_F118 = 16; macro FRED$Q_F119 = 2144,0,0,0 %; literal FRED$S_F119 = 16; macro FRED$Q_F120 = 2160,0,0,0 %; literal FRED$S_F120 = 16; macro FRED$Q_F121 = 2176,0,0,0 %; literal FRED$S_F121 = 16; macro FRED$Q_F122 = 2192,0,0,0 %; literal FRED$S_F122 = 16; macro FRED$Q_F123 = 2208,0,0,0 %; literal FRED$S_F123 = 16; macro FRED$Q_F124 = 2224,0,0,0 %; literal FRED$S_F124 = 16; macro FRED$Q_F125 = 2240,0,0,0 %; literal FRED$S_F125 = 16; macro FRED$Q_F126 = 2256,0,0,0 %; literal FRED$S_F126 = 16; macro FRED$Q_F127 = 2272,0,0,0 %; literal FRED$S_F127 = 16; ! ! End of Floating Point Register Save Area. ! ! ! Note: The Alpha architecture defines that the FEN bit in HWPCB cannot ! be read, so a separate software FEN bit must be kept. For performance ! reasons, we make this bit the low-bit. ! macro FRED$L_FLAGS = 2288,0,32,0 %; ! Flags longword macro FRED$V_SW_FEN = 2288,0,1,0 %; ! Software FEN bit macro FRED$V_BORROWED_QUANTUM = 2288,1,1,0 %; ! The next quantum was borrowed macro FRED$V_PREEMPT_AVOIDED = 2288,2,1,0 %; ! Prio raised to avoid preempt macro FRED$V_AST_PENDING = 2288,31,1,0 %; ! AST pending optimization ! quadword field and overlays ! PHD$L_EXTRACPU, so don't ! use it for anything. macro FRED$Q_ASNSEQ = 2296,0,0,0 %; literal FRED$S_ASNSEQ = 8; ! Current ASN/RID Sequence Number macro FRED$Q_KTB = 2304,0,0,1 %; literal FRED$S_KTB = 8; ! kernel thread block address macro FRED$Q_KT_ID = 2312,0,0,0 %; literal FRED$S_KT_ID = 8; ! kernel thread id literal FRED$C_LENGTH = 4096; ! Length of Fred block literal FRED$K_LENGTH = 4096; ! Length of Fred block literal FRED$S_FREDDEF = 4096; ! Old size name - synonym literal FRED$K_SHIFT = 12; ! Shift value for FRED size !*** MODULE $FTRDDEF *** ! + ! ! FTRD - Read request packet for FTDRIVER ! ! The FTRD packet is very similar to an IRP but much smaller. It has an ! ACB at the front, the EFN, and some information about the read buffer. ! ! - literal FTRD$K_LENGTH = 40; ! Size of read packet literal FTRD$C_LENGTH = 40; ! literal FTRD$S_FTRDDEF = 40; literal FTRD$S_FTRD = 40; macro FTRD$L_ASTQFL = 0,0,32,1 %; ! Read and AST queue forward link macro FTRD$L_ASTQBL = 4,0,32,1 %; ! Read and AST queue backward link macro FTRD$W_SIZE = 8,0,16,0 %; ! Size of structure macro FTRD$B_TYPE = 10,0,8,0 %; ! Type of structure macro FTRD$B_RMOD = 11,0,8,0 %; ! RMOD bits used by AST delivery code macro FTRD$L_PID = 12,0,32,0 %; ! Internal PID of process to receive AST macro FTRD$L_AST = 16,0,32,1 %; ! AST routine address macro FTRD$L_ASTPRM = 20,0,32,0 %; ! AST parameter macro FTRD$B_EFN = 24,0,8,0 %; ! EFN to be set macro FTRD$B_UNUSED = 25,0,8,0 %; ! Spare byte macro FTRD$W_READ_SIZE = 26,0,16,0 %; ! Size of read request in bytes macro FTRD$L_BUFF_ADDR = 28,0,32,1 %; ! Address of I/O buffer macro FTRD$L_CHAR_ADDR = 32,0,32,1 %; ! Address of next character macro FTRD$L_CHARS_READ = 36,0,32,0 %; ! Number of characters in read buffer !*** MODULE $FVEDEF *** ! + ! Define Fandle Vector Entry ! - literal FVE$K_LENGTH = 32; ! Length of FVE literal FVE$C_LENGTH = 32; ! Length of FVE literal FVE$S_FVEDEF = 32; ! Size of FVE literal FVE$S_FVE = 32; macro FVE$L_IRPPTR = 0,0,32,1 %; ! Address of associated IRP macro FVE$L_ORGFUN = 4,0,32,0 %; ! Original value of IRP$L_FUNC macro FVE$L_DATOB1 = 8,0,32,0 %; ! Data buffer object handle macro FVE$L_DATOB2 = 12,0,32,0 %; macro FVE$L_IOSOB1 = 16,0,32,0 %; ! IOSA buffer object handle macro FVE$L_IOSOB2 = 20,0,32,0 %; macro FVE$Q_DBYLEN = 24,0,0,1 %; literal FVE$S_DBYLEN = 8; !*** MODULE $FVHDEF *** ! + ! Define Fandle Vector Header ! - literal FVH$K_LENGTH = 32; ! Length of FVH literal FVH$C_LENGTH = 32; ! Length of FVH literal FVH$S_FVEDEF = 32; ! Size of FVH literal FVH$S_FVH = 32; macro FVH$L_FLINK = 0,0,32,1 %; macro FVH$L_BLINK = 4,0,32,1 %; macro FVH$W_SIZE = 8,0,16,1 %; macro FVH$B_TYPE = 10,0,8,1 %; macro FVH$B_SUBTYPE = 11,0,8,1 %; macro FVH$L_REAL_SIZE = 12,0,32,1 %; ! Actual size might be > 16 bits macro FVH$L_CCBOBJ = 16,0,0,0 %; literal FVH$S_CCBOBJ = 8; ! Process CCB buffer object handle macro FVH$l_fill1 = 24,0,32,1 %; macro FVH$l_fill2 = 28,0,32,1 %; !*** MODULE $FXEDEF *** ! ! DEFINE .ADDRESS AND LP_PSB FIXUP LIST ELEMENT ! literal FXE$K_LENGTH = 8; literal FXE$C_LENGTH = 8; literal FXE$S_FXEREC = 8; macro FXE$L_OFFSET = 0,0,32,0 %; ! OFFSET OF REFERENCE macro FXE$L_USV = 4,0,32,0 %; ! UNIVERSAL SYMBOL VALUE macro FXE$L_PSB = 4,0,32,0 %; ! PROCEDURE SIGNATURE BLOCK !*** MODULE GCTDEF *** literal GCT$K_GALAXY_ID_LENGTH = 16; ! ! typedef the ID and HANDLE ! macro GCT_ID = 0,0,0,0 %; literal S_GCT_ID = 8; macro GCT_HANDLE = 0,0,32,1 %; ! ! Success codes ! literal GCT$K_SUCCESS = 1; literal GCT$K_NOSTATUS = 0; ! ! Error codes. All negative, all even (low bit clear) ! This allows BLISS tests for errors on the low bit to ! work correctly... even though they are not VMS error ! codes. ! literal GCT$K_BADPARAM = -2; ! Bad parameter in call literal GCT$K_ILLEGAL = -4; ! Operation is illegal literal GCT$K_NOTFOUND = -6; ! Lookup failed literal GCT$K_BADALIGN = -8; ! Bad PA alignment literal GCT$K_BADALLOC = -10; ! Invalid size increment literal GCT$K_OVERLAP = -12; ! Fragment overlaps with existing literal GCT$K_NOTINITIALIZED = -14; ! Tree not initialized literal GCT$K_BADHANDLE = -16; ! Illegal HANDLE literal GCT$K_NOTDELETED = -18; ! Node was not deleted literal GCT$K_MAXEXCEEDED = -20; ! Too many memory fragments literal GCT$K_NOTALLOWED = -22; ! Operation is not allowed literal GCT$K_BADOWNER = -24; ! Node does not have the right owner literal GCT$K_ALREADYOWNED = -26; ! Node already has an owner literal GCT$K_NOTPARTITION = -28; ! The node is not a partition literal GCT$K_NOTCOMMUNITY = -30; ! The node is not a community literal GCT$K_ILLEGALTREE = -32; ! Corrupt tree state literal GCT$K_NOTHARDWARE = -34; ! The node is not a hardware component literal GCT$K_NOMEMORY = -36; ! Failed to allocate the node literal GCT$K_BADPA = -38; ! PA is not in the memory system literal GCT$K_BADSIZE = -40; ! Size of the fragment is not valid literal GCT$K_TREELOCKED = -42; ! Attempt to lock a locked tree literal GCT$K_BADUPDATELEVEL = -44; ! Illegal update level input literal GCT$K_NOTMEMORYDESC = -46; ! Not a memory descriptor node literal GCT$K_NOTLOCKED = -48; ! Tried to unlock an unlocked tree literal GCT$K_UNAVAILABLE = -50; ! Node is not available literal GCT$K_STILLACTIVE = -52; ! The HW component is still active literal GCT$K_CHILDSTILLACTIVE = -54; ! A component part of the HW is still active literal GCT$K_CHILDALREADYOWNED = -56; ! A child is owned. This is an internal error! literal GCT$K_NOTSHARED = -58; ! The device can't be assigned because an ancestor is not shared ! ! Node TYPE codes ! literal GCT$K_NODE_ROOT = 1; ! Root node literal GCT$K_NODE_HW_ROOT = 2; ! Hardware Root literal GCT$K_NODE_SW_ROOT = 3; ! Software Root literal GCT$K_NODE_TEMPLATE_ROOT = 4; ! Template Root literal GCT$K_NODE_COMMUNITY = 5; ! Community literal GCT$K_NODE_PARTITION = 6; ! Partition literal GCT$K_NODE_SBB = 7; ! System Building Block literal GCT$K_NODE_PSEUDO = 8; ! Pseudo device literal GCT$K_NODE_CPU = 9; ! CPU literal GCT$K_NODE_MEMORY_SUB = 10; ! Memory Subsystem literal GCT$K_NODE_MEMORY_DESC = 11; ! Memory Description literal GCT$K_NODE_MEMORY_CTRL = 12; ! Memory Controller literal GCT$K_NODE_IOP = 13; ! IO Processor literal GCT$K_NODE_HOSE = 14; ! IO Hose literal GCT$K_NODE_BUS = 15; ! Option Bus literal GCT$K_NODE_IO_CTRL = 16; ! IO Controller literal GCT$K_NODE_SLOT = 17; ! Option slot literal GCT$K_NODE_CPU_MODULE = 18; ! CPU module board literal GCT$K_NODE_POWER_ENVIR = 19; ! Power Environmental literal GCT$K_NODE_FRU_ROOT = 20; ! FRU Root literal GCT$K_NODE_FRU_DESC = 21; ! FRU Descripter literal GCT$K_NODE_SMB = 22; ! System Mother Board literal GCT$K_NODE_CAB = 23; ! Cabinet literal GCT$K_NODE_SYS_CHASSIS = 24; ! System Chassis literal GCT$K_NODE_EXP_CHASSIS = 25; ! Expander Chassis literal GCT$K_NODE_SYS_INTER_SWITCH = 26; ! System Interconnect Switch literal GCT$K_NODE_LAST = 27; ! Always Last ! ! Routine index values for console callbacks ! literal GCT$K_READ_LOCK = 1; ! Take out a read lock literal GCT$K_READ_UNLOCK = 2; ! Release the read lock literal GCT$K_SET_ACTIVE = 3; ! Set a node active (current_owner) literal GCT$K_SET_INACTIVE = 4; ! Set a node inactive (current_owner) literal GCT$K_ASSIGN_FRAGMENT = 5; ! Assign a memory fragment literal GCT$K_DEASSIGN_FRAGMENT = 6; ! Deassign a memory fragment literal GCT$K_CREATE_COMMUNITY = 7; ! Create a community node literal GCT$K_DELETE_COMMUNITY = 8; ! Delete a community literal GCT$K_CREATE_PARTITION = 9; ! Create a partition node literal GCT$K_DELETE_PARTITION = 10; ! Delete a partition literal GCT$K_ASSIGN_HW = 11; ! Assign HW to a community or partition literal GCT$K_DEASSIGN_HW = 12; ! Deassign HW literal GCT$K_FIND_PARTITION = 13; ! Find Partition literal GCT$K_FIND_NODE = 14; ! Search for a component literal GCT$K_GET_TEXT = 15; ! Get a text string literal GCT$K_UPDATE_GMDB = 16; ! Update GMDB area in community literal GCT$K_VALIDATE_PARTITION = 17; ! Validate a partition literal GCT$K_INITIALIZE_PARTITION = 18; ! Initialize a partition literal GCT$K_UPDATE_GALAXY_ID = 19; ! Update the Galaxy ID literal GCT$K_GET_MAX_PARTITION = 20; ! Get the max partition count literal GCT$K_UPDATE_INSTANCE_NAME = 21; ! Read/Write Instance Name literal GCT$K_SAVE_CONFIG = 22; ! Save Configuration literal GCT$K_GET_SENSOR_INFO = 23; ! Get sensor information ! ! Node subtype codes ! literal GCT$K_SNODE_UNKNOWN = 0; ! Unknown subtype ! CPU codes literal GCT$K_SNODE_CPU_NOPRIMARY = 1; ! A CPU not capable of being a primary ! Bus codes literal GCT$K_SNODE_PCI = 2; ! Peripheral Component Interconnect literal GCT$K_SNODE_EISA = 3; ! Extended ISA bus literal GCT$K_SNODE_ISA = 4; ! Industry Standard Architecture bus literal GCT$K_SNODE_XMI = 5; ! XMI bus literal GCT$K_SNODE_FBUS = 6; ! FutureBus literal GCT$K_SNODE_XBUS = 7; ! Built in device bus literal GCT$K_SNODE_USB = 8; ! Univeral Serial Bus ! IO controller codes literal GCT$K_SNODE_SERIAL_PORT = 9; ! Serial port literal GCT$K_SNODE_FLOPPY = 10; ! Standard Floppy literal GCT$K_SNODE_PARALLEL_PORT = 11; ! Parallel port literal GCT$K_SNODE_SCSI = 12; ! SCSI Controller literal GCT$K_SNODE_IDE = 13; ! IDE Controller literal GCT$K_SNODE_NI = 14; ! Ethernet Controller literal GCT$K_SNODE_FDDI = 15; ! FDDI literal GCT$K_SNODE_TOKEN_RING = 16; ! Token Ring literal GCT$K_SNODE_NI_SCSI = 17; ! Combo card literal GCT$K_SNODE_GRAPHICS = 18; ! Graphics Controller literal GCT$K_SNODE_ATM = 19; ! ATM Controller literal GCT$K_SNODE_MEM_CHAN = 20; ! Memory Channel literal GCT$K_SNODE_CI = 21; ! CI adapter literal GCT$K_SNODE_1394 = 22; ! literal GCT$K_SNODE_AGP = 23; ! AGP (Graphics Port) literal GCT$K_SNODE_SUPER_HIPPI = 24; ! Super Hippi literal GCT$K_SNODE_FIBRECHANNEL = 25; ! Fibrechannel literal GCT$K_SNODE_CAB = 26; ! Cabinet literal GCT$K_SNODE_CHASSIS = 27; ! System Chassis literal GCT$K_SNODE_EXP_CHASSIS = 28; ! Expand System Chassis literal GCT$K_SNODE_POWER_SUPPLY = 29; ! Power Envir - Power Supply literal GCT$K_SNODE_COOLING = 30; ! Power Envir - Cooling literal GCT$K_SNODE_LAST = 31; ! Highest ! ! Lookup flags ! literal GCT$K_FIND_ANY = 0; literal GCT$K_FIND_BY_OWNER = 1; literal GCT$K_FIND_BY_TYPE = 2; literal GCT$K_FIND_BY_SUBTYPE = 4; literal GCT$K_FIND_BY_ID = 8; literal GCT$K_FIND_UNAVAILABLE = 16; ! ! Lock types ! literal GCT$K_LOCK_FOR_READ = 1; ! Just want to read the tree literal GCT$K_LOCK_FOR_UPDATE = 2; ! Want to update the tree literal GCT$K_UNLOCK_READ = 3; ! Unlock a read literal GCT$K_UNLOCK_UPDATE = 4; ! Unlock an update literal GCT$K_UNLOCK_NO_UPDATE = 5; ! Unlock an update lock with no update ! ! Magic ! literal GCT$K_NODE_VALID = 1498958919; ! ! OS types ! literal GCT$K_OS_VMS = 1; ! OS is VMS on Partition literal GCT$K_OS_OSF = 2; ! OS is OSF on Partition literal GCT$K_OS_NT = 3; ! OS is NT on Partition literal GCT$K_OS_LAST = 4; ! Always last ! ! Version 5.1 ! literal GCT$K_REVISION_MAJOR = 5; literal GCT$K_REVISION_MINOR = 1; literal gct$S_gct_buffer_header = 64; macro gct$iq_buffer_cksum = 0,0,0,0 %; literal gct$s_buffer_cksum = 8; ! Placeholder for checksum macro gct$il_buffer_size = 8,0,32,0 %; ! Size of structure macro gct$r_revision = 12,0,32,0 %; literal gct$s_revision = 4; macro gct$il_rev_full = 12,0,32,0 %; ! Structure revision macro gct$iw_rev_major = 12,0,16,0 %; macro gct$iw_rev_minor = 14,0,16,0 %; macro gct$t_galaxy_enable = 16,0,8,0 %; ! System supports Galaxy macro gct$b_buffer_reserved = 17,0,0,0 %; literal gct$s_buffer_reserved = 47; ! Pad to 64 bytes ! ! Values for text lookups ! literal GCT$K_NAME_IS_PRETTY = 256; ! Return plain text literal GCT$K_NAME_IS_FLAG = 512; ! Input is flags literal GCT$K_FLAG_NAMES = 512; ! Decode gct$q_node_flags literal GCT$K_MEM_FLAG_NAMES = 513; ! Decode mem_flags literal GCT$K_SUBTYPE_NAMES = 2; ! Decode Subtypes literal GCT$K_TYPE_NAMES = 3; ! Decode Types literal GCT$K_OS_NAMES = 4; ! Decode OS name literal GCT$K_ERROR_TEXT = 5; ! Decode Error value literal GCT$K_RTN_NAMES = 6; ! Callback routine names literal GCT$K_LOCK_TYPES = 7; ! Lock types for calls ! ! An array of bindings are used to tell the code that populates a tree ! what the config and affinity bindings are for any node type. ! literal gct$S_gct_bindings = 4; macro gct$b_bind_type = 0,0,8,0 %; ! Node type macro gct$b_bind_parent = 1,0,8,0 %; ! Type of parent macro gct$b_bind_config = 2,0,8,0 %; ! Config binding macro gct$b_bind_affinity = 3,0,8,0 %; ! Affinity binding ! ! Define the node structure ! literal gct$m_node_hardware = %X'1'; literal gct$m_node_hotswap = %X'2'; literal gct$m_node_unavailable = %X'4'; literal gct$m_node_hw_template = %X'8'; literal gct$m_node_initialized = %X'10'; literal gct$m_node_cpu_primary = %X'20'; literal gct$m_node_in_console = %X'40'; literal gct$m_node_rsrvd_7_31 = %X'FFFFFF80'; literal gct$m_node_rsrvd_32_63 = %X'FFFFFFFF00000000'; literal gct$S_gct_node = 64; macro gct$b_type = 0,0,8,0 %; ! Node type macro gct$b_subtype = 1,0,8,0 %; ! Type-specific subtype macro gct$w_size = 2,0,16,0 %; ! Size of node macro gct$il_hd_extension = 4,0,32,0 %; ! Header Extension offset macro gct$iq_owner_both = 8,0,0,0 %; literal gct$s_owner_both = 8; ! Both owner and active owner macro gct$r_owner_each = 8,0,0,0 %; literal gct$s_owner_each = 8; macro gct$il_owner = 8,0,32,1 %; ! Software owner of node macro gct$il_current_owner = 12,0,32,1 %; ! Active user of the node macro gct$iq_gct_id64 = 16,0,0,0 %; literal gct$s_gct_id64 = 8; ! Reference to the entire 64-bit structure macro gct$_GCT_NODE_ID_SSB = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_SSB = 8; macro gct$v_node_id_sbb_rvd0_31 = 16,0,32,0 %; literal gct$s_node_id_sbb_rvd0_31 = 32; macro gct$v_node_id_sbb_rvd32_47 = 20,0,16,0 %; literal gct$s_node_id_sbb_rvd32_47 = 16; macro gct$v_node_id_sbb_sbb = 20,16,8,0 %; literal gct$s_node_id_sbb_sbb = 8; macro gct$v_node_id_sbb_rvd56_63 = 20,24,8,0 %; literal gct$s_node_id_sbb_rvd56_63 = 8; macro gct$_GCT_NODE_ID_SMB = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_SMB = 8; macro gct$v_node_id_smb_rvd0_31 = 16,0,32,0 %; literal gct$s_node_id_smb_rvd0_31 = 32; macro gct$v_node_id_smb_rvd32_38 = 20,0,8,0 %; literal gct$s_node_id_smb_rvd32_38 = 8; macro gct$v_node_id_smb_smb = 20,8,8,0 %; literal gct$s_node_id_smb_smb = 8; macro gct$v_node_id_smb_sbb = 20,16,8,0 %; literal gct$s_node_id_smb_sbb = 8; macro gct$v_node_id_smb_rvd56_63 = 20,24,8,0 %; literal gct$s_node_id_smb_rvd56_63 = 8; macro gct$_GCT_NODE_ID_CPU = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_CPU = 8; macro gct$v_node_id_cpu_cpu = 16,0,16,0 %; literal gct$s_node_id_cpu_cpu = 16; macro gct$v_node_id_cpu_rvd16_23 = 16,16,8,0 %; literal gct$s_node_id_cpu_rvd16_23 = 8; macro gct$v_node_id_cpu_revcnt = 16,24,8,0 %; literal gct$s_node_id_cpu_revcnt = 8; macro gct$v_node_id_cpu_rvd32_39 = 20,0,8,0 %; literal gct$s_node_id_cpu_rvd32_39 = 8; macro gct$v_node_id_cpu_smb = 20,8,8,0 %; literal gct$s_node_id_cpu_smb = 8; macro gct$v_node_id_cpu_sbb = 20,16,8,0 %; literal gct$s_node_id_cpu_sbb = 8; macro gct$v_node_id_cpu_rvd56_63 = 20,24,8,0 %; literal gct$s_node_id_cpu_rvd56_63 = 8; macro gct$_GCT_NODE_ID_MEM_SUB = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_MEM_SUB = 8; macro gct$v_node_id_mem_sub_memsub = 16,0,8,0 %; literal gct$s_node_id_mem_sub_memsub = 8; macro gct$v_node_id_mem_sub_rvd8_39 = 16,8,32,0 %; literal gct$s_node_id_mem_sub_rvd8_39 = 32; macro gct$v_node_id_mem_sub_smb = 20,8,8,0 %; literal gct$s_node_id_mem_sub_smb = 8; macro gct$v_node_id_mem_sub_sbb = 20,16,8,0 %; literal gct$s_node_id_mem_sub_sbb = 8; macro gct$v_node_id_mem_sub_rvd56_63 = 20,24,8,0 %; literal gct$s_node_id_mem_sub_rvd56_63 = 8; macro gct$_GCT_NODE_ID_MEM_DESC = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_MEM_DESC = 8; macro gct$v_node_id_mem_desc_memdesc = 16,0,16,0 %; literal gct$s_node_id_mem_desc_memdesc = 16; macro gct$v_node_id_mem_desc_memsub = 16,16,8,0 %; literal gct$s_node_id_mem_desc_memsub = 8; macro gct$v_node_id_mem_desc_rvd24_39 = 16,24,16,0 %; literal gct$s_node_id_mem_desc_rvd24_39 = 16; macro gct$v_node_id_mem_desc_smb = 20,8,8,0 %; literal gct$s_node_id_mem_desc_smb = 8; macro gct$v_node_id_mem_desc_sbb = 20,16,8,0 %; literal gct$s_node_id_mem_desc_sbb = 8; macro gct$v_node_id_mem_desc_rvd56_63 = 20,24,8,0 %; literal gct$s_node_id_mem_desc_rvd56_63 = 8; macro gct$_GCT_NODE_ID_MEM_CTRL = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_MEM_CTRL = 8; macro gct$v_node_id_mem_ctrl_memctrl = 16,0,16,0 %; literal gct$s_node_id_mem_ctrl_memctrl = 16; macro gct$v_node_id_mem_ctrl_memsub = 16,16,8,0 %; literal gct$s_node_id_mem_ctrl_memsub = 8; macro gct$v_node_id_mem_ctrl_rvd24_39 = 16,24,16,0 %; literal gct$s_node_id_mem_ctrl_rvd24_39 = 16; macro gct$v_node_id_mem_ctrl_smb = 20,8,8,0 %; literal gct$s_node_id_mem_ctrl_smb = 8; macro gct$v_node_id_mem_ctrl_sbb = 20,16,8,0 %; literal gct$s_node_id_mem_ctrl_sbb = 8; macro gct$v_node_id_mem_ctrl_rvd56_63 = 20,24,8,0 %; literal gct$s_node_id_mem_ctrl_rvd56_63 = 8; macro gct$_GCT_NODE_ID_IOP = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_IOP = 8; macro gct$v_node_id_iop_iop = 16,0,8,0 %; literal gct$s_node_id_iop_iop = 8; macro gct$v_node_id_iop_rvd8_39 = 16,8,32,0 %; literal gct$s_node_id_iop_rvd8_39 = 32; macro gct$v_node_id_iop_smb = 20,8,8,0 %; literal gct$s_node_id_iop_smb = 8; macro gct$v_node_id_iop_sbb = 20,16,8,0 %; literal gct$s_node_id_iop_sbb = 8; macro gct$v_node_id_iop_rvd56_63 = 20,24,8,0 %; literal gct$s_node_id_iop_rvd56_63 = 8; macro gct$_GCT_NODE_ID_HOSE = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_HOSE = 8; macro gct$v_node_id_hose_hose = 16,0,8,0 %; literal gct$s_node_id_hose_hose = 8; macro gct$v_node_id_hose_iop = 16,8,8,0 %; literal gct$s_node_id_hose_iop = 8; macro gct$v_node_id_hose_rvd24_47 = 16,16,24,0 %; literal gct$s_node_id_hose_rvd24_47 = 24; macro gct$v_node_id_hose_smb = 20,8,8,0 %; literal gct$s_node_id_hose_smb = 8; macro gct$v_node_id_hose_sbb = 20,16,8,0 %; literal gct$s_node_id_hose_sbb = 8; macro gct$v_node_id_hose_rvd56_63 = 20,24,8,0 %; literal gct$s_node_id_hose_rvd56_63 = 8; macro gct$_GCT_NODE_ID_BUS = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_BUS = 8; macro gct$v_node_id_bus_bus = 16,0,8,0 %; literal gct$s_node_id_bus_bus = 8; macro gct$v_node_id_bus_hose = 16,8,8,0 %; literal gct$s_node_id_bus_hose = 8; macro gct$v_node_id_bus_iop = 16,16,8,0 %; literal gct$s_node_id_bus_iop = 8; macro gct$v_node_id_bus_rvd24_39 = 16,24,16,0 %; literal gct$s_node_id_bus_rvd24_39 = 16; macro gct$v_node_id_bus_smb = 20,8,8,0 %; literal gct$s_node_id_bus_smb = 8; macro gct$v_node_id_bus_sbb = 20,16,8,0 %; literal gct$s_node_id_bus_sbb = 8; macro gct$v_node_id_bus_rvd56_63 = 20,24,8,0 %; literal gct$s_node_id_bus_rvd56_63 = 8; macro gct$_GCT_NODE_ID_SLOT = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_SLOT = 8; macro gct$v_node_id_slot_slot = 16,0,8,0 %; literal gct$s_node_id_slot_slot = 8; macro gct$v_node_id_slot_bus = 16,8,8,0 %; literal gct$s_node_id_slot_bus = 8; macro gct$v_node_id_slot_hose = 16,16,8,0 %; literal gct$s_node_id_slot_hose = 8; macro gct$v_node_id_slot_iop = 16,24,8,0 %; literal gct$s_node_id_slot_iop = 8; macro gct$v_node_id_slot_rvd24_31 = 20,0,8,0 %; literal gct$s_node_id_slot_rvd24_31 = 8; macro gct$v_node_id_slot_smb = 20,8,8,0 %; literal gct$s_node_id_slot_smb = 8; macro gct$v_node_id_slot_sbb = 20,16,8,0 %; literal gct$s_node_id_slot_sbb = 8; macro gct$v_node_id_slot_rvd56_63 = 20,24,8,0 %; literal gct$s_node_id_slot_rvd56_63 = 8; macro gct$_GCT_NODE_ID_IO_CTRL = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_IO_CTRL = 8; macro gct$v_node_id_io_ctrl_ctrlr = 16,0,8,0 %; literal gct$s_node_id_io_ctrl_ctrlr = 8; macro gct$v_node_id_io_ctrl_bus = 16,8,8,0 %; literal gct$s_node_id_io_ctrl_bus = 8; macro gct$v_node_id_io_ctrl_hose = 16,16,8,0 %; literal gct$s_node_id_io_ctrl_hose = 8; macro gct$v_node_id_io_ctrl_iop = 16,24,8,0 %; literal gct$s_node_id_io_ctrl_iop = 8; macro gct$v_node_id_io_ctrl_rvd24_31 = 20,0,8,0 %; literal gct$s_node_id_io_ctrl_rvd24_31 = 8; macro gct$v_node_id_io_ctrl_smb = 20,8,8,0 %; literal gct$s_node_id_io_ctrl_smb = 8; macro gct$v_node_id_io_ctrl_sbb = 20,16,8,0 %; literal gct$s_node_id_io_ctrl_sbb = 8; macro gct$v_node_id_io_ctrl_rvd56_63 = 20,24,8,0 %; literal gct$s_node_id_io_ctrl_rvd56_63 = 8; macro gct$_GCT_NODE_ID_POWER_ENV = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_POWER_ENV = 8; macro gct$v_node_id_power_env_pe_num = 16,0,16,0 %; literal gct$s_node_id_power_env_pe_num = 16; macro gct$v_node_id_power_rvd16_31 = 16,16,16,0 %; literal gct$s_node_id_power_rvd16_31 = 16; macro gct$v_node_id_power_env_smb = 20,0,8,0 %; literal gct$s_node_id_power_env_smb = 8; macro gct$v_node_id_power_env_sbb = 20,8,8,0 %; literal gct$s_node_id_power_env_sbb = 8; macro gct$v_node_id_power_env_chassis = 20,16,8,0 %; literal gct$s_node_id_power_env_chassis = 8; macro gct$v_node_id_power_env_cab = 20,24,8,0 %; literal gct$s_node_id_power_env_cab = 8; macro gct$_GCT_NODE_ID_FRU_DESC = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_FRU_DESC = 8; macro gct$v_node_id_fru_desc_site_loc = 16,0,8,0 %; literal gct$s_node_id_fru_desc_site_loc = 8; macro gct$v_node_id_fru_desc_cab_id = 16,8,8,0 %; literal gct$s_node_id_fru_desc_cab_id = 8; macro gct$v_node_id_fru_desc_position = 16,16,8,0 %; literal gct$s_node_id_fru_desc_position = 8; macro gct$v_node_id_fru_desc_chassis = 16,24,8,0 %; literal gct$s_node_id_fru_desc_chassis = 8; macro gct$v_node_id_fru_desc_assembly = 20,0,8,0 %; literal gct$s_node_id_fru_desc_assembly = 8; macro gct$v_node_id_fru_desc_subassem = 20,8,8,0 %; literal gct$s_node_id_fru_desc_subassem = 8; macro gct$v_node_id_fru_desc_slot = 20,16,16,0 %; literal gct$s_node_id_fru_desc_slot = 16; macro gct$_GCT_NODE_ID_SYS_INTER_SW = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_SYS_INTER_SW = 8; macro gct$v_node_id_switch_id = 16,0,16,0 %; literal gct$s_node_id_switch_id = 16; macro gct$_GCT_NODE_ID_PARTITION = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_PARTITION = 8; macro gct$v_node_id_part_id = 16,0,16,0 %; literal gct$s_node_id_part_id = 16; macro gct$_GCT_NODE_ID_COMMUNITY = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_COMMUNITY = 8; macro gct$v_node_id_comm_id = 16,0,16,0 %; literal gct$s_node_id_comm_id = 16; macro gct$_GCT_NODE_ID_ROOT = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_ROOT = 8; macro gct$v_node_id_root = 16,0,8,0 %; literal gct$s_node_id_root = 8; macro gct$_GCT_NODE_ID_HW_ROOT = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_HW_ROOT = 8; macro gct$v_node_id_hw_root = 16,0,8,0 %; literal gct$s_node_id_hw_root = 8; macro gct$_GCT_NODE_ID_SW_ROOT = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_SW_ROOT = 8; macro gct$v_node_id_sw_root = 16,0,8,0 %; literal gct$s_node_id_sw_root = 8; macro gct$_GCT_NODE_ID_FRU_ROOT = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_FRU_ROOT = 8; macro gct$v_node_id_fru_root = 16,0,8,0 %; literal gct$s_node_id_fru_root = 8; macro gct$_GCT_NODE_ID_PSEUDO = 16,0,0,0 %; literal gct$S_GCT_NODE_ID_PSEUDO = 8; macro gct$v_node_id_pseudo_num = 16,0,16,0 %; literal gct$s_node_id_pseudo_num = 16; macro gct$v_node_id_pseudo_chassis = 20,16,8,0 %; literal gct$s_node_id_pseudo_chassis = 8; macro gct$v_node_id_pseudo_cab = 20,24,8,0 %; literal gct$s_node_id_pseudo_cab = 8; macro gct$iq_node_flags = 24,0,0,0 %; literal gct$s_node_flags = 8; ! flags macro gct$v_node_hardware = 24,0,1,0 %; ! Node represents hardware macro gct$v_node_hotswap = 24,1,1,0 %; ! Hardware can be hotswapped macro gct$v_node_unavailable = 24,2,1,0 %; ! Hardware is not avail (power down) macro gct$v_node_hw_template = 24,3,1,0 %; ! Node is a template device macro gct$v_node_initialized = 24,4,1,0 %; ! Partition is initialized macro gct$v_node_cpu_primary = 24,5,1,0 %; ! CPU is a primary macro gct$v_node_in_console = 24,6,1,0 %; ! CPU is in console mode macro gct$v_node_rsrvd_7_31 = 24,7,25,0 %; literal gct$s_node_rsrvd_7_31 = 25; ! Unused bits in first longword macro gct$v_node_rsrvd_32_63 = 28,0,32,0 %; literal gct$s_node_rsrvd_32_63 = 32; ! Unused bits in second longword macro gct$il_config = 32,0,32,1 %; ! Config binging macro gct$il_affinity = 36,0,32,1 %; ! Affinity (performance) binding macro gct$il_parent = 40,0,32,1 %; ! Parent node macro gct$il_next_sib = 44,0,32,1 %; ! Next sibling node macro gct$il_prev_sib = 48,0,32,1 %; ! Previous sibling node macro gct$il_child = 52,0,32,1 %; ! Child node macro gct$il_magic = 60,0,32,0 %; ! Valid bits 'GLXY' literal gct$S_gct_root_node = 224; macro gct$r_hd_root = 0,0,0,0 %; literal gct$s_hd_root = 64; macro gct$iq_lock = 64,0,0,0 %; literal gct$s_lock = 8; ! Software lock macro gct$iq_transient_level = 72,0,0,0 %; literal gct$s_transient_level = 8; ! Update counter (in prog) macro gct$iq_current_level = 80,0,0,0 %; literal gct$s_current_level = 8; ! Update counter (actual) macro gct$iq_console_req = 88,0,0,0 %; literal gct$s_console_req = 8; ! Memory required for console macro gct$iq_min_alloc = 96,0,0,0 %; literal gct$s_min_alloc = 8; ! Minimum memory allocation macro gct$iq_min_align = 104,0,0,0 %; literal gct$s_min_align = 8; ! Memory allocation alignment macro gct$iq_base_alloc = 112,0,0,0 %; literal gct$s_base_alloc = 8; ! Base memory min allocation macro gct$iq_base_align = 120,0,0,0 %; literal gct$s_base_align = 8; ! Base memory alloc alignment macro gct$iq_max_phys_address = 128,0,0,0 %; literal gct$s_max_phys_address = 8; ! Largest Physical Address macro gct$iq_mem_size = 136,0,0,0 %; literal gct$s_mem_size = 8; ! Total current memory size macro gct$iq_platform_type = 144,0,0,0 %; literal gct$s_platform_type = 8; ! Type code of platform macro gct$il_platform_name = 152,0,32,1 %; ! Offset to name string macro gct$il_primary_instance = 156,0,32,1 %; ! Handle of GALAXY Primary Partiion macro gct$il_first_free = 160,0,32,1 %; ! First free byte of tree pool macro gct$il_high_limit = 164,0,32,1 %; ! High address limit for nodes macro gct$il_lookaside = 168,0,32,1 %; ! Lookaside list for node deletion macro gct$il_available = 172,0,32,1 %; ! Amount of bytes in pool macro gct$il_max_partition = 176,0,32,0 %; ! Max partitions macro gct$il_partitions = 180,0,32,1 %; ! Offset to partition ID map macro gct$il_communities = 184,0,32,1 %; ! Offset to community ID map macro gct$il_max_platform_partition = 188,0,32,0 %; ! Max part platform supports macro gct$il_max_fragments = 192,0,32,0 %; ! Max memory frags per desc macro gct$il_max_desc = 196,0,32,0 %; ! Max memory descriptors macro gct$b_galaxy_id = 200,0,0,1 %; literal gct$s_galaxy_id = 16; ! Galaxy ID macro gct$b_galaxy_id_pad = 216,0,32,1 %; literal gct$s_galaxy_id_pad = 4; ! Pad ID with a longword of bytes (ensures a null terminator) macro gct$il_bindings = 220,0,32,1 %; ! Offset to array of bindings literal gct$S_gct_sw_root_node = 64; macro gct$r_hd_sw_root = 0,0,0,0 %; literal gct$s_hd_sw_root = 64; literal gct$S_gct_hw_root_node = 64; macro gct$r_hd_hw_root = 0,0,0,0 %; literal gct$s_hd_hw_root = 64; literal gct$S_gct_template_root_node = 64; macro gct$r_hd_template_root = 0,0,0,0 %; literal gct$s_hd_template_root = 64; literal gct$S_gct_sbb_node = 64; macro gct$r_hd_sbb = 0,0,0,0 %; literal gct$s_hd_sbb = 64; literal gct$S_gct_iop_node = 80; macro gct$r_hd_iop = 0,0,0,0 %; literal gct$s_hd_iop = 64; macro gct$iq_min_io_pa = 64,0,0,0 %; literal gct$s_min_io_pa = 8; ! Lowest possible PA in I/O subsystem macro gct$iq_max_io_pa = 72,0,0,0 %; literal gct$s_max_io_pa = 8; ! Highest possible PA in I/O subsys literal gct$S_gct_hose_node = 64; macro gct$r_hd_hose = 0,0,0,0 %; literal gct$s_hd_hose = 64; literal gct$S_gct_bus_node = 64; macro gct$r_hd_bus = 0,0,0,0 %; literal gct$s_hd_bus = 64; literal gct$S_gct_slot_node = 64; macro gct$r_hd_slot = 0,0,0,0 %; literal gct$s_hd_slot = 64; literal gct$S_gct_io_ctrl_node = 64; macro gct$r_hd_io_ctrl = 0,0,0,0 %; literal gct$s_hd_io_ctrl = 64; literal gct$S_gct_cpu_module_node = 64; macro gct$r_hd_cpu_module = 0,0,0,0 %; literal gct$s_hd_cpu_module = 64; literal gct$S_gct_cpu_node = 64; macro gct$r_hd_cpu = 0,0,0,0 %; literal gct$s_hd_cpu = 64; literal GCT$K_INSTANCE_NAME_LENGTH = 128; literal gct$S_gct_partition_node = 224; macro gct$r_hd_partition = 0,0,0,0 %; literal gct$s_hd_partition = 64; macro gct$iq_hwrpb = 64,0,0,0 %; literal gct$s_hwrpb = 8; ! HWRPB PA macro gct$iq_incarnation = 72,0,0,0 %; literal gct$s_incarnation = 8; ! Partition incarnation macro gct$iq_priority = 80,0,0,0 %; literal gct$s_priority = 8; ! Partition priority macro gct$il_os_type = 88,0,32,0 %; ! OS type macro gct$il_part_reserved_1 = 92,0,32,1 %; ! Pad longword available for use macro gct$b_instance_name = 96,0,0,1 %; literal gct$s_instance_name = 128; ! Instance Name literal GCT$K_COMM_BLOCK_SIZE = 8; literal gct$S_gct_community_node = 128; macro gct$r_hd_community = 0,0,0,0 %; literal gct$s_hd_community = 64; macro gct$iq_gmdb = 64,0,0,0 %; literal gct$s_gmdb = 64; ! Communication block literal gct$S_gct_memory_sub_node = 80; macro gct$r_hd_memory_sub = 0,0,0,0 %; literal gct$s_hd_memory_sub = 64; macro gct$iq_min_pa = 64,0,0,0 %; literal gct$s_min_pa = 8; ! Lowest possible PA in subsystem macro gct$iq_max_pa = 72,0,0,0 %; literal gct$s_max_pa = 8; ! Highest possible PA in subsys literal gct$S_gct_memory_ctrl_node = 64; macro gct$r_hd_memory_ctrl = 0,0,0,0 %; literal gct$s_hd_memory_ctrl = 64; literal gct$m_mem_console = %X'1'; literal gct$m_mem_private = %X'2'; literal gct$m_mem_shared = %X'4'; literal gct$m_mem_base = %X'8'; literal gct$m_mem_valid = %X'10'; literal gct$m_mem_rsrvd_5_31 = %X'FFFFFFE0'; literal gct$S_gct_mem_desc = 32; macro gct$iq_pa = 0,0,0,0 %; literal gct$s_pa = 8; ! Base PA of memory fragment macro gct$iq_size = 8,0,0,0 %; literal gct$s_size = 8; ! Size of memory fragment macro gct$il_mem_owner = 16,0,32,1 %; macro gct$il_mem_current_owner = 20,0,32,1 %; macro gct$il_mem_flags = 24,0,32,0 %; ! flags macro gct$v_mem_console = 24,0,1,0 %; ! Console memory macro gct$v_mem_private = 24,1,1,0 %; ! Private (non-shared) memory macro gct$v_mem_shared = 24,2,1,0 %; ! Shared memory macro gct$v_mem_base = 24,3,1,0 %; ! Base Segment memory macro gct$v_mem_valid = 24,4,1,0 %; ! Fragment is valid macro gct$v_mem_rsrvd_5_31 = 24,5,27,0 %; literal gct$s_mem_rsrvd_5_31 = 27; ! Unused bits in longword macro gct$il_mem_reserved_1 = 28,0,32,0 %; ! Pad to a quad. Available for use. literal gct$S_gct_mem_info = 24; macro gct$iq_base_pa = 0,0,0,0 %; literal gct$s_base_pa = 8; ! Base PA of desc macro gct$iq_base_size = 8,0,0,0 %; literal gct$s_base_size = 8; ! Size of memory desc macro gct$il_desc_count = 16,0,32,0 %; ! Number of fragments macro gct$il_info_reserved = 20,0,32,0 %; ! Pad to a quad literal gct$S_gct_mem_desc_node = 104; macro gct$r_hd_mem_desc = 0,0,0,0 %; literal gct$s_hd_mem_desc = 64; macro gct$r_mem_info = 64,0,0,0 %; literal gct$s_mem_info = 24; ! Mem desc header macro gct$il_mem_frag = 88,0,32,1 %; ! Offset to descriptors macro gct$il_mem_desc_reserved = 92,0,32,1 %; ! Pad to a quad macro gct$iq_bitmap_pa = 96,0,0,0 %; literal gct$s_bitmap_pa = 8; ! PA of memory bitmap or zero literal gct$S_gct_pseudo_node = 64; macro gct$r_hd_pseudo = 0,0,0,0 %; literal gct$s_hd_pseudo = 64; literal gct$S_gct_power_env_node = 64; macro gct$r_hd_power_env = 0,0,0,0 %; literal gct$s_hd_power_env = 64; literal gct$S_fru_info = 16; macro gct$il_fru_info_diag_flag = 0,0,32,0 %; macro gct$il_fru_info_diag_info = 4,0,32,0 %; macro gct$b_fru_info_tlv = 8,0,8,0 %; ! start of TLVs for manufacturer, model, part_number, serial_number and ! firmware_revision. literal gct$S_gct_fru_root_node = 80; macro gct$r_hd_fru_root = 0,0,0,0 %; literal gct$s_hd_fru_root = 64; macro gct$r_fru_root_info = 64,0,0,0 %; literal gct$s_fru_root_info = 16; literal gct$S_gct_fru_desc_node = 80; macro gct$r_hd_fru_desc = 0,0,0,0 %; literal gct$s_hd_fru_desc = 64; macro gct$r_fru_desc_info = 64,0,0,0 %; literal gct$s_fru_desc_info = 16; literal gct$S_gct_smb_node = 64; macro gct$r_hd_smb = 0,0,0,0 %; literal gct$s_hd_smb = 64; literal gct$S_gct_cab_node = 64; macro gct$r_hd_cab = 0,0,0,0 %; literal gct$s_hd_cab = 64; literal gct$S_gct_chassis_node = 64; macro gct$r_hd_chassis = 0,0,0,0 %; literal gct$s_hd_chassis = 64; literal gct$S_gct_switch_node = 64; macro gct$r_hd_switch = 0,0,0,0 %; literal gct$s_hd_switch = 64; ! ! TLV strings... To access them -- you need to use the tag to understand ! the data type, the length to get the number of bytes. This structure ! contains: ! literal gct$S_GCT_TLV = 8; macro gct$iw_tlv_tag = 0,0,16,0 %; ! The Type of data macro gct$iw_tlv_length = 2,0,16,0 %; ! Its length macro gct$b_tlv_value = 4,0,8,0 %; ! The first byte(s) in the value literal GCT$K_TLV_TAG_ISOLATIN1 = 1; literal GCT$K_TLV_TAG_QUOTED = 2; literal GCT$K_TLV_TAG_BINARY = 3; literal GCT$K_TLV_TAG_UNICODE = 4; ! ! define the diag_failure structure ! literal gct$S_gct_diag_failure = 4; macro gct$b_failure_type_rev = 0,0,8,0 %; ! type nibble (0:3) and revision (4:7) macro gct$b_failure_test = 1,0,8,0 %; ! Test macro gct$b_failure_subtest = 2,0,8,0 %; ! Subtest code macro gct$b_failure_error = 3,0,8,0 %; ! Error code literal GCT$K_DIAG_ST_NA = 1; ! literal GCT$K_DIAG_ST_PASSED = 1; ! literal GCT$K_DIAG_ST_RSRVD_03_31 = -4; ! ! ! System Resource Configuration Subpacket header format ! literal gct$S_gct_subpack = 16; macro gct$iw_subpack_length = 0,0,16,0 %; ! Length macro gct$iw_subpack_class = 2,0,16,0 %; ! Class macro gct$iw_subpack_type = 4,0,16,0 %; ! Type macro gct$iw_subpack_rev = 6,0,16,0 %; ! Revision macro gct$il_subpack_diag_flags = 8,0,32,0 %; macro gct$il_subpack_diag_failure = 12,0,32,0 %; ! ! Subpacket TYPE codes for CLASS 1 ( System Resource Conf Subpackets ) ! literal GCT$K_SUBPACK_UNUSED_1 = 1; ! Used to be SYSTEM_PLATFORM literal GCT$K_SUBPACK_PROCESSOR = 2; ! Processor literal GCT$K_SUBPACK_MEMORY = 3; ! Memory literal GCT$K_SUBPACK_SYS_BUS_BRIDGE = 4; ! literal GCT$K_SUBPACK_PCI_DEVICE = 5; ! literal GCT$K_SUBPACK_UNUSED_6 = 6; ! literal GCT$K_SUBPACK_CACHE = 7; ! literal GCT$K_SUBPACK_POWER = 8; ! literal GCT$K_SUBPACK_COOLING = 9; ! literal GCT$K_SUBPACK_SYS_INIT_LOG = 10; ! literal GCT$K_SUBPACK_UNUSED_11 = 11; ! literal GCT$K_SUBPACK_UNUSED_12 = 12; ! literal GCT$K_SUBPACK_VME = 13; ! literal GCT$K_SUBPACK_SBB = 14; ! literal GCT$K_SUBPACK_IOP = 15; ! literal GCT$K_SUBPACK_HOSE = 16; ! literal GCT$K_SUBPACK_BUS = 17; ! literal GCT$K_SUBPACK_ISA_DEVICE = 18; ! literal GCT$K_SUBPACK_USB_DEVICE = 19; ! literal GCT$K_SUBPACK_CONSOLE = 20; ! literal GCT$K_SUBPACK_POWER_ENVIR = 21; ! literal GCT$K_SUBPACK_UNUSED_22 = 22; ! literal GCT$K_SUBPACK_UNUSED_23 = 23; ! literal GCT$K_SUBPACK_UNUSED_24 = 24; ! literal GCT$K_SUBPACK_UNUSED_25 = 25; ! literal GCT$K_SUBPACK_UNUSED_26 = 26; ! literal GCT$K_SUBPACK_UNUSED_27 = 27; ! literal GCT$K_SUBPACK_UNUSED_28 = 28; ! literal GCT$K_SUBPACK_UNUSED_29 = 29; ! literal GCT$K_SUBPACK_PCI_VPD = 30; ! literal GCT$K_SUBPACK_SMB = 31; ! literal GCT$K_SUBPACK_FIBRECHANNEL = 32; ! literal GCT$K_SUBPACK_AGP = 33; ! literal GCT$K_SUBPACK_IDE = 34; ! literal GCT$K_SUBPACK_SCSI = 35; ! literal GCT$K_SUBPACK_1394 = 36; ! literal GCT$K_SUBPACK_SUPER_HIPPI = 37; ! literal GCT$K_SUBPACK_MEMORY_DIR = 38; ! literal GCT$K_SUBPACK_NUMA_PORT = 39; ! literal GCT$K_SUBPACK_NUMA_SWITCH = 40; ! literal GCT$K_SUBPACK_RMC = 41; ! literal GCT$K_SUBPACK_SENSOR = 42; ! literal GCT$K_SUBPACK_LAST = 43; ! ! ! CPU Resource subpacket ( Class 1 Type 2 ) ! literal gct$S_subpkt_cpu_fru5 = 96; macro gct$r_cpu_sub = 0,0,0,0 %; literal gct$s_cpu_sub = 16; macro gct$il_cpu_id = 16,0,32,0 %; macro gct$il_cpu_family = 20,0,32,0 %; macro gct$iq_cpu_state = 24,0,0,0 %; literal gct$s_cpu_state = 8; macro gct$iq_cpu_ovms_palcode_rev = 32,0,0,0 %; literal gct$s_cpu_ovms_palcode_rev = 8; macro gct$iq_cpu_dunix_palcode_rev = 40,0,0,0 %; literal gct$s_cpu_dunix_palcode_rev = 8; macro gct$iq_cpu_wnt_palcode_rev = 48,0,0,0 %; literal gct$s_cpu_wnt_palcode_rev = 8; macro gct$iq_cpu_alpha_type = 56,0,0,0 %; literal gct$s_cpu_alpha_type = 8; macro gct$iq_cpu_variation = 64,0,0,0 %; literal gct$s_cpu_variation = 8; macro gct$r_cpu_manufacturer = 72,0,0,0 %; literal gct$s_cpu_manufacturer = 8; macro gct$r_cpu_serial_number = 80,0,0,0 %; literal gct$s_cpu_serial_number = 8; macro gct$r_cpu_revision_level = 88,0,0,0 %; literal gct$s_cpu_revision_level = 8; ! ! MEMORY Resouce subpacket ( Class 1 Type 3) ! literal gct$S_subpkt_mem_fru5 = 32; macro gct$r_mem_sub = 0,0,0,0 %; literal gct$s_mem_sub = 16; macro gct$iq_mem_id = 16,0,0,0 %; literal gct$s_mem_id = 8; macro gct$il_mem_register_count = 28,0,32,0 %; ! ! BUSBRIDGE Resouce subpacket ( Class 1 Type 4) ! literal gct$S_subpkt_bridge_fru5 = 32; macro gct$r_bridge_sub = 0,0,0,0 %; literal gct$s_bridge_sub = 16; macro gct$iw_bridge_level = 16,0,16,0 %; macro gct$iw_bridge_type = 18,0,16,0 %; macro gct$il_bridge_register_count = 20,0,32,0 %; macro gct$iq_bridge_physical_addr = 24,0,0,0 %; literal gct$s_bridge_physical_addr = 8; literal GCT$K_BRIDGE_LVL_PRIMARY = 1; literal GCT$K_BRIDGE_LVL_SECONDARY = 2; literal GCT$K_BRIDGE_LVL_TERTIARY = 3; literal GCT$K_BRIDGE_TYPE_HOSE = 1; literal GCT$K_BRIDGE_TYPE_PCI = 2; literal GCT$K_BRIDGE_TYPE_XMI = 3; literal GCT$K_BRIDGE_TYPE_FBUS = 4; literal GCT$K_BRIDGE_TYPE_VME = 5; literal GCT$K_BRIDGE_TYPE_ISA = 6; literal GCT$K_BRIDGE_TYPE_LAST = 7; ! ! PCI Resouce subpacket ( Class 1 Type 5) ! literal gct$S_subpkt_pci_fru5 = 88; macro gct$r_pci_sub = 0,0,0,0 %; literal gct$s_pci_sub = 16; macro gct$iq_pci_config_addr = 16,0,0,0 %; literal gct$s_pci_config_addr = 8; macro gct$iq_pci_config_head0 = 24,0,0,0 %; literal gct$s_pci_config_head0 = 8; macro gct$iq_pci_config_head1 = 32,0,0,0 %; literal gct$s_pci_config_head1 = 8; macro gct$iq_pci_config_head2 = 40,0,0,0 %; literal gct$s_pci_config_head2 = 8; macro gct$iq_pci_config_head3 = 48,0,0,0 %; literal gct$s_pci_config_head3 = 8; macro gct$iq_pci_config_head4 = 56,0,0,0 %; literal gct$s_pci_config_head4 = 8; macro gct$iq_pci_config_head5 = 64,0,0,0 %; literal gct$s_pci_config_head5 = 8; macro gct$iq_pci_config_head6 = 72,0,0,0 %; literal gct$s_pci_config_head6 = 8; macro gct$iq_pci_config_head7 = 80,0,0,0 %; literal gct$s_pci_config_head7 = 8; ! ! Cache Resouce subpacket ( Class 1 Type 7 ) ! literal gct$S_subpkt_cache_fru5 = 32; macro gct$r_cache_sub = 0,0,0,0 %; literal gct$s_cache_sub = 16; macro gct$iw_cache_level = 16,0,16,0 %; macro gct$iw_cache_speed = 18,0,16,0 %; macro gct$iw_cache_size = 20,0,16,0 %; macro gct$iw_cache_size_avail = 22,0,16,0 %; macro gct$iw_cache_wp = 24,0,16,0 %; macro gct$iw_cache_ec = 26,0,16,0 %; macro gct$iw_cache_type = 28,0,16,0 %; macro gct$iw_cache_state = 30,0,16,0 %; ! ! CACHE types ! literal GCT$K_CACHE_OTHER = 1; ! literal GCT$K_CACHE_UNKNOWN = 2; ! literal GCT$K_CACHE_LVL_PRIMARY = 3; ! 1st level literal GCT$K_CACHE_LVL_SECONDARY = 4; ! 2nd level literal GCT$K_CACHE_LVL_TERTIARY = 5; ! 3rd level literal GCT$K_CACHE_LAST = 6; ! literal GCT$K_CACHE_WP_WRITEBACK = 3; literal GCT$K_CACHE_WP_WRITETHROUGH = 4; literal GCT$K_CACHE_WP_LATEWRITE = 5; literal GCT$K_CACHE_EC_NONE = 3; literal GCT$K_CACHE_EC_PARITY = 4; literal GCT$K_CACHE_EC_SINGLEBITECC = 5; literal GCT$K_CACHE_EC_MULTIBITECC = 6; literal GCT$K_CACHE_TYPE_INSTRUCTION = 3; literal GCT$K_CACHE_TYPE_DATA = 4; literal GCT$K_CACHE_TYPE_UNIFIED = 5; literal GCT$K_CACHE_STAT_ENABLED = 3; literal GCT$K_CACHE_STAT_DISABLED = 4; literal GCT$K_CACHE_STAT_NOTAPPLY = 5; ! ! Power Resouce subpacket ( Class 1 Type 8 ) ! literal gct$S_subpkt_power_fru5 = 32; macro gct$r_power_sub = 0,0,0,0 %; literal gct$s_power_sub = 16; macro gct$il_power_fru_count = 16,0,32,0 %; macro gct$il_power_fru = 20,0,32,0 %; macro gct$iw_power_type = 24,0,16,0 %; macro gct$iw_power_id = 26,0,16,0 %; macro gct$il_power_status = 28,0,32,0 %; literal GCT$K_POWER_PS_TYPE_DC = 1; literal GCT$K_POWER_PS_TYPE_AC = 2; literal GCT$K_POWER_PS_TYPE_GNDCUR = 3; literal GCT$K_POWER_PS_TYPE_BBU = 4; literal GCT$K_POWER_PS_TYPE_UPS = 5; ! ! Cooling Resouce subpacket ( Class 1 Type 9 ) ! literal gct$S_subpkt_cooling_fru5 = 32; macro gct$r_cooling_sub = 0,0,0,0 %; literal gct$s_cooling_sub = 16; macro gct$il_cooling_fru_count = 16,0,32,0 %; macro gct$il_cooling_fru = 20,0,32,0 %; macro gct$iw_cooling_type = 24,0,16,0 %; macro gct$iw_cooling_id = 26,0,16,0 %; macro gct$il_cooling_status = 28,0,32,0 %; ! ! Bus Resouce subpacket ( Class 1 Type 17 ) ! literal gct$S_subpkt_bus_fru5 = 32; macro gct$r_bus_sub = 0,0,0,0 %; literal gct$s_bus_sub = 16; macro gct$iq_bus_id = 16,0,0,0 %; literal gct$s_bus_id = 8; macro gct$il_bus_register_count = 28,0,32,0 %; ! ! CSL Resouce subpacket ( Class 1 Type 20 ) ! literal gct$S_subpkt_csl_fru5 = 56; macro gct$r_csl_sub = 0,0,0,0 %; literal gct$s_csl_sub = 16; macro gct$il_csl_reset_reason = 16,0,32,0 %; macro gct$il_csl_ev_count = 20,0,32,0 %; macro gct$r_csl_srm_part_number = 24,0,0,0 %; literal gct$s_csl_srm_part_number = 8; macro gct$r_csl_srm_rev = 32,0,0,0 %; literal gct$s_csl_srm_rev = 8; macro gct$r_csl_alphabios_part_number = 40,0,0,0 %; literal gct$s_csl_alphabios_part_number = 8; macro gct$r_csl_alphabios_rev = 48,0,0,0 %; literal gct$s_csl_alphabios_rev = 8; literal GCT$K_CSL_UNKNOWN_RESET = 0; literal GCT$K_CSL_SOFT_RESET = 2; literal GCT$K_CSL_HARD_RESET = 4; literal GCT$K_CSL_OCP_RESET = 8; literal GCT$K_CSL_REMOTE_RESET = 16; ! ! PCI VPD Resouce subpacket ( Class 1 Type 30 ) ! literal gct$S_subpkt_vpd_fru5 = 80; macro gct$r_vpd_sub = 0,0,0,0 %; literal gct$s_vpd_sub = 16; macro gct$iq_vpd_load_id = 16,0,0,0 %; literal gct$s_vpd_load_id = 8; macro gct$iq_vpd_rom_level = 24,0,0,0 %; literal gct$s_vpd_rom_level = 8; macro gct$iq_vpd_rom_rev = 32,0,0,0 %; literal gct$s_vpd_rom_rev = 8; macro gct$iq_vpd_net_addr = 40,0,0,0 %; literal gct$s_vpd_net_addr = 8; macro gct$iq_vpd_dev_driv_level = 48,0,0,0 %; literal gct$s_vpd_dev_driv_level = 8; macro gct$iq_vpd_diag_level = 56,0,0,0 %; literal gct$s_vpd_diag_level = 8; macro gct$iq_vpd_load_ucode_level = 64,0,0,0 %; literal gct$s_vpd_load_ucode_level = 8; macro gct$iq_vpd_bin_func_num = 72,0,0,0 %; literal gct$s_vpd_bin_func_num = 8; ! ! SMB Resouce subpacket ( Class 1 Type 31 ) ! literal gct$S_subpkt_smb_fru5 = 32; macro gct$r_smb_sub = 0,0,0,0 %; literal gct$s_smb_sub = 16; macro gct$iq_smb_id = 16,0,0,0 %; literal gct$s_smb_id = 8; macro gct$il_smb_register_count = 28,0,32,0 %; ! ! RMC Resouce subpacket ( Class 1 Type 41 ) ! literal gct$S_subpkt_rmc_fru5 = 32; macro gct$r_rmc_sub = 0,0,0,0 %; literal gct$s_rmc_sub = 16; macro gct$iq_rmc_id = 16,0,0,0 %; literal gct$s_rmc_id = 8; macro gct$il_rmc_pic_hw_rev = 24,0,32,0 %; macro gct$il_rmc_pic_fw_rev = 28,0,32,0 %; ! ! SENSOR Resouce subpacket ( Class 1 Type 42 ) ! literal gct$m_sensor_prop_status = %X'1'; literal gct$m_sensor_prop_value = %X'2'; literal gct$m_sensor_prop_writeable = %X'4'; literal gct$m_sensor_prop_bitfield = %X'8'; literal gct$m_sensor_prop_fill = %X'FFFFFFF0'; literal gct$S_subpkt_sensor_fru5 = 40; macro gct$r_sensor_sub = 0,0,0,0 %; literal gct$s_sensor_sub = 16; macro gct$il_sensor_fru_count = 16,0,32,0 %; macro gct$il_sensor_fru_offset = 20,0,32,0 %; macro gct$iq_sensor_console_id = 24,0,0,0 %; literal gct$s_sensor_console_id = 8; macro gct$il_sensor_console_id = 24,0,32,0 %; macro gct$il_sensor_bitfield = 28,0,32,0 %; macro gct$il_sensor_class = 32,0,32,0 %; macro gct$il_sensor_prop = 36,0,32,0 %; ! Sensor properties macro gct$v_sensor_prop_status = 36,0,1,0 %; macro gct$v_sensor_prop_value = 36,1,1,0 %; macro gct$v_sensor_prop_writeable = 36,2,1,0 %; macro gct$v_sensor_prop_bitfield = 36,3,1,0 %; literal GCT$K_SENSOR_CLASS_FAN = 1; literal GCT$K_SENSOR_CLASS_TEMPERATURE = 2; literal GCT$K_SENSOR_CLASS_AC = 3; literal GCT$K_SENSOR_CLASS_DC = 4; literal GCT$K_SENSOR_CLASS_BATTERY = 5; ! ! Define the header extension structure. Offset to by hd_extension ! in the common header. If zero, no extended header information is ! present for the node. ! literal gct$S_gct_hd_ext = 16; macro gct$il_hd_ext_fru_count = 0,0,32,0 %; macro gct$il_hd_ext_fru = 4,0,32,1 %; macro gct$il_hd_ext_subpkt_count = 8,0,32,0 %; macro gct$il_hd_ext_subpkt_offset = 12,0,32,0 %; literal GCT$K_NODE_HARDWARE = 1; literal GCT$K_NODE_HOTSWAP = 2; literal GCT$K_NODE_UNAVAILABLE = 4; literal GCT$K_NODE_HW_TEMPLATE = 8; literal GCT$K_NODE_INITIALIZED = 16; literal GCT$K_NODE_CPU_PRIMARY = 32; literal GCT$K_NODE_IN_CONSOLE = 64; literal GCT$K_NODE_RSRVD_7_31 = -128; !*** MODULE gconoutdef IDENT X-2 *** ! ! Copyright © 2006 Hewlett-Packard Development Company, L.P. ! ! Confidential computer software. Valid license from HP and/or ! its subsidiaries required for possession, use, or copying. ! ! Consistent with FAR 12.211 and 12.212, Commercial Computer Software, ! Computer Software Documentation, and Technical Data for Commercial ! Items are licensed to the U.S. Government under vendor's standard ! commercial license. ! ! Neither HP nor any of its subsidiaries shall be liable for technical ! or editorial errors or omissions contained herein. The information ! in this document is provided "as is" without warranty of any kind and ! is subject to change without notice. The warranties for HP products ! are set forth in the express limited warranty statements accompanying ! such products. Nothing herein should be construed as constituting an ! additional warranty. ! ! ABSTRACT: ! ! This module describes the data structure for the generic ! graphics console for IA64 ! ! AUTHOR: ! ! Fred Kleinsorge, May 2006 ! ! MODIFIED BY: ! ! X-2 FGK0929-01 Fred Kleinsorge 29-Sep-2006 ! Add busy indication, and get rid of VISIBLE bit - it isn't ! being used on IA64 (HW_READY is always set/cleared at the ! same time). ! ! X-1 FGK Fred Kleinsorge 28-Sep-2006 ! Initial entry. ! literal GCON$K_MAGIC = 136911190; ! Magic number literal GCON$K_NO_DRIVER = 0; ! No driver init literal GCON$K_BOOT_DRIVER = 1; ! Boot driver literal GCON$K_EXEC_DRIVER = 2; ! Exec driver literal GCON$K_GRAPHICS_DRIVER = 3; ! Graphics driver literal GCON$M_INHIBIT = %X'1'; literal GCON$M_HW_READY = %X'2'; literal GCON$M_CURSOR_ENABLED = %X'4'; literal GCON$M_CURSOR_DISPLAYED = %X'8'; literal GCON$M_STATUS_LINE = %X'10'; literal GCON$M_STATUS_WS_SELECT = %X'20'; literal GCON$M_VT52_GRAPHICS = %X'40'; literal GCON$M_VT52_MODE = %X'80'; literal GCON$M_VT100_GRAPHICS = %X'100'; literal GCON$M_VT100_MODE = %X'200'; literal GCON$K_NO_STATUS = 0; ! No status line literal GCON$K_BOOT_STATUS = 1; ! Boot driver status line literal GCON$K_WINDOW_STATUS = 2; ! Graphics driver status line literal GCON$K_EXEC_STATUS = 3; ! Execlet status line literal GCON$K_LENGTH = 25480; literal GCON$K_DEF_WIDTH = 80; literal GCON$K_DEF_HEIGHT = 24; literal GCON$K_MAX_WIDTH = 132; literal GCON$K_MAX_HEIGHT = 44; literal GCON$K_MINOR_VERSION = 1; literal GCON$K_MAJOR_VERSION = 1; literal GCON$S_GCON = 25480; macro GCON$L_VERSION = 0,0,32,0 %; ! Block version # macro GCON$L_LENGTH = 4,0,32,1 %; ! Block length macro GCON$L_VALID = 8,0,32,1 %; ! Structure valid when equal to MAGIC macro GCON$L_ERROR = 12,0,32,1 %; ! Error macro GCON$L_DRIVER = 16,0,32,1 %; ! Which driver last initialized address data macro GCON$L_FLAGS = 20,0,32,1 %; ! Flags word macro GCON$V_INHIBIT = 20,0,1,0 %; ! Inhibit HW output to console macro GCON$V_HW_READY = 20,1,1,0 %; ! HW ready macro GCON$V_CURSOR_ENABLED = 20,2,1,0 %; ! Cursor enabled macro GCON$V_CURSOR_DISPLAYED = 20,3,1,0 %; ! Cursor is displayed macro GCON$V_STATUS_LINE = 20,4,1,0 %; ! Status line enabled macro GCON$V_STATUS_WS_SELECT = 20,5,1,0 %; ! Select Window System status line macro GCON$V_VT52_GRAPHICS = 20,6,1,0 %; ! VT52 graphic character set... macro GCON$V_VT52_MODE = 20,7,1,0 %; ! Recognize VT52 escape sequences macro GCON$V_VT100_GRAPHICS = 20,8,1,0 %; ! VT100 graphic character set... macro GCON$V_VT100_MODE = 20,9,1,0 %; ! Recognize VT100 escape sequences macro GCON$L_COLUMN = 24,0,32,1 %; ! Console X position macro GCON$L_ROW = 28,0,32,1 %; ! Console Y position macro GCON$L_WIDTH = 32,0,32,1 %; ! Console width (chars) macro GCON$L_HEIGHT = 36,0,32,1 %; ! Console height (chars) macro GCON$L_VT52_ESCAPE = 40,0,32,0 %; ! VT52 Escape sequence type ! ! Video text attributes ! macro GCON$L_ATTRIBUTES = 44,0,32,0 %; ! Video attributes macro GCON$L_ATTR_NORMAL = 48,0,32,0 %; ! Normal text macro GCON$L_ATTR_CURRENT = 52,0,32,0 %; ! Current attributes macro GCON$L_TEXT = 56,0,32,0 %; ! Normal Text Color (0xBBGGRR00) macro GCON$L_BACK = 60,0,32,0 %; ! Normal Background Color (0xBBGGRR00) macro GCON$L_TEXT_COLOR = 64,0,32,1 %; ! Text color in ANSI format (30-37) macro GCON$L_TEXT_BACK = 68,0,32,1 %; ! Text background color in ANSI format (40-47) ! ! ! macro GCON$L_ERROR_CHAR = 72,0,32,1 %; ! Error character ! ! Force quadword alignment! ! ! ! ! macro GCON$Q_DEVICE_DEPENDENT = 80,0,0,1 %; literal GCON$S_DEVICE_DEPENDENT = 8; macro GCON$A_DEVICE_DEPENDENT = 80,0,32,1 %; ! Pointer to device dependent extension ! ! ! macro GCON$Q_WINDOW_DATA = 88,0,0,1 %; literal GCON$S_WINDOW_DATA = 8; macro GCON$A_WINDOW_DATA = 88,0,32,1 %; ! Pointer to runtime window context ! ! Public entry for OPDRIVER style call ! ! PUTC(char *string, int length, UCB* pUCB, int *ret_len) ! macro GCON$Q_CONOUT = 96,0,0,1 %; literal GCON$S_CONOUT = 8; macro GCON$A_CONOUT = 96,0,32,1 %; ! Output a string ! ! This is the GCON version... ! ! PUT_STRING(GCON, char *string, int length) ! macro GCON$Q_PUT_STRING = 104,0,0,1 %; literal GCON$S_PUT_STRING = 8; macro GCON$A_PUT_STRING = 104,0,32,1 %; ! Output a string ! ! Device dependent action routines for drawing to the graphics device. ! macro GCON$Q_DRAW_STRING = 112,0,0,1 %; literal GCON$S_DRAW_STRING = 8; macro GCON$A_DRAW_STRING = 112,0,32,1 %; ! Draw string routine macro GCON$Q_DRAW_DEV_SEGMENT = 120,0,0,1 %; literal GCON$S_DRAW_DEV_SEGMENT = 8; macro GCON$A_DRAW_DEV_SEGMENT = 120,0,32,1 %; ! Draw string routine macro GCON$Q_ERASE_DEV_SEGMENT = 128,0,0,1 %; literal GCON$S_ERASE_DEV_SEGMENT = 8; macro GCON$A_ERASE_DEV_SEGMENT = 128,0,32,1 %; ! Draw string routine macro GCON$Q_DRAW_CHAR = 136,0,0,1 %; literal GCON$S_DRAW_CHAR = 8; macro GCON$A_DRAW_CHAR = 136,0,32,1 %; ! Draw a character macro GCON$Q_READ_CHAR = 144,0,0,1 %; literal GCON$S_READ_CHAR = 8; macro GCON$A_READ_CHAR = 144,0,32,1 %; ! Read a char from the display macro GCON$Q_CLEAR_BACKGROUND = 152,0,0,1 %; literal GCON$S_CLEAR_BACKGROUND = 8; macro GCON$A_CLEAR_BACKGROUND = 152,0,32,1 %; ! Clear the entire console macro GCON$Q_REDRAW_SCREEN = 160,0,0,1 %; literal GCON$S_REDRAW_SCREEN = 8; macro GCON$A_REDRAW_SCREEN = 160,0,32,1 %; ! Redraw screen from backing store macro GCON$Q_SELECT_CONSOLE = 168,0,0,1 %; literal GCON$S_SELECT_CONSOLE = 8; macro GCON$A_SELECT_CONSOLE = 168,0,32,1 %; ! Device select macro GCON$Q_DESELECT_CONSOLE = 176,0,0,1 %; literal GCON$S_DESELECT_CONSOLE = 8; macro GCON$A_DESELECT_CONSOLE = 176,0,32,1 %; ! Device unselect macro GCON$Q_ENABLE_CONSOLE = 184,0,0,1 %; literal GCON$S_ENABLE_CONSOLE = 8; macro GCON$A_ENABLE_CONSOLE = 184,0,32,1 %; ! Device enable macro GCON$Q_DISABLE_CONSOLE = 192,0,0,1 %; literal GCON$S_DISABLE_CONSOLE = 8; macro GCON$A_DISABLE_CONSOLE = 192,0,32,1 %; ! Device disable macro GCON$Q_ERASE_ROW = 200,0,0,1 %; literal GCON$S_ERASE_ROW = 8; macro GCON$A_ERASE_ROW = 200,0,32,1 %; ! Clear a character row macro GCON$Q_SCROLL_UP = 208,0,0,1 %; literal GCON$S_SCROLL_UP = 8; macro GCON$A_SCROLL_UP = 208,0,32,1 %; ! Up scroll (linefeed) macro GCON$Q_SCROLL_DOWN = 216,0,0,1 %; literal GCON$S_SCROLL_DOWN = 8; macro GCON$A_SCROLL_DOWN = 216,0,32,1 %; ! Down scroll (reverse index) macro GCON$Q_DRAW_CURSOR = 224,0,0,1 %; literal GCON$S_DRAW_CURSOR = 8; macro GCON$A_DRAW_CURSOR = 224,0,32,1 %; ! Draw cursor macro GCON$Q_READ_CURSOR_POS = 232,0,0,1 %; literal GCON$S_READ_CURSOR_POS = 8; macro GCON$A_READ_CURSOR_POS = 232,0,32,1 %; ! Read the cursor position macro GCON$Q_ERASE_CURSOR = 240,0,0,1 %; literal GCON$S_ERASE_CURSOR = 8; macro GCON$A_ERASE_CURSOR = 240,0,32,1 %; ! Erase Cursor macro GCON$Q_SCROLL_BS_UP = 248,0,0,1 %; literal GCON$S_SCROLL_BS_UP = 8; macro GCON$A_SCROLL_BS_UP = 248,0,32,1 %; ! Up scroll (linefeed) macro GCON$Q_SCROLL_BS_DOWN = 256,0,0,1 %; literal GCON$S_SCROLL_BS_DOWN = 8; macro GCON$A_SCROLL_BS_DOWN = 256,0,32,1 %; ! Down scroll (reverse index) macro GCON$Q_DRAW_STRING_TO_BS = 264,0,0,1 %; literal GCON$S_DRAW_STRING_TO_BS = 8; macro GCON$A_DRAW_STRING_TO_BS = 264,0,32,1 %; ! Draw string routine macro GCON$Q_SAVE_SCREEN_TO_BS = 272,0,0,1 %; literal GCON$S_SAVE_SCREEN_TO_BS = 8; macro GCON$A_SAVE_SCREEN_TO_BS = 272,0,32,1 %; ! Save screen to BS macro GCON$Q_INIT_FONT = 280,0,0,1 %; literal GCON$S_INIT_FONT = 8; macro GCON$A_INIT_FONT = 280,0,32,1 %; ! Initialize font macro GCON$Q_LOAD_GLYPH = 288,0,0,1 %; literal GCON$S_LOAD_GLYPH = 8; macro GCON$A_LOAD_GLYPH = 288,0,32,1 %; ! Load a single glyph macro GCON$Q_SAVE_CONSOLE = 296,0,0,1 %; literal GCON$S_SAVE_CONSOLE = 8; macro GCON$A_SAVE_CONSOLE = 296,0,32,1 %; ! Save console state macro GCON$Q_RESTORE_CONSOLE = 304,0,0,1 %; literal GCON$S_RESTORE_CONSOLE = 8; macro GCON$A_RESTORE_CONSOLE = 304,0,32,1 %; ! Restore console state macro GCON$Q_REINIT_CONSOLE = 312,0,0,1 %; literal GCON$S_REINIT_CONSOLE = 8; macro GCON$A_REINIT_CONSOLE = 312,0,32,1 %; ! Do re-init sequence macro GCON$Q_SET_STATUS_LINE = 320,0,0,1 %; literal GCON$S_SET_STATUS_LINE = 8; macro GCON$A_SET_STATUS_LINE = 320,0,32,1 %; ! Set status line macro GCON$Q_SEND_INPUT = 328,0,0,1 %; literal GCON$S_SEND_INPUT = 8; macro GCON$A_SEND_INPUT = 328,0,32,1 %; ! Emulate input from terminal macro GCON$Q_SET_TEXT_ATTR = 336,0,0,1 %; literal GCON$S_SET_TEXT_ATTR = 8; macro GCON$A_SET_TEXT_ATTR = 336,0,32,1 %; ! Set color/bold/blink/etc macro GCON$L_RESERVED = 344,0,0,0 %; literal GCON$S_RESERVED = 128; ! Extra's macro GCON$L_BUSY = 472,0,32,1 %; ! Set/Cleared on entry to PUT_STRING ! ! Status line defaults ! macro GCON$L_STATUS_LINE_LEN = 476,0,32,1 %; ! Status line length macro GCON$B_STATUS_LINE = 480,0,0,1 %; literal GCON$S_STATUS_LINE = 132; ! Status line (0) macro GCON$L_STATUS_LINE_WS_LEN = 612,0,32,1 %; ! Status line length macro GCON$B_STATUS_LINE_WS = 616,0,0,1 %; literal GCON$S_STATUS_LINE_WS = 132; ! Status line (1) macro GCON$L_STATUS_LINE_ROW = 748,0,32,1 %; ! Status line row number macro GCON$L_ATTR_STATUS_LINE = 752,0,32,0 %; ! Status line attributes macro GCON$L_LINE_OFFSETS = 756,0,0,1 %; literal GCON$S_LINE_OFFSETS = 192; ! Offsets to line starts macro GCON$B_LINE_LENGTHS = 948,0,0,1 %; literal GCON$S_LINE_LENGTHS = 48; ! Length of each line ! ! Force quadword alignment! ! ! ! Each character position has space for the character attribute and the character ! macro GCON$L_LINE_DATA = 1000,0,0,1 %; literal GCON$S_LINE_DATA = 24480; ! Character array literal GFONT$S_GFONT = 1080; macro GFONT$l_width = 0,0,32,1 %; ! Glyph width macro GFONT$l_height = 4,0,32,1 %; ! Glyph height macro GFONT$l_byte_count = 8,0,32,1 %; ! Byte count macro GFONT$l_byte_width = 12,0,32,1 %; ! Byte width macro GFONT$l_fill_count = 16,0,32,1 %; ! fill count macro GFONT$l_fill_data = 20,0,32,1 %; ! fill data macro GFONT$l_char_count = 24,0,32,1 %; ! Number of characters macro GFONT$l_first_char = 28,0,32,1 %; ! First Character macro GFONT$l_error_character = 32,0,32,1 %; ! Error glyph index macro GFONT$ps_char_directory = 36,0,0,1 %; literal GFONT$s_char_directory = 1040; ! Array of glyph pointers !*** MODULE $GESDEF *** ! ++ ! Types of sensor data. ! -- literal GES$K_TEMP = 0; literal GES$K_POWER = 1; literal GES$K_FAN = 2; literal GES$K_TABLE_SIZE = 3; ! ++ ! An array of these data structures will be created to store information ! about the sensors. There will be one array for each of the sensor types, ! and in each array there will be one of these structures for each ! individual sensor. ! ! 63 55 47 39 31 23 15 7 0 ! +---------------------------------------------------------------+ ! | FRU Node ID from cfg$iq_cfg_id64 in CFGDEF.H | ! +---------------------------------------------------------------+ ! | Node Flags from cfg$iq_node_flags in CFGDEF.H | ! +-------------------------------+-------------------------------+ ! | Bitfield | Offset | ! +-------+-------+-------+-------+-------------------------------+ ! | Node Change | Sub- | Type | Sensor Properties | ! | Counter | type | | | ! +-------+-------+-------+-------+-------------------------------+ ! | Node Handle | ! +---------------------------------------------------------------+ ! | Subpacket Handle | ! +---------------------------------------------------------------+ ! -- literal GES$S_SENSOR_FRU = 48; ! ! The byte fields in this 8-byte structure are declared in CFGDEF.H as ! struct cfg$_cfg_node_id_fru_desc in the CFG_NODE structure. macro GES$Q_FRU_NODE_ID = 0,0,0,0 %; literal GES$S_FRU_NODE_ID = 8; ! ! The following quadword is the cfg$iq_node_flags field of the FRU ! CFG_NODE. This provides a lot of salient information about the FRU. macro GES$Q_NODE_FLAGS = 8,0,0,0 %; literal GES$S_NODE_FLAGS = 8; ! ! The following two fields comprise the 64-bit cfg$iq_sensor_console_id ! declared in CFGDEF.H. The console_id field provides unique ! identifier for each FRU node in the tree. ! ! <31:0> Offset to the data in the hardware's environmental storage ! medium. macro GES$L_OFFSET = 16,0,32,0 %; ! ! <63:32> Can be bitfield or offset to Value. macro GES$L_BITFIELD = 20,0,32,0 %; ! ! Property of the data (status or value or both). ! See Config Tree Spec, pp 9-105 macro GES$L_PROP = 24,0,32,0 %; ! ! Config Tree FRU Node Type. macro GES$B_TYPE = 28,0,8,0 %; ! ! Config Tree FRU Node Subtype. macro GES$B_SUBTYPE = 29,0,8,0 %; ! ! Config Tree Node Change Counter. macro GES$W_NODE_CHANGE_COUNTER = 30,0,16,0 %; ! ! Config Tree Node Handle. macro GES$Q_NODE_HANDLE = 32,0,0,1 %; literal GES$S_NODE_HANDLE = 8; ! ! Config Tree Subpacket Handle. macro GES$Q_SUBPKT_HANDLE = 40,0,0,1 %; literal GES$S_SUBPKT_HANDLE = 8; literal GES$K_SENSOR_FRU_LENGTH = 48; ! ++ ! This struct will be used to build a table of pointers to SENSOR_FRU arrays ! for each of the sensor types, and the corresponding information required ! to access and maintain each of the arrays. ! ! 63 31 15 0 ! +-------------------------------+-------------------------------+ ! | pointer to SENSOR_FRU array | Item Code | ! +-------------------------------+---------------+---------------+ ! | Required Buffer Size | Sensor Count | Array Valid | ! +-------------------------------+---------------+---------------+ ! | Last Init Time | ! +---------------------------------------------------------------+ ! -- literal GES$S_ENV_SENSOR = 24; ! ! This element will be used by code to lookup the correct ! entry in the table of ENV_SENSOR structs. macro GES$L_ITEM_CODE = 0,0,32,1 %; ! ! Array of SENSOR_FRU structs for all sensors of this type. macro GES$PS_SENSOR_FRU = 4,0,32,1 %; ! ! This boolean will be used to determine if the SENSOR_FRU ! array is inited and valid. macro GES$W_ARRAY_INITED = 8,0,16,0 %; ! ! Count of sensors of this type. macro GES$W_SENSOR_COUNT = 10,0,16,1 %; ! ! Size of buffer required to contain all data, formatted as an array ! of ESFITEM, from all sensors of this type (see esfdef.h). macro GES$L_REQ_BUFF_SIZE = 12,0,32,1 %; ! ! The system time of the last init of the SENSOR_FRU array. macro GES$Q_LAST_INIT_TIME = 16,0,0,0 %; literal GES$S_LAST_INIT_TIME = 8; literal GES$K_ENV_SENSOR_LENGTH = 24; !*** MODULE $GLXDEF *** ! ! values for memory types ! literal GLX$C_PRIVATE = 1; literal GLX$C_SHARED = 2; literal GLX$C_IO = 3; literal GLX$C_UNOWNED = 4; ! ! Shared Memory CPP page allocation flags. ! literal GLX$M_SHM_CPP_LARGEST = %X'1'; literal GLX$M_SHM_CPP_RESERVED = %X'FFFFFFFE'; literal GLX$S_SHM_CPP_ALLOC = 4; macro GLX$L_SHM_CPP_ALLOC_FLAGS = 0,0,32,0 %; ! Shared memory CPP allocation flags macro GLX$V_SHM_CPP_LARGEST = 0,0,1,0 %; ! Allocate largest group found macro GLX$V_SHM_CPP_RESERVED = 0,1,31,0 %; literal GLX$S_SHM_CPP_RESERVED = 31; ! ! Shared Memory CPP page list IDs. ! literal GLX$C_FREE_LIST = 1; ! Free page list literal GLX$C_BAD_LIST = 2; ! Bad page list literal GLX$C_UNTESTED_LIST = 3; ! Untested page list ! ! Shared Memory Region callback routine reasons ! literal GLX$C_INIT = 1; ! This node is the creator of the shared memory region. literal GLX$C_ATTACH = 2; ! A gNode has attached to this SHM_REG. literal GLX$C_DETACH = 3; ! A gNode has deatched from this SHM_REG. literal GLX$C_GNODE_CRASH = 4; ! A gNode has detached because of a system crash. literal GLX$C_SHUTDOWN = 5; ! The local gNode is shutting down, the SHM_REG must be detached from. literal GLX$C_MEM_ERROR = 6; ! A memory error has occured, the SHM_REG must be detached from. ! ! Shared memory region tag max length ! literal GLX$C_SHM_TAG_MAX_LENGTH = 63; ! ! Shared Memory Info Functions ! literal GLX$M_WILDCARD_LOOKUP = %X'1'; literal GLX$M_TAG_LOOKUP = %X'2'; literal GLX$M_SHM_ID_LOOKUP = %X'4'; literal GLX$M_SHMEM_INFO_RESERVED = %X'FFFFFFF8'; literal GLX$S_SHMEM_INFO = 4; macro GLX$L_SHMEM_INFO_FLAGS = 0,0,32,0 %; macro GLX$V_WILDCARD_LOOKUP = 0,0,1,0 %; ! Wildcard lookup macro GLX$V_TAG_LOOKUP = 0,1,1,0 %; ! Look up region by tag macro GLX$V_SHM_ID_LOOKUP = 0,2,1,0 %; ! Look up region by ID macro GLX$V_SHMEM_INFO_RESERVED = 0,3,29,0 %; literal GLX$S_SHMEM_INFO_RESERVED = 29; ! ! Shared Memory Flags ! literal GLX$M_SHM_REG_VALID = %X'1'; literal GLX$M_GLOBAL_SECTION = %X'2'; literal GLX$M_SHM_REG_ATTACHED = %X'4'; literal GLX$M_SHM_CPP_VALID = %X'8'; literal GLX$M_SHM_CPP_CONNECTED = %X'10'; literal GLX$M_SHM_REG_SHARED_CONTEXT = %X'20'; literal GLX$M_SYS_VA_VALID = %X'40'; literal GLX$M_ATTACH_DETACH_NOTIFY = %X'80'; literal GLX$M_SHMEM_FLAGS_RESERVED = %X'FFFFFF00'; literal GLX$S_SHMEM_FLAGS = 4; macro GLX$L_SHMEM_FLAGS = 0,0,32,0 %; macro GLX$V_SHM_REG_VALID = 0,0,1,0 %; ! Shared memory region is valid macro GLX$V_GLOBAL_SECTION = 0,1,1,0 %; ! This region is associated with a global section macro GLX$V_SHM_REG_ATTACHED = 0,2,1,0 %; ! Local node is attached to the shared memory region macro GLX$V_SHM_CPP_VALID = 0,3,1,0 %; ! Shared memory region is valid macro GLX$V_SHM_CPP_CONNECTED = 0,4,1,0 %; ! Local node is connected to the shared memory CPP macro GLX$V_SHM_REG_SHARED_CONTEXT = 0,5,1,0 %; ! Shared memory region context variable is the same for all nodes macro GLX$V_SYS_VA_VALID = 0,6,1,0 %; ! This region is mapped in system space macro GLX$V_ATTACH_DETACH_NOTIFY = 0,7,1,0 %; ! Region callback routine is called when nodes attach and detach macro GLX$V_SHMEM_FLAGS_RESERVED = 0,8,24,0 %; literal GLX$S_SHMEM_FLAGS_RESERVED = 24; ! ! Bit definitions for GLX$GL_SYSTEM_FEATURES ! literal GLX$M_HW_PARTITIONABLE = %X'1'; literal GLX$M_CPU_MIGRATE = %X'2'; literal GLX$M_MEMORY_RECONFIG = %X'4'; literal GLX$M_SHARED_MEMORY = %X'8'; literal GLX$M_CONSOLE_EMULATION = %X'10'; literal GLX$M_GCT_EMULATION = %X'20'; literal GLX$M_SYSTEM_FEATURES_RSRVD = %X'FFFFFFC0'; literal GLX$S_SYSTEM_FEATURES_FLAGS = 4; macro GLX$V_HW_PARTITIONABLE = 0,0,1,0 %; macro GLX$V_CPU_MIGRATE = 0,1,1,0 %; macro GLX$V_MEMORY_RECONFIG = 0,2,1,0 %; macro GLX$V_SHARED_MEMORY = 0,3,1,0 %; macro GLX$V_CONSOLE_EMULATION = 0,4,1,0 %; ! Console does not support Galaxy callbacks macro GLX$V_GCT_EMULATION = 0,5,1,0 %; ! GCT is file based macro GLX$V_SYSTEM_FEATURES_RSRVD = 0,6,26,0 %; literal GLX$S_SYSTEM_FEATURES_RSRVD = 26; ! ! Config tree compatibility type values ! literal GLX$C_CFG_COMPAT_V5 = 0; ! The config tree is compatible with Version 5 trees literal GLX$C_CFG_COMPAT_V6 = 1; ! The config tree is compatible with Version 6.0 trees literal GLX$C_CFG_COMPAT_UNKNOWN = -1; ! The config tree is not compatible with either version literal GLX$C_CFG_COMPAT_NOTREE = -2; ! There is no valid config tree !*** MODULE $GPSCFGDEF *** ! *********************************************** ! CONSTANTS AND ENUMERATIONS ! *********************************************** ! ! Discoverable SBA Objects ! ------------------------ ! literal GPS$K_OBJ_GENERIC = 0; literal GPS$K_OBJ_SYSBUS = 17; literal GPS$K_OBJ_PCIHOST = 18; literal GPS$K_OBJ_PCIDEV = 19; literal GPS$K_OBJ_IOPORT = 20; literal GPS$K_OBJ_IOPORTDEV = 21; literal GPS$K_OBJ_HCDPDEV = 22; literal GPS$K_OBJ_EMBEDDED = 23; literal GPS$K_OBJ_IOC = 24; literal GPS$K_OBJ_SYSBUSLESS = 25; literal GPS$K_OBJ_ROOT = 26; literal GPS$K_OBJ_CONTAINER = 27; literal GPS$K_OBJ_GPEDEV = 28; ! ! Address Spaces ! -------------- ! See Generic Address Specification (GAS) in ACPI 2.0a Spec. ! literal GPS$K_SPACE_SYSMEM = 0; literal GPS$K_SPACE_SYSIO = 1; literal GPS$K_SPACE_PCICFG = 2; literal GPS$K_SPACE_EMBEDDED = 3; literal GPS$K_SPACE_SMB = 4; literal GPS$K_SPACE_FIXEDHW = 127; ! ! ! *********************************************** ! DATA STRUCTURES ! *********************************************** ! ! PRT - PCI Routing Table ! ----------------------- ! The PRT provides the information required to locate the interrupt ! wire for the corresponding PCI device. ! literal GPS_PRT$S_GPSPRTENTRY = 24; macro GPS_PRT$l_entry_length = 0,0,32,0 %; macro GPS_PRT$l_pin = 4,0,32,0 %; macro GPS_PRT$Q_ADDRESS = 8,0,0,0 %; literal GPS_PRT$S_ADDRESS = 8; macro GPS_PRT$l_source_index = 16,0,32,0 %; literal GPS$K_PRT_LENGTH = 24; ! ! ! GPS DESCRIPTOR ! -------------- ! literal GPS_DSC$S_GPSDESCRIPTOR = 16; macro GPS_DSC$l_type = 0,0,32,0 %; ! See ACPI OBJECT Types above macro GPS_DSC$l_size = 4,0,32,0 %; ! Size in bytes of the data object macro GPS_DSC$q_data = 8,0,0,0 %; literal GPS_DSC$s_data = 8; ! for GPS$K_OBJ_TYPE_INTEGER macro GPS_DSC$ps_data = 8,0,32,1 %; ! for types other than INTEGER ! ! GPS Header ! ---------- ! This structure is common to all GPSCONFIG type structures and ! contains the fields necessary to extract more information about ! the object from ACPI. Also contains fields that are common to ! most hardware objects. ! literal GPS_HDR$m_valid_sta = %X'1'; literal GPS_HDR$m_valid_adr = %X'2'; literal GPS_HDR$m_valid_hid = %X'4'; literal GPS_HDR$m_valid_uid = %X'8'; literal GPS_HDR$m_valid_cid = %X'10'; literal GPS_HDR$m_resrv_0 = %X'E0'; literal GPS_HDR$m_valid_bbn = %X'100'; literal GPS_HDR$m_valid_seg = %X'200'; literal GPS_HDR$S_GPSHEADER = 112; macro GPS_HDR$l_status = 0,0,32,1 %; ! Callback Status macro GPS_HDR$l_valid = 4,0,32,0 %; macro GPS_HDR$v_valid_sta = 4,0,1,0 %; ! These masks track the macro GPS_HDR$v_valid_adr = 4,1,1,0 %; ! : corresponding ones in macro GPS_HDR$v_valid_hid = 4,2,1,0 %; ! : [ACPI]ACTYPES.H macro GPS_HDR$v_valid_uid = 4,3,1,0 %; macro GPS_HDR$v_valid_cid = 4,4,1,0 %; macro GPS_HDR$v_resrv_0 = 4,5,3,0 %; literal GPS_HDR$s_resrv_0 = 3; macro GPS_HDR$v_valid_bbn = 4,8,1,0 %; macro GPS_HDR$v_valid_seg = 4,9,1,0 %; macro GPS_HDR$q_type = 8,0,0,0 %; literal GPS_HDR$s_type = 8; ! Object type macro GPS_HDR$q_hw_handle = 16,0,0,0 %; literal GPS_HDR$s_hw_handle = 8; ! Object's hardware handle macro GPS_HDR$q_parent = 24,0,0,0 %; literal GPS_HDR$s_parent = 8; ! hw_handle of object's parent ! ! ACPI 2.0a spec section ! ---------------------- macro GPS_HDR$q_adr = 32,0,0,0 %; literal GPS_HDR$s_adr = 8; ! _ADR 6.1.1 macro GPS_HDR$r_cid = 40,0,0,0 %; literal GPS_HDR$s_cid = 16; ! _CID 6.1.2 macro GPS_HDR$r_hid = 56,0,0,0 %; literal GPS_HDR$s_hid = 16; ! _HID 6.1.4 macro GPS_HDR$r_uid = 72,0,0,0 %; literal GPS_HDR$s_uid = 16; ! _UID 6.1.7 macro GPS_HDR$q_sta = 88,0,0,0 %; literal GPS_HDR$s_sta = 8; ! _STA 6.3.6, 7.1.4 macro GPS_HDR$q_bbn = 96,0,0,0 %; literal GPS_HDR$s_bbn = 8; ! _BBN 6.5.6 (Base Bus Number) macro GPS_HDR$q_seg = 104,0,0,0 %; literal GPS_HDR$s_seg = 8; ! _SEG 6.5.6 literal GPS$K_HDR_LENGTH = 112; ! ! GPS System Bus Object ! --------------------- ! Information reported upon the discovery of a system-level bus. ! literal GPS_SB$S_GPSSYSBUS = 40; macro GPS_SB$q_dma_base = 0,0,0,0 %; literal GPS_SB$s_dma_base = 8; ! Base Address of system DMA window macro GPS_SB$q_dma_max = 8,0,0,0 %; literal GPS_SB$s_dma_max = 8; ! Max Address of system DMA window macro GPS_SB$l_node_count = 16,0,32,1 %; ! Number of child nodes macro GPS_SB$l_reserved = 20,0,32,1 %; ! Pad macro GPS_SB$q_ioc_base = 24,0,0,0 %; literal GPS_SB$s_ioc_base = 8; ! Base Phys addr of IOC registers macro GPS_SB$q_tra_offset = 32,0,0,0 %; literal GPS_SB$s_tra_offset = 8; ! System access translation PA offset literal GPS$K_SB_LENGTH = 40; ! ! GPS PCI Host Object ! ------------------- ! Information reported upon the discovery of a PCI bus host. ! literal GPS_PCI$S_GPSPCIHOST = 56; macro GPS_PCI$q_base_pa = 0,0,0,0 %; literal GPS_PCI$s_base_pa = 8; ! Base Phys addr of this PCI space macro GPS_PCI$q_max_pa = 8,0,0,0 %; literal GPS_PCI$s_max_pa = 8; ! Max Phys addr of this PCI space macro GPS_PCI$q_prt_addr = 16,0,0,0 %; literal GPS_PCI$s_prt_addr = 8; ! VMS System VA of PRT for this bus macro GPS_PCI$q_prt_length = 24,0,0,0 %; literal GPS_PCI$s_prt_length = 8; ! Length of the whole PRT macro GPS_PCI$l_bus = 32,0,32,1 %; ! Bus Number of this PCI host bus macro GPS_PCI$l_seg = 36,0,32,1 %; ! Segment in which the PCI bus resides macro GPS_PCI$q_tra_offset = 40,0,0,0 %; literal GPS_PCI$s_tra_offset = 8; ! System access translation PA offset (per bus) macro GPS_PCI$q_tra_portio = 48,0,0,0 %; literal GPS_PCI$s_tra_portio = 8; ! Translation PA offset to port I/O space (per bus) literal GPS$K_PCI_LENGTH = 56; ! ! GPS PCI Device Object ! --------------------- ! Information reported upon the discovery of a PCI device. ! ! NOTE: ACPI does not report PCI devices, since there is an Industry ! Standard probing algorithm for PCI device discovery. This ! structure is more for informational purposes or for the unlikely ! case of non-ACPI device discovery and reporting mechanisms. ! literal GPS_PCIDEV$S_GPSPCIDEV = 40; macro GPS_PCIDEV$q_iosapic = 0,0,0,0 %; literal GPS_PCIDEV$s_iosapic = 8; ! VMS System VA of ACPI IOSAPIC struct macro GPS_PCIDEV$Q_ADDRESS = 8,0,0,0 %; literal GPS_PCIDEV$S_ADDRESS = 8; ! PCI config address macro GPS_PCIDEV$l_bus = 16,0,32,1 %; ! Bus upon which this device appears macro GPS_PCIDEV$l_seg = 20,0,32,1 %; ! Segment of device's bus macro GPS_PCIDEV$l_gsin = 24,0,32,0 %; ! Global System Interrupt Number macro GPS_PCIDEV$l_polarity = 28,0,32,1 %; ! Interrupt Polarity macro GPS_PCIDEV$l_trig_mode = 32,0,32,1 %; ! Interrupt Trigger Mode literal GPS$K_PCIDEV_LENGTH = 40; ! ! GPS IO Port Object ! ------------------ ! Information reported upon the discovery of an IO Port Space. ! literal GPS_IOP$S_GPSIOPORT = 16; macro GPS_IOP$q_base_pa = 0,0,0,0 %; literal GPS_IOP$s_base_pa = 8; ! Base Phys Addr of Port IO Space macro GPS_IOP$l_swizzle = 8,0,32,1 %; ! Number of bits to shift macro GPS_IOP$l_stride = 12,0,32,1 %; ! "Sparseness" of Port IO Space literal GPS$K_IOP_LENGTH = 16; ! ! GPS IO Port Device ! ------------------ ! Information reported upon the discovery of an IO Port Device. ! literal GPS_IOPDEV$S_GPSPORTDEV = 32; macro GPS_IOPDEV$q_iosapic = 0,0,0,0 %; literal GPS_IOPDEV$s_iosapic = 8; ! VMS System VA of ACPI IOSAPIC struct macro GPS_IOPDEV$q_csr_pa = 8,0,0,0 %; literal GPS_IOPDEV$s_csr_pa = 8; ! CSR Physical Address macro GPS_IOPDEV$l_gsin = 16,0,32,0 %; ! Global System Interrupt Number macro GPS_IOPDEV$l_polarity = 20,0,32,1 %; ! Interrupt Polarity macro GPS_IOPDEV$l_trig_mode = 24,0,32,1 %; ! Interrupt Trigger Mode literal GPS$K_IOPDEV_LENGTH = 32; ! ! GPS IO Embedded Device ! ---------------------- ! Information reported upon the discovery of an Embedded Device. ! literal GPS_EMB$S_GPSEMBDEV = 32; macro GPS_EMB$q_iosapic = 0,0,0,0 %; literal GPS_EMB$s_iosapic = 8; ! VMS System VA of ACPI IOSAPIC struct macro GPS_EMB$q_csr_pa = 8,0,0,0 %; literal GPS_EMB$s_csr_pa = 8; ! CSR Physical Address macro GPS_EMB$l_space = 16,0,32,1 %; ! Type of Address Space macro GPS_EMB$l_gsin = 20,0,32,0 %; ! Global System Interrupt Number macro GPS_EMB$l_polarity = 24,0,32,1 %; ! Interrupt Polarity macro GPS_EMB$l_trig_mode = 28,0,32,1 %; ! Interrupt Trigger Mode literal GPS$K_EMB_LENGTH = 32; ! ! GPS IOC Object ! --------------------- ! Information reported upon the discovery of an IOC which is separate ! from its system bus. HWP0004 for example. ! literal GPS_IOC$S_GPSIOC = 16; macro GPS_IOC$q_ioc_base = 0,0,0,0 %; literal GPS_IOC$s_ioc_base = 8; ! Base Phys addr of IOC registers macro GPS_IOC$q_tra_offset = 8,0,0,0 %; literal GPS_IOC$s_tra_offset = 8; ! System access translation PA offset literal GPS$K_IOC_LENGTH = 16; ! ! GPS ROOT Object ! --------------------- ! Information reported upon the discovery of the root node. ! literal GPS_ROOT$S_GPSROOT = 16; macro GPS_ROOT$q_reserved_1 = 0,0,0,0 %; literal GPS_ROOT$s_reserved_1 = 8; ! Reserved macro GPS_ROOT$q_reserved_2 = 8,0,0,0 %; literal GPS_ROOT$s_reserved_2 = 8; ! Reserved literal GPS$K_ROOT_LENGTH = 16; ! ! GPS CONTAIN Object ! --------------------- ! Information reported upon the discovery of a container node. ! literal GPS_CONTAIN$S_GPSCONTAIN = 16; macro GPS_CONTAIN$q_reserved_1 = 0,0,0,0 %; literal GPS_CONTAIN$s_reserved_1 = 8; ! Reserved macro GPS_CONTAIN$q_reserved_2 = 8,0,0,0 %; literal GPS_CONTAIN$s_reserved_2 = 8; ! Reserved literal GPS$K_CONTAIN_LENGTH = 16; ! ! GPS SPCR Object ! --------------------- ! Information reported upon the discovery of a SPCR table ! Defined as DIG64 Rev 5 Table, backwards compatible with Rev 4. ! literal GPS_SPMI$S_GPSSPMI = 32; macro GPS_SPMI$b_interface_type = 0,0,8,0 %; ! Interface type macro GPS_SPMI$b_ipmi = 1,0,8,0 %; ! Indicates IPMI enabled macro GPS_SPMI$w_spec_revision = 2,0,16,0 %; ! Rev of pertinent spec macro GPS_SPMI$b_interrupt_type = 4,0,8,0 %; ! Interrupt type macro GPS_SPMI$b_gpe = 5,0,8,0 %; ! GPE block number macro GPS_SPMI$b_reserved_0 = 6,0,8,0 %; ! reserved macro GPS_SPMI$b_pci_device_flag = 7,0,8,0 %; ! PCI Device Flag macro GPS_SPMI$l_gsin = 8,0,32,0 %; ! Global System Interrupt macro GPS_SPMI$b_address_space_id = 12,0,8,0 %; ! Part of ACPI GAS struct macro GPS_SPMI$b_register_bit_width = 13,0,8,0 %; ! Part of ACPI GAS struct macro GPS_SPMI$b_register_bit_offset = 14,0,8,0 %; ! Part of ACPI GAS struct macro GPS_SPMI$b_address_size = 15,0,8,0 %; ! Part of ACPI GAS struct macro GPS_SPMI$q_base_address = 16,0,0,0 %; literal GPS_SPMI$s_base_address = 8; ! Part of ACPI GAS struct macro GPS_SPMI$b_pci_seg = 24,0,8,0 %; ! PCI ident macro GPS_SPMI$b_pci_bus = 25,0,8,0 %; ! PCI ident macro GPS_SPMI$b_pci_device = 26,0,8,0 %; ! PCI ident macro GPS_SPMI$b_pci_function = 27,0,8,0 %; ! PCI ident macro GPS_SPMI$b_reserved_1 = 28,0,8,0 %; ! Reserved for compatibility literal GPS$K_SPMI_LENGTH = 32; ! ! GPS CPU Object ! --------------------- ! Information reported upon the discovery of a processor object. ! literal GPS_CPU$m_enabled = %X'1'; literal GPS_CPU$m_reserved = %X'FE'; literal GPS_CPU$S_GPSCPUDEV = 16; macro GPS_CPU$q_lid = 0,0,0,0 %; literal GPS_CPU$s_lid = 8; ! Local ID macro GPS_CPU$l_procid = 8,0,32,0 %; ! ACPI Processor ID macro GPS_CPU$b_flags = 12,0,8,0 %; macro GPS_CPU$v_enabled = 12,0,1,0 %; macro GPS_CPU$v_reserved = 12,1,7,0 %; literal GPS_CPU$s_reserved = 7; macro GPS_CPU$b_reserved_0 = 13,0,8,0 %; macro GPS_CPU$w_reserved_1 = 14,0,16,0 %; literal GPS$K_CPUDEV_LENGTH = 16; ! ! GPS GPE Block Device ! -------------------- ! Information reported upon the discovery of a GPE Block device ! literal GPS_GPE$S_GPSGPEDEV = 64; macro GPS_GPE$q_hw_id = 0,0,0,0 %; literal GPS_GPE$s_hw_id = 8; ! PNP ID string equivalent macro GPS_GPE$q_mbz = 8,0,0,0 %; literal GPS_GPE$s_mbz = 8; ! quadword of zeroes macro GPS_GPE$q_hw_handle = 16,0,0,0 %; literal GPS_GPE$s_hw_handle = 8; ! Object's hardware handle macro GPS_GPE$q_parent = 24,0,0,0 %; literal GPS_GPE$s_parent = 8; ! hw_handle of object's parent macro GPS_GPE$l_gsin = 32,0,32,0 %; ! Global System Interrupt Number macro GPS_GPE$l_int_type = 36,0,32,1 %; ! Interrupt Type macro GPS_GPE$l_polarity = 40,0,32,1 %; ! Interrupt Polarity macro GPS_GPE$l_trig_mode = 44,0,32,1 %; ! Interrupt Trigger Mode macro GPS_GPE$b_address_space_id = 48,0,8,0 %; ! Part of ACPI GAS struct macro GPS_GPE$b_register_bit_width = 49,0,8,0 %; ! Part of ACPI GAS struct macro GPS_GPE$b_register_bit_offset = 50,0,8,0 %; ! Part of ACPI GAS struct macro GPS_GPE$b_access_size = 51,0,8,0 %; ! Part of ACPI GAS struct macro GPS_GPE$q_base_address = 52,0,0,0 %; literal GPS_GPE$s_base_address = 8; ! Part of ACPI GAS struct literal GPS$K_GPEDEV_LENGTH = 64; ! ! GPS Data ! -------- ! Combine the discoverable bus objects into one union. ! literal GPS$S_GPSDATA = 64; macro GPS$r_sysbus = 0,0,0,0 %; literal GPS$s_sysbus = 40; ! GPSSYSBUSLESS uses same structure macro GPS$r_pci_host = 0,0,0,0 %; literal GPS$s_pci_host = 56; macro GPS$r_pci_dev = 0,0,0,0 %; literal GPS$s_pci_dev = 40; macro GPS$r_io_port = 0,0,0,0 %; literal GPS$s_io_port = 16; macro GPS$r_port_dev = 0,0,0,0 %; literal GPS$s_port_dev = 32; macro GPS$r_emb_dev = 0,0,0,0 %; literal GPS$s_emb_dev = 32; macro GPS$r_ioc = 0,0,0,0 %; literal GPS$s_ioc = 16; macro GPS$r_root = 0,0,0,0 %; literal GPS$s_root = 16; macro GPS$r_container = 0,0,0,0 %; literal GPS$s_container = 16; macro GPS$r_cpu_dev = 0,0,0,0 %; literal GPS$s_cpu_dev = 16; macro GPS$r_gpe_dev = 0,0,0,0 %; literal GPS$s_gpe_dev = 64; literal GPS$K_DATA_LENGTH = 64; ! ! GPS Config Information ! ---------------------- ! Combine the GPS Header and Data structures into one structure to be ! inited by ACPI calls and used by VMS IO mapping and configuring code. ! literal GPS$S_GPSCONFIG = 176; macro GPS$r_header = 0,0,0,0 %; literal GPS$s_header = 112; macro GPS$r_data = 112,0,0,0 %; literal GPS$s_data = 64; literal GPS$K_CONFIG_LENGTH = 176; ! ! GPS IO SAPIC Information ! ------------------------ ! literal GPS_IOSAPIC$S_GPSIOSAPICINFO = 16; macro GPS_IOSAPIC$q_base_addr = 0,0,0,0 %; literal GPS_IOSAPIC$s_base_addr = 8; macro GPS_IOSAPIC$l_base_gsin = 8,0,32,0 %; macro GPS_IOSAPIC$b_id = 12,0,8,0 %; literal GPS$K_IOSAPIC_LENGTH = 16; ! ! GPS HCDP Information ! -------------------- ! This structure provides information on the Headless Console & Debug Port, ! if there is one. ! literal GPS_HCDP$m_function = %X'7'; literal GPS_HCDP$m_reserved = %X'38'; literal GPS_HCDP$m_intr_flag = %X'40'; literal GPS_HCDP$m_pci_device = %X'80'; literal GPS_HCDP$m_console = %X'1'; literal GPS_HCDP$K_TYPE_generic_uart = 0; literal GPS_HCDP$K_TYPE_debug_port = 1; literal GPS_HCDP$K_TYPE_vga = 10; literal GPS_HCDP$K_TYPE_fpars_vcon = 130; literal GPS_HCDP$K_VERSION_pcdp = 3; literal GPS_HCDP$S_GPSHCDPDEV = 40; macro GPS_HCDP$w_vendor_id = 0,0,16,0 %; macro GPS_HCDP$w_device_id = 2,0,16,0 %; macro GPS_HCDP$l_space_id = 4,0,32,1 %; ! Type of address space macro GPS_HCDP$Q_ADDRESS = 8,0,0,0 %; literal GPS_HCDP$S_ADDRESS = 8; ! Address of the device macro GPS_HCDP$l_gsin = 16,0,32,0 %; ! Global System Interrupt Number macro GPS_HCDP$l_polarity = 20,0,32,1 %; ! Interrupt Polarity macro GPS_HCDP$l_trig_mode = 24,0,32,1 %; ! Interrupt Trigger Mode ! ! X-21 20070302 TLC ! Changed seg field from byte to word to comply with PCI_NODE_NUMBER ! and SAL. ! macro GPS_HCDP$b_seg = 28,0,8,0 %; ! These fields are valid when the macro GPS_HCDP$b_bus = 29,0,8,0 %; ! | pci_device flag bit is set macro GPS_HCDP$b_device = 30,0,8,0 %; ! | (see function_bits below) ! ! X-21 20070302 TLC - Clarification ! The PCI Function byte in the HCDP/PCDP is overloaded with flag bits, ! so we break them out here so they can be easily accessed by parsing ! code. ! macro GPS_HCDP$b_function = 31,0,8,0 %; ! whole word macro GPS_HCDP$v_function = 31,0,3,0 %; literal GPS_HCDP$s_function = 3; ! function number macro GPS_HCDP$v_reserved = 31,3,3,0 %; literal GPS_HCDP$s_reserved = 3; macro GPS_HCDP$v_intr_flag = 31,6,1,0 %; ! supports intr if 1 macro GPS_HCDP$v_pci_device = 31,7,1,0 %; ! pci_device if 1 ! ! X-21 20070302 TLC ! Flags ! macro GPS_HCDP$b_flags = 32,0,8,0 %; macro GPS_HCDP$v_console = 32,0,1,0 %; ! system console flag ! ! X-21 20070302 TLC ! Add version field to enable PLATFORM_SUPPORT to understand data ! in terms of whether coming from HCDP or PCDP. ! macro GPS_HCDP$b_version = 33,0,8,1 %; ! Version number: HCDP = 2, PCDP = 3 ! ! X-21 20070302 TLC ! Add type field to enable PLATFORM_SUPPORT to sort out the various ! console and com port device types. ! macro GPS_HCDP$b_type = 34,0,8,1 %; ! HCDP/PCDP device type ! ! X-21 20070302 TLC ! Pad out to next quadword. ! ! ! X-21 20070302 TLC ! HCDP/PCDP Console and Debug Port type constants. ! literal GPS$K_HCDP_LENGTH = 40; ! ! GPS System Information ! ---------------------- ! Provides information on the ACPI System. ! literal GPS_SYI$S_GPSSYSINFO = 32; macro GPS_SYI$t_vendor_name = 0,0,0,1 %; literal GPS_SYI$s_vendor_name = 8; macro GPS_SYI$t_vendor_model_name = 8,0,0,1 %; literal GPS_SYI$s_vendor_model_name = 8; macro GPS_SYI$q_acpi_ca_revision = 16,0,0,0 %; literal GPS_SYI$s_acpi_ca_revision = 8; macro GPS_SYI$l_acpi_major_revision = 24,0,32,0 %; literal GPS$K_SYSINFO_LENGTH = 32; ! ! Generic ACPI Buffer ! ------------------- ! For calls to acpi$osl_execute_method() that return with data type of ! ACPI_TYPE_BUFFER. ! literal GPS_BUF$S_GPSBUFFER = 16; macro GPS_BUF$l_length = 0,0,32,1 %; ! Length of data in bytes macro GPS_BUF$l_spare1_mbz = 4,0,32,1 %; ! Must be zeroed when created macro GPS_BUF$pq_pointer = 8,0,0,1 %; literal GPS_BUF$s_pointer = 8; ! Pointer to data ! ! System statistics returned by acpi$osl_get_statistics ! To get the entries in FixedEventCounts, ! acpi$osl_get_statistics fetches them via callback routines ! registered by previous calls to acpi$osl_install_fixed_handler. ! literal GPS_STA$S_GPSSTATISTICS = 32; macro GPS_STA$l_sci_count = 0,0,32,0 %; macro GPS_STA$l_gpe_count = 4,0,32,0 %; macro GPS_STA$l_fixed_event_count = 8,0,0,0 %; literal GPS_STA$s_fixed_event_count = 20; ! equal to acpi ACPI_NUM_FIXED_EVENTS macro GPS_STA$l_method_count = 28,0,32,0 %; literal GPS$K_STATISTICS_LENGTH = 32; ! ! Table Event handler used by acpi$osl_install_table_handler and ! acpi$os_remove_table_handler ! literal GPS_THDL$S_GPSTABLEHANDLER = 16; macro GPS_THDL$l_event = 0,0,32,0 %; macro GPS_THDL$ps_table = 4,0,32,1 %; macro GPS_THDL$ps_context = 8,0,32,1 %; literal GPS$K_THDL_LENGTH = 16; ! ! ============================================================================ ! SLOT OBJECT DEFINITION ! ============================================================================ ! ! A SLOT OBJECT is a physical connector on a backplane or motherboard into ! which a hardware device or adapter may be inserted. Slot Objects are ! tracked because it is possible for a device to be inserted into a slot in ! one hardware partition, while being "owned" by another hardware partition. ! ! This allows more flexibility in allocation of IO adapter resources in ! systems that have been partitioned. However, it is important to be able ! to determine whether an adapter or IO function in a slot can be configured ! into the current system. If the adapter or IO function is owned by another ! hardware partition, then the corresponding BUSARRAYENTRY in the non-owning ! partition must be invalidated. ! ! It is possible for a SLOT object to have another SLOT as its parent. ! ! EBA (Express Bus Agent) ! HID A ! ADP ----+------------------+ ! | | ! SLOT SLOT ! HID B HID C ! Parent HID A Parent HID A ! | | ! SLOT SLOT ! HID B1 HID C1 ! Parent HID B Parent HID C ! ! Since SLOT objects do not have their own ADPs, a problem ensues when ! trying to find the parent ADP of SLOT objects descendent from other ! SLOT objects, since the Parent Hardware Handle of descendent SLOT objects ! is that of their parent SLOT, rather than that of their ancestral Bus Agent. ! It is the Parent Hardware Handle of the ancestral Bus Agent that is required ! to locate the ADP for any given SLOT object. ! ! The following structure maps the ADP of the first-level SLOT objects ! of a Bus Agent (LBA, EBA, etc) with SLOT objects on descendent levels. ! An array of these structures is dynamicaly allocated by Bus Agents that ! require them. The pointer to the array will be placed in the adp$ps_devslots ! field of the ADP. ! literal DEVSLOT$S_DEVSLOT = 32; macro DEVSLOT$Q_HW_HANDLE = 0,0,0,0 %; literal DEVSLOT$S_HW_HANDLE = 8; macro DEVSLOT$Q_PARENT_HH = 8,0,0,0 %; literal DEVSLOT$S_PARENT_HH = 8; macro DEVSLOT$Q_RESERVED_0 = 16,0,0,1 %; literal DEVSLOT$S_RESERVED_0 = 8; macro DEVSLOT$Q_RESERVED_1 = 24,0,0,1 %; literal DEVSLOT$S_RESERVED_1 = 8; ! ***************************************************************************** ! ACPI DATA TYPES, CONSTANTS AND ENUMERATIONS ! ***************************************************************************** ! ! This section contains copies of the ACPI data types and definitions ! that must be exposed for other facilities, particularly PLATFORM_SUPPORT ! (aka IVMS), to use for calls into the ACPI. ! ! This section must be reviewed whenever there is a new ACPI code drop to ! assure proper synchronization with ACPI data types and definitions. ! ! NOTE: These definitions have been removed to prevent future backward ! compatibility issues with ACPI-CA updates from Intel. The file ! LOCALDEFS.H now imports ACPI data type definitions directly ! from the ACPI facility by including ACPI.H. ER - 12/16/2005 ! ! ! The following constant can be used to clue acpi$osl_get_crs_item that ! the parameter is unused or not required to fetch the item. ! literal GPS$K_IGNORE = -1; ! ! ============================================================================ ! ACPI RESOURCE DEFINITIONS ! ============================================================================ ! ! The ACPI Resource Hierarchy can be represented as follows. ! ! RESOURCE ! | ! +---------> ACPI_RESOURCE_TYPE ! | ! +-----------> ATTRIBUTE_ATTRIBUTE ! ! In a call to acpi$osl_get_crs_item, the top level parameter is required. ! The others may or may not be required, depending on the type of resource ! and the ways in which it can be characterized. ! ! ! Structures used to describe device-specific resources. ! literal GPS_VEND$S_GPS_RESOURCE_VENDCCSR = 27; macro GPS_VEND$W_CCSR_LENGTH = 0,0,16,0 %; macro GPS_VEND$B_CCSR_GUID_SUBTYPE = 2,0,8,0 %; macro GPS_VEND$B_CCSR_GUID = 3,0,0,0 %; literal GPS_VEND$S_CCSR_GUID = 16; macro GPS_VEND$B_CEC_CSR_BASE = 19,0,0,0 %; literal GPS_VEND$S_CEC_CSR_BASE = 8; literal GPS_VEND$S_GPS_RESOURCE_VENDPCIH = 21; macro GPS_VEND$W_PCIH_LENGTH = 0,0,16,0 %; macro GPS_VEND$B_PCIH_GUID_SUBTYPE = 2,0,8,0 %; macro GPS_VEND$B_PCIH_GUID = 3,0,0,0 %; literal GPS_VEND$S_PCIH_GUID = 16; macro GPS_VEND$B_PCI_HINT = 19,0,16,0 %; literal GPS_VEND$S_PCI_HINT = 2; !*** MODULE $GSDDEF *** ! + ! Global Section Descriptor Block ! - literal GSD$K_LENGTH = 49; ! LENGTH OF LOCAL MEMORY GSD literal GSD$C_LENGTH = 49; ! LENGTH OF LOCAL MEMORY GSD literal GSD$K_EXTGSDLNG = 73; ! MINIMUM EXTENDED GSD LENGTH literal GSD$C_EXTGSDLNG = 73; ! MINIMUM EXTENDED GSD LENGTH literal GSD$S_GSDDEF = 73; literal GSD$C_MAXNAMLEN = 43; ! Maximum length of a global section name (not including count byte) ! The size reflects 39-byte filenames and a 4-character prefix literal GSD$S_GSD = 80; macro GSD$L_GSDFL = 0,0,32,1 %; ! POINTER TO NEXT GSD macro GSD$L_GSDBL = 4,0,32,1 %; ! POINTER TO PREVIOUS GSD macro GSD$W_SIZE = 8,0,16,0 %; ! SIZE OF GSD IN BYTES macro GSD$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE CODE FOR GSD macro GSD$L_HASH = 12,0,32,0 %; ! HASH FOR GSD NAME macro GSD$L_PCBUIC = 16,0,32,0 %; ! UIC OF CREATOR OF SECTION, FROM PCB macro GSD$W_PCBGRP = 18,0,16,0 %; ! GROUP OF CREATOR OF SECTION, FROM PCB macro GSD$L_FILUIC = 20,0,32,0 %; ! OWNER OF FILE, UIC FROM FCB macro GSD$L_PROT = 24,0,32,0 %; ! PROTECTION MASK macro GSD$L_GSTX = 28,0,32,0 %; ! GLOBAL SECTION TABLE INDEX macro GSD$L_IDENT = 32,0,32,0 %; ! IDENTIFICATION OF GLOBAL SECTION macro GSD$L_ORB = 36,0,32,1 %; ! OBJECT RIGHTS BLOCK LOCATOR macro GSD$L_IPID = 40,0,32,0 %; ! IPID of nominal owner -- only defined while GSD is being deleted macro GSD$L_RELATED_GSTX = 40,0,32,0 %; ! GSTE index of another section related to this one. ! e.g. an MRES section with associated shared PTs macro GSD$L_FLAGS = 44,0,32,0 %; ! SECTION FLAGS macro GSD$T_GSDNAM = 48,0,8,0 %; ! LOCAL MEMORY SECTION NAME ! ! The following fields are only found in extended GSDs. These are used ! whenever a GSD is needed without a section table entry, i.e., for pages ! mapped by PFN. ! macro GSD$I_BASEPFN = 48,0,0,0 %; literal GSD$S_BASEPFN = 8; ! FIRST RELATIVE BASE PFN macro GSD$I_PAGES = 56,0,0,0 %; literal GSD$S_PAGES = 8; ! COUNT OF PAGES AT FIRST BASE PFN macro GSD$I_REFCNT = 64,0,0,0 %; literal GSD$S_REFCNT = 8; ! FIRST PROCESSOR PTE REF COUNT macro GSD$T_PFNGSDNAM = 72,0,8,0 %; ! PFN-MAPPED SECTION NAME ! from MA780 days. !*** MODULE $HD1DEF *** ! + ! HDR1 ANDSI MAGNETIC TAPE LABEL ! THIS IS THE FIRST LABEL IN THE FILE LABEL HEADER SET. IF IDENTIFIES THE FILE. ! - literal HD1$S_HD1DEF = 80; literal HD1$S_HD1 = 80; macro HD1$L_HD1LID = 0,0,32,0 %; ! LABEL IDENTIFIER AND NUMBER 'HDR1' macro HD1$T_FILEID = 4,0,0,0 %; literal HD1$S_FILEID = 17; ! FILE IDENTIFIER macro HD1$T_FILESETID = 21,0,0,0 %; literal HD1$S_FILESETID = 6; ! FILE SET IDENTIFIER macro HD1$T_FILESECNO = 27,0,32,0 %; literal HD1$S_FILESECNO = 4; ! FILE SECTION NUMBER macro HD1$T_FILESEQNO = 31,0,32,0 %; literal HD1$S_FILESEQNO = 4; ! FILE SEQUENCE NUMBER macro HD1$T_GENNO = 35,0,32,0 %; literal HD1$S_GENNO = 4; ! FILE GENERATION NUMBER macro HD1$T_GENVER = 39,0,16,0 %; literal HD1$S_GENVER = 2; ! FILE GENERATION VERSION NUMBER macro HD1$T_CREATEDT = 41,0,0,0 %; literal HD1$S_CREATEDT = 6; ! CREATION DATE ( YYDDD) macro HD1$T_EXPIREDT = 47,0,0,0 %; literal HD1$S_EXPIREDT = 6; ! EXPIRATION DATE macro HD1$B_FILACCESS = 53,0,8,0 %; ! FILE ACCESS macro HD1$T_BLOCKCNT = 54,0,0,0 %; literal HD1$S_BLOCKCNT = 6; ! BLOCK COUNT macro HD1$T_SYSCODE = 60,0,0,0 %; literal HD1$S_SYSCODE = 13; ! SYSTEM CODE macro HD1$T_HIBLOCKCNT = 76,0,32,0 %; literal HD1$S_HIBLOCKCNT = 4; ! HIGH BLOCK COUNT !*** MODULE $HD2DEF *** ! + ! HDR2 ANSI MAGNETIC TAPE LABEL ! THIS IS THE SECOND LABEL IN FILE LABEL HEADER SET. ! THE FILE ATTRIBUTES HAVE BEEN REMOVED FROM HDR2, AND PLACED IN HDR3. ! THE FIELDS REMAIN IN THE DEFINITION TO SUPPORT OLD TAPES. ! - literal HD2$S_HD2DEF = 72; literal HD2$S_HD2 = 72; macro HD2$L_HD2LID = 0,0,32,0 %; ! LABEL IDENTIFIER AND NUMBER 'HDR2' macro HD2$B_RECFORMAT = 4,0,8,0 %; ! RECORD FORMAT macro HD2$T_BLOCKLEN = 5,0,0,0 %; literal HD2$S_BLOCKLEN = 5; ! BLOCK LENGTH macro HD2$T_RECLEN = 10,0,0,0 %; literal HD2$S_RECLEN = 5; ! RECORD LENGTH macro HD2$T_RECATR1 = 15,0,0,0 %; literal HD2$S_RECATR1 = 20; ! FIRST 20 BYTES OF FILES-11 RECORD ATTRIBUTES macro HD2$B_FORMCNTRL = 36,0,8,0 %; ! FORMS CONTROL macro HD2$T_RECATR2 = 37,0,0,0 %; literal HD2$S_RECATR2 = 12; ! LAST 12 BYTES OF FILES-11 RECORD ATTRIBUTES macro HD2$T_BUFOFF = 50,0,16,0 %; literal HD2$S_BUFOFF = 2; ! BUFFER OFFSET !*** MODULE $HD3DEF *** ! + ! HDR3 ANSI MAGNETIC TAPE LABEL ! THIS IS THE THIRD LABEL IN FILE LABEL HEADER SET. ! IT IDENTIFIES THE FILE ATTRIBUTES. ! - literal HD3$S_HD3DEF = 80; literal HD3$S_HD3 = 80; macro HD3$L_HD3LID = 0,0,32,0 %; ! LABEL IDENTIFIES AND NUMBER 'HDR3' macro HD3$T_RECATR = 4,0,0,0 %; literal HD3$S_RECATR = 64; ! 64 BYTES OF FILES-11 RECORD ATTRIBUTES !*** MODULE $HD4DEF *** ! + ! HDR4 ANSI MAGNETIC TAPE LABEL ! THIS IS THE FOURTH LABEL IN FILE LABEL HEADER SET. ! IT CONTAINS THE LONG FILENAME EXTENSION TO THE HDR1 FILE IDENTIFIER ! FOR VMS LONG FILE NAMES ! - literal HD4$S_HD4DEF = 82; literal HD4$S_HD4 = 82; macro HD4$L_HD4LID = 0,0,32,0 %; ! LABEL IDENTIFIER AND NUMBER 'HDR4' macro HD4$B_FILEID_EXT_SIZE = 4,0,8,0 %; ! SIZE OF FILE ID EXT FOR ANSI 4 VOLUMES macro HD4$T_FILEID_EXT = 5,0,0,0 %; literal HD4$S_FILEID_EXT = 62; ! EXTENSION OF HDR1 FILEID macro HD4$T_FILEID_EXT_V3 = 67,0,16,0 %; literal HD4$S_FILEID_EXT_V3 = 2; ! SIZE OF FILE ID EXT FOR ANSI 3 VOLUMES !*** MODULE $HPCDEF *** literal HPC$S_HPC = 6168; macro HPC$b_f00 = 0,0,0,0 %; literal HPC$s_f00 = 24; macro HPC$L_CTL = 24,0,32,0 %; macro HPC$b_f10 = 28,0,0,0 %; literal HPC$s_f10 = 124; macro HPC$L_MRETRY = 152,0,32,0 %; macro HPC$b_f20 = 156,0,0,0 %; literal HPC$s_f20 = 124; macro HPC$L_GPR = 280,0,32,0 %; macro HPC$b_f30 = 284,0,0,0 %; literal HPC$s_f30 = 124; macro HPC$L_ERR = 408,0,32,0 %; macro HPC$b_f40 = 412,0,0,0 %; literal HPC$s_f40 = 124; macro HPC$L_FADR = 536,0,32,0 %; macro HPC$b_f50 = 540,0,0,0 %; literal HPC$s_f50 = 124; macro HPC$L_IMASK = 664,0,32,0 %; macro HPC$b_f60 = 668,0,0,0 %; literal HPC$s_f60 = 124; macro HPC$L_DIAG = 792,0,32,0 %; macro HPC$b_f70 = 796,0,0,0 %; literal HPC$s_f70 = 124; macro HPC$L_IPEND = 920,0,32,0 %; macro HPC$b_f80 = 924,0,0,0 %; literal HPC$s_f80 = 124; macro HPC$L_IPROG = 1048,0,32,0 %; macro HPC$b_f90 = 1052,0,0,0 %; literal HPC$s_f90 = 124; macro HPC$L_WMASK_A = 1176,0,32,0 %; macro HPC$b_f100 = 1180,0,0,0 %; literal HPC$s_f100 = 124; macro HPC$L_WBASE_A = 1304,0,32,0 %; macro HPC$b_f110 = 1308,0,0,0 %; literal HPC$s_f110 = 124; macro HPC$L_TBASE_A = 1432,0,32,0 %; macro HPC$b_f120 = 1436,0,0,0 %; literal HPC$s_f120 = 124; macro HPC$L_WMASK_B = 1560,0,32,0 %; macro HPC$b_f130 = 1564,0,0,0 %; literal HPC$s_f130 = 124; macro HPC$L_WBASE_B = 1688,0,32,0 %; macro HPC$b_f140 = 1692,0,0,0 %; literal HPC$s_f140 = 124; macro HPC$L_TBASE_B = 1816,0,32,0 %; macro HPC$b_f150 = 1820,0,0,0 %; literal HPC$s_f150 = 124; macro HPC$L_WMASK_C = 1944,0,32,0 %; macro HPC$b_f160 = 1948,0,0,0 %; literal HPC$s_f160 = 124; macro HPC$L_WBASE_C = 2072,0,32,0 %; macro HPC$b_f170 = 2076,0,0,0 %; literal HPC$s_f170 = 124; macro HPC$L_TBASE_C = 2200,0,32,0 %; macro HPC$b_f180 = 2204,0,0,0 %; literal HPC$s_f180 = 124; macro HPC$L_ERRVEC = 2328,0,32,0 %; macro HPC$b_f190 = 2332,0,0,0 %; literal HPC$s_f190 = 1788; macro HPC$L_D_INTA = 4120,0,32,0 %; macro HPC$L_D_INT_FILL1 = 4124,0,0,0 %; literal HPC$S_D_INT_FILL1 = 124; macro HPC$L_D_INTB = 4248,0,32,0 %; macro HPC$L_D_INT_FILL2 = 4252,0,0,0 %; literal HPC$S_D_INT_FILL2 = 124; macro HPC$L_D_INTC = 4376,0,32,0 %; macro HPC$L_D_INT_FILL3 = 4380,0,0,0 %; literal HPC$S_D_INT_FILL3 = 124; macro HPC$L_D_INTD = 4504,0,32,0 %; macro HPC$L_D_INT_FILL4 = 4508,0,0,0 %; literal HPC$S_D_INT_FILL4 = 124; literal IACK$S_IACK = 28; macro IACK$b_f210 = 0,0,0,0 %; literal IACK$s_f210 = 24; macro IACK$L_IACK = 24,0,32,0 %; literal HPC$S_HPC_CTL = 4; macro HPC$L_REG_CTL = 0,0,32,0 %; macro HPC$V_CONFIG_CYCLE_TYPE = 0,0,2,0 %; literal HPC$S_CONFIG_CYCLE_TYPE = 2; macro HPC$V_MEMORY_BLOCK_SIZE = 0,2,1,0 %; macro HPC$V_PCI_RESET = 0,3,1,0 %; macro HPC$V_PCI_CT_THRESHOLD = 0,4,4,0 %; literal HPC$S_PCI_CT_THRESHOLD = 4; macro HPC$V_PCI_CT_ENABLE = 0,8,1,0 %; macro HPC$V_IO_HAE = 0,9,5,0 %; literal HPC$S_IO_HAE = 5; macro HPC$V_MEMORY_HAE = 0,14,5,0 %; literal HPC$S_MEMORY_HAE = 5; macro HPC$V_HAE_DISABLE = 0,19,1,0 %; macro HPC$V_MRM_ARB = 0,20,1,0 %; macro HPC$V_MRM_ENABLE = 0,21,1,0 %; macro HPC$V_MRM_PREFETCH_SIZE = 0,22,1,0 %; macro HPC$V_IO_UPHOSE_BUFF = 0,23,2,0 %; literal HPC$S_IO_UPHOSE_BUFF = 2; macro HPC$V_SGM_RAM_SIZE = 0,25,2,0 %; literal HPC$S_SGM_RAM_SIZE = 2; macro HPC$V_PCI_ARB_CONTROL = 0,27,2,0 %; literal HPC$S_PCI_ARB_CONTROL = 2; literal HPC$S_HPC_IMASK = 4; macro HPC$L_REG_IMASK = 0,0,32,0 %; macro HPC$W_INT = 0,0,16,0 %; macro HPC$V_ENABLE_ERRINT = 0,16,1,0 %; macro HPC$V_DEVICE_PRIORITY = 0,17,4,0 %; literal HPC$S_DEVICE_PRIORITY = 4; macro HPC$V_ERROR_PRIORITY = 0,21,4,0 %; literal HPC$S_ERROR_PRIORITY = 4; macro HPC$V_MBZ = 0,25,7,0 %; literal HPC$S_MBZ = 7; literal HPC$S_HPC_PRESENT = 4; macro HPC$L_REG_PRESENT = 0,0,32,0 %; macro HPC$V_PCI_0_SLOT_0 = 0,0,2,0 %; literal HPC$S_PCI_0_SLOT_0 = 2; macro HPC$V_PCI_0_SLOT_1 = 0,2,2,0 %; literal HPC$S_PCI_0_SLOT_1 = 2; macro HPC$V_PCI_0_SLOT_2 = 0,4,2,0 %; literal HPC$S_PCI_0_SLOT_2 = 2; macro HPC$V_PCI_0_SLOT_3 = 0,6,2,0 %; literal HPC$S_PCI_0_SLOT_3 = 2; macro HPC$V_PCI_1_SLOT_0 = 0,8,2,0 %; literal HPC$S_PCI_1_SLOT_0 = 2; macro HPC$V_PCI_1_SLOT_1 = 0,10,2,0 %; literal HPC$S_PCI_1_SLOT_1 = 2; macro HPC$V_PCI_1_SLOT_2 = 0,12,2,0 %; literal HPC$S_PCI_1_SLOT_2 = 2; macro HPC$V_PCI_1_SLOT_3 = 0,14,2,0 %; literal HPC$S_PCI_1_SLOT_3 = 2; macro HPC$V_PCI_2_SLOT_0 = 0,16,2,0 %; literal HPC$S_PCI_2_SLOT_0 = 2; macro HPC$V_PCI_2_SLOT_1 = 0,18,2,0 %; literal HPC$S_PCI_2_SLOT_1 = 2; macro HPC$V_PCI_2_SLOT_2 = 0,20,2,0 %; literal HPC$S_PCI_2_SLOT_2 = 2; macro HPC$V_PCI_2_SLOT_3 = 0,22,2,0 %; literal HPC$S_PCI_2_SLOT_3 = 2; macro HPC$V_STANDARD_IO = 0,24,1,0 %; macro HPC$V_REVISION = 0,25,4,0 %; literal HPC$S_REVISION = 4; macro HPC$V_PRESENT_MBZ = 0,29,3,0 %; literal HPC$S_PRESENT_MBZ = 3; !*** MODULE $HQBDEF *** ! + ! HQB (Host Queue Block) Definitions ! ! This data structure contains information pertaining ! to a host that has established a connection to the ! server. ! - literal HQB$M_VC_FAILED = %X'1'; literal HQB$M_DISCON_INIT = %X'2'; literal HQB$M_PATHMOVE = %X'4'; literal HQB$M_UNIT_ONLINE = %X'1'; literal HQB$M_V5CL = %X'2'; literal HQB$M_HUNN = %X'4'; literal HQB$K_LENGTH = 72; literal HQB$S_HQBDEF = 72; literal HQB$S_HQB = 72; macro HQB$L_FLINK = 0,0,32,1 %; ! Used to link together all macro HQB$L_BLINK = 4,0,32,1 %; ! host HQBs using the server macro HQB$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro HQB$B_TYPE = 10,0,8,0 %; ! MSCP type structure macro HQB$B_SUBTYPE = 11,0,8,0 %; ! with a HQB subtype (2) macro HQB$B_HOSTNO = 12,0,8,0 %; ! Assigned host number macro HQB$B_STATE = 13,0,8,0 %; ! State of this host macro HQB$V_VC_FAILED = 13,0,1,0 %; ! The VC to this host has failed macro HQB$V_DISCON_INIT = 13,1,1,0 %; ! Disconnect being processed macro HQB$V_PATHMOVE = 13,2,1,0 %; ! Closing connection for port load balancing macro HQB$W_CNT_FLGS = 14,0,16,0 %; ! Host settable controller flags macro HQB$W_HTIMO = 16,0,16,0 %; ! Host access timeout interval macro HQB$W_FLAGS = 18,0,16,0 %; macro HQB$V_UNIT_ONLINE = 18,0,1,0 %; ! This host had units online macro HQB$V_V5CL = 18,1,1,0 %; ! This is the V5 class driver macro HQB$V_HUNN = 18,2,1,0 %; ! Class driver knows new naming ! when the link was broken macro HQB$Q_TIME = 20,0,0,0 %; literal HQB$S_TIME = 8; ! Time host issued set-ctrl-chr macro HQB$W_NUM_QUE = 28,0,16,0 %; ! Requests outstanding macro HQB$W_MAX_QUE = 30,0,16,0 %; ! Most requests ever out macro HQB$L_HRB_FL = 32,0,32,1 %; ! HRB queue listhead for macro HQB$L_HRB_BL = 36,0,32,1 %; ! this host macro HQB$L_CDT = 40,0,32,1 %; ! Connection Desc Table addr macro HQB$L_DSRV = 44,0,32,1 %; ! DSRV address macro HQB$B_SYSTEMID = 48,0,0,0 %; literal HQB$S_SYSTEMID = 6; ! SCS system ID of host macro HQB$W_MAX_HULB = 54,0,16,0 %; ! Size of HULB vector macro HQB$L_HULB_VECTOR = 56,0,32,1 %; ! HULB vector address macro HQB$L_TSRV = 60,0,32,1 %; ! TSRV address macro HQB$L_ACK_TIME = 64,0,32,0 %; ! Time stamp form last remote request macro HQB$L_ARR_TIME = 68,0,32,0 %; ! Round trip time from server to host !*** MODULE $HRBDEF *** ! + ! HRB (Host Request Block) Definitions ! ! These definitions describe the format of a data structure ! that is used in the MSCP server to represent the context ! of a request from one of the served hosts. ! - literal HRB$M_STATE_INVALID = %X'8000'; literal HRB$M_ABORT = %X'1'; literal HRB$M_ABORTWS = %X'2'; literal HRB$M_DEQUEUED = %X'4'; literal HRB$M_ENDMSG = %X'8'; literal HRB$M_MAP = %X'10'; literal HRB$M_UNBLOCK = %X'20'; literal HRB$M_VCFAILED = %X'40'; literal HRB$M_OLDBUF = %X'80'; literal HRB$M_WBC_IMMED = %X'100'; literal HRB$M_FIRST = %X'200'; literal HRB$M_FLUSH = %X'400'; literal HRB$M_CMD_TMO = %X'800'; literal HRB$K_LENGTH = 140; ! request state definitions literal HRB$K_ST_MSG_WAIT = 1; ! Atn msg buffer/credit wait literal HRB$K_ST_SEQ_WAIT = 2; ! Waiting for sequential cmd literal HRB$K_ST_BUF_WAIT = 3; ! Waiting for server buffer literal HRB$K_ST_SNDAT_WAIT = 4; ! Sending or receiving data literal HRB$K_ST_DRV_WAIT = 5; ! Driver queue literal HRB$K_ST_MAP_WAIT = 6; ! Mapping a data buffer literal HRB$K_ST_UNMAP_WAIT = 7; ! Returning mapping resources literal HRB$K_ST_SNDMS_WAIT = 8; ! Sending message literal HRB$K_ST_MEM_WAIT = 9; ! Local buffer wait literal HRB$K_ST_FLUSHED = 10; ! Flushed from cache literal HRB$K_ST_CACHED = 11; ! In local host cache literal HRB$S_HRBDEF = 140; ! Old size name - synonym literal HRB$S_HRB = 140; macro HRB$L_FLINK = 0,0,32,1 %; ! Used to link this request macro HRB$L_BLINK = 4,0,32,1 %; ! into the HQB data styructure macro HRB$W_SIZE = 8,0,16,0 %; ! Data structure size in bytes macro HRB$B_TYPE = 10,0,8,0 %; ! This is an MSCP type struct macro HRB$B_SUBTYPE = 11,0,8,0 %; ! with a HRB subtype (3) macro HRB$L_RESPC = 12,0,32,1 %; ! PC to resume on restart macro HRB$L_SAVD_RTN = 16,0,32,1 %; ! Saved address of caller macro HRB$W_STATE = 20,0,16,0 %; ! State of the request macro HRB$V_STATE_INVALID = 20,15,1,0 %; ! State is current but previous ! state was (bits 0-15) macro HRB$W_FLAGS = 22,0,16,0 %; ! Status flags macro HRB$V_ABORT = 22,0,1,0 %; ! Abort macro HRB$V_ABORTWS = 22,1,1,0 %; ! Abort with status macro HRB$V_DEQUEUED = 22,2,1,0 %; ! Removed from resource queues macro HRB$V_ENDMSG = 22,3,1,0 %; ! End message needs to be sent macro HRB$V_MAP = 22,4,1,0 %; ! Map resources allocated macro HRB$V_UNBLOCK = 22,5,1,0 %; ! Unblock needs to be called macro HRB$V_VCFAILED = 22,6,1,0 %; ! The VC for this host failed macro HRB$V_OLDBUF = 22,7,1,0 %; ! The buffer allocated for this ! rqst is out of the old buffer macro HRB$V_WBC_IMMED = 22,8,1,0 %; ! Write-back caching command macro HRB$V_FIRST = 22,9,1,0 %; ! First in burst sequence for tapes macro HRB$V_FLUSH = 22,10,1,0 %; ! This is a flush type command macro HRB$V_CMD_TMO = 22,11,1,0 %; ! This command has "timed out" macro HRB$L_MSGBUF = 24,0,32,1 %; ! Addr of MSCP request packet macro HRB$L_IRP_CDRP = 28,0,32,1 %; ! CDRP for I/O requests macro HRB$B_LBUFF = 32,0,0,0 %; literal HRB$S_LBUFF = 12; ! Local buffer descriptor macro HRB$L_BD_ADDR = 44,0,32,1 %; ! Buffer Descriptor Address macro HRB$L_BUFLEN = 48,0,32,0 %; ! Length of buffer allocated macro HRB$L_BUFADR = 52,0,32,1 %; ! Buffer starting address macro HRB$L_LBN = 56,0,32,0 %; ! LBN place holder for xfr macro HRB$L_OBCNT = 60,0,32,0 %; ! Original request byte count macro HRB$L_ABCNT = 64,0,32,0 %; ! Number of bytes already sent macro HRB$L_SVAPTE = 68,0,32,0 %; ! Page table entry for lcl bufr macro HRB$L_BCNT = 72,0,32,0 %; ! Temp storage for current xfr macro HRB$W_BOFF = 76,0,16,0 %; ! Offset within page of sob macro HRB$L_WAIT_FL = 80,0,32,1 %; ! Pointers to link HRB into macro HRB$L_WAIT_BL = 84,0,32,1 %; ! wait queues in UQB macro HRB$L_HQB = 88,0,32,1 %; ! Host Queue Block address macro HRB$L_UQB = 92,0,32,1 %; ! Unit Queue Block address macro HRB$L_PDT = 96,0,32,1 %; ! Port Desc Table for requestor macro HRB$L_CMD_STS = 100,0,32,0 %; ! Measure of work to be done macro HRB$L_OBJECT_SKIP = 104,0,32,0 %; ! Objects requested for skipfile macro HRB$L_CURRENT_SKIP = 108,0,32,0 %; ! Placemarker during REPOS macro HRB$L_IO_TIME = 112,0,32,0 %; ! Time for I/O to go from ! server to tape and back macro HRB$L_CACHE_FL = 116,0,32,1 %; ! Cache queue macro HRB$L_CACHE_BL = 120,0,32,1 %; ! macro HRB$L_MEMW_FL = 124,0,32,1 %; ! Waiting on more memory macro HRB$L_MEMW_BL = 128,0,32,1 %; ! macro HRB$L_RECORD = 132,0,32,0 %; ! Record position on tape macro HRB$L_CMD_TIME = 136,0,32,0 %; ! Record timestamp !*** MODULE $HULBDEF *** ! + ! HULB (Host/Unit Load Block) Definitions ! ! These definitions describe the format of a data structure ! that is used in the MSCP server to record traffic and status ! information used by server load balancing. Time fields are in ! EXE$GL_ABSTIM format. ! - literal HULB$M_LB_REQ = %X'1'; literal HULB$M_DELETE = %X'2'; literal HULB$M_LB_DISABLED = %X'4'; literal HULB$K_LENGTH = 28; literal HULB$K_VECLEN = 256; literal HULB$S_HULBDEF = 28; literal HULB$S_HULB = 28; macro HULB$L_FLINK = 0,0,32,1 %; ! Used to link this request macro HULB$L_BLINK = 4,0,32,1 %; ! into the DSRV data styructure macro HULB$W_SIZE = 8,0,16,0 %; ! Data structure size in bytes macro HULB$B_TYPE = 10,0,8,0 %; ! This is an MSCP type struct macro HULB$B_SUBTYPE = 11,0,8,0 %; ! with a HULB subtype (4) macro HULB$W_HOSTNO = 12,0,16,0 %; ! Assigned host number macro HULB$W_UNITNO = 14,0,16,0 %; ! Assigned unit number macro HULB$W_OPCOUNT = 16,0,16,0 %; ! Current operation count macro HULB$W_PREV_OPC = 18,0,16,0 %; ! Operation count for prev interval macro HULB$L_TIME = 20,0,32,0 %; ! Time of last LB request macro HULB$W_STATUS = 24,0,16,0 %; ! LB status bits macro HULB$V_LB_REQ = 24,0,1,0 %; ! This unit has been asked to LB macro HULB$V_DELETE = 24,1,1,0 %; ! This unit is offline and the HULB can be deleted macro HULB$V_LB_DISABLED = 24,2,1,0 %; ! This unit is not available for load balancing !*** MODULE $HWPRTDEF *** ! + ! Protection field definitions. These encodings are specific ! to the architecture and should only be used for ! privileged interfaces. ! - literal HWPRT$C_HWPRT = -2147483648; ! Identify protection argument as HW protection form literal HWPRT$M_HWPRT = -2147483648; ! Identify protection argument as HW protection form literal HWPRT$C_NA = 0; ! No Access literal HWPRT$C_KR = 4; ! Kernel Read only AR=1 PL=0 (execute) literal HWPRT$C_ER = 5; ! Exec Read only AR=1 PL=1 (execute) literal HWPRT$C_SR = 6; ! Super Read only AR=1 PL=2 (execute) literal HWPRT$C_UR = 7; ! User Read only AR=1 PL=3 (execute) literal HWPRT$C_KW = 8; ! Kernel Write AR=2 PL=0 (no execute) literal HWPRT$C_EW = 9; ! Exec Write AR=2 PL=1 (no execute) literal HWPRT$C_SW = 10; ! Super Write AR=2 PL=2 (no execute) literal HWPRT$C_UW = 11; ! User Write AR=2 PL=3 (no execute) literal HWPRT$C_ERKW = 17; ! Exec Read Kernel Write AR=4 PL=1 (no execute) literal HWPRT$C_SRKW = 22; ! Super Read Kernel Write AR=5 PL=2 (execute) literal HWPRT$C_SREW = 18; ! Super Read Exec Write AR=4 PL=2 (no execute) literal HWPRT$C_URKW = 23; ! User Read Kernel Write AR=5 PL=3 (execute) ! UREW cannot be expressed in IA64 AR/PL form. We use URSW which allows SW access. literal HWPRT$C_UREW = 19; ! User Read Exec Write AR=4 PL=3 (no execute) literal HWPRT$C_URSW = 19; ! User Read Super Write AR=4 PL=3 (no execute) ! ! These protection encodings are not VAX / Alpha compatible: ! literal HWPRT$C_KRO = 0; ! Kernel Read Only AR=0 PL=0 (no execute) literal HWPRT$C_ERO = 1; ! Exec Read Only AR=0 PL=1 (no execute) literal HWPRT$C_SRO = 2; ! Super Read Only AR=0 PL=2 (no execute) literal HWPRT$C_URO = 3; ! User Read Only AR=0 PL=3 (no execute) literal HWPRT$C_KWX = 12; ! Kernel Write AR=3 PL=0 (execute) literal HWPRT$C_EWX = 13; ! Exec Write AR=3 PL=0 (execute) literal HWPRT$C_SWX = 14; ! Super Write AR=3 PL=0 (execute) literal HWPRT$C_UWX = 15; ! User Write AR=3 PL=0 (execute) literal HWPRT$C_KPX = 28; ! Kernel promote, execute only AR=7 PL=0 literal HWPRT$C_EPX = 29; ! Exec promote, execute only AR=7 PL=1 literal HWPRT$C_SPX = 30; ! Super promote, execute only AR=7 PL=2 literal HWPRT$C_UX = 31; ! User execute only AR=7 PL=3 !*** MODULE $HWRPBDEF *** ! Verified for IA64 port - WBF literal EXE$K_SECBOOT = 0; ! Address of secondary boot literal EXE$K_HWRPB = 268435456; ! Address of HWRPB = 256Mb literal EXE$K_PRIMBOOT = 536870912; ! Address of primary bootstrap literal EXE$K_NETBOOT = 805306368; ! Address of network bootstrap literal EXE$K_DEBUGBOOT = 939524096; ! Address of debug bootstrap literal EXE$K_BOOTPT = 1073741824; ! Fixed addr. of page tbl =1Gb ! ! ******************************* MAIN HWRPB DEFINITION ******************************* ! literal HWRPB_SYSTYPE$K_GENERIC = 64; ! 64 Generic Itanium System literal HWRPB_SYSTYPE$K_MAX_SYSTYPE = 64; ! literal HWRPB$M_MPCAP = %X'1'; literal HWRPB$M_CNSLE = %X'2'; literal HWRPB$M_FILL2 = %X'20'; literal HWRPB$M_FILL3 = %X'100'; literal HWRPB$M_GRAPHICS = %X'200'; literal HWRPB$M_MEMBER_ID = %X'400'; literal HWRPB$M_FILL0 = %X'1'; literal HWRPB$M_BIGCONFIG = %X'400'; literal HWRPB$M_VIRBND = %X'1'; literal HWRPB$M_RXTX_EXTENT = %X'2'; literal HWRPB_MEMBER_ID$K_NORITAKE = 1; literal HWRPB_MEMBER_ID$K_PINNACLE = 2; literal HWRPB_MEMBER_ID$K_PNORITAKE = 3; literal HWRPB_MEMBER_ID$K_CORELLE = 4; ! literal HWRPB_MEMBER_ID$K_PC264 = 1; literal HWRPB_MEMBER_ID$K_DP264 = 1; literal HWRPB_MEMBER_ID$K_WARHOL = 2; literal HWRPB_MEMBER_ID$K_WINDJAMMER = 3; literal HWRPB_MEMBER_ID$K_MONET = 4; literal HWRPB_MEMBER_ID$K_CLIPPER = 5; literal HWRPB_MEMBER_ID$K_GOLDRUSH = 6; literal HWRPB_MEMBER_ID$K_WEBBRICK = 7; literal HWRPB_MEMBER_ID$K_GOLDRACK = 8; literal HWRPB_MEMBER_ID$K_PRIVATEER = 1; literal HWRPB_MEMBER_ID$K_FALCON_E = 2; literal HWRPB_MEMBER_ID$K_FALCON_S = 3; literal HWRPB_MEMBER_ID$K_GRANITE = 4; literal HWRPB_MEMBER_ID$K_HYPERBRICK = 5; literal HWRPB_MEMBER_ID$K_HYPERSLATE = 6; ! literal HWRPB_BOOT_FLAGS$M_ROOT = %X'FFFF0000'; literal HWRPB_ADDRESS_ID$K_SYSMEM = 0; literal HWRPB_ADDRESS_ID$K_SYSIO = 1; literal HWRPB_ADDRESS_ID$K_PCICFG = 2; literal HWRPB_ADDRESS_ID$K_EMBED = 3; literal HWRPB_ADDRESS_ID$K_SMBUS = 4; literal HWRPB_ADDRESS_ID$K_FIXED = 127; ! literal HWRPB$M_TXRDY_SUMMARY = %X'1'; literal HWRPB$M_FUNCTION = %X'7'; literal HWRPB$M_RESERVED = %X'38'; literal HWRPB$M_INTR_FLAG = %X'40'; literal HWRPB$M_PCI_DEVICE = %X'80'; literal HWRPB$M_FUNCT = %X'7'; literal HWRPB$M_DEVICE = %X'F8'; literal HWRPB$M_BUS = %X'FF00'; literal HWRPB$M_HOSE = %X'FF0000'; literal HWRPB$M_FILL1 = %X'FF000000'; literal HWRPB$M_UART_PCICFG_FUNCTION = %X'7'; literal HWRPB$M_UART_PCICFG_DEVICE = %X'F8'; literal HWRPB$M_UART_PCICFG_BUS = %X'FF00'; literal HWRPB$M_UART_PCICFG_OFFSET = %X'FFFF0000'; literal HWRPB$M_VGA_PCICFG_FUNCTION = %X'7'; literal HWRPB$M_VGA_PCICFG_DEVICE = %X'F8'; literal HWRPB$M_VGA_PCICFG_BUS = %X'FF00'; literal HWRPB$M_VGA_PCICFG_OFFSET = %X'FFFF0000'; literal HWRPB$M_VGA_CONSOLE = %X'1'; literal HWRPB$S_HWRPB = 1272; ! ! Physical address of the HWRPB ! ****************************** macro HWRPB$PQ_BASE = 0,0,0,1 %; literal HWRPB$S_BASE = 8; ! Physical address of HWRPB macro HWRPB$PS_BASE_L = 0,0,32,1 %; ! ! ASCIIZ "HWRPB" ! *************** macro HWRPB$IQ_IDENT = 8,0,0,0 %; literal HWRPB$S_IDENT = 8; ! Contains ASCIZ "HWRPB" macro HWRPB$IL_IDENT_L = 8,0,32,0 %; macro HWRPB$IL_IDENT_H = 12,0,32,0 %; ! ! HWRPB revision (Begins with 257 for Itanium) ! *************** macro HWRPB$IQ_REVISION = 16,0,0,0 %; literal HWRPB$S_REVISION = 8; ! HWRPB revision number macro HWRPB$IL_REVISION_L = 16,0,32,0 %; macro HWRPB$IL_REVISION_H = 20,0,32,0 %; ! ! HWRPB size ! *********** macro HWRPB$IQ_SIZE = 24,0,0,0 %; literal HWRPB$S_SIZE = 8; ! HWRPB Size macro HWRPB$IL_SIZE_L = 24,0,32,0 %; macro HWRPB$IL_SIZE_H = 28,0,32,0 %; ! ! Virtual address of the HWRPB ! ****************************** macro HWRPB$PQ_VBASE = 32,0,0,1 %; literal HWRPB$S_VBASE = 8; ! Virtual address of HWRPB ! ! Primary CPU ID (Hard partition CPU ID that matches WHAMI and slot offset values - not a LID) ! *************** macro HWRPB$IQ_PRIMARY = 40,0,0,0 %; literal HWRPB$S_PRIMARY = 8; ! Primary CPU ID macro HWRPB$IL_PRIMARY_L = 40,0,32,0 %; macro HWRPB$IL_PRIMARY_H = 44,0,32,0 %; ! ! Page size in bytes ! ******************* macro HWRPB$IQ_PAGESIZE = 48,0,0,0 %; literal HWRPB$S_PAGESIZE = 8; ! Page size in bytes macro HWRPB$IL_PAGESIZE_L = 48,0,32,0 %; macro HWRPB$IL_PAGESIZE_H = 52,0,32,0 %; ! ! Number of Physical Address Bits ! ******************************** macro HWRPB$IQ_PA_SIZE = 56,0,0,0 %; literal HWRPB$S_PA_SIZE = 8; ! Number of Phys. addr. bits macro HWRPB$IL_PA_SIZE_L = 56,0,32,0 %; macro HWRPB$IL_PA_SIZE_H = 60,0,32,0 %; ! ! Maximum ASN ! ************ macro HWRPB$IQ_ASN_MAX = 64,0,0,0 %; literal HWRPB$S_ASN_MAX = 8; ! Maximum ASN macro HWRPB$IL_ASN_MAX_L = 64,0,32,0 %; macro HWRPB$IL_ASN_MAX_H = 68,0,32,0 %; ! ! System Serial Number - Virtualized version, if applicable ! ********************** macro HWRPB$B_SYS_SERIALNUM = 72,0,0,0 %; literal HWRPB$S_SYS_SERIALNUM = 16; ! System Serial number ! ! System Type ! ************ macro HWRPB$IQ_SYSTYPE = 88,0,0,0 %; literal HWRPB$S_SYSTYPE = 8; ! System type macro HWRPB$IL_SYSTYPE_L = 88,0,32,0 %; macro HWRPB$IL_SYSTYPE_H = 92,0,32,0 %; ! ! System Variation ! ***************** macro HWRPB$IQ_SYSVAR = 96,0,0,0 %; literal HWRPB$S_SYSVAR = 8; ! System variation quadword macro HWRPB$IL_SYSVAR_L = 96,0,32,0 %; macro HWRPB$V_MPCAP = 96,0,1,0 %; ! Capable of Multi-Processors macro HWRPB$V_CNSLE = 96,1,1,0 %; literal HWRPB$S_CNSLE = 4; ! Console Type macro HWRPB$V_FILL2 = 96,5,1,0 %; literal HWRPB$S_FILL2 = 3; ! ex-Powerfail Type macro HWRPB$V_FILL3 = 96,8,1,0 %; ! ex-Powerfail Restart macro HWRPB$V_GRAPHICS = 96,9,1,0 %; ! Embedded graphics processor macro HWRPB$V_MEMBER_ID = 96,10,1,0 %; literal HWRPB$S_MEMBER_ID = 6; ! Member ID field ! ! The following definition is for backward compatibility with ! Laser/Blazer code, which only used one bit of the member ID ! field. ! macro HWRPB$V_FILL0 = 96,0,1,0 %; literal HWRPB$S_FILL0 = 10; macro HWRPB$V_BIGCONFIG = 96,10,1,0 %; ! Blazer (vs. Laser) macro HWRPB$IL_SYSVAR_H = 100,0,32,0 %; macro HWRPB$V_VIRBND = 100,0,1,0 %; ! Virtual Address Boundary Register support macro HWRPB$V_RXTX_EXTENT = 100,1,1,0 %; ! ECO 123 discriminator ! ****************************************** ! * Define constants for member ID field. ** ! ****************************************** ! ! This field is used to identify a system only after first examining ! SYSTEM_TYPE and CPU_TYPE fields. It is possible that platforms with ! different SYSTEM_TYPE to re-use previously defined values as a different ! member ID. ! ! ! System Revision ! **************** macro HWRPB$IQ_SYSREV = 104,0,0,0 %; literal HWRPB$S_SYSREV = 8; ! System revision macro HWRPB$IL_SYSREV_L = 104,0,32,0 %; macro HWRPB$IL_SYSREV_H = 108,0,32,0 %; ! ! Clock Interrupt Frequency ! ************************** macro HWRPB$IQ_CLOCK_INT_FREQ = 112,0,0,0 %; literal HWRPB$S_CLOCK_INT_FREQ = 8; ! Clock interrupt frequency macro HWRPB$IL_CLOCK_INT_FREQ_L = 112,0,32,0 %; macro HWRPB$IL_CLOCK_INT_FREQ_H = 116,0,32,0 %; ! ! ITC Update Frequency ! ************************** macro HWRPB$IQ_ITC_FREQ = 120,0,0,0 %; literal HWRPB$S_ITC_FREQ = 8; ! Itanium ITC update interrupt frequency ! ! Cycle Counter Frequency ! ************************ macro HWRPB$IQ_CYCLE_COUNT_FREQ = 128,0,0,0 %; literal HWRPB$S_CYCLE_COUNT_FREQ = 8; ! Cycle counter frequency macro HWRPB$IL_CYCLE_COUNT_FREQ_L = 128,0,32,0 %; macro HWRPB$IL_CYCLE_COUNT_FREQ_H = 132,0,32,0 %; ! ! Virtual Page Table Base ! ************************ macro HWRPB$IQ_VPTB = 136,0,0,0 %; literal HWRPB$S_VPTB = 8; ! Virtual Page Table Base macro HWRPB$IL_VPTB_L = 136,0,32,0 %; macro HWRPB$IL_VPTB_H = 140,0,32,0 %; ! ! Number of Per-CPU Slots ! ************************ macro HWRPB$IQ_NPROC = 144,0,0,0 %; literal HWRPB$S_NPROC = 8; ! Number of Per-CPU slots macro HWRPB$IL_NPROC_L = 144,0,32,0 %; macro HWRPB$IL_NPROC_H = 148,0,32,0 %; ! ! Size of Per-CPU slots ! ********************** macro HWRPB$IQ_SLOT_SIZE = 152,0,0,0 %; literal HWRPB$S_SLOT_SIZE = 8; ! Size of Per-CPU slots macro HWRPB$IL_SLOT_SIZE_L = 152,0,32,0 %; macro HWRPB$IL_SLOT_SIZE_H = 156,0,32,0 %; ! ! Offset to Per-CPU slots ! ************************ macro HWRPB$IQ_SLOT_OFFSET = 160,0,0,0 %; literal HWRPB$S_SLOT_OFFSET = 8; ! Offset to Per-CPU slots macro HWRPB$IL_SLOT_OFFSET_L = 160,0,32,0 %; macro HWRPB$IL_SLOT_OFFSET_H = 164,0,32,0 %; ! ! Offset to Console Routine Block ! ******************************** macro HWRPB$IQ_CRB_OFFSET = 168,0,0,0 %; literal HWRPB$S_CRB_OFFSET = 8; ! Offset to Console routine blk macro HWRPB$IL_CRB_OFFSET_L = 168,0,32,0 %; macro HWRPB$IL_CRB_OFFSET_H = 172,0,32,0 %; ! ! Offset to Memory Data Descriptor Table ! *************************************** macro HWRPB$IQ_MEM_OFFSET = 176,0,0,0 %; literal HWRPB$S_MEM_OFFSET = 8; ! Offset to memory descriptor macro HWRPB$IL_MEM_OFFSET_L = 176,0,32,0 %; macro HWRPB$IL_MEM_OFFSET_H = 180,0,32,0 %; ! ! Virtual Address of CPU restart routine ! *************************************** macro HWRPB$IQ_RESTART = 184,0,0,0 %; literal HWRPB$S_RESTART = 8; ! VA of restart routine macro HWRPB$IL_RESTART_L = 184,0,32,1 %; macro HWRPB$IL_RESTART_H = 188,0,32,0 %; ! ! Procedure Descriptor for CPU restart routine ! ********************************************* macro HWRPB$IQ_RESTART_PD = 192,0,0,0 %; literal HWRPB$S_RESTART_PD = 8; ! Restart Procedure Descriptor macro HWRPB$IL_RESTART_PD_L = 192,0,32,0 %; macro HWRPB$IL_RESTART_PD_H = 196,0,32,0 %; ! ! SWRPB - Software Restart Parameter Block ! ***************************************** macro HWRPB$PQ_SWRPB = 200,0,0,1 %; literal HWRPB$S_SWRPB = 8; ! Reserved for software macro HWRPB$PL_SWRPB_L = 200,0,32,1 %; macro HWRPB$IL_SWRPB_H = 204,0,32,1 %; ! ! [IPF] Offset to Whami Table ! ************************ macro HWRPB$IQ_WHAMI_OFFSET = 208,0,0,0 %; literal HWRPB$S_WHAMI_OFFSET = 8; ! [IPF] Offset to Whami Table macro HWRPB$IL_WHAMI_OFFSET_L = 208,0,32,0 %; macro HWRPB$IL_WHAMI_OFFSET_H = 212,0,32,0 %; ! ! [IPF] System Table Base PA ! ************************ macro HWRPB$IQ_ST_BASE_PA = 216,0,0,0 %; literal HWRPB$S_ST_BASE_PA = 8; ! [IPF] System Table Base PA macro HWRPB$IL_ST_BASE_PA_L = 216,0,32,0 %; macro HWRPB$IL_ST_BASE_PA_H = 220,0,32,0 %; ! ! [IPF] IPB PA ! ************************ macro HWRPB$IQ_IPB_PA = 224,0,0,0 %; literal HWRPB$S_IPB_PA = 8; ! [IPF] IPB PA macro HWRPB$IL_IPB_PA_L = 224,0,32,0 %; macro HWRPB$IL_IPB_PA_H = 228,0,32,0 %; ! ! [IPF] IPB size ! *********** macro HWRPB$IQ_IPB_SIZE = 232,0,0,0 %; literal HWRPB$S_IPB_SIZE = 8; ! [IPF] IPB Size macro HWRPB$IL_IPB_SIZE_L = 232,0,32,0 %; macro HWRPB$IL_IPB_SIZE_H = 236,0,32,0 %; ! ! [IPF] PA of ACPI Tables RSDP - Root System Descriptor Pointer ! ************************ macro HWRPB$IQ_ACPI_RSDP_PA = 240,0,0,0 %; literal HWRPB$S_ACPI_RSDP_PA = 8; ! [IPF] PA of ACPI RSDP macro HWRPB$IL_ACPI_RSDP_PA_L = 240,0,32,0 %; macro HWRPB$IL_ACPI_RSDP_PA_H = 244,0,32,0 %; ! ! [IPF] PA of ACPI Tables HCDP - Headless Console Debug Port structure ! ************************ macro HWRPB$IQ_ACPI_HCDP_PA = 248,0,0,0 %; literal HWRPB$S_ACPI_HCDP_PA = 8; ! [IPF] PA of ACPI HCDP macro HWRPB$IL_ACPI_HCDP_PA_L = 248,0,32,0 %; macro HWRPB$IL_ACPI_HCDP_PA_H = 252,0,32,0 %; ! ! [IPF] PA of EFI Memory Map ! ************************ macro HWRPB$IQ_MMAP_PA = 256,0,0,0 %; literal HWRPB$S_MMAP_PA = 8; ! [IPF] PA of EFI Memory Map macro HWRPB$IL_MMAP_PA_L = 256,0,32,0 %; macro HWRPB$IL_MMAP_PA_H = 260,0,32,0 %; ! ! [IPF] EFI Memory Map Size ! *********** macro HWRPB$IQ_MMAP_SIZE = 264,0,0,0 %; literal HWRPB$S_MMAP_SIZE = 8; ! [IPF] EFI Memory Map Size macro HWRPB$IL_MMAP_SIZE_L = 264,0,32,0 %; macro HWRPB$IL_MMAP_SIZE_H = 268,0,32,0 %; ! ! [IPF] EFI Memory Map Desc Entry Size ! *********** macro HWRPB$IQ_MMAP_ENTRY_SIZE = 272,0,0,0 %; literal HWRPB$S_MMAP_ENTRY_SIZE = 8; ! [IPF] EFI Memory Map Desc Entry Size macro HWRPB$IL_MMAP_ENTRY_SIZE_L = 272,0,32,0 %; macro HWRPB$IL_MMAP_ENTRY_SIZE_H = 276,0,32,0 %; ! ! [IPF] EFI Memory Map Key ! *********** macro HWRPB$IQ_MMAP_KEY = 280,0,0,0 %; literal HWRPB$S_MMAP_KEY = 8; ! [IPF] EFI Memory Map Key macro HWRPB$IL_MMAP_KEY_L = 280,0,32,0 %; macro HWRPB$IL_MMAP_KEY_H = 284,0,32,0 %; ! ! [IPF] EFI Memory Map Version ! *********** macro HWRPB$IL_MMAP_VERSION = 288,0,32,0 %; ! [IPF] EFI Memory Map Version macro HWRPB$IL_MMAP_RSVD = 292,0,32,0 %; ! [IPF] For alignment ! ! [IPF] CMD BUF size ! *********** macro HWRPB$IQ_CMD_BUF_SIZE = 296,0,0,0 %; literal HWRPB$S_CMD_BUF_SIZE = 8; ! [IPF] CMD_BUF Size macro HWRPB$IL_CMD_BUF_SIZE_L = 296,0,32,0 %; macro HWRPB$IL_CMD_BUF_SIZE_H = 300,0,32,0 %; ! ! [IPF] Console Command Line Buffer Area ! *********************************** macro HWRPB$IQ_CMD_BUF_OFFSET = 304,0,0,0 %; literal HWRPB$S_CMD_BUF_OFFSET = 8; ! [IPF] Offset to Cmd Buf Area macro HWRPB$IL_CMD_BUF_OFFSET_L = 304,0,32,0 %; macro HWRPB$IL_CMD_BUF_OFFSET_H = 308,0,32,0 %; ! ! [IPF] BOOTDEV size ! *********** macro HWRPB$IQ_BOOTDEV_SIZE = 312,0,0,0 %; literal HWRPB$S_BOOTDEV_SIZE = 8; ! [IPF] BOOTDEV Size macro HWRPB$IL_BOOTDEV_SIZE_L = 312,0,32,0 %; macro HWRPB$IL_BOOTDEV_SIZE_H = 316,0,32,0 %; ! ! [IPF] Offset to Boot Device Path Descriptor ! ************************ macro HWRPB$IQ_BOOTDEV_OFFSET = 320,0,0,0 %; literal HWRPB$S_BOOTDEV_OFFSET = 8; ! [IPF] Offset to Boot Device Path Desc macro HWRPB$IL_BOOTDEV_OFFSET_L = 320,0,32,0 %; macro HWRPB$IL_BOOTDEV_OFFSET_H = 324,0,32,0 %; ! ! [IPF] Boot flags ! ************************ macro HWRPB$IQ_BOOT_FLAGS = 328,0,0,0 %; literal HWRPB$S_BOOT_FLAGS = 8; ! [IPF] Boot flags macro HWRPB$IL_BOOT_FLAGS_L = 328,0,32,0 %; macro HWRPB$IL_BOOT_FLAGS_H = 332,0,32,0 %; macro HWRPB_BOOT_FLAGS$V_ROOT = 332,16,16,0 %; literal HWRPB_BOOT_FLAGS$S_ROOT = 16; ! System root ! ! [IPF] Base address of Debug UART ! ************************ macro HWRPB$IQ_DEBUG_UART_PA = 336,0,0,0 %; literal HWRPB$S_DEBUG_UART_PA = 8; ! [IPF] Base address of Debug UART macro HWRPB$IL_DEBUG_UART_PA_L = 336,0,32,0 %; macro HWRPB$IL_DEBUG_UART_PA_H = 340,0,32,0 %; ! ! [IPF] Number of Boot Space Descs ! ************************ macro HWRPB$IQ_TR_COUNT = 344,0,0,0 %; literal HWRPB$S_TR_COUNT = 8; ! [IPF] # of Translation Registers & BOOTSPACE structs macro HWRPB$IL_TR_COUNT_L = 344,0,32,0 %; macro HWRPB$IL_TR_COUNT_H = 348,0,32,0 %; ! ! [IPF] Offset to Boot Space Descriptors, One per TR ! ************************ macro HWRPB$IQ_BOOTSPACE_OFFSET = 352,0,0,0 %; literal HWRPB$S_BOOTSPACE_OFFSET = 8; ! [IPF] Offset to first Boot Space Desc macro HWRPB$IL_BOOTSPACE_OFFSET_L = 352,0,32,0 %; macro HWRPB$IL_BOOTSPACE_OFFSET_H = 356,0,32,0 %; ! ! [IPF] Generic Address Structure from ACPI HCDP table ! ************************ macro HWRPB$IQ_UART_GAS = 360,0,0,0 %; literal HWRPB$S_UART_GAS = 8; macro HWRPB$B_ADDRESS_ID = 360,0,8,0 %; macro HWRPB$B_REGISTER_BIT_WIDTH = 361,0,8,0 %; macro HWRPB$B_REGISTER_BIT_OFFSET = 362,0,8,0 %; ! [IPF] Base address of UART ! ************************ macro HWRPB$IQ_UART_ADDRESS = 368,0,0,0 %; literal HWRPB$S_UART_ADDRESS = 8; macro HWRPB$IL_UART_ADDRESS_L = 368,0,32,0 %; macro HWRPB$IL_UART_ADDRESS_H = 372,0,32,0 %; ! ! [IPF] IPI Block Pointer ! ************************ macro HWRPB$PQ_PIB_BASE = 376,0,0,1 %; literal HWRPB$S_PIB_BASE = 8; ! PA of IPI Block macro HWRPB$PS_PIB_BASE_L = 376,0,32,1 %; ! ! [IPF] Offset to Config Tree ! ************************ macro HWRPB$IQ_FRU_OFFSET = 384,0,0,0 %; literal HWRPB$S_FRU_OFFSET = 8; ! [IPF] Offset to Config Tree macro HWRPB$IL_FRU_OFFSET_L = 384,0,32,0 %; macro HWRPB$IL_FRU_OFFSET_H = 388,0,32,0 %; macro HWRPB$IQ_CFG_OFFSET = 384,0,0,0 %; literal HWRPB$S_CFG_OFFSET = 8; ! [IPF] Offset to Config Tree macro HWRPB$IL_CFG_OFFSET_L = 384,0,32,0 %; macro HWRPB$IL_CFG_OFFSET_H = 388,0,32,0 %; ! ! Checksum of HWRPB ! ****************** macro HWRPB$IQ_CHKSUM = 392,0,0,0 %; literal HWRPB$S_CHKSUM = 8; ! Checksum of HWRPB macro HWRPB$IL_CHKSUM_L = 392,0,32,0 %; macro HWRPB$IL_CHKSUM_H = 396,0,32,0 %; ! ! RXRDY bitmask ! ************************ macro HWRPB$IQ_RXRDY = 400,0,0,0 %; literal HWRPB$S_RXRDY = 8; ! RXRDY bitmask macro HWRPB$IQ_RXRDY_OFFSET = 400,0,0,0 %; literal HWRPB$S_RXRDY_OFFSET = 8; ! Offset to RXRDY bitmask for ECO 123 macro HWRPB$IL_RXRDY_L = 400,0,32,0 %; macro HWRPB$IL_RXRDY_H = 404,0,32,0 %; ! ! TXRDY bitmask ! ************************ macro HWRPB$IQ_TXRDY = 408,0,0,0 %; literal HWRPB$S_TXRDY = 8; ! TXRDY bitmask macro HWRPB$IL_TXRDY_L = 408,0,32,0 %; macro HWRPB$V_TXRDY_SUMMARY = 408,0,1,0 %; ! ECO 123 - At least 1 bitmask is nonzero macro HWRPB$IL_TXRDY_H = 412,0,32,0 %; ! ! [IPF] IPF_BASE_OFFSET ! ************************ macro HWRPB$IQ_IPF_BASE_OFFSET = 416,0,0,0 %; literal HWRPB$S_IPF_BASE_OFFSET = 8; ! [IPF] Offset to IPF Base structure ! ! [IPF] BOOT_RENDEZ_VEC ! ************************ macro HWRPB$IQ_BOOT_RENDEZ_VEC = 424,0,0,0 %; literal HWRPB$S_BOOT_RENDEZ_VEC = 8; ! [IPF] SAL BOOT_RENDEZ vector ! ! [IPF] CONINDEV size ! *********** macro HWRPB$IQ_CONINDEV_SIZE = 432,0,0,0 %; literal HWRPB$S_CONINDEV_SIZE = 8; ! [IPF] CONINDEV Size macro HWRPB$IL_CONINDEV_SIZE_L = 432,0,32,0 %; macro HWRPB$IL_CONINDEV_SIZE_H = 436,0,32,0 %; ! ! [IPF] Offset to Conin Device Path Descriptor ! ************************ macro HWRPB$IQ_CONINDEV_OFFSET = 440,0,0,0 %; literal HWRPB$S_CONINDEV_OFFSET = 8; ! [IPF] Offset to Conin Device Path Desc macro HWRPB$IL_CONINDEV_OFFSET_L = 440,0,32,0 %; macro HWRPB$IL_CONINDEV_OFFSET_H = 444,0,32,0 %; ! ! [IPF] CONOUTDEV size ! *********** macro HWRPB$IQ_CONOUTDEV_SIZE = 448,0,0,0 %; literal HWRPB$S_CONOUTDEV_SIZE = 8; ! [IPF] CONOUTDEV Size macro HWRPB$IL_CONOUTDEV_SIZE_L = 448,0,32,0 %; macro HWRPB$IL_CONOUTDEV_SIZE_H = 452,0,32,0 %; ! ! [IPF] Offset to Conout Device Path Descriptor ! ************************ macro HWRPB$IQ_CONOUTDEV_OFFSET = 456,0,0,0 %; literal HWRPB$S_CONOUTDEV_OFFSET = 8; ! [IPF] Offset to Conout Device Path Desc macro HWRPB$IL_CONOUTDEV_OFFSET_L = 456,0,32,0 %; macro HWRPB$IL_CONOUTDEV_OFFSET_H = 460,0,32,0 %; ! ! [IPF] CONERRDEV size ! *********** macro HWRPB$IQ_CONERRDEV_SIZE = 464,0,0,0 %; literal HWRPB$S_CONERRDEV_SIZE = 8; ! [IPF] CONERRDEV Size macro HWRPB$IL_CONERRDEV_SIZE_L = 464,0,32,0 %; macro HWRPB$IL_CONERRDEV_SIZE_H = 468,0,32,0 %; ! ! [IPF] Offset to Conerr Device Path Descriptor ! ************************ macro HWRPB$IQ_CONERRDEV_OFFSET = 472,0,0,0 %; literal HWRPB$S_CONERRDEV_OFFSET = 8; ! [IPF] Offset to Conerr Device Path Desc macro HWRPB$IL_CONERRDEV_OFFSET_L = 472,0,32,0 %; macro HWRPB$IL_CONERRDEV_OFFSET_H = 476,0,32,0 %; ! ! [IPF] ALTDEV size ! *********** macro HWRPB$IQ_ALTDEV_SIZE = 480,0,0,0 %; literal HWRPB$S_ALTDEV_SIZE = 8; ! [IPF] ALTDEV Size macro HWRPB$IL_ALTDEV_SIZE_L = 480,0,32,0 %; macro HWRPB$IL_ALTDEV_SIZE_H = 484,0,32,0 %; ! ! [IPF] Offset to Alt Device Path Descriptor ! ************************ macro HWRPB$IQ_ALTDEV_OFFSET = 488,0,0,0 %; literal HWRPB$S_ALTDEV_OFFSET = 8; ! [IPF] Offset to Alt Device Path Desc macro HWRPB$IL_ALTDEV_OFFSET_L = 488,0,32,0 %; macro HWRPB$IL_ALTDEV_OFFSET_H = 492,0,32,0 %; ! ! [IPF] ACPI HCDP Function for console identification ! ************************ macro HWRPB$IQ_CONS_FUNCTION = 496,0,0,0 %; literal HWRPB$S_CONS_FUNCTION = 8; macro HWRPB$B_FUNCTION = 496,0,8,0 %; ! Whole byte macro HWRPB$V_FUNCTION = 496,0,3,0 %; literal HWRPB$S_FUNCTION = 3; ! Function number macro HWRPB$V_RESERVED = 496,3,3,0 %; literal HWRPB$S_RESERVED = 3; macro HWRPB$V_INTR_FLAG = 496,6,1,0 %; ! Supports int if 1 macro HWRPB$V_PCI_DEVICE = 496,7,1,0 %; ! PCI device if 1 macro HWRPB$IQ_BOOTDEV_PCINODE = 504,0,0,0 %; literal HWRPB$S_BOOTDEV_PCINODE = 8; ! PCI node of boot dev macro HWRPB$IL_BOOTDEV_PCINODE_L = 504,0,32,0 %; macro HWRPB$V_FUNCT = 504,0,3,0 %; literal HWRPB$S_FUNCT = 3; macro HWRPB$V_DEVICE = 504,3,5,0 %; literal HWRPB$S_DEVICE = 5; macro HWRPB$V_BUS = 504,8,8,0 %; literal HWRPB$S_BUS = 8; macro HWRPB$V_HOSE = 504,16,8,0 %; literal HWRPB$S_HOSE = 8; macro HWRPB$IL_BOOTDEV_PCINODE_H = 508,0,32,0 %; ! ! [IPF] Size of Per-CPU SWIS data ! ********************** macro HWRPB$IQ_SWIS_SIZE = 512,0,0,0 %; literal HWRPB$S_SWIS_SIZE = 8; ! Size of Per-CPU SWIS data macro HWRPB$IL_SWIS_SIZE_L = 512,0,32,0 %; macro HWRPB$IL_SWIS_SIZE_H = 516,0,32,0 %; ! ! [IPF] Offset to Per-CPU SWIS data ! ************************ macro HWRPB$IQ_SWIS_OFFSET = 520,0,0,0 %; literal HWRPB$S_SWIS_OFFSET = 8; ! Offset to Per-CPU SWIS data macro HWRPB$IL_SWIS_OFFSET_L = 520,0,32,0 %; macro HWRPB$IL_SWIS_OFFSET_H = 524,0,32,0 %; ! ! [IPF] MCA Error Record context ! ************************ macro HWRPB$IQ_MCA_ERROR_RECORD = 528,0,0,0 %; literal HWRPB$S_MCA_ERROR_RECORD = 8; ! Physical pointer to MCA error record buffer macro HWRPB$IQ_MCA_RECORD_SIZE_COUNT = 536,0,0,0 %; literal HWRPB$S_MCA_RECORD_SIZE_COUNT = 8; macro HWRPB$IL_MCA_RECORD_SIZE = 536,0,32,0 %; macro HWRPB$IL_MCA_RECORD_COUNT = 540,0,32,0 %; ! ! [IPF] INIT Error Record context ! ************************ macro HWRPB$IQ_INIT_ERROR_RECORD = 544,0,0,0 %; literal HWRPB$S_INIT_ERROR_RECORD = 8; ! Physical pointer to INIT error record buffer macro HWRPB$IQ_INIT_RECORD_SIZE_COUNT = 552,0,0,0 %; literal HWRPB$S_INIT_RECORD_SIZE_COUNT = 8; macro HWRPB$IL_INIT_RECORD_SIZE = 552,0,32,0 %; macro HWRPB$IL_INIT_RECORD_COUNT = 556,0,32,0 %; ! ! [IPF] CMC Error Record context ! ************************ macro HWRPB$IQ_CMC_ERROR_RECORD = 560,0,0,0 %; literal HWRPB$S_CMC_ERROR_RECORD = 8; ! Physical pointer to CMC error record buffer macro HWRPB$IQ_CMC_RECORD_SIZE_COUNT = 568,0,0,0 %; literal HWRPB$S_CMC_RECORD_SIZE_COUNT = 8; macro HWRPB$IL_CMC_RECORD_SIZE = 568,0,32,0 %; macro HWRPB$IL_CMC_RECORD_COUNT = 572,0,32,0 %; ! ! [IPF] CPE Error Record context ! ************************ macro HWRPB$IQ_CPE_ERROR_RECORD = 576,0,0,0 %; literal HWRPB$S_CPE_ERROR_RECORD = 8; ! Physical pointer to CPE error record buffer macro HWRPB$IQ_CPE_RECORD_SIZE_COUNT = 584,0,0,0 %; literal HWRPB$S_CPE_RECORD_SIZE_COUNT = 8; macro HWRPB$IL_CPE_RECORD_SIZE = 584,0,32,0 %; macro HWRPB$IL_CPE_RECORD_COUNT = 588,0,32,0 %; ! ! Virtual Address of hardware interrupt handler PC ! ************************************************ macro HWRPB$IQ_HWINT_HANDLER_PC = 592,0,0,0 %; literal HWRPB$S_HWINT_HANDLER_PC = 8; ! VA of interrupt handler routine macro HWRPB$IL_HWINT_HANDLER_PC_L = 592,0,32,1 %; macro HWRPB$IL_HWINT_HANDLER_PC_H = 596,0,32,0 %; ! ! Virtual Address of hardware interrupt handler PC ! ************************************************ macro HWRPB$IQ_HWINT_HANDLER_GP = 600,0,0,0 %; literal HWRPB$S_HWINT_HANDLER_GP = 8; ! VA of interrupt handler routine macro HWRPB$IL_HWINT_HANDLER_GP_L = 600,0,32,1 %; macro HWRPB$IL_HWINT_HANDLER_GP_H = 604,0,32,0 %; ! ! [IPF] Console Data Log (CDL) context ! ************************ macro HWRPB$IQ_CDL_PA = 608,0,0,0 %; literal HWRPB$S_CDL_PA = 8; ! Physical pointer to CDL buffer macro HWRPB$IQ_CDL_SIZE_COUNT = 616,0,0,0 %; literal HWRPB$S_CDL_SIZE_COUNT = 8; macro HWRPB$IL_CDL_SIZE = 616,0,32,0 %; macro HWRPB$IL_CDL_COUNT = 620,0,32,0 %; ! ! [IPF] UART PCI Config Address ! ************************ ! ! ========= ! NOTE: ! ========= ! ! This field is valid only when the ADDRESS_ID in the UART_GAS ! structure indicates that it is a PCI device with a PCI Config ! Header. ! ! The overlaid structure has the advantage of being cast as a ! PCI_NODE_NUMBER (see PCIDEF.SDL), since its bitfields are ! congruent to those in PCI_NODE_NUMBER. ! macro HWRPB$IQ_UART_PCICFG_ADDRESS = 624,0,0,0 %; literal HWRPB$S_UART_PCICFG_ADDRESS = 8; macro HWRPB$V_UART_PCICFG_FUNCTION = 624,0,3,0 %; literal HWRPB$S_UART_PCICFG_FUNCTION = 3; macro HWRPB$V_UART_PCICFG_DEVICE = 624,3,5,0 %; literal HWRPB$S_UART_PCICFG_DEVICE = 5; macro HWRPB$V_UART_PCICFG_BUS = 624,8,8,0 %; literal HWRPB$S_UART_PCICFG_BUS = 8; macro HWRPB$V_UART_PCICFG_OFFSET = 624,16,16,0 %; literal HWRPB$S_UART_PCICFG_OFFSET = 16; macro HWRPB$V_UART_PCICFG_SEGMENT = 628,0,8,0 %; literal HWRPB$S_UART_PCICFG_SEGMENT = 8; macro HWRPB$V_UART_PCICFG_RESERVED = 628,8,24,0 %; literal HWRPB$S_UART_PCICFG_RESERVED = 24; ! fPars Shared Hardware Assist (FSHWA) macro HWRPB$IQ_FSHWA_PA = 632,0,0,0 %; literal HWRPB$S_FSHWA_PA = 8; macro HWRPB$IL_FSHWA_PA_L = 632,0,32,0 %; macro HWRPB$IL_FSHWA_PA_H = 636,0,32,0 %; ! Counted string. Remote device name. Used for NISCA booting only. macro HWRPB$T_DEVICE_NAME = 640,0,0,0 %; literal HWRPB$S_DEVICE_NAME = 32; ! ! ***************************************************************** ! [IPF] VGA SPECIFIC FIELDS ! ***************************************************************** ! ! VGA PCI Config Address ! ====================== ! This structure can be cast as a PCI_NODE_NUMBER (see PCIDEF.SDL) ! macro HWRPB$IQ_VGA_PCICFG_ADDRESS = 672,0,0,0 %; literal HWRPB$S_VGA_PCICFG_ADDRESS = 8; macro HWRPB$V_VGA_PCICFG_FUNCTION = 672,0,3,0 %; literal HWRPB$S_VGA_PCICFG_FUNCTION = 3; macro HWRPB$V_VGA_PCICFG_DEVICE = 672,3,5,0 %; literal HWRPB$S_VGA_PCICFG_DEVICE = 5; macro HWRPB$V_VGA_PCICFG_BUS = 672,8,8,0 %; literal HWRPB$S_VGA_PCICFG_BUS = 8; macro HWRPB$V_VGA_PCICFG_OFFSET = 672,16,16,0 %; literal HWRPB$S_VGA_PCICFG_OFFSET = 16; macro HWRPB$V_VGA_PCICFG_SEGMENT = 676,0,8,0 %; literal HWRPB$S_VGA_PCICFG_SEGMENT = 8; macro HWRPB$V_VGA_PCICFG_RESERVED = 676,8,24,0 %; literal HWRPB$S_VGA_PCICFG_RESERVED = 24; ! ! ! Translation Offset for VGA MMIO space ! macro HWRPB$IQ_VGA_TRA_OFFSET = 680,0,0,0 %; literal HWRPB$S_VGA_TRA_OFFSET = 8; ! ! ! VGA Flag Bits ! macro HWRPB$IQ_VGA_FLAGS = 688,0,0,0 %; literal HWRPB$S_VGA_FLAGS = 8; macro HWRPB$V_VGA_CONSOLE = 688,0,1,0 %; macro HWRPB$V_VGA_RESERVED_FLAGS1 = 688,1,31,0 %; literal HWRPB$S_VGA_RESERVED_FLAGS1 = 31; macro HWRPB$V_VGA_RESERVED_FLAGS2 = 692,0,32,0 %; literal HWRPB$S_VGA_RESERVED_FLAGS2 = 32; ! ! ! Virtual address of a data structure containing VGA state and data ! used to preserve screen contents when moving from IPB environment ! to SYSBOOT. ! macro HWRPB$IQ_VGA_STATE_POINTER = 696,0,0,0 %; literal HWRPB$S_VGA_STATE_POINTER = 8; ! ! ! Size of the VGA State data structure. The size of the structure is ! needed by SYSBOOT for fixup of the VGA_STATE_POINTER when moving ! from the IPB environment to SYSBOOT. ! macro HWRPB$IQ_VGA_STATE_SIZE = 704,0,0,0 %; literal HWRPB$S_VGA_STATE_SIZE = 8; ! ! ! Reserved for VGA future needs. ! macro HWRPB$IQ_VGA_SPARE = 712,0,0,0 %; literal HWRPB$S_VGA_SPARE = 8; macro HWRPB$IQ_USB_FLAGS = 720,0,0,0 %; literal HWRPB$S_USB_FLAGS = 8; macro HWRPB$W_USB_VENDOR_ID = 720,0,16,0 %; macro HWRPB$W_USB_PRODUCT_ID = 722,0,16,0 %; macro HWRPB$B_USB_INTERFACE_CLASS = 724,0,8,0 %; macro HWRPB$B_USB_INTERFACE_SUBCLASS = 725,0,8,0 %; macro HWRPB$B_USB_INTERFACE_PROTOCOL = 726,0,8,0 %; macro HWRPB$B_USB_SERIALNUM_LEN = 727,0,8,0 %; macro HWRPB$B_USB_SERIALNUM = 728,0,0,0 %; literal HWRPB$S_USB_SERIALNUM = 256; ! ! [IPF] Deconfigured Error Record context ! ************************ macro HWRPB$IQ_DECON_ERROR_RECORD = 984,0,0,0 %; literal HWRPB$S_DECON_ERROR_RECORD = 8; ! Physical pointer to Deconfigured error record buffer macro HWRPB$IQ_DECON_RECORD_SIZE_CNT = 992,0,0,0 %; literal HWRPB$S_DECON_RECORD_SIZE_CNT = 8; macro HWRPB$IL_DECON_RECORD_SIZE = 992,0,32,0 %; macro HWRPB$IL_DECON_RECORD_COUNT = 996,0,32,0 %; ! ! System Serial Number - Physical version if applicable, null if not ! ********************** macro HWRPB$B_SYS_PHYS_SERIALNUM = 1000,0,0,0 %; literal HWRPB$S_SYS_PHYS_SERIALNUM = 16; ! Physical System Serial number ! ! InfoServer service - Bootstrap via Memory disk ! ************************************************* macro HWRPB$B_SERVICE_NAME = 1016,0,0,0 %; literal HWRPB$S_SERVICE_NAME = 256; ! Service Name ! ! ************************** END OF HWRPB PRIMARY STRUCTURE ***************************** ! literal HWRPB$C_LENGTH = 1272; ! Length of HWRPB literal HWRPB$K_LENGTH = 1272; ! Length of HWRPB literal HWRPB$S_HWRPBDEF = 1272; ! Old size name - synonym ! ! HWPCB structure in Per-CPU slot definitions - zero relative ! ************************************************************ literal HWPCB$M_ASTEN = %X'F'; literal HWPCB$M_ASTSR = %X'F0'; literal HWPCB$M_ASTEN_KEN = %X'1'; literal HWPCB$M_ASTEN_EEN = %X'2'; literal HWPCB$M_ASTEN_SEN = %X'4'; literal HWPCB$M_ASTEN_UEN = %X'8'; literal HWPCB$M_ASTSR_KPD = %X'10'; literal HWPCB$M_ASTSR_EPD = %X'20'; literal HWPCB$M_ASTSR_SPD = %X'40'; literal HWPCB$M_ASTSR_UPD = %X'80'; literal HWPCB$M_UP = %X'4'; literal HWPCB$M_AC = %X'8'; literal HWPCB$M_MFL = %X'10'; literal HWPCB$M_MFH = %X'20'; literal HWPCB$M_DFH = %X'80000'; literal HWPCB$S_HWPCB = 352; ! ! Base of HWPCB ! ************** macro HWPCB$IQ_HWPCB_BASE = 0,0,0,0 %; literal HWPCB$S_HWPCB_BASE = 8; ! Base of HWPCB ! ! Kernel Stack Pointer ! ********************* macro HWPCB$IQ_KSP = 0,0,0,0 %; literal HWPCB$S_KSP = 8; ! Kernel stack pointer macro HWPCB$IL_KSP_L = 0,0,32,0 %; macro HWPCB$IL_KSP_H = 4,0,32,0 %; ! ! Executive Stack Pointer ! ************************ macro HWPCB$IQ_ESP = 8,0,0,0 %; literal HWPCB$S_ESP = 8; ! Executive stack pointer macro HWPCB$IL_ESP_L = 8,0,32,0 %; macro HWPCB$IL_ESP_H = 12,0,32,0 %; ! ! Supervisor Stack Pointer ! ************************* macro HWPCB$IQ_SSP = 16,0,0,0 %; literal HWPCB$S_SSP = 8; ! Supervisor stack pointer macro HWPCB$IL_SSP_L = 16,0,32,0 %; macro HWPCB$IL_SSP_H = 20,0,32,0 %; ! ! User Stack Pointer ! ******************* macro HWPCB$IQ_USP = 24,0,0,0 %; literal HWPCB$S_USP = 8; ! User stack pointer macro HWPCB$IL_USP_L = 24,0,32,0 %; macro HWPCB$IL_USP_H = 28,0,32,0 %; ! ! Kernel Register Stack Engine ! *************************** macro HWPCB$Q_KPFS = 32,0,0,0 %; literal HWPCB$S_KPFS = 8; ! PFS of thread switched out macro HWPCB$Q_KRNAT = 40,0,0,0 %; literal HWPCB$S_KRNAT = 8; ! RNAT of thread switched out macro HWPCB$PQ_KBSP = 48,0,0,1 %; literal HWPCB$S_KBSP = 8; ! Kernel Backing Store Pointer ! ! Exec Register Stack Engine ! *************************** macro HWPCB$PQ_EBSP = 56,0,0,1 %; literal HWPCB$S_EBSP = 8; ! Exec Backing Store Pointer ! ! Supervisor Register Stack Engine ! *************************** macro HWPCB$PQ_SBSP = 64,0,0,1 %; literal HWPCB$S_SBSP = 8; ! Supervisor Backing Store Pointer ! ! User Register Stack Engine ! *************************** macro HWPCB$PQ_UBSP = 72,0,0,1 %; literal HWPCB$S_UBSP = 8; ! User Backing Store Pointer ! ! Page Table Bases ! ************************* macro HWPCB$IQ_PTBR = 80,0,0,0 %; literal HWPCB$S_PTBR = 128; ! (Dimension is really 8,2: Page Table Base Register for 2 sections in each region ! ! Region IDs/ASNs ! *************************** macro HWPCB$IQ_ASN = 208,0,0,0 %; literal HWPCB$S_ASN = 64; ! Region IDs for each region ! ! AST Enable and Summary Registers (ASTSR and ASTEN) ! *************************************************** macro HWPCB$IQ_ASTSR_ASTEN = 272,0,0,0 %; literal HWPCB$S_ASTSR_ASTEN = 8; ! ASTSR / ASTEN quadword macro HWPCB$IL_AST_L = 272,0,32,0 %; macro HWPCB$IL_AST_H = 276,0,32,0 %; macro HWPCB$V_ASTEN = 272,0,4,0 %; literal HWPCB$S_ASTEN = 4; ! AST Enable Register macro HWPCB$V_ASTSR = 272,4,4,0 %; literal HWPCB$S_ASTSR = 4; ! AST Pending Summary Register macro HWPCB$V_ASTEN_KEN = 272,0,1,0 %; ! Kernel AST Enable = 1 macro HWPCB$V_ASTEN_EEN = 272,1,1,0 %; ! Executive AST Enable = 1 macro HWPCB$V_ASTEN_SEN = 272,2,1,0 %; ! Supervisor AST Enable = 1 macro HWPCB$V_ASTEN_UEN = 272,3,1,0 %; ! User AST Enable = 1 macro HWPCB$V_ASTSR_KPD = 272,4,1,0 %; ! Kernel AST Pending = 1 macro HWPCB$V_ASTSR_EPD = 272,5,1,0 %; ! Executive AST Pending = 1 macro HWPCB$V_ASTSR_SPD = 272,6,1,0 %; ! Supervisor AST Pending = 1 macro HWPCB$V_ASTSR_UPD = 272,7,1,0 %; ! User AST Pending = 1 ! ! Process Attributes Section ! *************************** macro HWPCB$IQ_PAS = 280,0,0,0 %; literal HWPCB$S_PAS = 8; ! Floating Point Disable / modified / UP / DATFX macro HWPCB$IL_PAS_L = 280,0,32,0 %; macro HWPCB$IL_PAS_H = 284,0,32,0 %; macro HWPCB$V_UP = 280,2,1,0 %; ! User Performance Monitor Enable macro HWPCB$V_AC = 280,3,1,0 %; ! Data Alignment Check Enable macro HWPCB$V_MFL = 280,4,1,0 %; ! Low FPRs modified macro HWPCB$V_MFH = 280,5,1,0 %; ! High FPRs modified macro HWPCB$V_DFH = 280,19,1,0 %; ! High Floating Point Disable ! fill_44 bitfield length 44 fill; ! ! Cycle Counter ! ************** macro HWPCB$IQ_CC = 288,0,0,0 %; literal HWPCB$S_CC = 8; ! Cycle Counter macro HWPCB$IL_CC_L = 288,0,32,0 %; macro HWPCB$IL_CC_H = 292,0,32,0 %; ! ! Process Unique Value - IA64 Thread Pointer (R13) ! ********************** macro HWPCB$IQ_UNQ = 296,0,0,0 %; literal HWPCB$S_UNQ = 8; ! Process Unique Value macro HWPCB$IL_UNQ_L = 296,0,32,0 %; macro HWPCB$IL_UNQ_H = 300,0,32,0 %; ! ! Previous mode ! ********************** macro HWPCB$B_PMOD = 304,0,8,0 %; ! Previous mode macro HWPCB$b_reserved_1 = 305,0,0,1 %; literal HWPCB$s_reserved_1 = 7; ! Reserved for future use ! ! Reserved for PALcode scratch ! ***************************** macro HWPCB$IQ_PAL_RSVD = 312,0,0,1 %; literal HWPCB$S_PAL_RSVD = 40; ! Reserved for PAL scratch ! literal HWPCB$C_LENGTH = 352; ! Full length of HWPCB$ literal HWPCB$K_LENGTH = 352; ! Full length of HWPCB$ literal HWPCB$S_HWPCBDEF = 352; ! Old size name - synonym ! ! Per-CPU slot definitions ! ************************* literal SLOT$M_BIP = %X'1'; literal SLOT$M_RC = %X'2'; literal SLOT$M_PA = %X'4'; literal SLOT$M_PP = %X'8'; literal SLOT$M_OH = %X'10'; literal SLOT$M_CV = %X'20'; literal SLOT$M_PV = %X'40'; literal SLOT$M_PMV = %X'80'; literal SLOT$M_PL = %X'100'; literal SLOT$M_RIP = %X'200'; literal SLOT$M_HLTREQ = %X'FF0000'; literal HWRPB_HALT$K_NO_ACTION = 0; ! Just Halt literal HWRPB_HALT$K_SAVE_RESTORE_TERM = 1; ! Save or restore term literal HWRPB_HALT$K_COLD_REBOOT = 2; ! Cold bootstrap request literal HWRPB_HALT$K_WARM_REBOOT = 3; ! Warm bootstrap request literal HWRPB_HALT$K_REMAIN_HALTED = 4; ! Don't restart literal HWRPB_HALT$K_POWEROFF = 5; ! Power-off system ! reserved literal HWRPB_HALT$K_MIGRATE = 7; ! Galaxy CPU migration ! reserved literal HWRPB_HALT$K_BIB_STATE = 9; ! Invoke ACPI state for BIB state literal SLOT$M_PARTID = %X'FFFF'; literal HWRPB_PAL_REV$K_IPF = 32; ! Standard PAL code ! literal HWRPB_CPU_TYPE$K_MERCED = 7; literal HWRPB_CPU_TYPE$K_MCKINLEY = 31; ! literal SLOT$M_VAX_FP = %X'1'; literal SLOT$M_IEEE_FP = %X'2'; literal SLOT$M_PE = %X'4'; literal HWRPB$K_RESTART = 0; ! Btstrap,procr strt, or pwrfl. literal HWRPB$K_CRASH_CMD = 1; ! Crash via cosole request literal HWRPB$K_KSP_NOT_VALID = 2; ! Kernel stack not valid halt literal HWRPB$K_INVALID_SCBB = 3; ! Invalid SCB Base register literal HWRPB$K_INVALID_PTBR = 4; ! Invalid Page Table Base Reg. literal HWRPB$K_CALL_PAL_HALT = 5; ! Processor executed in ker. mode literal HWRPB$K_DOUBLE_ERROR = 6; ! Double error abort literal HWRPB$K_MCHECK_IN_PAL = 7; ! Mcheck in PAL environment literal HWRPB$K_LAST_HALT_REASON = 7; ! literal SLOT$M_MCES_MCA = %X'1'; literal SLOT$M_MCES_CPE = %X'2'; literal SLOT$M_MCES_CMC = %X'4'; literal SLOT$M_MCES_CPE_DIS = %X'8'; literal SLOT$M_MCES_CMC_DIS = %X'10'; literal SLOT$M_MCES_INIT = %X'20'; literal SLOT$S_CPU_SLOT = 2120; ! ! Restart/Boot HWPCB ! ******************* macro SLOT$IQ_HWPCB = 0,0,0,0 %; literal SLOT$S_HWPCB = 384; ! HWPCB rounded to multiple of 128 ! ! Physical offset from slot to HWRPB ! *********************************** macro SLOT$IQ_HWRPB_OFFSET = 384,0,0,0 %; literal SLOT$S_HWRPB_OFFSET = 8; ! Offset to HWRPB ! ! Per-CPU state bits ! ******************* macro SLOT$IQ_STATE = 392,0,0,0 %; literal SLOT$S_STATE = 8; ! Per-CPU state bits macro SLOT$IL_STATE = 392,0,32,0 %; macro SLOT$V_BIP = 392,0,1,0 %; ! Bootstrap in progress macro SLOT$V_RC = 392,1,1,0 %; ! Restart capable macro SLOT$V_PA = 392,2,1,0 %; ! Processor available macro SLOT$V_PP = 392,3,1,0 %; ! Processor present macro SLOT$V_OH = 392,4,1,0 %; ! Operator halted macro SLOT$V_CV = 392,5,1,0 %; ! Context valid macro SLOT$V_PV = 392,6,1,0 %; ! PAL code valid macro SLOT$V_PMV = 392,7,1,0 %; ! PAL code memory valid macro SLOT$V_PL = 392,8,1,0 %; ! PAL code loaded macro SLOT$V_RIP = 392,9,1,0 %; ! Rendezvous in progress macro SLOT$V_HLTREQ = 392,16,8,0 %; literal SLOT$S_HLTREQ = 8; macro SLOT$IL_STATE_H = 396,0,32,0 %; macro SLOT$V_PARTID = 396,0,16,0 %; literal SLOT$S_PARTID = 16; ! ! Physical Address of SAL memory space ! ****************************************** macro SLOT$IQ_SAL_MEM_PA = 400,0,0,0 %; literal SLOT$S_SAL_MEM_PA = 8; ! Phys addr of SAL memory macro SLOT$IL_SAL_MEM_PA_L = 400,0,32,0 %; macro SLOT$IL_SAL_MEM_PA_H = 404,0,32,0 %; ! ! Physical Address of PAL memory space ! ***************************************** macro SLOT$IQ_PAL_MEM_PA = 408,0,0,0 %; literal SLOT$S_PAL_MEM_PA = 8; ! Phys addr of PAL memory macro SLOT$IL_PAL_MEM_PA_L = 408,0,32,0 %; macro SLOT$IL_PAL_MEM_PA_H = 412,0,32,0 %; ! ! PALcode revision required by processor ! *************************************** macro SLOT$IQ_PAL_REV = 416,0,0,0 %; literal SLOT$S_PAL_REV = 8; ! Revision of PAL code required macro SLOT$IL_PAL_REV_L = 416,0,32,0 %; macro SLOT$B_PAL_MIN_REV = 416,0,8,0 %; ! PAL code minor revision macro SLOT$B_PAL_MAJ_REV = 417,0,8,0 %; ! PAL code major revision macro SLOT$B_PAL_VAR = 418,0,8,0 %; ! PAL code variation macro SLOT$IL_PAL_REV_H = 420,0,32,0 %; macro SLOT$IW_PAL_COMPT = 420,0,16,0 %; ! PAL code compatibility macro SLOT$IW_MAX_SHARE = 422,0,16,0 %; ! Max number CPUs to share ! ! Processor Type ! *************** macro SLOT$IQ_CPU_TYPE = 424,0,0,0 %; literal SLOT$S_CPU_TYPE = 8; ! Processor type macro SLOT$IL_CPU_TYPE_L = 424,0,32,0 %; macro SLOT$IL_CPU_TYPE_H = 428,0,32,0 %; ! ! Processor Variation ! ******************** macro SLOT$IQ_CPU_VAR = 432,0,0,0 %; literal SLOT$S_CPU_VAR = 8; ! Processor variation macro SLOT$IL_CPU_VAR_L = 432,0,32,0 %; macro SLOT$V_VAX_FP = 432,0,1,0 %; ! VAX floating point macro SLOT$V_IEEE_FP = 432,1,1,0 %; ! IEEE floating point macro SLOT$V_PE = 432,2,1,0 %; ! Processor Eligibility macro SLOT$IL_CPU_VAR_H = 436,0,32,0 %; ! ! Processor Stepping Revision ! **************************** macro SLOT$IQ_CPU_REV = 440,0,0,0 %; literal SLOT$S_CPU_REV = 8; ! Processor revision macro SLOT$IL_CPU_REV_L = 440,0,32,0 %; macro SLOT$IL_CPU_REV_H = 444,0,32,0 %; ! ! CPU serial number ! ****************** macro SLOT$B_CPU_SERIALNUM = 448,0,0,0 %; literal SLOT$S_CPU_SERIALNUM = 16; ! CPU Serial number ! ! Physical Address of logout area ! ******************************** macro SLOT$IQ_LOGOUT_PA = 464,0,0,0 %; literal SLOT$S_LOGOUT_PA = 8; ! Physical Addr of logout area macro SLOT$IL_LOGOUT_PA_L = 464,0,32,0 %; macro SLOT$IL_LOGOUT_PA_H = 468,0,32,0 %; ! ! Size of logout area ! ******************** macro SLOT$IQ_LOGOUT_LEN = 472,0,0,0 %; literal SLOT$S_LOGOUT_LEN = 8; ! Size of logout area macro SLOT$IL_LOGOUT_LEN_L = 472,0,32,0 %; macro SLOT$IL_LOGOUT_LEN_H = 476,0,32,0 %; ! ! Halt PCBB ! ********** macro SLOT$IQ_HALT_PCBB = 480,0,0,0 %; literal SLOT$S_HALT_PCBB = 8; ! Halt PCBB macro SLOT$IL_HALT_PCBB_L = 480,0,32,0 %; macro SLOT$IL_HALT_PCBB_H = 484,0,32,0 %; ! ! Halt PC ! ******** macro SLOT$IQ_HALT_PC = 488,0,0,0 %; literal SLOT$S_HALT_PC = 8; ! Halt PC macro SLOT$IL_HALT_PC_L = 488,0,32,0 %; macro SLOT$IL_HALT_PC_H = 492,0,32,0 %; ! ! Halt PS ! ******** macro SLOT$IQ_HALT_PS = 496,0,0,0 %; literal SLOT$S_HALT_PS = 8; ! Halt PS macro SLOT$IL_HALT_PS_L = 496,0,32,0 %; macro SLOT$IL_HALT_PS_H = 500,0,32,0 %; ! ! Halt Argument List ! ******************* macro SLOT$IQ_HALT_ARG = 504,0,0,0 %; literal SLOT$S_HALT_ARG = 8; ! Halt Argument List macro SLOT$IL_HALT_ARG_L = 504,0,32,0 %; macro SLOT$IL_HALT_ARG_H = 508,0,32,0 %; ! ! Halt Return Address ! ******************** macro SLOT$IQ_HALT_RET = 512,0,0,0 %; literal SLOT$S_HALT_RET = 8; ! Halt Return Address macro SLOT$IL_HALT_RET_L = 512,0,32,0 %; macro SLOT$IL_HALT_RET_H = 516,0,32,0 %; ! ! Halt Procedure Value ! ********************* macro SLOT$IQ_HALT_PV = 520,0,0,0 %; literal SLOT$S_HALT_PV = 8; ! Halt PV macro SLOT$IL_HALT_PV_L = 520,0,32,0 %; macro SLOT$IL_HALT_PV_H = 524,0,32,0 %; ! ! Halt Code ! ********** macro SLOT$IQ_HALTCODE = 528,0,0,0 %; literal SLOT$S_HALTCODE = 8; ! Halt code macro SLOT$IL_HALTCODE_L = 528,0,32,0 %; macro SLOT$IL_HALTCODE_H = 532,0,32,0 %; ! ! Reserved for Software ! ********************** macro SLOT$IQ_SOFT_FLAGS = 536,0,0,0 %; literal SLOT$S_SOFT_FLAGS = 8; ! Reserved to software macro SLOT$IL_SOFT_FLAGS_L = 536,0,32,0 %; macro SLOT$IL_SOFT_FLAGS_H = 540,0,32,0 %; ! ! Interprocessor Console Buffer Area ! *********************************** macro SLOT$B_INCON_BUF_AREA = 544,0,0,0 %; literal SLOT$S_INCON_BUF_AREA = 168; ! SMP Console Buf Area macro SLOT$IL_RXLEN = 544,0,32,0 %; macro SLOT$IL_TXLEN = 548,0,32,0 %; macro SLOT$B_RXBUFFER = 552,0,0,0 %; literal SLOT$S_RXBUFFER = 80; macro SLOT$B_TXBUFFER = 632,0,0,0 %; literal SLOT$S_TXBUFFER = 80; ! ! The next 16 quadwords are reserved for the ! "PALcode Revisions Available Block". ! The format of the first quadword is platform specific. ! The format of each subsequent quadword follows the ! PALcode revision field (SLOT[168]) ! macro SLOT$Q_PAL_REV_AVAIL = 712,0,0,0 %; literal SLOT$S_PAL_REV_AVAIL = 128; ! PALcode Revisions Available Block ! ! Processor Software Compatibility ! ********************************* macro SLOT$IQ_CPU_SW_COMP = 840,0,0,0 %; literal SLOT$S_CPU_SW_COMP = 8; ! Processor software compatibility macro SLOT$IL_CPU_SW_COMP_L = 840,0,32,0 %; macro SLOT$IL_CPU_SW_COMP_H = 844,0,32,0 %; macro SLOT$IQ_CONSOLE_DATA_PA = 848,0,0,0 %; literal SLOT$S_CONSOLE_DATA_PA = 8; ! Console frame data buffer base PA macro SLOT$IL_CONSOLE_DATA_PA_L = 848,0,32,0 %; macro SLOT$IL_CONSOLE_DATA_PA_H = 852,0,32,0 %; macro SLOT$IQ_CONSOLE_DATA_SIZE = 856,0,0,0 %; literal SLOT$S_CONSOLE_DATA_SIZE = 8; ! Console frame data buffer length macro SLOT$IL_CONSOLE_DATA_SIZE_L = 856,0,32,0 %; macro SLOT$IL_CONSOLE_DATA_SIZE_H = 860,0,32,0 %; ! ! Cache Information ! ******************************************* macro SLOT$IQ_CPU_CACHE = 864,0,0,0 %; literal SLOT$S_CPU_CACHE = 8; ! Cache Information macro SLOT$IL_CPU_CACHE_L = 864,0,32,0 %; ! CPU_CACHE_FIELD1 structure fill; ! CPU_CACHE_ASSOC_DEGREE byte unsigned; /* Degree of set associativity ! CPU_CACHE_FIELD2 structure fill; ! CPU_CACHE_WRITE_BACK bitfield mask; /* Write-back or Write-through ! CPU_CACHE_FILL1 bitfield dimension 7 fill; ! end CPU_CACHE_FIELD2; ! CPU_CACHE_BLOCK_SIZE integer_word unsigned; /* Size of individual cache block ! end CPU_CACHE_FIELD1; macro SLOT$IL_CPU_CACHE_H = 868,0,32,0 %; ! Total size of cache in kbytes ! ! Cycle Counter Frequency ! ************************ macro SLOT$IQ_CYCLE_COUNT_FREQ = 872,0,0,0 %; literal SLOT$S_CYCLE_COUNT_FREQ = 8; ! Cycle counter frequency macro SLOT$IL_CYCLE_COUNT_FREQ_L = 872,0,32,0 %; macro SLOT$IL_CYCLE_COUNT_FREQ_H = 876,0,32,0 %; ! ! Clock Interrupt Frequency ! ************************** macro SLOT$IQ_CLOCK_INT_FREQ = 880,0,0,0 %; literal SLOT$S_CLOCK_INT_FREQ = 8; ! Clock interrupt frequency macro SLOT$IL_CLOCK_INT_FREQ_L = 880,0,32,0 %; macro SLOT$IL_CLOCK_INT_FREQ_H = 884,0,32,0 %; ! ! ITC Frequency ! ************************ macro SLOT$IQ_ITC_FREQ = 888,0,0,0 %; literal SLOT$S_ITC_FREQ = 8; ! Cycle counter frequency ! ! LID - IPF CPU Local ID ! ************************ macro SLOT$IQ_LID = 896,0,0,0 %; literal SLOT$S_LID = 8; ! CPU Local ID used for interrupt generation ! *************CPU register init values******************************** ! ! Translation buffer registers ! ************************************* macro SLOT$Q_TBREG_INIT = 904,0,0,0 %; literal SLOT$S_TBREG_INIT = 64; ! Values to stuff into TB registers (0=unused) ! ! Kernel Register Values for this CPU ! ************************************* macro SLOT$Q_KREG_INIT = 968,0,0,0 %; literal SLOT$S_KREG_INIT = 64; ! Values to stuff into kernel registers (0=unused) ! ! Interrupt Vector Table Address ! ************************************* macro SLOT$PQ_IVT_INIT = 1032,0,0,1 %; literal SLOT$S_IVT_INIT = 8; ! VA of the interrupt vector table for this CPU ! ! Virtual Hash Page Table for this CPU ! ************************************* macro SLOT$IQ_SWIS_OFFSET = 1040,0,0,0 %; literal SLOT$S_SWIS_OFFSET = 8; ! VA of VHPT for this CPU (0 means VHPT is disabled) ! ************************************************************************ ! ! Interrupt Stack Bases ! ************************************* macro SLOT$Q_ISP_BASE = 1048,0,0,0 %; literal SLOT$S_ISP_BASE = 8; ! The interrupt stack pointer base macro SLOT$Q_IBSP_BASE = 1056,0,0,0 %; literal SLOT$S_IBSP_BASE = 8; ! The interrupt stack RSE backing store pointer base ! ************************************************************************ ! ! Obsolete SWIS cells now defined in SWISDEF ! ******************************************* macro SLOT$IQ_SWIS_PRIVATE = 1064,0,0,1 %; literal SLOT$S_SWIS_PRIVATE = 400; ! Reserved for SWIS private storage macro SLOT$IQ_FPSWA_PA = 1464,0,0,0 %; literal SLOT$S_FPSWA_PA = 8; ! Floating point SW Assist macro SLOT$IL_FPSWA_PA_L = 1464,0,32,0 %; macro SLOT$IL_FPSWA_PA_H = 1468,0,32,0 %; ! ! ITC Drift value ! ************************ macro SLOT$IQ_ITC_DRIFT = 1472,0,0,0 %; literal SLOT$S_ITC_DRIFT = 8; ! Hardware drift in ppm clock ticks ! ! ITR and DTR register arrays to be initialized on restart operations ! ************************************* macro SLOT$Q_RESTART_ITR_ARRAY = 1480,0,0,0 %; literal SLOT$S_RESTART_ITR_ARRAY = 256; ! 4 quads for each of 8 minimum TRs macro SLOT$Q_RESTART_DTR_ARRAY = 1736,0,0,0 %; literal SLOT$S_RESTART_DTR_ARRAY = 256; ! 4 quads for each of 8 minimum TRs ! ! Stack pointers for hardware interrupt events ! ********************************************* macro SLOT$PQ_MCA_KSP = 1992,0,0,1 %; literal SLOT$S_MCA_KSP = 8; ! MCA Kernel Stack macro SLOT$PQ_INIT_KSP = 2000,0,0,1 %; literal SLOT$S_INIT_KSP = 8; ! Init Kernel Stack macro SLOT$PQ_CMC_KSP = 2008,0,0,1 %; literal SLOT$S_CMC_KSP = 8; ! CMC Kernel Stack macro SLOT$PQ_CPE_KSP = 2016,0,0,1 %; literal SLOT$S_CPE_KSP = 8; ! CPE Kernel Stack macro SLOT$PQ_MCA_BSP = 2024,0,0,1 %; literal SLOT$S_MCA_BSP = 8; ! MCA Backing Store Pointer macro SLOT$PQ_INIT_BSP = 2032,0,0,1 %; literal SLOT$S_INIT_BSP = 8; ! Init Backing Store Pointer macro SLOT$PQ_CMC_BSP = 2040,0,0,1 %; literal SLOT$S_CMC_BSP = 8; ! CMC Backing Store Pointer macro SLOT$PQ_CPE_BSP = 2048,0,0,1 %; literal SLOT$S_CPE_BSP = 8; ! CPE Backing Store Pointer ! ! Emulated Machine Check Error Summary cell (MCES) ! ********************************************* macro SLOT$Q_MCES = 2056,0,0,0 %; literal SLOT$S_MCES = 8; ! Machine Check Error Summary macro SLOT$V_MCES_MCA = 2056,0,1,0 %; macro SLOT$V_MCES_CPE = 2056,1,1,0 %; macro SLOT$V_MCES_CMC = 2056,2,1,0 %; macro SLOT$V_MCES_CPE_DIS = 2056,3,1,0 %; macro SLOT$V_MCES_CMC_DIS = 2056,4,1,0 %; macro SLOT$V_MCES_INIT = 2056,5,1,0 %; ! ! ACPI Processor Identifier ! ********************************************* macro SLOT$IQ_ACPI_ID = 2064,0,0,0 %; literal SLOT$S_ACPI_ID = 8; macro SLOT$IL_ACPI_ID_L = 2064,0,32,0 %; macro SLOT$IL_ACPI_ID_H = 2068,0,32,0 %; ! ! ACPI Processor Unique Identifier ! ********************************************* macro SLOT$PQ_ACPI_UID = 2072,0,0,1 %; literal SLOT$S_ACPI_UID = 8; macro SLOT$PS_ACPI_UID_L = 2072,0,32,1 %; ! ! Handle to Processor Object in ACPI Namespace ! ********************************************* macro SLOT$IQ_ACPI_HANDLE = 2080,0,0,0 %; literal SLOT$S_ACPI_HANDLE = 8; ! ! System Firmware Revision ! ********************************************* macro SLOT$IQ_SYS_FW_REV = 2088,0,0,0 %; literal SLOT$S_SYS_FW_REV = 8; macro SLOT$IW_SYS_FW_MIN_REV = 2088,0,16,0 %; macro SLOT$IW_SYS_FW_MAJ_REV = 2090,0,16,0 %; ! ! Baseboard Management Controller (BMC) Firmware Revision ! ********************************************* macro SLOT$IQ_BMC_FW_REV = 2096,0,0,0 %; literal SLOT$S_BMC_FW_REV = 8; macro SLOT$IW_BMC_FW_MIN_REV = 2096,0,16,0 %; macro SLOT$IW_BMC_FW_MAJ_REV = 2098,0,16,0 %; ! ! Management Port (MP) Firmware Revision ! ********************************************* macro SLOT$IQ_MP_FW_REV = 2104,0,0,0 %; literal SLOT$S_MP_FW_REV = 8; macro SLOT$IW_MP_FW_MIN_REV = 2104,0,16,0 %; macro SLOT$IW_MP_FW_MAJ_REV = 2106,0,16,0 %; ! ! Base Processor Frequency ! ************************ macro SLOT$IQ_BASE_PROC_FREQ = 2112,0,0,0 %; literal SLOT$S_BASE_PROC_FREQ = 8; ! true max CPU speed ! ! Length of SLOT$ is defined to be rounded to nearest 128 bytes ! literal SLOT$C_LENGTH = 2176; literal SLOT$K_LENGTH = 2176; literal SLOT$S_SLOTDEF = 2120; ! Old size name, synonym ! ! Physical Memory Cluster Descriptor Table (MEMDSC) ! ************************************************** literal HWRPB_PMD$C_LENGTH = 24; ! Length of HWRPB_PMD$ literal HWRPB_PMD$K_LENGTH = 24; ! Length of HWRPB_PMD$ ! literal HWRPB_PMD$S_NULLPMDDEF = 80; ! Size of NULL memory descr. ! literal HWRPB_PMD$S_PMD = 136; ! ! Checksum of Memory Descriptor from MEMDSC+8 through MEMDSC_END ! *************************************************************** macro HWRPB_PMD$IQ_CHKSUM = 0,0,0,0 %; literal HWRPB_PMD$S_CHKSUM = 8; ! Checksum of PMD+8 to PMD+end macro HWRPB_PMD$IL_CHKSUM_L = 0,0,32,0 %; macro HWRPB_PMD$IL_CHKSUM_H = 4,0,32,0 %; ! ! Optional Implementation-Specific Data ! ************************************** macro HWRPB_PMD$IQ_OPT_DATA = 8,0,0,0 %; literal HWRPB_PMD$S_OPT_DATA = 8; ! Optional data macro HWRPB_PMD$IL_OPT_DATA_L = 8,0,32,0 %; macro HWRPB_PMD$IL_OPT_DATA_H = 12,0,32,0 %; ! ! Number of Memory Clusters in MEMDSC ! ************************************ macro HWRPB_PMD$IQ_CLUSTER_COUNT = 16,0,0,0 %; literal HWRPB_PMD$S_CLUSTER_COUNT = 8; ! Count of clusters present macro HWRPB_PMD$IL_CLUSTER_COUNT_L = 16,0,32,0 %; macro HWRPB_PMD$IL_CLUSTER_COUNT_H = 20,0,32,0 %; ! ! Physical Memory Region (PMR) ! ***************************** ! ! For system with PHYSICALLY DIS-CONTIGUOUS memory, PMR points to ! an array of Physical Memory Regions (PMR). ! macro HWRPB_PMD$IQ_PMR = 24,0,0,0 %; literal HWRPB_PMD$S_PMR = 8; ! Start of first region macro HWRPB_PMD$IL_PMR_L = 24,0,32,0 %; macro HWRPB_PMD$IL_PMR_H = 28,0,32,0 %; ! ! For system with PHYSICALLY CONTIGUOUS memory, there are only two regions ! defined. The first region describes memory in use by the console, and the ! second region describes memory for use by the system. ! macro HWRPB_PMD$IQ_CN_PFN_START = 24,0,0,0 %; literal HWRPB_PMD$S_CN_PFN_START = 8; ! Start PFN of console region macro HWRPB_PMD$IL_CN_PFN_START_L = 24,0,32,0 %; macro HWRPB_PMD$IL_CN_PFN_START_H = 28,0,32,0 %; ! ! For system with DYNAMIC memory descriptors, there is only one region defined. It is a ! NULL cluster descriptor. It describes the listheads of shared and private memory cluster ! descriptors. The first field which is normally the PFN_START field, must be set to -1. macro HWRPB_PMD$IQ_NULL_MBMO = 24,0,0,1 %; literal HWRPB_PMD$S_NULL_MBMO = 8; ! Must be minus one macro HWRPB_PMD$IL_NULL_MBMO_L = 24,0,32,1 %; macro HWRPB_PMD$IL_NULL_MBMO_H = 28,0,32,1 %; ! ! Number of Page Frame Numbers (PFNs) in the region ! ************************************************** macro HWRPB_PMD$IQ_CN_PFN_COUNT = 32,0,0,0 %; literal HWRPB_PMD$S_CN_PFN_COUNT = 8; ! Number of PFNs in region macro HWRPB_PMD$IL_CN_PFN_COUNT_L = 32,0,32,0 %; macro HWRPB_PMD$IL_CN_PFN_COUNT_H = 36,0,32,0 %; ! ! Must be zero field in NULL cluster descriptor ! ********************************************** macro HWRPB_PMD$IQ_NULL_MBZ = 32,0,0,1 %; literal HWRPB_PMD$S_NULL_MBZ = 8; ! Must be zero macro HWRPB_PMD$IL_NULL_MBZ_L = 32,0,32,1 %; macro HWRPB_PMD$IL_NULL_MBZ_H = 36,0,32,1 %; ! ! Number of tested PFNs in the region ! ************************************ macro HWRPB_PMD$IQ_CN_TEST_COUNT = 40,0,0,0 %; literal HWRPB_PMD$S_CN_TEST_COUNT = 8; ! Num. of tested PFNs in region macro HWRPB_PMD$IL_CN_TEST_COUNT_L = 40,0,32,0 %; macro HWRPB_PMD$IL_CN_TEST_COUNT_H = 44,0,32,0 %; ! ! Must be zero field in NULL cluster descriptor ! ********************************************** macro HWRPB_PMD$IQ_NULL_TEST_MBZ = 40,0,0,1 %; literal HWRPB_PMD$S_NULL_TEST_MBZ = 8; ! Must be zero macro HWRPB_PMD$IL_NULL_TEST_MBZ_L = 40,0,32,1 %; macro HWRPB_PMD$IL_NULL_TEST_MBZ_H = 44,0,32,1 %; ! ! Virtual Address of Memory bitmap ! ********************************* macro HWRPB_PMD$IQ_CN_BITMAP_VA = 48,0,0,0 %; literal HWRPB_PMD$S_CN_BITMAP_VA = 8; ! VA of bitmap macro HWRPB_PMD$IL_CN_BITMAP_VA_L = 48,0,32,0 %; macro HWRPB_PMD$IL_CN_BITMAP_VA_H = 52,0,32,0 %; ! ! Physical offset to listhead of shared MCDs ! in NULL cluster descriptor ! ******************************************* macro HWRPB_PMD$IQ_NULL_SHR_LH = 48,0,0,0 %; literal HWRPB_PMD$S_NULL_SHR_LH = 8; macro HWRPB_PMD$IL_NULL_SHR_LH_L = 48,0,32,0 %; macro HWRPB_PMD$IL_NULL_SHR_LH_H = 52,0,32,0 %; ! ! Physical Address of bitmap ! *************************** macro HWRPB_PMD$IQ_CN_BITMAP_PA = 56,0,0,0 %; literal HWRPB_PMD$S_CN_BITMAP_PA = 8; ! PA of bitmap macro HWRPB_PMD$IL_CN_BITMAP_PA_L = 56,0,32,0 %; macro HWRPB_PMD$IL_CN_BITMAP_PA_H = 60,0,32,0 %; ! ! Physical offset to first MCD in private list ! in NULL cluster descriptor ! ********************************************* macro HWRPB_PMD$IQ_NULL_PRV_OFFSET = 56,0,0,0 %; literal HWRPB_PMD$S_NULL_PRV_OFFSET = 8; macro HWRPB_PMD$IL_NULL_PRV_OFFSET_L = 56,0,32,0 %; macro HWRPB_PMD$IL_NULL_PRV_OFFSET_H = 60,0,32,0 %; ! ! Checksum of bitmap ! ******************* macro HWRPB_PMD$IQ_CN_BITMAP_CHKSUM = 64,0,0,0 %; literal HWRPB_PMD$S_CN_BITMAP_CHKSUM = 8; ! Checksum of bitmap macro HWRPB_PMD$IL_CN_BITMAP_CHKSUM_L = 64,0,32,0 %; macro HWRPB_PMD$IL_CN_BITMAP_CHKSUM_H = 68,0,32,0 %; ! ! Must be zero field in NULL cluster descriptor ! ********************************************** macro HWRPB_PMD$IQ_NULL_CHKSUM_MBZ = 64,0,0,1 %; literal HWRPB_PMD$S_NULL_CHKSUM_MBZ = 8; ! Must be zero macro HWRPB_PMD$IL_NULL_CHKSUM_MBZ_L = 64,0,32,1 %; macro HWRPB_PMD$IL_NULL_CHKSUM_MBZ_H = 68,0,32,1 %; ! ! Cluster Usage Flags ! ******************** macro HWRPB_PMD$IQ_CN_USAGE = 72,0,0,0 %; literal HWRPB_PMD$S_CN_USAGE = 8; ! Cluster usage flags macro HWRPB_PMD$IL_CN_USAGE_L = 72,0,32,0 %; macro HWRPB_PMD$IL_CN_USAGE_H = 76,0,32,0 %; ! ! Must be zero field in NULL cluster descriptor ! ********************************************** macro HWRPB_PMD$IQ_NULL_USAGE_MBZ = 72,0,0,1 %; literal HWRPB_PMD$S_NULL_USAGE_MBZ = 8; ! Must be zero macro HWRPB_PMD$IL_NULL_USAGE_MBZ_L = 72,0,32,1 %; macro HWRPB_PMD$IL_NULL_USAGE_MBZ_H = 76,0,32,1 %; ! Start PFN of system region ! *************************** macro HWRPB_PMD$IQ_SY_PFN_START = 80,0,0,0 %; literal HWRPB_PMD$S_SY_PFN_START = 8; ! Start PFN of system region macro HWRPB_PMD$IL_SY_PFN_START_L = 80,0,32,0 %; macro HWRPB_PMD$IL_SY_PFN_START_H = 84,0,32,0 %; ! ! Number of PFNs in region ! ************************* macro HWRPB_PMD$IQ_SY_PFN_COUNT = 88,0,0,0 %; literal HWRPB_PMD$S_SY_PFN_COUNT = 8; ! Number of PFNs in region macro HWRPB_PMD$IL_SY_PFN_COUNT_L = 88,0,32,0 %; macro HWRPB_PMD$IL_SY_PFN_COUNT_H = 92,0,32,0 %; ! ! Number of tested PFNs in region ! ******************************** macro HWRPB_PMD$IQ_SY_TEST_COUNT = 96,0,0,0 %; literal HWRPB_PMD$S_SY_TEST_COUNT = 8; ! Num. of tested PFNs in region macro HWRPB_PMD$IL_SY_TEST_COUNT_L = 96,0,32,0 %; macro HWRPB_PMD$IL_SY_TEST_COUNT_H = 100,0,32,0 %; ! ! Virtual Address of bitmap ! ************************** macro HWRPB_PMD$IQ_SY_BITMAP_VA = 104,0,0,0 %; literal HWRPB_PMD$S_SY_BITMAP_VA = 8; ! VA of bitmap macro HWRPB_PMD$IL_SY_BITMAP_VA_L = 104,0,32,0 %; macro HWRPB_PMD$IL_SY_BITMAP_VA_H = 108,0,32,0 %; ! ! Physical Address of bitmap ! *************************** macro HWRPB_PMD$IQ_SY_BITMAP_PA = 112,0,0,0 %; literal HWRPB_PMD$S_SY_BITMAP_PA = 8; ! PA of bitmap macro HWRPB_PMD$IL_SY_BITMAP_PA_L = 112,0,32,0 %; macro HWRPB_PMD$IL_SY_BITMAP_PA_H = 116,0,32,0 %; ! ! Checksum of bitmap ! ******************* macro HWRPB_PMD$IQ_SY_BITMAP_CHKSUM = 120,0,0,0 %; literal HWRPB_PMD$S_SY_BITMAP_CHKSUM = 8; ! Checksum of bitmap macro HWRPB_PMD$IL_SY_BITMAP_CHKSUM_L = 120,0,32,0 %; macro HWRPB_PMD$IL_SY_BITMAP_CHKSUM_H = 124,0,32,0 %; ! ! Cluster Usage Flags ! ******************** macro HWRPB_PMD$IQ_SY_USAGE = 128,0,0,0 %; literal HWRPB_PMD$S_SY_USAGE = 8; ! Cluster usage flags macro HWRPB_PMD$IL_SY_USAGE_L = 128,0,32,0 %; macro HWRPB_PMD$IL_SY_USAGE_H = 132,0,32,0 %; ! literal HWRPB_PMD$S_PMDDEF = 136; ! Old size name - synonym ! ! Physical Memory Region Descriptor ! ********************************** literal HWRPB_PMR$M_CONSOLE = %X'1'; literal HWRPB_PMR$S_PMREG = 56; ! ! Starting PFN in region ! *********************** macro HWRPB_PMR$IQ_PFN_START = 0,0,0,0 %; literal HWRPB_PMR$S_PFN_START = 8; ! Starting PFN in region macro HWRPB_PMR$IL_PFN_START_L = 0,0,32,0 %; macro HWRPB_PMR$IL_PFN_START_H = 4,0,32,0 %; ! ! Number of PFNs in region ! ************************* macro HWRPB_PMR$IQ_PFN_COUNT = 8,0,0,0 %; literal HWRPB_PMR$S_PFN_COUNT = 8; ! Number of PFNs in region macro HWRPB_PMR$IL_PFN_COUNT_L = 8,0,32,0 %; macro HWRPB_PMR$IL_PFN_COUNT_H = 12,0,32,0 %; ! ! Number of tested PFNs in region ! ******************************** macro HWRPB_PMR$IQ_TEST_COUNT = 16,0,0,0 %; literal HWRPB_PMR$S_TEST_COUNT = 8; ! Num. of tested PFNs in region macro HWRPB_PMR$IL_TEST_COUNT_L = 16,0,32,0 %; macro HWRPB_PMR$IL_TEST_COUNT_H = 20,0,32,0 %; ! ! Virtual Address of bitmap ! ************************** macro HWRPB_PMR$PQ_BITMAP_VA = 24,0,0,1 %; literal HWRPB_PMR$S_BITMAP_VA = 8; ! VA of bitmap macro HWRPB_PMR$PL_BITMAP_VA_L = 24,0,32,1 %; ! ! Physical Address of bitmap ! *************************** macro HWRPB_PMR$PQ_BITMAP_PA = 32,0,0,1 %; literal HWRPB_PMR$S_BITMAP_PA = 8; ! PA of bitmap macro HWRPB_PMR$PL_BITMAP_PA_L = 32,0,32,1 %; ! ! Checksum of bitmap ! ******************* macro HWRPB_PMR$IQ_BITMAP_CHKSUM = 40,0,0,0 %; literal HWRPB_PMR$S_BITMAP_CHKSUM = 8; ! Checksum of bitmap macro HWRPB_PMR$IL_BITMAP_CHKSUM_L = 40,0,32,0 %; macro HWRPB_PMR$IL_BITMAP_CHKSUM_H = 44,0,32,0 %; ! ! Cluster Usage Flags ! ******************** macro HWRPB_PMR$IQ_USAGE = 48,0,0,0 %; literal HWRPB_PMR$S_USAGE = 8; ! Cluster usage flags macro HWRPB_PMR$IL_USAGE_L = 48,0,32,0 %; macro HWRPB_PMR$V_CONSOLE = 48,0,1,0 %; ! Cluster reserved by console macro HWRPB_PMR$IL_USAGE_H = 52,0,32,0 %; ! literal HWRPB_PMR$C_LENGTH = 56; ! Size of region entry literal HWRPB_PMR$K_LENGTH = 56; ! Size of region entry literal HWRPB_PMR$S_PMREGDEF = 56; ! Old size name - synonym ! ! Console languages ! ****************** literal HWRPB_LANG$K_UNKNOWN = 0; literal HWRPB_LANG$K_DANISH = 48; literal HWRPB_LANG$K_GERMAN = 50; literal HWRPB_LANG$K_SWISS = 52; literal HWRPB_LANG$K_AMERICAN = 54; literal HWRPB_LANG$K_BRITISH = 56; literal HWRPB_LANG$K_SPANISH = 58; literal HWRPB_LANG$K_FRENCH = 60; literal HWRPB_LANG$K_CANADIAN = 62; literal HWRPB_LANG$K_ROMANDE = 64; literal HWRPB_LANG$K_ITALIAN = 66; literal HWRPB_LANG$K_NETHERLANDS = 68; literal HWRPB_LANG$K_NORSK = 70; literal HWRPB_LANG$K_PORTUGUESE = 72; literal HWRPB_LANG$K_SUOMI = 74; literal HWRPB_LANG$K_SWEDISH = 76; literal HWRPB_LANG$K_VLAAMS = 78; ! ! Console Routine Block ! ********************** literal HWRPB_CRB$S_HWRPB_CRB = 56; ! ! Virtual Address of DISPATCH Procedure Descriptor ! ************************************************* macro HWRPB_CRB$IQ_VA_DISPATCH_PD = 0,0,0,0 %; literal HWRPB_CRB$S_VA_DISPATCH_PD = 8; ! VA of Procedure Desc. macro HWRPB_CRB$IL_VA_DISPATCH_PD_L = 0,0,32,0 %; macro HWRPB_CRB$IL_VA_DISPATCH_PD_H = 4,0,32,0 %; ! ! Physical Address of DISPATCH Procedure Descriptor ! ************************************************** macro HWRPB_CRB$IQ_PA_DISPATCH_PD = 8,0,0,0 %; literal HWRPB_CRB$S_PA_DISPATCH_PD = 8; ! PA of Procedure Desc. macro HWRPB_CRB$IL_PA_DISPATCH_PD_L = 8,0,32,0 %; macro HWRPB_CRB$IL_PA_DISPATCH_PD_H = 12,0,32,0 %; ! ! Virtual Address of FIXUP Procedure Descriptor ! ********************************************** macro HWRPB_CRB$IQ_VA_FIXUP_PD = 16,0,0,0 %; literal HWRPB_CRB$S_VA_FIXUP_PD = 8; ! VA of Procedure Desc. macro HWRPB_CRB$IL_VA_FIXUP_PD_L = 16,0,32,0 %; macro HWRPB_CRB$IL_VA_FIXUP_PD_H = 20,0,32,0 %; ! ! Physical Address of FIXUP Procedure Descriptor ! ********************************************** macro HWRPB_CRB$IQ_PA_FIXUP_PD = 24,0,0,0 %; literal HWRPB_CRB$S_PA_FIXUP_PD = 8; ! PA of Procedure Desc. macro HWRPB_CRB$IL_PA_FIXUP_PD_L = 24,0,32,0 %; macro HWRPB_CRB$IL_PA_FIXUP_PD_H = 28,0,32,0 %; ! ! Number of entries in VA/PA map ! ******************************* macro HWRPB_CRB$IQ_MAP_COUNT = 32,0,0,0 %; literal HWRPB_CRB$S_MAP_COUNT = 8; ! Num entries in VA/PA map macro HWRPB_CRB$IL_MAP_COUNT_L = 32,0,32,0 %; macro HWRPB_CRB$IL_MAP_COUNT_H = 36,0,32,0 %; ! ! Number of pages to be mapped ! ***************************** macro HWRPB_CRB$IQ_PAGE_COUNT = 40,0,0,0 %; literal HWRPB_CRB$S_PAGE_COUNT = 8; ! Num pages to be mapped macro HWRPB_CRB$IL_PAGE_COUNT_L = 40,0,32,0 %; macro HWRPB_CRB$IL_PAGE_COUNT_H = 44,0,32,0 %; ! ! Console VA/PA map ! ****************** macro HWRPB_CRB$IQ_VAPA_MAP = 48,0,0,0 %; literal HWRPB_CRB$S_VAPA_MAP = 8; ! Console VA/PA map macro HWRPB_CRB$IL_VAPA_MAP_L = 48,0,32,0 %; macro HWRPB_CRB$IL_VAPA_MAP_H = 52,0,32,0 %; ! literal HWRPB_CRB$C_LENGTH = 56; ! Length of CRB literal HWRPB_CRB$K_LENGTH = 56; ! Length of CRB literal HWRPB_CRB$S_CRBDEF = 56; ! Old size name - synonym ! ! Virtual/Physical Address Map ! ***************************** literal HWRPB_VAPAMAP$S_VAPAMAP = 24; ! ! Console Virtual Address ! ************************ macro HWRPB_VAPAMAP$IQ_VA = 0,0,0,0 %; literal HWRPB_VAPAMAP$S_VA = 8; ! Console VA macro HWRPB_VAPAMAP$IL_VA_L = 0,0,32,0 %; macro HWRPB_VAPAMAP$IL_VA_H = 4,0,32,0 %; ! ! Console Physical Address ! ************************ macro HWRPB_VAPAMAP$IQ_PA = 8,0,0,0 %; literal HWRPB_VAPAMAP$S_PA = 8; ! Console PA macro HWRPB_VAPAMAP$IL_PA_L = 8,0,32,0 %; macro HWRPB_VAPAMAP$IL_PA_H = 12,0,32,0 %; ! ! Page Count of Entry ! ******************** macro HWRPB_VAPAMAP$IQ_PAGE_COUNT = 16,0,0,0 %; literal HWRPB_VAPAMAP$S_PAGE_COUNT = 8; ! Page count of entry macro HWRPB_VAPAMAP$IL_PAGE_COUNT_L = 16,0,32,0 %; macro HWRPB_VAPAMAP$IL_PAGE_COUNT_H = 20,0,32,0 %; ! literal HWRPB_VAPAMAP$S_VAPAMAPDEF = 24; ! Old size name synonym ! ! [IPF] Boot Path Descriptor ! ***************************** literal HWRPB_BOOTDEV$S_BOOTDEV = 16; ! ! [IPF] Size of Bootpath Desc ! ************************ macro HWRPB_BOOTDEV$IQ_SIZE = 0,0,0,0 %; literal HWRPB_BOOTDEV$S_SIZE = 8; ! [IPF] Size of Bootpath Desc macro HWRPB_BOOTDEV$IL_SIZE_L = 0,0,32,0 %; macro HWRPB_BOOTDEV$IL_SIZE_H = 4,0,32,0 %; ! ! [IPF] Boot Device Path Binary Data ! ************************ macro HWRPB_BOOTDEV$IQ_DEVICE_PATH = 8,0,0,0 %; literal HWRPB_BOOTDEV$S_DEVICE_PATH = 8; ! [IPF] Boot Device Path Binary Data macro HWRPB_BOOTDEV$IL_DEVICE_PATH_L = 8,0,32,0 %; macro HWRPB_BOOTDEV$IL_DEVICE_PATH_H = 12,0,32,0 %; ! literal HWRPB_BOOTDEV$S_BOOTDEVDEF = 16; ! Old size name synonym ! ! [IPF] Boot Space Descriptor ! ***************************** literal HWRPB_BOOTSPACE$S_BOOTSPACE = 24; ! ! Boot Space Physical Address ! ************************ macro HWRPB_BOOTSPACE$IQ_PA = 0,0,0,0 %; literal HWRPB_BOOTSPACE$S_PA = 8; ! [IPF] Boot Space PA macro HWRPB_BOOTSPACE$IL_PA_L = 0,0,32,0 %; macro HWRPB_BOOTSPACE$IL_PA_H = 4,0,32,0 %; ! ! Boot Space Virtual Address ! ************************ macro HWRPB_BOOTSPACE$IQ_VA = 8,0,0,0 %; literal HWRPB_BOOTSPACE$S_VA = 8; ! [IPF] Boot Space VA macro HWRPB_BOOTSPACE$IL_VA_L = 8,0,32,0 %; macro HWRPB_BOOTSPACE$IL_VA_H = 12,0,32,0 %; ! ! Boot Space Size ! ************************ macro HWRPB_BOOTSPACE$IQ_SIZE = 16,0,0,0 %; literal HWRPB_BOOTSPACE$S_SIZE = 8; ! [IPF] Boot Space Size macro HWRPB_BOOTSPACE$IL_SIZE_L = 16,0,32,0 %; macro HWRPB_BOOTSPACE$IL_SIZE_H = 20,0,32,0 %; ! literal HWRPB_BOOTSPACE$S_BOOTSPACEDEF = 24; ! Old size name synonym ! ! CONSTANTS ! ! BOOTSPACE Identifiers literal HWRPB_BOOTSPACE$K_IPB = 0; ! 0 IPB Bootspace literal HWRPB_BOOTSPACE$K_SYSBOOT = 1; ! 1 SYSBOOT Bootspace literal HWRPB_BOOTSPACE$K_HWRPB = 2; ! 2 HWRPB Bootspace literal HWRPB_BOOTSPACE$K_IOP = 3; ! 3 IO Port Bootspace literal HWRPB_BOOTSPACE$K_PCI = 4; ! 4 PCI Memory Bootspace literal HWRPB_BOOTSPACE$K_VGA = 5; ! 5 VGA Bootspace literal HWRPB_BOOTSPACE$K_CFGTREE = 6; ! 6 Config-Tree Bootspace literal HWRPB_BOOTSPACE$K_MEMORYDISK = 7; ! 7 Memorydisk Bootspace literal HWRPB_BOOTSPACE$K_RSVD_1 = 8; ! Reserved Bootspace (IPB depends on this being last) ! ! Console terminal routines literal HWRPB_CRB$K_GETC = 1; ! Get a character from console literal HWRPB_CRB$K_PUTS = 2; ! Put a string to console term literal HWRPB_CRB$K_RESET_TERM = 3; ! Reset console terminal literal HWRPB_CRB$K_SET_TERM_INTR = 4; ! Set console terminal int. literal HWRPB_CRB$K_SET_TERM_CTL = 5; ! Set console terminal controls literal HWRPB_CRB$K_PROCESS_KEYCODE = 6; ! Process and translate keycode literal HWRPB_CRB$K_CONSOLE_OPEN = 7; ! Open console for I/O literal HWRPB_CRB$K_CONSOLE_CLOSE = 8; ! Close console for I/O ! ! Console Generic IO routines literal HWRPB_CRB$K_OPEN = 16; ! Open access to I/O device literal HWRPB_CRB$K_CLOSE = 17; ! Close access to I/O device literal HWRPB_CRB$K_IOCTL = 18; literal HWRPB_CRB$K_READ = 19; ! Perform read operation literal HWRPB_CRB$K_WRITE = 20; ! Perform write operation ! ! Console Env. Variable Routines literal HWRPB_CRB$K_SET_ENV = 32; ! Set an environment varible literal HWRPB_CRB$K_RESET_ENV = 33; ! Reset an environment variable literal HWRPB_CRB$K_GET_ENV = 34; ! Fetch an environment varible literal HWRPB_CRB$K_SAVE_ENV = 35; ! Save an environment varible ! ! Write/Read FRU EEROM routines literal HWRPB_CRB$K_WRITE_EEROM = 51; literal HWRPB_CRB$K_READ_EEROM = 52; literal HWRPB_CRB$K_NEW_CPU_OWNERSHIP = 53; literal HWRPB_CRB$K_RELEASE_TO_FIRMWARE = 54; literal HWRPB_CRB$K_GET_HW_ERROR_RECORD = 55; ! ! Required Environment Variables literal HWRPB_CRB$K_AUTO_ACTION = 1; literal HWRPB_CRB$K_BOOT_DEV = 2; literal HWRPB_CRB$K_BOOTCMD_DEV = 3; literal HWRPB_CRB$K_BOOTED_DEV = 4; literal HWRPB_CRB$K_BOOT_FILE = 5; literal HWRPB_CRB$K_BOOTED_FILE = 6; literal HWRPB_CRB$K_BOOT_OSFLAGS = 7; literal HWRPB_CRB$K_BOOTED_OSFLAGS = 8; literal HWRPB_CRB$K_BOOT_RESET = 9; literal HWRPB_CRB$K_DUMP_DEV = 10; literal HWRPB_CRB$K_ENABLE_AUDIT = 11; literal HWRPB_CRB$K_LICENSE = 12; literal HWRPB_CRB$K_CHAR_SET = 13; literal HWRPB_CRB$K_LANGUAGE = 14; literal HWRPB_CRB$K_TTY_DEV = 15; ! literal HWRPB_CRB$K_PSWITCH = 48; literal HWRPB_CRB$K_SAVE_ERROR_LOG = 49; literal HWRPB_CRB$K_HALT_CPU = 50; ! literal HWRPB_CRB$K_PARTITION = 40; literal HWRPB_CRB$K_GALAXY = 40; ! ! IA64 ! Alpha ! Alpha ! ! Itanium min-state save structure - zero relative ! ************************************************************ literal MCAMIN$S_MCAMIN = 456; macro MCAMIN$IQ_SAVED_GR_NATS = 0,0,0,0 %; literal MCAMIN$S_SAVED_GR_NATS = 8; ! NaT bits for saved GRs ! ! Static registers ! ****************** macro MCAMIN$IQ_GR1 = 8,0,0,0 %; literal MCAMIN$S_GR1 = 8; ! General register 1 macro MCAMIN$IQ_GR2 = 16,0,0,0 %; literal MCAMIN$S_GR2 = 8; ! General register 2 macro MCAMIN$IQ_GR3 = 24,0,0,0 %; literal MCAMIN$S_GR3 = 8; ! General register 3 macro MCAMIN$IQ_GR4 = 32,0,0,0 %; literal MCAMIN$S_GR4 = 8; ! General register 4 macro MCAMIN$IQ_GR5 = 40,0,0,0 %; literal MCAMIN$S_GR5 = 8; ! General register 5 macro MCAMIN$IQ_GR6 = 48,0,0,0 %; literal MCAMIN$S_GR6 = 8; ! General register 6 macro MCAMIN$IQ_GR7 = 56,0,0,0 %; literal MCAMIN$S_GR7 = 8; ! General register 7 macro MCAMIN$IQ_GR8 = 64,0,0,0 %; literal MCAMIN$S_GR8 = 8; ! General register 8 macro MCAMIN$IQ_GR9 = 72,0,0,0 %; literal MCAMIN$S_GR9 = 8; ! General register 9 macro MCAMIN$IQ_GR10 = 80,0,0,0 %; literal MCAMIN$S_GR10 = 8; ! General register 10 macro MCAMIN$IQ_GR11 = 88,0,0,0 %; literal MCAMIN$S_GR11 = 8; ! General register 11 macro MCAMIN$IQ_GR12 = 96,0,0,0 %; literal MCAMIN$S_GR12 = 8; ! General register 12 macro MCAMIN$IQ_GR13 = 104,0,0,0 %; literal MCAMIN$S_GR13 = 8; ! General register 13 macro MCAMIN$IQ_GR14 = 112,0,0,0 %; literal MCAMIN$S_GR14 = 8; ! General register 14 macro MCAMIN$IQ_GR15 = 120,0,0,0 %; literal MCAMIN$S_GR15 = 8; ! General register 15 ! ! Bank 0 registers ! ****************** macro MCAMIN$IQ_BANK0_GR16 = 128,0,0,0 %; literal MCAMIN$S_BANK0_GR16 = 8; ! Bank 0 register 16 macro MCAMIN$IQ_BANK0_GR17 = 136,0,0,0 %; literal MCAMIN$S_BANK0_GR17 = 8; ! Bank 0 register 17 macro MCAMIN$IQ_BANK0_GR18 = 144,0,0,0 %; literal MCAMIN$S_BANK0_GR18 = 8; ! Bank 0 register 18 macro MCAMIN$IQ_BANK0_GR19 = 152,0,0,0 %; literal MCAMIN$S_BANK0_GR19 = 8; ! Bank 0 register 19 macro MCAMIN$IQ_BANK0_GR20 = 160,0,0,0 %; literal MCAMIN$S_BANK0_GR20 = 8; ! Bank 0 register 20 macro MCAMIN$IQ_BANK0_GR21 = 168,0,0,0 %; literal MCAMIN$S_BANK0_GR21 = 8; ! Bank 0 register 21 macro MCAMIN$IQ_BANK0_GR22 = 176,0,0,0 %; literal MCAMIN$S_BANK0_GR22 = 8; ! Bank 0 register 22 macro MCAMIN$IQ_BANK0_GR23 = 184,0,0,0 %; literal MCAMIN$S_BANK0_GR23 = 8; ! Bank 0 register 23 macro MCAMIN$IQ_BANK0_GR24 = 192,0,0,0 %; literal MCAMIN$S_BANK0_GR24 = 8; ! Bank 0 register 24 macro MCAMIN$IQ_BANK0_GR25 = 200,0,0,0 %; literal MCAMIN$S_BANK0_GR25 = 8; ! Bank 0 register 25 macro MCAMIN$IQ_BANK0_GR26 = 208,0,0,0 %; literal MCAMIN$S_BANK0_GR26 = 8; ! Bank 0 register 26 macro MCAMIN$IQ_BANK0_GR27 = 216,0,0,0 %; literal MCAMIN$S_BANK0_GR27 = 8; ! Bank 0 register 27 macro MCAMIN$IQ_BANK0_GR28 = 224,0,0,0 %; literal MCAMIN$S_BANK0_GR28 = 8; ! Bank 0 register 28 macro MCAMIN$IQ_BANK0_GR29 = 232,0,0,0 %; literal MCAMIN$S_BANK0_GR29 = 8; ! Bank 0 register 29 macro MCAMIN$IQ_BANK0_GR30 = 240,0,0,0 %; literal MCAMIN$S_BANK0_GR30 = 8; ! Bank 0 register 30 macro MCAMIN$IQ_BANK0_GR31 = 248,0,0,0 %; literal MCAMIN$S_BANK0_GR31 = 8; ! Bank 0 register 31 ! ! Bank 1 registers ! ****************** macro MCAMIN$IQ_BANK1_GR16 = 256,0,0,0 %; literal MCAMIN$S_BANK1_GR16 = 8; ! Bank 1 register 16 macro MCAMIN$IQ_BANK1_GR17 = 264,0,0,0 %; literal MCAMIN$S_BANK1_GR17 = 8; ! Bank 1 register 17 macro MCAMIN$IQ_BANK1_GR18 = 272,0,0,0 %; literal MCAMIN$S_BANK1_GR18 = 8; ! Bank 1 register 18 macro MCAMIN$IQ_BANK1_GR19 = 280,0,0,0 %; literal MCAMIN$S_BANK1_GR19 = 8; ! Bank 1 register 19 macro MCAMIN$IQ_BANK1_GR20 = 288,0,0,0 %; literal MCAMIN$S_BANK1_GR20 = 8; ! Bank 1 register 20 macro MCAMIN$IQ_BANK1_GR21 = 296,0,0,0 %; literal MCAMIN$S_BANK1_GR21 = 8; ! Bank 1 register 21 macro MCAMIN$IQ_BANK1_GR22 = 304,0,0,0 %; literal MCAMIN$S_BANK1_GR22 = 8; ! Bank 1 register 22 macro MCAMIN$IQ_BANK1_GR23 = 312,0,0,0 %; literal MCAMIN$S_BANK1_GR23 = 8; ! Bank 1 register 23 macro MCAMIN$IQ_BANK1_GR24 = 320,0,0,0 %; literal MCAMIN$S_BANK1_GR24 = 8; ! Bank 1 register 24 macro MCAMIN$IQ_BANK1_GR25 = 328,0,0,0 %; literal MCAMIN$S_BANK1_GR25 = 8; ! Bank 1 register 25 macro MCAMIN$IQ_BANK1_GR26 = 336,0,0,0 %; literal MCAMIN$S_BANK1_GR26 = 8; ! Bank 1 register 26 macro MCAMIN$IQ_BANK1_GR27 = 344,0,0,0 %; literal MCAMIN$S_BANK1_GR27 = 8; ! Bank 1 register 27 macro MCAMIN$IQ_BANK1_GR28 = 352,0,0,0 %; literal MCAMIN$S_BANK1_GR28 = 8; ! Bank 1 register 28 macro MCAMIN$IQ_BANK1_GR29 = 360,0,0,0 %; literal MCAMIN$S_BANK1_GR29 = 8; ! Bank 1 register 29 macro MCAMIN$IQ_BANK1_GR30 = 368,0,0,0 %; literal MCAMIN$S_BANK1_GR30 = 8; ! Bank 1 register 30 macro MCAMIN$IQ_BANK1_GR31 = 376,0,0,0 %; literal MCAMIN$S_BANK1_GR31 = 8; ! Bank 1 register 31 ! ! Saved predicate registers ! ************************** macro MCAMIN$IQ_SAVED_PRS = 384,0,0,0 %; literal MCAMIN$S_SAVED_PRS = 8; ! Predicate registers ! ! State registers ! ************************** macro MCAMIN$IQ_BR0 = 392,0,0,0 %; literal MCAMIN$S_BR0 = 8; ! BR0 macro MCAMIN$IQ_RSC = 400,0,0,0 %; literal MCAMIN$S_RSC = 8; ! RSC macro MCAMIN$IQ_IIP = 408,0,0,0 %; literal MCAMIN$S_IIP = 8; ! IIP macro MCAMIN$IQ_IPSR = 416,0,0,0 %; literal MCAMIN$S_IPSR = 8; ! IPSR macro MCAMIN$IQ_IFS = 424,0,0,0 %; literal MCAMIN$S_IFS = 8; ! IFS ! ! Possibly undefined registers ! ***************************** macro MCAMIN$IQ_XIP = 432,0,0,0 %; literal MCAMIN$S_XIP = 8; ! XIP or undefined macro MCAMIN$IQ_XPSR = 440,0,0,0 %; literal MCAMIN$S_XPSR = 8; ! XPSR or undefined macro MCAMIN$IQ_XFS = 448,0,0,0 %; literal MCAMIN$S_XFS = 8; ! XFS or undefined ! literal MCAMIN$K_LENGTH = 456; ! Full length of MCAMIN$ ! ! Itanium machine check interrupt state block ! ************************************************************ literal MCAINT$M_HALTED_IN_CONSOLE = %X'1'; literal MCAINT$M_CONTEXT_VALID = %X'2'; literal MCAINT$M_NO_DATA = %X'4'; literal MCAINT$S_MCAINT = 160; macro MCAINT$IQ_FLAGS = 0,0,0,0 %; literal MCAINT$S_FLAGS = 8; ! Flags bitmask macro MCAINT$V_HALTED_IN_CONSOLE = 0,0,1,0 %; ! CPU is not running OS software macro MCAINT$V_CONTEXT_VALID = 0,1,1,0 %; ! Valid data has been dumped into buffer macro MCAINT$V_NO_DATA = 0,2,1,0 %; ! Hardware returned no information in buffer macro MCAINT$IQ_CPU_ID = 8,0,0,0 %; literal MCAINT$S_CPU_ID = 8; ! Zero-relative CPU ID of interrupted processor macro MCAINT$IQ_INT_TYPE = 16,0,0,0 %; literal MCAINT$S_INT_TYPE = 8; ! Interrupt type code macro MCAINT$IQ_HANDLER_GP = 24,0,0,0 %; literal MCAINT$S_HANDLER_GP = 8; ! Physical GP of current handler macro MCAINT$IQ_HANDLER_RET = 32,0,0,0 %; literal MCAINT$S_HANDLER_RET = 8; ! Physical PC of handler procedure return macro MCAINT$IQ_HANDLER_KSP = 40,0,0,0 %; literal MCAINT$S_HANDLER_KSP = 8; ! Physical KSP of console handler macro MCAINT$IQ_HANDLER_BSP = 48,0,0,0 %; literal MCAINT$S_HANDLER_BSP = 8; ! Physical BSP of console handler macro MCAINT$IQ_MINSTATE_SAVE_AREA = 56,0,0,0 %; literal MCAINT$S_MINSTATE_SAVE_AREA = 8; ! Physical address of interrupt min-state save area macro MCAINT$IQ_SAVED_CONTEXT = 64,0,0,0 %; literal MCAINT$S_SAVED_CONTEXT = 8; ! Physical address of saved hardware state block macro MCAINT$IQ_PROCESSOR_STATE_PARAM = 72,0,0,0 %; literal MCAINT$S_PROCESSOR_STATE_PARAM = 8; ! Itanium processor state parameter value macro MCAINT$IQ_STATE_INFO = 80,0,0,0 %; literal MCAINT$S_STATE_INFO = 8; ! Interrupt-specific state macro MCAINT$IQ_PAL_PROC_ENTRY = 88,0,0,0 %; literal MCAINT$S_PAL_PROC_ENTRY = 8; ! Physical PC of PAL routine entry macro MCAINT$IQ_SAL_PROC_ENTRY = 96,0,0,0 %; literal MCAINT$S_SAL_PROC_ENTRY = 8; ! Physical PC of SAL routine entry macro MCAINT$IQ_SAL_GP = 104,0,0,0 %; literal MCAINT$S_SAL_GP = 8; ! Physical GP of SAL routines macro MCAINT$IQ_SAL_RETURN = 112,0,0,0 %; literal MCAINT$S_SAL_RETURN = 8; ! Physical PC of SAL return procedure macro MCAINT$IQ_HANDLER_RNAT = 120,0,0,0 %; literal MCAINT$S_HANDLER_RNAT = 8; ! RNAT of console handler register stack macro MCAINT$IQ_HANDLER_XFR_BSP = 128,0,0,0 %; literal MCAINT$S_HANDLER_XFR_BSP = 8; ! Physical BSP of console handler macro MCAINT$IQ_HANDLER_RSVD1 = 136,0,0,0 %; literal MCAINT$S_HANDLER_RSVD1 = 8; ! Reserved cell macro MCAINT$IQ_HANDLER_RSVD2 = 144,0,0,0 %; literal MCAINT$S_HANDLER_RSVD2 = 8; ! Reserved cell macro MCAINT$IQ_HANDLER_RSVD3 = 152,0,0,0 %; literal MCAINT$S_HANDLER_RSVD3 = 8; ! Reserved cell ! literal MCAINT$K_LENGTH = 160; ! Full length of MCAINT$ ! ! Itanium machine check saved context structure not in minstate save array ! ************************************************************************* literal MCASAV$S_MCASAV = 2208; macro MCASAV$IQ_BSP = 0,0,0,0 %; literal MCASAV$S_BSP = 8; ! Interrupted BSP pointer macro MCASAV$IQ_BSPSTORE = 8,0,0,0 %; literal MCASAV$S_BSPSTORE = 8; ! Interrupted BSPSTORE pointer macro MCASAV$IQ_RNAT = 16,0,0,0 %; literal MCASAV$S_RNAT = 8; ! Interrupted RNAT value macro MCASAV$IQ_UNAT = 24,0,0,0 %; literal MCASAV$S_UNAT = 8; ! Interrupted UNAT value macro MCASAV$IQ_PFS = 32,0,0,0 %; literal MCASAV$S_PFS = 8; ! Interrupted PFS value macro MCASAV$IQ_FPSR = 40,0,0,0 %; literal MCASAV$S_FPSR = 8; ! Interrupted FPSR value macro MCASAV$IQ_ISR = 48,0,0,0 %; literal MCASAV$S_ISR = 8; ! Interrupted ISR value macro MCASAV$IQ_IFA = 56,0,0,0 %; literal MCASAV$S_IFA = 8; ! Interrupted IFA value macro MCASAV$IQ_ITIR = 64,0,0,0 %; literal MCASAV$S_ITIR = 8; ! Interrupted ITIR value macro MCASAV$IQ_IIPA = 72,0,0,0 %; literal MCASAV$S_IIPA = 8; ! Interrupted IIPA value macro MCASAV$IQ_IIM = 80,0,0,0 %; literal MCASAV$S_IIM = 8; ! Interrupted IIM value macro MCASAV$IQ_IHA = 88,0,0,0 %; literal MCASAV$S_IHA = 8; ! Interrupted IHA value macro MCASAV$IQ_CCV = 96,0,0,0 %; literal MCASAV$S_CCV = 8; ! Interrupted CCV value macro MCASAV$IQ_DCR = 104,0,0,0 %; literal MCASAV$S_DCR = 8; ! Interrupted DCR value macro MCASAV$IQ_LC = 112,0,0,0 %; literal MCASAV$S_LC = 8; ! Interrupted LC value macro MCASAV$IQ_EC = 120,0,0,0 %; literal MCASAV$S_EC = 8; ! Interrupted EC value macro MCASAV$IQ_BR1 = 128,0,0,0 %; literal MCASAV$S_BR1 = 8; ! Interrupted BR1 value macro MCASAV$IQ_BR2 = 136,0,0,0 %; literal MCASAV$S_BR2 = 8; ! Interrupted BR2 value macro MCASAV$IQ_BR3 = 144,0,0,0 %; literal MCASAV$S_BR3 = 8; ! Interrupted BR3 value macro MCASAV$IQ_BR4 = 152,0,0,0 %; literal MCASAV$S_BR4 = 8; ! Interrupted BR4 value macro MCASAV$IQ_BR5 = 160,0,0,0 %; literal MCASAV$S_BR5 = 8; ! Interrupted BR5 value macro MCASAV$IQ_BR6 = 168,0,0,0 %; literal MCASAV$S_BR6 = 8; ! Interrupted BR6 value macro MCASAV$IQ_BR7 = 176,0,0,0 %; literal MCASAV$S_BR7 = 8; ! Interrupted BR7 value macro MCASAV$Q_F2 = 192,0,0,0 %; literal MCASAV$S_F2 = 16; ! F2 macro MCASAV$Q_F3 = 208,0,0,0 %; literal MCASAV$S_F3 = 16; ! F3 macro MCASAV$Q_F4 = 224,0,0,0 %; literal MCASAV$S_F4 = 16; ! F4 macro MCASAV$Q_F5 = 240,0,0,0 %; literal MCASAV$S_F5 = 16; ! F5 macro MCASAV$Q_F6 = 256,0,0,0 %; literal MCASAV$S_F6 = 16; ! F6 macro MCASAV$Q_F7 = 272,0,0,0 %; literal MCASAV$S_F7 = 16; ! F7 macro MCASAV$Q_F8 = 288,0,0,0 %; literal MCASAV$S_F8 = 16; ! F8 macro MCASAV$Q_F9 = 304,0,0,0 %; literal MCASAV$S_F9 = 16; ! F9 macro MCASAV$Q_F10 = 320,0,0,0 %; literal MCASAV$S_F10 = 16; ! F10 macro MCASAV$Q_F11 = 336,0,0,0 %; literal MCASAV$S_F11 = 16; ! F11 macro MCASAV$Q_F12 = 352,0,0,0 %; literal MCASAV$S_F12 = 16; ! F12 macro MCASAV$Q_F13 = 368,0,0,0 %; literal MCASAV$S_F13 = 16; ! F13 macro MCASAV$Q_F14 = 384,0,0,0 %; literal MCASAV$S_F14 = 16; ! F14 macro MCASAV$Q_F15 = 400,0,0,0 %; literal MCASAV$S_F15 = 16; ! F15 macro MCASAV$Q_F16 = 416,0,0,0 %; literal MCASAV$S_F16 = 16; ! F16 macro MCASAV$Q_F17 = 432,0,0,0 %; literal MCASAV$S_F17 = 16; ! F17 macro MCASAV$Q_F18 = 448,0,0,0 %; literal MCASAV$S_F18 = 16; ! F18 macro MCASAV$Q_F19 = 464,0,0,0 %; literal MCASAV$S_F19 = 16; ! F19 macro MCASAV$Q_F20 = 480,0,0,0 %; literal MCASAV$S_F20 = 16; ! F20 macro MCASAV$Q_F21 = 496,0,0,0 %; literal MCASAV$S_F21 = 16; ! F21 macro MCASAV$Q_F22 = 512,0,0,0 %; literal MCASAV$S_F22 = 16; ! F22 macro MCASAV$Q_F23 = 528,0,0,0 %; literal MCASAV$S_F23 = 16; ! F23 macro MCASAV$Q_F24 = 544,0,0,0 %; literal MCASAV$S_F24 = 16; ! F24 macro MCASAV$Q_F25 = 560,0,0,0 %; literal MCASAV$S_F25 = 16; ! F25 macro MCASAV$Q_F26 = 576,0,0,0 %; literal MCASAV$S_F26 = 16; ! F26 macro MCASAV$Q_F27 = 592,0,0,0 %; literal MCASAV$S_F27 = 16; ! F27 macro MCASAV$Q_F28 = 608,0,0,0 %; literal MCASAV$S_F28 = 16; ! F28 macro MCASAV$Q_F29 = 624,0,0,0 %; literal MCASAV$S_F29 = 16; ! F29 macro MCASAV$Q_F30 = 640,0,0,0 %; literal MCASAV$S_F30 = 16; ! F30 macro MCASAV$Q_F31 = 656,0,0,0 %; literal MCASAV$S_F31 = 16; ! F31 macro MCASAV$Q_F32 = 672,0,0,0 %; literal MCASAV$S_F32 = 16; ! F32 macro MCASAV$Q_F33 = 688,0,0,0 %; literal MCASAV$S_F33 = 16; ! F33 macro MCASAV$Q_F34 = 704,0,0,0 %; literal MCASAV$S_F34 = 16; ! F34 macro MCASAV$Q_F35 = 720,0,0,0 %; literal MCASAV$S_F35 = 16; ! F35 macro MCASAV$Q_F36 = 736,0,0,0 %; literal MCASAV$S_F36 = 16; ! F36 macro MCASAV$Q_F37 = 752,0,0,0 %; literal MCASAV$S_F37 = 16; ! F37 macro MCASAV$Q_F38 = 768,0,0,0 %; literal MCASAV$S_F38 = 16; ! F38 macro MCASAV$Q_F39 = 784,0,0,0 %; literal MCASAV$S_F39 = 16; ! F39 macro MCASAV$Q_F40 = 800,0,0,0 %; literal MCASAV$S_F40 = 16; ! F40 macro MCASAV$Q_F41 = 816,0,0,0 %; literal MCASAV$S_F41 = 16; ! F41 macro MCASAV$Q_F42 = 832,0,0,0 %; literal MCASAV$S_F42 = 16; ! F42 macro MCASAV$Q_F43 = 848,0,0,0 %; literal MCASAV$S_F43 = 16; ! F43 macro MCASAV$Q_F44 = 864,0,0,0 %; literal MCASAV$S_F44 = 16; ! F44 macro MCASAV$Q_F45 = 880,0,0,0 %; literal MCASAV$S_F45 = 16; ! F45 macro MCASAV$Q_F46 = 896,0,0,0 %; literal MCASAV$S_F46 = 16; ! F46 macro MCASAV$Q_F47 = 912,0,0,0 %; literal MCASAV$S_F47 = 16; ! F47 macro MCASAV$Q_F48 = 928,0,0,0 %; literal MCASAV$S_F48 = 16; ! F48 macro MCASAV$Q_F49 = 944,0,0,0 %; literal MCASAV$S_F49 = 16; ! F49 macro MCASAV$Q_F50 = 960,0,0,0 %; literal MCASAV$S_F50 = 16; ! F50 macro MCASAV$Q_F51 = 976,0,0,0 %; literal MCASAV$S_F51 = 16; ! F51 macro MCASAV$Q_F52 = 992,0,0,0 %; literal MCASAV$S_F52 = 16; ! F52 macro MCASAV$Q_F53 = 1008,0,0,0 %; literal MCASAV$S_F53 = 16; ! F53 macro MCASAV$Q_F54 = 1024,0,0,0 %; literal MCASAV$S_F54 = 16; ! F54 macro MCASAV$Q_F55 = 1040,0,0,0 %; literal MCASAV$S_F55 = 16; ! F55 macro MCASAV$Q_F56 = 1056,0,0,0 %; literal MCASAV$S_F56 = 16; ! F56 macro MCASAV$Q_F57 = 1072,0,0,0 %; literal MCASAV$S_F57 = 16; ! F57 macro MCASAV$Q_F58 = 1088,0,0,0 %; literal MCASAV$S_F58 = 16; ! F58 macro MCASAV$Q_F59 = 1104,0,0,0 %; literal MCASAV$S_F59 = 16; ! F59 macro MCASAV$Q_F60 = 1120,0,0,0 %; literal MCASAV$S_F60 = 16; ! F60 macro MCASAV$Q_F61 = 1136,0,0,0 %; literal MCASAV$S_F61 = 16; ! F61 macro MCASAV$Q_F62 = 1152,0,0,0 %; literal MCASAV$S_F62 = 16; ! F62 macro MCASAV$Q_F63 = 1168,0,0,0 %; literal MCASAV$S_F63 = 16; ! F63 macro MCASAV$Q_F64 = 1184,0,0,0 %; literal MCASAV$S_F64 = 16; ! F64 macro MCASAV$Q_F65 = 1200,0,0,0 %; literal MCASAV$S_F65 = 16; ! F65 macro MCASAV$Q_F66 = 1216,0,0,0 %; literal MCASAV$S_F66 = 16; ! F66 macro MCASAV$Q_F67 = 1232,0,0,0 %; literal MCASAV$S_F67 = 16; ! F67 macro MCASAV$Q_F68 = 1248,0,0,0 %; literal MCASAV$S_F68 = 16; ! F68 macro MCASAV$Q_F69 = 1264,0,0,0 %; literal MCASAV$S_F69 = 16; ! F69 macro MCASAV$Q_F70 = 1280,0,0,0 %; literal MCASAV$S_F70 = 16; ! F70 macro MCASAV$Q_F71 = 1296,0,0,0 %; literal MCASAV$S_F71 = 16; ! F71 macro MCASAV$Q_F72 = 1312,0,0,0 %; literal MCASAV$S_F72 = 16; ! F72 macro MCASAV$Q_F73 = 1328,0,0,0 %; literal MCASAV$S_F73 = 16; ! F73 macro MCASAV$Q_F74 = 1344,0,0,0 %; literal MCASAV$S_F74 = 16; ! F74 macro MCASAV$Q_F75 = 1360,0,0,0 %; literal MCASAV$S_F75 = 16; ! F75 macro MCASAV$Q_F76 = 1376,0,0,0 %; literal MCASAV$S_F76 = 16; ! F76 macro MCASAV$Q_F77 = 1392,0,0,0 %; literal MCASAV$S_F77 = 16; ! F77 macro MCASAV$Q_F78 = 1408,0,0,0 %; literal MCASAV$S_F78 = 16; ! F78 macro MCASAV$Q_F79 = 1424,0,0,0 %; literal MCASAV$S_F79 = 16; ! F79 macro MCASAV$Q_F80 = 1440,0,0,0 %; literal MCASAV$S_F80 = 16; ! F80 macro MCASAV$Q_F81 = 1456,0,0,0 %; literal MCASAV$S_F81 = 16; ! F81 macro MCASAV$Q_F82 = 1472,0,0,0 %; literal MCASAV$S_F82 = 16; ! F82 macro MCASAV$Q_F83 = 1488,0,0,0 %; literal MCASAV$S_F83 = 16; ! F83 macro MCASAV$Q_F84 = 1504,0,0,0 %; literal MCASAV$S_F84 = 16; ! F84 macro MCASAV$Q_F85 = 1520,0,0,0 %; literal MCASAV$S_F85 = 16; ! F85 macro MCASAV$Q_F86 = 1536,0,0,0 %; literal MCASAV$S_F86 = 16; ! F86 macro MCASAV$Q_F87 = 1552,0,0,0 %; literal MCASAV$S_F87 = 16; ! F87 macro MCASAV$Q_F88 = 1568,0,0,0 %; literal MCASAV$S_F88 = 16; ! F88 macro MCASAV$Q_F89 = 1584,0,0,0 %; literal MCASAV$S_F89 = 16; ! F89 macro MCASAV$Q_F90 = 1600,0,0,0 %; literal MCASAV$S_F90 = 16; ! F90 macro MCASAV$Q_F91 = 1616,0,0,0 %; literal MCASAV$S_F91 = 16; ! F91 macro MCASAV$Q_F92 = 1632,0,0,0 %; literal MCASAV$S_F92 = 16; ! F92 macro MCASAV$Q_F93 = 1648,0,0,0 %; literal MCASAV$S_F93 = 16; ! F93 macro MCASAV$Q_F94 = 1664,0,0,0 %; literal MCASAV$S_F94 = 16; ! F94 macro MCASAV$Q_F95 = 1680,0,0,0 %; literal MCASAV$S_F95 = 16; ! F95 macro MCASAV$Q_F96 = 1696,0,0,0 %; literal MCASAV$S_F96 = 16; ! F96 macro MCASAV$Q_F97 = 1712,0,0,0 %; literal MCASAV$S_F97 = 16; ! F97 macro MCASAV$Q_F98 = 1728,0,0,0 %; literal MCASAV$S_F98 = 16; ! F98 macro MCASAV$Q_F99 = 1744,0,0,0 %; literal MCASAV$S_F99 = 16; ! F99 macro MCASAV$Q_F100 = 1760,0,0,0 %; literal MCASAV$S_F100 = 16; ! F100 macro MCASAV$Q_F101 = 1776,0,0,0 %; literal MCASAV$S_F101 = 16; ! F101 macro MCASAV$Q_F102 = 1792,0,0,0 %; literal MCASAV$S_F102 = 16; ! F102 macro MCASAV$Q_F103 = 1808,0,0,0 %; literal MCASAV$S_F103 = 16; ! F103 macro MCASAV$Q_F104 = 1824,0,0,0 %; literal MCASAV$S_F104 = 16; ! F104 macro MCASAV$Q_F105 = 1840,0,0,0 %; literal MCASAV$S_F105 = 16; ! F105 macro MCASAV$Q_F106 = 1856,0,0,0 %; literal MCASAV$S_F106 = 16; ! F106 macro MCASAV$Q_F107 = 1872,0,0,0 %; literal MCASAV$S_F107 = 16; ! F107 macro MCASAV$Q_F108 = 1888,0,0,0 %; literal MCASAV$S_F108 = 16; ! F108 macro MCASAV$Q_F109 = 1904,0,0,0 %; literal MCASAV$S_F109 = 16; ! F109 macro MCASAV$Q_F110 = 1920,0,0,0 %; literal MCASAV$S_F110 = 16; ! F110 macro MCASAV$Q_F111 = 1936,0,0,0 %; literal MCASAV$S_F111 = 16; ! F111 macro MCASAV$Q_F112 = 1952,0,0,0 %; literal MCASAV$S_F112 = 16; ! F112 macro MCASAV$Q_F113 = 1968,0,0,0 %; literal MCASAV$S_F113 = 16; ! F113 macro MCASAV$Q_F114 = 1984,0,0,0 %; literal MCASAV$S_F114 = 16; ! F114 macro MCASAV$Q_F115 = 2000,0,0,0 %; literal MCASAV$S_F115 = 16; ! F115 macro MCASAV$Q_F116 = 2016,0,0,0 %; literal MCASAV$S_F116 = 16; ! F116 macro MCASAV$Q_F117 = 2032,0,0,0 %; literal MCASAV$S_F117 = 16; ! F117 macro MCASAV$Q_F118 = 2048,0,0,0 %; literal MCASAV$S_F118 = 16; ! F118 macro MCASAV$Q_F119 = 2064,0,0,0 %; literal MCASAV$S_F119 = 16; ! F119 macro MCASAV$Q_F120 = 2080,0,0,0 %; literal MCASAV$S_F120 = 16; ! F120 macro MCASAV$Q_F121 = 2096,0,0,0 %; literal MCASAV$S_F121 = 16; ! F121 macro MCASAV$Q_F122 = 2112,0,0,0 %; literal MCASAV$S_F122 = 16; ! F122 macro MCASAV$Q_F123 = 2128,0,0,0 %; literal MCASAV$S_F123 = 16; ! F123 macro MCASAV$Q_F124 = 2144,0,0,0 %; literal MCASAV$S_F124 = 16; ! F124 macro MCASAV$Q_F125 = 2160,0,0,0 %; literal MCASAV$S_F125 = 16; ! F125 macro MCASAV$Q_F126 = 2176,0,0,0 %; literal MCASAV$S_F126 = 16; ! F126 macro MCASAV$Q_F127 = 2192,0,0,0 %; literal MCASAV$S_F127 = 16; ! F127 ! literal MCASAV$K_LENGTH = 2208; ! Full length of MCASAV$ ! ! Itanium machine check interrupt state type code ! ************************************************************ ! Hardware interrupt type codes literal HWINT$K_PROCESSOR_START = 1; ! CPU coming out of console mode literal HWINT$K_INIT = 2; ! INIT interrupt literal HWINT$K_MCA = 3; ! Machine Check Abort interrupt literal HWINT$K_CMC = 4; ! Corrected Machine Check interrupt literal HWINT$K_CPE = 5; ! Corrected Platform Error interrupt ! IA64 !*** MODULE $HWSCBDEF *** ! ! System Control Block Entry Definitions. The system control block (SCB) ! specifies the entry points for exception and interrupt service routines. ! The first quadword is the virtual address of the service routine associated ! with that entry. The second quadword is an arbitrary parameter to be passed ! to the service routine. The parameter for EVMS for most exceptions and ! interrupts is the virtual address of the procedure descrtor for the service ! routine. ! literal HWSCB$K_VECTOR = 0; ! Entry point address literal HWSCB$K_PARAMETER = 8; ! Arbitrary parameter literal HWSCB$Q_UNUSED_00 = 0; ! %X00 Unused vector literal HWSCB$Q_FLOAT_FAULT = 16; ! %X10 Floating disabled fault literal HWSCB$Q_UNUSED_20 = 32; ! %X20 Unused vector literal HWSCB$Q_UNUSED_30 = 48; ! %X30 Unused vector literal HWSCB$Q_UNUSED_40 = 64; ! %X40 Unused vector literal HWSCB$Q_UNUSED_50 = 80; ! %X50 Unused vector literal HWSCB$Q_UNUSED_60 = 96; ! %X60 Unused vector literal HWSCB$Q_UNUSED_70 = 112; ! %X70 Unused vector literal HWSCB$Q_ACCVIO = 128; ! %X80 Access control violation fault literal HWSCB$Q_TRANSLATION_FAULT = 144; ! %X90 Translation not valid fault literal HWSCB$Q_READ_FAULT = 160; ! %XA0 Fault on read fault literal HWSCB$Q_WRITE_FAULT = 176; ! %XB0 Fault on write fault literal HWSCB$Q_EXECUTE_FAULT = 192; ! %XC0 Fault on execute fault literal HWSCB$Q_ARITHMETIC_TRAP = 512; ! %X200 Arithmetic trap literal HWSCB$Q_KERNEL_AST = 576; ! %X240 Kernel mode AST literal HWSCB$Q_EXEC_AST = 592; ! %X250 Exec mode AST literal HWSCB$Q_SUPER_AST = 608; ! %X260 Super mode AST literal HWSCB$Q_USER_AST = 624; ! %X270 User mode AST literal HWSCB$Q_REPORT_ALIGN_FAULT = 640; ! %X280 Report alignment fault literal HWSCB$Q_UNUSED_290 = 656; ! %X290 Unused vector literal HWSCB$Q_UNUSED_2A0 = 672; ! %X2A0 Unused vector literal HWSCB$Q_UNUSED_2B0 = 688; ! %X2B0 Unused vector literal HWSCB$Q_UNUSED_2C0 = 704; ! %X2C0 Unused vector literal HWSCB$Q_UNUSED_2D0 = 720; ! %X2D0 Unused vector literal HWSCB$Q_UNUSED_2E0 = 736; ! %X2E0 Unused vector literal HWSCB$Q_UNUSED_2F0 = 752; ! %X2F0 Unused vector literal HWSCB$Q_LOAD_F_FLOAT = 768; ! %X300 Load F floating literal HWSCB$Q_LOAD_D_FLOAT = 784; ! %X310 Load D floating literal HWSCB$Q_LOAD_S_FLOAT = 800; ! %X320 Load S floating literal HWSCB$Q_LOAD_T_FLOAT = 816; ! %X330 Load T floating literal HWSCB$Q_STORE_F_FLOAT = 832; ! %X340 Store F floating literal HWSCB$Q_STORE_D_FLOAT = 848; ! %X350 Store D floating literal HWSCB$Q_STORE_S_FLOAT = 864; ! %X360 Store S floating literal HWSCB$Q_STORE_T_FLOAT = 880; ! %X370 Store T floating literal HWSCB$Q_LOAD_SEXT_LONG = 896; ! %X380 Load sign-extended longword literal HWSCB$Q_LOAD_QUAD = 912; ! %X390 Load quadword literal HWSCB$Q_LOAD_SEXT_LONG_L = 928; ! %X3A0 Load sign-extended longword locked literal HWSCB$Q_LOAD_QUAD_L = 944; ! %X3B0 Load quadword locked literal HWSCB$Q_STORE_LONG = 960; ! %X3C0 Store longword literal HWSCB$Q_STORE_QUAD = 976; ! %X3D0 Store quadword literal HWSCB$Q_STORE_LONG_C = 992; ! %X3E0 Store longword conditional literal HWSCB$Q_STORE_QUAD_C = 1008; ! %X3F0 Store quadword conditional literal HWSCB$Q_BREAK_POINT = 1024; ! %X400 Break point trap literal HWSCB$Q_BUG_CHECK = 1040; ! %X410 Bug check trap literal HWSCB$Q_ILLEGAL_INSTRUCTION = 1056; ! %X420 Illegal instruction trap literal HWSCB$Q_ILLEGAL_PAL_OPERAND = 1072; ! %X430 Illegal call PAL operand literal HWSCB$Q_GENTRAP = 1088; ! %X440 Software generated trap literal HWSCB$Q_UNUSED_450 = 1104; ! %X450 Unused vector literal HWSCB$Q_UNUSED_460 = 1120; ! %X460 Unused vector literal HWSCB$Q_UNUSED_470 = 1136; ! %X470 Unused vector literal HWSCB$Q_CHANGE_MODE_KERNEL = 1152; ! %X480 Change mode to kernel literal HWSCB$Q_CHANGE_MODE_EXEC = 1168; ! %X490 Change mode to exec literal HWSCB$Q_CHANGE_MODE_SUPER = 1184; ! %X4A0 Change mode to super literal HWSCB$Q_CHANGE_MODE_USER = 1200; ! %X4B0 Change mode to user literal HWSCB$Q_DIGITAL_1 = 1216; ! %X4C0 Reserved for Digital literal HWSCB$Q_DIGITAL_2 = 1232; ! %X4D0 Reserved for Digital literal HWSCB$Q_DIGITAL_3 = 1248; ! %X4E0 Reserved for Digital literal HWSCB$Q_DIGITAL_4 = 1264; ! %X4F0 Reserved for Digital literal HWSCB$Q_UNUSED_500 = 1280; ! %X500 Unused literal HWSCB$Q_SOFT_INTERRUPT_1 = 1296; ! %X510 Software level 1 interrupt literal HWSCB$Q_SOFT_INTERRUPT_2 = 1312; ! %x520 Software level 2 interrupt literal HWSCB$Q_SOFT_INTERRUPT_3 = 1328; ! %X530 Software level 3 interrupt literal HWSCB$Q_SOFT_INTERRUPT_4 = 1344; ! %X540 Software level 4 interrupt literal HWSCB$Q_SOFT_INTERRUPT_5 = 1360; ! %X550 Software level 5 interrupt literal HWSCB$Q_SOFT_INTERRUPT_6 = 1376; ! %X560 Software level 6 interrupt literal HWSCB$Q_SOFT_INTERRUPT_7 = 1392; ! %X570 Software level 7 interrupt literal HWSCB$Q_SOFT_INTERRUPT_8 = 1408; ! %X580 Software level 8 interrupt literal HWSCB$Q_SOFT_INTERRUPT_9 = 1424; ! %X590 Software level 9 interrupt literal HWSCB$Q_SOFT_INTERRUPT_10 = 1440; ! %X5A0 Software level 10 interrupt literal HWSCB$Q_SOFT_INTERRUPT_11 = 1456; ! %X5B0 Software level 11 interrupt literal HWSCB$Q_SOFT_INTERRUPT_12 = 1472; ! %X5C0 Software level 12 interrupt literal HWSCB$Q_SOFT_INTERRUPT_13 = 1488; ! %X5D0 Software level 13 interrupt literal HWSCB$Q_SOFT_INTERRUPT_14 = 1504; ! %X5E0 Software level 14 interrupt literal HWSCB$Q_SOFT_INTERRUPT_15 = 1520; ! %X5F0 Software level 15 interrupt literal HWSCB$Q_RESCHEDULE = 1328; ! Reschedule interrupt literal HWSCB$Q_IO_POST = 1344; ! I/O post interrupt literal HWSCB$Q_SW_TIMER_INTERRUPT = 1392; ! Software timer interrupt literal HWSCB$Q_IP_CONTROL = 1472; ! IP control literal HWSCB$Q_XDELTA = 1504; ! Xdelta literal HWSCB$Q_INTERVAL_CLOCK = 1536; ! %X600 Interval clock interrupt literal HWSCB$Q_INTERPROCESSOR = 1552; ! %X610 Interprocessor interrupt literal HWSCB$Q_SYSTEM_CORRECTED_ERROR = 1568; ! %X620 System corrected error interrupt literal HWSCB$Q_PROCESS_CORRECTED_ERROR = 1584; ! %X630 Processor corrected error interrupt literal HWSCB$Q_POWER_FAIL = 1600; ! %X640 Power fail interrupt literal HWSCB$Q_PERF_MONITOR = 1616; ! %X650 Reserved for performance monitor literal HWSCB$Q_SYSTEM_MACHINE_CHECK = 1632; ! %X660 System machine check abort literal HWSCB$Q_PROCESSOR_MACHINE_CHECK = 1648; ! %X670 Processor machine check abort literal HWSCB$Q_SYSTEM_ENV_EVENT = 1664; ! %X680 Environmental event interrupt literal HWSCB$Q_PROCESSOR_SPECIFIC_1 = 1680; ! %X690 Reserved - processor specific literal HWSCB$Q_SYSTEM_REC_ERROR = 1696; ! %X6A0 System recoverable machine check abort literal HWSCB$Q_PROC_REC_ERROR = 1712; ! %X6B0 Processer recoverable machine check abort literal HWSCB$Q_IO_INTERRUPT_BASE = 2048; ! %X800 !*** MODULE $IA64_MCHKDEF *** ! ++ ! SAL Record Header ! ! SAL 3.0 ! "Itanium Processor Family System Abstraction Layer Specification, November 2002" ! Section B.2.1, pp. B-2 ! ! (RHD - Record Header) ! -- literal SAL_RHD$M_OEM_SYS_ID_VALID = %X'1'; literal SAL_RHD$S_SAL_RHD = 40; macro SAL_RHD$Q_REC_ID = 0,0,0,0 %; literal SAL_RHD$S_REC_ID = 8; macro SAL_RHD$W_REV = 8,0,16,0 %; macro SAL_RHD$B_MINOR_REV = 8,0,8,0 %; macro SAL_RHD$B_MAJOR_REV = 9,0,8,0 %; macro SAL_RHD$B_ERR_SEVERITY = 10,0,8,0 %; macro SAL_RHD$B_VALID = 11,0,8,0 %; macro SAL_RHD$V_OEM_SYS_ID_VALID = 11,0,1,0 %; macro SAL_RHD$L_REC_LEN = 12,0,32,0 %; macro SAL_RHD$Q_TIMESTAMP = 16,0,0,0 %; literal SAL_RHD$S_TIMESTAMP = 8; macro SAL_RHD$B_SECONDS = 16,0,8,0 %; macro SAL_RHD$B_MINUTES = 17,0,8,0 %; macro SAL_RHD$B_HOURS = 18,0,8,0 %; macro SAL_RHD$B_DAY = 20,0,8,0 %; macro SAL_RHD$B_MONTH = 21,0,8,0 %; macro SAL_RHD$B_YEAR = 22,0,8,0 %; macro SAL_RHD$B_CENTURY = 23,0,8,0 %; macro SAL_RHD$O_OEM_SYS_ID = 24,0,0,0 %; literal SAL_RHD$S_OEM_SYS_ID = 16; macro SAL_RHD$Q_OEM_SYS_ID_L = 24,0,0,0 %; literal SAL_RHD$S_OEM_SYS_ID_L = 8; macro SAL_RHD$Q_OEM_SYS_ID_H = 32,0,0,0 %; literal SAL_RHD$S_OEM_SYS_ID_H = 8; literal SAL_RHD$FRAME_SIZE = 40; ! ++ ! SAL GUID Structure ! ! SAL 3.0 ! "Itanium Processor Family System Abstraction Layer Specification, November 2002" ! Table B-1, pp. B-3 ! ! (GUID - Global Unique ID) ! -- literal SAL_GUID$S_SAL_GUID = 16; macro SAL_GUID$O_GUID = 0,0,0,0 %; literal SAL_GUID$S_GUID = 16; macro SAL_GUID$Q_GUID_L = 0,0,0,0 %; literal SAL_GUID$S_GUID_L = 8; macro SAL_GUID$Q_GUID_H = 8,0,0,0 %; literal SAL_GUID$S_GUID_H = 8; macro SAL_GUID$L_GUID_DATA1 = 0,0,32,0 %; macro SAL_GUID$W_GUID_DATA2 = 4,0,16,0 %; macro SAL_GUID$W_GUID_DATA3 = 6,0,16,0 %; macro SAL_GUID$Q_GUID_DATA4 = 8,0,0,0 %; literal SAL_GUID$S_GUID_DATA4 = 8; macro SAL_GUID$B_GUID_DATA4_0 = 8,0,8,0 %; macro SAL_GUID$B_GUID_DATA4_1 = 9,0,8,0 %; macro SAL_GUID$B_GUID_DATA4_2 = 10,0,8,0 %; macro SAL_GUID$B_GUID_DATA4_3 = 11,0,8,0 %; macro SAL_GUID$B_GUID_DATA4_4 = 12,0,8,0 %; macro SAL_GUID$B_GUID_DATA4_5 = 13,0,8,0 %; macro SAL_GUID$B_GUID_DATA4_6 = 14,0,8,0 %; macro SAL_GUID$B_GUID_DATA4_7 = 15,0,8,0 %; literal SAL_GUID$K_LENGTH = 16; ! ++ ! SAL Section Header ! ! SAL 3.0 ! "Itanium Processor Family System Abstraction Layer Specification, November 2002" ! Section B.2.2, pp. B-2 - B-3 ! ! (SHD - Section Header) ! -- literal SAL_SHD$M_ERR_CORRECTED = %X'1'; literal SAL_SHD$M_CONTAINMENT_WARNING = %X'2'; literal SAL_SHD$M_MUST_RESET = %X'4'; literal SAL_SHD$M_ERR_THRESH_EXCEED = %X'8'; literal SAL_SHD$M_RESOURCE_UNAVAIL = %X'10'; literal SAL_SHD$M_REMAINING_BITS_VALID = %X'80'; literal SAL_SHD$S_SAL_SHD = 24; macro SAL_SHD$R_GUID = 0,0,0,0 %; literal SAL_SHD$S_GUID = 16; macro SAL_SHD$W_REV = 16,0,16,0 %; macro SAL_SHD$B_MINOR_REV = 16,0,8,0 %; macro SAL_SHD$B_MAJOR_REV = 17,0,8,0 %; macro SAL_SHD$B_ERR_RECOVERY = 18,0,8,0 %; macro SAL_SHD$V_ERR_CORRECTED = 18,0,1,0 %; macro SAL_SHD$V_CONTAINMENT_WARNING = 18,1,1,0 %; macro SAL_SHD$V_MUST_RESET = 18,2,1,0 %; macro SAL_SHD$V_ERR_THRESH_EXCEED = 18,3,1,0 %; macro SAL_SHD$V_RESOURCE_UNAVAIL = 18,4,1,0 %; macro SAL_SHD$V_REMAINING_BITS_VALID = 18,7,1,0 %; macro SAL_SHD$L_SECTION_LEN = 20,0,32,0 %; literal SAL_SHD$FRAME_SIZE = 24; ! ++ ! SAL Processor Device Error Info Section - Header Structure ! ! SAL 3.0 ! "Itanium Processor Family System Abstraction Layer Specification, November 2002" ! Section B.2.3, pp. B-4 - B-5 ! ! (PHD - Processor Header) ! -- literal SAL_PHD$M_PROC_ERR_MAP_VALID = %X'1'; literal SAL_PHD$M_PROC_STATE_PARAM_VALID = %X'2'; literal SAL_PHD$M_PROC_CR_LID_VALID = %X'4'; literal SAL_PHD$M_PSI_STATIC_VALID = %X'8'; literal SAL_PHD$M_CPUID_INFO_VALID = %X'1000000'; literal SAL_PHD$S_SAL_PHD = 56; macro SAL_PHD$R_SAL_SHD = 0,0,0,0 %; literal SAL_PHD$S_SAL_SHD = 24; macro SAL_PHD$Q_VALID = 24,0,0,0 %; literal SAL_PHD$S_VALID = 8; macro SAL_PHD$V_PROC_ERR_MAP_VALID = 24,0,1,0 %; macro SAL_PHD$V_PROC_STATE_PARAM_VALID = 24,1,1,0 %; macro SAL_PHD$V_PROC_CR_LID_VALID = 24,2,1,0 %; macro SAL_PHD$V_PSI_STATIC_VALID = 24,3,1,0 %; macro SAL_PHD$V_CACHE_CHECK_NUM = 24,4,4,0 %; literal SAL_PHD$S_CACHE_CHECK_NUM = 4; macro SAL_PHD$V_TLB_CHECK_NUM = 24,8,4,0 %; literal SAL_PHD$S_TLB_CHECK_NUM = 4; macro SAL_PHD$V_BUS_CHECK_NUM = 24,12,4,0 %; literal SAL_PHD$S_BUS_CHECK_NUM = 4; macro SAL_PHD$V_REG_FILE_CHECK_NUM = 24,16,4,0 %; literal SAL_PHD$S_REG_FILE_CHECK_NUM = 4; macro SAL_PHD$V_MS_CHECK_NUM = 24,20,4,0 %; literal SAL_PHD$S_MS_CHECK_NUM = 4; macro SAL_PHD$V_CPUID_INFO_VALID = 24,24,1,0 %; macro SAL_PHD$Q_PROC_ERR_MAP = 32,0,0,0 %; literal SAL_PHD$S_PROC_ERR_MAP = 8; macro SAL_PHD$Q_PROC_STATE_PARAM = 40,0,0,0 %; literal SAL_PHD$S_PROC_STATE_PARAM = 8; macro SAL_PHD$Q_PROC_CR_LID = 48,0,0,0 %; literal SAL_PHD$S_PROC_CR_LID = 8; literal SAL_PHD$FRAME_SIZE = 56; ! ++ ! SAL Processor Device Error Info Section - ID Structure ! ! SAL 3.0 ! "Itanium Processor Family System Abstraction Layer Specification, November 2002" ! Section B.2.3, pp. B-5 ! ! (PIDS - Processor ID Structure) ! -- literal SAL_PIDS$S_SAL_PIDS = 48; macro SAL_PIDS$Q_CPUID = 0,0,0,0 %; literal SAL_PIDS$S_CPUID = 40; macro SAL_PIDS$Q_CPUID0 = 0,0,0,0 %; literal SAL_PIDS$S_CPUID0 = 8; macro SAL_PIDS$Q_CPUID1 = 8,0,0,0 %; literal SAL_PIDS$S_CPUID1 = 8; macro SAL_PIDS$Q_CPUID2 = 16,0,0,0 %; literal SAL_PIDS$S_CPUID2 = 8; macro SAL_PIDS$Q_CPUID3 = 24,0,0,0 %; literal SAL_PIDS$S_CPUID3 = 8; macro SAL_PIDS$Q_CPUID4 = 32,0,0,0 %; literal SAL_PIDS$S_CPUID4 = 8; literal SAL_PIDS$FRAME_SIZE = 48; ! ++ ! Min-State Save Area ! ! "Intel IA-64 Architecture Software Developer's Manual, July 2000" ! Section 11.3.2.3, Figure 11-11, pp. 11-19 ! ! (MSSAS - Min-State Save Area Structure) ! -- literal SAL_MSSAS$S_SAL_MSSAS = 1024; macro SAL_MSSAS$Q_NAT_FOR_SAVED_GR = 0,0,0,0 %; literal SAL_MSSAS$S_NAT_FOR_SAVED_GR = 8; macro SAL_MSSAS$Q_GR1 = 8,0,0,0 %; literal SAL_MSSAS$S_GR1 = 8; macro SAL_MSSAS$Q_GR2 = 16,0,0,0 %; literal SAL_MSSAS$S_GR2 = 8; macro SAL_MSSAS$Q_GR3 = 24,0,0,0 %; literal SAL_MSSAS$S_GR3 = 8; macro SAL_MSSAS$Q_GR4 = 32,0,0,0 %; literal SAL_MSSAS$S_GR4 = 8; macro SAL_MSSAS$Q_GR5 = 40,0,0,0 %; literal SAL_MSSAS$S_GR5 = 8; macro SAL_MSSAS$Q_GR6 = 48,0,0,0 %; literal SAL_MSSAS$S_GR6 = 8; macro SAL_MSSAS$Q_GR7 = 56,0,0,0 %; literal SAL_MSSAS$S_GR7 = 8; macro SAL_MSSAS$Q_GR8 = 64,0,0,0 %; literal SAL_MSSAS$S_GR8 = 8; macro SAL_MSSAS$Q_GR9 = 72,0,0,0 %; literal SAL_MSSAS$S_GR9 = 8; macro SAL_MSSAS$Q_GR10 = 80,0,0,0 %; literal SAL_MSSAS$S_GR10 = 8; macro SAL_MSSAS$Q_GR11 = 88,0,0,0 %; literal SAL_MSSAS$S_GR11 = 8; macro SAL_MSSAS$Q_GR12 = 96,0,0,0 %; literal SAL_MSSAS$S_GR12 = 8; macro SAL_MSSAS$Q_GR13 = 104,0,0,0 %; literal SAL_MSSAS$S_GR13 = 8; macro SAL_MSSAS$Q_GR14 = 112,0,0,0 %; literal SAL_MSSAS$S_GR14 = 8; macro SAL_MSSAS$Q_GR15 = 120,0,0,0 %; literal SAL_MSSAS$S_GR15 = 8; macro SAL_MSSAS$Q_BANK0_GR16 = 128,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR16 = 8; macro SAL_MSSAS$Q_BANK0_GR17 = 136,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR17 = 8; macro SAL_MSSAS$Q_BANK0_GR18 = 144,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR18 = 8; macro SAL_MSSAS$Q_BANK0_GR19 = 152,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR19 = 8; macro SAL_MSSAS$Q_BANK0_GR20 = 160,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR20 = 8; macro SAL_MSSAS$Q_BANK0_GR21 = 168,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR21 = 8; macro SAL_MSSAS$Q_BANK0_GR22 = 176,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR22 = 8; macro SAL_MSSAS$Q_BANK0_GR23 = 184,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR23 = 8; macro SAL_MSSAS$Q_BANK0_GR24 = 192,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR24 = 8; macro SAL_MSSAS$Q_BANK0_GR25 = 200,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR25 = 8; macro SAL_MSSAS$Q_BANK0_GR26 = 208,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR26 = 8; macro SAL_MSSAS$Q_BANK0_GR27 = 216,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR27 = 8; macro SAL_MSSAS$Q_BANK0_GR28 = 224,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR28 = 8; macro SAL_MSSAS$Q_BANK0_GR29 = 232,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR29 = 8; macro SAL_MSSAS$Q_BANK0_GR30 = 240,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR30 = 8; macro SAL_MSSAS$Q_BANK0_GR31 = 248,0,0,0 %; literal SAL_MSSAS$S_BANK0_GR31 = 8; macro SAL_MSSAS$Q_BANK1_GR16 = 256,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR16 = 8; macro SAL_MSSAS$Q_BANK1_GR17 = 264,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR17 = 8; macro SAL_MSSAS$Q_BANK1_GR18 = 272,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR18 = 8; macro SAL_MSSAS$Q_BANK1_GR19 = 280,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR19 = 8; macro SAL_MSSAS$Q_BANK1_GR20 = 288,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR20 = 8; macro SAL_MSSAS$Q_BANK1_GR21 = 296,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR21 = 8; macro SAL_MSSAS$Q_BANK1_GR22 = 304,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR22 = 8; macro SAL_MSSAS$Q_BANK1_GR23 = 312,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR23 = 8; macro SAL_MSSAS$Q_BANK1_GR24 = 320,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR24 = 8; macro SAL_MSSAS$Q_BANK1_GR25 = 328,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR25 = 8; macro SAL_MSSAS$Q_BANK1_GR26 = 336,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR26 = 8; macro SAL_MSSAS$Q_BANK1_GR27 = 344,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR27 = 8; macro SAL_MSSAS$Q_BANK1_GR28 = 352,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR28 = 8; macro SAL_MSSAS$Q_BANK1_GR29 = 360,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR29 = 8; macro SAL_MSSAS$Q_BANK1_GR30 = 368,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR30 = 8; macro SAL_MSSAS$Q_BANK1_GR31 = 376,0,0,0 %; literal SAL_MSSAS$S_BANK1_GR31 = 8; macro SAL_MSSAS$Q_PREDICATE_REGS = 384,0,0,0 %; literal SAL_MSSAS$S_PREDICATE_REGS = 8; macro SAL_MSSAS$Q_BR0 = 392,0,0,0 %; literal SAL_MSSAS$S_BR0 = 8; macro SAL_MSSAS$Q_RSC = 400,0,0,0 %; literal SAL_MSSAS$S_RSC = 8; macro SAL_MSSAS$Q_IIP = 408,0,0,0 %; literal SAL_MSSAS$S_IIP = 8; macro SAL_MSSAS$Q_IPSR = 416,0,0,0 %; literal SAL_MSSAS$S_IPSR = 8; macro SAL_MSSAS$Q_IFS = 424,0,0,0 %; literal SAL_MSSAS$S_IFS = 8; macro SAL_MSSAS$Q_XIP = 432,0,0,0 %; literal SAL_MSSAS$S_XIP = 8; macro SAL_MSSAS$Q_XPSR = 440,0,0,0 %; literal SAL_MSSAS$S_XPSR = 8; macro SAL_MSSAS$Q_XFS = 448,0,0,0 %; literal SAL_MSSAS$S_XFS = 8; literal SAL_MSSAS$FRAME_SIZE = 1024; ! ++ ! SAL Processor Device Error Info Section - Static Structure ! ! SAL 3.0 ! "Itanium Processor Family System Abstraction Layer Specification, November 2002" ! Section B.2.3, pp. B-5 ! ! (PSS - Processor Static Structure) ! -- literal SAL_PSS$M_MINSTATE_VALID = %X'1'; literal SAL_PSS$M_BR_VALID = %X'2'; literal SAL_PSS$M_CR_VALID = %X'4'; literal SAL_PSS$M_AR_VALID = %X'8'; literal SAL_PSS$M_RR_VALID = %X'10'; literal SAL_PSS$M_FR_VALID = %X'20'; literal SAL_PSS$S_SAL_PSS = 5256; macro SAL_PSS$Q_VALID = 0,0,0,0 %; literal SAL_PSS$S_VALID = 8; macro SAL_PSS$V_MINSTATE_VALID = 0,0,1,0 %; macro SAL_PSS$V_BR_VALID = 0,1,1,0 %; macro SAL_PSS$V_CR_VALID = 0,2,1,0 %; macro SAL_PSS$V_AR_VALID = 0,3,1,0 %; macro SAL_PSS$V_RR_VALID = 0,4,1,0 %; macro SAL_PSS$V_FR_VALID = 0,5,1,0 %; macro SAL_PSS$R_MIN_STATE = 8,0,0,0 %; literal SAL_PSS$S_MIN_STATE = 1024; macro SAL_PSS$Q_BRANCH_REGS = 1032,0,0,0 %; literal SAL_PSS$S_BRANCH_REGS = 64; macro SAL_PSS$Q_BR0 = 1032,0,0,0 %; literal SAL_PSS$S_BR0 = 8; macro SAL_PSS$Q_BR1 = 1040,0,0,0 %; literal SAL_PSS$S_BR1 = 8; macro SAL_PSS$Q_BR2 = 1048,0,0,0 %; literal SAL_PSS$S_BR2 = 8; macro SAL_PSS$Q_BR3 = 1056,0,0,0 %; literal SAL_PSS$S_BR3 = 8; macro SAL_PSS$Q_BR4 = 1064,0,0,0 %; literal SAL_PSS$S_BR4 = 8; macro SAL_PSS$Q_BR5 = 1072,0,0,0 %; literal SAL_PSS$S_BR5 = 8; macro SAL_PSS$Q_BR6 = 1080,0,0,0 %; literal SAL_PSS$S_BR6 = 8; macro SAL_PSS$Q_BR7 = 1088,0,0,0 %; literal SAL_PSS$S_BR7 = 8; macro SAL_PSS$Q_CONTROL_REGS = 1096,0,0,0 %; literal SAL_PSS$S_CONTROL_REGS = 1024; macro SAL_PSS$Q_CR0 = 1096,0,0,0 %; literal SAL_PSS$S_CR0 = 8; macro SAL_PSS$Q_CR1 = 1104,0,0,0 %; literal SAL_PSS$S_CR1 = 8; macro SAL_PSS$Q_CR2 = 1112,0,0,0 %; literal SAL_PSS$S_CR2 = 8; macro SAL_PSS$Q_CR3 = 1120,0,0,0 %; literal SAL_PSS$S_CR3 = 8; macro SAL_PSS$Q_CR4 = 1128,0,0,0 %; literal SAL_PSS$S_CR4 = 8; macro SAL_PSS$Q_CR5 = 1136,0,0,0 %; literal SAL_PSS$S_CR5 = 8; macro SAL_PSS$Q_CR6 = 1144,0,0,0 %; literal SAL_PSS$S_CR6 = 8; macro SAL_PSS$Q_CR7 = 1152,0,0,0 %; literal SAL_PSS$S_CR7 = 8; macro SAL_PSS$Q_CR8 = 1160,0,0,0 %; literal SAL_PSS$S_CR8 = 8; macro SAL_PSS$Q_CR9 = 1168,0,0,0 %; literal SAL_PSS$S_CR9 = 8; macro SAL_PSS$Q_CR10 = 1176,0,0,0 %; literal SAL_PSS$S_CR10 = 8; macro SAL_PSS$Q_CR11 = 1184,0,0,0 %; literal SAL_PSS$S_CR11 = 8; macro SAL_PSS$Q_CR12 = 1192,0,0,0 %; literal SAL_PSS$S_CR12 = 8; macro SAL_PSS$Q_CR13 = 1200,0,0,0 %; literal SAL_PSS$S_CR13 = 8; macro SAL_PSS$Q_CR14 = 1208,0,0,0 %; literal SAL_PSS$S_CR14 = 8; macro SAL_PSS$Q_CR15 = 1216,0,0,0 %; literal SAL_PSS$S_CR15 = 8; macro SAL_PSS$Q_CR16 = 1224,0,0,0 %; literal SAL_PSS$S_CR16 = 8; macro SAL_PSS$Q_CR17 = 1232,0,0,0 %; literal SAL_PSS$S_CR17 = 8; macro SAL_PSS$Q_CR18 = 1240,0,0,0 %; literal SAL_PSS$S_CR18 = 8; macro SAL_PSS$Q_CR19 = 1248,0,0,0 %; literal SAL_PSS$S_CR19 = 8; macro SAL_PSS$Q_CR20 = 1256,0,0,0 %; literal SAL_PSS$S_CR20 = 8; macro SAL_PSS$Q_CR21 = 1264,0,0,0 %; literal SAL_PSS$S_CR21 = 8; macro SAL_PSS$Q_CR22 = 1272,0,0,0 %; literal SAL_PSS$S_CR22 = 8; macro SAL_PSS$Q_CR23 = 1280,0,0,0 %; literal SAL_PSS$S_CR23 = 8; macro SAL_PSS$Q_CR24 = 1288,0,0,0 %; literal SAL_PSS$S_CR24 = 8; macro SAL_PSS$Q_CR25 = 1296,0,0,0 %; literal SAL_PSS$S_CR25 = 8; macro SAL_PSS$Q_CR26 = 1304,0,0,0 %; literal SAL_PSS$S_CR26 = 8; macro SAL_PSS$Q_CR27 = 1312,0,0,0 %; literal SAL_PSS$S_CR27 = 8; macro SAL_PSS$Q_CR28 = 1320,0,0,0 %; literal SAL_PSS$S_CR28 = 8; macro SAL_PSS$Q_CR29 = 1328,0,0,0 %; literal SAL_PSS$S_CR29 = 8; macro SAL_PSS$Q_CR30 = 1336,0,0,0 %; literal SAL_PSS$S_CR30 = 8; macro SAL_PSS$Q_CR31 = 1344,0,0,0 %; literal SAL_PSS$S_CR31 = 8; macro SAL_PSS$Q_CR32 = 1352,0,0,0 %; literal SAL_PSS$S_CR32 = 8; macro SAL_PSS$Q_CR33 = 1360,0,0,0 %; literal SAL_PSS$S_CR33 = 8; macro SAL_PSS$Q_CR34 = 1368,0,0,0 %; literal SAL_PSS$S_CR34 = 8; macro SAL_PSS$Q_CR35 = 1376,0,0,0 %; literal SAL_PSS$S_CR35 = 8; macro SAL_PSS$Q_CR36 = 1384,0,0,0 %; literal SAL_PSS$S_CR36 = 8; macro SAL_PSS$Q_CR37 = 1392,0,0,0 %; literal SAL_PSS$S_CR37 = 8; macro SAL_PSS$Q_CR38 = 1400,0,0,0 %; literal SAL_PSS$S_CR38 = 8; macro SAL_PSS$Q_CR39 = 1408,0,0,0 %; literal SAL_PSS$S_CR39 = 8; macro SAL_PSS$Q_CR40 = 1416,0,0,0 %; literal SAL_PSS$S_CR40 = 8; macro SAL_PSS$Q_CR41 = 1424,0,0,0 %; literal SAL_PSS$S_CR41 = 8; macro SAL_PSS$Q_CR42 = 1432,0,0,0 %; literal SAL_PSS$S_CR42 = 8; macro SAL_PSS$Q_CR43 = 1440,0,0,0 %; literal SAL_PSS$S_CR43 = 8; macro SAL_PSS$Q_CR44 = 1448,0,0,0 %; literal SAL_PSS$S_CR44 = 8; macro SAL_PSS$Q_CR45 = 1456,0,0,0 %; literal SAL_PSS$S_CR45 = 8; macro SAL_PSS$Q_CR46 = 1464,0,0,0 %; literal SAL_PSS$S_CR46 = 8; macro SAL_PSS$Q_CR47 = 1472,0,0,0 %; literal SAL_PSS$S_CR47 = 8; macro SAL_PSS$Q_CR48 = 1480,0,0,0 %; literal SAL_PSS$S_CR48 = 8; macro SAL_PSS$Q_CR49 = 1488,0,0,0 %; literal SAL_PSS$S_CR49 = 8; macro SAL_PSS$Q_CR50 = 1496,0,0,0 %; literal SAL_PSS$S_CR50 = 8; macro SAL_PSS$Q_CR51 = 1504,0,0,0 %; literal SAL_PSS$S_CR51 = 8; macro SAL_PSS$Q_CR52 = 1512,0,0,0 %; literal SAL_PSS$S_CR52 = 8; macro SAL_PSS$Q_CR53 = 1520,0,0,0 %; literal SAL_PSS$S_CR53 = 8; macro SAL_PSS$Q_CR54 = 1528,0,0,0 %; literal SAL_PSS$S_CR54 = 8; macro SAL_PSS$Q_CR55 = 1536,0,0,0 %; literal SAL_PSS$S_CR55 = 8; macro SAL_PSS$Q_CR56 = 1544,0,0,0 %; literal SAL_PSS$S_CR56 = 8; macro SAL_PSS$Q_CR57 = 1552,0,0,0 %; literal SAL_PSS$S_CR57 = 8; macro SAL_PSS$Q_CR58 = 1560,0,0,0 %; literal SAL_PSS$S_CR58 = 8; macro SAL_PSS$Q_CR59 = 1568,0,0,0 %; literal SAL_PSS$S_CR59 = 8; macro SAL_PSS$Q_CR60 = 1576,0,0,0 %; literal SAL_PSS$S_CR60 = 8; macro SAL_PSS$Q_CR61 = 1584,0,0,0 %; literal SAL_PSS$S_CR61 = 8; macro SAL_PSS$Q_CR62 = 1592,0,0,0 %; literal SAL_PSS$S_CR62 = 8; macro SAL_PSS$Q_CR63 = 1600,0,0,0 %; literal SAL_PSS$S_CR63 = 8; macro SAL_PSS$Q_CR64 = 1608,0,0,0 %; literal SAL_PSS$S_CR64 = 8; macro SAL_PSS$Q_CR65 = 1616,0,0,0 %; literal SAL_PSS$S_CR65 = 8; macro SAL_PSS$Q_CR66 = 1624,0,0,0 %; literal SAL_PSS$S_CR66 = 8; macro SAL_PSS$Q_CR67 = 1632,0,0,0 %; literal SAL_PSS$S_CR67 = 8; macro SAL_PSS$Q_CR68 = 1640,0,0,0 %; literal SAL_PSS$S_CR68 = 8; macro SAL_PSS$Q_CR69 = 1648,0,0,0 %; literal SAL_PSS$S_CR69 = 8; macro SAL_PSS$Q_CR70 = 1656,0,0,0 %; literal SAL_PSS$S_CR70 = 8; macro SAL_PSS$Q_CR71 = 1664,0,0,0 %; literal SAL_PSS$S_CR71 = 8; macro SAL_PSS$Q_CR72 = 1672,0,0,0 %; literal SAL_PSS$S_CR72 = 8; macro SAL_PSS$Q_CR73 = 1680,0,0,0 %; literal SAL_PSS$S_CR73 = 8; macro SAL_PSS$Q_CR74 = 1688,0,0,0 %; literal SAL_PSS$S_CR74 = 8; macro SAL_PSS$Q_CR75 = 1696,0,0,0 %; literal SAL_PSS$S_CR75 = 8; macro SAL_PSS$Q_CR76 = 1704,0,0,0 %; literal SAL_PSS$S_CR76 = 8; macro SAL_PSS$Q_CR77 = 1712,0,0,0 %; literal SAL_PSS$S_CR77 = 8; macro SAL_PSS$Q_CR78 = 1720,0,0,0 %; literal SAL_PSS$S_CR78 = 8; macro SAL_PSS$Q_CR79 = 1728,0,0,0 %; literal SAL_PSS$S_CR79 = 8; macro SAL_PSS$Q_CR80 = 1736,0,0,0 %; literal SAL_PSS$S_CR80 = 8; macro SAL_PSS$Q_CR81 = 1744,0,0,0 %; literal SAL_PSS$S_CR81 = 8; macro SAL_PSS$Q_CR82 = 1752,0,0,0 %; literal SAL_PSS$S_CR82 = 8; macro SAL_PSS$Q_CR83 = 1760,0,0,0 %; literal SAL_PSS$S_CR83 = 8; macro SAL_PSS$Q_CR84 = 1768,0,0,0 %; literal SAL_PSS$S_CR84 = 8; macro SAL_PSS$Q_CR85 = 1776,0,0,0 %; literal SAL_PSS$S_CR85 = 8; macro SAL_PSS$Q_CR86 = 1784,0,0,0 %; literal SAL_PSS$S_CR86 = 8; macro SAL_PSS$Q_CR87 = 1792,0,0,0 %; literal SAL_PSS$S_CR87 = 8; macro SAL_PSS$Q_CR88 = 1800,0,0,0 %; literal SAL_PSS$S_CR88 = 8; macro SAL_PSS$Q_CR89 = 1808,0,0,0 %; literal SAL_PSS$S_CR89 = 8; macro SAL_PSS$Q_CR90 = 1816,0,0,0 %; literal SAL_PSS$S_CR90 = 8; macro SAL_PSS$Q_CR91 = 1824,0,0,0 %; literal SAL_PSS$S_CR91 = 8; macro SAL_PSS$Q_CR92 = 1832,0,0,0 %; literal SAL_PSS$S_CR92 = 8; macro SAL_PSS$Q_CR93 = 1840,0,0,0 %; literal SAL_PSS$S_CR93 = 8; macro SAL_PSS$Q_CR94 = 1848,0,0,0 %; literal SAL_PSS$S_CR94 = 8; macro SAL_PSS$Q_CR95 = 1856,0,0,0 %; literal SAL_PSS$S_CR95 = 8; macro SAL_PSS$Q_CR96 = 1864,0,0,0 %; literal SAL_PSS$S_CR96 = 8; macro SAL_PSS$Q_CR97 = 1872,0,0,0 %; literal SAL_PSS$S_CR97 = 8; macro SAL_PSS$Q_CR98 = 1880,0,0,0 %; literal SAL_PSS$S_CR98 = 8; macro SAL_PSS$Q_CR99 = 1888,0,0,0 %; literal SAL_PSS$S_CR99 = 8; macro SAL_PSS$Q_CR100 = 1896,0,0,0 %; literal SAL_PSS$S_CR100 = 8; macro SAL_PSS$Q_CR101 = 1904,0,0,0 %; literal SAL_PSS$S_CR101 = 8; macro SAL_PSS$Q_CR102 = 1912,0,0,0 %; literal SAL_PSS$S_CR102 = 8; macro SAL_PSS$Q_CR103 = 1920,0,0,0 %; literal SAL_PSS$S_CR103 = 8; macro SAL_PSS$Q_CR104 = 1928,0,0,0 %; literal SAL_PSS$S_CR104 = 8; macro SAL_PSS$Q_CR105 = 1936,0,0,0 %; literal SAL_PSS$S_CR105 = 8; macro SAL_PSS$Q_CR106 = 1944,0,0,0 %; literal SAL_PSS$S_CR106 = 8; macro SAL_PSS$Q_CR107 = 1952,0,0,0 %; literal SAL_PSS$S_CR107 = 8; macro SAL_PSS$Q_CR108 = 1960,0,0,0 %; literal SAL_PSS$S_CR108 = 8; macro SAL_PSS$Q_CR109 = 1968,0,0,0 %; literal SAL_PSS$S_CR109 = 8; macro SAL_PSS$Q_CR110 = 1976,0,0,0 %; literal SAL_PSS$S_CR110 = 8; macro SAL_PSS$Q_CR111 = 1984,0,0,0 %; literal SAL_PSS$S_CR111 = 8; macro SAL_PSS$Q_CR112 = 1992,0,0,0 %; literal SAL_PSS$S_CR112 = 8; macro SAL_PSS$Q_CR113 = 2000,0,0,0 %; literal SAL_PSS$S_CR113 = 8; macro SAL_PSS$Q_CR114 = 2008,0,0,0 %; literal SAL_PSS$S_CR114 = 8; macro SAL_PSS$Q_CR115 = 2016,0,0,0 %; literal SAL_PSS$S_CR115 = 8; macro SAL_PSS$Q_CR116 = 2024,0,0,0 %; literal SAL_PSS$S_CR116 = 8; macro SAL_PSS$Q_CR117 = 2032,0,0,0 %; literal SAL_PSS$S_CR117 = 8; macro SAL_PSS$Q_CR118 = 2040,0,0,0 %; literal SAL_PSS$S_CR118 = 8; macro SAL_PSS$Q_CR119 = 2048,0,0,0 %; literal SAL_PSS$S_CR119 = 8; macro SAL_PSS$Q_CR120 = 2056,0,0,0 %; literal SAL_PSS$S_CR120 = 8; macro SAL_PSS$Q_CR121 = 2064,0,0,0 %; literal SAL_PSS$S_CR121 = 8; macro SAL_PSS$Q_CR122 = 2072,0,0,0 %; literal SAL_PSS$S_CR122 = 8; macro SAL_PSS$Q_CR123 = 2080,0,0,0 %; literal SAL_PSS$S_CR123 = 8; macro SAL_PSS$Q_CR124 = 2088,0,0,0 %; literal SAL_PSS$S_CR124 = 8; macro SAL_PSS$Q_CR125 = 2096,0,0,0 %; literal SAL_PSS$S_CR125 = 8; macro SAL_PSS$Q_CR126 = 2104,0,0,0 %; literal SAL_PSS$S_CR126 = 8; macro SAL_PSS$Q_CR127 = 2112,0,0,0 %; literal SAL_PSS$S_CR127 = 8; macro SAL_PSS$Q_APPLICATION_REGS = 2120,0,0,0 %; literal SAL_PSS$S_APPLICATION_REGS = 1024; macro SAL_PSS$Q_AR0 = 2120,0,0,0 %; literal SAL_PSS$S_AR0 = 8; macro SAL_PSS$Q_AR1 = 2128,0,0,0 %; literal SAL_PSS$S_AR1 = 8; macro SAL_PSS$Q_AR2 = 2136,0,0,0 %; literal SAL_PSS$S_AR2 = 8; macro SAL_PSS$Q_AR3 = 2144,0,0,0 %; literal SAL_PSS$S_AR3 = 8; macro SAL_PSS$Q_AR4 = 2152,0,0,0 %; literal SAL_PSS$S_AR4 = 8; macro SAL_PSS$Q_AR5 = 2160,0,0,0 %; literal SAL_PSS$S_AR5 = 8; macro SAL_PSS$Q_AR6 = 2168,0,0,0 %; literal SAL_PSS$S_AR6 = 8; macro SAL_PSS$Q_AR7 = 2176,0,0,0 %; literal SAL_PSS$S_AR7 = 8; macro SAL_PSS$Q_AR8 = 2184,0,0,0 %; literal SAL_PSS$S_AR8 = 8; macro SAL_PSS$Q_AR9 = 2192,0,0,0 %; literal SAL_PSS$S_AR9 = 8; macro SAL_PSS$Q_AR10 = 2200,0,0,0 %; literal SAL_PSS$S_AR10 = 8; macro SAL_PSS$Q_AR11 = 2208,0,0,0 %; literal SAL_PSS$S_AR11 = 8; macro SAL_PSS$Q_AR12 = 2216,0,0,0 %; literal SAL_PSS$S_AR12 = 8; macro SAL_PSS$Q_AR13 = 2224,0,0,0 %; literal SAL_PSS$S_AR13 = 8; macro SAL_PSS$Q_AR14 = 2232,0,0,0 %; literal SAL_PSS$S_AR14 = 8; macro SAL_PSS$Q_AR15 = 2240,0,0,0 %; literal SAL_PSS$S_AR15 = 8; macro SAL_PSS$Q_AR16 = 2248,0,0,0 %; literal SAL_PSS$S_AR16 = 8; macro SAL_PSS$Q_AR17 = 2256,0,0,0 %; literal SAL_PSS$S_AR17 = 8; macro SAL_PSS$Q_AR18 = 2264,0,0,0 %; literal SAL_PSS$S_AR18 = 8; macro SAL_PSS$Q_AR19 = 2272,0,0,0 %; literal SAL_PSS$S_AR19 = 8; macro SAL_PSS$Q_AR20 = 2280,0,0,0 %; literal SAL_PSS$S_AR20 = 8; macro SAL_PSS$Q_AR21 = 2288,0,0,0 %; literal SAL_PSS$S_AR21 = 8; macro SAL_PSS$Q_AR22 = 2296,0,0,0 %; literal SAL_PSS$S_AR22 = 8; macro SAL_PSS$Q_AR23 = 2304,0,0,0 %; literal SAL_PSS$S_AR23 = 8; macro SAL_PSS$Q_AR24 = 2312,0,0,0 %; literal SAL_PSS$S_AR24 = 8; macro SAL_PSS$Q_AR25 = 2320,0,0,0 %; literal SAL_PSS$S_AR25 = 8; macro SAL_PSS$Q_AR26 = 2328,0,0,0 %; literal SAL_PSS$S_AR26 = 8; macro SAL_PSS$Q_AR27 = 2336,0,0,0 %; literal SAL_PSS$S_AR27 = 8; macro SAL_PSS$Q_AR28 = 2344,0,0,0 %; literal SAL_PSS$S_AR28 = 8; macro SAL_PSS$Q_AR29 = 2352,0,0,0 %; literal SAL_PSS$S_AR29 = 8; macro SAL_PSS$Q_AR30 = 2360,0,0,0 %; literal SAL_PSS$S_AR30 = 8; macro SAL_PSS$Q_AR31 = 2368,0,0,0 %; literal SAL_PSS$S_AR31 = 8; macro SAL_PSS$Q_AR32 = 2376,0,0,0 %; literal SAL_PSS$S_AR32 = 8; macro SAL_PSS$Q_AR33 = 2384,0,0,0 %; literal SAL_PSS$S_AR33 = 8; macro SAL_PSS$Q_AR34 = 2392,0,0,0 %; literal SAL_PSS$S_AR34 = 8; macro SAL_PSS$Q_AR35 = 2400,0,0,0 %; literal SAL_PSS$S_AR35 = 8; macro SAL_PSS$Q_AR36 = 2408,0,0,0 %; literal SAL_PSS$S_AR36 = 8; macro SAL_PSS$Q_AR37 = 2416,0,0,0 %; literal SAL_PSS$S_AR37 = 8; macro SAL_PSS$Q_AR38 = 2424,0,0,0 %; literal SAL_PSS$S_AR38 = 8; macro SAL_PSS$Q_AR39 = 2432,0,0,0 %; literal SAL_PSS$S_AR39 = 8; macro SAL_PSS$Q_AR40 = 2440,0,0,0 %; literal SAL_PSS$S_AR40 = 8; macro SAL_PSS$Q_AR41 = 2448,0,0,0 %; literal SAL_PSS$S_AR41 = 8; macro SAL_PSS$Q_AR42 = 2456,0,0,0 %; literal SAL_PSS$S_AR42 = 8; macro SAL_PSS$Q_AR43 = 2464,0,0,0 %; literal SAL_PSS$S_AR43 = 8; macro SAL_PSS$Q_AR44 = 2472,0,0,0 %; literal SAL_PSS$S_AR44 = 8; macro SAL_PSS$Q_AR45 = 2480,0,0,0 %; literal SAL_PSS$S_AR45 = 8; macro SAL_PSS$Q_AR46 = 2488,0,0,0 %; literal SAL_PSS$S_AR46 = 8; macro SAL_PSS$Q_AR47 = 2496,0,0,0 %; literal SAL_PSS$S_AR47 = 8; macro SAL_PSS$Q_AR48 = 2504,0,0,0 %; literal SAL_PSS$S_AR48 = 8; macro SAL_PSS$Q_AR49 = 2512,0,0,0 %; literal SAL_PSS$S_AR49 = 8; macro SAL_PSS$Q_AR50 = 2520,0,0,0 %; literal SAL_PSS$S_AR50 = 8; macro SAL_PSS$Q_AR51 = 2528,0,0,0 %; literal SAL_PSS$S_AR51 = 8; macro SAL_PSS$Q_AR52 = 2536,0,0,0 %; literal SAL_PSS$S_AR52 = 8; macro SAL_PSS$Q_AR53 = 2544,0,0,0 %; literal SAL_PSS$S_AR53 = 8; macro SAL_PSS$Q_AR54 = 2552,0,0,0 %; literal SAL_PSS$S_AR54 = 8; macro SAL_PSS$Q_AR55 = 2560,0,0,0 %; literal SAL_PSS$S_AR55 = 8; macro SAL_PSS$Q_AR56 = 2568,0,0,0 %; literal SAL_PSS$S_AR56 = 8; macro SAL_PSS$Q_AR57 = 2576,0,0,0 %; literal SAL_PSS$S_AR57 = 8; macro SAL_PSS$Q_AR58 = 2584,0,0,0 %; literal SAL_PSS$S_AR58 = 8; macro SAL_PSS$Q_AR59 = 2592,0,0,0 %; literal SAL_PSS$S_AR59 = 8; macro SAL_PSS$Q_AR60 = 2600,0,0,0 %; literal SAL_PSS$S_AR60 = 8; macro SAL_PSS$Q_AR61 = 2608,0,0,0 %; literal SAL_PSS$S_AR61 = 8; macro SAL_PSS$Q_AR62 = 2616,0,0,0 %; literal SAL_PSS$S_AR62 = 8; macro SAL_PSS$Q_AR63 = 2624,0,0,0 %; literal SAL_PSS$S_AR63 = 8; macro SAL_PSS$Q_AR64 = 2632,0,0,0 %; literal SAL_PSS$S_AR64 = 8; macro SAL_PSS$Q_AR65 = 2640,0,0,0 %; literal SAL_PSS$S_AR65 = 8; macro SAL_PSS$Q_AR66 = 2648,0,0,0 %; literal SAL_PSS$S_AR66 = 8; macro SAL_PSS$Q_AR67 = 2656,0,0,0 %; literal SAL_PSS$S_AR67 = 8; macro SAL_PSS$Q_AR68 = 2664,0,0,0 %; literal SAL_PSS$S_AR68 = 8; macro SAL_PSS$Q_AR69 = 2672,0,0,0 %; literal SAL_PSS$S_AR69 = 8; macro SAL_PSS$Q_AR70 = 2680,0,0,0 %; literal SAL_PSS$S_AR70 = 8; macro SAL_PSS$Q_AR71 = 2688,0,0,0 %; literal SAL_PSS$S_AR71 = 8; macro SAL_PSS$Q_AR72 = 2696,0,0,0 %; literal SAL_PSS$S_AR72 = 8; macro SAL_PSS$Q_AR73 = 2704,0,0,0 %; literal SAL_PSS$S_AR73 = 8; macro SAL_PSS$Q_AR74 = 2712,0,0,0 %; literal SAL_PSS$S_AR74 = 8; macro SAL_PSS$Q_AR75 = 2720,0,0,0 %; literal SAL_PSS$S_AR75 = 8; macro SAL_PSS$Q_AR76 = 2728,0,0,0 %; literal SAL_PSS$S_AR76 = 8; macro SAL_PSS$Q_AR77 = 2736,0,0,0 %; literal SAL_PSS$S_AR77 = 8; macro SAL_PSS$Q_AR78 = 2744,0,0,0 %; literal SAL_PSS$S_AR78 = 8; macro SAL_PSS$Q_AR79 = 2752,0,0,0 %; literal SAL_PSS$S_AR79 = 8; macro SAL_PSS$Q_AR80 = 2760,0,0,0 %; literal SAL_PSS$S_AR80 = 8; macro SAL_PSS$Q_AR81 = 2768,0,0,0 %; literal SAL_PSS$S_AR81 = 8; macro SAL_PSS$Q_AR82 = 2776,0,0,0 %; literal SAL_PSS$S_AR82 = 8; macro SAL_PSS$Q_AR83 = 2784,0,0,0 %; literal SAL_PSS$S_AR83 = 8; macro SAL_PSS$Q_AR84 = 2792,0,0,0 %; literal SAL_PSS$S_AR84 = 8; macro SAL_PSS$Q_AR85 = 2800,0,0,0 %; literal SAL_PSS$S_AR85 = 8; macro SAL_PSS$Q_AR86 = 2808,0,0,0 %; literal SAL_PSS$S_AR86 = 8; macro SAL_PSS$Q_AR87 = 2816,0,0,0 %; literal SAL_PSS$S_AR87 = 8; macro SAL_PSS$Q_AR88 = 2824,0,0,0 %; literal SAL_PSS$S_AR88 = 8; macro SAL_PSS$Q_AR89 = 2832,0,0,0 %; literal SAL_PSS$S_AR89 = 8; macro SAL_PSS$Q_AR90 = 2840,0,0,0 %; literal SAL_PSS$S_AR90 = 8; macro SAL_PSS$Q_AR91 = 2848,0,0,0 %; literal SAL_PSS$S_AR91 = 8; macro SAL_PSS$Q_AR92 = 2856,0,0,0 %; literal SAL_PSS$S_AR92 = 8; macro SAL_PSS$Q_AR93 = 2864,0,0,0 %; literal SAL_PSS$S_AR93 = 8; macro SAL_PSS$Q_AR94 = 2872,0,0,0 %; literal SAL_PSS$S_AR94 = 8; macro SAL_PSS$Q_AR95 = 2880,0,0,0 %; literal SAL_PSS$S_AR95 = 8; macro SAL_PSS$Q_AR96 = 2888,0,0,0 %; literal SAL_PSS$S_AR96 = 8; macro SAL_PSS$Q_AR97 = 2896,0,0,0 %; literal SAL_PSS$S_AR97 = 8; macro SAL_PSS$Q_AR98 = 2904,0,0,0 %; literal SAL_PSS$S_AR98 = 8; macro SAL_PSS$Q_AR99 = 2912,0,0,0 %; literal SAL_PSS$S_AR99 = 8; macro SAL_PSS$Q_AR100 = 2920,0,0,0 %; literal SAL_PSS$S_AR100 = 8; macro SAL_PSS$Q_AR101 = 2928,0,0,0 %; literal SAL_PSS$S_AR101 = 8; macro SAL_PSS$Q_AR102 = 2936,0,0,0 %; literal SAL_PSS$S_AR102 = 8; macro SAL_PSS$Q_AR103 = 2944,0,0,0 %; literal SAL_PSS$S_AR103 = 8; macro SAL_PSS$Q_AR104 = 2952,0,0,0 %; literal SAL_PSS$S_AR104 = 8; macro SAL_PSS$Q_AR105 = 2960,0,0,0 %; literal SAL_PSS$S_AR105 = 8; macro SAL_PSS$Q_AR106 = 2968,0,0,0 %; literal SAL_PSS$S_AR106 = 8; macro SAL_PSS$Q_AR107 = 2976,0,0,0 %; literal SAL_PSS$S_AR107 = 8; macro SAL_PSS$Q_AR108 = 2984,0,0,0 %; literal SAL_PSS$S_AR108 = 8; macro SAL_PSS$Q_AR109 = 2992,0,0,0 %; literal SAL_PSS$S_AR109 = 8; macro SAL_PSS$Q_AR110 = 3000,0,0,0 %; literal SAL_PSS$S_AR110 = 8; macro SAL_PSS$Q_AR111 = 3008,0,0,0 %; literal SAL_PSS$S_AR111 = 8; macro SAL_PSS$Q_AR112 = 3016,0,0,0 %; literal SAL_PSS$S_AR112 = 8; macro SAL_PSS$Q_AR113 = 3024,0,0,0 %; literal SAL_PSS$S_AR113 = 8; macro SAL_PSS$Q_AR114 = 3032,0,0,0 %; literal SAL_PSS$S_AR114 = 8; macro SAL_PSS$Q_AR115 = 3040,0,0,0 %; literal SAL_PSS$S_AR115 = 8; macro SAL_PSS$Q_AR116 = 3048,0,0,0 %; literal SAL_PSS$S_AR116 = 8; macro SAL_PSS$Q_AR117 = 3056,0,0,0 %; literal SAL_PSS$S_AR117 = 8; macro SAL_PSS$Q_AR118 = 3064,0,0,0 %; literal SAL_PSS$S_AR118 = 8; macro SAL_PSS$Q_AR119 = 3072,0,0,0 %; literal SAL_PSS$S_AR119 = 8; macro SAL_PSS$Q_AR120 = 3080,0,0,0 %; literal SAL_PSS$S_AR120 = 8; macro SAL_PSS$Q_AR121 = 3088,0,0,0 %; literal SAL_PSS$S_AR121 = 8; macro SAL_PSS$Q_AR122 = 3096,0,0,0 %; literal SAL_PSS$S_AR122 = 8; macro SAL_PSS$Q_AR123 = 3104,0,0,0 %; literal SAL_PSS$S_AR123 = 8; macro SAL_PSS$Q_AR124 = 3112,0,0,0 %; literal SAL_PSS$S_AR124 = 8; macro SAL_PSS$Q_AR125 = 3120,0,0,0 %; literal SAL_PSS$S_AR125 = 8; macro SAL_PSS$Q_AR126 = 3128,0,0,0 %; literal SAL_PSS$S_AR126 = 8; macro SAL_PSS$Q_AR127 = 3136,0,0,0 %; literal SAL_PSS$S_AR127 = 8; macro SAL_PSS$Q_REGION_REGS = 3144,0,0,0 %; literal SAL_PSS$S_REGION_REGS = 64; macro SAL_PSS$Q_RR0 = 3144,0,0,0 %; literal SAL_PSS$S_RR0 = 8; macro SAL_PSS$Q_RR1 = 3152,0,0,0 %; literal SAL_PSS$S_RR1 = 8; macro SAL_PSS$Q_RR2 = 3160,0,0,0 %; literal SAL_PSS$S_RR2 = 8; macro SAL_PSS$Q_RR3 = 3168,0,0,0 %; literal SAL_PSS$S_RR3 = 8; macro SAL_PSS$Q_RR4 = 3176,0,0,0 %; literal SAL_PSS$S_RR4 = 8; macro SAL_PSS$Q_RR5 = 3184,0,0,0 %; literal SAL_PSS$S_RR5 = 8; macro SAL_PSS$Q_RR6 = 3192,0,0,0 %; literal SAL_PSS$S_RR6 = 8; macro SAL_PSS$Q_RR7 = 3200,0,0,0 %; literal SAL_PSS$S_RR7 = 8; macro SAL_PSS$O_FP_REGS = 3208,0,0,0 %; literal SAL_PSS$S_FP_REGS = 2048; macro SAL_PSS$O_FP0 = 3208,0,0,0 %; literal SAL_PSS$S_FP0 = 16; macro SAL_PSS$O_FP1 = 3224,0,0,0 %; literal SAL_PSS$S_FP1 = 16; macro SAL_PSS$O_FP2 = 3240,0,0,0 %; literal SAL_PSS$S_FP2 = 16; macro SAL_PSS$O_FP3 = 3256,0,0,0 %; literal SAL_PSS$S_FP3 = 16; macro SAL_PSS$O_FP4 = 3272,0,0,0 %; literal SAL_PSS$S_FP4 = 16; macro SAL_PSS$O_FP5 = 3288,0,0,0 %; literal SAL_PSS$S_FP5 = 16; macro SAL_PSS$O_FP6 = 3304,0,0,0 %; literal SAL_PSS$S_FP6 = 16; macro SAL_PSS$O_FP7 = 3320,0,0,0 %; literal SAL_PSS$S_FP7 = 16; macro SAL_PSS$O_FP8 = 3336,0,0,0 %; literal SAL_PSS$S_FP8 = 16; macro SAL_PSS$O_FP9 = 3352,0,0,0 %; literal SAL_PSS$S_FP9 = 16; macro SAL_PSS$O_FP10 = 3368,0,0,0 %; literal SAL_PSS$S_FP10 = 16; macro SAL_PSS$O_FP11 = 3384,0,0,0 %; literal SAL_PSS$S_FP11 = 16; macro SAL_PSS$O_FP12 = 3400,0,0,0 %; literal SAL_PSS$S_FP12 = 16; macro SAL_PSS$O_FP13 = 3416,0,0,0 %; literal SAL_PSS$S_FP13 = 16; macro SAL_PSS$O_FP14 = 3432,0,0,0 %; literal SAL_PSS$S_FP14 = 16; macro SAL_PSS$O_FP15 = 3448,0,0,0 %; literal SAL_PSS$S_FP15 = 16; macro SAL_PSS$O_FP16 = 3464,0,0,0 %; literal SAL_PSS$S_FP16 = 16; macro SAL_PSS$O_FP17 = 3480,0,0,0 %; literal SAL_PSS$S_FP17 = 16; macro SAL_PSS$O_FP18 = 3496,0,0,0 %; literal SAL_PSS$S_FP18 = 16; macro SAL_PSS$O_FP19 = 3512,0,0,0 %; literal SAL_PSS$S_FP19 = 16; macro SAL_PSS$O_FP20 = 3528,0,0,0 %; literal SAL_PSS$S_FP20 = 16; macro SAL_PSS$O_FP21 = 3544,0,0,0 %; literal SAL_PSS$S_FP21 = 16; macro SAL_PSS$O_FP22 = 3560,0,0,0 %; literal SAL_PSS$S_FP22 = 16; macro SAL_PSS$O_FP23 = 3576,0,0,0 %; literal SAL_PSS$S_FP23 = 16; macro SAL_PSS$O_FP24 = 3592,0,0,0 %; literal SAL_PSS$S_FP24 = 16; macro SAL_PSS$O_FP25 = 3608,0,0,0 %; literal SAL_PSS$S_FP25 = 16; macro SAL_PSS$O_FP26 = 3624,0,0,0 %; literal SAL_PSS$S_FP26 = 16; macro SAL_PSS$O_FP27 = 3640,0,0,0 %; literal SAL_PSS$S_FP27 = 16; macro SAL_PSS$O_FP28 = 3656,0,0,0 %; literal SAL_PSS$S_FP28 = 16; macro SAL_PSS$O_FP29 = 3672,0,0,0 %; literal SAL_PSS$S_FP29 = 16; macro SAL_PSS$O_FP30 = 3688,0,0,0 %; literal SAL_PSS$S_FP30 = 16; macro SAL_PSS$O_FP31 = 3704,0,0,0 %; literal SAL_PSS$S_FP31 = 16; macro SAL_PSS$O_FP32 = 3720,0,0,0 %; literal SAL_PSS$S_FP32 = 16; macro SAL_PSS$O_FP33 = 3736,0,0,0 %; literal SAL_PSS$S_FP33 = 16; macro SAL_PSS$O_FP34 = 3752,0,0,0 %; literal SAL_PSS$S_FP34 = 16; macro SAL_PSS$O_FP35 = 3768,0,0,0 %; literal SAL_PSS$S_FP35 = 16; macro SAL_PSS$O_FP36 = 3784,0,0,0 %; literal SAL_PSS$S_FP36 = 16; macro SAL_PSS$O_FP37 = 3800,0,0,0 %; literal SAL_PSS$S_FP37 = 16; macro SAL_PSS$O_FP38 = 3816,0,0,0 %; literal SAL_PSS$S_FP38 = 16; macro SAL_PSS$O_FP39 = 3832,0,0,0 %; literal SAL_PSS$S_FP39 = 16; macro SAL_PSS$O_FP40 = 3848,0,0,0 %; literal SAL_PSS$S_FP40 = 16; macro SAL_PSS$O_FP41 = 3864,0,0,0 %; literal SAL_PSS$S_FP41 = 16; macro SAL_PSS$O_FP42 = 3880,0,0,0 %; literal SAL_PSS$S_FP42 = 16; macro SAL_PSS$O_FP43 = 3896,0,0,0 %; literal SAL_PSS$S_FP43 = 16; macro SAL_PSS$O_FP44 = 3912,0,0,0 %; literal SAL_PSS$S_FP44 = 16; macro SAL_PSS$O_FP45 = 3928,0,0,0 %; literal SAL_PSS$S_FP45 = 16; macro SAL_PSS$O_FP46 = 3944,0,0,0 %; literal SAL_PSS$S_FP46 = 16; macro SAL_PSS$O_FP47 = 3960,0,0,0 %; literal SAL_PSS$S_FP47 = 16; macro SAL_PSS$O_FP48 = 3976,0,0,0 %; literal SAL_PSS$S_FP48 = 16; macro SAL_PSS$O_FP49 = 3992,0,0,0 %; literal SAL_PSS$S_FP49 = 16; macro SAL_PSS$O_FP50 = 4008,0,0,0 %; literal SAL_PSS$S_FP50 = 16; macro SAL_PSS$O_FP51 = 4024,0,0,0 %; literal SAL_PSS$S_FP51 = 16; macro SAL_PSS$O_FP52 = 4040,0,0,0 %; literal SAL_PSS$S_FP52 = 16; macro SAL_PSS$O_FP53 = 4056,0,0,0 %; literal SAL_PSS$S_FP53 = 16; macro SAL_PSS$O_FP54 = 4072,0,0,0 %; literal SAL_PSS$S_FP54 = 16; macro SAL_PSS$O_FP55 = 4088,0,0,0 %; literal SAL_PSS$S_FP55 = 16; macro SAL_PSS$O_FP56 = 4104,0,0,0 %; literal SAL_PSS$S_FP56 = 16; macro SAL_PSS$O_FP57 = 4120,0,0,0 %; literal SAL_PSS$S_FP57 = 16; macro SAL_PSS$O_FP58 = 4136,0,0,0 %; literal SAL_PSS$S_FP58 = 16; macro SAL_PSS$O_FP59 = 4152,0,0,0 %; literal SAL_PSS$S_FP59 = 16; macro SAL_PSS$O_FP60 = 4168,0,0,0 %; literal SAL_PSS$S_FP60 = 16; macro SAL_PSS$O_FP61 = 4184,0,0,0 %; literal SAL_PSS$S_FP61 = 16; macro SAL_PSS$O_FP62 = 4200,0,0,0 %; literal SAL_PSS$S_FP62 = 16; macro SAL_PSS$O_FP63 = 4216,0,0,0 %; literal SAL_PSS$S_FP63 = 16; macro SAL_PSS$O_FP64 = 4232,0,0,0 %; literal SAL_PSS$S_FP64 = 16; macro SAL_PSS$O_FP65 = 4248,0,0,0 %; literal SAL_PSS$S_FP65 = 16; macro SAL_PSS$O_FP66 = 4264,0,0,0 %; literal SAL_PSS$S_FP66 = 16; macro SAL_PSS$O_FP67 = 4280,0,0,0 %; literal SAL_PSS$S_FP67 = 16; macro SAL_PSS$O_FP68 = 4296,0,0,0 %; literal SAL_PSS$S_FP68 = 16; macro SAL_PSS$O_FP69 = 4312,0,0,0 %; literal SAL_PSS$S_FP69 = 16; macro SAL_PSS$O_FP70 = 4328,0,0,0 %; literal SAL_PSS$S_FP70 = 16; macro SAL_PSS$O_FP71 = 4344,0,0,0 %; literal SAL_PSS$S_FP71 = 16; macro SAL_PSS$O_FP72 = 4360,0,0,0 %; literal SAL_PSS$S_FP72 = 16; macro SAL_PSS$O_FP73 = 4376,0,0,0 %; literal SAL_PSS$S_FP73 = 16; macro SAL_PSS$O_FP74 = 4392,0,0,0 %; literal SAL_PSS$S_FP74 = 16; macro SAL_PSS$O_FP75 = 4408,0,0,0 %; literal SAL_PSS$S_FP75 = 16; macro SAL_PSS$O_FP76 = 4424,0,0,0 %; literal SAL_PSS$S_FP76 = 16; macro SAL_PSS$O_FP77 = 4440,0,0,0 %; literal SAL_PSS$S_FP77 = 16; macro SAL_PSS$O_FP78 = 4456,0,0,0 %; literal SAL_PSS$S_FP78 = 16; macro SAL_PSS$O_FP79 = 4472,0,0,0 %; literal SAL_PSS$S_FP79 = 16; macro SAL_PSS$O_FP80 = 4488,0,0,0 %; literal SAL_PSS$S_FP80 = 16; macro SAL_PSS$O_FP81 = 4504,0,0,0 %; literal SAL_PSS$S_FP81 = 16; macro SAL_PSS$O_FP82 = 4520,0,0,0 %; literal SAL_PSS$S_FP82 = 16; macro SAL_PSS$O_FP83 = 4536,0,0,0 %; literal SAL_PSS$S_FP83 = 16; macro SAL_PSS$O_FP84 = 4552,0,0,0 %; literal SAL_PSS$S_FP84 = 16; macro SAL_PSS$O_FP85 = 4568,0,0,0 %; literal SAL_PSS$S_FP85 = 16; macro SAL_PSS$O_FP86 = 4584,0,0,0 %; literal SAL_PSS$S_FP86 = 16; macro SAL_PSS$O_FP87 = 4600,0,0,0 %; literal SAL_PSS$S_FP87 = 16; macro SAL_PSS$O_FP88 = 4616,0,0,0 %; literal SAL_PSS$S_FP88 = 16; macro SAL_PSS$O_FP89 = 4632,0,0,0 %; literal SAL_PSS$S_FP89 = 16; macro SAL_PSS$O_FP90 = 4648,0,0,0 %; literal SAL_PSS$S_FP90 = 16; macro SAL_PSS$O_FP91 = 4664,0,0,0 %; literal SAL_PSS$S_FP91 = 16; macro SAL_PSS$O_FP92 = 4680,0,0,0 %; literal SAL_PSS$S_FP92 = 16; macro SAL_PSS$O_FP93 = 4696,0,0,0 %; literal SAL_PSS$S_FP93 = 16; macro SAL_PSS$O_FP94 = 4712,0,0,0 %; literal SAL_PSS$S_FP94 = 16; macro SAL_PSS$O_FP95 = 4728,0,0,0 %; literal SAL_PSS$S_FP95 = 16; macro SAL_PSS$O_FP96 = 4744,0,0,0 %; literal SAL_PSS$S_FP96 = 16; macro SAL_PSS$O_FP97 = 4760,0,0,0 %; literal SAL_PSS$S_FP97 = 16; macro SAL_PSS$O_FP98 = 4776,0,0,0 %; literal SAL_PSS$S_FP98 = 16; macro SAL_PSS$O_FP99 = 4792,0,0,0 %; literal SAL_PSS$S_FP99 = 16; macro SAL_PSS$O_FP100 = 4808,0,0,0 %; literal SAL_PSS$S_FP100 = 16; macro SAL_PSS$O_FP101 = 4824,0,0,0 %; literal SAL_PSS$S_FP101 = 16; macro SAL_PSS$O_FP102 = 4840,0,0,0 %; literal SAL_PSS$S_FP102 = 16; macro SAL_PSS$O_FP103 = 4856,0,0,0 %; literal SAL_PSS$S_FP103 = 16; macro SAL_PSS$O_FP104 = 4872,0,0,0 %; literal SAL_PSS$S_FP104 = 16; macro SAL_PSS$O_FP105 = 4888,0,0,0 %; literal SAL_PSS$S_FP105 = 16; macro SAL_PSS$O_FP106 = 4904,0,0,0 %; literal SAL_PSS$S_FP106 = 16; macro SAL_PSS$O_FP107 = 4920,0,0,0 %; literal SAL_PSS$S_FP107 = 16; macro SAL_PSS$O_FP108 = 4936,0,0,0 %; literal SAL_PSS$S_FP108 = 16; macro SAL_PSS$O_FP109 = 4952,0,0,0 %; literal SAL_PSS$S_FP109 = 16; macro SAL_PSS$O_FP110 = 4968,0,0,0 %; literal SAL_PSS$S_FP110 = 16; macro SAL_PSS$O_FP111 = 4984,0,0,0 %; literal SAL_PSS$S_FP111 = 16; macro SAL_PSS$O_FP112 = 5000,0,0,0 %; literal SAL_PSS$S_FP112 = 16; macro SAL_PSS$O_FP113 = 5016,0,0,0 %; literal SAL_PSS$S_FP113 = 16; macro SAL_PSS$O_FP114 = 5032,0,0,0 %; literal SAL_PSS$S_FP114 = 16; macro SAL_PSS$O_FP115 = 5048,0,0,0 %; literal SAL_PSS$S_FP115 = 16; macro SAL_PSS$O_FP116 = 5064,0,0,0 %; literal SAL_PSS$S_FP116 = 16; macro SAL_PSS$O_FP117 = 5080,0,0,0 %; literal SAL_PSS$S_FP117 = 16; macro SAL_PSS$O_FP118 = 5096,0,0,0 %; literal SAL_PSS$S_FP118 = 16; macro SAL_PSS$O_FP119 = 5112,0,0,0 %; literal SAL_PSS$S_FP119 = 16; macro SAL_PSS$O_FP120 = 5128,0,0,0 %; literal SAL_PSS$S_FP120 = 16; macro SAL_PSS$O_FP121 = 5144,0,0,0 %; literal SAL_PSS$S_FP121 = 16; macro SAL_PSS$O_FP122 = 5160,0,0,0 %; literal SAL_PSS$S_FP122 = 16; macro SAL_PSS$O_FP123 = 5176,0,0,0 %; literal SAL_PSS$S_FP123 = 16; macro SAL_PSS$O_FP124 = 5192,0,0,0 %; literal SAL_PSS$S_FP124 = 16; macro SAL_PSS$O_FP125 = 5208,0,0,0 %; literal SAL_PSS$S_FP125 = 16; macro SAL_PSS$O_FP126 = 5224,0,0,0 %; literal SAL_PSS$S_FP126 = 16; macro SAL_PSS$O_FP127 = 5240,0,0,0 %; literal SAL_PSS$S_FP127 = 16; literal SAL_PSS$FRAME_SIZE = 5256; ! ++ ! SAL Processor Device Error Info Section - Module Structure ! ! SAL 3.0 ! "Itanium Processor Family System Abstraction Layer Specification, November 2002" ! Section B.2.3, pp. B-5 - B-6 ! ! (PMS - Processor Module Structure) ! -- literal SAL_PMS$M_CHECK_VALID = %X'1'; literal SAL_PMS$M_TARGET_ID_VALID = %X'2'; literal SAL_PMS$M_REQ_ID_VALID = %X'4'; literal SAL_PMS$M_RESP_ID_VALID = %X'8'; literal SAL_PMS$M_PRECISE_IP_VALID = %X'10'; literal SAL_PMS$S_SAL_PMS = 48; macro SAL_PMS$Q_VALID = 0,0,0,0 %; literal SAL_PMS$S_VALID = 8; macro SAL_PMS$V_CHECK_VALID = 0,0,1,0 %; macro SAL_PMS$V_TARGET_ID_VALID = 0,1,1,0 %; macro SAL_PMS$V_REQ_ID_VALID = 0,2,1,0 %; macro SAL_PMS$V_RESP_ID_VALID = 0,3,1,0 %; macro SAL_PMS$V_PRECISE_IP_VALID = 0,4,1,0 %; macro SAL_PMS$Q_CHECK = 8,0,0,0 %; literal SAL_PMS$S_CHECK = 8; macro SAL_PMS$Q_TARGET_ID = 16,0,0,0 %; literal SAL_PMS$S_TARGET_ID = 8; macro SAL_PMS$Q_REQ_ID = 24,0,0,0 %; literal SAL_PMS$S_REQ_ID = 8; macro SAL_PMS$Q_RESP_ID = 32,0,0,0 %; literal SAL_PMS$S_RESP_ID = 8; macro SAL_PMS$Q_PRECISE_IP = 40,0,0,0 %; literal SAL_PMS$S_PRECISE_IP = 8; literal SAL_PMS$FRAME_SIZE = 48; ! ++ ! SAL Platform Memory Device Error Info Section - Header Structure ! ! SAL 3.0 ! "Itanium Processor Family System Abstraction Layer Specification, November 2002" ! Section B.2.4.1, pp. B-6 - B-7 ! ! (SMS - System Memory Section) ! -- literal SAL_SMS$M_ERR_STS_VALID = %X'1'; literal SAL_SMS$M_PHYS_ADDR_VALID = %X'2'; literal SAL_SMS$M_PHYS_ADDR_MASK = %X'4'; literal SAL_SMS$M_NODE_VALID = %X'8'; literal SAL_SMS$M_CARD_VALID = %X'10'; literal SAL_SMS$M_MOD_VALID = %X'20'; literal SAL_SMS$M_BANK_VALID = %X'40'; literal SAL_SMS$M_DEV_VALID = %X'80'; literal SAL_SMS$M_ROW_VALID = %X'100'; literal SAL_SMS$M_COL_VALID = %X'200'; literal SAL_SMS$M_BIT_POS_VALID = %X'400'; literal SAL_SMS$M_REQ_ID_VALID = %X'800'; literal SAL_SMS$M_RESP_ID_VALID = %X'1000'; literal SAL_SMS$M_TARGET_VALID = %X'2000'; literal SAL_SMS$M_BUS_DATA_VALID = %X'4000'; literal SAL_SMS$M_OEM_ID_VALID = %X'8000'; literal SAL_SMS$M_OEM_DATA_VALID = %X'10000'; literal SAL_SMS$M_ADDR = %X'10000'; literal SAL_SMS$M_CONTROL = %X'20000'; literal SAL_SMS$M_DATA = %X'40000'; literal SAL_SMS$M_RESP = %X'80000'; literal SAL_SMS$M_REQ = %X'100000'; literal SAL_SMS$M_FIRST_ERR = %X'200000'; literal SAL_SMS$M_OVERFLOW = %X'400000'; literal SAL_SMS$S_SAL_SMS = 120; macro SAL_SMS$R_SAL_SHD = 0,0,0,0 %; literal SAL_SMS$S_SAL_SHD = 24; macro SAL_SMS$V_ERR_STS_VALID = 24,0,1,0 %; macro SAL_SMS$V_PHYS_ADDR_VALID = 24,1,1,0 %; macro SAL_SMS$V_PHYS_ADDR_MASK = 24,2,1,0 %; macro SAL_SMS$V_NODE_VALID = 24,3,1,0 %; macro SAL_SMS$V_CARD_VALID = 24,4,1,0 %; macro SAL_SMS$V_MOD_VALID = 24,5,1,0 %; macro SAL_SMS$V_BANK_VALID = 24,6,1,0 %; macro SAL_SMS$V_DEV_VALID = 24,7,1,0 %; macro SAL_SMS$V_ROW_VALID = 24,8,1,0 %; macro SAL_SMS$V_COL_VALID = 24,9,1,0 %; macro SAL_SMS$V_BIT_POS_VALID = 24,10,1,0 %; macro SAL_SMS$V_REQ_ID_VALID = 24,11,1,0 %; macro SAL_SMS$V_RESP_ID_VALID = 24,12,1,0 %; macro SAL_SMS$V_TARGET_VALID = 24,13,1,0 %; macro SAL_SMS$V_BUS_DATA_VALID = 24,14,1,0 %; macro SAL_SMS$V_OEM_ID_VALID = 24,15,1,0 %; macro SAL_SMS$V_OEM_DATA_VALID = 24,16,1,0 %; macro SAL_SMS$Q_ERR_STS = 32,0,0,0 %; literal SAL_SMS$S_ERR_STS = 8; macro SAL_SMS$B_ENCODED_ERR_TYPE = 33,0,8,0 %; macro SAL_SMS$V_ADDR = 32,16,1,0 %; macro SAL_SMS$V_CONTROL = 32,17,1,0 %; macro SAL_SMS$V_DATA = 32,18,1,0 %; macro SAL_SMS$V_RESP = 32,19,1,0 %; macro SAL_SMS$V_REQ = 32,20,1,0 %; macro SAL_SMS$V_FIRST_ERR = 32,21,1,0 %; macro SAL_SMS$V_OVERFLOW = 32,22,1,0 %; macro SAL_SMS$Q_PHYS_ADDR = 40,0,0,0 %; literal SAL_SMS$S_PHYS_ADDR = 8; macro SAL_SMS$Q_PHYS_ADDR_MASK = 48,0,0,0 %; literal SAL_SMS$S_PHYS_ADDR_MASK = 8; macro SAL_SMS$W_NODE = 56,0,16,0 %; macro SAL_SMS$W_CARD = 58,0,16,0 %; macro SAL_SMS$W_MOD = 60,0,16,0 %; macro SAL_SMS$W_BANK = 62,0,16,0 %; macro SAL_SMS$W_DEV = 64,0,16,0 %; macro SAL_SMS$W_ROW = 66,0,16,0 %; macro SAL_SMS$W_COL = 68,0,16,0 %; macro SAL_SMS$W_BIT_POS = 70,0,16,0 %; macro SAL_SMS$Q_REQ_ID = 72,0,0,0 %; literal SAL_SMS$S_REQ_ID = 8; macro SAL_SMS$Q_RESP_ID = 80,0,0,0 %; literal SAL_SMS$S_RESP_ID = 8; macro SAL_SMS$Q_TARGET_ID = 88,0,0,0 %; literal SAL_SMS$S_TARGET_ID = 8; macro SAL_SMS$Q_BUS_DATA = 96,0,0,0 %; literal SAL_SMS$S_BUS_DATA = 8; macro SAL_SMS$O_OEM_ID = 104,0,0,0 %; literal SAL_SMS$S_OEM_ID = 16; macro SAL_SMS$Q_OEM_ID_L = 104,0,0,0 %; literal SAL_SMS$S_OEM_ID_L = 8; macro SAL_SMS$Q_OEM_ID_H = 112,0,0,0 %; literal SAL_SMS$S_OEM_ID_H = 8; literal SAL_SMS$FRAME_SIZE = 120; ! ++ ! SAL Platform PCI Bus Error Info Section - Header Structure ! ! SAL 3.0 ! "Itanium Processor Family System Abstraction Layer Specification, November 2002" ! Section B.2.4.2, pp. B-8 - B-9 ! ! (SPCIBS - System PCI Bus Section) ! -- literal SAL_SPCIBS$M_ERR_STS_VALID = %X'1'; literal SAL_SPCIBS$M_ERR_TYPE_VALID = %X'2'; literal SAL_SPCIBS$M_ID_VALID = %X'4'; literal SAL_SPCIBS$M_ADDR_VALID = %X'8'; literal SAL_SPCIBS$M_DATA_VALID = %X'10'; literal SAL_SPCIBS$M_CMD_VALID = %X'20'; literal SAL_SPCIBS$M_REQ_ID_VALID = %X'40'; literal SAL_SPCIBS$M_COMPL_ID_VALID = %X'80'; literal SAL_SPCIBS$M_TARGET_ID_VALID = %X'100'; literal SAL_SPCIBS$M_OEM_ID_VALID = %X'200'; literal SAL_SPCIBS$M_OEM_DATA_VALID = %X'400'; literal SAL_SPCIBS$M_ADDR = %X'10000'; literal SAL_SPCIBS$M_CONTROL = %X'20000'; literal SAL_SPCIBS$M_DATA = %X'40000'; literal SAL_SPCIBS$M_RESP = %X'80000'; literal SAL_SPCIBS$M_REQ = %X'100000'; literal SAL_SPCIBS$M_FIRST_ERR = %X'200000'; literal SAL_SPCIBS$M_OVERFLOW = %X'400000'; literal SAL_SPCIBS$S_SAL_SPCIBS = 112; macro SAL_SPCIBS$R_SAL_SHD = 0,0,0,0 %; literal SAL_SPCIBS$S_SAL_SHD = 24; macro SAL_SPCIBS$Q_VALID = 24,0,0,0 %; literal SAL_SPCIBS$S_VALID = 8; macro SAL_SPCIBS$V_ERR_STS_VALID = 24,0,1,0 %; macro SAL_SPCIBS$V_ERR_TYPE_VALID = 24,1,1,0 %; macro SAL_SPCIBS$V_ID_VALID = 24,2,1,0 %; macro SAL_SPCIBS$V_ADDR_VALID = 24,3,1,0 %; macro SAL_SPCIBS$V_DATA_VALID = 24,4,1,0 %; macro SAL_SPCIBS$V_CMD_VALID = 24,5,1,0 %; macro SAL_SPCIBS$V_REQ_ID_VALID = 24,6,1,0 %; macro SAL_SPCIBS$V_COMPL_ID_VALID = 24,7,1,0 %; macro SAL_SPCIBS$V_TARGET_ID_VALID = 24,8,1,0 %; macro SAL_SPCIBS$V_OEM_ID_VALID = 24,9,1,0 %; macro SAL_SPCIBS$V_OEM_DATA_VALID = 24,10,1,0 %; macro SAL_SPCIBS$Q_ERR_STS = 32,0,0,0 %; literal SAL_SPCIBS$S_ERR_STS = 8; macro SAL_SPCIBS$B_ENCODED_ERR_TYPE = 33,0,8,0 %; macro SAL_SPCIBS$V_ADDR = 32,16,1,0 %; macro SAL_SPCIBS$V_CONTROL = 32,17,1,0 %; macro SAL_SPCIBS$V_DATA = 32,18,1,0 %; macro SAL_SPCIBS$V_RESP = 32,19,1,0 %; macro SAL_SPCIBS$V_REQ = 32,20,1,0 %; macro SAL_SPCIBS$V_FIRST_ERR = 32,21,1,0 %; macro SAL_SPCIBS$V_OVERFLOW = 32,22,1,0 %; macro SAL_SPCIBS$W_ERR_TYPE = 40,0,16,0 %; macro SAL_SPCIBS$W_ID = 42,0,16,0 %; macro SAL_SPCIBS$B_BUS_NUM = 42,0,8,0 %; macro SAL_SPCIBS$B_SEG_NUM = 43,0,8,0 %; macro SAL_SPCIBS$Q_ADDR = 48,0,0,0 %; literal SAL_SPCIBS$S_ADDR = 8; macro SAL_SPCIBS$Q_DATA = 56,0,0,0 %; literal SAL_SPCIBS$S_DATA = 8; macro SAL_SPCIBS$Q_CMD = 64,0,0,0 %; literal SAL_SPCIBS$S_CMD = 8; macro SAL_SPCIBS$Q_REQ_ID = 72,0,0,0 %; literal SAL_SPCIBS$S_REQ_ID = 8; macro SAL_SPCIBS$Q_COMPL_ID = 80,0,0,0 %; literal SAL_SPCIBS$S_COMPL_ID = 8; macro SAL_SPCIBS$Q_TARGET_ID = 88,0,0,0 %; literal SAL_SPCIBS$S_TARGET_ID = 8; macro SAL_SPCIBS$O_OEM_ID = 96,0,0,0 %; literal SAL_SPCIBS$S_OEM_ID = 16; macro SAL_SPCIBS$Q_OEM_ID_L = 96,0,0,0 %; literal SAL_SPCIBS$S_OEM_ID_L = 8; macro SAL_SPCIBS$Q_OEM_ID_H = 104,0,0,0 %; literal SAL_SPCIBS$S_OEM_ID_H = 8; literal SAL_SPCIBS$FRAME_SIZE = 112; ! ++ ! SAL Platform PCI Component Error Info Section - Header Structure ! ! SAL 3.0 ! "Itanium Processor Family System Abstraction Layer Specification, November 2002" ! Section B.2.4.3, pp. B-9 - B-10 ! ! (SPCICS - System PCI Component Section) ! -- literal SAL_SPCICS$M_ERR_STS_VALID = %X'1'; literal SAL_SPCICS$M_DATA_VALID = %X'2'; literal SAL_SPCICS$M_MEM_NUM_VALID = %X'4'; literal SAL_SPCICS$M_IO_NUM_VALID = %X'8'; literal SAL_SPCICS$M_REGS_DATA_PAIR_VALID = %X'10'; literal SAL_SPCICS$M_OEM_DATA_VALID = %X'20'; literal SAL_SPCICS$M_ADDR = %X'10000'; literal SAL_SPCICS$M_CONTROL = %X'20000'; literal SAL_SPCICS$M_DATA = %X'40000'; literal SAL_SPCICS$M_RESP = %X'80000'; literal SAL_SPCICS$M_REQ = %X'100000'; literal SAL_SPCICS$M_FIRST_ERR = %X'200000'; literal SAL_SPCICS$M_OVERFLOW = %X'400000'; literal SAL_SPCICS$S_SAL_SPCICS = 72; macro SAL_SPCICS$R_SAL_SHD = 0,0,0,0 %; literal SAL_SPCICS$S_SAL_SHD = 24; macro SAL_SPCICS$Q_VALID = 24,0,0,0 %; literal SAL_SPCICS$S_VALID = 8; macro SAL_SPCICS$V_ERR_STS_VALID = 24,0,1,0 %; macro SAL_SPCICS$V_DATA_VALID = 24,1,1,0 %; macro SAL_SPCICS$V_MEM_NUM_VALID = 24,2,1,0 %; macro SAL_SPCICS$V_IO_NUM_VALID = 24,3,1,0 %; macro SAL_SPCICS$V_REGS_DATA_PAIR_VALID = 24,4,1,0 %; macro SAL_SPCICS$V_OEM_DATA_VALID = 24,5,1,0 %; macro SAL_SPCICS$Q_ERR_STS = 32,0,0,0 %; literal SAL_SPCICS$S_ERR_STS = 8; macro SAL_SPCICS$B_ENCODED_ERR_TYPE = 33,0,8,0 %; macro SAL_SPCICS$V_ADDR = 32,16,1,0 %; macro SAL_SPCICS$V_CONTROL = 32,17,1,0 %; macro SAL_SPCICS$V_DATA = 32,18,1,0 %; macro SAL_SPCICS$V_RESP = 32,19,1,0 %; macro SAL_SPCICS$V_REQ = 32,20,1,0 %; macro SAL_SPCICS$V_FIRST_ERR = 32,21,1,0 %; macro SAL_SPCICS$V_OVERFLOW = 32,22,1,0 %; macro SAL_SPCICS$O_PCI_COMP = 40,0,0,0 %; literal SAL_SPCICS$S_PCI_COMP = 16; macro SAL_SPCICS$W_VENDOR_ID = 40,0,16,0 %; macro SAL_SPCICS$W_DEV_ID = 42,0,16,0 %; macro SAL_SPCICS$W_CLASS_CODE = 44,0,0,0 %; literal SAL_SPCICS$S_CLASS_CODE = 6; macro SAL_SPCICS$B_FUNC_NUM = 50,0,8,0 %; macro SAL_SPCICS$B_DEV_NUM = 51,0,8,0 %; macro SAL_SPCICS$B_BUS_NUM = 52,0,8,0 %; macro SAL_SPCICS$B_SEG_NUM = 53,0,8,0 %; macro SAL_SPCICS$L_MEM_NUM = 59,0,32,0 %; macro SAL_SPCICS$L_IO_NUM = 63,0,32,0 %; literal SAL_SPCICS$FRAME_SIZE = 72; ! ++ ! SAL Platform SEL Device Error Info Section ! ! SAL 3.0 ! "Itanium Processor Family System Abstraction Layer Specification, November 2002" ! Section B.2.4.4, pp. B-10 - B-11 ! ! (SSELS - System SEL Section) ! -- literal SAL_SSELS$M_REC_ID_VALID = %X'1'; literal SAL_SSELS$M_REC_TYPE_VALID = %X'2'; literal SAL_SSELS$M_TIMESTAMP_VALID = %X'4'; literal SAL_SSELS$M_GEN_TYPE_VALID = %X'8'; literal SAL_SSELS$M_EVM_REV_VALID = %X'10'; literal SAL_SSELS$M_SENS_TYPE_VALID = %X'20'; literal SAL_SSELS$M_SENS_NUM_VALID = %X'40'; literal SAL_SSELS$M_EVENT_DIR_TYPE_VALID = %X'80'; literal SAL_SSELS$M_EVENT_DATA1_VALID = %X'100'; literal SAL_SSELS$M_EVENT_DATA2_VALID = %X'200'; literal SAL_SSELS$M_EVENT_DATA3_VALID = %X'400'; literal SAL_SSELS$M_SYS_SW_ID_VALID = %X'1'; literal SAL_SSELS$M_DEASSERTION = %X'80'; literal SAL_SSELS$S_SAL_SSELS = 48; macro SAL_SSELS$R_SAL_SHD = 0,0,0,0 %; literal SAL_SSELS$S_SAL_SHD = 24; macro SAL_SSELS$Q_VALID = 24,0,0,0 %; literal SAL_SSELS$S_VALID = 8; macro SAL_SSELS$V_REC_ID_VALID = 24,0,1,0 %; macro SAL_SSELS$V_REC_TYPE_VALID = 24,1,1,0 %; macro SAL_SSELS$V_TIMESTAMP_VALID = 24,2,1,0 %; macro SAL_SSELS$V_GEN_TYPE_VALID = 24,3,1,0 %; macro SAL_SSELS$V_EVM_REV_VALID = 24,4,1,0 %; macro SAL_SSELS$V_SENS_TYPE_VALID = 24,5,1,0 %; macro SAL_SSELS$V_SENS_NUM_VALID = 24,6,1,0 %; macro SAL_SSELS$V_EVENT_DIR_TYPE_VALID = 24,7,1,0 %; macro SAL_SSELS$V_EVENT_DATA1_VALID = 24,8,1,0 %; macro SAL_SSELS$V_EVENT_DATA2_VALID = 24,9,1,0 %; macro SAL_SSELS$V_EVENT_DATA3_VALID = 24,10,1,0 %; macro SAL_SSELS$W_REC_ID = 32,0,16,0 %; macro SAL_SSELS$B_REC_TYPE = 34,0,8,0 %; macro SAL_SSELS$L_TIMESTAMP = 35,0,32,0 %; macro SAL_SSELS$W_GEN_ID = 39,0,16,0 %; macro SAL_SSELS$B_GEN_ID_L = 39,0,8,0 %; macro SAL_SSELS$V_SYS_SW_ID_VALID = 39,0,1,0 %; macro SAL_SSELS$V_SYS_SW_ID = 39,1,7,0 %; literal SAL_SSELS$S_SYS_SW_ID = 7; macro SAL_SSELS$B_GEN_ID_H = 40,0,8,0 %; macro SAL_SSELS$V_IPMB_DEV_LUN = 40,0,2,0 %; literal SAL_SSELS$S_IPMB_DEV_LUN = 2; macro SAL_SSELS$B_EVM_REV = 41,0,8,0 %; macro SAL_SSELS$B_SENS_TYPE = 42,0,8,0 %; macro SAL_SSELS$B_SENS_NUM = 43,0,8,0 %; macro SAL_SSELS$B_EVENT_DIR_TYPE = 44,0,8,0 %; macro SAL_SSELS$V_EVENT_TYPE_CODE = 44,0,7,0 %; literal SAL_SSELS$S_EVENT_TYPE_CODE = 7; macro SAL_SSELS$V_DEASSERTION = 44,7,1,0 %; macro SAL_SSELS$B_EVENT_DATA1 = 45,0,8,0 %; macro SAL_SSELS$B_EVENT_DATA2 = 46,0,8,0 %; macro SAL_SSELS$B_EVENT_DATA3 = 47,0,8,0 %; literal SAL_SSELS$FRAME_SIZE = 48; ! ++ ! SAL SMBIOS Device Error Info Section - Header Structure ! ! SAL 3.0 ! "Itanium Processor Family System Abstraction Layer Specification, November 2002" ! Section B.2.4.5, pp. B-11 ! ! (SSMBIOSS - System SMBIOS Section) ! -- literal SAL_SSMBIOSS$M_EVENT_TYPE_VALID = %X'1'; literal SAL_SSMBIOSS$M_LEN_VALID = %X'2'; literal SAL_SSMBIOSS$M_TIMESTAMP_VALID = %X'4'; literal SAL_SSMBIOSS$M_DATA_VALID = %X'8'; literal SAL_SSMBIOSS$S_SAL_SSMBIOSS = 40; macro SAL_SSMBIOSS$R_SAL_SHD = 0,0,0,0 %; literal SAL_SSMBIOSS$S_SAL_SHD = 24; macro SAL_SSMBIOSS$Q_VALID = 24,0,0,0 %; literal SAL_SSMBIOSS$S_VALID = 8; macro SAL_SSMBIOSS$V_EVENT_TYPE_VALID = 24,0,1,0 %; macro SAL_SSMBIOSS$V_LEN_VALID = 24,1,1,0 %; macro SAL_SSMBIOSS$V_TIMESTAMP_VALID = 24,2,1,0 %; macro SAL_SSMBIOSS$V_DATA_VALID = 24,3,1,0 %; macro SAL_SSMBIOSS$B_EVENT_TYPE = 32,0,8,0 %; macro SAL_SSMBIOSS$B_LEN = 33,0,8,0 %; macro SAL_SSMBIOSS$B_TIMESTAMP = 34,0,0,0 %; literal SAL_SSMBIOSS$S_TIMESTAMP = 6; literal SAL_SSMBIOSS$FRAME_SIZE = 40; ! ++ ! SAL Specific Error Info Section - Header Structure ! ! SAL 3.0 ! "Itanium Processor Family System Abstraction Layer Specification, November 2002" ! Section B.2.4.6, pp. B-11 - B-12 ! ! (SOEMS - System OEM Section) ! -- literal SAL_SOEMS$M_ERR_STS_VALID = %X'1'; literal SAL_SOEMS$M_REQ_ID_VALID = %X'2'; literal SAL_SOEMS$M_RESP_ID_VALID = %X'4'; literal SAL_SOEMS$M_TARGET_ID_VALID = %X'8'; literal SAL_SOEMS$M_SYS_SPEC_DATA_VALID = %X'10'; literal SAL_SOEMS$M_OEM_ID_VALID = %X'20'; literal SAL_SOEMS$M_OEM_DATA_VALID = %X'40'; literal SAL_SOEMS$M_OEM_DEV_PATH_VALID = %X'80'; literal SAL_SOEMS$M_ADDR = %X'10000'; literal SAL_SOEMS$M_CONTROL = %X'20000'; literal SAL_SOEMS$M_DATA = %X'40000'; literal SAL_SOEMS$M_RESP = %X'80000'; literal SAL_SOEMS$M_REQ = %X'100000'; literal SAL_SOEMS$M_FIRST_ERR = %X'200000'; literal SAL_SOEMS$M_OVERFLOW = %X'400000'; literal SAL_SOEMS$S_SAL_SOEMS = 88; macro SAL_SOEMS$R_SAL_SHD = 0,0,0,0 %; literal SAL_SOEMS$S_SAL_SHD = 24; macro SAL_SOEMS$Q_VALID = 24,0,0,0 %; literal SAL_SOEMS$S_VALID = 8; macro SAL_SOEMS$V_ERR_STS_VALID = 24,0,1,0 %; macro SAL_SOEMS$V_REQ_ID_VALID = 24,1,1,0 %; macro SAL_SOEMS$V_RESP_ID_VALID = 24,2,1,0 %; macro SAL_SOEMS$V_TARGET_ID_VALID = 24,3,1,0 %; macro SAL_SOEMS$V_SYS_SPEC_DATA_VALID = 24,4,1,0 %; macro SAL_SOEMS$V_OEM_ID_VALID = 24,5,1,0 %; macro SAL_SOEMS$V_OEM_DATA_VALID = 24,6,1,0 %; macro SAL_SOEMS$V_OEM_DEV_PATH_VALID = 24,7,1,0 %; macro SAL_SOEMS$Q_ERR_STS = 32,0,0,0 %; literal SAL_SOEMS$S_ERR_STS = 8; macro SAL_SOEMS$B_ENCODED_ERR_TYPE = 33,0,8,0 %; macro SAL_SOEMS$V_ADDR = 32,16,1,0 %; macro SAL_SOEMS$V_CONTROL = 32,17,1,0 %; macro SAL_SOEMS$V_DATA = 32,18,1,0 %; macro SAL_SOEMS$V_RESP = 32,19,1,0 %; macro SAL_SOEMS$V_REQ = 32,20,1,0 %; macro SAL_SOEMS$V_FIRST_ERR = 32,21,1,0 %; macro SAL_SOEMS$V_OVERFLOW = 32,22,1,0 %; macro SAL_SOEMS$Q_REQ_ID = 40,0,0,0 %; literal SAL_SOEMS$S_REQ_ID = 8; macro SAL_SOEMS$Q_RESP_ID = 48,0,0,0 %; literal SAL_SOEMS$S_RESP_ID = 8; macro SAL_SOEMS$Q_TARGET_ID = 56,0,0,0 %; literal SAL_SOEMS$S_TARGET_ID = 8; macro SAL_SOEMS$Q_BUS_SPEC_DATA = 64,0,0,0 %; literal SAL_SOEMS$S_BUS_SPEC_DATA = 8; macro SAL_SOEMS$O_OEM_COMP_ID = 72,0,0,0 %; literal SAL_SOEMS$S_OEM_COMP_ID = 16; macro SAL_SOEMS$Q_OEM_COMP_ID_L = 72,0,0,0 %; literal SAL_SOEMS$S_OEM_COMP_ID_L = 8; macro SAL_SOEMS$Q_OEM_COMP_ID_H = 80,0,0,0 %; literal SAL_SOEMS$S_OEM_COMP_ID_H = 8; literal SAL_SOEMS$FRAME_SIZE = 88; ! ++ ! CER_STAT Field ! -- literal CER_STAT$M_PCER = %X'8'; literal CER_STAT$M_SCER = %X'10'; literal CER_STAT$M_PCEL = %X'100'; literal CER_STAT$M_SCEL = %X'1'; literal CER_STAT$S_CER_STAT = 8; macro CER_STAT$L_CPU_STAT = 0,0,32,0 %; macro CER_STAT$V_PCER = 0,3,1,0 %; ! [3] macro CER_STAT$V_SCER = 0,4,1,0 %; ! [4] macro CER_STAT$V_PCEL = 0,8,1,0 %; ! [8] macro CER_STAT$L_SYS_STAT = 4,0,32,0 %; macro CER_STAT$V_SCEL = 4,0,1,0 %; ! [32] literal CER_STAT$K_LENGTH = 8; ! ++ ! Correctable Error Reporting Subpacket ! -- literal CER$S_CER = 24; macro CER$W_LENGTH = 0,0,16,0 %; macro CER$W_CLASS = 2,0,16,0 %; macro CER$W_TYPE = 4,0,16,0 %; macro CER$W_REV = 6,0,16,0 %; macro CER$Q_CPU_WHAMI = 8,0,0,0 %; literal CER$S_CPU_WHAMI = 8; ! Logical CPU number of reporting processor. macro CER$R_CER_STAT = 16,0,0,0 %; literal CER$S_CER_STAT = 8; ! Correctable error reporting status. literal CER$K_LENGTH = 24; literal CER$K_CLASS = 9; literal CER$K_TYPE = 1; literal CER$K_REV = 2; ! ++ ! Entry Terminator Subpacket ! -- literal ENTRY_TERM$S_ENTRY_TERM = 8; macro ENTRY_TERM$W_LENGTH = 0,0,16,0 %; macro ENTRY_TERM$W_CLASS = 2,0,16,0 %; macro ENTRY_TERM$W_TYPE = 4,0,16,0 %; macro ENTRY_TERM$W_REV = 6,0,16,0 %; literal ENTRY_TERM$K_LENGTH = 8; literal ENTRY_TERM$K_CLASS = 0; literal ENTRY_TERM$K_TYPE = 0; literal ENTRY_TERM$K_REV = 1; ! ++ ! IA64-specific CRD_CONTROL bits. ! ! Overlay of exe$gl_crd_control.crd_control$w_sys_specific ! which is the upper word of exe$gl_crd_control. ! -- literal CRD_CONTROL_IA64$M_POLLING_TIME = %X'7'; literal CRD_CONTROL_IA64$M_DISABLE_POLLING = %X'8'; literal CRD_CONTROL_IA64$S_CRD_CONTROL_IA64 = 2; macro CRD_CONTROL_IA64$V_POLLING_TIME = 0,0,3,0 %; literal CRD_CONTROL_IA64$S_POLLING_TIME = 3; ! Used for tuning the polling time for corrected errors macro CRD_CONTROL_IA64$V_DISABLE_POLLING = 0,3,1,0 %; ! Disable polling for corrected errors macro CRD_CONTROL_IA64$B_DEBUG = 1,0,8,0 %; ! Reserved for debug use. literal CRD_CONTROL_IA64$K_LENGTH = 2; !*** MODULE $IA64_PALDEF *** ! ++ ! PAL Procedure return structure ! -- literal PAL_RET$S_PAL_RET = 32; macro PAL_RET$Q_VAL0 = 0,0,0,0 %; literal PAL_RET$S_VAL0 = 8; macro PAL_RET$Q_VAL1 = 8,0,0,0 %; literal PAL_RET$S_VAL1 = 8; macro PAL_RET$Q_VAL2 = 16,0,0,0 %; literal PAL_RET$S_VAL2 = 8; macro PAL_RET$Q_VAL3 = 24,0,0,0 %; literal PAL_RET$S_VAL3 = 8; ! ++ ! PAL calls ! -- literal IA64_PAL$K_CACHE_FLUSH = 1; literal IA64_PAL$K_CACHE_INFO = 2; literal IA64_PAL$K_CACHE_INIT = 3; literal IA64_PAL$K_CACHE_SUMMARY = 4; literal IA64_PAL$K_MEM_ATTRIB = 5; literal IA64_PAL$K_PTCE_INFO = 6; literal IA64_PAL$K_VM_INFO = 7; literal IA64_PAL$K_VM_SUMMARY = 8; literal IA64_PAL$K_BUS_GET_FEATURES = 9; literal IA64_PAL$K_BUS_SET_FEATURES = 10; literal IA64_PAL$K_DEBUG_INFO = 11; literal IA64_PAL$K_FIXED_ADDR = 12; literal IA64_PAL$K_FREQ_BASE = 13; literal IA64_PAL$K_FREQ_RATIOS = 14; literal IA64_PAL$K_PERF_MON_INFO = 15; literal IA64_PAL$K_PLATFORM_ADDR = 16; literal IA64_PAL$K_PROC_GET_FEATURES = 17; literal IA64_PAL$K_PROC_SET_FEATURES = 18; literal IA64_PAL$K_RSE_INFO = 19; literal IA64_PAL$K_VERSION = 20; literal IA64_PAL$K_MC_CLEAR_LOG = 21; literal IA64_PAL$K_MC_DRAIN = 22; literal IA64_PAL$K_MC_EXPECTED = 23; literal IA64_PAL$K_MC_DYNAMIC_STATE = 24; literal IA64_PAL$K_MC_ERROR_INFO = 25; literal IA64_PAL$K_MC_RESUME = 26; literal IA64_PAL$K_MC_REGISTER_MEM = 27; literal IA64_PAL$K_HALT = 28; literal IA64_PAL$K_HALT_LIGHT = 29; literal IA64_PAL$K_COPY_INFO = 30; literal IA64_PAL$K_CACHE_LINE_INIT = 31; literal IA64_PAL$K_PMI_ENTRYPOINT = 32; literal IA64_PAL$K_ENTER_IA_32_ENV = 33; literal IA64_PAL$K_VM_PAGE_SIZE = 34; literal IA64_PAL$K_MEM_FOR_TEST = 37; literal IA64_PAL$K_CACHE_PROT_INFO = 38; literal IA64_PAL$K_REGISTER_INFO = 39; literal IA64_PAL$K_SHUTDOWN = 40; literal IA64_PAL$K_PREFETCH_VISIBILITY = 41; literal IA64_PAL$K_LOGICAL_TO_PHYSICAL = 42; literal IA64_PAL$K_CACHE_SHARED_INFO = 43; literal IA64_PAL$K_PSTATE_INFO = 44; literal IA64_PAL$K_MC_ERROR_INJECT = 47; ! ++ ! 256-511 reserved for architecture defined ! stack register calls ! -- literal IA64_PAL$K_COPY_PAL = 256; literal IA64_PAL$K_HALT_INFO = 257; literal IA64_PAL$K_TEST_PROC = 258; literal IA64_PAL$K_CACHE_READ = 259; literal IA64_PAL$K_CACHE_WRITE = 260; literal IA64_PAL$K_VM_TR_READ = 261; literal IA64_PAL$K_GET_PSTATE = 262; literal IA64_PAL$K_SET_PSTATE = 263; literal IA64_PAL$K_BRAND_INFO = 274; literal IA64_PAL$K_CAR_INIT = 520; literal IA64_PAL$K_AUTH = 521; literal IA64_PAL$K_HALT_LIGHT_SPECIAL = 522; literal IA64_PAL$K_CHECK_UNLOGGED_CMCI = 523; literal IA64_PAL$K_POWER_INFO = 524; literal IA64_PAL$K_SET_MAX_POWER = 527; literal IA64_PAL$K_THREAD_CONTROL = 528; literal IA64_PAL$K_CACHE_DISABLED_INFO = 529; literal IA64_PAL$K_DEFEATURE_L3 = 530; literal IA64_PAL$K_SET_TIMEOUT = 531; literal IA64_PAL$K_CONTEXT_SAVE = 544; literal IA64_PAL$K_CONTEXT_RESTORE = 545; literal IA64_PAL$K_FORCE_UC_ACCESS = 768; ! ++ ! Generic return status used by PAL calls ! -- literal IA64_PAL$K_SUCCESS = 0; literal IA64_PAL$C_SUCCESS = 0; literal IA64_PAL$K_UNIMPL = -1; literal IA64_PAL$K_INVAL_ARG = -2; literal IA64_PAL$K_FAIL = -3; literal IA64_PAL$K_SIDE_EFFECT = -4; literal IA64_PAL$K_INFO_NOT_AVAIL = -6; ! ++ ! Definitions used by PAL_BUS_GET_FEATURES/PAL_BUS_SET_FEATURES ! -- ! definition of return structure literal PAL_BUS$M_BCFG_REQ_PARK = %X'20000000'; literal PAL_BUS$M_BCFG_LOCK = %X'40000000'; literal PAL_BUS$M_ENA_HALF_XFER = %X'80000000'; literal PAL_BUS$M_BCFG_DIS_XACT_QUE = %X'80000000000000'; literal PAL_BUS$M_BCFG_DIS_RSPERR_CHK = %X'100000000000000'; literal PAL_BUS$M_BCFG_DIS_BERR_CHK = %X'200000000000000'; literal PAL_BUS$M_BCFG_DIS_IREQ_SIG = %X'400000000000000'; literal PAL_BUS$M_BCFG_DIS_REQ_SIG = %X'800000000000000'; literal PAL_BUS$M_BCFG_DIS_INIT = %X'1000000000000000'; literal PAL_BUS$M_BCFG_DIS_INIT_SIG = %X'2000000000000000'; literal PAL_BUS$M_BCFG_DIS_AERR = %X'4000000000000000'; literal PAL_BUS$M_BCFG_DIS_AERR_SIG = %X'8000000000000000'; literal PAL_BUS$M_BCFG_DIS_DERR = %X'0'; literal PAL_BUS$S_PAL_BUS = 40; macro PAL_BUS$Q_STATUS = 0,0,0,0 %; literal PAL_BUS$S_STATUS = 8; macro PAL_BUS$Q_FEATURES_AVAIL = 8,0,0,0 %; literal PAL_BUS$S_FEATURES_AVAIL = 8; macro PAL_BUS$Q_FEATURES_STATUS = 16,0,0,0 %; literal PAL_BUS$S_FEATURES_STATUS = 8; macro PAL_BUS$Q_FEATURES_CONTROL = 24,0,0,0 %; literal PAL_BUS$S_FEATURES_CONTROL = 8; macro PAL_BUS$V_BCFG_REQ_PARK = 24,29,1,0 %; ! (1UL << 29) macro PAL_BUS$V_BCFG_LOCK = 24,30,1,0 %; ! (1UL << 30) macro PAL_BUS$V_ENA_HALF_XFER = 24,31,1,0 %; ! (1UL << 31) macro PAL_BUS$V_BCFG_DIS_XACT_QUE = 28,23,1,0 %; ! (1UL << 54) macro PAL_BUS$V_BCFG_DIS_RSPERR_CHK = 28,24,1,0 %; ! (1UL << 55) macro PAL_BUS$V_BCFG_DIS_BERR_CHK = 28,25,1,0 %; ! (1UL << 56) macro PAL_BUS$V_BCFG_DIS_IREQ_SIG = 28,26,1,0 %; ! (1UL << 57) macro PAL_BUS$V_BCFG_DIS_REQ_SIG = 28,27,1,0 %; ! (1UL << 58) macro PAL_BUS$V_BCFG_DIS_INIT = 28,28,1,0 %; ! (1UL << 59) macro PAL_BUS$V_BCFG_DIS_INIT_SIG = 28,29,1,0 %; ! (1UL << 60) macro PAL_BUS$V_BCFG_DIS_AERR = 28,30,1,0 %; ! (1UL << 61) macro PAL_BUS$V_BCFG_DIS_AERR_SIG = 28,31,1,0 %; ! (1UL << 62) macro PAL_BUS$V_BCFG_DIS_DERR = 32,0,1,0 %; ! (1UL << 63) ! ++ ! Definitions used by PAL_CACHE_FLUSH ! -- literal IA64_PAL$K_CACHE_ISTREAM = 1; literal IA64_PAL$K_CACHE_DSTREAM = 2; literal IA64_PAL$K_CACHE_BOTH = 3; literal IA64_PAL$K_CACHE_VALIDATE = 0; literal IA64_PAL$K_CACHE_INVALIDATE = 1; literal IA64_PAL$K_CACHE_POLL_INT = 2; literal IA64_PAL$K_CACHE_PLAT_ACK = 4; literal PAL_CFLUSH$S_PAL_CFLUSH = 32; macro PAL_CFLUSH$Q_STATUS = 0,0,0,0 %; literal PAL_CFLUSH$S_STATUS = 8; macro PAL_CFLUSH$Q_VECTOR = 8,0,0,0 %; literal PAL_CFLUSH$S_VECTOR = 8; macro PAL_CFLUSH$Q_PROGRESS = 16,0,0,0 %; literal PAL_CFLUSH$S_PROGRESS = 8; macro PAL_CFLUSH$q_spare = 24,0,0,0 %; literal PAL_CFLUSH$s_spare = 8; ! ++ ! Definitions used by PAL_CACHE_INFO ! -- literal PAL_CINFO$M_CINFO1_UNIFIED = %X'1'; literal PAL_CINFO$M_CINFO1_ATTRIB = %X'6'; literal PAL_CINFO$M_CINFO1_ASSOC = %X'FF00'; literal PAL_CINFO$M_CINFO1_LSIZE = %X'FF0000'; literal PAL_CINFO$M_CINFO1_STRIDE = %X'FF000000'; literal PAL_CINFO$M_CINFO1_STLAT = %X'FF00000000'; literal PAL_CINFO$M_CINFO1_LDLAT = %X'FF0000000000'; literal PAL_CINFO$M_CINFO1_STHINT = %X'FF000000000000'; literal PAL_CINFO$M_CINFO1_LDHINT = %X'FF00000000000000'; literal PAL_CINFO$M_CINFO2_ALIASB = %X'FF00000000'; literal PAL_CINFO$M_CINFO2_TAGLS = %X'FF0000000000'; literal PAL_CINFO$M_CINFO2_TAGMS = %X'FF000000000000'; literal PAL_CINFO$m_filler_2 = %X'FF00000000000000'; literal PAL_CINFO$S_PAL_CINFO = 32; macro PAL_CINFO$Q_STATUS = 0,0,0,0 %; literal PAL_CINFO$S_STATUS = 8; macro PAL_CINFO$Q_CONFIG_INFO1 = 8,0,0,0 %; literal PAL_CINFO$S_CONFIG_INFO1 = 8; macro PAL_CINFO$V_CINFO1_UNIFIED = 8,0,1,0 %; ! (0x1UL << 0) 0 macro PAL_CINFO$V_CINFO1_ATTRIB = 8,1,2,0 %; literal PAL_CINFO$S_CINFO1_ATTRIB = 2; ! (0x3UL << 1) 1-2 macro PAL_CINFO$V_CINFO1_ASSOC = 8,8,8,0 %; literal PAL_CINFO$S_CINFO1_ASSOC = 8; ! (0xffUL << 8) 8-15 macro PAL_CINFO$V_CINFO1_LSIZE = 8,16,8,0 %; literal PAL_CINFO$S_CINFO1_LSIZE = 8; ! (0xffUL << 16) 16-23 macro PAL_CINFO$V_CINFO1_STRIDE = 8,24,8,0 %; literal PAL_CINFO$S_CINFO1_STRIDE = 8; ! (0xffUL << 24) 24-31 macro PAL_CINFO$V_CINFO1_STLAT = 12,0,8,0 %; literal PAL_CINFO$S_CINFO1_STLAT = 8; ! (0xffUL << 32) 32-39 macro PAL_CINFO$V_CINFO1_LDLAT = 12,8,8,0 %; literal PAL_CINFO$S_CINFO1_LDLAT = 8; ! (0xffUL << 40) 40-47 macro PAL_CINFO$V_CINFO1_STHINT = 12,16,8,0 %; literal PAL_CINFO$S_CINFO1_STHINT = 8; ! (0xffUL << 48) 48-55 macro PAL_CINFO$V_CINFO1_LDHINT = 12,24,8,0 %; literal PAL_CINFO$S_CINFO1_LDHINT = 8; ! (0xffUL << 56) 56-63 macro PAL_CINFO$Q_CONFIG_INFO2 = 16,0,0,0 %; literal PAL_CINFO$S_CONFIG_INFO2 = 8; macro PAL_CINFO$L_CINFO2_CSIZE = 16,0,32,0 %; macro PAL_CINFO$V_CINFO2_ALIASB = 20,0,8,0 %; literal PAL_CINFO$S_CINFO2_ALIASB = 8; ! (0xff << 32) 32-39 macro PAL_CINFO$V_CINFO2_TAGLS = 20,8,8,0 %; literal PAL_CINFO$S_CINFO2_TAGLS = 8; ! (0xff << 40) 40-47 macro PAL_CINFO$V_CINFO2_TAGMS = 20,16,8,0 %; literal PAL_CINFO$S_CINFO2_TAGMS = 8; ! (0xff << 48) 48-55 macro PAL_CINFO$v_filler_2 = 20,24,8,0 %; literal PAL_CINFO$s_filler_2 = 8; ! 56-63 macro PAL_CINFO$q_spare = 24,0,0,0 %; literal PAL_CINFO$s_spare = 8; ! ++ ! Config 1 information returned ! -- literal IA64_PAL$K_CACHE_WRITETHRU = 0; literal IA64_PAL$K_CACHE_WRITEBACK = 1; literal IA64_PAL$K_CACHE_EITHER = 2; literal IA64_PAL$K_CACHE_TYPE_INST = 1; literal IA64_PAL$K_CACHE_TYPE_DATA = 2; ! ++ ! Config 2 information returned ! -- ! ++ ! Definitions used by PAL_CACHE_INIT ! -- literal IA64_PAL$K_CACHE_INIT_ALL = -1; literal IA64_PAL$K_CACHE_NO_RESTRICT = 0; literal IA64_PAL$K_CACHE_RESTRICT = 1; ! ++ ! Definitions used by PAL_CACHE_PROT_INFO ! -- literal PAL_CPINFO$S_PAL_CPINFO = 32; macro PAL_CPINFO$Q_STATUS = 0,0,0,0 %; literal PAL_CPINFO$S_STATUS = 8; macro PAL_CPINFO$L_CONFIG_INFO1 = 8,0,0,0 %; literal PAL_CPINFO$S_CONFIG_INFO1 = 8; macro PAL_CPINFO$L_CONFIG_INFO2 = 16,0,0,0 %; literal PAL_CPINFO$S_CONFIG_INFO2 = 8; macro PAL_CPINFO$L_CONFIG_INFO3 = 24,0,0,0 %; literal PAL_CPINFO$S_CONFIG_INFO3 = 8; ! bitmask for config literal IA64_PAL$M_CPINFO_DATA_BITS = 255; literal IA64_PAL$M_CPINFO_TPROT_LSB = 768; literal IA64_PAL$M_CPINFO_TPROT_MSB = 1032192; literal IA64_PAL$M_CPINFO_TPROT_BITS = 66060288; literal IA64_PAL$M_CPINFO_METHOD = 1006632960; literal IA64_PAL$M_CPINFO_TAG_DATA = -1073741824; ! bitmask for config literal IA64_PAL$V_CPINFO_DATA_BITS = 0; literal IA64_PAL$V_CPINFO_TPROT_LSB = 8; literal IA64_PAL$V_CPINFO_TPROT_MSB = 14; literal IA64_PAL$V_CPINFO_TPROT_BITS = 20; literal IA64_PAL$V_CPINFO_METHOD = 26; literal IA64_PAL$V_CPINFO_TAG_DATA = 30; ! values literal IA64_PAL$K_CACHE_PROT_DATA = 0; literal IA64_PAL$K_CACHE_PROT_TAG = 1; literal IA64_PAL$K_CACHE_PROT_TAG_DATA = 2; literal IA64_PAL$K_CACHE_PROT_DATA_TAG = 3; literal IA64_PAL$K_CACHE_PROT_NONE = 0; literal IA64_PAL$K_CACHE_PROT_ODDPAR = 1; literal IA64_PAL$K_CACHE_PROT_EVENPAR = 2; literal IA64_PAL$K_CACHE_PROT_ECC = 3; ! ++ ! Definitions used by PAL_CACHE_SUMMARY ! -- ! return structure literal PAL_CSUMM$S_PAL_CSUMM = 32; macro PAL_CSUMM$Q_STATUS = 0,0,0,0 %; literal PAL_CSUMM$S_STATUS = 8; macro PAL_CSUMM$Q_CACHE_LEVELS = 8,0,0,0 %; literal PAL_CSUMM$S_CACHE_LEVELS = 8; macro PAL_CSUMM$Q_UNIQUE_CACHES = 16,0,0,0 %; literal PAL_CSUMM$S_UNIQUE_CACHES = 8; macro PAL_CSUMM$q_spare = 24,0,0,0 %; literal PAL_CSUMM$s_spare = 8; ! ++ ! Definitions used by PAL_COPY_INFO ! -- ! return structure literal PAL_COPY_INFO$S_PAL_COPY_INFO = 32; macro PAL_COPY_INFO$Q_STATUS = 0,0,0,0 %; literal PAL_COPY_INFO$S_STATUS = 8; macro PAL_COPY_INFO$Q_BUFFER_SIZE = 8,0,0,0 %; literal PAL_COPY_INFO$S_BUFFER_SIZE = 8; macro PAL_COPY_INFO$Q_BUFFER_ALIGN = 16,0,0,0 %; literal PAL_COPY_INFO$S_BUFFER_ALIGN = 8; macro PAL_COPY_INFO$q_spare = 24,0,0,0 %; literal PAL_COPY_INFO$s_spare = 8; ! ++ ! Definitions used by PAL_COPY_PAL ! -- ! return structure literal PAL_COPY_PAL$S_PAL_COPY_PAL = 32; macro PAL_COPY_PAL$Q_STATUS = 0,0,0,0 %; literal PAL_COPY_PAL$S_STATUS = 8; macro PAL_COPY_PAL$Q_PROC_OFFSET = 8,0,0,0 %; literal PAL_COPY_PAL$S_PROC_OFFSET = 8; macro PAL_COPY_PAL$q_spare1 = 16,0,0,0 %; literal PAL_COPY_PAL$s_spare1 = 8; macro PAL_COPY_PAL$q_spare2 = 24,0,0,0 %; literal PAL_COPY_PAL$s_spare2 = 8; ! ++ ! Definitions used by PAL_DEBUG_INFO ! -- ! return structure literal PAL_DEBUG_INFO$S_PAL_DEBUG_INFO = 32; macro PAL_DEBUG_INFO$Q_STATUS = 0,0,0,0 %; literal PAL_DEBUG_INFO$S_STATUS = 8; macro PAL_DEBUG_INFO$Q_IREGS = 8,0,0,0 %; literal PAL_DEBUG_INFO$S_IREGS = 8; macro PAL_DEBUG_INFO$Q_DREGS = 16,0,0,0 %; literal PAL_DEBUG_INFO$S_DREGS = 8; macro PAL_DEBUG_INFO$q_spare = 24,0,0,0 %; literal PAL_DEBUG_INFO$s_spare = 8; ! ++ ! Definitions used by PAL_PSTATE_INFO ! -- ! return structure. PAL_PSTATE_INFO wants an array of 8 of these (i.e. 256 bytes), with the number ! of valid entries = the number of pstates = the second integer return value literal PAL_PSTATE_INFO$M_PERF_INDEX = %X'7F'; literal PAL_PSTATE_INFO$M_TYPICAL_POWER = %X'FFFFFFFFFFFFF000'; literal PAL_PSTATE_INFO$S_PAL_PSTATE_INFO = 32; macro PAL_PSTATE_INFO$Q_QUAD1 = 0,0,0,0 %; literal PAL_PSTATE_INFO$S_QUAD1 = 8; macro PAL_PSTATE_INFO$V_PERF_INDEX = 0,0,7,0 %; literal PAL_PSTATE_INFO$S_PERF_INDEX = 7; macro PAL_PSTATE_INFO$V_TYPICAL_POWER = 0,12,52,0 %; literal PAL_PSTATE_INFO$S_TYPICAL_POWER = 52; macro PAL_PSTATE_INFO$Q_TRANS_LATENCY_1 = 8,0,0,0 %; literal PAL_PSTATE_INFO$S_TRANS_LATENCY_1 = 8; macro PAL_PSTATE_INFO$Q_TRANS_LATENCY_2 = 16,0,0,0 %; literal PAL_PSTATE_INFO$S_TRANS_LATENCY_2 = 8; macro PAL_PSTATE_INFO$q_spare = 24,0,0,0 %; literal PAL_PSTATE_INFO$s_spare = 8; ! Pstate return values literal PAL_PSTATE_RETURNS$M_DDT = %X'7'; literal PAL_PSTATE_RETURNS$M_DDIT = %X'7E0'; literal PAL_PSTATE_RETURNS$S_PAL_PSTATE_INFO_RETURNS = 32; macro PAL_PSTATE_RETURNS$Q_STATUS = 0,0,0,0 %; literal PAL_PSTATE_RETURNS$S_STATUS = 8; macro PAL_PSTATE_RETURNS$Q_PSTATE_NUM = 8,0,0,0 %; literal PAL_PSTATE_RETURNS$S_PSTATE_NUM = 8; macro PAL_PSTATE_RETURNS$Q_DD_INFO = 16,0,0,0 %; literal PAL_PSTATE_RETURNS$S_DD_INFO = 8; macro PAL_PSTATE_RETURNS$V_DDT = 16,0,3,0 %; literal PAL_PSTATE_RETURNS$S_DDT = 3; macro PAL_PSTATE_RETURNS$V_DDIT = 16,5,6,0 %; literal PAL_PSTATE_RETURNS$S_DDIT = 6; macro PAL_PSTATE_RETURNS$Q_SPARE = 24,0,0,0 %; literal PAL_PSTATE_RETURNS$S_SPARE = 8; ! ++ ! Definitions used by PAL_RSE_INFO ! -- ! return structure literal PAL_RSE_INFO$S_PAL_RSE_INFO = 32; macro PAL_RSE_INFO$Q_STATUS = 0,0,0,0 %; literal PAL_RSE_INFO$S_STATUS = 8; macro PAL_RSE_INFO$Q_PHYS_STACKED = 8,0,0,0 %; literal PAL_RSE_INFO$S_PHYS_STACKED = 8; macro PAL_RSE_INFO$Q_HINTS = 16,0,0,0 %; literal PAL_RSE_INFO$S_HINTS = 8; macro PAL_RSE_INFO$q_spare = 24,0,0,0 %; literal PAL_RSE_INFO$s_spare = 8; ! ++ ! Definitions used by PAL_FREQ_BASE ! -- ! return structure literal PAL_FREQ_BASE$S_PAL_FREQ_BASE = 32; macro PAL_FREQ_BASE$Q_STATUS = 0,0,0,0 %; literal PAL_FREQ_BASE$S_STATUS = 8; macro PAL_FREQ_BASE$Q_BASE_FREQ = 8,0,0,0 %; literal PAL_FREQ_BASE$S_BASE_FREQ = 8; macro PAL_FREQ_BASE$q_spare1 = 16,0,0,0 %; literal PAL_FREQ_BASE$s_spare1 = 8; macro PAL_FREQ_BASE$q_spare2 = 24,0,0,0 %; literal PAL_FREQ_BASE$s_spare2 = 8; literal PAL_FREQ_RATIO$S_PAL_FREQ_RATIO = 8; macro PAL_FREQ_RATIO$Q_V0 = 0,0,0,0 %; literal PAL_FREQ_RATIO$S_V0 = 8; macro PAL_FREQ_RATIO$L_DENOMINATOR = 0,0,32,0 %; macro PAL_FREQ_RATIO$L_NUMERATOR = 4,0,32,0 %; ! ++ ! Definitions used by PAL_HALT ! -- literal IA64_PAL$K_PAL_HALT_1 = 1; literal IA64_PAL$K_PAL_HALT_2 = 2; literal IA64_PAL$K_PAL_HALT_3 = 3; literal IA64_PAL$K_PAL_HALT_4 = 4; literal IA64_PAL$K_PAL_HALT_5 = 5; literal IA64_PAL$K_PAL_HALT_6 = 6; literal IA64_PAL$K_PAL_HALT_7 = 7; ! ++ ! Definitions used by PAL_HALT_INFO ! -- literal PAL_HALT_INFO$M_PWR_IM = %X'1000000000000000'; literal PAL_HALT_INFO$M_PWR_CO = %X'2000000000000000'; literal PAL_HALT_INFO$S_PAL_HALT_INFO = 8; macro PAL_HALT_INFO$Q_INFO = 0,0,0,0 %; literal PAL_HALT_INFO$S_INFO = 8; macro PAL_HALT_INFO$W_PWR_EXIT_LAT = 0,0,16,0 %; ! (0xffffUL << 0) macro PAL_HALT_INFO$W_PWR_ENTRY_LAT = 2,0,16,0 %; ! (0xffffUL << 16) macro PAL_HALT_INFO$V_PWR_CONSUMP = 4,0,28,0 %; literal PAL_HALT_INFO$S_PWR_CONSUMP = 28; macro PAL_HALT_INFO$V_PWR_IM = 4,28,1,0 %; macro PAL_HALT_INFO$V_PWR_CO = 4,29,1,0 %; ! ++ ! Definitions used by PAL_MC_CLEAR_LOG ! -- ! return structure literal PAL_MC_CLOG$M_PEND_MCHK = %X'1'; literal PAL_MC_CLOG$M_PEND_INIT = %X'2'; literal PAL_MC_CLOG$S_PAL_MC_CLOG = 32; macro PAL_MC_CLOG$Q_STATUS = 0,0,0,0 %; literal PAL_MC_CLOG$S_STATUS = 8; macro PAL_MC_CLOG$Q_PENDING = 8,0,0,0 %; literal PAL_MC_CLOG$S_PENDING = 8; macro PAL_MC_CLOG$V_PEND_MCHK = 8,0,1,0 %; macro PAL_MC_CLOG$V_PEND_INIT = 8,1,1,0 %; macro PAL_MC_CLOG$q_spare1 = 16,0,0,0 %; literal PAL_MC_CLOG$s_spare1 = 8; macro PAL_MC_CLOG$q_spare2 = 24,0,0,0 %; literal PAL_MC_CLOG$s_spare2 = 8; ! ++ ! Definitions used by PAL_MC_ERROR_INFO ! -- ! return structure literal PAL_MCERR$m_filler_1 = %X'FFFF'; literal PAL_MCERR$M_CACHE_CHK_WAY = %X'1F0000'; literal PAL_MCERR$m_filler_2 = %X'200000'; literal PAL_MCERR$M_CACHE_CHK_MC = %X'400000'; literal PAL_MCERR$M_CACHE_CHK_TV = %X'800000'; literal PAL_MCERR$M_CACHE_CHK_WV = %X'1000000'; literal PAL_MCERR$M_CACHE_CHK_OPER = %X'E000000'; literal PAL_MCERR$M_CACHE_CHK_DATA = %X'10000000'; literal PAL_MCERR$M_CACHE_CHK_TAG = %X'20000000'; literal PAL_MCERR$M_CACHE_CHK_DCACHE = %X'40000000'; literal PAL_MCERR$M_CACHE_CHK_ICACHE = %X'80000000'; literal PAL_MCERR$M_CACHE_CHK_INDEX = %X'FFFFFF00000000'; literal PAL_MCERR$M_CACHE_CHK_MV = %X'100000000000000'; literal PAL_MCERR$M_CACHE_CHK_MESI = %X'E00000000000000'; literal PAL_MCERR$M_CACHE_CHK_LEVEL = %X'F000000000000000'; literal PAL_MCERR$M_TLB_CHK_TRSLOT = %X'FF'; literal PAL_MCERR$m_filler_3 = %X'FF00'; literal PAL_MCERR$M_TLB_CHK_ITC = %X'10000'; literal PAL_MCERR$M_TLB_CHK_DTC = %X'20000'; literal PAL_MCERR$M_TLB_CHK_ITR = %X'40000'; literal PAL_MCERR$M_TLB_CHK_DTR = %X'80000'; literal PAL_MCERR$M_TLB_CHK_MC = %X'100000'; literal PAL_MCERR$M_BUS_CHK_SIZE = %X'1F'; literal PAL_MCERR$M_BUS_CHK_IB = %X'20'; literal PAL_MCERR$M_BUS_CHK_EB = %X'40'; literal PAL_MCERR$M_BUS_CHK_CC = %X'80'; literal PAL_MCERR$M_BUS_CHK_TYPE = %X'FF00'; literal PAL_MCERR$M_BUS_CHK_SEVERITY = %X'1F0000'; literal PAL_MCERR$M_BUS_CHK_TADDR_V = %X'200000'; literal PAL_MCERR$M_BUS_CHK_RSPADDR_V = %X'400000'; literal PAL_MCERR$M_BUS_CHK_REQADDR_V = %X'800000'; literal PAL_MCERR$M_BUS_CHK_BUSINFO = %X'FF000000'; literal PAL_MCERR$M_BUS_CHK_MC = %X'100000000'; literal PAL_MCERR$S_PAL_MCERR = 32; macro PAL_MCERR$Q_STATUS = 0,0,0,0 %; literal PAL_MCERR$S_STATUS = 8; macro PAL_MCERR$Q_ERROR_INFO = 8,0,0,0 %; literal PAL_MCERR$S_ERROR_INFO = 8; macro PAL_MCERR$Q_SIZE = 8,0,0,0 %; literal PAL_MCERR$S_SIZE = 8; macro PAL_MCERR$V_CACHE_CHK_WAY = 8,16,5,0 %; literal PAL_MCERR$S_CACHE_CHK_WAY = 5; ! (0x1fUL << 16) 16-20 macro PAL_MCERR$V_CACHE_CHK_MC = 8,22,1,0 %; ! (0x1UL << 22) 22 macro PAL_MCERR$V_CACHE_CHK_TV = 8,23,1,0 %; ! (0x1UL << 23) 23 macro PAL_MCERR$V_CACHE_CHK_WV = 8,24,1,0 %; ! (0x1UL << 24) 24 macro PAL_MCERR$V_CACHE_CHK_OPER = 8,25,3,0 %; literal PAL_MCERR$S_CACHE_CHK_OPER = 3; ! (0x7UL << 25) 25-27 macro PAL_MCERR$V_CACHE_CHK_DATA = 8,28,1,0 %; ! (0x1UL << 28) 28 macro PAL_MCERR$V_CACHE_CHK_TAG = 8,29,1,0 %; ! (0x1UL << 29) 29 macro PAL_MCERR$V_CACHE_CHK_DCACHE = 8,30,1,0 %; ! (0x1UL << 30) 30 macro PAL_MCERR$V_CACHE_CHK_ICACHE = 8,31,1,0 %; ! (0x1UL << 31) 31 macro PAL_MCERR$V_CACHE_CHK_INDEX = 12,0,24,0 %; literal PAL_MCERR$S_CACHE_CHK_INDEX = 24; ! (0xffffffUL << 32) 32-55 macro PAL_MCERR$V_CACHE_CHK_MV = 12,24,1,0 %; ! (0x1fUL << 56) 56 macro PAL_MCERR$V_CACHE_CHK_MESI = 12,25,3,0 %; literal PAL_MCERR$S_CACHE_CHK_MESI = 3; ! (0x7UL << 57) 57-59 macro PAL_MCERR$V_CACHE_CHK_LEVEL = 12,28,4,0 %; literal PAL_MCERR$S_CACHE_CHK_LEVEL = 4; ! (0xfUL << 60) 60-63 macro PAL_MCERR$V_TLB_CHK_TRSLOT = 8,0,8,0 %; literal PAL_MCERR$S_TLB_CHK_TRSLOT = 8; ! (0xffUL << 0) 0-7 macro PAL_MCERR$v_filler_3 = 8,8,8,0 %; literal PAL_MCERR$s_filler_3 = 8; ! 8-15 macro PAL_MCERR$V_TLB_CHK_ITC = 8,16,1,0 %; ! (0x1UL << 16) 16 macro PAL_MCERR$V_TLB_CHK_DTC = 8,17,1,0 %; ! (0x1UL << 17) 17 macro PAL_MCERR$V_TLB_CHK_ITR = 8,18,1,0 %; ! (0x1UL << 18) 18 macro PAL_MCERR$V_TLB_CHK_DTR = 8,19,1,0 %; ! (0x1UL << 19) 19 macro PAL_MCERR$V_TLB_CHK_MC = 8,20,1,0 %; ! (0x1UL << 20) 20 macro PAL_MCERR$V_BUS_CHK_SIZE = 8,0,5,0 %; literal PAL_MCERR$S_BUS_CHK_SIZE = 5; ! (0x1fUL << 0) 0-4 macro PAL_MCERR$V_BUS_CHK_IB = 8,5,1,0 %; ! (0x1UL << 5) 5 macro PAL_MCERR$V_BUS_CHK_EB = 8,6,1,0 %; ! (0x1UL << 6) 6 macro PAL_MCERR$V_BUS_CHK_CC = 8,7,1,0 %; ! (0x1UL << 7) 7 macro PAL_MCERR$V_BUS_CHK_TYPE = 8,8,8,0 %; literal PAL_MCERR$S_BUS_CHK_TYPE = 8; ! (0xffUL << 8) 8-15 macro PAL_MCERR$V_BUS_CHK_SEVERITY = 8,16,5,0 %; literal PAL_MCERR$S_BUS_CHK_SEVERITY = 5; ! (0x1fUL << 16) 16-20 macro PAL_MCERR$V_BUS_CHK_TADDR_V = 8,21,1,0 %; ! (0x1UL << 21) 21 macro PAL_MCERR$V_BUS_CHK_RSPADDR_V = 8,22,1,0 %; ! (0x1UL << 22) 22 macro PAL_MCERR$V_BUS_CHK_REQADDR_V = 8,23,1,0 %; ! (0x1UL << 23) 23 macro PAL_MCERR$V_BUS_CHK_BUSINFO = 8,24,8,0 %; literal PAL_MCERR$S_BUS_CHK_BUSINFO = 8; ! (0xffUL << 24) 24-31 macro PAL_MCERR$V_BUS_CHK_MC = 12,0,1,0 %; ! (0x1UL << 32) 32 macro PAL_MCERR$Q_INC_ERR_TYPE = 16,0,0,0 %; literal PAL_MCERR$S_INC_ERR_TYPE = 8; macro PAL_MCERR$q_spare = 24,0,0,0 %; literal PAL_MCERR$s_spare = 8; ! values needed literal IA64_PAL$K_MCERR_TYPE_PROC = 0; literal IA64_PAL$K_MCERR_TYPE_CACHE = 1; literal IA64_PAL$K_MCERR_TYPE_TLB = 2; literal IA64_PAL$K_MCERR_TYPE_BUS = 3; literal IA64_PAL$K_MCERR_TYPE_REQADR = 4; literal IA64_PAL$K_MCERR_TYPE_RSPADR = 5; literal IA64_PAL$K_MCERR_TYPE_TGTADR = 6; literal IA64_PAL$K_MCERR_TYPE_IMPL = 7; ! ++ ! Definitions used by PAL_PERF_MON_INFO ! -- ! return structure literal PAL_PM_INFO$S_PAL_PM_INFO = 32; macro PAL_PM_INFO$Q_STATUS = 0,0,0,0 %; literal PAL_PM_INFO$S_STATUS = 8; macro PAL_PM_INFO$Q_INFO = 8,0,0,0 %; literal PAL_PM_INFO$S_INFO = 8; macro PAL_PM_INFO$B_GENERIC = 8,0,8,0 %; ! (0xffUL << 0) macro PAL_PM_INFO$B_WIDTH = 9,0,8,0 %; ! (0xffUL << 8) macro PAL_PM_INFO$B_CYCLES = 10,0,8,0 %; ! (0xffUL << 16) macro PAL_PM_INFO$B_RETIRED = 11,0,8,0 %; ! (0xffUL << 24) macro PAL_PM_INFO$q_spare1 = 16,0,0,0 %; literal PAL_PM_INFO$s_spare1 = 8; macro PAL_PM_INFO$q_spare2 = 24,0,0,0 %; literal PAL_PM_INFO$s_spare2 = 8; ! PM buffer structure literal PAL_PM_BUFFER$S_PAL_PM_BUFFER = 128; macro PAL_PM_BUFFER$Q_PMC_IMPLEMENTED = 0,0,0,0 %; literal PAL_PM_BUFFER$S_PMC_IMPLEMENTED = 32; macro PAL_PM_BUFFER$Q_PMD_IMPLEMENTED = 32,0,0,0 %; literal PAL_PM_BUFFER$S_PMD_IMPLEMENTED = 32; macro PAL_PM_BUFFER$Q_COUNT_CYCLES = 64,0,0,0 %; literal PAL_PM_BUFFER$S_COUNT_CYCLES = 32; macro PAL_PM_BUFFER$Q_COUNT_RETIRED = 96,0,0,0 %; literal PAL_PM_BUFFER$S_COUNT_RETIRED = 32; ! ++ ! Definitions needed by PAL_PTCE_INFO ! -- ! return structure literal PAL_PTCE_INFO$S_PAL_PTCE_INFO = 32; macro PAL_PTCE_INFO$Q_STATUS = 0,0,0,0 %; literal PAL_PTCE_INFO$S_STATUS = 8; macro PAL_PTCE_INFO$PQ_TC_BASE = 8,0,0,1 %; literal PAL_PTCE_INFO$S_TC_BASE = 8; macro PAL_PTCE_INFO$L_TC_COUNTS = 16,0,0,0 %; literal PAL_PTCE_INFO$S_TC_COUNTS = 8; macro PAL_PTCE_INFO$L_TC_STRIDES = 24,0,0,0 %; literal PAL_PTCE_INFO$S_TC_STRIDES = 8; ! ++ ! Definitions needed by PAL_VM_INFO ! -- ! return structure literal PAL_VM_INFO$M_PF = %X'100000000'; literal PAL_VM_INFO$M_UNIFIED = %X'200000000'; literal PAL_VM_INFO$M_TR_REDUCE = %X'400000000'; literal PAL_VM_INFO$S_PAL_VM_INFO = 32; macro PAL_VM_INFO$Q_STATUS = 0,0,0,0 %; literal PAL_VM_INFO$S_STATUS = 8; macro PAL_VM_INFO$Q_TC_INFO = 8,0,0,0 %; literal PAL_VM_INFO$S_TC_INFO = 8; macro PAL_VM_INFO$B_NUM_SETS = 8,0,8,0 %; ! (0xffUL << 0) macro PAL_VM_INFO$B_NUM_WAYS = 9,0,8,0 %; ! (0xffUL << 8) macro PAL_VM_INFO$W_NUM_ENTRIES = 10,0,16,0 %; ! (0xffffUL << 16) macro PAL_VM_INFO$V_PF = 12,0,1,0 %; ! (0x1UL << 32) macro PAL_VM_INFO$V_UNIFIED = 12,1,1,0 %; ! (0x1UL << 33) macro PAL_VM_INFO$V_TR_REDUCE = 12,2,1,0 %; ! (0x1UL << 34) macro PAL_VM_INFO$Q_TC_PAGES = 16,0,0,0 %; literal PAL_VM_INFO$S_TC_PAGES = 8; macro PAL_VM_INFO$q_spare = 24,0,0,0 %; literal PAL_VM_INFO$s_spare = 8; ! ++ ! Definitions needed by PAL_VM_PAGE_SIZE ! -- ! return structure literal PAL_VM_PGSIZE$S_PAL_VM_PGSIZE = 32; macro PAL_VM_PGSIZE$Q_STATUS = 0,0,0,0 %; literal PAL_VM_PGSIZE$S_STATUS = 8; macro PAL_VM_PGSIZE$Q_INSERT_PAGES = 8,0,0,0 %; literal PAL_VM_PGSIZE$S_INSERT_PAGES = 8; macro PAL_VM_PGSIZE$Q_PURGE_PAGES = 16,0,0,0 %; literal PAL_VM_PGSIZE$S_PURGE_PAGES = 8; macro PAL_VM_PGSIZE$q_spare = 24,0,0,0 %; literal PAL_VM_PGSIZE$s_spare = 8; ! bits masks literal IA64_PAL$M_VM_PGSIZE_4KB = 4096; ! (0x1UL << 12) literal IA64_PAL$M_VM_PGSIZE_8KB = 8192; ! (0x1UL << 13) literal IA64_PAL$M_VM_PGSIZE_16KB = 16384; ! (0x1UL << 14) literal IA64_PAL$M_VM_PGSIZE_32KB = 32768; ! (0x1UL << 15) literal IA64_PAL$M_VM_PGSIZE_64KB = 65536; ! (0x1UL << 16) literal IA64_PAL$M_VM_PGSIZE_128KB = 131072; ! (0x1UL << 17) literal IA64_PAL$M_VM_PGSIZE_256KB = 262144; ! (0x1UL << 18) literal IA64_PAL$M_VM_PGSIZE_512KB = 524288; ! (0x1UL << 19) literal IA64_PAL$M_VM_PGSIZE_1MB = 1048576; ! (0x1UL << 20) literal IA64_PAL$M_VM_PGSIZE_2MB = 2097152; ! (0x1UL << 21) literal IA64_PAL$M_VM_PGSIZE_4MB = 4194304; ! (0x1UL << 22) literal IA64_PAL$M_VM_PGSIZE_8MB = 8388608; ! (0x1UL << 23) literal IA64_PAL$M_VM_PGSIZE_16MB = 16777216; ! (0x1UL << 24) literal IA64_PAL$M_VM_PGSIZE_32MB = 33554432; ! (0x1UL << 25) literal IA64_PAL$M_VM_PGSIZE_64MB = 67108864; ! (0x1UL << 26) literal IA64_PAL$M_VM_PGSIZE_128MB = 134217728; ! (0x1UL << 27) literal IA64_PAL$M_VM_PGSIZE_256MB = 268435456; ! (0x1UL << 28) literal IA64_PAL$M_VM_PGSIZE_512MB = 536870912; ! (0x1UL << 29) literal IA64_PAL$M_VM_PGSIZE_1GB = 1073741824; ! (0x1UL << 30) literal IA64_PAL$M_VM_PGSIZE_2GB = -2147483648; ! (0x1UL << 31) ! ++ ! Definitions needed for PAL_VM_SUMMARY ! -- ! return structure literal PAL_VM_SUMMARY$M_VW = %X'1'; literal PAL_VM_SUMMARY$M_PADDR_SIZE = %X'FE'; literal PAL_VM_SUMMARY$S_PAL_VM_SUMMARY = 32; macro PAL_VM_SUMMARY$Q_STATUS = 0,0,0,0 %; literal PAL_VM_SUMMARY$S_STATUS = 8; macro PAL_VM_SUMMARY$Q_INFO1 = 8,0,0,0 %; literal PAL_VM_SUMMARY$S_INFO1 = 8; macro PAL_VM_SUMMARY$V_VW = 8,0,1,0 %; ! (0x1UL << 0) macro PAL_VM_SUMMARY$V_PADDR_SIZE = 8,1,7,0 %; literal PAL_VM_SUMMARY$S_PADDR_SIZE = 7; ! (0x7fUL << 1) macro PAL_VM_SUMMARY$B_KEY_SIZE = 9,0,8,0 %; ! (0xffUL << 8) macro PAL_VM_SUMMARY$B_MAX_PKR = 10,0,8,0 %; ! (0xffUL << 16) macro PAL_VM_SUMMARY$B_HASH_ID = 11,0,8,0 %; ! (0xffUL << 24) macro PAL_VM_SUMMARY$B_MAX_DTR = 12,0,8,0 %; ! (0xffUL << 32) macro PAL_VM_SUMMARY$B_MAX_ITR = 13,0,8,0 %; ! (0xffUL << 40) macro PAL_VM_SUMMARY$B_UNIQ_TC = 14,0,8,0 %; ! (0xffUL << 48) macro PAL_VM_SUMMARY$B_TC_LEVELS = 15,0,8,0 %; ! (0xffUL << 56) macro PAL_VM_SUMMARY$Q_INFO2 = 16,0,0,0 %; literal PAL_VM_SUMMARY$S_INFO2 = 8; macro PAL_VM_SUMMARY$B_VA_MSB = 16,0,8,0 %; ! (0xffUL << 0) macro PAL_VM_SUMMARY$B_RID_SIZE = 17,0,8,0 %; ! (0xffUL << 8) macro PAL_VM_SUMMARY$q_spare = 24,0,0,0 %; literal PAL_VM_SUMMARY$s_spare = 8; ! ++ ! Definitions used by PAL_FIXED_ADDR ! -- literal PAL_FIXED_ADDR$S_PAL_FIXED_ADDR = 32; macro PAL_FIXED_ADDR$Q_STATUS = 0,0,0,0 %; literal PAL_FIXED_ADDR$S_STATUS = 8; macro PAL_FIXED_ADDR$Q_ADDRESS = 8,0,0,0 %; literal PAL_FIXED_ADDR$S_ADDRESS = 8; macro PAL_FIXED_ADDR$q_spare1 = 16,0,0,0 %; literal PAL_FIXED_ADDR$s_spare1 = 8; macro PAL_FIXED_ADDR$q_spare2 = 24,0,0,0 %; literal PAL_FIXED_ADDR$s_spare2 = 8; ! ++ ! Definitions used by PAL_MEM_ATTRIB ! -- literal PAL_MEM_ATTRIB$S_PAL_MEM_ATTRIB = 32; macro PAL_MEM_ATTRIB$Q_STATUS = 0,0,0,0 %; literal PAL_MEM_ATTRIB$S_STATUS = 8; macro PAL_MEM_ATTRIB$Q_ATTRIB = 8,0,0,0 %; literal PAL_MEM_ATTRIB$S_ATTRIB = 8; macro PAL_MEM_ATTRIB$B_ATTRIB = 8,0,8,0 %; macro PAL_MEM_ATTRIB$q_spare1 = 16,0,0,0 %; literal PAL_MEM_ATTRIB$s_spare1 = 8; macro PAL_MEM_ATTRIB$q_spare2 = 24,0,0,0 %; literal PAL_MEM_ATTRIB$s_spare2 = 8; ! ++ ! Definitions used by PAL_TR_READ ! (Not sure what AV, PV, DV, MV are for) ! -- literal PAL_TR_VALID$M_AV = %X'1'; literal PAL_TR_VALID$M_PV = %X'2'; literal PAL_TR_VALID$M_DV = %X'4'; literal PAL_TR_VALID$M_MV = %X'8'; literal PAL_TR_VALID$M_RSV1 = %X'FFFFFFF0'; literal PAL_TR_VALID$M_RSV2 = %X'FFFFFFFF00000000'; literal PAL_TR_VALID$S_PAL_TR_VALID = 32; macro PAL_TR_VALID$Q_VAL = 0,0,0,0 %; literal PAL_TR_VALID$S_VAL = 8; macro PAL_TR_VALID$V_AV = 8,0,1,0 %; macro PAL_TR_VALID$V_PV = 8,1,1,0 %; macro PAL_TR_VALID$V_DV = 8,2,1,0 %; macro PAL_TR_VALID$V_MV = 8,3,1,0 %; macro PAL_TR_VALID$V_RSV1 = 8,4,28,0 %; literal PAL_TR_VALID$S_RSV1 = 28; macro PAL_TR_VALID$V_RSV2 = 12,0,32,0 %; literal PAL_TR_VALID$S_RSV2 = 32; macro PAL_TR_VALID$q_spare1 = 16,0,0,0 %; literal PAL_TR_VALID$s_spare1 = 8; macro PAL_TR_VALID$q_spare2 = 24,0,0,0 %; literal PAL_TR_VALID$s_spare2 = 8; ! ++ ! Definitions used by PAL_LOGICAL_TO_PHYSICAL ! -- literal PAL_LOG_TO_PHY$M_NUM_LOG = %X'FFFF'; literal PAL_LOG_TO_PHY$M_TPC = %X'FF0000'; literal PAL_LOG_TO_PHY$M_RSV1 = %X'FF000000'; literal PAL_LOG_TO_PHY$M_CPP = %X'FF00000000'; literal PAL_LOG_TO_PHY$M_RSV2 = %X'FF0000000000'; literal PAL_LOG_TO_PHY$M_PPID = %X'FF000000000000'; literal PAL_LOG_TO_PHY$M_RSV3 = %X'FF00000000000000'; literal PAL_LOG_TO_PHY$M_TID = %X'FFFF'; literal PAL_LOG_TO_PHY$M_RSV4 = %X'FFFF0000'; literal PAL_LOG_TO_PHY$M_CID = %X'FFFF00000000'; literal PAL_LOG_TO_PHY$M_RSV5 = %X'FFFF000000000000'; literal PAL_LOG_TO_PHY$M_LA = %X'FFFF'; literal PAL_LOG_TO_PHY$M_RSV6 = %X'FFFF0000'; literal PAL_LOG_TO_PHY$M_RSV7 = %X'FFFFFFFF00000000'; literal PAL_LOG_TO_PHY$S_PAL_LOG_TO_PHY = 32; macro PAL_LOG_TO_PHY$Q_STATUS = 0,0,0,0 %; literal PAL_LOG_TO_PHY$S_STATUS = 8; macro PAL_LOG_TO_PHY$V_NUM_LOG = 8,0,16,0 %; literal PAL_LOG_TO_PHY$S_NUM_LOG = 16; macro PAL_LOG_TO_PHY$V_TPC = 8,16,8,0 %; literal PAL_LOG_TO_PHY$S_TPC = 8; macro PAL_LOG_TO_PHY$V_CPP = 12,0,8,0 %; literal PAL_LOG_TO_PHY$S_CPP = 8; macro PAL_LOG_TO_PHY$V_PPID = 12,16,8,0 %; literal PAL_LOG_TO_PHY$S_PPID = 8; macro PAL_LOG_TO_PHY$V_TID = 16,0,16,0 %; literal PAL_LOG_TO_PHY$S_TID = 16; macro PAL_LOG_TO_PHY$V_CID = 20,0,16,0 %; literal PAL_LOG_TO_PHY$S_CID = 16; macro PAL_LOG_TO_PHY$V_LA = 24,0,16,0 %; literal PAL_LOG_TO_PHY$S_LA = 16; !*** MODULE $IA64_SALDEF *** ! ++ ! SAL Procedure Function IDs ! ! 0x01XXXXXX Architected SAL functional group. ! 0x02XXXXXX - 0x03XXXXXX OEM SAL functional group. ! 0x04XXXXXX - 0xFFFFFFFF Reserved. ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Table 9-2, Section 9.3, pp. 9-4 ! -- literal IA64_SAL$K_SET_VECTORS = 16777216; literal IA64_SAL$K_GET_STATE_INFO = 16777217; literal IA64_SAL$K_GET_STATE_INFO_SIZE = 16777218; literal IA64_SAL$K_CLEAR_STATE_INFO = 16777219; literal IA64_SAL$K_MC_RENDEZ = 16777220; literal IA64_SAL$K_MC_SET_PARAMS = 16777221; literal IA64_SAL$K_REG_PHYS_ADDR = 16777222; literal IA64_SAL$K_CACHE_FLUSH = 16777224; literal IA64_SAL$K_CACHE_INIT = 16777225; literal IA64_SAL$K_PCI_CFG_READ = 16777232; literal IA64_SAL$K_PCI_CFG_WRITE = 16777233; literal IA64_SAL$K_FREQ_BASE = 16777234; literal IA64_SAL$K_PHYSICAL_ID_INFO = 16777235; literal IA64_SAL$K_UPDATE_PAL = 16777248; ! ++ ! SAL Procedure Generic Return Structure ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Section 8.2, pp. 8-5 ! -- literal SAL_RET$S_SAL_RET = 32; macro SAL_RET$Q_STATUS = 0,0,0,1 %; literal SAL_RET$S_STATUS = 8; macro SAL_RET$Q_RET1 = 8,0,0,0 %; literal SAL_RET$S_RET1 = 8; macro SAL_RET$Q_RET2 = 16,0,0,0 %; literal SAL_RET$S_RET2 = 8; macro SAL_RET$Q_RET3 = 24,0,0,0 %; literal SAL_RET$S_RET3 = 8; literal SAL_RET$K_LENGTH = 32; ! ++ ! SAL Procedure Generic Return Status ! ! Each SAL procedure uses a subset of these return status values. ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Table 8-5, Section 8.2.2.1, pp. 8-7 ! -- literal IA64_SAL$K_MOREINFO = 3; literal IA64_SAL$K_WARMBOOT = 2; literal IA64_SAL$K_OVRFLW = 1; literal IA64_SAL$K_SUCCESS = 0; literal IA64_SAL$K_UNIMPL = -1; literal IA64_SAL$K_INVALARG = -2; literal IA64_SAL$K_FAIL = -3; literal IA64_SAL$K_VANOTREG = -4; literal IA64_SAL$K_NOINFO = -5; literal IA64_SAL$K_BUFREQ = -9; literal IA64_SAL$K_RETRY = -15; ! SAL Procedures ! ++ ! SAL_SET_VECTORS ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Section 9.3, pp. 9-21 ! -- ! Values for VEC_TYPE Argument literal SAL_SV$K_MCA = 0; literal SAL_SV$K_INIT = 1; literal SAL_SV$K_BOOT_RENDEZ = 2; ! Structure for LEN_CS_N Argument literal SAL_SV$M_LEN_PROC = %X'FFFFFFFF'; literal SAL_SV$M_CHECKSUM_PRES = %X'100000000'; literal SAL_SV$M_MOD_CHECKSUM = %X'FF0000000000'; literal SAL_SV$S_SAL_SV_LEN_CS_N = 8; macro SAL_SV$Q_LEN_CS_N = 0,0,0,0 %; literal SAL_SV$S_LEN_CS_N = 8; macro SAL_SV$V_LEN_PROC = 0,0,32,0 %; literal SAL_SV$S_LEN_PROC = 32; macro SAL_SV$V_CHECKSUM_PRES = 4,0,1,0 %; macro SAL_SV$V_MOD_CHECKSUM = 4,8,8,0 %; literal SAL_SV$S_MOD_CHECKSUM = 8; literal SAL_SV_LEN_CS_N$K_LENGTH = 8; ! Return Structure literal SAL_SV_RET$S_SAL_SV_RET = 32; macro SAL_SV_RET$Q_STATUS = 0,0,0,1 %; literal SAL_SV_RET$S_STATUS = 8; literal SAL_SV_RET$K_LENGTH = 32; ! ++ ! SAL_GET_STATE_INFO ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Section 9.3, pp. 9-10 ! -- ! Values for TYPE Argument literal SAL_GSI$K_MCA = 0; literal SAL_GSI$K_INIT = 1; literal SAL_GSI$K_CMC = 2; literal SAL_GSI$K_CPE = 3; literal SAL_GSI$K_DECONFIGURED = 4; ! Return Structure literal SAL_GSI_RET$S_SAL_GSI_RET = 32; macro SAL_GSI_RET$Q_STATUS = 0,0,0,1 %; literal SAL_GSI_RET$S_STATUS = 8; macro SAL_GSI_RET$Q_TOTAL_LEN = 8,0,0,0 %; literal SAL_GSI_RET$S_TOTAL_LEN = 8; literal SAL_GSI_RET$K_LENGTH = 32; ! ++ ! SAL_GET_STATE_INFO_SIZE ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Section 9.3, pp. 9-12 ! -- ! Values for TYPE Argument literal SAL_GSIS$K_MCA = 0; literal SAL_GSIS$K_INIT = 1; literal SAL_GSIS$K_CMC = 2; literal SAL_GSIS$K_CPE = 3; literal SAL_GSIS$K_DECONFIGURED = 4; ! Return Structure literal SAL_GSIS_RET$S_SAL_GSIS_RET = 32; macro SAL_GSIS_RET$Q_STATUS = 0,0,0,1 %; literal SAL_GSIS_RET$S_STATUS = 8; macro SAL_GSIS_RET$Q_SIZE = 8,0,0,0 %; literal SAL_GSIS_RET$S_SIZE = 8; literal SAL_GSIS_RET$K_LENGTH = 32; ! ++ ! SAL_CLEAR_STATE_INFO ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Section 9.3, pp. 9-8 ! -- ! Values for TYPE Argument literal SAL_CSI$K_MCA = 0; literal SAL_CSI$K_INIT = 1; literal SAL_CSI$K_CMC = 2; literal SAL_CSI$K_CPE = 3; literal SAL_CSI$K_DECONFIGURED = 4; ! Return Structure literal SAL_CSI_RET$S_SAL_CSI_RET = 32; macro SAL_CSI_RET$Q_STATUS = 0,0,0,1 %; literal SAL_CSI_RET$S_STATUS = 8; literal SAL_CSI_RET$K_LENGTH = 32; ! ++ ! SAL_MC_RENDEZ ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Section 9.3, pp. 9-13 ! -- ! Return Structure literal SAL_MCR_RET$S_SAL_MCR_RET = 32; macro SAL_MCR_RET$Q_STATUS = 0,0,0,1 %; literal SAL_MCR_RET$S_STATUS = 8; literal SAL_MCR_RET$K_LENGTH = 32; ! ++ ! SAL_MC_SET_PARAMS ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Section 9.3, pp. 9-15 ! -- ! Values for PARAM_TYPE Argument literal SAL_MCSP$K_RENDEZ_INT = 1; literal SAL_MCSP$K_WAKE_UP = 2; literal SAL_MCSP$K_CPE_VEC = 3; ! Values for I_OR_M Argument literal SAL_MCSP$K_INT_VEC = 1; literal SAL_MCSP$K_MEM_ADDR = 2; ! Structure for MCA_OPT Argument literal SAL_MCSP$M_RZ_ALWAYS = %X'1'; literal SAL_MCSP$M_BINIT_ESC = %X'2'; literal SAL_MCSP$S_SAL_MCSP_MCA_OPT = 8; macro SAL_MCSP$Q_MCA_OPT = 0,0,0,0 %; literal SAL_MCSP$S_MCA_OPT = 8; macro SAL_MCSP$V_RZ_ALWAYS = 0,0,1,0 %; macro SAL_MCSP$V_BINIT_ESC = 0,1,1,0 %; macro SAL_MCSP$V_RESERVED = 0,2,30,0 %; literal SAL_MCSP$S_RESERVED = 30; macro SAL_MCSP$V_RESERVED_1 = 4,0,32,0 %; literal SAL_MCSP$S_RESERVED_1 = 32; literal SAL_MCSP_MCA_OPT$K_LENGTH = 8; ! Return Structure literal SAL_MCSP_RET$S_SAL_MCSP_RET = 32; macro SAL_MCSP_RET$Q_STATUS = 0,0,0,1 %; literal SAL_MCSP_RET$S_STATUS = 8; macro SAL_MCSP_RET$Q_TIME_OUT_MIN = 8,0,0,0 %; literal SAL_MCSP_RET$S_TIME_OUT_MIN = 8; literal SAL_MCSP_RET$K_LENGTH = 32; ! ++ ! SAL_REG_PHYS_ADDR ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Section 9.3, pp. 9-20 ! -- ! Value for PHYS_ENTITY Argument literal SAL_RPA$K_PAL_PROC = 0; ! Return Structure literal SAL_RPA_RET$S_SAL_RPA_RET = 32; macro SAL_RPA_RET$Q_STATUS = 0,0,0,1 %; literal SAL_RPA_RET$S_STATUS = 8; literal SAL_RPA_RET$K_LENGTH = 32; ! ++ ! SAL_CACHE_FLUSH ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Section 9.3, pp. 9-5 ! -- ! Values for I_OR_D Argument literal SAL_CF$K_FLUSH_ICACHE = 1; literal SAL_CF$K_FLUSH_DCACHE = 2; literal SAL_CF$K_FLUSH_BOTH = 3; literal SAL_CF$K_MAKE_COHERENT = 4; ! Return Structure literal SAL_CF_RET$S_SAL_CF_RET = 32; macro SAL_CF_RET$Q_STATUS = 0,0,0,1 %; literal SAL_CF_RET$S_STATUS = 8; literal SAL_CF_RET$K_LENGTH = 32; ! ++ ! SAL_CACHE_INIT ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Section 9.3, pp. 9-7 ! -- ! Return Structure literal SAL_CI_RET$S_SAL_CI_RET = 32; macro SAL_CI_RET$Q_STATUS = 0,0,0,1 %; literal SAL_CI_RET$S_STATUS = 8; literal SAL_CI_RET$K_LENGTH = 32; ! ++ ! SAL_PCI_CFG_READ ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Section 9.3, pp. 9-18 ! -- ! Structure for ADDR Argument literal SAL_PCICR$M_REG_ADDR = %X'FF'; literal SAL_PCICR$M_FUNC_NUM = %X'700'; literal SAL_PCICR$M_DEV_NUM = %X'F800'; literal SAL_PCICR$M_BUS_NUM = %X'FF0000'; literal SAL_PCICR$M_SEG_NUM = %X'FF000000'; literal SAL_PCICR$S_SAL_PCICR_ADDR = 8; macro SAL_PCICR$Q_ADDR = 0,0,0,0 %; literal SAL_PCICR$S_ADDR = 8; macro SAL_PCICR$V_REG_ADDR = 0,0,8,0 %; literal SAL_PCICR$S_REG_ADDR = 8; macro SAL_PCICR$V_FUNC_NUM = 0,8,3,0 %; literal SAL_PCICR$S_FUNC_NUM = 3; macro SAL_PCICR$V_DEV_NUM = 0,11,5,0 %; literal SAL_PCICR$S_DEV_NUM = 5; macro SAL_PCICR$V_BUS_NUM = 0,16,8,0 %; literal SAL_PCICR$S_BUS_NUM = 8; macro SAL_PCICR$V_SEG_NUM = 0,24,8,0 %; literal SAL_PCICR$S_SEG_NUM = 8; literal SAL_PCICR_ADDR$K_LENGTH = 8; ! Return Structure literal SAL_PCICR_RET$S_SAL_PCICR_RET = 32; macro SAL_PCICR_RET$Q_STATUS = 0,0,0,1 %; literal SAL_PCICR_RET$S_STATUS = 8; macro SAL_PCICR_RET$Q_VALUE = 8,0,0,0 %; literal SAL_PCICR_RET$S_VALUE = 8; literal SAL_PCICR_RET$K_LENGTH = 32; ! ++ ! SAL_PCI_CFG_WRITE ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Section 9.3, pp. 9-19 ! -- ! Structure for ADDR Argument literal SAL_PCICW$M_REG_ADDR = %X'FF'; literal SAL_PCICW$M_FUNC_NUM = %X'700'; literal SAL_PCICW$M_DEV_NUM = %X'F800'; literal SAL_PCICW$M_BUS_NUM = %X'FF0000'; literal SAL_PCICW$M_SEG_NUM = %X'FF000000'; literal SAL_PCICW$S_SAL_PCICW_ADDR = 8; macro SAL_PCICW$Q_ADDR = 0,0,0,0 %; literal SAL_PCICW$S_ADDR = 8; macro SAL_PCICW$V_REG_ADDR = 0,0,8,0 %; literal SAL_PCICW$S_REG_ADDR = 8; macro SAL_PCICW$V_FUNC_NUM = 0,8,3,0 %; literal SAL_PCICW$S_FUNC_NUM = 3; macro SAL_PCICW$V_DEV_NUM = 0,11,5,0 %; literal SAL_PCICW$S_DEV_NUM = 5; macro SAL_PCICW$V_BUS_NUM = 0,16,8,0 %; literal SAL_PCICW$S_BUS_NUM = 8; macro SAL_PCICW$V_SEG_NUM = 0,24,8,0 %; literal SAL_PCICW$S_SEG_NUM = 8; literal SAL_PCICW_ADDR$K_LENGTH = 8; ! Return Structure literal SAL_PCICW_RET$S_SAL_PCICW_RET = 32; macro SAL_PCICW_RET$Q_STATUS = 0,0,0,1 %; literal SAL_PCICW_RET$S_STATUS = 8; literal SAL_PCICW_RET$K_LENGTH = 32; ! ++ ! SAL_FREQ_BASE ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Section 9.3, pp. 9-9 ! -- ! Values for CLOCK_TYPE Argument literal SAL_FB$K_SYS_CLK_FREQ = 0; literal SAL_FB$K_INT_TIMER = 1; literal SAL_FB$K_REAL_TIME_CLK = 2; ! Return Structure literal SAL_FB_RET$S_SAL_FB_RET = 32; macro SAL_FB_RET$Q_STATUS = 0,0,0,1 %; literal SAL_FB_RET$S_STATUS = 8; literal SAL_FB_RET$K_LENGTH = 32; ! Return structure for PHYSICAL_ID_INFO literal SAL_PID_RET$S_SAL_PID_RET = 32; macro SAL_PID_RET$Q_STATUS = 0,0,0,1 %; literal SAL_PID_RET$S_STATUS = 8; macro SAL_PID_RET$W_PLID = 8,0,16,0 %; literal SAL_PID_RET$K_LENGTH = 32; ! ++ ! SAL_UPDATE_PAL ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Section 9.3, pp. 9-21 ! -- ! Structure for PARAM_BUF Argument literal SAL_UPAL$S_SAL_UPAL_PARAM_BUF = 32; macro SAL_UPAL$Q_NEXT_PTR = 0,0,0,0 %; literal SAL_UPAL$S_NEXT_PTR = 8; macro SAL_UPAL$Q_UPD_DAT_BLK_PTR = 8,0,0,0 %; literal SAL_UPAL$S_UPD_DAT_BLK_PTR = 8; macro SAL_UPAL$B_CHECKSUM_FLAG = 16,0,8,0 %; literal SAL_UPAL_PBUF$K_LENGTH = 32; ! Structure for Update Data Block literal SAL_UPAL$S_SAL_UPAL_UPD_DAT_BLK = 64; macro SAL_UPAL$L_FW_SIZE = 0,0,32,0 %; macro SAL_UPAL$L_FW_DATE = 4,0,32,0 %; macro SAL_UPAL$W_FW_VER = 8,0,16,0 %; macro SAL_UPAL$B_FW_TYPE = 10,0,8,0 %; macro SAL_UPAL$Q_FW_VEND_ID = 16,0,0,0 %; literal SAL_UPAL$S_FW_VEND_ID = 8; literal SAL_UPAL_UDBLK$K_LENGTH = 64; ! Return Structure literal SAL_UPAL_RET$S_SAL_UPAL_RET = 32; macro SAL_UPAL_RET$Q_STATUS = 0,0,0,1 %; literal SAL_UPAL_RET$S_STATUS = 8; literal SAL_UPAL_RET$K_LENGTH = 32; ! Value for ERROR_CODE Return Value literal SAL_UPAL$K_INCOMP_FW_VER = -1; literal SAL_UPAL$K_AUTH_TEST_FAIL = -2; literal SAL_UPAL$K_INV_FW_COMP = -3; literal SAL_UPAL$K_FW_NOT_ERASE = -4; literal SAL_UPAL$K_WRITE_FAIL = -10; literal SAL_UPAL$K_ERASE_FAIL = -11; literal SAL_UPAL$K_READ_FAIL = -12; literal SAL_UPAL$K_INSUFF_SPACE = -13; ! SAL System Table ! ++ ! SAL System Table Header ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Table 3-2, Section 3.2.7, pp. 3-11 - 3-12 ! -- literal SAL_STHD$S_SAL_SYS_TBL_HD = 96; macro SAL_STHD$B_SIG = 0,0,32,0 %; literal SAL_STHD$S_SIG = 4; macro SAL_STHD$L_TOTAL_TBL_LEN = 4,0,32,0 %; macro SAL_STHD$W_SAL_REV = 8,0,16,0 %; macro SAL_STHD$B_MINOR_SAL_REV = 8,0,8,0 %; macro SAL_STHD$B_MAJOR_SAL_REV = 9,0,8,0 %; macro SAL_STHD$W_ENTRY_COUNT = 10,0,16,0 %; macro SAL_STHD$B_CHECKSUM = 12,0,8,0 %; macro SAL_STHD$W_SAL_A_VER = 20,0,16,0 %; macro SAL_STHD$B_MINOR_SAL_A_VER = 20,0,8,0 %; macro SAL_STHD$B_MAJOR_SAL_A_VER = 21,0,8,0 %; macro SAL_STHD$W_SAL_B_VER = 22,0,16,0 %; macro SAL_STHD$B_MINOR_SAL_B_VER = 22,0,8,0 %; macro SAL_STHD$B_MAJOR_SAL_B_VER = 23,0,8,0 %; macro SAL_STHD$B_OEM_ID = 24,0,0,0 %; literal SAL_STHD$S_OEM_ID = 32; macro SAL_STHD$B_PRODUCT_ID = 56,0,0,0 %; literal SAL_STHD$S_PRODUCT_ID = 32; literal SAL_STHD$K_LENGTH = 96; ! ++ ! SAL System Table Entrypoint Descriptor Entry ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Table 3-4, Section 3.2.7.1, pp. 3-12 ! -- literal SAL_STEPD$S_SAL_SYS_TBL_EPD = 48; macro SAL_STEPD$B_ENTRY_TYPE = 0,0,8,0 %; macro SAL_STEPD$Q_PHYS_ADDR_PAL_PROC = 8,0,0,0 %; literal SAL_STEPD$S_PHYS_ADDR_PAL_PROC = 8; macro SAL_STEPD$Q_PHYS_ADDR_SAL_PROC = 16,0,0,0 %; literal SAL_STEPD$S_PHYS_ADDR_SAL_PROC = 8; macro SAL_STEPD$Q_GP_SAL = 24,0,0,0 %; literal SAL_STEPD$S_GP_SAL = 8; literal SAL_STEPD$K_LENGTH = 48; ! ++ ! SAL System Table Memory Descriptor Entry ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Table 3-5, Section 3.2.7.2, pp. 3-13 - 3-14 ! -- literal SAL_STMD$M_NEED_VA_REG = %X'1'; literal SAL_STMD$M_MEM_ATTR_SET = %X'7'; literal SAL_STMD$M_WB = %X'1'; literal SAL_STMD$M_UC = %X'2'; literal SAL_STMD$M_UCE = %X'4'; literal SAL_STMD$M_WC = %X'8'; literal SAL_STMD$S_SAL_SYS_TBL_MD = 32; macro SAL_STMD$B_ENTRY_TYPE = 0,0,8,0 %; macro SAL_STMD$B_NEED_VA_REG = 1,0,8,0 %; macro SAL_STMD$V_NEED_VA_REG = 1,0,1,0 %; macro SAL_STMD$B_MEM_ATTR_SET = 2,0,8,0 %; macro SAL_STMD$V_MEM_ATTR_SET = 2,0,3,0 %; literal SAL_STMD$S_MEM_ATTR_SET = 3; macro SAL_STMD$B_PAGE_ACCESS_RIGHTS = 3,0,8,0 %; macro SAL_STMD$B_MEM_ATTR_SUP = 4,0,8,0 %; macro SAL_STMD$V_WB = 4,0,1,0 %; macro SAL_STMD$V_UC = 4,1,1,0 %; macro SAL_STMD$V_UCE = 4,2,1,0 %; macro SAL_STMD$V_WC = 4,3,1,0 %; macro SAL_STMD$B_MEM_TYPE = 6,0,8,0 %; macro SAL_STMD$B_MEM_USAGE = 7,0,8,0 %; macro SAL_STMD$Q_PHYS_ADDR = 8,0,0,0 %; literal SAL_STMD$S_PHYS_ADDR = 8; macro SAL_STMD$L_NUM_4K_PAGES = 16,0,32,0 %; literal SAL_STMD$K_LENGTH = 32; ! ++ ! SAL System Table Platform Features Descriptor Entry ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Table 3-7, Section 3.2.7.3, pp. 3-15 - 3-16 ! -- literal SAL_STSFD$M_BUS_LOCK = %X'1'; literal SAL_STSFD$M_SYS_INT_REDIR = %X'2'; literal SAL_STSFD$M_PROC_IPI_MSG_REDIR = %X'4'; literal SAL_STSFD$S_SAL_SYS_TBL_SFD = 16; macro SAL_STSFD$B_ENTRY_TYPE = 0,0,8,0 %; macro SAL_STSFD$B_SYS_FEAT = 1,0,8,0 %; macro SAL_STSFD$V_BUS_LOCK = 1,0,1,0 %; macro SAL_STSFD$V_SYS_INT_REDIR = 1,1,1,0 %; macro SAL_STSFD$V_PROC_IPI_MSG_REDIR = 1,2,1,0 %; literal SAL_STSFD$K_LENGTH = 16; ! ++ ! SAL System Table Translation Register Descriptor Entry ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Table 3-8, Section 3.2.7.4, pp. 3-16 ! -- literal SAL_STTRD$S_SAL_SYS_TBL_TRD = 32; macro SAL_STTRD$B_ENTRY_TYPE = 0,0,8,0 %; macro SAL_STTRD$B_TRANS_REG_TYPE = 1,0,8,0 %; macro SAL_STTRD$B_TRANS_REG_NUM = 2,0,8,0 %; macro SAL_STTRD$Q_VA_TRANS_REG = 8,0,0,0 %; literal SAL_STTRD$S_VA_TRANS_REG = 8; macro SAL_STTRD$Q_PAGE_SIZE_TRANS_REG = 16,0,0,0 %; literal SAL_STTRD$S_PAGE_SIZE_TRANS_REG = 8; literal SAL_STRDD$K_LENGTH = 32; ! ++ ! SAL System Table Purge Translation Cache Coherence Domain Entry ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Table 3-9, Section 3.2.7.5, pp. 3-16 ! -- literal SAL_STPTCCD$S_SAL_SYS_TBL_PTCCD = 16; macro SAL_STPTCCD$B_ENTRY_TYPE = 0,0,8,0 %; macro SAL_STPTCCD$L_NUM_SYS_COH_DOM = 4,0,32,0 %; macro SAL_STPTCCD$Q_COH_DOM_DATA_ADDR = 8,0,0,0 %; literal SAL_STPTCCD$S_COH_DOM_DATA_ADDR = 8; literal SAL_STPTCCD$K_LENGTH = 16; ! ++ ! SAL System Table Application Processor Wake-up Descriptor Entry ! ! "Itanium Processor Family System Abstraction Layer Specification, July 2001" ! Table 3-11, Section 3.2.7.6, pp. 3-17 ! -- literal SAL_STAPWUD$S_SAL_SYS_TBL_APWUD = 16; macro SAL_STAPWUD$B_ENTRY_TYPE = 0,0,8,0 %; macro SAL_STAPWUD$B_WAKE_UP_MECH_TYPE = 1,0,8,0 %; macro SAL_STAPWUD$Q_EX_INTVEC_10_FF = 8,0,0,0 %; literal SAL_STAPWUD$S_EX_INTVEC_10_FF = 8; literal SAL_STAPWUD$K_LENGTH = 16; !*** MODULE $IAFDEF *** ! + ! IAF - IMAGE ACTIVATOR FIXUP SECTION ! ! THE IMAGE ACTIVATOR FIXUP SECTION IS AN IMAGE SECTION THAT IS CREATED ! BY THE LINKER AND USED BY THE IMAGE ACTIVATOR TO MODIFY THE IMAGE AS ! IT IS ACTIVATED. THIS IS DONE TO MAINTAIN THE POSITION INDEPENDENCE ! OF EXTERNAL REFERENCES. ! - literal IAF$K_LENGTH = 64; ! Length of fixed area literal IAF$C_LENGTH = 64; ! Length of fixed area literal IAF$S_IAFDEF = 64; literal IAF$S_IAF = 64; macro IAF$L_IAFLINK = 0,0,32,1 %; ! Link for image activator use macro IAF$L_FIXUPLNK = 4,0,32,1 %; ! Link for shareable image fixups macro IAF$W_SIZE = 8,0,16,0 %; ! Size of fixed part of IAF macro IAF$W_FLAGS = 10,0,16,0 %; ! Flags macro IAF$V_SHR = 10,0,1,0 %; ! This is in a shareable image macro IAF$L_G_FIXOFF = 12,0,32,0 %; ! Offset to g^ address data macro IAF$L_DOTADROFF = 16,0,32,0 %; ! Offset to .address fixup data macro IAF$L_CHGPRTOFF = 20,0,32,0 %; ! Offset to isect change prot. data macro IAF$L_SHLSTOFF = 24,0,32,0 %; ! Offset to shareable image list macro IAF$L_SHRIMGCNT = 28,0,32,0 %; ! Number of shareable images in shlst macro IAF$L_SHLEXTRA = 32,0,32,0 %; ! Number of extra shareable images allowed macro IAF$L_PERMCTX = 36,0,32,1 %; ! Permanent sharable image context !*** MODULE $ICAPDEF *** ! + ! iCAP flags reside in ICAP$GQ_STATE ! ! - literal ICAP$M_ICAP = %X'1'; literal ICAP$M_TICAP = %X'2'; literal ICAP$M_GWLM = %X'4'; literal ICAP$M_RESERVED2 = %X'8'; literal ICAP$M_RESERVED3 = %X'10'; literal ICAP$M_RESERVED4 = %X'20'; literal ICAP$S_ICAP = 8; macro ICAP$Q_QUADWORD = 0,0,0,0 %; literal ICAP$S_QUADWORD = 8; macro ICAP$V_ICAP = 0,0,1,0 %; ! iCAP system detected macro ICAP$V_TICAP = 0,1,1,0 %; ! Temporary capacity is being consumed macro ICAP$V_GWLM = 0,2,1,0 %; ! gwlm: global workload manager in use macro ICAP$V_RESERVED2 = 0,3,1,0 %; macro ICAP$V_RESERVED3 = 0,4,1,0 %; macro ICAP$V_RESERVED4 = 0,5,1,0 %; !*** MODULE $ICPDEF *** ! + ! ICP - CHANGE IMAGE SECTION PROTECTION DATA ! ! THIS STRUCTURE IS USED IN THE IMAGE FIXUP SECTION BY THE LINKER ! TO INFORM THE IMAGE ACTIVATOR OF THE IMAGE SECTIONS THAT NEED ! THEIR PROTECTION CHANGED. ! - literal ICP$K_LENGTH = 8; ! size of one section's data literal ICP$C_LENGTH = 8; ! size of one section's data literal ICP$S_ICPDEF = 8; literal ICP$S_ICP = 8; macro ICP$L_BASEVA = 0,0,32,1 %; ! virtual address of start of section macro ICP$W_NPAGES = 4,0,16,0 %; ! number of pages to change protection on macro ICP$W_NEWPRT = 6,0,16,0 %; ! new protection !*** MODULE $ICRDDEF *** ! ! Invo Context Region Descriptor Definitions. The invo context region ! descriptor entry contains memory management data for an invo context ! region. ! literal ICRD$M_IN_USE = %X'1'; literal ICRD$m_reserved_1 = %X'FE'; literal ICRD$m_mode = %X'300'; literal ICRD$M_RESERVED_FLAGS = %X'FFFFFC00'; literal ICRD$C_LENGTH = 48; ! Length of ICRD literal ICRD$S_ICRD = 48; macro ICRD$PQ_BASE_VA = 0,0,0,1 %; literal ICRD$S_BASE_VA = 8; ! Base address for address space macro ICRD$PQ_GUARD_VA = 8,0,0,1 %; literal ICRD$S_GUARD_VA = 8; ! Address of high guard page macro ICRD$W_SIZE = 16,0,16,0 %; ! Structure size macro ICRD$B_TYPE = 18,0,8,0 %; ! Dynamic structure type macro ICRD$B_SUBTYPE = 19,0,8,0 %; ! Dynamic structore subtype macro ICRD$L_FLAGS = 20,0,32,0 %; ! FLAGS longword macro ICRD$V_IN_USE = 20,0,1,0 %; ! Region is in use macro ICRD$v_reserved_1 = 20,1,7,0 %; literal ICRD$s_reserved_1 = 7; ! macro ICRD$v_mode = 20,8,2,0 %; literal ICRD$s_mode = 2; ! Owner and page access mode macro ICRD$V_RESERVED_FLAGS = 20,10,22,0 %; literal ICRD$S_RESERVED_FLAGS = 22; macro ICRD$Q_REGION_ID = 24,0,0,0 %; literal ICRD$S_REGION_ID = 8; ! ID of virtual region macro ICRD$PQ_FIRST_FREE_VA = 32,0,0,1 %; literal ICRD$S_FIRST_FREE_VA = 8; ! First page in region not yet created macro ICRD$PQ_NEXT_VA = 40,0,0,1 %; literal ICRD$S_NEXT_VA = 8; ! Next VA for malloc !*** MODULE $IDBDEF *** ! + ! IDB - INTERRUPT DISPATCH BLOCK ! ! AN INTERRUPT DISPATCH BLOCK PROVIDES THE INFORMATION NECESSARY FOR A ! UNIT INDEPENDENT, BUT CONTROLLER SPECIFIC, INTERRUPT DISPATCHER TO ! DISPATCH INTERRUPTS TO THE PROPER DRIVER TO HANDLE AN INTERRUPT ON ! A DEVICE UNIT. ! - literal IDB$M_CRAM_ALLOC = %X'1'; literal IDB$M_VLE = %X'2'; literal IDB$M_NORESIZE = %X'4'; literal IDB$M_MCJ = %X'8'; literal IDB$M_SHARED_INT = %X'10'; literal IDB$M_DISTRIBUTED_INT = %X'20'; literal IDB$M_ISR_CALLABLE = %X'40'; literal IDB$K_BASE_LENGTH = 56; ! length without UCBLST literal IDB$C_BASE_LENGTH = 56; ! length without UCBLST literal IDB$S_IDB = 88; macro IDB$Q_CSR = 0,0,0,0 %; literal IDB$S_CSR = 8; ! CONTROLLER CSR "ADDRESS" macro IDB$W_SIZE = 8,0,16,0 %; ! SIZE OF IDB IN BYTES macro IDB$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE OF IDB macro IDB$W_UNITS = 12,0,16,0 %; ! NUMBER OF UNITS (SIZE OF UCBLST) macro IDB$W_TT_ENABLE = 14,0,16,0 %; ! DZ32 line enable field macro IDB$PS_OWNER = 16,0,32,1 %; ! OWNER UCB ADDRESS macro IDB$PS_CRAM = 20,0,32,1 %; ! Per-controller CRAM list macro IDB$PS_SPL = 24,0,32,1 %; ! ADDRESS OF DEVICE SPINLOCK macro IDB$PS_ADP = 28,0,32,1 %; ! ADDRESS OF ADAPTER CONTROL BLOCK macro IDB$L_FLAGS = 32,0,32,0 %; ! IDB flags macro IDB$V_CRAM_ALLOC = 32,0,1,0 %; ! $LOAD_DRIVER has done CRAM allocation for this IDB macro IDB$V_VLE = 32,1,1,0 %; ! IDB$L_VECTOR points to a VLE macro IDB$V_NORESIZE = 32,2,1,0 %; ! IDB isn't in pool and shouldn't be resized macro IDB$V_MCJ = 32,3,1,0 %; ! IDB$Q_CSR points to an MCJ macro IDB$V_SHARED_INT = 32,4,1,0 %; ! Connected as Shared Interrupt macro IDB$V_DISTRIBUTED_INT = 32,5,1,0 %; ! Connected as Distributed Interrupt macro IDB$V_ISR_CALLABLE = 32,6,1,0 %; ! Ints can be delivered to the ISR macro IDB$L_DEVICE_SPECIFIC = 36,0,32,0 %; ! Available to device drivers macro IDB$L_VECTOR = 40,0,32,1 %; ! SCB offset for interrupts macro IDB$PS_AUXSTRUC = 44,0,32,1 %; ! driver specific data macro IDB$L_INTERRUPT_CPU = 48,0,32,0 %; ! Target CPU for Distributed Interrupts macro IDB$L_RESERVED = 52,0,32,0 %; ! ...for future expansion macro IDB$L_UCBLST = 56,0,0,1 %; literal IDB$S_UCBLST = 32; ! UCB OR SECONDARY IDB ADDRESSES ! (DEFAULT OF 8) literal IDB$K_LENGTH = 88; ! LENGTH OF STANDARD IDB literal IDB$C_LENGTH = 88; ! LENGTH OF STANDARD IDB literal IDB$S_IDBDEF = 88; ! OLD IDB SIZE FOR COMPATIBILITY !*** MODULE $IDTDEF *** ! ! Interrupt and Exception Handler Dispatch Table Definitions. This table ! specifies the entry points for exception and interrupt handlers. ! literal IDT$C_UNUSED_0 = 0; ! %X0 Unused vector literal IDT$C_FLOAT_DISABLED = 1; ! %X1 Floating disabled fault literal IDT$C_UNUSED_2 = 2; ! %X2 Unused vector literal IDT$C_UNUSED_3 = 3; ! %X3 Unused vector literal IDT$C_UNUSED_4 = 4; ! %X4 Unused vector literal IDT$C_UNUSED_5 = 5; ! %X5 Unused vector literal IDT$C_UNUSED_6 = 6; ! %X6 Unused vector literal IDT$C_UNUSED_7 = 7; ! %X7 Unused vector literal IDT$C_ACCVIO = 8; ! %X8 Access control violation fault literal IDT$C_TRANSLATION_FAULT = 9; ! %X9 Translation not valid fault literal IDT$C_READ_FAULT = 10; ! %XA Fault on read fault literal IDT$C_WRITE_FAULT = 11; ! %XB Fault on write fault literal IDT$C_EXECUTE_FAULT = 12; ! %XC Fault on execute fault literal IDT$C_ARITHMETIC_TRAP = 32; ! %X20 Arithmetic trap literal IDT$C_KERNEL_AST = 36; ! %X24 Kernel mode AST literal IDT$C_EXEC_AST = 37; ! %X25 Exec mode AST literal IDT$C_SUPER_AST = 38; ! %X26 Super mode AST literal IDT$C_USER_AST = 39; ! %X27 User mode AST literal IDT$C_REPORT_ALIGN_FAULT = 40; ! %X28 Report alignment fault literal IDT$C_UNUSED_290 = 41; ! %X29 Unused vector literal IDT$C_UNUSED_2A0 = 42; ! %X2A Unused vector literal IDT$C_UNUSED_2B0 = 43; ! %X2B Unused vector literal IDT$C_UNUSED_2C0 = 44; ! %X2C Unused vector literal IDT$C_UNUSED_2D0 = 45; ! %X2D Unused vector literal IDT$C_UNUSED_2E0 = 46; ! %X2E Unused vector literal IDT$C_UNUSED_2F0 = 47; ! %X2F Unused vector literal IDT$C_LOAD_F_FLOAT = 48; ! %X30 Load F floating literal IDT$C_LOAD_D_FLOAT = 49; ! %X31 Load D floating literal IDT$C_LOAD_S_FLOAT = 50; ! %X32 Load S floating literal IDT$C_LOAD_T_FLOAT = 51; ! %X33 Load T floating literal IDT$C_STORE_F_FLOAT = 52; ! %X34 Store F floating literal IDT$C_STORE_D_FLOAT = 53; ! %X35 Store D floating literal IDT$C_STORE_S_FLOAT = 54; ! %X36 Store S floating literal IDT$C_STORE_T_FLOAT = 55; ! %X37 Store T floating literal IDT$C_LOAD_SEXT_LONG = 56; ! %X38 Load sign-extended longword literal IDT$C_LOAD_QUAD = 57; ! %X39 Load quadword literal IDT$C_LOAD_SEXT_LONG_L = 58; ! %X3A Load sign-extended longword locked literal IDT$C_LOAD_QUAD_L = 59; ! %X3B Load quadword locked literal IDT$C_STORE_LONG = 60; ! %X3C Store longword literal IDT$C_STORE_QUAD = 61; ! %X3D Store quadword literal IDT$C_STORE_LONG_C = 62; ! %X3E Store longword conditional literal IDT$C_STORE_QUAD_C = 63; ! %X3F Store quadword conditional literal IDT$C_BREAK_DBG = 64; ! %X40 Debug break point trap literal IDT$C_BREAK_BUGCHK = 65; ! %X41 Bugcheck break point trap literal IDT$C_ILLEGAL_INSTRUCTION = 66; ! %X42 Illegal instruction trap literal IDT$C_ILLEGAL_PAL_OPERAND = 67; ! %X43 Illegal call PAL operand literal IDT$C_GENTRAP = 68; ! %X44 Software generated trap literal IDT$C_UNUSED_45 = 69; ! %X45 Unused vector literal IDT$C_UNUSED_46 = 70; ! %X46 Unused vector literal IDT$C_UNUSED_47 = 71; ! %X47 Unused vector literal IDT$C_CHANGE_MODE_KERNEL = 72; ! %X48 Change mode to kernel literal IDT$C_CHANGE_MODE_EXEC = 73; ! %X49 Change mode to exec literal IDT$C_CHANGE_MODE_SUPER = 74; ! %X4A Change mode to super literal IDT$C_CHANGE_MODE_USER = 75; ! %X4B Change mode to user literal IDT$C_HP_1 = 76; ! %X4C Reserved for hp literal IDT$C_HP_2 = 77; ! %X4D Reserved for hp literal IDT$C_HP_3 = 78; ! %X4E Reserved for hp literal IDT$C_HP_4 = 79; ! %X4F Reserved for hp literal IDT$C_UNUSED_50 = 80; ! %X50 Unused literal IDT$C_SOFT_INTERRUPT_1 = 81; ! %X51 Software level 1 interrupt literal IDT$C_SOFT_INTERRUPT_2 = 82; ! %x52 Software level 2 interrupt literal IDT$C_SOFT_INTERRUPT_3 = 83; ! %X53 Software level 3 interrupt literal IDT$C_SOFT_INTERRUPT_4 = 84; ! %X54 Software level 4 interrupt literal IDT$C_SOFT_INTERRUPT_5 = 85; ! %X55 Software level 5 interrupt literal IDT$C_SOFT_INTERRUPT_6 = 86; ! %X56 Software level 6 interrupt literal IDT$C_SOFT_INTERRUPT_7 = 87; ! %X57 Software level 7 interrupt literal IDT$C_SOFT_INTERRUPT_8 = 88; ! %X58 Software level 8 interrupt literal IDT$C_SOFT_INTERRUPT_9 = 89; ! %X59 Software level 9 interrupt literal IDT$C_SOFT_INTERRUPT_10 = 90; ! %X5A Software level 10 interrupt literal IDT$C_SOFT_INTERRUPT_11 = 91; ! %X5B Software level 11 interrupt literal IDT$C_SOFT_INTERRUPT_12 = 92; ! %X5C Software level 12 interrupt literal IDT$C_SOFT_INTERRUPT_13 = 93; ! %X5D Software level 13 interrupt literal IDT$C_SOFT_INTERRUPT_14 = 94; ! %X5E Software level 14 interrupt literal IDT$C_SOFT_INTERRUPT_15 = 95; ! %X5F Software level 15 interrupt literal IDT$C_SOFT_INTERRUPT_BASE = 80; ! Reschedule interrupt literal IDT$C_RESCHEDULE = 83; ! Reschedule interrupt literal IDT$C_IO_POST = 84; ! I/O post interrupt literal IDT$C_SW_TIMER_INTERRUPT = 87; ! Software timer interrupt literal IDT$C_IP_CONTROL = 92; ! IP control literal IDT$C_XDELTA = 94; ! Xdelta literal IDT$C_INTERVAL_CLOCK = 96; ! %X60 Interval clock interrupt literal IDT$C_INTERPROCESSOR = 97; ! %X61 Interprocessor interrupt literal IDT$C_SYSTEM_CORRECTED_ERROR = 98; ! %X62 System corrected error interrupt literal IDT$C_PROCESS_CORRECTED_ERROR = 99; ! %X63 Processor corrected error interrupt literal IDT$C_POWER_FAIL = 100; ! %X64 Power fail interrupt literal IDT$C_PERF_MONITOR = 101; ! %X65 Reserved for performance monitor literal IDT$C_SYSTEM_MACHINE_CHECK = 102; ! %X66 System machine check abort literal IDT$C_PROCESSOR_MACHINE_CHECK = 103; ! %X67 Processor machine check abort literal IDT$C_SYSTEM_ENV_EVENT = 104; ! %X68 Environmental event interrupt literal IDT$C_PROCESSOR_SPECIFIC_1 = 105; ! %X69 Reserved - processor specific literal IDT$C_SYSTEM_REC_ERROR = 106; ! %X6A System recoverable machine check abort literal IDT$C_PROC_REC_ERROR = 107; ! %X6B Processer recoverable machine check abort literal IDT$C_EXTERNAL_INTERRUPT = 128; ! %X80 External interrupt literal IDT$C_BREAK_SYS = 129; ! %X81 System break (BREAK_DBG is %X40) literal IDT$C_BREAK_APP = 130; ! %X82 Application break literal IDT$C_BREAK_ARCH = 131; ! %X83 Architected break (Intel) literal IDT$C_DEBUG_FAULT = 132; ! %X84 Debug fault literal IDT$C_UNEXPECTED = 133; ! %X85 Unexpected exception or interrupt literal IDT$C_NAT_CONSUMPTION = 134; ! %x86 NaT comsumption fault literal IDT$C_TAKEN_BRANCH = 135; ! %x87 Taken branch trap literal IDT$C_SINGLE_STEP = 136; ! %x88 Single step trap literal IDT$C_IA32_TRAP = 137; ! %X89 IA-32 exception, interrupt, etc literal IDT$C_BREAK_HALT = 138; ! %x8a PAL_HALT equivalent literal IDT$C_BREAK_UNKNOWN = 139; ! %x8b Needs further processing to figure out what kind of break it is ! Probably a bad idea to override this! literal IDT$C_PROBE = 140; ! %x8c Probe VA was not in TLB, emulate literal IDT$C_KSTK_INVALID = 141; ! %x8d An invalid kernel stack was detected. We've switched to slot HWPCB ! and the intstk may not be totally valid literal IDT$C_LOWER_PRIV = 142; ! %x8e We took a lower privilege trap. This may be an ACCVIO from an unimplemented ! virtual address (and the handler needs to check) or a lower priv trap. literal IDT$C_SPARE_1 = 143; ! Leave spares literal IDT$C_SPARE_2 = 144; literal IDT$C_COUNT = 145; ! Number of entry slots. Add new entries before this. !*** MODULE $IFDDEF *** ! + ! IMAGE FILE DESCRIPTOR BLOCK - RETURNED BY IMAGE ACTIVATOR ! - literal IFD$M_EXEONLY = %X'1'; literal IFD$M_PRIV = %X'2'; literal IFD$M_SETVECTOR = %X'4'; literal IFD$K_LENGTH = 28; ! LENGTH OF FIXED AREA OF IFD literal IFD$C_LENGTH = 28; ! LENGTH OF FIXED AREA OF IFD literal IFD$S_IFDDEF = 28; literal IFD$S_IFD = 28; macro IFD$W_SIZE = 0,0,16,0 %; ! SIZE IN BYTES OF IMAGE FILE DESCRIPTOR macro IFD$W_FILNAMOFF = 2,0,16,0 %; ! OFFSET TO ASCIC ! FULLY QUALIFIED FILE SPEC macro IFD$W_CHAN = 8,0,16,0 %; ! CHANNEL ON WHICH IMAGE FILE IS OPEN macro IFD$W_CMCHAN = 10,0,16,0 %; ! COMPATIBILITY MODE CHANNEL macro IFD$L_CMKFIADR = 12,0,32,1 %; ! COMPATIBILITY MODE IMAGE ! KNOWN FILE ENTRY ADDRESS OR 0 macro IFD$W_FLAGS = 16,0,16,0 %; ! IMAGE FILE DESCRIPTOR FLAGS macro IFD$V_EXEONLY = 16,0,1,0 %; ! EXECUTE ONLY FILE macro IFD$V_PRIV = 16,1,1,0 %; ! IMAGE INSTALLED WITH ENHANCED PRIVILEGE macro IFD$V_SETVECTOR = 16,2,1,0 %; ! PRIVILEGED VECTORS TO BE INSTALLED macro IFD$Q_CURPROG = 20,0,0,0 %; literal IFD$S_CURPROG = 8; ! STRING DESCRIPTOR FOR ! FULLY QUALIFIED FILE SPEC OF ! RUNNING PROGRAM !*** MODULE $IFSDEF *** ! ! Definitions for Interruption Function State (IFS - CR23) ! literal IFS$M_IFM = %X'3FFFFFFFFF'; literal IFS$M_MBZ0 = %X'7FFFFFC000000000'; literal IFS$M_V = %X'8000000000000000'; literal IFS$S_IFS = 8; macro IFS$R_IFS_UNION = 0,0,0,0 %; literal IFS$S_IFS_UNION = 8; macro IFS$Q_REGISTER = 0,0,0,0 %; literal IFS$S_REGISTER = 8; macro IFS$V_IFM = 0,0,38,0 %; literal IFS$S_IFM = 38; ! Interruption Frame Marker macro IFS$V_MBZ0 = 4,6,25,0 %; literal IFS$S_MBZ0 = 25; ! Reserved IFS{62:38} (MBZ) macro IFS$V_V = 4,31,1,0 %; ! Valid bit !*** MODULE $IHDDEF *** ! + ! IMAGE HEADER RECORD DEFINITIONS - FIRST RECORD OF IMAGE HEADER ! - literal IHD$K_MAJORID = 12848; ! Major id value literal IHD$K_MINORID = 13616; ! Minor id value literal IHD$K_EXE = 1; ! Executable image literal IHD$K_LIM = 2; ! Linkable image literal IHD$M_LNKDEBUG = %X'1'; literal IHD$M_LNKNOTFR = %X'2'; literal IHD$M_NOP0BUFS = %X'4'; literal IHD$M_PICIMG = %X'8'; literal IHD$M_P0IMAGE = %X'10'; literal IHD$M_DBGDMT = %X'20'; literal IHD$M_INISHR = %X'40'; literal IHD$M_IHSLONG = %X'80'; literal IHD$M_UPCALLS = %X'100'; literal IHD$M_MATCHCTL = %X'7000000'; literal IHD$K_LENGTH = 48; ! Length of fixed area literal IHD$C_LENGTH = 48; ! Length of fixed area literal IHD$C_MINCODE = -1; ! Low bound of ALIAS values literal IHD$C_NATIVE = -1; ! Native mode image literal IHD$C_RSX = 0; ! RSX image produced by TKB literal IHD$C_BPA = 1; ! BASIC plus analog literal IHD$C_ALIAS = 2; ! Last 126 bytes contains ASCIC of image to activate literal IHD$C_CLI = 3; ! Image is a CLI, run LOGINOUT literal IHD$C_PMAX = 4; ! PMAX system image literal IHD$C_ALPHA = 5; ! ALPHA image literal IHD$C_MAXCODE = 5; ! High bound of ALIAS values ! literal IHD$C_GEN_XLNKR = 1; ! Cross linker literal IHD$C_GEN_NATIVE = 2; ! First native mode image header. ! does not have LNKFLAGS, SYSVER and IAFVA fields literal IHD$C_GEN_LNKFLG = 3; ! Native with LNKFLAGS longword added ! does not have SYSVER and IAFVA fields literal IHD$C_GEN_SYSVER = 4; ! Native with LNKFLAGS and SYSVER added ! does not have IAFVA field literal IHD$C_GEN_FIXUP = 5; ! Version III image ! contains LNKFLAGS, SYSVER, and IAFVA fields literal IHD$C_GEN_NEWISD = 6; ! ISD size field is a byte literal IHD$S_IHDDEF = 512; ! Old size name - synonym literal IHD$S_IHD = 512; macro IHD$W_SIZE = 0,0,16,0 %; ! Size in bytes of Image Header record macro IHD$W_ACTIVOFF = 2,0,16,0 %; ! Byte offset to activation data macro IHD$W_SYMDBGOFF = 4,0,16,0 %; ! Byte offset to symbol table and debug data macro IHD$W_IMGIDOFF = 6,0,16,0 %; ! Byte offset to image ident data macro IHD$W_PATCHOFF = 8,0,16,0 %; ! Byte offset to patch data macro IHD$W_VERSION_ARRAY_OFF = 10,0,16,0 %; ! Byte offset to version number array macro IHD$W_MAJORID = 12,0,16,0 %; ! Major id macro IHD$W_MINORID = 14,0,16,0 %; ! Minor id macro IHD$B_HDRBLKCNT = 16,0,8,0 %; ! Count of header blocks macro IHD$B_IMGTYPE = 17,0,8,0 %; ! Image type ! ! IMAGE TYPE CODES ! macro IHD$Q_PRIVREQS = 20,0,0,0 %; literal IHD$S_PRIVREQS = 8; ! Requested privilege mask macro IHD$W_IOCHANCNT = 28,0,16,0 %; ! ! of channels requested ! 0 if default macro IHD$W_IMGIOCNT = 30,0,16,0 %; ! ! of pages of image i/o section requested ! 0 if default macro IHD$R_LNKFLAGS_OVERLAY = 32,0,32,0 %; macro IHD$L_LNKFLAGS = 32,0,32,0 %; ! Linker produced image flags macro IHD$R_LNKFLAGS_BITS = 32,0,32,0 %; macro IHD$V_LNKDEBUG = 32,0,1,0 %; ! Full debugging requested macro IHD$V_LNKNOTFR = 32,1,1,0 %; ! First transfer address missing macro IHD$V_NOP0BUFS = 32,2,1,0 %; ! RMS use of P0 for image i/o disabled macro IHD$V_PICIMG = 32,3,1,0 %; ! Image is position independent macro IHD$V_P0IMAGE = 32,4,1,0 %; ! Image is in P0 space only macro IHD$V_DBGDMT = 32,5,1,0 %; ! Image header has dmt fields macro IHD$V_INISHR = 32,6,1,0 %; ! Transfer array contains valid IHA$L_INISHR macro IHD$V_IHSLONG = 32,7,1,0 %; ! Longword DSTBLKS and GSTRECS valid in IHS$ macro IHD$V_UPCALLS = 32,8,1,0 %; ! Upcalls enabled macro IHD$V_MATCHCTL = 32,24,3,0 %; literal IHD$S_MATCHCTL = 3; ! Match control for linkable image macro IHD$L_IDENT = 36,0,32,0 %; ! GBL SEC ident value for linkable image macro IHD$L_SYSVER = 40,0,32,0 %; ! SYS$K_VERSION or 0 if not linked with exec macro IHD$L_IAFVA = 44,0,32,1 %; ! Relative virtual address of fixup info macro IHD$T_SKIP = 48,0,0,0 %; literal IHD$S_SKIP = 462; ! ALIAS should be last word in 512 byte block macro IHD$W_ALIAS = 510,0,16,0 %; ! Code to use secondary image name ! ***************************************** ! ! Define legal range of ALIAS constants. MINCODE must be equal to the ! lowest value and MAXCODE must be equal to the highest value. ! ! ****************************************** ! ! Generation number returned by IMGSHR IMG$GET_IHD to SYSIMGACT. ! These do not appear in the image header but are inferred from the ! contents of the image header ! !*** MODULE $IHADEF *** ! + ! IMAGE HEADER ACTIVATION SECTION OFFSETS ! - literal IHA$K_LENGTH = 20; ! SIZE OF ACTIVATION SECTION literal IHA$C_LENGTH = 20; ! SIZE OF ACTIVATION SECTION literal IHA$S_IHADEF = 20; literal IHA$S_IHA = 20; macro IHA$L_TFRADR1 = 0,0,32,0 %; ! FIRST TRANSFER ADDRESS macro IHA$L_TFRADR2 = 4,0,32,0 %; ! SECOND TRANSFER ADDRESS macro IHA$L_TFRADR3 = 8,0,32,0 %; ! THIRD TRANSFER ADDRESS macro IHA$L_INISHR = 16,0,32,0 %; ! SHARED IMAGE INITIALIZATION ! (valid if IHD$V_INISHR set) !*** MODULE $IHPDEF *** ! + ! IMAGE HEADER PATCH SECTION OFFSETS ! - literal IHP$K_LENGTH = 44; ! LENGTH OF PATCH HEADER SECTION literal IHP$C_LENGTH = 44; ! LENGTH OF PATCH HEADER SECTION literal IHP$S_IHPDEF = 44; literal IHP$S_IHP = 44; macro IHP$L_ECO1 = 0,0,32,0 %; ! DEC ECO LEVELS 1-32 macro IHP$L_ECO2 = 4,0,32,0 %; ! DEC ECO LEVELS 33-64 macro IHP$L_ECO3 = 8,0,32,0 %; ! DEC ECO LEVELS 65-98 macro IHP$L_ECO4 = 12,0,32,0 %; ! USER ECO LEVELS 99-132 macro IHP$L_RW_PATSIZ = 16,0,32,0 %; ! SIZE OF FREE RW PATCH AREA macro IHP$L_RW_PATADR = 20,0,32,1 %; ! VIR ADDR OF NEXT FREE RW PATCH AREA macro IHP$L_RO_PATSIZ = 24,0,32,0 %; ! SIZE OF FREE RO PATCH AREA macro IHP$L_RO_PATADR = 28,0,32,1 %; ! VIR ADDR OF NEXT FREE RO PATCH AREA macro IHP$L_PATCOMTXT = 32,0,32,0 %; ! PATCH COMMAND TEXT VIRTUAL BLOCK NUMBER macro IHP$Q_PATDATE = 36,0,0,0 %; literal IHP$S_PATDATE = 8; ! DATE OF MOST RECENT PATCH !*** MODULE $IHSDEF *** ! + ! IMAGE HEADER SYMBOL TABLE AND DEBUG SECTION OFFSETS ! - literal IHS$K_LENGTH = 28; ! LENGTH OF SYMBOL TABLE SECTION literal IHS$C_LENGTH = 28; ! LENGTH OF SYMBOL TABLE SECTION literal IHS$S_IHSDEF = 28; literal IHS$S_IHS = 28; macro IHS$L_DSTVBN = 0,0,32,0 %; ! DEBUG SYMBOL TABLE VIRTUAL BLOCK NUMBER macro IHS$L_GSTVBN = 4,0,32,0 %; ! GLOBAL SYMBOL TABLE VIRTUAL BLOCK NUMBER macro IHS$W_DSTBLKS = 8,0,16,0 %; ! DEBUG SYMBOL TABLE BLOCK COUNT macro IHS$W_GSTRECS = 10,0,16,0 %; ! GLOBAL SYMBOL TABLE RECORD COUNT macro IHS$L_DMTVBN = 12,0,32,0 %; ! VBN OF DMT INFORMATION macro IHS$L_DMTBYTES = 16,0,32,0 %; ! LENGTH OF DMT INFO macro IHS$L_DSTBLKS = 20,0,32,1 %; ! Debug symbol table block count -- LONGWORD macro IHS$L_GSTRECS = 24,0,32,1 %; ! Global symbol table record count -- LONGWORD !*** MODULE $IHIDEF *** ! + ! IMAGE HEADER IDENTIFICATION SECTION OFFSETS ! - literal IHI$K_LENGTH = 80; ! LENGTH OF IMAGE HEADER IDENT SECTION literal IHI$C_LENGTH = 80; ! LENGTH OF IMAGE HEADER IDENT SECTION literal IHI$S_IHIDEF = 80; literal IHI$S_IHI = 80; macro IHI$T_IMGNAM = 0,0,0,0 %; literal IHI$S_IMGNAM = 40; ! IMAGE NAME STRING macro IHI$T_IMGID = 40,0,0,0 %; literal IHI$S_IMGID = 16; ! IMAGE IDENT STRING macro IHI$Q_LINKTIME = 56,0,0,0 %; literal IHI$S_LINKTIME = 8; ! DATE AND TIME THIS IMAGE WAS LINKED ! STANDARD SYSTEM QUADWORD FORMAT macro IHI$T_LINKID = 64,0,0,0 %; literal IHI$S_LINKID = 16; ! LINKER IDENT STRING !*** MODULE $IHVNDEF *** literal IHVN$M_SUBVERSION_MINOR_ID = %X'FFFF'; literal IHVN$M_SUBVERSION_MAJOR_ID = %X'FFFF0000'; literal IHVN$S_IMG_VERSION_ARRAY = 8; macro IHVN$L_SUBSYSTEM_MASK = 0,0,32,0 %; ! Bit mask of nonzero version numbers macro IHVN$L_SUBVERSION_ARRAY = 4,0,32,0 %; ! First array element macro IHVN$V_SUBVERSION_MINOR_ID = 4,0,16,0 %; literal IHVN$S_SUBVERSION_MINOR_ID = 16; ! Minor ID for each component macro IHVN$V_SUBVERSION_MAJOR_ID = 4,16,16,0 %; literal IHVN$S_SUBVERSION_MAJOR_ID = 16; ! Major ID for each component literal IHVN$M_VERSION_MINOR_ID = %X'FFFFFF'; literal IHVN$M_VERSION_MAJOR_ID = %X'FF000000'; literal IHVN$S_IMG_OVERALL_VERSION = 4; macro IHVN$V_VERSION_MINOR_ID = 0,0,24,0 %; literal IHVN$S_VERSION_MINOR_ID = 24; ! Minor ID of SYS.STB macro IHVN$V_VERSION_MAJOR_ID = 0,24,8,0 %; literal IHVN$S_VERSION_MAJOR_ID = 8; ! Major ID of SYS.STB literal IHVN$K_LENGTH = 132; literal IHVN$C_LENGTH = 132; !*** MODULE $IHXDEF *** ! + ! IMAGE HEADER RECORD DEFINITIONS - CROSS LINKER - MAJORID = "01" ! 1ST RECORD OF IMAGE HEADER BLOCK ! - literal IHX$K_MAJORID = 12592; ! ^A/01/ MAJOR ID VALUE FOR CROSS LINKER literal IHX$K_MINORID = 12592; ! ^A/01/ MINOR ID VALUE FOR CROSS LINKER literal IHX$K_MINORID1 = 12592; ! ^A/01/ MINOR ID VALUE FOR CROSS LINKER WITH ! SYMBOL TABLE AND 3RD TRANSFER ADR literal IHX$K_LENGTH = 56; ! LENGTH OF CROSS LINKER HEADER literal IHX$C_LENGTH = 56; ! LENGTH OF CROSS LINKER HEADER literal IHX$S_IHXDEF = 56; literal IHX$S_IHX = 56; macro IHX$W_SIZE = 0,0,16,0 %; ! SIZE IN BYTE OF IMAGE HEADER RECORD macro IHX$B_HDRBLKCNT = 2,0,8,0 %; ! COUNT OF BLOCKS IN IMAGE HEADER macro IHX$Q_STARTADR = 4,0,0,0 %; literal IHX$S_STARTADR = 8; ! START ADDRESS macro IHX$W_MAJORID = 12,0,16,0 %; ! MAJOR ID OF IMAGE HEADER macro IHX$W_MINORID = 14,0,16,0 %; ! MINOR ID OF IMAGE HEADER macro IHX$T_IMGNAM = 16,0,0,0 %; literal IHX$S_IMGNAM = 24; ! IMAGE NAME ! ! THE FOLLOWING FIELDS ARE PRESENT FOR MINOR ID'S GREATER OR EQUAL TO "03" ! macro IHX$L_DSTVBN = 40,0,32,0 %; ! DEBUG SYMBOL TABLE VBN macro IHX$L_GSTVBN = 44,0,32,0 %; ! GLOBAL SYMBOL TABLE VBN macro IHX$W_DSTBLKS = 48,0,16,0 %; ! DEBUG SYMBOL TABLE BLOCKS macro IHX$W_GSTRECS = 50,0,16,0 %; ! GLOBAL SYMBOL TABLE RECORD COUNT macro IHX$L_TFRADR3 = 52,0,32,0 %; ! THIRD TRANSFER ADDRESS !*** MODULE $IMCBDEF *** literal IMCB$K_MAIN_PROGRAM = 1; ! Object of RUN command literal IMCB$K_MERGED_IMAGE = 2; ! Additional image mapped literal IMCB$K_GLOBAL_IMAGE_SECTION = 3; ! Image described by global ISD literal IMCB$M_EXPREG = %X'1'; literal IMCB$M_SHAREABLE = %X'2'; literal IMCB$M_OPEN_FOR_WRITE = %X'4'; literal IMCB$M_RES_HEADER = %X'8'; literal IMCB$M_LOAD_IMAGE = %X'10'; literal IMCB$M_INITIALIZE = %X'20'; literal IMCB$M_DONE = %X'40'; literal IMCB$M_SYS_STB = %X'80'; literal IMCB$M_IN_CIRCULARITY = %X'100'; literal IMCB$M_MAPPED = %X'200'; literal IMCB$M_PROTECTED = %X'400'; literal IMCB$M_PARENT_PROT = %X'800'; literal IMCB$M_CMOD_VECTOR_MAPPED = %X'1000'; literal IMCB$M_XLATED = %X'2000'; literal IMCB$M_PROTSECT = %X'4000'; literal IMCB$M_NOTPROTSECT = %X'8000'; literal IMCB$M_DISCONTIGUOUS = %X'10000'; literal IMCB$M_FORKABLE = %X'20000'; literal IMCB$M_COMPRESS_DATASEC = %X'40000'; literal IMCB$M_VERSION_SAFE = %X'80000'; literal IMCB$M_PRIMARY_FIX = %X'100000'; literal IMCB$M_DATA_RESIDENT = %X'200000'; literal IMCB$M_SHARE_LINK = %X'400000'; literal IMCB$M_AUTOACT = %X'800000'; literal IMCB$M_MKTHREADS = %X'1000000'; literal IMCB$M_UPCALLS = %X'2000000'; literal IMCB$M_SYSTEM_IMAGE = %X'4000000'; literal IMCB$M_PERM = %X'8000000'; literal IMCB$M_RELOCATE = %X'10000000'; literal IMCB$M_MATCH_CONTROL = %X'7'; literal IMCB$M_MINOR_ID = %X'FFFFFF'; literal IMCB$M_MAJOR_ID = %X'FF000000'; literal IMCB$C_LENGTH = 292; ! Length of IMCB literal IMCB$K_LENGTH = 292; ! Length of IMCB literal IMCB$S_IMCB$DEF = 292; ! Old size name - synonym literal IMCB$S_IMCB = 296; macro IMCB$L_FLINK = 0,0,32,1 %; ! Forward link in list macro IMCB$L_BLINK = 4,0,32,1 %; ! Backward link in list macro IMCB$W_SIZE = 8,0,16,0 %; ! Size of IMCB in bytes macro IMCB$B_TYPE = 10,0,8,0 %; ! Structure type for IMCB (DYN$C_PGD) macro IMCB$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype for IMCB (DYN$C_IMCB) macro IMCB$B_ACCESS_MODE = 12,0,8,0 %; ! Access mode of image macro IMCB$B_ACT_CODE = 13,0,8,0 %; ! Activation code macro IMCB$W_CHAN = 14,0,16,0 %; ! Channel on which image file is opened macro IMCB$L_FLAGS = 16,0,32,0 %; ! Name attributes macro IMCB$V_EXPREG = 16,0,1,0 %; ! Image mapped at end of address space macro IMCB$V_SHAREABLE = 16,1,1,0 %; ! Image installed /SHAREABLE macro IMCB$V_OPEN_FOR_WRITE = 16,2,1,0 %; ! Image will be opened for write macro IMCB$V_RES_HEADER = 16,3,1,0 %; ! Image header already decoded macro IMCB$V_LOAD_IMAGE = 16,4,1,0 %; ! Load image from sequential device macro IMCB$V_INITIALIZE = 16,5,1,0 %; ! Image contains initialization code macro IMCB$V_DONE = 16,6,1,0 %; ! Image is completely activated macro IMCB$V_SYS_STB = 16,7,1,0 %; ! Image is linked against SYS.STB macro IMCB$V_IN_CIRCULARITY = 16,8,1,0 %; ! Image is involved in an image circularity macro IMCB$V_MAPPED = 16,9,1,0 %; ! Image is mapped in address space macro IMCB$V_PROTECTED = 16,10,1,0 %; ! Image installed protected macro IMCB$V_PARENT_PROT = 16,11,1,0 %; ! Parent image installed protected macro IMCB$V_CMOD_VECTOR_MAPPED = 16,12,1,0 %; ! Change mode vectors already mapped macro IMCB$V_XLATED = 16,13,1,0 %; ! Image is a translated VAX image macro IMCB$V_PROTSECT = 16,14,1,0 %; ! Image contains some protected sections macro IMCB$V_NOTPROTSECT = 16,15,1,0 %; ! Image does not contain some protected sections macro IMCB$V_DISCONTIGUOUS = 16,16,1,0 %; ! Some image sections are resident macro IMCB$V_FORKABLE = 16,17,1,0 %; ! Protected image allows POSIX fork() macro IMCB$V_COMPRESS_DATASEC = 16,18,1,0 %; ! Data sections will be laid out one after another ! Flag is only meaningful if DISCONTIGUOUS bit is set macro IMCB$V_VERSION_SAFE = 16,19,1,0 %; ! Image is exempt from system version checks macro IMCB$V_PRIMARY_FIX = 16,20,1,0 %; ! Image has had primary fixups performed on it macro IMCB$V_DATA_RESIDENT = 16,21,1,0 %; ! Image has it's read-only data sections placed in ! the data granularity hint region. macro IMCB$V_SHARE_LINK = 16,22,1,0 %; ! Image was installed with shareable linkage macro IMCB$V_AUTOACT = 16,23,1,0 %; ! Image is being automatically activated (currently ! this is just SYS$SSISHR). Certain errors in ! activation can, and should, be ignored. macro IMCB$V_MKTHREADS = 16,24,1,0 %; ! Multiple kernel threads enabled macro IMCB$V_UPCALLS = 16,25,1,0 %; ! Upcalls enabled macro IMCB$V_SYSTEM_IMAGE = 16,26,1,0 %; ! image is SYS$BASE_IMAGE or SYS$PUBLIC_VECTORS macro IMCB$V_PERM = 16,27,1,0 %; ! image is permanent. macro IMCB$V_RELOCATE = 16,28,1,0 %; ! image relocations [to be/have been] applied ! The image name is stored as a counted ASCII string. macro IMCB$T_IMAGE_NAME = 20,0,0,0 %; literal IMCB$S_IMAGE_NAME = 40; ! Name string (counted ASCII) macro IMCB$L_SYMBOL_VECTOR_SIZE = 60,0,32,0 %; ! Entries in symbol vector. macro IMCB$Q_IDENT = 64,0,0,0 %; literal IMCB$S_IDENT = 8; macro IMCB$L_MATCH_CONTROL = 64,0,32,0 %; macro IMCB$V_MATCH_CONTROL = 64,0,3,0 %; literal IMCB$S_MATCH_CONTROL = 3; macro IMCB$L_VERSION = 68,0,32,0 %; macro IMCB$V_MINOR_ID = 68,0,24,0 %; literal IMCB$S_MINOR_ID = 24; macro IMCB$V_MAJOR_ID = 68,24,8,0 %; literal IMCB$S_MAJOR_ID = 8; macro IMCB$Q_ADDRESS_RANGE = 72,0,0,0 %; literal IMCB$S_ADDRESS_RANGE = 8; macro IMCB$L_STARTING_ADDRESS = 72,0,32,1 %; macro IMCB$L_END_ADDRESS = 76,0,32,1 %; macro IMCB$L_IHD = 80,0,32,1 %; ! Address of IHD for image macro IMCB$L_KFE = 84,0,32,1 %; ! Address of KFE for image macro IMCB$L_CONTEXT = 88,0,32,1 %; ! Address of context block macro IMCB$L_BASE_ADDRESS = 92,0,32,1 %; ! Base address at which image is mapped macro IMCB$L_INITIALIZE = 96,0,32,1 %; ! Address of initialization code macro IMCB$L_ACTIVE_SONS = 100,0,32,0 %; ! Count of not yet mapped son images ! Valid only during activation macro IMCB$PS_FIXUP_VECTOR_ADDRESS = 104,0,32,1 %; macro IMCB$PS_SYMBOL_VECTOR_ADDRESS = 112,0,32,1 %; macro IMCB$PS_PLV_ADDRESS = 120,0,32,1 %; macro IMCB$PS_CMOD_KERNEL_ADDRESS = 128,0,32,1 %; macro IMCB$PS_CMOD_EXEC_ADDRESS = 136,0,32,1 %; macro IMCB$PS_SSI_PLV = 144,0,32,1 %; macro IMCB$L_KFERES_PTR = 152,0,32,1 %; ! Pointer to resident section description ! The global section name of a shareable image is stored as a counted ASCII string. macro IMCB$T_LOG_IMAGE_NAME = 156,0,0,0 %; literal IMCB$S_LOG_IMAGE_NAME = 40; ! Name string (counted ASCII) macro IMCB$T_DVI = 196,0,0,0 %; literal IMCB$S_DVI = 16; ! device id macro IMCB$W_FID = 212,0,0,0 %; literal IMCB$S_FID = 6; ! file id macro IMCB$B_RISIG = 218,0,0,1 %; literal IMCB$S_RISIG = 32; ! image signiture macro IMCB$L_KFERES64_PTR = 252,0,32,1 %; ! Pointer to 64-bit resident section descs macro IMCB$PQ_STARTING_ADDRESS_64 = 256,0,0,1 %; literal IMCB$S_STARTING_ADDRESS_64 = 8; ! Start addr of 64-bit image VA macro IMCB$PQ_END_ADDRESS_64 = 264,0,0,1 %; literal IMCB$S_END_ADDRESS_64 = 8; ! End addr of 64-bit image VA macro IMCB$Q_LINKTIME = 272,0,0,0 %; literal IMCB$S_LINKTIME = 8; ! link time macro IMCB$L_LDRIMG = 280,0,32,1 %; ! pointer to loaded image structure macro IMCB$L_PROT_IMAGE_FLINK = 284,0,32,1 %; ! Forward link in list of protected images macro IMCB$L_LKWSET_COUNT = 288,0,32,1 %; ! Count of times image has been locked in WS ! ! Define the layout of the page header for locked-down image activator ! pool within P1 pool ! literal IMGACT_POOL$K_LENGTH = 16; ! Length of IMGACT_POOL literal IMGACT_POOL$S_IMGACT_POOL = 16; macro IMGACT_POOL$L_FLINK = 0,0,32,1 %; ! Forward link in list macro IMGACT_POOL$L_BLINK = 4,0,32,1 %; ! Backward link in list macro IMGACT_POOL$W_SIZE = 8,0,16,0 %; ! Size of IMGACT_POOL in bytes (multiple of pages) macro IMGACT_POOL$B_TYPE = 10,0,8,0 %; ! Structure type for IMGACT_POOL (DYN$C_PGD) macro IMGACT_POOL$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype for IMGACT_POOL (DYN$C_IMGACT_POOL) macro IMGACT_POOL$L_FREE_LIST = 12,0,32,1 %; ! Header for free list (first IMGACT_POOL only) !*** MODULE $IMPDEF *** ! + ! RMS32 IMPURE AREA OFFSET DEFINITIONS ! ! - literal IMP$C_ASYEFN = 30; ! EFN FOR ASYNC WAITS literal IMP$C_IOREFN = 30; ! EFN FOR IO RUNDOWN SYNCHRONIZATION literal IMP$C_ASYQIOEFN = 31; ! EFN FOR ASYNC QIOS literal IMP$C_SYNCEFN = 27; ! BASE EFN FOR SYNCHRONOUS QIO'S ! (28, 29 ALSO USED) literal IMP$C_MBXEFN = 26; ! EFN FOR QIOS TO NETWORK MAILBOXES ! literal IMP$C_NPIOFILES = 63; ! ! OF PIO SEGMENT FILES literal IMP$C_ENTPERSEG = 15; ! ! OF IIO SEGMENT SLOTS ! PER INDEX TABLE SEGMENT literal IMP$S_IMPDEF = 112; literal IMP$S_IMP = 112; macro IMP$W_RMSSTATUS = 0,0,16,0 %; ! RMS OVERALL STATUS macro IMP$V_IIOS = 0,0,1,0 %; ! SET IF THIS IS THE IMAGE ! I.O SEGMENT macro IMP$V_AST = 0,1,1,0 %; ! SET IF RUNNING AT EXEC AST LEVEL macro IMP$V_TEMP1 = 0,2,1,0 %; ! TEMPORARY FLAG macro IMP$V_TEMP2 = 0,3,1,0 %; ! " macro IMP$V_IORUNDOWN = 0,4,1,0 %; ! SET IF IO RUNDOWN IN PROGRESS macro IMP$V_NOP0BUFS = 0,5,1,0 %; ! SET IF RMS USE OF P0 FOR IMAGE I/O DISABLED macro IMP$V_RUH = 0,6,1,0 %; ! Set if within RMS RU Handler macro IMP$V_RECOVERY = 0,7,1,0 %; ! SET IF RECOVERY IN PROGRESS macro IMP$V_RUH_SYNCH = 0,8,1,0 %; ! SET IF RMS IO MUST SYNCH ! WITH THE RU HANDLER ! macro IMP$B_PROT = 2,0,8,0 %; ! PROTECTION FOR I/O BUFFER PAGES macro IMP$L_IOSEGADDR = 4,0,32,1 %; ! ADDRESS OF FIRST FREE PAGE ! IN THIS (IMAGE OR PROCESS) ! I/O SEGMENT macro IMP$L_IOSEGLEN = 8,0,32,0 %; ! ! OF FREE BYTES AT ABOVE ADDR macro IMP$L_FREEPGLH = 12,0,0,1 %; literal IMP$S_FREEPGLH = 8; ! FREE PAGE LIST HEAD macro IMP$L_SAVED_SP = 20,0,32,0 %; ! SAVED VALUE OF SP AT ENTRY macro IMP$L_IFABTBL = 24,0,32,1 %; ! IFAB TABLE ADDR macro IMP$L_IRABTBL = 28,0,32,1 %; ! IRAB TABLE ADDR macro IMP$W_ENTPERSEG = 32,0,16,0 %; ! ! OF SLOTS PER TABLE SEGMENT macro IMP$W_NUM_IFABS = 34,0,16,0 %; ! NUMBER OF IFABS & IRABS CURRENTLY ALLOCATED macro IMP$L_ASB_LOOKASIDE_LIST = 36,0,0,1 %; literal IMP$S_ASB_LOOKASIDE_LIST = 8; ! ASB LOOKASIDE LIST HEAD macro IMP$L_IFBTBLINK = 44,0,32,1 %; ! START OF IFAB TABLE (LINK TO NEXT SEGMENT) macro IMP$L_IRBTBLINK = 108,0,32,1 %; ! START OF IRAB TABLE (LINK TO NEXT SEGMENT) !*** MODULE $INDICTINTDEF *** ! Include base definitions ! + ! This is the internal to VMS defintion file [LIB] used with the component ! indictment server software pieces. ! ! **** NOTE **** ! ! These constants are a direct conversion of Compaq Analyse's or should ! I say Tru64 UNIX's indict.h file. ! If any changes are done in that file then this file should be ! adjusted to match it. ! - ! ! ! The urgency value represents the seriousness of the problem. ! The higher the urgency, the more serious the problem. literal INDICT$k_MIN_URGENCY = 1; literal INDICT$k_MAX_URGENCY = 10; ! ! The probability value represents the likelihood that the indicted ! component is the culprit. The higher the probability the more ! likely the initiator of the indictment notification believes the ! indicted component is the source of the errors. literal INDICT$k_MIN_PROBABILITY = 1; literal INDICT$k_MAX_PROBABILITY = 100; ! ! The total_indictments value represents the number of components ! being indicted for the same error. In some cases, the indictment ! initiator isn't 100% sure which component needs to be replaced, ! so the initiator will indict more than one component. For the ! case where two components get indicted for the same error, the ! total_indictments should be set to 2. literal INDICT$k_MIN_INDICTMENTS = 1; literal INDICT$k_MAX_INDICTMENTS = 10; ! ! The reason for the indictment contains up to this ! many characters including the null terminator. literal INDICT$k_MAX_DESCR = 256; ! ! The initiator of the indictment request. This is the requestor's name ! and may contain up to this many characters including the null terminator. literal INDICT$k_MAX_INITIATOR = 32; ! ! The report handle contains up to this many characters including ! the null terminator. This is the requesting report program name(s). literal INDICT$k_MAX_REPORT_HNDL = 128; ! ! The version number for indictment Info structure. ! This is set by the caller. literal INDICT$k_VERSION_1 = 1; ! ! ! List of objects that can be indicted. If new object types get added ! to the enum type then place in between INDICT_COMPONENT and ! INDICT_OS_SPECIFIC since the validation code in sys_indict_Object API ! uses these values as the min and max. ! literal INDICT$k_COMPONENT = 0; ! FRU Config ID of component indicted literal INDICT$k_PFN = 1; ! Page Frame Number to be indicted literal INDICT$k_OS_SPECIFIC = 2; ! OS HWR ID component to be indicted literal INDICTREQ$S_INDICTREQUEST = 640; macro INDICTREQ$PS_QFL = 0,0,32,1 %; macro INDICTREQ$PS_QBL = 4,0,32,1 %; macro INDICTREQ$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro INDICTREQ$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE CODE macro INDICTREQ$B_SUBTYPE = 11,0,8,0 %; ! STRUCTURE SUB-TYPE CODE macro INDICTREQ$PQ_IOSB_ADDRESS = 12,0,0,1 %; literal INDICTREQ$S_IOSB_ADDRESS = 8; ! IOSB macro INDICTREQ$L_EFN = 20,0,32,0 %; ! Event Flag macro INDICTREQ$L_STATUS = 24,0,32,0 %; ! Status macro INDICTREQ$R_BASE_ACB = 32,0,0,0 %; literal INDICTREQ$S_BASE_ACB = 64; ! Embedded ACB64 structure macro INDICTREQ$L_VERSION = 96,0,32,0 %; ! Version of Indictment Data macro INDICTREQ$L_OBJECT_TYPE = 100,0,32,0 %; ! Type of indictment macro INDICTREQ$Q_PFN_OR_OS_HANDLE = 104,0,0,0 %; literal INDICTREQ$S_PFN_OR_OS_HANDLE = 8; ! Failing PFN or OS HWR ID macro INDICTREQ$IQ_COMPONENT_ID = 112,0,0,0 %; literal INDICTREQ$S_COMPONENT_ID = 8; ! Component Handle ID macro INDICTREQ$B_COMPONENT_TYPE = 120,0,8,0 %; ! Component Handle Type macro INDICTREQ$B_COMPONENT_SUBTYPE = 121,0,8,0 %; ! Component Handle Subtype macro INDICTREQ$IQ_MODULE_ID = 128,0,0,0 %; literal INDICTREQ$S_MODULE_ID = 8; ! Module Handle ID macro INDICTREQ$B_MODULE_TYPE = 136,0,8,0 %; ! Module Handle Type macro INDICTREQ$B_MODULE_SUBTYPE = 137,0,8,0 %; ! Module Handle Subtype macro INDICTREQ$L_URGENCY = 144,0,32,0 %; ! Urgency of indictment request macro INDICTREQ$L_PROBABILITY = 148,0,32,0 %; ! Probability of correct fault macro INDICTREQ$L_TOTAL_INDICTMENTS = 152,0,32,0 %; ! Total number to be indicted macro INDICTREQ$L_DESCRIPTION_SIZE = 156,0,32,0 %; ! Size of descriptor string macro INDICTREQ$L_INITIATOR_SIZE = 160,0,32,0 %; ! Size of initiator string macro INDICTREQ$L_REPORT_HANDLE_SIZE = 164,0,32,0 %; ! Size of report handle string macro INDICTREQ$B_DESCRIPTION = 168,0,0,1 %; literal INDICTREQ$S_DESCRIPTION = 256; ! Readable description of problem macro INDICTREQ$B_INITIATOR = 432,0,0,1 %; literal INDICTREQ$S_INITIATOR = 32; ! Who called us macro INDICTREQ$B_REPORT_HANDLE = 472,0,0,1 %; literal INDICTREQ$S_REPORT_HANDLE = 128; ! report handle program name literal INDICT$S_INDICTDEF = 24; macro INDICT$PS_REQUEST_QFL = 0,0,32,1 %; macro INDICT$PS_REQUEST_QBL = 4,0,32,1 %; macro INDICT$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro INDICT$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE CODE macro INDICT$B_SUBTYPE = 11,0,8,0 %; ! STRUCTURE SUB-TYPE CODE macro INDICT$PS_LOCK = 12,0,32,1 %; ! Lock for access to queue macro INDICT$L_SERVER = 16,0,32,1 %; ! Indictment server flag macro INDICT$L_QUE_COUNT = 20,0,32,1 %; ! amount of indictment que entries !*** MODULE INIRTNDEF *** literal INIRTN$M_CALLED = %X'1'; literal INIRTN$M_NO_RECALL = %X'2'; literal INIRTN$S_INIRTNDEF = 4; ! Old size name - synonym literal INIRTN$S_INIRTN = 4; macro INIRTN$V_CALLED = 0,0,1,0 %; ! Routine has been called already macro INIRTN$V_NO_RECALL = 0,1,1,0 %; ! Routine is not to be recalled !*** MODULE $INTSTKDEF *** ! Verified for IA64 port - WBF ! ! Interrupt stack - this defines the interrupt frame, which will be on the kernel ! or interrupt stack on IPF by the time any OS interrupt handlers are called. It ! is created on the memory stack by the code in SWIS_EXCEPTION.S ! literal INTSTK$M_AST_MFL = %X'1'; literal INTSTK$M_AST_MFH = %X'2'; literal INTSTK$M_AST_PSR_MFL = %X'4'; literal INTSTK$M_AST_PSR_MFH = %X'8'; literal INTSTK$M_AST_CALLED = %X'10'; literal INTSTK$M_AST_PSR_DFL = %X'20'; literal INTSTK$M_AST_PSR_DFH = %X'40'; literal INTSTK$M_IIB_VALID = %X'80'; literal INTSTK$S_INTSTK = 768; macro INTSTK$B_FLAGS = 0,0,8,0 %; macro INTSTK$R_FLAG_BITS = 0,0,8,0 %; macro INTSTK$V_AST_MFL = 0,0,1,0 %; ! F12-F15 have been saved in AST_Fxx fields below macro INTSTK$V_AST_MFH = 0,1,1,0 %; ! Upper floating regs have been saved in a separate structure following this one macro INTSTK$V_AST_PSR_MFL = 0,2,1,0 %; ! Saved PSR.mfl bit macro INTSTK$V_AST_PSR_MFH = 0,3,1,0 %; ! Saved PSR.mfh bit macro INTSTK$V_AST_CALLED = 0,4,1,0 %; ! ASTDEL has been called at least once with this frame macro INTSTK$V_AST_PSR_DFL = 0,5,1,0 %; ! Saved PSR.dfl bit macro INTSTK$V_AST_PSR_DFH = 0,6,1,0 %; ! Saved PSR.dfh bit macro INTSTK$V_IIB_VALID = 0,7,1,0 %; ! Was there an IIB register saved? macro INTSTK$B_PPREVMODE = 1,0,8,0 %; ! Save interrupted context's PREVMODE macro INTSTK$B_PREVSTACK = 2,0,8,0 %; ! What mode of stack (register and memory) do we return to? ! Note: The OS must prevent interruptions any time the register ! stack and memory stack are different modes macro INTSTK$B_IPL = 3,0,8,0 %; ! SWIS IPL state macro INTSTK$L_STKALIGN = 4,0,32,0 %; ! How much allocated on this stack for int frame? Guaranteed that ! STKALIGN & 0XFFF0 is the actual length of the structure. In other ! words, the structure is always allocated on a 16-byte boundary is ! is a multiple of 16-bytes long. macro INTSTK$W_NATMASK = 8,0,16,0 %; ! Mask of bits 3-9 of the interrupt frame when ! it was created. This shows the mapping ! between UNAT bits and registers. Used to calculate ! how to change the NAT save if interrupt frame is moved macro INTSTK$B_TYPE = 10,0,8,0 %; ! Make this structure look like a standard VMS structure macro INTSTK$B_SUBTYPE = 11,0,8,0 %; macro INTSTK$L_TRAP_TYPE = 12,0,32,1 %; ! Trap type macro INTSTK$Q_IIP = 16,0,0,0 %; literal INTSTK$S_IIP = 8; ! Interruption Instr. Pointer (CR19) ! ! Register Stack Information ! macro INTSTK$Q_RSC = 24,0,0,0 %; literal INTSTK$S_RSC = 8; ! Register Stack Control register macro INTSTK$Q_BSP = 32,0,0,0 %; literal INTSTK$S_BSP = 8; ! Backing store pointer macro INTSTK$Q_BSPSTORE = 40,0,0,0 %; literal INTSTK$S_BSPSTORE = 8; ! User BSP store pointer for next spill macro INTSTK$Q_RNAT = 48,0,0,0 %; literal INTSTK$S_RNAT = 8; ! RNAT register macro INTSTK$Q_BSPBASE = 56,0,0,0 %; literal INTSTK$S_BSPBASE = 8; ! Base of backing store for the inner mode (used for loadrs) macro INTSTK$Q_PFS = 64,0,0,0 %; literal INTSTK$S_PFS = 8; ! Previous function state ! ! Bookkeeping Info ! macro INTSTK$Q_CONTEXT = 72,0,0,0 %; literal INTSTK$S_CONTEXT = 8; ! Opaque context left by trap handler to speed ! processing on the way out. If the interrupt frame is ! moved or if the return will be from a different mode, ! this quadword must be cleared. macro INTSTK$Q_AST_F12 = 80,0,0,0 %; literal INTSTK$S_AST_F12 = 16; ! f12 - temporary FP register; sometimes saved by AST macro INTSTK$Q_AST_F13 = 96,0,0,0 %; literal INTSTK$S_AST_F13 = 16; ! f13 - temporary FP register; sometimes saved by AST macro INTSTK$Q_AST_F14 = 112,0,0,0 %; literal INTSTK$S_AST_F14 = 16; ! f14 - temporary FP register; sometimes saved by AST macro INTSTK$Q_AST_F15 = 128,0,0,0 %; literal INTSTK$S_AST_F15 = 16; ! f15 - temporary FP register; sometimes saved by AST ! End of overlay between Interrupt Frame and System Service Entry structures macro INTSTK$Q_FPSR = 144,0,0,0 %; literal INTSTK$S_FPSR = 8; ! Floating point status register macro INTSTK$B_INTERRUPT_DEPTH = 152,0,8,1 %; ! Keep track of interrupt depth macro INTSTK$W_CPU_NUM = 154,0,16,1 %; ! What CPU number was interrupted (for external I/O) macro INTSTK$Q_PREDS = 160,0,0,0 %; literal INTSTK$S_PREDS = 8; ! Predication registers ! ! Interrupt resources ! macro INTSTK$Q_IPSR = 168,0,0,0 %; literal INTSTK$S_IPSR = 8; ! Interruption Processor Status (CR16) macro INTSTK$Q_ISR = 176,0,0,0 %; literal INTSTK$S_ISR = 8; ! Interruption Status Register (CR17) macro INTSTK$Q_CR18 = 184,0,0,0 %; literal INTSTK$S_CR18 = 8; ! Reserved control register macro INTSTK$Q_IFA = 192,0,0,0 %; literal INTSTK$S_IFA = 8; ! Interruption Fault Address (CR20) macro INTSTK$Q_ITIR = 200,0,0,0 %; literal INTSTK$S_ITIR = 8; ! Interruption TLB Insertion Register (CR21) macro INTSTK$Q_IIPA = 208,0,0,0 %; literal INTSTK$S_IIPA = 8; ! Interruption immediate register (CR22) macro INTSTK$Q_IFS = 216,0,0,0 %; literal INTSTK$S_IFS = 8; ! Interruption Function State (CR23) macro INTSTK$Q_IIM = 224,0,0,0 %; literal INTSTK$S_IIM = 8; ! Interruption immediate (CR24) macro INTSTK$Q_IHA = 232,0,0,0 %; literal INTSTK$S_IHA = 8; ! Interruption Hash Address (CR25) ! ! Application register state ! macro INTSTK$Q_UNAT = 240,0,0,0 %; literal INTSTK$S_UNAT = 8; ! User NAT collection register macro INTSTK$Q_CCV = 248,0,0,0 %; literal INTSTK$S_CCV = 8; ! CCV register macro INTSTK$Q_DCR = 256,0,0,0 %; literal INTSTK$S_DCR = 8; ! Default control register macro INTSTK$Q_LC = 264,0,0,0 %; literal INTSTK$S_LC = 8; ! Loop counter macro INTSTK$Q_EC = 272,0,0,0 %; literal INTSTK$S_EC = 8; ! Epilogue counter (preserved, not saved by interrupt) macro INTSTK$Q_NATS = 280,0,0,0 %; literal INTSTK$S_NATS = 8; ! NATs for registers saved in this structure ! ! Volatile and preserved integer registers. We need to preserve the preserved regs ! not so much to save their values, but to save their NATs ! macro INTSTK$Q_REGBASE = 288,0,0,0 %; literal INTSTK$S_REGBASE = 8; ! Used to index into registers macro INTSTK$Q_CSD = 288,0,0,0 %; literal INTSTK$S_CSD = 8; ! R0 not used, so put CSD register here macro INTSTK$Q_GP = 296,0,0,0 %; literal INTSTK$S_GP = 8; ! r1 - Used as global pointer macro INTSTK$Q_R2 = 304,0,0,0 %; literal INTSTK$S_R2 = 8; ! r2 - temporary register macro INTSTK$Q_R3 = 312,0,0,0 %; literal INTSTK$S_R3 = 8; ! r3 - temporary register macro INTSTK$Q_R4 = 320,0,0,0 %; literal INTSTK$S_R4 = 8; ! r4 - preserved register (not saved by interrupt) macro INTSTK$Q_R5 = 328,0,0,0 %; literal INTSTK$S_R5 = 8; ! r5 - preserved register (not saved by interrupt) macro INTSTK$Q_R6 = 336,0,0,0 %; literal INTSTK$S_R6 = 8; ! r6 - preserved register (not saved by interrupt) macro INTSTK$Q_R7 = 344,0,0,0 %; literal INTSTK$S_R7 = 8; ! r7 - preserved register (not saved by interrupt) macro INTSTK$Q_R8 = 352,0,0,0 %; literal INTSTK$S_R8 = 8; ! r8 - return value macro INTSTK$Q_R9 = 360,0,0,0 %; literal INTSTK$S_R9 = 8; ! r9 - argument pointer macro INTSTK$Q_R10 = 368,0,0,0 %; literal INTSTK$S_R10 = 8; ! r10 - temporary register macro INTSTK$Q_R11 = 376,0,0,0 %; literal INTSTK$S_R11 = 8; ! r11 - temporary register macro INTSTK$Q_SSD = 384,0,0,0 %; literal INTSTK$S_SSD = 8; ! SP is actually saved in IPRs. Use this space so NaTs line up. SSD is a future register macro INTSTK$Q_R13 = 392,0,0,0 %; literal INTSTK$S_R13 = 8; ! r13 - Thread Pointer macro INTSTK$Q_R14 = 400,0,0,0 %; literal INTSTK$S_R14 = 8; ! r14 - temporary register macro INTSTK$Q_R15 = 408,0,0,0 %; literal INTSTK$S_R15 = 8; ! r15 - temporary register macro INTSTK$Q_R16 = 416,0,0,0 %; literal INTSTK$S_R16 = 8; ! r16 - temporary register macro INTSTK$Q_R17 = 424,0,0,0 %; literal INTSTK$S_R17 = 8; ! r17 - temporary register macro INTSTK$Q_R18 = 432,0,0,0 %; literal INTSTK$S_R18 = 8; ! r18 - temporary register macro INTSTK$Q_R19 = 440,0,0,0 %; literal INTSTK$S_R19 = 8; ! r19 - temporary register macro INTSTK$Q_R20 = 448,0,0,0 %; literal INTSTK$S_R20 = 8; ! r20 - temporary register macro INTSTK$Q_R21 = 456,0,0,0 %; literal INTSTK$S_R21 = 8; ! r21 - temporary register macro INTSTK$Q_R22 = 464,0,0,0 %; literal INTSTK$S_R22 = 8; ! r22 - temporary register macro INTSTK$Q_R23 = 472,0,0,0 %; literal INTSTK$S_R23 = 8; ! r23 - temporary register macro INTSTK$Q_R24 = 480,0,0,0 %; literal INTSTK$S_R24 = 8; ! r24 - temporary register macro INTSTK$Q_R25 = 488,0,0,0 %; literal INTSTK$S_R25 = 8; ! r25 - temporary register macro INTSTK$Q_R26 = 496,0,0,0 %; literal INTSTK$S_R26 = 8; ! r26 - temporary register macro INTSTK$Q_R27 = 504,0,0,0 %; literal INTSTK$S_R27 = 8; ! r27 - temporary register macro INTSTK$Q_R28 = 512,0,0,0 %; literal INTSTK$S_R28 = 8; ! r28 - temporary register macro INTSTK$Q_R29 = 520,0,0,0 %; literal INTSTK$S_R29 = 8; ! r29 - temporary register macro INTSTK$Q_R30 = 528,0,0,0 %; literal INTSTK$S_R30 = 8; ! r30 - temporary register macro INTSTK$Q_R31 = 536,0,0,0 %; literal INTSTK$S_R31 = 8; ! r31 - temporary register ! ! Branch registers ! (br1-br5 are preserved) ! macro INTSTK$Q_B0 = 544,0,0,0 %; literal INTSTK$S_B0 = 8; ! Return pointer on kernel entry macro INTSTK$Q_B1 = 552,0,0,0 %; literal INTSTK$S_B1 = 8; ! b1 - Preserved branch register (not saved by interrupt) macro INTSTK$Q_B2 = 560,0,0,0 %; literal INTSTK$S_B2 = 8; ! b2 - Preserved branch register (not saved by interrupt) macro INTSTK$Q_B3 = 568,0,0,0 %; literal INTSTK$S_B3 = 8; ! b3 - Preserved branch register (not saved by interrupt) macro INTSTK$Q_B4 = 576,0,0,0 %; literal INTSTK$S_B4 = 8; ! b4 - Preserved branch register (not saved by interrupt) macro INTSTK$Q_B5 = 584,0,0,0 %; literal INTSTK$S_B5 = 8; ! b5 - Preserved branch register (not saved by interrupt) macro INTSTK$Q_B6 = 592,0,0,0 %; literal INTSTK$S_B6 = 8; ! b6 - temporary branch register macro INTSTK$Q_B7 = 600,0,0,0 %; literal INTSTK$S_B7 = 8; ! b7 - temporary branch register macro INTSTK$L_IVT_OFFSET = 608,0,32,0 %; ! - Offset in IVT (more specific than trap type) macro INTSTK$L_RESERVED_2 = 612,0,32,0 %; ! - Reserved for future use ! ! Floating point data ! ! ! Alignment for 128-bit floating point ! ! ! Reduced FP subset that compilers might use in the exec ! macro INTSTK$Q_F6 = 624,0,0,0 %; literal INTSTK$S_F6 = 16; ! f6 - temporary FP register macro INTSTK$Q_F7 = 640,0,0,0 %; literal INTSTK$S_F7 = 16; ! f7 - temporary FP register macro INTSTK$Q_F8 = 656,0,0,0 %; literal INTSTK$S_F8 = 16; ! f8 - temporary FP register macro INTSTK$Q_F9 = 672,0,0,0 %; literal INTSTK$S_F9 = 16; ! f9 - temporary FP register macro INTSTK$Q_F10 = 688,0,0,0 %; literal INTSTK$S_F10 = 16; ! f10 - temporary FP register macro INTSTK$Q_F11 = 704,0,0,0 %; literal INTSTK$S_F11 = 16; ! f11 - temporary FP register ! The IIB register contains the instruction bundle that was interrupted on certain ! interrupt types and certain processor. The IIB_VALID flag in the INTSTK will tell ! whether the following is valid: macro INTSTK$Q_IIB0 = 720,0,0,0 %; literal INTSTK$S_IIB0 = 8; ! IIB - Interrupt Instruction Bundle; first 64 bits macro INTSTK$Q_IIB1 = 728,0,0,0 %; literal INTSTK$S_IIB1 = 8; ! IIB - Interrupt Instruction Bundle; remainder of bundle macro INTSTK$Q_SPARE = 736,0,0,0 %; literal INTSTK$S_SPARE = 32; ! Leave 2 spare octawords for future stuff literal INTSTK$K_LENGTH = 768; literal INTSTK$C_LENGTH = 768; literal INTSTK$S_INTSTKDEF = 768; ! Old size name, synonym for INTSTK$S_INTSTK literal REGVA$M_UNUSED_1 = %X'7'; literal REGVA$M_NATINDEX = %X'1F8'; literal REGVA$M_SLOT_GROUPS = %X'FFFFFFFFFFFFFE00'; literal REGVA$S_REGVA = 8; macro REGVA$R_REGVA_UNION = 0,0,0,0 %; literal REGVA$S_REGVA_UNION = 8; macro REGVA$PQ_VA = 0,0,0,1 %; literal REGVA$S_VA = 8; macro REGVA$V_UNUSED_1 = 0,0,3,0 %; literal REGVA$S_UNUSED_1 = 3; macro REGVA$V_NATINDEX = 0,3,6,0 %; literal REGVA$S_NATINDEX = 6; macro REGVA$V_SLOT_GROUPS = 0,9,55,0 %; literal REGVA$S_SLOT_GROUPS = 55; ! ! SSENTRY - this defines the context frame placed on the stack when we go to an ! inner mode via an EPC, typically a system service entry. The SSENTRY frame will ! be on stack by the time we leave SWIS to any normal OS system service code. ! It is created by SWIS in module SWIS_SS.S. Note that for the most part, SSENTRY ! is the same as the first part of INTSTK ! literal SSENTRY$M_AST_MFL = %X'1'; literal SSENTRY$M_AST_MFH = %X'2'; literal SSENTRY$M_AST_PSR_MFL = %X'4'; literal SSENTRY$M_AST_PSR_MFH = %X'8'; literal SSENTRY$M_AST_CALLED = %X'10'; literal SSENTRY$M_AST_PSR_DFL = %X'20'; literal SSENTRY$M_AST_PSR_DFH = %X'40'; literal SSENTRY$K_LENGTH = 192; ! Length of normal ssentry without restart info literal SSENTRY$S_SSENTRY = 352; macro SSENTRY$B_FLAGS = 0,0,8,1 %; macro SSENTRY$R_FLAG_BITS = 0,0,8,0 %; macro SSENTRY$V_AST_MFL = 0,0,1,0 %; ! F12-F15 have been saved in AST_Fxx fields below macro SSENTRY$V_AST_MFH = 0,1,1,0 %; ! Upper floating regs have been saved in a separate structure following this one macro SSENTRY$V_AST_PSR_MFL = 0,2,1,0 %; ! Saved PSR.mfl bit macro SSENTRY$V_AST_PSR_MFH = 0,3,1,0 %; ! Saved PSR.mfh bit macro SSENTRY$V_AST_CALLED = 0,4,1,0 %; ! ASTDEL has been called at least once with this frame macro SSENTRY$V_AST_PSR_DFL = 0,5,1,0 %; ! Saved PSR.dfl bit macro SSENTRY$V_AST_PSR_DFH = 0,6,1,0 %; ! Saved PSR.dfh bit macro SSENTRY$B_PPREVMODE = 1,0,8,0 %; ! Save interrupted context's PREVMODE macro SSENTRY$B_PREVSTACK = 2,0,8,0 %; ! What mode of stack (register and memory) do we return to? ! Note: The OS must prevent interruptions any time the register ! stack and memory stack are different modes macro SSENTRY$B_IPL = 3,0,8,0 %; ! SWIS IPL state macro SSENTRY$L_STKALIGN = 4,0,32,0 %; ! How much allocated on this stack for int frame? Guaranteed that ! STKALIGN & 0XFFF0 is the actual length of the structure. In other ! words, the structure is always allocated on a 16-byte boundary is ! is a multiple of 16-bytes long. macro SSENTRY$W_SPARE2 = 8,0,16,0 %; ! NATMASK in INTSTK macro SSENTRY$B_TYPE = 10,0,8,0 %; ! Make this structure look like a standard VMS structure macro SSENTRY$B_SUBTYPE = 11,0,8,0 %; macro SSENTRY$L_SERVICE_NUMBER = 12,0,32,1 %; macro SSENTRY$Q_RET_ADDR = 16,0,0,0 %; literal SSENTRY$S_RET_ADDR = 8; ! Saved B0 (IIP in INTSTK) ! ! Register Stack Information ! macro SSENTRY$Q_RSC = 24,0,0,0 %; literal SSENTRY$S_RSC = 8; ! Register Stack Control register macro SSENTRY$Q_BSP = 32,0,0,0 %; literal SSENTRY$S_BSP = 8; ! Backing store pointer macro SSENTRY$Q_BSPSTORE = 40,0,0,0 %; literal SSENTRY$S_BSPSTORE = 8; ! User BSP store pointer for next spill macro SSENTRY$Q_RNAT = 48,0,0,0 %; literal SSENTRY$S_RNAT = 8; ! RNAT register macro SSENTRY$Q_BSPBASE = 56,0,0,0 %; literal SSENTRY$S_BSPBASE = 8; ! Base of backing store for the inner mode (used for loadrs) macro SSENTRY$Q_PFS = 64,0,0,0 %; literal SSENTRY$S_PFS = 8; ! Previous function state ! ! Bookkeeping Info ! macro SSENTRY$Q_CONTEXT = 72,0,0,0 %; literal SSENTRY$S_CONTEXT = 8; ! Opaque context left by trap handler to speed ! processing on the way out. If the interrupt frame is ! moved or if the return will be from a different mode, ! this quadword must be cleared. macro SSENTRY$Q_AST_F12 = 80,0,0,0 %; literal SSENTRY$S_AST_F12 = 16; ! f12 - temporary FP register; sometimes saved by AST macro SSENTRY$Q_AST_F13 = 96,0,0,0 %; literal SSENTRY$S_AST_F13 = 16; ! f12 - temporary FP register; sometimes saved by AST macro SSENTRY$Q_AST_F14 = 112,0,0,0 %; literal SSENTRY$S_AST_F14 = 16; ! f12 - temporary FP register; sometimes saved by AST macro SSENTRY$Q_AST_F15 = 128,0,0,0 %; literal SSENTRY$S_AST_F15 = 16; ! f12 - temporary FP register; sometimes saved by AST ! End of overlay between Interrupt Frame and System Service Entry structures macro SSENTRY$Q_PAL_RESERVED_1 = 144,0,0,1 %; literal SSENTRY$S_PAL_RESERVED_1 = 8; ! For the moment, used to save SS return value macro SSENTRY$Q_PAL_RESERVED_2 = 152,0,0,1 %; literal SSENTRY$S_PAL_RESERVED_2 = 8; ! For the moment, used to save SS return value 2 macro SSENTRY$Q_PAL_RESERVED_3 = 160,0,0,1 %; literal SSENTRY$S_PAL_RESERVED_3 = 8; ! More area to save information and pad to aligned boundary macro SSENTRY$Q_PAL_RESERVED_4 = 168,0,0,1 %; literal SSENTRY$S_PAL_RESERVED_4 = 8; macro SSENTRY$Q_PAL_RESERVED_5 = 176,0,0,1 %; literal SSENTRY$S_PAL_RESERVED_5 = 8; macro SSENTRY$Q_PAL_RESERVED_6 = 184,0,0,1 %; literal SSENTRY$S_PAL_RESERVED_6 = 8; macro SSENTRY$Q_SS_RESTART_FV = 192,0,0,0 %; literal SSENTRY$S_SS_RESTART_FV = 8; ! For restarting SS, this is the function value to restart macro SSENTRY$Q_SS_RESTART_RETPC = 200,0,0,0 %; literal SSENTRY$S_SS_RESTART_RETPC = 8; ! For restarting SS, this is the actual caller's return PC macro SSENTRY$Q_SS_RESTART_ARGCNT = 208,0,0,0 %; literal SSENTRY$S_SS_RESTART_ARGCNT = 8; ! For restarting SS, this is the argument count (arguments follow, 16 max) macro SSENTRY$Q_SS_RESTART_ARGS = 216,0,0,0 %; literal SSENTRY$S_SS_RESTART_ARGS = 128; ! Save service arguments in order to restart a system service called from kernel literal SSENTRY$K_RESTRT_LENGTH = 352; ! Length of an SSENTRY with restart info !*** MODULE $IO_ROUTINES_DATA *** ! + ! DEFINITION OF IO_ROUTINES IMAGE LOCAL DATA ! - literal S_IO_ROUTINES_DATA = 8; macro IOC_GL_PSFL = 0,0,32,1 %; ! I/O POST QUEUE FORWARD LINK macro IOC_GL_PSBL = 4,0,32,1 %; ! I/O POST QUEUE BACKWARD LINK !*** MODULE $IO0202DEF *** literal IO0202$Q_IOCSR_H = 2; ! High nibble of address literal IO0202$Q_IOCSR = 268435456; ! I/O control/status register literal IO0202$Q_CPU0CSR = 0; ! CPU0 control/status register literal IO0202$Q_CPU1CSR = 134217728; ! CPU1 control/status register literal IO0202$Q_CMM0CSR = 1073741824; ! MEM0 control/status register literal IO0202$Q_CMM1CSR = 1342177280; ! MEM1 control/status register literal IO0202$Q_CMM2CSR = 1610612736; ! MEM2 control/status register literal IO0202$Q_CMM3CSR = 1879048192; ! MEM3 control/status register literal IO0202$Q_CERR1 = 268435488; ! Cbus error register 1 literal IO0202$Q_CERR2 = 268435520; ! Cbus error register 2 literal IO0202$Q_CERR3 = 268435552; ! Cbus error register 3 literal IO0202$Q_LMBPR = 268435584; ! Lbus mailbos pointer register literal IO0202$Q_FMBPR = 268435616; ! Futurebus mailbos pointer register literal IO0202$Q_DIAGCSR = 268435648; ! Diagnostic control/status register literal IO0202$Q_FIVECT = 268435680; ! Futurebus interrupt vector register literal IO0202$Q_FHVECT = 268435712; ! Futurebus halt vector register literal IO0202$Q_FERRI = 268435744; ! Futurebus error register 1 literal IO0202$Q_FERR2 = 268435776; ! Futurebus error register 2 literal IO0202$Q_LINT = 268435808; ! Local interrupt register literal IO0202$Q_LERR1 = 268435840; ! Lbus error register 1 literal IO0202$Q_LERR2 = 268435872; ! Lbus error register 1 !*** MODULE $IO0302DEF *** literal IO0302$L_UART0A_RR0 = -201326592; literal IO0302$L_UART0A_RR8 = -201326528; literal IO0302$L_UART0B_RR0 = -201326464; literal IO0302$L_UART0B_RR8 = -201326400; literal IO0302$L_UART1B_RR0 = -192937984; literal IO0302$L_UART1B_RR8 = -192937920; literal IO0302$L_UART1A_RR0 = -192937856; literal IO0302$L_UART1A_RR8 = -192937792; literal IO0302$L_UART2B_RR0 = -184549376; literal IO0302$L_UART2B_RR8 = -184549312; literal IO0302$L_UART2A_RR0 = -184549248; literal IO0302$L_UART2A_RR8 = -184549184; literal IO0302$L_WATCH_SECONDS = -167772160; literal IO0302$L_WATCH_MINUTES = -167772032; literal IO0302$L_WATCH_HOURS = -167771904; literal IO0302$L_WATCH_DAY_OF_MONTH = -167771712; literal IO0302$L_WATCH_MONTH = -167771648; literal IO0302$L_WATCH_YEAR = -167771584; literal IO0302$L_WATCH_CSRA = -167771520; literal IO0302$L_WATCH_CSRB = -167771456; literal IO0302$L_WATCH_CSRC = -167771392; literal IO0302$L_WATCH_CSRD = -167771328; literal IO0302$L_WATCH_RAM = -167771264; literal IO0302$L_GBUS_WHAMI = -150994944; literal IO0302$L_GBUS_LEDS = -150994880; literal IO0302$L_GBUS_PMASK = -150994816; literal IO0302$L_GBUS_INTR = -150994752; literal IO0302$L_GBUS_HALT = -150994688; literal IO0302$L_GBUS_LSBRST = -150994624; literal IO0302$L_GBUS_MISC = -150994560; literal IO0302$L_GBUS_RMODE_ENA = -142606336; literal IO0302$L_SLOT0_LDEV = -134217728; ! DEVICE literal IO0302$L_SLOT0_LBER = -134217664; ! ERROR literal IO0302$L_SLOT0_LCNF = -134217600; ! CONFIGURATION literal IO0302$L_SLOT0_IBR = -134217536; ! REPAIR literal IO0302$L_SLOT0_LMMR0 = -134217216; ! MEM MAPPING 0 literal IO0302$L_SLOT0_LMMR1 = -134217152; ! MEM MAPPING 1 literal IO0302$L_SLOT0_LMMR2 = -134217088; ! MEM MAPPING 2 literal IO0302$L_SLOT0_LMMR3 = -134217024; ! MEM MAPPING 3 literal IO0302$L_SLOT0_LMMR4 = -134216960; ! MEM MAPPING 4 literal IO0302$L_SLOT0_LMMR5 = -134216896; ! MEM MAPPING 5 literal IO0302$L_SLOT0_LMMR6 = -134216832; ! MEM MAPPING 6 literal IO0302$L_SLOT0_LMMR7 = -134216768; ! MEM MAPPING 7 literal IO0302$L_SLOT0_LBESR0 = -134216192; ! BUS ERROR SYNDROME 0 literal IO0302$L_SLOT0_LBESR1 = -134216128; ! BUS ERROR SYNDROME 1 literal IO0302$L_SLOT0_LBESR2 = -134216064; ! BUS ERROR SYNDROME 2 literal IO0302$L_SLOT0_LBESR3 = -134216000; ! BUS ERROR SYNDROME 3 literal IO0302$L_SLOT0_LBECR0 = -134215936; ! BUS ERROR COMMAND 0 literal IO0302$L_SLOT0_LBECR1 = -134215872; ! BUS ERROR COMMAND 1 literal IO0302$L_SLOT1_LDEV = -130023424; ! DEVICE REG literal IO0302$L_SLOT1_LBER = -130023360; ! ERROR literal IO0302$L_SLOT1_LCNF = -130023296; ! CONFIGURATION literal IO0302$L_SLOT1_IBR = -130023232; ! REPAIR literal IO0302$L_SLOT1_LMMR0 = -130022912; ! MEM MAPPING 0 literal IO0302$L_SLOT1_LMMR1 = -130022848; ! MEM MAPPING 1 literal IO0302$L_SLOT1_LMMR2 = -130022784; ! MEM MAPPING 2 literal IO0302$L_SLOT1_LMMR3 = -130022720; ! MEM MAPPING 3 literal IO0302$L_SLOT1_LMMR4 = -130022656; ! MEM MAPPING 4 literal IO0302$L_SLOT1_LMMR5 = -130022592; ! MEM MAPPING 5 literal IO0302$L_SLOT1_LMMR6 = -130022528; ! MEM MAPPING 6 literal IO0302$L_SLOT1_LMMR7 = -130022464; ! MEM MAPPING 7 literal IO0302$L_SLOT1_LBESR0 = -130021888; ! BUS ERROR SYNDROME 0 literal IO0302$L_SLOT1_LBESR1 = -130021824; ! BUS ERROR SYNDROME 1 literal IO0302$L_SLOT1_LBESR2 = -130021760; ! BUS ERROR SYNDROME 2 literal IO0302$L_SLOT1_LBESR3 = -130021696; ! BUS ERROR SYNDROME 3 literal IO0302$L_SLOT1_LBECR0 = -130021632; ! BUS ERROR COMMAND 0 literal IO0302$L_SLOT1_LBECR1 = -130021568; ! BUS ERROR COMMAND 1 literal IO0302$L_SLOT2_LDEV = -125829120; ! DEVICE REG literal IO0302$L_SLOT2_LBER = -125829056; ! ERROR literal IO0302$L_SLOT2_LCNF = -125828992; ! CONFIGURATION literal IO0302$L_SLOT2_IBR = -125828928; ! REPAIR literal IO0302$L_SLOT2_LMMR0 = -125828608; ! MEM MAPPING 0 literal IO0302$L_SLOT2_LMMR1 = -125828544; ! MEM MAPPING 1 literal IO0302$L_SLOT2_LMMR2 = -125828480; ! MEM MAPPING 2 literal IO0302$L_SLOT2_LMMR3 = -125828416; ! MEM MAPPING 3 literal IO0302$L_SLOT2_LMMR4 = -125828352; ! MEM MAPPING 4 literal IO0302$L_SLOT2_LMMR5 = -125828288; ! MEM MAPPING 5 literal IO0302$L_SLOT2_LMMR6 = -125828224; ! MEM MAPPING 6 literal IO0302$L_SLOT2_LMMR7 = -125828160; ! MEM MAPPING 7 literal IO0302$L_SLOT2_LBESR0 = -125827584; ! BUS ERROR SYNDROME 0 literal IO0302$L_SLOT2_LBESR1 = -125827520; ! BUS ERROR SYNDROME 1 literal IO0302$L_SLOT2_LBESR2 = -125827456; ! BUS ERROR SYNDROME 2 literal IO0302$L_SLOT2_LBESR3 = -125827392; ! BUS ERROR SYNDROME 3 literal IO0302$L_SLOT2_LBECR0 = -125827328; ! BUS ERROR COMMAND 0 literal IO0302$L_SLOT2_LBECR1 = -125827264; ! BUS ERROR COMMAND 1 literal IO0302$L_SLOT3_LDEV = -121634816; ! DEVICE REG literal IO0302$L_SLOT3_LBER = -121634752; ! ERROR literal IO0302$L_SLOT3_LCNF = -121634688; ! CONFIGURATION literal IO0302$L_SLOT3_IBR = -121634624; ! REPAIR literal IO0302$L_SLOT3_LMMR0 = -121634304; ! MEM MAPPING 0 literal IO0302$L_SLOT3_LMMR1 = -121634240; ! MEM MAPPING 1 literal IO0302$L_SLOT3_LMMR2 = -121634176; ! MEM MAPPING 2 literal IO0302$L_SLOT3_LMMR3 = -121634112; ! MEM MAPPING 3 literal IO0302$L_SLOT3_LMMR4 = -121634048; ! MEM MAPPING 4 literal IO0302$L_SLOT3_LMMR5 = -121633984; ! MEM MAPPING 5 literal IO0302$L_SLOT3_LMMR6 = -121633920; ! MEM MAPPING 6 literal IO0302$L_SLOT3_LMMR7 = -121633856; ! MEM MAPPING 7 literal IO0302$L_SLOT3_LBESR0 = -121633280; ! BUS ERROR SYNDROME 0 literal IO0302$L_SLOT3_LBESR1 = -121633216; ! BUS ERROR SYNDROME 1 literal IO0302$L_SLOT3_LBESR2 = -121633152; ! BUS ERROR SYNDROME 2 literal IO0302$L_SLOT3_LBESR3 = -121633088; ! BUS ERROR SYNDROME 3 literal IO0302$L_SLOT3_LBECR0 = -121633024; ! BUS ERROR COMMAND 0 literal IO0302$L_SLOT3_LBECR1 = -121632960; ! BUS ERROR COMMAND 1 literal IO0302$L_SLOT4_LDEV = -117440512; ! DEVICE REG literal IO0302$L_SLOT4_LBER = -117440448; ! ERROR literal IO0302$L_SLOT4_LCNF = -117440384; ! CONFIGURATION literal IO0302$L_SLOT4_IBR = -117440320; ! REPAIR literal IO0302$L_SLOT4_LMMR0 = -117440000; ! MEM MAPPING 0 literal IO0302$L_SLOT4_LMMR1 = -117439936; ! MEM MAPPING 1 literal IO0302$L_SLOT4_LMMR2 = -117439872; ! MEM MAPPING 2 literal IO0302$L_SLOT4_LMMR3 = -117439808; ! MEM MAPPING 3 literal IO0302$L_SLOT4_LMMR4 = -117439744; ! MEM MAPPING 4 literal IO0302$L_SLOT4_LMMR5 = -117439680; ! MEM MAPPING 5 literal IO0302$L_SLOT4_LMMR6 = -117439616; ! MEM MAPPING 6 literal IO0302$L_SLOT4_LMMR7 = -117439552; ! MEM MAPPING 7 literal IO0302$L_SLOT4_LBESR0 = -117438976; ! BUS ERROR SYNDROME 0 literal IO0302$L_SLOT4_LBESR1 = -117438912; ! BUS ERROR SYNDROME 1 literal IO0302$L_SLOT4_LBESR2 = -117438848; ! BUS ERROR SYNDROME 2 literal IO0302$L_SLOT4_LBESR3 = -117438784; ! BUS ERROR SYNDROME 3 literal IO0302$L_SLOT4_LBECR0 = -117438720; ! BUS ERROR COMMAND 0 literal IO0302$L_SLOT4_LBECR1 = -117438656; ! BUS ERROR COMMAND 1 literal IO0302$L_SLOT5_LDEV = -113246208; ! DEVICE REG literal IO0302$L_SLOT5_LBER = -113246144; ! ERROR literal IO0302$L_SLOT5_LCNF = -113246080; ! CONFIGURATION literal IO0302$L_SLOT5_IBR = -113246016; ! REPAIR literal IO0302$L_SLOT5_LMMR0 = -113245696; ! MEM MAPPING 0 literal IO0302$L_SLOT5_LMMR1 = -113245632; ! MEM MAPPING 1 literal IO0302$L_SLOT5_LMMR2 = -113245568; ! MEM MAPPING 2 literal IO0302$L_SLOT5_LMMR3 = -113245504; ! MEM MAPPING 3 literal IO0302$L_SLOT5_LMMR4 = -113245440; ! MEM MAPPING 4 literal IO0302$L_SLOT5_LMMR5 = -113245376; ! MEM MAPPING 5 literal IO0302$L_SLOT5_LMMR6 = -113245312; ! MEM MAPPING 6 literal IO0302$L_SLOT5_LMMR7 = -113245248; ! MEM MAPPING 7 literal IO0302$L_SLOT5_LBESR0 = -113244672; ! BUS ERROR SYNDROME 0 literal IO0302$L_SLOT5_LBESR1 = -113244608; ! BUS ERROR SYNDROME 1 literal IO0302$L_SLOT5_LBESR2 = -113244544; ! BUS ERROR SYNDROME 2 literal IO0302$L_SLOT5_LBESR3 = -113244480; ! BUS ERROR SYNDROME 3 literal IO0302$L_SLOT5_LBECR0 = -113244416; ! BUS ERROR COMMAND 0 literal IO0302$L_SLOT5_LBECR1 = -113244352; ! BUS ERROR COMMAND 1 literal IO0302$L_SLOT6_LDEV = -109051904; ! DEVICE REG literal IO0302$L_SLOT6_LBER = -109051840; ! ERROR literal IO0302$L_SLOT6_LCNF = -109051776; ! CONFIGURATION literal IO0302$L_SLOT6_IBR = -109051712; ! REPAIR literal IO0302$L_SLOT6_LMMR0 = -109051392; ! MEM MAPPING 0 literal IO0302$L_SLOT6_LMMR1 = -109051328; ! MEM MAPPING 1 literal IO0302$L_SLOT6_LMMR2 = -109051264; ! MEM MAPPING 2 literal IO0302$L_SLOT6_LMMR3 = -109051200; ! MEM MAPPING 3 literal IO0302$L_SLOT6_LMMR4 = -109051136; ! MEM MAPPING 4 literal IO0302$L_SLOT6_LMMR5 = -109051072; ! MEM MAPPING 5 literal IO0302$L_SLOT6_LMMR6 = -109051008; ! MEM MAPPING 6 literal IO0302$L_SLOT6_LMMR7 = -109050944; ! MEM MAPPING 7 literal IO0302$L_SLOT6_LBESR0 = -109050368; ! BUS ERROR SYNDROME 0 literal IO0302$L_SLOT6_LBESR1 = -109050304; ! BUS ERROR SYNDROME 1 literal IO0302$L_SLOT6_LBESR2 = -109050240; ! BUS ERROR SYNDROME 2 literal IO0302$L_SLOT6_LBESR3 = -109050176; ! BUS ERROR SYNDROME 3 literal IO0302$L_SLOT6_LBECR0 = -109050112; ! BUS ERROR COMMAND 0 literal IO0302$L_SLOT6_LBECR1 = -109050048; ! BUS ERROR COMMAND 1 literal IO0302$L_SLOT7_LDEV = -104857600; ! DEVICE REG literal IO0302$L_SLOT7_LBER = -104857536; ! ERROR literal IO0302$L_SLOT7_LCNF = -104857472; ! CONFIGURATION literal IO0302$L_SLOT7_IBR = -104857408; ! REPAIR literal IO0302$L_SLOT7_LMMR0 = -104857088; ! MEM MAPPING 0 literal IO0302$L_SLOT7_LMMR1 = -104857024; ! MEM MAPPING 1 literal IO0302$L_SLOT7_LMMR2 = -104856960; ! MEM MAPPING 2 literal IO0302$L_SLOT7_LMMR3 = -104856896; ! MEM MAPPING 3 literal IO0302$L_SLOT7_LMMR4 = -104856832; ! MEM MAPPING 4 literal IO0302$L_SLOT7_LMMR5 = -104856768; ! MEM MAPPING 5 literal IO0302$L_SLOT7_LMMR6 = -104856704; ! MEM MAPPING 6 literal IO0302$L_SLOT7_LMMR7 = -104856640; ! MEM MAPPING 7 literal IO0302$L_SLOT7_LBESR0 = -104856064; ! BUS ERROR SYNDROME 0 literal IO0302$L_SLOT7_LBESR1 = -104856000; ! BUS ERROR SYNDROME 1 literal IO0302$L_SLOT7_LBESR2 = -104855936; ! BUS ERROR SYNDROME 2 literal IO0302$L_SLOT7_LBESR3 = -104855872; ! BUS ERROR SYNDROME 3 literal IO0302$L_SLOT7_LBECR0 = -104855808; ! BUS ERROR COMMAND 0 literal IO0302$L_SLOT7_LBECR1 = -104855744; ! BUS ERROR COMMAND 1 literal IO0302$L_SLOT8_LDEV = -100663296; ! DEVICE REG literal IO0302$L_SLOT8_LBER = -100663232; ! ERROR literal IO0302$L_SLOT8_LCNF = -100663168; ! CONFIGURATION literal IO0302$L_SLOT8_IBR = -100663104; ! REPAIR literal IO0302$L_SLOT8_LMMR0 = -100662784; ! MEM MAPPING 0 literal IO0302$L_SLOT8_LMMR1 = -100662720; ! MEM MAPPING 1 literal IO0302$L_SLOT8_LMMR2 = -100662656; ! MEM MAPPING 2 literal IO0302$L_SLOT8_LMMR3 = -100662592; ! MEM MAPPING 3 literal IO0302$L_SLOT8_LMMR4 = -100662528; ! MEM MAPPING 4 literal IO0302$L_SLOT8_LMMR5 = -100662464; ! MEM MAPPING 5 literal IO0302$L_SLOT8_LMMR6 = -100662400; ! MEM MAPPING 6 literal IO0302$L_SLOT8_LMMR7 = -100662336; ! MEM MAPPING 7 literal IO0302$L_SLOT8_LBESR0 = -100661760; ! BUS ERROR SYNDROME 0 literal IO0302$L_SLOT8_LBESR1 = -100661696; ! BUS ERROR SYNDROME 1 literal IO0302$L_SLOT8_LBESR2 = -100661632; ! BUS ERROR SYNDROME 2 literal IO0302$L_SLOT8_LBESR3 = -100661568; ! BUS ERROR SYNDROME 3 literal IO0302$L_SLOT8_LBECR0 = -100661504; ! BUS ERROR COMMAND 0 literal IO0302$L_SLOT8_LBECR1 = -100661440; ! BUS ERROR COMMAND 1 literal IO0302$L_LILID0 = -100660736; ! INTERRUPT LEVEL0 IDENT literal IO0302$L_LILID1 = -100660672; ! INTERRUPT LEVEL1 IDENT literal IO0302$L_LILID2 = -100660608; ! INTERRUPT LEVEL2 IDENT literal IO0302$L_LILID3 = -100660544; ! INTERRUPT LEVEL3 IDENT literal IO0302$L_LCPUMASK = -100660480; ! CPU INTERRUPT MASK literal IO0302$L_LMBPR = -100660224; ! MAILBOX POINTER literal IO0302$L_IPCNSE = -100655104; ! IO Port Chip Error literal IO0302$L_IPCVR = -100655040; ! IO Port Chip Vector literal IO0302$L_IPCMSR = -100654976; ! IO Port Chip Mode Select literal IO0302$L_IPCHST = -100654912; ! IO Port Chip Hose Status literal IO0302$L_IPCDR = -100654848; ! IO Port Chip Diagnostic literal IO0302$L_LIOINTR = -33554432; ! IO Interrupt reg literal IO0302$L_LIPINTR = -33554368; ! IP Interrupt reg !*** MODULE $IO0402DEF *** literal IO0402$Q_TC_NUMBER = 1; ! Turbochannel number. ! Upper lw of physical ! address literal IO0402$Q_SCSI_CIR = -804782080; ! SCSI Control Interrupts literal IO0402$Q_SCSI_IMER = -804782072; ! SCSI Interrupt Mask Enable literal IO0402$Q_SCSI0_SDA = -804773888; ! SCSI DMA Address literal IO0402$Q_SCSI0_SDIC = -804773880; ! SCSI DMA Interrupt Control literal IO0402$Q_SCSI0_DMA_UNAL0 = -804773872; ! SCSI DMA Unaligned Data 0 literal IO0402$Q_SCSI0_DMA_UNAL1 = -804773864; ! SCSI DMA Unaligned Data 1 literal IO0402$Q_SCSI1_SDA = -804773376; ! SCSI DMA Address literal IO0402$Q_SCSI1_SDIC = -804773368; ! SCSI DMA Interrupt Control literal IO0402$Q_SCSI1_DMA_UNAL0 = -804773360; ! SCSI DMA Unaligned Data 0 literal IO0402$Q_SCSI1_DMA_UNAL1 = -804773352; ! SCSI DMA Unaligned Data 1 literal IO0402$Q_SCSI0_TC_LSB = -804257792; ! SCSI Transfer Counter LSB literal IO0402$Q_SCSI0_TC_MSB = -804257784; ! SCSI Transfer Counter MSB literal IO0402$Q_SCSI0_FIFO = -804257776; ! SCSI FIFO literal IO0402$Q_SCSI0_CMD = -804257768; ! SCSI Command literal IO0402$Q_SCSI0_STATUS = -804257760; ! SCSI Status literal IO0402$Q_SCSI0_INTR = -804257752; ! SCSI Interrupt/Timeout literal IO0402$Q_SCSI0_SEQ = -804257744; ! SCSI Sequence Step literal IO0402$Q_SCSI0_FF = -804257736; ! SCSI FIFO Flags literal IO0402$Q_SCSI0_CONFIG1 = -804257728; ! SCSI Configuration 1 literal IO0402$Q_SCSI0_CC = -804257720; ! SCSI reserved/Clock Conversion literal IO0402$Q_SCSI0_TM = -804257712; ! SCSI reserved/Test Mode literal IO0402$Q_SCSI0_CONFIG2 = -804257704; ! SCSI Configuration 2 literal IO0402$Q_SCSI0_CONFIG3 = -804257696; ! SCSI Configuration 3 literal IO0402$Q_SCSI1_TC_LSB = -804257280; ! SCSI Transfer Counter LSB literal IO0402$Q_SCSI1_TC_MSB = -804257272; ! SCSI Transfer Counter MSB literal IO0402$Q_SCSI1_FIFO = -804257264; ! SCSI FIFO literal IO0402$Q_SCSI1_CMD = -804257256; ! SCSI Command literal IO0402$Q_SCSI1_STATUS = -804257248; ! SCSI Status literal IO0402$Q_SCSI1_INTR = -804257240; ! SCSI Interrupt literal IO0402$Q_SCSI1_SEQ = -804257232; ! SCSI Sequence Step literal IO0402$Q_SCSI1_FF = -804257224; ! SCSI FIFO Flags literal IO0402$Q_SCSI1_CONFIG1 = -804257216; ! SCSI Configuration 1 literal IO0402$Q_SCSI1_CC = -804257208; ! SCSI reserved/Clock Conversion literal IO0402$Q_SCSI1_TM = -804257200; ! SCSI reserved/Test Mode literal IO0402$Q_SCSI1_CONFIG2 = -804257192; ! SCSI Configuration 2 literal IO0402$Q_SCSI1_CONFIG3 = -804257184; ! SCSI Configuration 3 literal IO0402$Q_SCSI0_DMA = -803733504; ! SCSI DMA Buffer literal IO0402$Q_SCSI1_DMA = -803732992; ! SCSI DMA Buffer literal IO0402$Q_IOSLOT = -738197504; ! IO Slot Configuration literal IO0402$Q_TCCONFIG = -738197488; ! TC Configuration literal IO0402$Q_FADR = -738197472; ! Failing Address literal IO0402$Q_TCEREG = -738197456; ! Turbochannel Error Register literal IO0402$Q_MCR0 = -734003200; ! Memory Configuration 0 literal IO0402$Q_MCR1 = -733872128; ! Memory Configuration 1 literal IO0402$Q_MCR2 = -733741056; ! Memory Configuration 2 literal IO0402$Q_MCR3 = -733609984; ! Memory Configuration 3 literal IO0402$Q_MCR4 = -733478912; ! Memory Configuration 4 literal IO0402$Q_MCR5 = -733347840; ! Memory Configuration 5 literal IO0402$Q_MCR6 = -733216768; ! Memory Configuration 6 literal IO0402$Q_MCR7 = -733085696; ! Memory Configuration 7 literal IO0402$Q_IR = -729808896; ! Interrupt Register literal IO0402$Q_IC = -725614592; ! Interrupt Cause literal IO0402$Q_SG_MAP = -721420288; ! Scatter/Gather literal IO0402$Q_TCRESET = -717225984; ! Turbochannel Reset literal IO0402$Q_FLASH_EEPROM = -268435456; ! CORE I/O ASIC registers - system ROM, part 2 literal IO0402$Q_IOCTL_CSR = -267911168; ! CORE I/O base CSR address literal IO0402$Q_LDP = -267911104; ! Ethernet DMA pointer literal IO0402$Q_SCOMM_TR = -267911072; ! Serial comm transmit port 1 DMA pointer literal IO0402$Q_SCOMM_RC = -267911040; ! Serial comm receive port 1 DMA pointer literal IO0402$Q_PRINTER_TR = -267911008; ! Serial comm transmit port 2 DMA pointer literal IO0402$Q_PRINTER_RC = -267910976; ! Serial comm receive port 2 DMA pointer literal IO0402$Q_ISDN_TR = -267910912; ! ISDN transmit DMA pointer literal IO0402$Q_ISDN_TR_BUF = -267910880; ! ISDN transmit DMA buffer pointer literal IO0402$Q_ISDN_RC = -267910848; ! ISDN receive DMA pointer literal IO0402$Q_ISDN_RC_BUF = -267910816; ! ISDN receive DMA buffer pointer literal IO0402$Q_DATA0 = -267910784; ! System Data Buffer 0 literal IO0402$Q_DATA1 = -267910752; ! System Data Buffer 1 literal IO0402$Q_DATA2 = -267910720; ! System Data Buffer 2 literal IO0402$Q_DATA3 = -267910688; ! System Data Buffer 3 literal IO0402$Q_SSR = -267910656; ! System support register literal IO0402$Q_SIR = -267910624; ! System interrupt register literal IO0402$Q_SIMR = -267910592; ! System interrupt mask register literal IO0402$Q_SADR = -267910560; ! System address register literal IO0402$Q_ISDN_DATA_TR = -267910528; ! ISDN Data Transmit literal IO0402$Q_ISDN_DATA_RC = -267910496; ! ISDN Data Receive literal IO0402$Q_LANCE_SLOT = -267910464; ! Lance slot register literal IO0402$Q_SCC0_SLOT = -267910400; ! SCC1 slot register literal IO0402$Q_SCC1_SLOT = -267910368; ! SCC0 slot register literal IO0402$Q_NI_ADR_ROM = -267386880; ! Ethernet address ROM literal IO0402$Q_LANCE_RDP = -266862592; ! Lance ethernet CSR literal IO0402$Q_LANCE_RAP = -266862584; ! Lance ethernet CSR literal IO0402$Q_SCC0B_COMM_RAP = -266338304; ! Comm Port 1 RAP literal IO0402$Q_SCC0B_COMM_DATA = -266338296; ! Comm Port 1 data literal IO0402$Q_SCC0A_MOUSE_RAP = -266338288; ! Mouse RAP literal IO0402$Q_SCC0A_MOUSE_DATA = -266338280; ! Mouse port data register literal IO0402$Q_SCC1B_PRINTER_RAP = -265289728; ! Comm Port 2 RAP literal IO0402$Q_SCC1B_PRINTER_DATA = -265289720; ! Comm Port 2 data literal IO0402$Q_SCC1A_KEY_RAP = -265289712; ! Keyboard RAP literal IO0402$Q_SCC1A_KEY_DATA = -265289704; ! Keyboard port data register literal IO0402$Q_RTC_SEC = -264241152; ! TOY clock CSR--seconds literal IO0402$Q_RTC_ALMS = -264241144; ! TOY clock CSR--seconds alarm literal IO0402$Q_RTC_MIN = -264241136; ! TOY clock CSR--minutes literal IO0402$Q_RTC_ALMN = -264241128; ! TOY clock CSR--minutes alarm literal IO0402$Q_RTC_HOUR = -264241120; ! TOY clock CSR--hours literal IO0402$Q_RTC_ALMH = -264241112; ! TOY clock CSR--hours alarm literal IO0402$Q_RTC_DOW = -264241104; ! TOY clock CSR--day of week literal IO0402$Q_RTC_DAY = -264241096; ! TOY clock CSR--date of month literal IO0402$Q_RTC_MON = -264241088; ! TOY clock CSR--month literal IO0402$Q_RTC_YEAR = -264241080; ! TOY clock CSR--year literal IO0402$Q_RTC_REGA = -264241072; ! TOY clock CSR--register A literal IO0402$Q_RTC_REGB = -264241064; ! TOY clock CSR--register B literal IO0402$Q_RTC_REGC = -264241056; ! TOY clock CSR--register C literal IO0402$Q_RTC_REGD = -264241048; ! TOY clock CSR--register D literal IO0402$Q_RTC_RAM = -264241040; ! TOY clock CSR--base of BBU RAM literal IO0402$Q_ISDN_AUDIO = -263716864; ! ISDN audio chip CSR literal IO0402$Q_SYSTEM_EEPROM = -201326592; ! base of system ROM, part 1 literal IO0402$Q_CPYBUF0 = -199229440; literal IO0402$Q_CPYBUF1 = -199229432; literal IO0402$Q_CPYBUF2 = -199229424; literal IO0402$Q_CPYBUF3 = -199229416; literal IO0402$Q_CPYBUF4 = -199229408; literal IO0402$Q_CPYBUF5 = -199229400; literal IO0402$Q_CPYBUF6 = -199229392; literal IO0402$Q_CPYBUF7 = -199229384; literal IO0402$Q_FG = -199229376; literal IO0402$Q_BG = -199229368; literal IO0402$Q_PLANEMASK = -199229360; literal IO0402$Q_PIXMASK = -199229352; literal IO0402$Q_MODE = -199229344; literal IO0402$Q_BOOLOP = -199229336; literal IO0402$Q_PIXSHIFT = -199229328; literal IO0402$Q_ADDR_REG = -199229320; literal IO0402$Q_BRES1 = -199229312; literal IO0402$Q_BRES2 = -199229304; literal IO0402$Q_BRES3 = -199229296; literal IO0402$Q_BCONT = -199229288; literal IO0402$Q_DEEP = -199229280; literal IO0402$Q_START = -199229272; literal IO0402$Q_CI = -199229264; literal IO0402$Q_V_REF_COUNT = -199229248; literal IO0402$Q_V_HOR = -199229240; literal IO0402$Q_V_VER = -199229232; literal IO0402$Q_VV = -199229216; literal IO0402$Q_EI = -199229208; literal IO0402$Q_TCCLK_COUNT = -199229200; literal IO0402$Q_VIDCLK_COUNT = -199229192; literal IO0402$Q_RAMDAC_ADDR_LO = -197656576; literal IO0402$Q_RAMDAC_ADDR_HI = -197656568; literal IO0402$Q_RAMDAC_REG_ADDR = -197656560; literal IO0402$Q_RAMDAC_MAP_LOC = -197656552; literal IO0402$Q_FB = -501219328; literal IO0402$Q_SLOT0_DENSE_BASE = 0; literal IO0402$Q_SLOT1_DENSE_BASE = 536870912; literal IO0402$Q_SLOT2_DENSE_BASE = 1073741824; literal IO0402$Q_SLOT3_DENSE_BASE = 1610612736; literal IO0402$Q_SLOT4_DENSE_BASE = -2147483648; literal IO0402$Q_SLOT5_DENSE_BASE = -1610612736; literal IO0402$Q_SLOT6_DENSE_BASE = -1073741824; literal IO0402$Q_SLOT7_DENSE_BASE = -536870912; literal IO0402$Q_CXTURBO_DENSE_BASE = -503316480; literal IO0402$Q_SLOT0_SPARSE_BASE = 268435456; literal IO0402$Q_SLOT1_SPARSE_BASE = 805306368; literal IO0402$Q_SLOT2_SPARSE_BASE = 1342177280; literal IO0402$Q_SLOT3_SPARSE_BASE = 1879048192; literal IO0402$Q_SLOT4_SPARSE_BASE = -1879048192; literal IO0402$Q_SLOT5_SPARSE_BASE = -1342177280; literal IO0402$Q_SLOT6_SPARSE_BASE = -805306368; literal IO0402$Q_SLOT7_SPARSE_BASE = -268435456; literal IO0402$Q_LDP_DENSE = -536608736; ! Ethernet DMA pointer literal IO0402$Q_NI_ADR_ROM_DENSE = -536346624; ! Ethernet address ROM literal IO0402$Q_LANCE_RDP_DENSE = -536084480; ! Lance ethernet CSR literal IO0402$Q_IMASK_READ = -1035993088; ! IR dense space literal IO0402$Q_SG_DENSE = -1031675904; ! Base of last page of SG dense space !*** MODULE $IO0602DEF *** literal IO0602$K_EISA_LOCAL = 1; literal IO0602$K_EISA_MEM = 2; literal IO0602$K_EISA_IO = 3; literal IO0602$Q_EISA_INTA_CYCLE = 0; literal IO0602$Q_EISA_COMBO_CHIP = -1073741824; ! base address of COMBO ADDR space literal IO0602$Q_EISA_COMBO_CHIP_RTC = -1073553408; ! base address of COMBO ADDR space, RTC literal IO0602$B_KBD_PS2 = -1073696768; ! PS2 keyboard register, read literal IO0602$B_KBD_DBB = -1073696768; ! PS2 keyboard register, write literal IO0602$B_KBD_PS2S = -1073694720; ! PS2 status register literal IO0602$B_TOY_R_INDX_REG = -1073684480; ! address of index register for read addr. literal IO0602$B_TOY_R_DATA_REG = -1073683968; ! address of data register for read data. literal IO0602$B_TOY_W_INDX_REG = -1073553408; ! address of index register for write addr. literal IO0602$B_TOY_W_DATA_REG = -1073552896; ! address of data register for write data. literal IO0602$K_TOY_SECS = 0; ! seconds of TOY clock. literal IO0602$K_TOY_ASECS = 1; ! seconds of TOY clock, alarm func. literal IO0602$K_TOY_MINS = 2; ! minutes of TOY clock. literal IO0602$K_TOY_AMINS = 3; ! minutes of TOY clock, alarm func. literal IO0602$K_TOY_HOURS = 4; ! hours of TOY clock. literal IO0602$K_TOY_AHOURS = 5; ! hours of TOY clock, alarm func. literal IO0602$K_TOY_DAY = 6; ! day of week, 1-7 literal IO0602$K_TOY_DATE = 7; ! date of month literal IO0602$K_TOY_MONTH = 8; ! month literal IO0602$K_TOY_YEAR = 9; ! year literal IO0602$K_TOY_CNTRLA = 10; ! control register A literal IO0602$K_TOY_CNTRLB = 11; ! control register B literal IO0602$K_TOY_CNTRLC = 12; ! control register C literal IO0602$K_TOY_CNTRLD = 13; ! control register D literal IO0602$B_COMB_RBR = -1073352704; ! Recieve Buffer Register literal IO0602$B_COMB_THR = -1073352704; ! Transmitter Holding Register literal IO0602$B_COMB_DLL = -1073352704; ! Divisor Latch Register(LSB) literal IO0602$B_COMB_DLM = -1073352192; ! Divisor Latch Register(MSB) literal IO0602$B_COMB_IER = -1073352192; ! Interrupt Enable Register literal IO0602$B_COMB_FCR = -1073351680; ! literal IO0602$B_COMB_IIR = -1073351680; ! Interrupt Identification Register literal IO0602$B_COMB_LCR = -1073351168; ! Line Control Register literal IO0602$B_COMB_MCR = -1073350656; ! Modem Control Register literal IO0602$B_COMB_LSR = -1073350144; ! Line Status Register literal IO0602$B_COMB_MSR = -1073349632; ! Modem Status Register literal IO0602$B_COMB_SCR = -1073349120; ! Scratch Register literal IO0602$B_LPT_REG0 = -1073252352; ! Data Register literal IO0602$B_LPT_REG1 = -1073251840; ! Status Register literal IO0602$B_LPT_REG2 = -1073251328; ! Control Register literal IO0602$B_COMA_RBR = -1073221632; ! Recieve Buffer Register literal IO0602$B_COMA_THR = -1073221632; ! Transmitter Holding Register literal IO0602$B_COMA_DLL = -1073221632; ! Divisor Latch Register(LSB) literal IO0602$B_COMA_DLM = -1073221120; ! Divisor Latch Register(MSB) literal IO0602$B_COMA_IER = -1073221120; ! Interrupt Enable Register literal IO0602$B_COMA_FCR = -1073220608; ! literal IO0602$B_COMA_IIR = -1073220608; ! Interrupt Identification Register literal IO0602$B_COMA_LCR = -1073220096; ! Line Control Register literal IO0602$B_COMA_MCR = -1073219584; ! Modem Control Register literal IO0602$B_COMA_LSR = -1073219072; ! Line Status Register literal IO0602$B_COMA_MSR = -1073218560; ! Modem Status Register literal IO0602$B_COMA_SCR = -1073218048; ! Scratch Register literal IO0602$Q_EISA_CONFIG_DATA = -1409286144; literal IO0602$Q_EISA_CONFIG_IRQ = 107520; literal IO0602$Q_EISA_CONFIG_DMA = 114688; literal IO0602$Q_EISA_CONFIG_MEM = 76288; literal IO0602$Q_EISA_CONFIG_IO_PORT = 102912; literal IO0602$Q_HOST_ADDR_EXT = -805306368; literal IO0602$Q_SYS_CNTRL_REG = -536870912; literal IO0602$Q_SPARE_REG = -268435456; literal IO0602$Q_EISA_MEM_BASE = 0; literal IO0602$Q_EISA_IO_BASE = 0; literal IO0602$Q_EISA_IO_ISP = 0; ! base addr of ISP chip(82357) literal IO0602$B_DMA1_CH0_ADDR = 0; ! 0 addr of DMA1 CH-0 Base and Current Address literal IO0602$B_DMA1_CH0_CNT = 128; ! 1 addr of DMA1 CH-0 Base and Current Address literal IO0602$B_DMA1_CH1_ADDR = 256; ! 2 addr of DMA1 CH-1 Base and Current Address literal IO0602$B_DMA1_CH1_CNT = 384; ! 3 addr of DMA1 CH-1 Base and Current Address literal IO0602$B_DMA1_CH2_ADDR = 512; ! 4 addr of DMA1 CH-2 Base and Current Address literal IO0602$B_DMA1_CH2_CNT = 640; ! 5 addr of DMA1 CH-2 Base and Current Address literal IO0602$B_DMA1_CH3_ADDR = 768; ! 6 addr of DMA1 CH-3 Base and Current Address literal IO0602$B_DMA1_CH3_CNT = 896; ! 7 addr of DMA1 CH-3 Base and Current Address literal IO0602$B_DMA1_STATUS = 1024; ! 8 addr of DMA1 status literal IO0602$B_DMA1_WR_REQ = 1152; ! 9 addr of DMA1 write request literal IO0602$B_DMA1_WR_MASK = 1280; ! A addr of DMA1 write single mask bit literal IO0602$B_DMA1_WR_MODE = 1408; ! B addr of DMA1 write mode register literal IO0602$B_DMA1_CL_BYTE = 1536; ! C addr of DMA1 clear byte pointer literal IO0602$B_DMA1_MASTER_CLR = 1664; ! D addr of DMA1 master clear literal IO0602$B_DMA1_CLR_MASK = 1792; ! E addr of DMA1 clear mask reg literal IO0602$B_DMA1_RW_MASK_REG = 1920; ! F addr of DMA1 read/write all mask reg bits literal IO0602$B_INT_1_CNTRL = 4096; ! 20 INT1 control register literal IO0602$B_INT_1_MASK = 4224; ! 21 INT1 mask register literal IO0602$B_INTV_TIMER1 = 8192; ! 40 Interval Timer 1 literal IO0602$B_REF_REQ = 8320; ! 41 Refresh Request Register literal IO0602$B_SKR_TONE = 8448; ! 42 Speaker Tone Register literal IO0602$B_CMD_MODE = 8576; ! 43 Command Mode Register literal IO0602$B_INTV_TIMER2 = 9216; ! 48 Interval Timer 2 literal IO0602$B_SPD_CNTRL = 9472; ! 4A CPU Speed Control literal IO0602$B_CMD_MODE2 = 9600; ! 4B Command Mode Register literal IO0602$B_NMI_STATUS = 12416; ! 61 NMI Status literal IO0602$B_NMI_ENABLE = 14336; ! 70 NMI Enable Register literal IO0602$B_DMA_PAGE_R1 = 16384; ! 80 DMA PAGE Register(reserved) literal IO0602$B_DMA_PAGE_CH2 = 16512; ! 81 DMA PAGE Register CH 2 literal IO0602$B_DMA_PAGE_CH3 = 16640; ! 82 DMA PAGE Register Ch 3 literal IO0602$B_DMA_PAGE_CH1 = 16768; ! 83 DMA PAGE Register Ch 1 literal IO0602$B_DMA_PAGE_R2 = 16896; ! 84 DMA PAGE Register(reserved) literal IO0602$B_DMA_PAGE_R3 = 17024; ! 85 DMA PAGE Register(reserved) literal IO0602$B_DMA_PAGE_R4 = 17152; ! 86 DMA PAGE Register(reserved) literal IO0602$B_DMA_PAGE_CH0 = 17280; ! 87 DMA PAGE Register CH 0 literal IO0602$B_DMA_PAGE_R5 = 17408; ! 88 DMA PAGE Register(reserved) literal IO0602$B_DMA_PAGE_CH6 = 17536; ! 89 DMA PAGE Register CH 6 literal IO0602$B_DMA_PAGE_CH7 = 17664; ! 8A DMA PAGE Register CH 7 literal IO0602$B_DMA_PAGE_CH5 = 17792; ! 8B DMA PAGE Register CH 5 literal IO0602$B_DMA_PAGE_R6 = 17920; ! 8C DMA PAGE Register(reserved) literal IO0602$B_DMA_PAGE_R7 = 18048; ! 8D DMA PAGE Register(reserved) literal IO0602$B_DMA_PAGE_R8 = 18176; ! 8E DMA PAGE Register(reserved) literal IO0602$B_DMA_PAGE_REF = 18304; ! 8F DMA PAGE Register Refresh Page literal IO0602$B_INT2_CNTRL = 20480; ! A0 INT-2 control register literal IO0602$B_INT2_MASK = 20608; ! A1 INT-2 mask register literal IO0602$B_DMA2_CH0_ADDR = 24576; ! C0 addr of DMA2 CH-0 Base and Current Address literal IO0602$B_DMA2_CH0_CNT = 24832; ! C2 addr of DMA2 CH-0 Base and Current Address literal IO0602$B_DMA2_CH1_ADDR = 25088; ! C4 addr of DMA2 CH-1 Base and Current Address literal IO0602$B_DMA2_CH1_CNT = 25344; ! C6 addr of DMA2 CH-1 Base and Current Address literal IO0602$B_DMA2_CH2_ADDR = 25600; ! C8 addr of DMA2 CH-2 Base and Current Address literal IO0602$B_DMA2_CH2_CNT = 25856; ! CA addr of DMA2 CH-2 Base and Current Address literal IO0602$B_DMA2_CH3_ADDR = 26112; ! CC addr of DMA2 CH-3 Base and Current Address literal IO0602$B_DMA2_CH3_CNT = 26368; ! CE addr of DMA2 CH-3 Base and Current Address literal IO0602$B_DMA2_STATUS = 26624; ! D0 addr of DMA2 status literal IO0602$B_DMA2_WR_REQ = 26880; ! D2 addr of DMA2 write request literal IO0602$B_DMA2_WR_MASK = 27136; ! D4 addr of DMA2 write single mask bit literal IO0602$B_DMA2_WR_MODE = 27392; ! D6 addr of DMA2 write mode register literal IO0602$B_DMA2_CL_BYTE = 27648; ! D8 addr of DMA2 clear byte pointer literal IO0602$B_DMA2_MASTER_CLR = 27904; ! DA addr of DMA2 master clear literal IO0602$B_DMA2_CLR_MASK = 28160; ! DC addr of DMA2 clear mask reg literal IO0602$B_DMA2_RW_MASK_REG = 28416; ! DE addr of DMA2 read/write all mask reg bits literal IO0602$B_DMA1_CH0_CNT_HIGH = 131200; ! 401 DMA1 Ch0 base/current count high literal IO0602$B_DMA1_CH1_CNT_HIGH = 131456; ! 403 DMA1 Ch1 base/current count high literal IO0602$B_DMA1_CH2_CNT_HIGH = 131712; ! 405 DMA1 Ch2 base/current count high literal IO0602$B_DMA1_CH3_CNT_HIGH = 131968; ! 407 DMA1 Ch3 base/current count high literal IO0602$B_DMA1_CHN_MODE = 132352; ! 40A DMA1 Set Chaining Mode(w), Int status (r) literal IO0602$B_DMA1_WRT_MODE = 132480; ! 40B DMA1 Ext Write Mode Reg literal IO0602$B_DMA1_CHN_BUF_CNTRL = 132608; ! 40C DMA1 Chain Buf Control literal IO0602$B_DMA1_STEP_LVL = 132736; ! 40D DMA1 Stepping LEvel Reg literal IO0602$B_EXNMI_CNTRL = 143488; ! 461 Extended NMI and reset control literal IO0602$B_NMI_IO_INT_PORT = 143616; ! 462 NMI IO Int Port(casual) literal IO0602$B_LAST_BUS_MSTR = 143872; ! 464 LAst Bus MAster Granted literal IO0602$B_DMA_CH2_HIGH_PAGE = 147584; ! 481 DMA High Page Resgister CH-2 PAge literal IO0602$B_DMA_CH3_HIGH_PAGE = 147712; ! 482 DMA High Page Resgister CH-3 PAge literal IO0602$B_DMA_CH1_HIGH_PAGE = 147840; ! 483 DMA High Page Resgister CH-1 PAge literal IO0602$B_DMA_CH0_HIGH_PAGE = 148352; ! 487 DMA High Page Resgister CH-0 PAge literal IO0602$B_DMA_CH6_HIGH_PAGE = 148608; ! 489 DMA High Page Resgister CH-6 PAge literal IO0602$B_DMA_CH7_HIGH_PAGE = 148736; ! 48A DMA High Page Resgister CH-7 PAge literal IO0602$B_DMA_CH5_HIGH_PAGE = 148864; ! 48B DMA High Page Resgister CH-5 PAge literal IO0602$B_DMA_REG_REFRESH = 149376; ! 48F DMA High Page Resgister Refresh literal IO0602$B_DMA2_CH5_CNT_HIGH = 156416; ! 4C6 DMA2 Ch 5 base/current count high literal IO0602$B_DMA2_CH6_CNT_HIGH = 156928; ! 4CA DMA2 Ch 6 base/current count high literal IO0602$B_DMA2_CH7_CNT_HIGH = 157440; ! 4CE DMA2 Ch 7 base/current count high literal IO0602$B_INT1_LVL_CTRL = 157696; ! 4D0 INT-1 Edge LEvel Control Reg literal IO0602$B_INT2_LVL_CTRL = 157824; ! 4D1 INT-2 Edge LEvel Control Reg literal IO0602$B_DMA2_CHN_MODE = 158208; ! 4D4 DMA2 Set chaining mode literal IO0602$B_DMA2_EXT_WRT_MODE = 158464; ! 4D6 DMA2 Ext Write Mode Reg literal IO0602$B_DMA_CH0_STOP_7_2 = 159744; ! 4E0 DMA CH0 Stop Reg Bits<7:2> literal IO0602$B_DMA_CH0_STOP_15_8 = 159872; ! 4E1 DMA CH0 Stop Reg Bits<15:8> literal IO0602$B_DMA_CH0_STOP_23_16 = 160000; ! 4E2 DMA CH0 Stop Reg Bits<23:16> literal IO0602$B_DMA_CH1_STOP_7_2 = 160256; ! 4E4 DMA CH1 Stop Reg Bits<7:2> literal IO0602$B_DMA_CH1_STOP_15_8 = 160384; ! 4E5 DMA CH1 Stop Reg Bits<15:8> literal IO0602$B_DMA_CH1_STOP_23_16 = 160512; ! 4E6 DMA CH1 Stop Reg Bits<23:16> literal IO0602$B_DMA_CH2_STOP_7_2 = 160768; ! 4E8 DMA CH2 Stop Reg Bits<7:2> literal IO0602$B_DMA_CH2_STOP_15_8 = 160896; ! 4E9 DMA CH2 Stop Reg Bits<15:8> literal IO0602$B_DMA_CH2_STOP_23_16 = 161024; ! 4EA DMA CH2 Stop Reg Bits<23:16> literal IO0602$B_DMA_CH3_STOP_7_2 = 161280; ! 4EC DMA CH3 Stop Reg Bits<7:2> literal IO0602$B_DMA_CH3_STOP_15_8 = 161408; ! 4ED DMA CH3 Stop Reg Bits<15:8> literal IO0602$B_DMA_CH3_STOP_23_16 = 161536; ! 4EE DMA CH3 Stop Reg Bits<23:16> literal IO0602$B_DMA_CH5_STOP_7_2 = 162304; ! 4F4 DMA CH5 Stop Reg Bits<7:2> literal IO0602$B_DMA_CH5_STOP_15_8 = 162432; ! 4F5 DMA CH5 Stop Reg Bits<15:8> literal IO0602$B_DMA_CH5_STOP_23_16 = 162560; ! 4F6 DMA CH5 Stop Reg Bits<23:16> literal IO0602$B_DMA_CH6_STOP_7_2 = 162816; ! 4F8 DMA CH6 Stop Reg Bits<7:2> literal IO0602$B_DMA_CH6_STOP_15_8 = 162944; ! 4F9 DMA CH6 Stop Reg Bits<15:8> literal IO0602$B_DMA_CH6_STOP_23_16 = 163072; ! 4FA DMA CH6 Stop Reg Bits<23:16> literal IO0602$B_DMA_CH7_STOP_7_2 = 163328; ! 4FC DMA CH7 Stop Reg Bits<7:2> literal IO0602$B_DMA_CH7_STOP_15_8 = 163456; ! 4FD DMA CH7 Stop Reg Bits<15:8> literal IO0602$B_DMA_CH7_STOP_23_16 = 163584; ! 4FE DMA CH7 Stop Reg Bits<23:16> literal IO0602$Q_EISA_SLOT1_BASE = 524288; ! 1000 literal IO0602$Q_EISA_SLOT2_BASE = 1048576; ! 2000 literal IO0602$Q_EISA_SLOT3_BASE = 1572864; ! 3000 literal IO0602$Q_EISA_SLOT4_BASE = 2097152; ! 4000 literal IO0602$Q_EISA_SLOT5_BASE = 2621440; ! 5000 literal IO0602$Q_EISA_SLOT6_BASE = 3145728; ! 6000 !*** MODULE $IO0702DEF *** literal IO0702$Q_TC_NUMBER = 1; ! Turbochannel number. ! Upper lw of physical ! address literal IO0702$Q_SCSI_CIR = -1878523904; ! SCSI Control Interrupts literal IO0702$Q_SCSI_IMER = -1878523896; ! SCSI Interrupt Mask Enable literal IO0702$Q_SCSI0_SDA = -1878515712; ! SCSI DMA Address literal IO0702$Q_SCSI0_SDIC = -1878515704; ! SCSI DMA Interrupt Control literal IO0702$Q_SCSI0_DMA_UNAL0 = -1878515696; ! SCSI DMA Unaligned Data 0 literal IO0702$Q_SCSI0_DMA_UNAL1 = -1878515688; ! SCSI DMA Unaligned Data 1 literal IO0702$Q_SCSI0_TC_LSB = -1877999616; ! SCSI Transfer Counter LSB literal IO0702$Q_SCSI0_TC_MSB = -1877999608; ! SCSI Transfer Counter MSB literal IO0702$Q_SCSI0_FIFO = -1877999600; ! SCSI FIFO literal IO0702$Q_SCSI0_CMD = -1877999592; ! SCSI Command literal IO0702$Q_SCSI0_STATUS = -1877999584; ! SCSI Status literal IO0702$Q_SCSI0_INTR = -1877999576; ! SCSI Interrupt/Timeout literal IO0702$Q_SCSI0_SEQ = -1877999568; ! SCSI Sequence Step literal IO0702$Q_SCSI0_FF = -1877999560; ! SCSI FIFO Flags literal IO0702$Q_SCSI0_CONFIG1 = -1877999552; ! SCSI Configuration 1 literal IO0702$Q_SCSI0_CC = -1877999544; ! SCSI reserved/Clock Conversion literal IO0702$Q_SCSI0_TM = -1877999536; ! SCSI reserved/Test Mode literal IO0702$Q_SCSI0_CONFIG2 = -1877999528; ! SCSI Configuration 2 literal IO0702$Q_SCSI0_CONFIG3 = -1877999520; ! SCSI Configuration 3 literal IO0702$Q_SCSI0_DMA = -1877475328; ! SCSI DMA Buffer literal IO0702$Q_IR = -268435456; ! Interrupt Register literal IO0702$Q_TCSR = -268435440; ! TC Control & Status Register literal IO0702$Q_MCR = -268435424; ! Memory Config Register literal IO0702$Q_FLASH_EEPROM = -1342177280; ! CORE I/O ASIC registers - system ROM, part 2 literal IO0702$Q_IOCTL_CSR = -1341652992; ! CORE I/O base CSR address literal IO0702$Q_LDP = -1341652928; ! Ethernet DMA pointer literal IO0702$Q_SCOMM_TR = -1341652896; ! Serial comm transmit port 1 DMA pointer literal IO0702$Q_SCOMM_RC = -1341652864; ! Serial comm receive port 1 DMA pointer literal IO0702$Q_PRINTER_TR = -1341652832; ! Serial comm transmit port 2 DMA pointer literal IO0702$Q_PRINTER_RC = -1341652800; ! Serial comm receive port 2 DMA pointer literal IO0702$Q_ISDN_TR = -1341652736; ! ISDN transmit DMA pointer literal IO0702$Q_ISDN_TR_BUF = -1341652704; ! ISDN transmit DMA buffer pointer literal IO0702$Q_ISDN_RC = -1341652672; ! ISDN receive DMA pointer literal IO0702$Q_ISDN_RC_BUF = -1341652640; ! ISDN receive DMA buffer pointer literal IO0702$Q_DATA0 = -1341652608; ! System Data Buffer 0 literal IO0702$Q_DATA1 = -1341652576; ! System Data Buffer 1 literal IO0702$Q_DATA2 = -1341652544; ! System Data Buffer 2 literal IO0702$Q_DATA3 = -1341652512; ! System Data Buffer 3 literal IO0702$Q_SSR = -1341652480; ! System support register literal IO0702$Q_SIR = -1341652448; ! System interrupt register literal IO0702$Q_SIMR = -1341652416; ! System interrupt mask register literal IO0702$Q_SADR = -1341652384; ! System address register literal IO0702$Q_ISDN_DATA_TR = -1341652352; ! ISDN Data Transmit literal IO0702$Q_ISDN_DATA_RC = -1341652320; ! ISDN Data Receive literal IO0702$Q_LANCE_SLOT = -1341652288; ! Lance slot register literal IO0702$Q_SCC0_SLOT = -1341652224; ! SCC1 slot register literal IO0702$Q_SCC1_SLOT = -1341652192; ! SCC0 slot register literal IO0702$Q_NI_ADR_ROM = -1341128704; ! Ethernet address ROM literal IO0702$Q_LANCE_RDP = -1340604416; ! Lance ethernet CSR literal IO0702$Q_LANCE_RAP = -1340604408; ! Lance ethernet CSR literal IO0702$Q_SCC0B_COMM_RAP = -1340080128; ! Comm Port 1 RAP literal IO0702$Q_SCC0B_COMM_DATA = -1340080120; ! Comm Port 1 data literal IO0702$Q_SCC0A_MOUSE_RAP = -1340080112; ! Mouse RAP literal IO0702$Q_SCC0A_MOUSE_DATA = -1340080104; ! Mouse port data register literal IO0702$Q_SCC1B_PRINTER_RAP = -1339031552; ! Comm Port 2 RAP literal IO0702$Q_SCC1B_PRINTER_DATA = -1339031544; ! Comm Port 2 data literal IO0702$Q_SCC1A_KEY_RAP = -1339031536; ! Keyboard RAP literal IO0702$Q_SCC1A_KEY_DATA = -1339031528; ! Keyboard port data register literal IO0702$Q_RTC_SEC = -1337982976; ! TOY clock CSR--seconds literal IO0702$Q_RTC_ALMS = -1337982968; ! TOY clock CSR--seconds alarm literal IO0702$Q_RTC_MIN = -1337982960; ! TOY clock CSR--minutes literal IO0702$Q_RTC_ALMN = -1337982952; ! TOY clock CSR--minutes alarm literal IO0702$Q_RTC_HOUR = -1337982944; ! TOY clock CSR--hours literal IO0702$Q_RTC_ALMH = -1337982936; ! TOY clock CSR--hours alarm literal IO0702$Q_RTC_DOW = -1337982928; ! TOY clock CSR--day of week literal IO0702$Q_RTC_DAY = -1337982920; ! TOY clock CSR--date of month literal IO0702$Q_RTC_MON = -1337982912; ! TOY clock CSR--month literal IO0702$Q_RTC_YEAR = -1337982904; ! TOY clock CSR--year literal IO0702$Q_RTC_REGA = -1337982896; ! TOY clock CSR--register A literal IO0702$Q_RTC_REGB = -1337982888; ! TOY clock CSR--register B literal IO0702$Q_RTC_REGC = -1337982880; ! TOY clock CSR--register C literal IO0702$Q_RTC_REGD = -1337982872; ! TOY clock CSR--register D literal IO0702$Q_RTC_RAM = -1337982864; ! TOY clock CSR--base of BBU RAM literal IO0702$Q_ISDN_AUDIO = -1337458688; ! ISDN audio chip CSR literal IO0702$Q_SYSTEM_EEPROM = -1073741824; ! base of system ROM, part 1 literal IO0702$Q_CPYBUF0 = -1072693248; literal IO0702$Q_CPYBUF1 = -1072693244; literal IO0702$Q_CPYBUF2 = -1072693240; literal IO0702$Q_CPYBUF3 = -1072693236; literal IO0702$Q_CPYBUF4 = -1072693232; literal IO0702$Q_CPYBUF5 = -1072693228; literal IO0702$Q_CPYBUF6 = -1072693224; literal IO0702$Q_CPYBUF7 = -1072693220; literal IO0702$Q_FG = -1072693216; literal IO0702$Q_BG = -1072693212; literal IO0702$Q_PLANEMASK = -1072693208; literal IO0702$Q_PIXMASK = -1072693204; literal IO0702$Q_MODE = -1072693200; literal IO0702$Q_BOOLOP = -1072693196; literal IO0702$Q_PIXSHIFT = -1072693192; literal IO0702$Q_ADDR_REG = -1072693188; literal IO0702$Q_BRES1 = -1072693184; literal IO0702$Q_BRES2 = -1072693180; literal IO0702$Q_BRES3 = -1072693176; literal IO0702$Q_BCONT = -1072693172; literal IO0702$Q_DEEP = -1072693168; literal IO0702$Q_START = -1072693164; literal IO0702$Q_CI = -1072693160; literal IO0702$Q_V_REF_COUNT = -1072693152; literal IO0702$Q_V_HOR = -1072693148; literal IO0702$Q_V_VER = -1072693144; literal IO0702$Q_V_BASE_ADDR = -1072693140; literal IO0702$Q_VV = -1072693136; literal IO0702$Q_EI = -1072693132; literal IO0702$Q_TCCLK_COUNT = -1072693128; literal IO0702$Q_VIDCLK_COUNT = -1072693124; literal IO0702$Q_RAMDAC_ADDR_LO = -1071906816; literal IO0702$Q_RAMDAC_ADDR_HI = -1071906812; literal IO0702$Q_RAMDAC_REG_ADDR = -1071906808; literal IO0702$Q_RAMDAC_MAP_LOC = -1071906804; literal IO0702$Q_FB = -1071644672; literal IO0702$Q_SLOT0_DENSE_BASE = 0; literal IO0702$Q_SLOT1_DENSE_BASE = 536870912; literal IO0702$Q_SLOT4_DENSE_BASE = -2147483648; literal IO0702$Q_SLOT5_DENSE_BASE = -1610612736; literal IO0702$Q_SLOT6_DENSE_BASE = -1073741824; literal IO0702$Q_SLOT0_SPARSE_BASE = 268435456; literal IO0702$Q_SLOT1_SPARSE_BASE = 805306368; literal IO0702$Q_SLOT4_SPARSE_BASE = -1879048192; literal IO0702$Q_SLOT5_SPARSE_BASE = -1342177280; literal IO0702$Q_LDP_DENSE = -1610350560; ! Ethernet DMA pointer literal IO0702$Q_NI_ADR_ROM_DENSE = -1610088448; ! Ethernet address ROM literal IO0702$Q_LANCE_RDP_DENSE = -1609826304; ! Lance ethernet CSR !*** MODULE $IO0802DEF *** literal IO0802$Q_PCI_IO = -2147483648; ! 1 8000 0000 ! One 8 KB page can map the following APC control registers literal IO0802$Q_APC_CONTROL = -805306368; ! 1 D000 0000 literal IO0802$Q_APC_HAE = -805306368; ! 1 D000 0000 literal IO0802$Q_APC_INTERVAL_TIMER = -805306240; ! 1 D000 0080 literal IO0802$Q_APC_BUFFER_STATUS = -805306176; ! 1 D000 00C0 literal IO0802$Q_APC_ERROR_STATUS = -805306112; ! 1 D000 0100 literal IO0802$Q_APC_ERROR_MASK = -805306048; ! 1 D000 0140 literal IO0802$Q_APC_LAST_PREFIX = -805305984; ! 1 D000 0180 literal IO0802$Q_APC_LOCK_ADDRESS = -805305920; ! 1 D000 01C0 literal IO0802$Q_APC_LOCAL_DEVICE_PORT = -805305856; ! 1 D000 0200 literal IO0802$Q_APC_MISC_DATA0 = -805305728; ! 1 D000 0280 literal IO0802$Q_APC_MISC_DATA1 = -805305664; ! 1 D000 02C0 ! The prefix registers occupy 16 KB. Use 2 8 KB pages to map. literal IO0802$Q_APC_PREFIX = -788529152; ! 1 d100 0000 ! One 8 KB page can map the APC configuration and diagnostic registers literal IO0802$Q_APC_CONFIG = -536870912; ! 1 e000 0000 literal IO0802$Q_APC_CACHE_CONTROL = -536870912; ! 1 e000 0000 literal IO0802$Q_APC_PCI_CONFIG = -536870784; ! 1 e000 0080 literal IO0802$Q_APC_PCI_STATUS = -536870720; ! 1 e000 00C0 literal IO0802$Q_APC_MEM_BANK_01 = -536870656; ! 1 e000 0100 literal IO0802$Q_APC_MEM_BANK_23 = -536870624; ! 1 e000 0120 literal IO0802$Q_APC_MEM_BANK_45 = -536870592; ! 1 e000 0140 literal IO0802$Q_APC_MEM_BANK_67 = -536870560; ! 1 e000 0160 literal IO0802$Q_APC_MEM_CONTROL = -536870528; ! 1 e000 0180 literal IO0802$Q_APC_EXT_PC_HOLE = -536870464; ! 1 e000 01C0 literal IO0802$Q_APC_EXT_PROG_HOLE = -536870432; ! 1 e000 01E0 literal IO0802$Q_APC_DIAG_CONTROL = -536870400; ! 1 e000 0200 literal IO0802$Q_APC_DIAG_DATA0 = -536870272; ! 1 e000 0280 literal IO0802$Q_APC_DIAG_DATA1 = -536870208; ! 1 e000 02C0 literal IO0802$Q_APC_REV_LEVEL = -536870144; ! 1 e000 0300 literal IO0802$Q_APC_PARITY_CONTROL = -536870080; ! 1 e000 0340 literal IO0802$Q_APC_SM_ADDRESS = -536869888; ! 1 e000 0400 literal IO0802$Q_APC_SM_DATA = -536869824; ! 1 e000 0440 literal IO0802$Q_PCI_SPARSE_MEM = 0; ! 2 0000 0000 literal IO0802$Q_PCI_DENSE_MEM = 0; ! 3 0000 0000 !*** MODULE $IO0902DEF *** literal IO0902$Q_CPU0_PA_L = -2147483648; literal IO0902$Q_CPU0_PA_H = 131; literal IO0902$Q_CPU1_PA_L = -2130706432; literal IO0902$Q_CPU1_PA_H = 131; literal IO0902$Q_CPU2_PA_L = -2113929216; literal IO0902$Q_CPU2_PA_H = 131; literal IO0902$Q_CPU3_PA_L = -2097152000; literal IO0902$Q_CPU3_PA_H = 131; literal IO0902$Q_SMM0_PA_L = -2013265920; literal IO0902$Q_SMM0_PA_H = 131; literal IO0902$Q_SMM1_PA_L = -1996488704; literal IO0902$Q_SMM1_PA_H = 131; literal IO0902$Q_SMM2_PA_L = -1979711488; literal IO0902$Q_SMM2_PA_H = 131; literal IO0902$Q_SMM3_PA_L = -1962934272; literal IO0902$Q_SMM3_PA_H = 131; literal IO0902$Q_T2IO_PA_L = -1912602624; literal IO0902$Q_T2IO_PA_H = 131; literal IO0902$Q_EIO_PA_L = -1895825408; literal IO0902$Q_EIO_PA_H = 131; literal IO0902$Q_IIC_PA_L = -1610570240; literal IO0902$Q_IIC_PA_H = 131; literal IO0902$Q_DS1287_PA_L = -1610609152; literal IO0902$Q_DS1287_PA_H = 131; literal IO0902$Q_MASTER_ICR_L = -1610570112; literal IO0902$Q_MASTER_ICR_H = 131; literal IO0902$Q_SLAVE0_ICR_L = -1610570048; literal IO0902$Q_SLAVE0_ICR_H = 131; literal IO0902$Q_SLAVE1_ICR_L = -1610569920; literal IO0902$Q_SLAVE1_ICR_H = 131; literal IO0902$Q_SLAVE2_ICR_L = -1610569856; literal IO0902$Q_SLAVE2_ICR_H = 131; literal IO0902$L_MASTER_ICR_PCI = 1332; literal IO0902$L_SLAVE0_ICR_PCI = 1334; literal IO0902$L_SLAVE1_ICR_PCI = 1338; literal IO0902$L_SLAVE2_ICR_PCI = 1340; literal IO0902$L_SLAVE3_ICR_PCI = 1342; literal IO0902$L_SLAVE4_ICR_PCI = 1336; literal IO0902$L_ESC_INT1_ICR = 32; literal IO0902$L_ESC_INT2_ICR = 160; literal IO0902$Q_MASTER_IMR_L = -1610570080; literal IO0902$Q_MASTER_IMR_H = 131; literal IO0902$Q_SLAVE0_IMR_L = -1610570016; literal IO0902$Q_SLAVE0_IMR_H = 131; literal IO0902$Q_SLAVE1_IMR_L = -1610569888; literal IO0902$Q_SLAVE1_IMR_H = 131; literal IO0902$Q_SLAVE2_IMR_L = -1610569824; literal IO0902$Q_SLAVE2_IMR_H = 131; literal IO0902$L_MASTER_IMR_PCI = 1333; literal IO0902$L_SLAVE0_IMR_PCI = 1335; literal IO0902$L_SLAVE1_IMR_PCI = 1339; literal IO0902$L_SLAVE2_IMR_PCI = 1341; literal IO0902$L_SLAVE3_IMR_PCI = 1343; literal IO0902$L_SLAVE4_IMR_PCI = 1337; literal IO0902$L_ESC_INT1_IMR = 33; literal IO0902$L_ESC_INT2_IMR = 161; literal IO0902$Q_SLU0_RCV_BUF_L = -1610580224; literal IO0902$Q_SLU0_RCV_BUF_H = 131; literal IO0902$Q_SLU0_IER_L = -1610580192; literal IO0902$Q_SLU0_IER_H = 131; literal IO0902$Q_SLU0_IIR_L = -1610580160; literal IO0902$Q_SLU0_IIR_H = 131; literal IO0902$Q_SLU0_L_CTL_L = -1610580128; literal IO0902$Q_SLU0_L_CTL_H = 131; literal IO0902$Q_SLU0_M_CTL_L = -1610580096; literal IO0902$Q_SLU0_M_CTL_H = 131; literal IO0902$Q_SLU0_L_STAT_L = -1610580064; literal IO0902$Q_SLU0_L_STAT_H = 131; literal IO0902$Q_SLU0_M_STAT_L = -1610580032; literal IO0902$Q_SLU0_M_STAT_H = 131; literal IO0902$L_SLU0_RCV_BUF_PCI = 1016; literal IO0902$L_SLU0_IER_PCI = 1017; literal IO0902$L_SLU0_IIR_PCI = 1018; literal IO0902$L_SLU0_L_CTL_PCI = 1019; literal IO0902$L_SLU0_M_CTL_PCI = 1020; literal IO0902$L_SLU0_L_STAT_PCI = 1021; literal IO0902$L_SLU0_M_STAT_PCI = 1022; literal IO0902$Q_SLU1_RCV_BUF_L = -1610588416; literal IO0902$Q_SLU1_RCV_BUF_H = 131; literal IO0902$Q_SLU1_IER_L = -1610588384; literal IO0902$Q_SLU1_IER_H = 131; literal IO0902$Q_SLU1_IIR_L = -1610588352; literal IO0902$Q_SLU1_IIR_H = 131; literal IO0902$Q_SLU1_L_CTL_L = -1610588320; literal IO0902$Q_SLU1_L_CTL_H = 131; literal IO0902$Q_SLU1_M_CTL_L = -1610588288; literal IO0902$Q_SLU1_M_CTL_H = 131; literal IO0902$Q_SLU1_L_STAT_L = -1610588256; literal IO0902$Q_SLU1_L_STAT_H = 131; literal IO0902$Q_SLU1_M_STAT_L = -1610588224; literal IO0902$Q_SLU1_M_STAT_H = 131; literal IO0902$L_SLU1_RCV_BUF_PCI = 760; literal IO0902$L_SLU1_IER_PCI = 761; literal IO0902$L_SLU1_IIR_PCI = 762; literal IO0902$L_SLU1_L_CTL_PCI = 763; literal IO0902$L_SLU1_M_CTL_PCI = 764; literal IO0902$L_SLU1_L_STAT_PCI = 765; literal IO0902$L_SLU1_M_STAT_PCI = 766; literal IO0902$B_KBD_CMD_PCI = 100; literal IO0902$B_KBD_DATA_PCI = 96; literal IO0902$Q_KBD_CMD_L = -1610609536; literal IO0902$Q_KBD_CMD_H = 131; literal IO0902$Q_KBD_DATA_L = -1610609664; literal IO0902$Q_KBD_DATA_H = 131; literal IO0902$Q_PCI_SLOT0_CFG_PA_L = -1878982656; literal IO0902$Q_PCI_SLOT0_CFG_PA_H = 131; literal IO0902$Q_PCI_SLOT1_CFG_PA_L = -1878917120; literal IO0902$Q_PCI_SLOT1_CFG_PA_H = 131; literal IO0902$Q_PCI_SLOT2_CFG_PA_L = -1878786048; literal IO0902$Q_PCI_SLOT2_CFG_PA_H = 131; literal IO0902$Q_PCI_SLOT3_CFG_PA_L = -1878523904; literal IO0902$Q_PCI_SLOT3_CFG_PA_H = 131; literal IO0902$Q_PCI_SLOT4_CFG_PA_L = -1877999616; literal IO0902$Q_PCI_SLOT4_CFG_PA_H = 131; literal IO0902$Q_PCI_SLOT5_CFG_PA_L = -1876951040; literal IO0902$Q_PCI_SLOT5_CFG_PA_H = 131; literal IO0902$Q_PCI_SLOT6_CFG_PA_L = -1874853888; literal IO0902$Q_PCI_SLOT6_CFG_PA_H = 131; literal IO0902$Q_PCI_SLOT7_CFG_PA_L = -1870659584; literal IO0902$Q_PCI_SLOT7_CFG_PA_H = 131; literal IO0902$Q_PCI_SLOT8_CFG_PA_L = -1862270976; literal IO0902$Q_PCI_SLOT8_CFG_PA_H = 131; literal IO0902$Q_PCI_SLOT9_CFG_PA_L = -1845493760; literal IO0902$Q_PCI_SLOT9_CFG_PA_H = 131; literal IO0902$Q_PCI_SLOT10_CFG_PA_L = -1811939328; literal IO0902$Q_PCI_SLOT10_CFG_PA_H = 131; literal IO0902$Q_PCI_SPARSE_IO_L = -1610612736; literal IO0902$Q_PCI_SPARSE_IO_H = 131; literal IO0902$Q_PCI_SPARSE_MEM_L = 0; literal IO0902$Q_PCI_SPARSE_MEM_H = 130; literal IO0902$Q_PCI_DENSE_MEM_L = -1073741824; literal IO0902$Q_PCI_DENSE_MEM_H = 131; literal IO0902$Q_PCI_CONFIG_SPACE_L = -1879048192; literal IO0902$Q_PCI_CONFIG_SPACE_H = 131; literal IO0902$Q_PCI_EIO_SPARSE_IO_L = -1073741824; literal IO0902$Q_PCI_EIO_SPARSE_IO_H = 129; literal IO0902$Q_PCI_EIO_SPARSE_MEM_L = 0; literal IO0902$Q_PCI_EIO_SPARSE_MEM_H = 131; literal IO0902$Q_PCI_EIO_DENSE_MEM_L = -2147483648; literal IO0902$Q_PCI_EIO_DENSE_MEM_H = 129; literal IO0902$Q_PCI_EIO_CONFIG_SPACE_L = -1744830464; literal IO0902$Q_PCI_EIO_CONFIG_SPACE_H = 131; literal IO0902$Q_T4MASTER_ICR_L = -1073699200; literal IO0902$Q_T4MASTER_ICR_H = 129; literal IO0902$Q_T4SLAVE0_ICR_L = -1073699136; literal IO0902$Q_T4SLAVE0_ICR_H = 129; literal IO0902$Q_T4MASTER_IMR_L = -1073699168; literal IO0902$Q_T4MASTER_IMR_H = 129; literal IO0902$Q_T4SLAVE0_IMR_L = -1073699104; literal IO0902$Q_T4SLAVE0_IMR_H = 129; literal IO0902$K_T2_VECTOR_COUNT = 56; literal IO0902$K_T3_VECTOR_COUNT = 64; literal IO0902$K_EXTIO_VECTOR_COUNT = 16; !*** MODULE $IO0C05DEF *** literal IO0C05$L_IO_PA_H = 3968; literal IO0C05$L_NODE_PA_H = 4095; literal IO0C05$L_NODE0_PA_L = -2013265920; literal IO0C05$L_NODE1_PA_L = -2009071616; literal IO0C05$L_NODE2_PA_L = -2004877312; literal IO0C05$L_NODE3_PA_L = -2000683008; literal IO0C05$L_NODE4_PA_L = -1996488704; literal IO0C05$L_NODE5_PA_L = -1992294400; literal IO0C05$L_NODE6_PA_L = -1988100096; literal IO0C05$L_NODE7_PA_L = -1983905792; literal IO0C05$L_NODE8_PA_L = -1979711488; literal IO0C05$L_BROADCAST_L = -1912602624; ! BROADCAST SPACE literal IO0C05$L_UART0_L = -1610612736; ! UART 0 literal IO0C05$L_UART1_L = -1593835520; ! UART 1 literal IO0C05$L_WATCH_L = -1342177280; ! WATCH CHIP literal IO0C05$L_GBUS_L = -1073741824; ! GBUS literal IO0C05$K_TLIPINTR = 64; ! IP INTR REG literal IO0C05$K_TLIOINTR4 = 256; ! I/O INT REG 4 literal IO0C05$K_TLIOINTR5 = 320; ! I/O INT REG 5 literal IO0C05$K_TLIOINTR6 = 384; ! I/O INT REG 6 literal IO0C05$K_TLIOINTR7 = 448; ! I/O INT REG 4 literal IO0C05$K_TLIOINTR8 = 512; ! I/O INT REG 7 literal IO0C05$K_TLWSDQR4 = 1024; ! WIND SPACE DC4 literal IO0C05$K_TLWSDQR5 = 1088; ! WIND SPACE DC5 literal IO0C05$K_TLWSDQR6 = 1152; ! WIND SPACE DC6 literal IO0C05$K_TLWSDQR7 = 1216; ! WIND SPACE DC7 literal IO0C05$K_TLWSDQR8 = 1280; ! WIND SPACE DC8 literal IO0C05$K_TLRMDQRX = 1536; ! RM DEC CNT X literal IO0C05$K_TLRMDQR8 = 1600; ! RM DEC CNT 8 literal IO0C05$K_TLRDRD = 2048; ! WIND SP RD DATA DATA literal IO0C05$K_TLRDRE = 2112; ! WIND SP RD DATA ERR literal IO0C05$K_B_RR0 = 0; literal IO0C05$K_B_RR8 = 64; literal IO0C05$K_A_RR0 = 128; literal IO0C05$K_A_RR8 = 192; literal IO0C05$K_SECONDS = 0; literal IO0C05$K_MINUTES = 128; literal IO0C05$K_HOURS = 256; literal IO0C05$K_DAY_OF_MONTH = 448; literal IO0C05$K_MONTH = 512; literal IO0C05$K_YEAR = 576; literal IO0C05$K_CSRA = 640; literal IO0C05$K_CSRB = 704; literal IO0C05$K_CSRC = 768; literal IO0C05$K_CSRD = 832; literal IO0C05$K_RAM = 896; literal IO0C05$K_WHAMI = 0; literal IO0C05$K_LED0 = 16777216; literal IO0C05$K_LED1 = 33554432; literal IO0C05$K_LED2 = 50331648; literal IO0C05$K_MISCR = 67108864; literal IO0C05$K_MISCW = 83886080; literal IO0C05$K_TLSBRST = 100663296; literal IO0C05$K_SERNUM = 117440512; literal IO0C05$K_TEST = 134217728; literal IO0C05$K_TLDEV = 0; ! DEVICE literal IO0C05$K_TLBER = 64; ! ERROR literal IO0C05$K_TLCNR = 128; ! CONFIGURATION literal IO0C05$K_TLVID = 192; ! VIRT ID literal IO0C05$K_TLMMR0 = 512; ! MEM MAPPING 0 literal IO0C05$K_TLMMR1 = 576; ! MEM MAPPING 1 literal IO0C05$K_TLMMR2 = 640; ! MEM MAPPING 2 literal IO0C05$K_TLMMR3 = 704; ! MEM MAPPING 3 literal IO0C05$K_TLMMR4 = 768; ! MEM MAPPING 4 literal IO0C05$K_TLMMR5 = 832; ! MEM MAPPING 5 literal IO0C05$K_TLMMR6 = 896; ! MEM MAPPING 6 literal IO0C05$K_TLMMR7 = 960; ! MEM MAPPING 7 literal IO0C05$K_TLFADR0 = 1536; ! FAILING ADDR 0 literal IO0C05$K_TLFADR1 = 1600; ! FAILING ADDR 1 literal IO0C05$K_TLESR0 = 1664; ! BUS ERROR SYNDROME 0 literal IO0C05$K_TLESR1 = 1728; ! BUS ERROR SYNDROME 1 literal IO0C05$K_TLESR2 = 1792; ! BUS ERROR SYNDROME 2 literal IO0C05$K_TLESR3 = 1856; ! BUS ERROR SYNDROME 3 literal IO0C05$K_TLILID0 = 2560; ! TIOP INT LVL 0 literal IO0C05$K_TLILID1 = 2624; ! TIOP INT LVL 1 literal IO0C05$K_TLILID2 = 2688; ! TIOP INT LVL 2 literal IO0C05$K_TLILID3 = 2752; ! TIOP INT LVL 3 literal IO0C05$K_TLCPUMASK = 2816; ! TIOP CPU INT MASK literal IO0C05$K_TLMBPR = 3072; ! TIOP MBX PNTR REG literal IO0C05$K_TLDIAG = 4096; ! TLEP DIAG SETUP literal IO0C05$K_TLDTAGDATA = 4160; ! TLEP DTAG DATA literal IO0C05$K_TLDTAGSTAT = 4224; ! TLEP DTAG STAT literal IO0C05$K_TLMODCONFIG = 4288; ! TLEP MOD CONFIG literal IO0C05$K_TLINTRMASK0 = 4352; ! TLEP INT MASK 0 literal IO0C05$K_TLINTRMASK1 = 4416; ! TLEP INT MASK 1 literal IO0C05$K_TLINTRSUM0 = 4480; ! TLEP INT SUM 0 literal IO0C05$K_TLINTRSUM1 = 4544; ! TLEP INT SUM 1 literal IO0C05$K_TLCON00 = 4608; ! TLEP CONS COMM literal IO0C05$K_TLCON00A = 4672; ! TLEP DIGA COMM TEST literal IO0C05$K_TLCON00B = 4736; ! TLEP DIGA COMM TEST literal IO0C05$K_TLCON00C = 4800; ! TLEP DIGA COMM TEST literal IO0C05$K_TLCON10 = 4864; ! TLEP CONS COMM literal IO0C05$K_TLCON10A = 4928; ! TLEP DIGA COMM TEST literal IO0C05$K_TLCON10B = 4992; ! TLEP DIGA COMM TEST literal IO0C05$K_TLCON10C = 5056; ! TLEP DIGA COMM TEST literal IO0C05$K_TLCON01 = 5120; ! TLEP CONS COMM literal IO0C05$K_TLCON11 = 5184; ! TLEP CONS COMM literal IO0C05$K_TLEPAERR = 5376; ! TLEP ADG ERROR literal IO0C05$K_TLEPDERR = 5440; ! TLEP DIGA ERROR literal IO0C05$K_TLEPMERR = 5504; ! TLEP MMG ERROR literal IO0C05$K_TLEP_VMG = 5568; ! TLEP VOLT MARG literal IO0C05$K_TLDMCMD = 5632; ! TLEP DM CMD literal IO0C05$K_TLDMADRA = 5760; ! TLEP DM A literal IO0C05$K_TLDMADRB = 5824; ! TLEP DM B literal IO0C05$K_TLPM_CMD = 6144; ! TLEP PERF MON CMD literal IO0C05$K_TLPM_TOT_CYC = 6208; ! TLEP # OF CYCLES literal IO0C05$K_TLPM_EV5_LAT = 6272; ! TLEP EV5 RD LAT literal IO0C05$K_TLPM_READ_LAT = 6336; ! TLEP AV RD LAT literal IO0C05$K_TLPM_SYS_OWNER = 6400; ! TLEP # CYC OF SYS OWNER literal IO0C05$K_TLPM_CMD_SILO = 6464; ! TLEP CMD SILO literal IO0C05$K_TLPM_LOCK = 6528; ! TLEP # LOCK ACKS literal IO0C05$K_TLPM_MB = 6592; ! TLEP # MB ACKS literal IO0C05$K_TLPM_SD_TOTAL = 6656; ! TLEP # SD literal IO0C05$K_TLPM_SD_ACKED = 6720; ! TLEP # SD ACKS literal IO0C05$K_TLPM_RD_CSR = 6784; ! TLEP # CSR RDS literal IO0C05$K_TLPM_RD = 6848; ! TLEP # MEM RD MISS literal IO0C05$K_TLPM_RD_MOD = 6912; ! TLEP # RD MISS MODS literal IO0C05$K_TLPM_RD_STC = 6976; ! TLEP # RD MISS STXC literal IO0C05$K_TLPM_VICTIM = 7040; ! TLEP # BC VICTIMS literal IO0C05$K_TLPM_WR_CSR = 7104; ! TLEP # CSR WR CMDS literal IO0C05$K_TLPM_WR = 7168; ! TLEP # WR BLK CMDS ACKED literal IO0C05$K_TLPM_WR_LOCK = 7232; ! TLEP # WR BLK LK CMDS ACKED literal IO0C05$K_TLPM_INVAL = 7296; ! TLEP # INVAL literal IO0C05$K_TLPM_SET_SHRD = 7360; ! TLEP # SET SHRDS literal IO0C05$K_TLPM_RD_DIRTY = 7424; ! TLEP # RD DIRTYS literal IO0C05$K_TLPM_ADR_SILO = 7488; ! TLEP ADR SILO REG literal IO0C05$K_RM_RANG_REG0A = 7680; ! TLEP RM MR CHAN0A literal IO0C05$K_RM_RANG_REG0B = 7744; ! TLEP RM MR CHAN0B literal IO0C05$K_RM_RANG_REG1A = 7808; ! TLEP RM MR CHAN1A literal IO0C05$K_RM_RANG_REG1B = 7872; ! TLEP RM MR CHAN1B literal IO0C05$K_TLMODCONFIG0 = 4096; ! TL-6 MODULE CONFIG REG 0 literal IO0C05$K_TLDTAGADDR = 4224; ! TL-6 DTAG ADDRESS REG literal IO0C05$K_TLMODCONFIG1 = 4288; ! TL-6 MODULE CONFIG REG 1 literal IO0C05$K_TCCERR = 5376; ! TL-6 TCC ERROR REGISTER literal IO0C05$K_TDIERR = 5440; ! TL-6 TDI ERROR REGISTER literal IO0C05$K_TL6_VMG = 5568; ! TL-6 VOLTAGE MARGINING REG literal IO0C05$K_TL6WERR = 5632; ! TL-6 WINDOW SPACE ERROR REG literal IO0C05$K_TLDTAGEX = 6144; ! TL-6 DTAG TEST EXECUTE REG literal IO0C05$K_TLLOOPBCK = 6208; ! TL-6 DIAG LOOPBACK REG. literal IO0C05$K_TLICCMSR = 8192; ! TIOP I/O CNTRL CHIP MODE SEL literal IO0C05$K_TLICCNSE = 8256; ! TIOP I/O CNTRL CHIP NODE SPEC ERR literal IO0C05$K_TLICCDR = 8320; ! TIOP I/O CNTRL CHIP DIAG REG literal IO0C05$K_TLICCMTR = 8384; ! TIOP I/O CNTRL CHIP MBX TRANS REG literal IO0C05$K_TLICCWRT = 8448; ! TIOP I/O CNTRL CHIP CSR WIND TRANS literal IO0C05$K_TLIDPNSE1 = 8512; ! TIOP NODE SPEC DPATH ERROR 1 literal IO0C05$K_TLIDPDR1 = 8576; ! TIOP I/O DPATH DIAG REG 1 literal IO0C05$K_TLIDPNSE2 = 8768; ! TIOP NODE SPEC DPATH ERROR 2 literal IO0C05$K_TLIDPDR2 = 8832; ! TIOP I/O DPATH DIAG REG 2 literal IO0C05$K_TLIDPNSE3 = 9024; ! TIOP NODE SPEC DPATH ERROR 3 literal IO0C05$K_TLIDPDR3 = 9088; ! TIOP I/O DPATH DIAG REG 3 literal IO0C05$K_TLIDPNSE0 = 10816; ! TIOP NODE SPEC DPATH ERROR 0 literal IO0C05$K_TLIDPDR0 = 10880; ! TIOP I/O DPATH DIAG REG 0 literal IO0C05$K_TLIPCPUMASK = 10944; ! TIOP IP CPU INTR MASK literal IO0C05$K_TLIDPVR = 11072; ! TIOP I/O DPATH VECT literal IO0C05$K_TLIDPMSR = 11136; ! TIOP I/O DPATH MODE SEL literal IO0C05$K_TLIBR = 11200; ! TIOP INFO BASE REPAIR literal IO0C05$K_TLDHRR0A = 12288; ! TIOP DOWN HOSE RANGE REGISTER 0A literal IO0C05$K_TLDHRR0B = 12352; ! TIOP DOWN HOSE RANGE REGISTER 0B literal IO0C05$K_TLDHRR1A = 12416; ! TIOP DOWN HOSE RANGE REGISTER 1A literal IO0C05$K_TLDHRR1B = 12480; ! TIOP DOWN HOSE RANGE REGISTER 1B literal IO0C05$K_TLSECR = 6144; ! TLMEM SECR EEPROM CNTL literal IO0C05$K_TLMIR = 6208; ! TLMEM MEM INTERLEAVE literal IO0C05$K_TLMCR = 6272; ! TLMEM MEM CONFIG literal IO0C05$K_TLSTAIR = 6336; ! TLMEM SELFTEST ADR ISOL literal IO0C05$K_TLSTER = 6400; ! TLMEM SELFTEST ERR REG literal IO0C05$K_TLMER = 6464; ! TLMEM MEM ERROR REG literal IO0C05$K_TLMDRA = 6528; ! TLMEM MEM DIAG REG A literal IO0C05$K_TLMDRB = 6592; ! TLMEM MEM DIAG REG B literal IO0C05$K_TLSTDERA_0 = 65536; ! TLMEM SELFTEST DATA ERR REG A0 literal IO0C05$K_TLSTDERB_0 = 65600; ! TLMEM SELFTEST DATA ERR REG B0 literal IO0C05$K_TLSTDERC_0 = 65664; ! TLMEM SELFTEST DATA ERR REG C0 literal IO0C05$K_TLSTDERD_0 = 65728; ! TLMEM SELFTEST DATA ERR REG D0 literal IO0C05$K_TLSTDERE_0 = 65792; ! TLMEM SELFTEST DATA ERR REG E0 literal IO0C05$K_TLDDR0 = 65856; ! TLMEM DATA DIAG REG 0 literal IO0C05$K_TLSTDERA_1 = 81920; ! TLMEM SELFTEST DATA ERR REG A1 literal IO0C05$K_TLSTDERB_1 = 81984; ! TLMEM SELFTEST DATA ERR REG B1 literal IO0C05$K_TLSTDERC_1 = 82048; ! TLMEM SELFTEST DATA ERR REG C1 literal IO0C05$K_TLSTDERD_1 = 82112; ! TLMEM SELFTEST DATA ERR REG D1 literal IO0C05$K_TLSTDERE_1 = 82176; ! TLMEM SELFTEST DATA ERR REG E1 literal IO0C05$K_TLDDR1 = 82240; ! TLMEM DATA DIAG REG 1 literal IO0C05$K_TLSTDERA_2 = 98304; ! TLMEM SELFTEST DATA ERR REG A2 literal IO0C05$K_TLSTDERB_2 = 98368; ! TLMEM SELFTEST DATA ERR REG B2 literal IO0C05$K_TLSTDERC_2 = 98432; ! TLMEM SELFTEST DATA ERR REG C2 literal IO0C05$K_TLSTDERD_2 = 98496; ! TLMEM SELFTEST DATA ERR REG D2 literal IO0C05$K_TLSTDERE_2 = 98560; ! TLMEM SELFTEST DATA ERR REG E2 literal IO0C05$K_TLDDR2 = 98624; ! TLMEM DATA DIAG REG 2 literal IO0C05$K_TLSTDERA_3 = 114688; ! TLMEM SELFTEST DATA ERR REG A3 literal IO0C05$K_TLSTDERB_3 = 114752; ! TLMEM SELFTEST DATA ERR REG B3 literal IO0C05$K_TLSTDERC_3 = 114816; ! TLMEM SELFTEST DATA ERR REG C3 literal IO0C05$K_TLSTDERD_3 = 114880; ! TLMEM SELFTEST DATA ERR REG D3 literal IO0C05$K_TLSTDERE_3 = 114944; ! TLMEM SELFTEST DATA ERR REG E3 literal IO0C05$K_TLDDR3 = 115008; ! TLMEM DATA DIAG REG 3 !*** MODULE $IO0E04DEF *** literal IO0E04$L_IOC_IACK_SC_PA_L = -1073741824; literal IO0E04$L_IOC_IACK_SC_PA_H = 1; literal IO0E04$L_CFG_CYCLE_PA_L = -2147483648; literal IO0E04$L_CFG_CYCLE_PA_H = 1; literal IO0E04$L_TB_EN_PA_L = -2147483648; literal IO0E04$L_TB_EN_PA_H = 1; literal IO0E04$L_PCI_SFT_RST_PA_L = -2147483648; literal IO0E04$L_PCI_SFT_RST_PA_H = 1; literal IO0E04$L_PCI_PAR_DISABLE_PA_L = -2147483648; literal IO0E04$L_PCI_PAR_DISABLE_PA_H = 1; literal IO0E04$L_PCI_IO_PA_L = 0; literal IO0E04$L_PCI_IO_PA_H = 3; literal IO0E04$L_PCI_IO_END_PA_L = 2097152; literal IO0E04$L_PCI_IO_END_PA_H = 3; literal IO0E04$L_KBD_DATA_PA_L = 3072; literal IO0E04$L_KBD_DATA_PA_H = 3; literal IO0E04$B_KBD_DATA_PCI = 96; literal IO0E04$L_KBD_CMD_PA_L = 3200; literal IO0E04$L_KBD_CMD_PA_H = 3; literal IO0E04$B_KBD_CMD_PCI = 100; literal IO0E04$L_DS1287_PA_L = 3584; literal IO0E04$L_DS1287_PA_H = 3; literal IO0E04$L_COM1_PA_L = 32512; literal IO0E04$L_COM1_PA_H = 3; literal IO0E04$L_COM1_RCV_BUF_PCI = 1016; literal IO0E04$L_COM1_IER_PCI = 1017; literal IO0E04$L_COM1_IIR_PCI = 1018; literal IO0E04$L_COM1_L_CTL_PCI = 1019; literal IO0E04$L_COM1_M_CTL_PCI = 1020; literal IO0E04$L_COM1_L_STAT_PCI = 1021; literal IO0E04$L_COM1_M_STAT_PCI = 1022; literal IO0E04$L_COM2_PA_L = 24320; literal IO0E04$L_COM2_PA_H = 3; literal IO0E04$L_COM2_RCV_BUF_PCI = 760; literal IO0E04$L_COM2_IER_PCI = 761; literal IO0E04$L_COM2_IIR_PCI = 762; literal IO0E04$L_COM2_L_CTL_PCI = 763; literal IO0E04$L_COM2_M_CTL_PCI = 764; literal IO0E04$L_COM2_L_STAT_PCI = 765; literal IO0E04$L_COM2_M_STAT_PCI = 766; literal IO0E04$L_PPORT_PA_L = 28416; literal IO0E04$L_PPORT_PA_H = 3; literal IO0E04$L_FLOPPY_PA_L = 32256; literal IO0E04$L_FLOPPY_PA_H = 3; literal IO0E04$L_MASTER_ICR_PCI = 32; literal IO0E04$L_MASTER_IMR_PCI = 33; literal IO0E04$L_SLAVE_ICR_PCI = 160; literal IO0E04$L_SLAVE_IMR_PCI = 161; literal IO0E04$L_PCI_IRR_REG = 38; literal IO0E04$L_PCI_IMR_REG = 38; literal IO0E04$L_HAE_PA_L = -2147483648; literal IO0E04$L_HAE_PA_H = 1; literal IO0E04$L_IOC_STAT0_PA_L = -2147483584; literal IO0E04$L_IOC_STAT0_PA_H = 1; literal IO0E04$L_IOC_STAT1_PA_L = -2147483552; literal IO0E04$L_IOC_STAT1_PA_H = 1; literal IO0E04$L_IOC_TBIA_PA_L = -2147483520; literal IO0E04$L_IOC_TBIA_PA_H = 1; literal IO0E04$L_IOC_W_BASE_0_PA_L = -2147483392; literal IO0E04$L_IOC_W_BASE_0_PA_H = 1; literal IO0E04$L_IOC_W_BASE_1_PA_L = -2147483360; literal IO0E04$L_IOC_W_BASE_1_PA_H = 1; literal IO0E04$L_IOC_W_MASK_0_PA_L = -2147483328; literal IO0E04$L_IOC_W_MASK_0_PA_H = 1; literal IO0E04$L_IOC_W_MASK_1_PA_L = -2147483296; literal IO0E04$L_IOC_W_MASK_1_PA_H = 1; literal IO0E04$L_IOC_T_BASE_0_PA_L = -2147483264; literal IO0E04$L_IOC_T_BASE_0_PA_H = 1; literal IO0E04$L_IOC_T_BASE_1_PA_L = -2147483232; literal IO0E04$L_IOC_T_BASE_1_PA_H = 1; literal IO0E04$L_IOC_TB_TAG_0_PA_L = -2130706432; literal IO0E04$L_IOC_TB_TAG_0_PA_H = 1; literal IO0E04$L_IOC_TB_TAG_1_PA_L = -2130706400; literal IO0E04$L_IOC_TB_TAG_1_PA_H = 1; literal IO0E04$L_IOC_TB_TAG_2_PA_L = -2130706368; literal IO0E04$L_IOC_TB_TAG_2_PA_H = 1; literal IO0E04$L_IOC_TB_TAG_3_PA_L = -2130706336; literal IO0E04$L_IOC_TB_TAG_3_PA_H = 1; literal IO0E04$L_IOC_TB_TAG_4_PA_L = -2130706304; literal IO0E04$L_IOC_TB_TAG_4_PA_H = 1; literal IO0E04$L_IOC_TB_TAG_5_PA_L = -2130706272; literal IO0E04$L_IOC_TB_TAG_5_PA_H = 1; literal IO0E04$L_IOC_TB_TAG_6_PA_L = -2130706240; literal IO0E04$L_IOC_TB_TAG_6_PA_H = 1; literal IO0E04$L_IOC_TB_TAG_7_PA_L = -2130706208; literal IO0E04$L_IOC_TB_TAG_7_PA_H = 1; literal IO0E04$L_FLASH_ROM1_PA = 939524096; literal IO0E04$L_FLASH_ROM2_PA = 941621248; literal IO0E04$L_FLASH_ROM3_PA = 943718400; literal IO0E04$L_FLASH_ROM4_PA = 945815552; literal IO0E04$L_FLASH_ROM1_END_PA = 941621240; literal IO0E04$L_FLASH_ROM2_END_PA = 943718392; literal IO0E04$L_FLASH_ROM3_END_PA = 945815544; literal IO0E04$L_FLASH_ROM4_END_PA = 947912696; literal IO0E04$L_PCI_SPARSE_MEM_PA_L = 0; literal IO0E04$L_PCI_SPARSE_MEM_PA_H = 2; literal IO0E04$L_PCI_SPARSE_MEMEND_PA_L = 536870912; literal IO0E04$L_PCI_SPARSE_MEMEND_PA_H = 2; literal IO0E04$L_PCI_DENSE_MEM_PA_L = 0; literal IO0E04$L_PCI_DENSE_MEM_PA_H = 3; literal IO0E04$L_PCI_DENSE_MEM_END_PA_L = -1; literal IO0E04$L_PCI_DENSE_MEM_END_PA_H = 3; !*** MODULE $IO0F05DEF IDENT X-3 *** literal IO0F05$L_NODE_PA_H = 135; ! High order word literal IO0F05$L_CIA_GENERAL_L = 1073741824; literal IO0F05$L_CIA_MEMORY_L = 1342177280; literal IO0F05$L_CIA_PCI_ADDR_L = 1610612736; literal IO0F05$L_FLASH_AND_GRU_L = -2147483648; literal IO0F05$L_PCI_REV_L = 128; ! PCI revision literal IO0F05$L_PCI_LAT_L = 192; ! PCI Latency literal IO0F05$L_CIA_CTRL_L = 256; ! CIA COntrol literal IO0F05$L_HAE_MEM_L = 1024; ! HAE memory literal IO0F05$L_HAE_IO_L = 1088; ! HAE I/O literal IO0F05$L_HAE_CFG_L = 1152; ! COnfig literal IO0F05$L_CIA_CACK_EN_L = 1536; ! Ack control literal IO0F05$L_CIA_DIAG_L = 8192; ! Diag control literal IO0F05$L_CIA_CHECK_L = 12288; ! Diag check literal IO0F05$L_PERF_MON_L = 16384; ! Perf monitor literal IO0F05$L_PERF_CNTR_L = 16448; ! Perf control literal IO0F05$L_CPU_ERR0_L = 32768; ! Cpu err info 0 literal IO0F05$L_CPU_ERR1_L = 32832; ! Cpu err info 1 literal IO0F05$L_CIA_ERR_L = 33280; ! CIA err literal IO0F05$L_CIA_STAT_L = 33344; ! CIA status literal IO0F05$L_CIA_ERR_MSK_L = 33408; ! CIA err mask literal IO0F05$L_CIA_SYN_L = 33536; ! CIA syndrome literal IO0F05$L_CPU_MPSR0_L = 33792; ! Memport stat0 literal IO0F05$L_CPU_MPSR1_L = 33856; ! Memport stat1 literal IO0F05$L_PCI_ERR0_L = 34816; ! PCI Err 0 literal IO0F05$L_PCI_ERR1_L = 34880; ! PCI Err 1 literal IO0F05$L_PCI_ERR2_L = 34944; ! PCI Err 1 literal IO0F05$L_MEM_CNFG_L = 0; ! Memory config literal IO0F05$L_MEM_BA0_L = 1536; ! Mem base addr0 literal IO0F05$L_MEM_BA2_L = 1664; ! Mem base addr2 literal IO0F05$L_MEM_BA4_L = 1792; ! Mem base addr4 literal IO0F05$L_MEM_BA6_L = 1920; ! Mem base addr6 literal IO0F05$L_MEM_BA8_L = 2048; ! Mem base addr8 literal IO0F05$L_MEM_BAA_L = 2176; ! Mem base addrA literal IO0F05$L_MEM_BAC_L = 2304; ! Mem base addrC literal IO0F05$L_MEM_BAE_L = 2432; ! Mem base addrE literal IO0F05$L_MEM_TMG0_L = 2816; ! Mem timing 0 literal IO0F05$L_MEM_TMG1_L = 2880; ! Mem timing 1 literal IO0F05$L_MEM_TMG2_L = 2944; ! Mem timing 2 literal IO0F05$L_PCI_TBIA_L = 256; ! SG TB inval literal IO0F05$L_PCI_W0_BASE_L = 1024; ! Window base0 literal IO0F05$L_PCI_W0_MASK_L = 1088; ! Window mask0 literal IO0F05$L_PCI_T0_BASE_L = 1152; ! Trans base0 literal IO0F05$L_PCI_W1_BASE_L = 1280; ! Window base1 literal IO0F05$L_PCI_W1_MASK_L = 1344; ! Window mask1 literal IO0F05$L_PCI_T1_BASE_L = 1408; ! Trans base1 literal IO0F05$L_PCI_W2_BASE_L = 1536; ! Window base2 literal IO0F05$L_PCI_W2_MASK_L = 1600; ! Window mask2 literal IO0F05$L_PCI_T2_BASE_L = 1664; ! Trans base2 literal IO0F05$L_PCI_W3_BASE_L = 1792; ! Window base3 literal IO0F05$L_PCI_W3_MASK_L = 1856; ! Window mask3 literal IO0F05$L_PCI_T3_BASE_L = 1920; ! Trans base3 literal IO0F05$L_PCI_DAC_BASE_L = 1984; ! DAC Base literal IO0F05$L_PCI_LTB_TAG0_L = 2048; ! Lock TB tag0 literal IO0F05$L_PCI_LTB_TAG1_L = 2112; ! Lock TB tag1 literal IO0F05$L_PCI_LTB_TAG2_L = 2176; ! Lock TB tag2 literal IO0F05$L_PCI_LTB_TAG3_L = 2240; ! Lock TB tag3 literal IO0F05$L_PCI_TB_TAG0_L = 2304; ! TB tag0 literal IO0F05$L_PCI_TB_TAG1_L = 2368; ! TB tag1 literal IO0F05$L_PCI_TB_TAG2_L = 2432; ! TB tag2 literal IO0F05$L_PCI_TB_TAG3_L = 2496; ! TB tag3 literal IO0F05$L_PCI_TB0_PAGE0_L = 4096; ! TB0 page0 literal IO0F05$L_PCI_TB0_PAGE1_L = 4160; ! TB0 page1 literal IO0F05$L_PCI_TB0_PAGE2_L = 4224; ! TB0 page2 literal IO0F05$L_PCI_TB0_PAGE3_L = 4288; ! TB0 page3 literal IO0F05$L_PCI_TB1_PAGE0_L = 4352; ! TB1 page0 literal IO0F05$L_PCI_TB1_PAGE1_L = 4416; ! TB1 page1 literal IO0F05$L_PCI_TB1_PAGE2_L = 4480; ! TB1 page2 literal IO0F05$L_PCI_TB1_PAGE3_L = 4544; ! TB1 page3 literal IO0F05$L_PCI_TB2_PAGE0_L = 4608; ! TB2 page0 literal IO0F05$L_PCI_TB2_PAGE1_L = 4672; ! TB2 page1 literal IO0F05$L_PCI_TB2_PAGE2_L = 4736; ! TB2 page2 literal IO0F05$L_PCI_TB2_PAGE3_L = 4800; ! TB2 page3 literal IO0F05$L_PCI_TB3_PAGE0_L = 4864; ! TB3 page0 literal IO0F05$L_PCI_TB3_PAGE1_L = 4928; ! TB3 page1 literal IO0F05$L_PCI_TB3_PAGE2_L = 4992; ! TB3 page2 literal IO0F05$L_PCI_TB3_PAGE3_L = 5056; ! TB3 page3 literal IO0F05$L_PCI_TB4_PAGE0_L = 5120; ! TB4 page0 literal IO0F05$L_PCI_TB4_PAGE1_L = 5184; ! TB4 page1 literal IO0F05$L_PCI_TB4_PAGE2_L = 5248; ! TB4 page2 literal IO0F05$L_PCI_TB4_PAGE3_L = 5312; ! TB4 page3 literal IO0F05$L_PCI_TB5_PAGE0_L = 5376; ! TB5 page0 literal IO0F05$L_PCI_TB5_PAGE1_L = 5440; ! TB5 page1 literal IO0F05$L_PCI_TB5_PAGE2_L = 5504; ! TB5 page2 literal IO0F05$L_PCI_TB5_PAGE3_L = 5568; ! TB5 page3 literal IO0F05$L_PCI_TB6_PAGE0_L = 5632; ! TB6 page0 literal IO0F05$L_PCI_TB6_PAGE1_L = 5696; ! TB6 page1 literal IO0F05$L_PCI_TB6_PAGE2_L = 5760; ! TB6 page2 literal IO0F05$L_PCI_TB6_PAGE3_L = 5824; ! TB6 page3 literal IO0F05$L_PCI_TB7_PAGE0_L = 5888; ! TB7 page0 literal IO0F05$L_PCI_TB7_PAGE1_L = 5952; ! TB7 page1 literal IO0F05$L_PCI_TB7_PAGE2_L = 6016; ! TB7 page2 literal IO0F05$L_PCI_TB7_PAGE3_L = 6080; ! TB7 page3 literal IO0F05$L_GRU_INT_REQ_L = 0; ! Int request literal IO0F05$L_GRU_INT_MASK_L = 64; ! Int mask literal IO0F05$L_GRU_INT_EDGE_L = 128; ! Level/edge selct literal IO0F05$L_GRU_INT_HILO_L = 192; ! Hi/lo irq select literal IO0F05$L_GRU_INT_CLR_L = 256; ! Clear Int literal IO0F05$L_GRU_CACHE_CNFG_L = 512; ! Cache config literal IO0F05$L_GRU_SET_CNFG_L = 768; ! Set Cache config literal IO0F05$L_GRU_LEDS_L = 2048; ! LEDs literal IO0F05$L_GRU_RESET_L = 2304; ! Force system reset !*** MODULE $IO1504DEF *** literal IO1504$K_IOC_HAE_PA_L = -2147483648; literal IO1504$K_IOC_HAE_PA_H = 1; literal IO1504$K_IOC_CONF_PA_L = -2147483648; literal IO1504$K_IOC_CONF_PA_H = 32; literal IO1504$K_IOC_STAT0_PA_L = -2147483584; literal IO1504$K_IOC_STAT0_PA_H = 1; literal IO1504$K_IOC_STAT1_PA_L = -2147483552; literal IO1504$K_IOC_STAT1_PA_H = 1; literal IO1504$K_IOC_TBIA_PA_L = -2147483520; literal IO1504$K_IOC_TBIA_PA_H = 1; literal IO1504$K_TB_ENA_PA_L = -2147483648; literal IO1504$K_TB_ENA_PA_H = 160; literal IO1504$K_SFT_RST_PA_L = -2147483648; literal IO1504$K_SFT_RST_PA_H = 192; literal IO1504$K_PAR_DIS_PA_L = -2147483648; literal IO1504$K_PAR_DIS_PA_H = 224; literal IO1504$K_IOC_W_BASE0_PA_L = -2147483392; literal IO1504$K_IOC_W_BASE0_PA_H = 1; literal IO1504$K_IOC_W_BASE1_PA_L = -2147483360; literal IO1504$K_IOC_W_BASE1_PA_H = 1; literal IO1504$K_IOC_W_MASK0_PA_L = -2147483328; literal IO1504$K_IOC_W_MASK0_PA_H = 1; literal IO1504$K_IOC_W_MASK1_PA_L = -2147483296; literal IO1504$K_IOC_W_MASK1_PA_H = 1; literal IO1504$K_IOC_T_BASE0_PA_L = -2147483264; literal IO1504$K_IOC_T_BASE0_PA_H = 1; literal IO1504$K_IOC_T_BASE1_PA_L = -2147483232; literal IO1504$K_IOC_T_BASE1_PA_H = 1; literal IO1504$K_IOC_TB_TAG0_PA_L = -2130706432; literal IO1504$K_IOC_TB_TAG0_PA_H = 0; literal IO1504$K_IOC_TB_TAG1_PA_L = -2130706432; literal IO1504$K_IOC_TB_TAG1_PA_H = 32; literal IO1504$K_IOC_TB_TAG2_PA_L = -2130706432; literal IO1504$K_IOC_TB_TAG2_PA_H = 64; literal IO1504$K_IOC_TB_TAG3_PA_L = -2130706432; literal IO1504$K_IOC_TB_TAG3_PA_H = 96; literal IO1504$K_IOC_TB_TAG4_PA_L = -2130706432; literal IO1504$K_IOC_TB_TAG4_PA_H = 128; literal IO1504$K_IOC_TB_TAG5_PA_L = -2130706432; literal IO1504$K_IOC_TB_TAG5_PA_H = 160; literal IO1504$K_IOC_TB_TAG6_PA_L = -2130706432; literal IO1504$K_IOC_TB_TAG6_PA_H = 192; literal IO1504$K_IOC_TB_TAG7_PA_L = -2130706432; literal IO1504$K_IOC_TB_TAG7_PA_H = 224; literal IO1504$K_IOC_IACK_SC_PA_L = -1610612736; literal IO1504$K_IOC_IACK_SC_PA_H = 1; literal IO1504$K_PCI_IO_PA_L = -1073741824; literal IO1504$K_PCI_IO_PA_H = 1; literal IO1504$K_PCI_IO_END_PA_L = -536870913; literal IO1504$K_PCI_IO_END_PA_H = 1; literal IO1504$K_PCI_CFG_PA_L = -536870912; literal IO1504$K_PCI_CFG_PA_H = 1; literal IO1504$K_PCI_SPARSE_MEM_PA_L = 0; literal IO1504$K_PCI_SPARSE_MEM_PA_H = 2; literal IO1504$K_PCI_SPARSE_MEMEND_PA_L = 536870912; literal IO1504$K_PCI_SPARSE_MEMEND_PA_H = 2; literal IO1504$K_PCI_DENSE_MEM_PA_L = 0; literal IO1504$K_PCI_DENSE_MEM_PA_H = 3; literal IO1504$K_PCI_DENSE_MEM_END_PA_L = -1; literal IO1504$K_PCI_DENSE_MEM_END_PA_H = 3; literal IO1504$K_KBD_DATA_PA_L = -1073738752; literal IO1504$K_KBD_DATA_PA_H = 1; literal IO1504$B_KBD_DATA_PCI = 96; literal IO1504$K_KBD_CMD_PA_L = -1073738624; literal IO1504$K_KBD_CMD_PA_H = 1; literal IO1504$B_KBD_CMD_PCI = 100; literal IO1504$K_DS1287_PA_L = -1073738240; literal IO1504$K_DS1287_PA_H = 1; literal IO1504$K_COM1_PA_L = -1073709312; literal IO1504$K_COM1_PA_H = 1; literal IO1504$K_COM1_RCV_BUF_PCI = 1016; literal IO1504$K_COM1_IER_PCI = 1017; literal IO1504$K_COM1_IIR_PCI = 1018; literal IO1504$K_COM1_L_CTL_PCI = 1019; literal IO1504$K_COM1_M_CTL_PCI = 1020; literal IO1504$K_COM1_L_STAT_PCI = 1021; literal IO1504$K_COM1_M_STAT_PCI = 1022; literal IO1504$K_COM2_PA_L = -1073717504; literal IO1504$K_COM2_PA_H = 1; literal IO1504$K_COM2_RCV_BUF_PCI = 760; literal IO1504$K_COM2_IER_PCI = 761; literal IO1504$K_COM2_IIR_PCI = 762; literal IO1504$K_COM2_L_CTL_PCI = 763; literal IO1504$K_COM2_M_CTL_PCI = 764; literal IO1504$K_COM2_L_STAT_PCI = 765; literal IO1504$K_COM2_M_STAT_PCI = 766; literal IO1504$K_PPORT_PA_L = -1073713408; literal IO1504$K_PPORT_PA_H = 1; literal IO1504$K_FLOPPY_PA_L = -1073709568; literal IO1504$K_FLOPPY_PA_H = 1; literal IO1504$K_MASTER_ICR_PCI = 32; literal IO1504$K_MASTER_IMR_PCI = 33; literal IO1504$K_SLAVE_ICR_PCI = 160; literal IO1504$K_SLAVE_IMR_PCI = 161; literal IO1504$K_PCI_IRR_REG = 38; literal IO1504$K_PCI_IMR_REG = 38; literal IO1504$K_FLASH_ROM1_PA = 939524096; literal IO1504$K_FLASH_ROM2_PA = 941621248; literal IO1504$K_FLASH_ROM3_PA = 943718400; literal IO1504$K_FLASH_ROM4_PA = 945815552; literal IO1504$K_FLASH_ROM1_END_PA = 941621240; literal IO1504$K_FLASH_ROM2_END_PA = 943718392; literal IO1504$K_FLASH_ROM3_END_PA = 945815544; literal IO1504$K_FLASH_ROM4_END_PA = 947912696; literal IO1504$K_OPDRIVER_XMT_ISR = 3; literal IO1504$K_OPDRIVER_RCV_ISR = 4; !*** MODULE $IOCDEF *** ! + ! ! $IOCDEF - flag bits used in I/O database search routines. ! ! - literal IOC$M_PHY = %X'1'; literal IOC$M_TYPE = %X'2'; literal IOC$M_CLASS = %X'4'; literal IOC$M_LOCAL = %X'8'; literal IOC$M_EXISTS = %X'10'; literal IOC$M_2P = %X'20'; literal IOC$M_ANY = %X'40'; literal IOC$M_MOUNT = %X'80'; literal IOC$M_ALT = %X'100'; literal IOC$M_NO_TRANS = %X'200'; literal IOC$M_ALLOC = %X'400'; literal IOC$M_DTN = %X'800'; literal IOC$M_NOLOCK = %X'1000'; literal IOC$M_PAC = %X'2000'; literal IOC$M_B4CREATE = %X'4000'; literal IOC$S_IOCDEF = 2; ! Old size name, synonym for IOC$S_IOC literal IOC$S_IOC = 2; ! IOC$V_PHY must be bit 0!! macro IOC$V_PHY = 0,0,1,0 %; ! physical device specified macro IOC$V_TYPE = 0,1,1,0 %; ! device type name specified macro IOC$V_CLASS = 0,2,1,0 %; ! allocation class present macro IOC$V_LOCAL = 0,3,1,0 %; ! search local devices only macro IOC$V_EXISTS = 0,4,1,0 %; ! device exists macro IOC$V_2P = 0,5,1,0 %; ! device is on UCB secondary path macro IOC$V_ANY = 0,6,1,0 %; ! find any matching device macro IOC$V_MOUNT = 0,7,1,0 %; ! find only mountable devices macro IOC$V_ALT = 0,8,1,0 %; ! alternate UCB found macro IOC$V_NO_TRANS = 0,9,1,0 %; ! caller translated logical name macro IOC$V_ALLOC = 0,10,1,0 %; ! allocate mountable device macro IOC$V_DTN = 0,11,1,0 %; ! search for DDRed device macro IOC$V_NOLOCK = 0,12,1,0 %; ! don't take out device lock macro IOC$V_PAC = 0,13,1,0 %; ! This is a port allocation class macro IOC$V_B4CREATE = 0,14,1,0 %; ! don't skip UCB$V_NO_ASSIGN or UCB$V_CDP devices ! ! ! ************************************************************************* ! Format of AGP Command Register as defined by AGP Spec V2.0 ! ************************************************************************* ! literal IOC$M_AGP_CMD_1X = %X'1'; literal IOC$M_AGP_CMD_2X = %X'2'; literal IOC$M_AGP_CMD_4X = %X'4'; literal IOC$M_AGP_CMD_FW = %X'10'; literal IOC$M_AGP_CMD_4G = %X'20'; literal IOC$M_AGP_ENABLE = %X'100'; literal IOC$M_AGP_CMD_SBA = %X'200'; literal IOC$M_AGP_RQ_DEPTH = %X'FF000000'; literal IOC$S_CMD = 4; macro IOC$V_AGP_CMD_1X = 0,0,1,0 %; ! AGP RATE = 1 macro IOC$V_AGP_CMD_2X = 0,1,1,0 %; ! AGP RATE = 2 macro IOC$V_AGP_CMD_4X = 0,2,1,0 %; ! AGP RATE = 4 macro IOC$V_AGP_CMD_FW = 0,4,1,0 %; ! AGP FASTWRITE macro IOC$V_AGP_CMD_4G = 0,5,1,0 %; ! AGP ADDRESS > 4GIGABYTE macro IOC$V_AGP_ENABLE = 0,8,1,0 %; ! AGP ENABLE macro IOC$V_AGP_CMD_SBA = 0,9,1,0 %; ! SIDEBAND ADDRESS MECHANISM macro IOC$V_AGP_RQ_DEPTH = 0,24,8,0 %; literal IOC$S_AGP_RQ_DEPTH = 8; ! AGP REQUEST QUEUE DEPTH ! ! ! ************************************************************************* ! Format of AGP Status Register as defined by AGP Spec V2.0 ! ************************************************************************* ! literal IOC$M_AGP_STS_1X = %X'1'; literal IOC$M_AGP_STS_2X = %X'2'; literal IOC$M_AGP_STS_4X = %X'4'; literal IOC$M_AGP_STS_FW = %X'10'; literal IOC$M_AGP_STS_4G = %X'20'; literal IOC$M_AGP_STS_SBA = %X'200'; literal IOC$M_AGP_RQ = %X'FF000000'; literal IOC$S_STS = 4; macro IOC$V_AGP_STS_1X = 0,0,1,0 %; ! AGP RATE = 1 macro IOC$V_AGP_STS_2X = 0,1,1,0 %; ! AGP RATE = 2 macro IOC$V_AGP_STS_4X = 0,2,1,0 %; ! AGP RATE = 4 macro IOC$V_AGP_STS_FW = 0,4,1,0 %; ! AGP FASTWRITE macro IOC$V_AGP_STS_4G = 0,5,1,0 %; ! AGP ADDRESS > 4GIGABYTE macro IOC$V_AGP_STS_SBA = 0,9,1,0 %; ! SIDEBAND ADDRESS MECHANISM macro IOC$V_AGP_RQ = 0,24,8,0 %; literal IOC$S_AGP_RQ = 8; ! AGP REQUEST QUEUE DEPTH ! ! ! ************************************************************************* ! Function codes used by system routines ioc$read_io, ioc$write_io ! ************************************************************************* ! literal IOC$K_BYTE_LANED = 1; literal IOC$K_WORD_LANED = 2; literal IOC$K_LONGWORD = 4; literal IOC$K_QUADWORD = 8; literal IOC$K_BYTE = 256; literal IOC$K_WORD = 512; ! ! ! ************************************************************************* ! Function codes used by system routine ioc$node_function ! ************************************************************************* ! literal IOC$K_ENABLE_INTR = 1; literal IOC$K_DISABLE_INTR = 2; literal IOC$K_ENABLE_SG = 3; literal IOC$K_DISABLE_SG = 4; literal IOC$K_ENABLE_PAR = 5; literal IOC$K_DISABLE_PAR = 6; literal IOC$K_ENABLE_BLKM = 7; literal IOC$K_DISABLE_BLKM = 8; literal IOC$K_ISSUE_EOI = 9; literal IOC$K_ENABLE_DISTRIB_INTR = 10; literal IOC$K_DISABLE_DISTRIB_INTR = 11; literal IOC$K_AGP_READ_COMMAND = 12; literal IOC$K_AGP_WRITE_COMMAND = 13; ! ! ------------------------------------------------------------------------- ! Multiple Vector Interrupt ioc$node_function codes ! literal IOC$K_MVI_MASK_EVENT = 14; literal IOC$K_MVI_UNMASK_EVENT = 15; literal IOC$K_MVI_REQUEST_VECTORS = 16; literal IOC$K_MVI_MAP_VECTOR = 17; literal IOC$K_MVI_DISPATCH_EVENT = 18; literal IOC$K_MVI_DISPATCH_VECTOR = 19; literal IOC$K_MVI_DISPATCH_UNIQUE = 20; ! ! ! ************************************************************************* ! Function codes used by system routine ioc$node_data ! ************************************************************************* ! literal IOC$K_TURBO_SLOT_DENSE_PA = 1; literal IOC$K_TURBO_SLOT_SPARSE_PA = 2; literal IOC$K_FBUS_INT_LOC = 3; literal IOC$K_EISA_IRQ = 4; literal IOC$K_EISA_DMA_CHAN = 5; literal IOC$K_EISA_CONFIG_BLOCK = 6; literal IOC$K_EISA_MEM_CONFIG = 7; literal IOC$K_LBUS_DEV_BLK_PTR = 8; literal IOC$K_EISA_IO_PORT = 9; literal IOC$K_SCSI_CLK_PERIOD = 10; literal IOC$K_CPU_INT_MASK = 11; literal IOC$K_IO_PORT_RAD = 12; ! ! ! ------------------------------------------------------------------------- ! The following codes are actually used by the I/O space ! mapping routine IOC$MAP_IO. But, add them anyway to the ! IOC$NODE_DATA list as unique codes. ! ! Add synonyms for the IOC$MAP_IO function codes until the ! old ones are legislated out of existence. ! literal IOC$K_IO_CSR_BYTE_ACCESS = 11; literal IOC$K_BUS_IO_BYTE_GRAN = 11; literal IOC$K_IO_CSR_LONG_ACCESS = 12; literal IOC$K_IO_MEM_BYTE_ACCESS = 13; literal IOC$K_BUS_MEM_BYTE_GRAN = 13; literal IOC$K_IO_MEM_LONG_ACCESS = 14; literal IOC$K_BUS_MEM_DENSE = 14; ! ! ! ------------------------------------------------------------------------- ! The following code is used by drivers to request the address ! swizzle factor of an I/O bus. ! literal IOC$K_IO_ADDRESS_SWIZZLE = 15; ! ! ! ------------------------------------------------------------------------- ! The following two are synonyms to request the bus address ! of the direct DMA window. ! literal IOC$K_DIRECT_DMA_BASE = 16; literal IOC$K_DDMA_BASE_BA = 16; ! ! ! ------------------------------------------------------------------------- ! Old code uses this function code to get the size of the ! direct dma window. If the system is a Galaxy system, ! and the minpfn is nonzero, this function code will ! return a size of zero, even if it isn't. See DDMA_WIN_SIZE ! below. ! literal IOC$K_DIRECT_DMA_SIZE = 17; ! ! ! ------------------------------------------------------------------------- ! add an ioc$node_data code for the ISA bus user parameter. ! also an ioc$node_data code for the dipl problem. ! these are added here so that it is easy to see what the next ! number to use will be. (could be added to node_data list above) ! literal IOC$K_ISA_USER_PARAM = 18; literal IOC$K_DEVICE_IPL = 19; ! ! ------------------------------------------------------------------------- ! Add an ioc$node_data code for monster windows ! literal IOC$K_MONSTER_WINDOW = 20; ! ! ! ------------------------------------------------------------------------- ! This function code will always return the true size of ! the direct dma window. DDMA_BASE_PA will return the ! memory address of the direct dma window, no longer to ! be presumed zero. literal IOC$K_DDMA_WIN_SIZE = 21; literal IOC$K_DDMA_BASE_PA = 22; ! ! ! ------------------------------------------------------------------------- ! Add an ioc$node_data code for AGP capabilities mask ! The data returned is formatted to conform to the AGP STATUS longword ! found in the configuration header for the AGP bus. literal IOC$K_AGP_CAP_MASK = 23; ! ! ! ! ------------------------------------------------------------------------- ! This ioc$node_data function code will identify the system building block ! in which an adapter resides. Support for this code is currently ! planned only for Wildfire and Marvel class alpha systems. All others ! will return SS$_ILLIOFUNC. ! literal IOC$K_IO_PORT_LOC = 24; ! ! ! ------------------------------------------------------------------------- ! This ioc$node_data function returns the translation offset quadword ! from the ADP for the specified CRB. If the ADP doesn't contain a ! valid translation offset, this function returns SS$_ILLIOFUNC. ! literal IOC$K_IO_TRA_OFFSET = 25; ! ! ! ------------------------------------------------------------------------- ! Return a pointer to the BUSARRAYENTRY ! literal IOC$K_BUSARRAYENTRY = 26; ! ! ! ------------------------------------------------------------------------- ! MSI and Multiple Vector Interrupt ioc$node_data codes ! literal IOC$K_INT_MECH = 27; literal IOC$K_MSIABS = 28; literal IOC$K_MVI_DEV_VECTORS_REQ = 29; literal IOC$K_MVI_SYS_VECTORS_GRA = 30; literal IOC$K_MVI_DATA = 31; literal IOC$K_MVI_PENDING_EVENT = 32; ! ! ! ------------------------------------------------------------------------- ! Return a mask of platform DMA capabilities as defined in ADPDEF ! literal IOC$K_DMA_CAP_MASK = 33; ! ! ! ------------------------------------------------------------------------- ! Additional MSI and Multiple Vector Interrupt ioc$node_data codes ! literal IOC$K_MVI_USR_VECTORS_REQ = 34; ! ! ! ------------------------------------------------------------------------- ! A function code for IOC$NODE_DATA that drivers can call to see if ! their platform has a SG Map. (The only platforms that should fail with ! SS$_ITEMNOTFOUND are Sentosa, Kauai and Bucchaneer and later platforms). ! literal IOC$K_SG_MAP_PRESENT = 35; ! ! ! ************************************************************************* ! Values returned by IOC$K_INT_MECH node_data call. ! These values are mutually exclusive. ! ************************************************************************* ! literal IOC$K_INT_MECH_IOSAPIC = 1; ! IOSAPIC delivery mechanism literal IOC$K_INT_MECH_MSI = 2; ! Standard MSI mechanism literal IOC$K_INT_MECH_MSIX = 3; ! MSI-X mechanism ! ! ! ************************************************************************* ! MVI_DATA and MVI_QENTRY ! ************************************************************************* ! ! These structures contain Data returned by calling ioc$node_function ! with the function code IOC$K_MSI_REQUEST_VECTORS. ! ! The Hash Table created maps Interrupt Vectors and Vector Table ! Entries to ISR subroutines. ! ! The sequence of events that builds this tree is as follows. ! ! AT UNIT INIT TIME: ! ! . A driver calls ioc$node_function for IOC$K_MVI_REQUEST_VECTORS ! ! . This call returns an MVI_DATA structure containing the number ! of interrupt vectors requested by the device, the number of ! vectors granted by the system, and a pointer to an array of ! queue headers, one for each of the vectors granted, containing ! the vector. ! ! . The driver implements its policy for distributing the vectors ! granted to it by walking the mvi_array and for each vector ! in the array, the driver calls ioc$node_function again for ! IOC$K_MVI_MAP_FUNCTION with the Interrupt Vector, the Pointer ! to the Subroutine for handling the Interrupt, and, in the case ! of MSI-X, the Vector Table Entry Index. ! ! . In the case where the driver was granted fewer vectors than ! requested, and the driver must share the vectors with more ! than one ISR subroutine or Vector Table Entry, a queue will ! be formed for each shared Interrupt Vector. ! ! AT RUN TIME ! ! . When an interrupt occurs, the driver will call ioc$node_function ! for IOC$K_MVI_DISPATCH_VECTOR, which will run down each ISR ! subroutine in the queue for the given vector. The driver should ! fork and lower IPL before calling this function. ! ! . Before exiting, the driver should call ioc$node_function for ! IOC$K_MVI_PENDING to see if there are any other interrupts ! pending. This call will return the Vector Table Index of any ! pending interrupts. ! ! . For each pending interrupt the driver should call ! ioc$node_function for IOC$K_MVI_DISPATCH_VTE in a loop ! until all pending interrupts have been handled. ! ! . Optionally, a driver can call ioc$node_function with a code ! of IOC$K_MASK_VTE to mask interrupts from a Vector Table Entry ! or IOC$_UNMASK_VTE to unmask interrupts from a Vector Table ! Entry. ! ! . In the case where a driver wants to assign a different vector ! to a given Vector Table Entry, it will call ioc$node_function ! for IOC$K_MVI_CHANGE_VECTOR with the new vector, the Vector ! Table Index, and the Pointer to the ISR subroutine. ! ! ! MVI_DATA ! +-------------+ ! | Requested | ! +-------------+ ! | Granted | ! +-------------+ ! .------| Hash_Table | ! | +-------------+ ! | ! | .-----------------------------------------------------------------. ! | | | ! | | .-------------------------------------------------------------. | ! | | | | | ! | | | MULTIPLE VECTOR INTERRUPT HASH TABLE | | ! | | | | | ! | | | MVI_QENTRY MVI_QENTRY MVI_QENTRY | | ! | | | +-------------+ +-------------+ +-------------+ | | ! | | `->| Flink |----->| Flink |----->| Flink |>-' | ! `----->| |<--. | |<--. | |<---' ! | +-------------+ | +-------------+ | +-------------+ ! `---<| Blink | `--| Blink | `--| Blink | ! +-------------+ +-------------+ +-------------+ ! | Vector | | Vector | | Vector | ! +-------------+ +-------------+ +-------------+ ! | CPU ID | | CPU ID | | CPU ID | ! +-------------+ +-------------+ +-------------+ ! | Func Ptr | | Func Ptr | | Func Ptr | ! +-------------+ +-------------+ +-------------+ ! | Vec Tab Idx | | Vec Tab Idx | | Vec Tab Idx | ! +-------------+ +-------------+ +-------------+ ! | ! v ! +-------------+ +-------------+ +-------------+ ! | Flink |----->| Flink |----->| Flink | ! | |<--. | |<--. | | ! +-------------+ | +-------------+ | +-------------+ ! | Blink | `--| Blink | `--| Blink | ! +-------------+ +-------------+ +-------------+ ! | Vector | | Vector | | Vector | ! +-------------+ +-------------+ +-------------+ ! | CPU ID | | CPU ID | | CPU ID | ! +-------------+ +-------------+ +-------------+ ! | Func Ptr | | Func Ptr | | Func Ptr | ! +-------------+ +-------------+ +-------------+ ! | Vec Tab Idx | | Vec Tab Idx | | Vec Tab Idx | ! +-------------+ +-------------+ +-------------+ ! | ! v ! ! ************************************************************************* ! MVI_QENTRY Multiple Vector Interrupt Queue Entry ! ************************************************************************* ! ! MVI_QENTRY Maps an Interrupt Vector to an ISR subroutine, and, for ! MSIX, an MSIX Vector Table Entry. ! ! There will be one instance of these for every vector, and in the case ! of MSIX, every Vector Table Entry. Additionally, for MSI, there is an ! array of pointers to every MVI_QENTRY structure, one for each Vector ! Table Entry. ! ! Because it is possible that the OS will not return all the vectors ! that a device requests, vectors will have to be shared among the ! various ISR subroutines and, in the case of MSIX, associated Vector ! Table Entries. ! ! Vectors that hash to the same MVI_QENTRY index will be chained in a ! queue. For the sake of performance, we hope our hash algorithm is ! good enough to hash only one vector to each queue. ! ! When the ISR dispatch function runs down a given vector, it will be ! hashed to a chain in the MVI_QENTRY has table and the dispatch function ! will execute all the ISR subroutines in that chain. ! literal MVI_QE$S_MVI_QENTRY = 24; macro MVI_QE$PS_FLINK = 0,0,32,1 %; macro MVI_QE$PS_BLINK = 4,0,32,1 %; macro MVI_QE$PS_FUNCTION = 8,0,32,1 %; ! ISR Subroutine macro MVI_QE$L_VECTOR = 12,0,32,1 %; macro MVI_QE$L_CPUID = 16,0,32,1 %; macro MVI_QE$L_VTE_INDEX = 20,0,32,1 %; ! Useful to MVI-X only ! ! Insure quadword alignment. ! literal MVI_DATA$S_MVI_DATA = 32; macro MVI_DATA$L_REQUESTED = 0,0,32,1 %; ! Number of vectors requested macro MVI_DATA$L_GRANTED = 4,0,32,1 %; ! Number of vectors granted macro MVI_DATA$PS_VEC_ARRAY = 8,0,32,1 %; ! List of granted vectors macro MVI_DATA$PS_VTE_ARRAY = 12,0,32,1 %; ! Vector Table Entry Array macro MVI_DATA$PS_HASH_TABLE = 16,0,32,1 %; ! Pointer to the Hash Table macro MVI_DATA$PS_BITMAP = 20,0,32,1 %; ! Bitmap for hash table macro MVI_DATA$L_BITMAP_SIZE = 24,0,32,1 %; ! Size of Bitmap in bits ! ! Insure quadword alignment. ! !*** MODULE $IOCNTDEF *** literal IOCNT$K_LENGTH = 308; ! LENGTH OF IOCNT literal IOCNT$C_LENGTH = 308; ! LENGTH OF IOCNT literal IOCNT$S_IOCNT = 312; macro IOCNT$PS_PTR_1 = 0,0,32,1 %; ! macro IOCNT$PS_PTR_2 = 4,0,32,1 %; ! macro IOCNT$W_SIZE = 8,0,16,0 %; ! Size of IOCNT, in bytes. macro IOCNT$B_TYPE = 10,0,8,0 %; ! Nonpaged pool packet type, DYN$C_MISC macro IOCNT$B_SUBTYPE = 11,0,8,0 %; ! Nonpaged pool packet subtype, DYN$C_IOCNT ! ! Fast Path counters ! ! IOC_STD$INITIATE counters: macro IOCNT$L_FP_PORT_CPU_IO = 16,0,32,0 %; ! On port CPU and new IO (dev UCB) macro IOCNT$L_FP_IO_QUEUED = 20,0,32,0 %; ! IRP queued to UCB IOQ (dev UCB) macro IOCNT$L_FP_UCB_QUEUED = 24,0,32,0 %; ! UCB was already queued (dev UCB) macro IOCNT$L_FP_OTHER_UCB_QUEUED = 28,0,32,0 %; ! UCB queued to CPU db (dev UCB) macro IOCNT$L_FP_IPINT = 32,0,32,0 %; ! Sent IPINT (dev UCB) macro IOCNT$L_FP_QUEUE_SELF = 36,0,32,0 %; ! Queued UCB to local IPL8 FQ (dev UCB) macro IOCNT$L_FP_AFF_FKB_INUSE = 40,0,32,0 %; ! Start I/O affinity FKB found inuse (dev UCB) macro IOCNT$L_FP_UCB_WAS_QUEUED = 44,0,32,0 %; ! Number of times UCB was already queued to port CPU (dev UCB) ! Port CPU Initiate counters: macro IOCNT$L_FP_BAD_START_AFF = 48,0,32,0 %; ! Affinity has changed (dev UCB) macro IOCNT$L_FP_EMPTY_UCB = 52,0,32,0 %; ! UCB found with no start I/Os (dev UCB) macro IOCNT$L_FP_AFF_IO_FOUND = 56,0,32,0 %; ! Number of affinitized start I/Os found (dev UCB) macro IOCNT$L_FP_AFF_IO_STARTED = 60,0,32,0 %; ! Number of Affinitized I/Os started (dev UCB) ! SCS$UNSTALLUCB counters: macro IOCNT$L_FP_RESUMED_IO = 64,0,32,0 %; ! Number of resumed I/Os (dev UCB) ! Fast Send Message vetoes from various layers: macro IOCNT$L_FP_SYSAP_SENDS = 68,0,32,0 %; ! Number of SYSAP Send messages via Fast Path macro IOCNT$L_FP_SYSAP_NOSEND = 72,0,32,0 %; ! Number of SYSAP denials for Fast Path send msg (dev UCB) macro IOCNT$L_FP_SCS_NOSEND = 76,0,32,0 %; ! Number of SCS denials for Fast Path send message (not used, see CDT) macro IOCNT$L_FP_PORT_NOSEND = 80,0,32,0 %; ! Number of port driver denials for Fast Path send msg (port UCB) macro IOCNT$L_FP_PORT_NORBUN = 84,0,32,0 %; ! Number of times lack of RBUN denied for Fast Path send msg (port UCB) ! Receive Send Message vetoes from various layers: macro IOCNT$L_FP_SYSAP_RECVS = 88,0,32,0 %; ! Number of SYSAP Send messages via Fast Path macro IOCNT$L_FP_SYSAP_NORECV = 92,0,32,0 %; ! Number of SYSAP denials for Fast Path receive msg (dev UCB) macro IOCNT$L_FP_SCS_NORECV = 96,0,32,0 %; ! Number of SCS denials for Fast Path receive message (not used, see CDT) macro IOCNT$L_FP_PORT_NORECV = 100,0,32,0 %; ! Number of port driver denials for Fast Path receive msg (port UCB) ! RBUN pool activity: macro IOCNT$L_FP_RBUN_CREATES = 104,0,32,0 %; ! Number of RBUN creates (port UCB) macro IOCNT$L_FP_RBUN_DELETES = 108,0,32,0 %; ! Number of RBUN deletions (port UCB) macro IOCNT$L_FP_URGENT_RECLAIMS = 112,0,32,0 %; ! Number of Urgent Reclamations of SCS non-paged pool (not used) macro IOCNT$L_FP_RBUN_POOL_CLEANUPS = 116,0,32,0 %; ! Number of times RBUN pool cleaned up (port UCB) macro IOCNT$L_FP_PORT_TYP1 = 120,0,32,0 %; ! Number of Typ1 maps over port (port UCB) ! Port driver ISR counters: macro IOCNT$L_FP_INTERRUPTS = 124,0,32,0 %; ! Number of device interrupts (port UCB) macro IOCNT$L_FP_SAVED_FORKS = 128,0,32,0 %; ! Number of Response Q forks saved (port UCB) macro IOCNT$L_FP_INT_QUEUED = 132,0,32,0 %; ! Number of interrupt fork blocks queued locally or to port CPU (port UCB) ! Port driver fork routine counters: macro IOCNT$L_FP_BAD_INT_AFF = 136,0,32,0 %; ! Affinity has changed after device interrupt IPINT (port UCB) macro IOCNT$L_FP_PORT_FORKS = 140,0,32,0 %; ! Number of times port response queue fork executes (port UCB) macro IOCNT$L_FP_PORT_FORK_REQUEUES = 144,0,32,0 %; ! Number of times port response queue fork requeued (port UCB) macro IOCNT$L_FP_RESPONSES = 148,0,32,0 %; ! Number of responses taken from response queue (port UCB) ! Miscellaneous port activities: macro IOCNT$L_FP_REPO_CDRP = 152,0,32,0 %; ! Number of Repossess CDRP service calls (port UCB) macro IOCNT$L_FP_AFFINITY_CHANGES = 156,0,32,0 %; ! Number of affinity changes on port (port UCB) ! IOC_STD$REQCOM_LOCAL counters: macro IOCNT$L_FP_REQCOM = 160,0,32,0 %; ! Number of Fast Path request completions (dev UCB) macro IOCNT$L_FP_RESERVED1 = 164,0,32,0 %; ! Reserved for Fast Path macro IOCNT$L_FP_RESERVED2 = 168,0,32,0 %; ! Reserved for Fast Path macro IOCNT$L_FP_RESERVED3 = 172,0,32,0 %; ! Reserved for Fast Path macro IOCNT$L_FP_RESERVED4 = 176,0,32,0 %; ! Reserved for Fast Path macro IOCNT$L_FP_RESERVED5 = 180,0,32,0 %; ! Reserved for Fast Path macro IOCNT$L_FP_RESERVED6 = 184,0,32,0 %; ! Reserved for Fast Path macro IOCNT$L_FP_RESERVED7 = 188,0,32,0 %; ! Reserved for Fast Path macro IOCNT$L_FP_RESERVED8 = 192,0,32,0 %; ! Reserved for Fast Path macro IOCNT$L_FP_RESERVED9 = 196,0,32,0 %; ! Reserved for Fast Path macro IOCNT$L_FP_RESERVED10 = 200,0,32,0 %; ! Reserved for Fast Path ! ! Fast-IO counters ! macro IOCNT$L_FIOPCNT = 204,0,32,0 %; ! IO_PERFORM calls for this UCB macro IOCNT$L_FIOCOPT = 208,0,32,0 %; ! "Channel == same" optimization count macro IOCNT$L_FIOFFDT = 212,0,32,0 %; ! Count of ACP$FASTIO_BLOCK routine calls macro IOCNT$L_FIOECNT = 216,0,32,0 %; ! Number of ACP$FASTIO_BLOCK error returns macro IOCNT$L_FIOELNO = 220,0,32,0 %; ! Source code line number of last error return macro IOCNT$L_FIOEPID = 224,0,32,0 %; ! PID of process causing the last error return macro IOCNT$L_FIOVIOC = 228,0,32,0 %; ! Fast-IO calls to VIO cache macro IOCNT$L_FIOVIOH = 232,0,32,0 %; ! VIO cache hits macro IOCNT$L_FIOCIOC = 236,0,32,0 %; ! VIO cache I/Os (complete or partial miss) ! FIOVIOC - FIOVIOH - FIOCIOC is count of ! I/Os to file not cached but we had to invoke ! the VIOC before we knew we didn't want to. macro IOCNT$L_FIORVOP = 240,0,32,0 %; ! Number of read virtual operations to driver macro IOCNT$L_FIOWVOP = 244,0,32,0 %; ! Number of write virtual operations to driver macro IOCNT$L_FIORLOP = 248,0,32,0 %; ! Number of read logical operations to driver macro IOCNT$L_FIOWLOP = 252,0,32,0 %; ! Number of write logical operations to driver macro IOCNT$L_FIOBKRD = 256,0,32,0 %; ! Total Blocks read (block == 512 bytes) macro IOCNT$L_FIOBKWT = 260,0,32,0 %; ! Total Blocks written (block == 512 bytes) macro IOCNT$L_FIOFFIN = 264,0,32,0 %; ! Count of fast-finishes macro IOCNT$L_FIOCOMP = 268,0,32,0 %; ! PID/FPC of last fast-finish macro IOCNT$L_FIOBCOM = 272,0,32,0 %; ! Count of fast-finishes for buffered I/O macro IOCNT$L_FIODCOM = 276,0,32,0 %; ! Count of fast-finishes for direct I/O macro IOCNT$L_FIOSCOM = 280,0,32,0 %; ! Count of fast-finishes with system completion macro IOCNT$L_FIOBIOL = 284,0,32,0 %; ! # bufio fast-finish longword buffer copies macro IOCNT$L_FIOBIOQ = 288,0,32,0 %; ! # bufio fast-finish quadword buffer copies macro IOCNT$L_FIOSTQF = 292,0,32,0 %; ! Count of fast-finish STQCs that failed when ! decrementing IOC and checking DIRP macro IOCNT$L_FIODIRP = 296,0,32,0 %; ! Count of fast-finishes with deaccess packets macro IOCNT$L_FIOIRPE = 300,0,32,0 %; ! Count of fast-finishes with IRPEs to delete macro IOCNT$L_FIOUAST = 304,0,32,0 %; ! Count of fast-finishes with user ASTs !*** MODULE $IOGENDEF *** ! ! Function codes and modifiers for the $LOAD_DRIVER server. ! literal IOGEN$_LOAD = 1; ! LOAD a device driver literal IOGEN$_RELOAD = 2; ! RELOAD a device driver literal IOGEN$_CONNECT = 3; ! CONNECT unit(s) literal IOGEN$_INIT_CTRL = 4; ! call driver ctrl init routine literal IOGEN$_INIT_UNIT = 5; ! call driver unit init routine literal IOGEN$_DELIVER = 6; ! perform unit delivery literal IOGEN$K_MINFCODE = 1; literal IOGEN$K_MAXFCODE = 6; literal IOGEN$M_NOWAIT = %X'10000'; literal IOGEN$M_LDDB = %X'20000'; literal IOGEN$M_SYSDEVICE = %X'40000'; literal IOGEN$M_NOINIT = %X'80000'; literal IOGEN$S_IOGENDEF = 4; ! Old size name, synonym for IOGEN$S_IOGEN literal IOGEN$S_IOGEN = 4; macro IOGEN$W_FCODE = 0,0,16,0 %; ! function codes in range 1-65535 macro IOGEN$W_MODIFIERS = 2,0,16,0 %; ! 16 modifier bits reserved macro IOGEN$V_NOWAIT = 0,16,1,0 %; ! asynchronous operation requested macro IOGEN$V_LDDB = 0,17,1,0 %; ! preparsed LDDB provided macro IOGEN$V_SYSDEVICE = 0,18,1,0 %; ! this is the sysdevice device macro IOGEN$V_NOINIT = 0,19,1,0 %; ! don't call init bros (for ordering) literal IOGEN$_ADAPTER = 16; ! ADAPTER TR number literal IOGEN$_NOADAPTER = 17; ! connect to the NULL adapter literal IOGEN$_CSR = 18; ! magic number for CSR accesses literal IOGEN$_VECTOR = 19; ! byte offset into SCB/ADP vector table literal IOGEN$_MAXUNITS = 20; ! maximum # of units for this controller literal IOGEN$_SYSID = 21; ! SCS system id of controller literal IOGEN$_SYSLOA_CRB = 22; ! address of preexisting CRB literal IOGEN$_UNIT = 23; ! unit number for this device literal IOGEN$_NUMUNITS = 24; ! number of consecutive units to create literal IOGEN$_DELIVER_DATA = 25; ! scratch space for unit delivery rtn literal IOGEN$_DDB = 26; ! return the address of the DDB literal IOGEN$_CRB = 27; ! return the address of the CRB literal IOGEN$_IDB = 28; ! return the address of the IDB literal IOGEN$_UCB = 29; ! return the address of the UCB literal IOGEN$_SB = 30; ! return the address of the SB literal IOGEN$_NODE = 31; ! set CRB$L_NODE field literal IOGEN$_ALLOCLS = 32; ! Allocation class for DDB -- treated as port allocation class! literal IOGEN$_WWID = 33; ! WWID value literal IOGEN$_DEVPATH = 34; ! path information literal IOGEN$_DNP = 35; ! Device Name Prefix; literal IOGEN$_SASADDRESS = 36; ! SAS Address literal IOGEN$_SATA_END_DEVICE = 37; ! SATA end device literal IOGEN$_IR_VOLUME = 38; ! Integrated RAID volume literal IOGEN$_CISS_EXT_LUN = 39; ! CISS external Lun literal IOGEN$K_MINITEM = 16; literal IOGEN$K_MAXITEM = 39; literal IOGEN$M_AC_LOG = %X'1'; literal IOGEN$M_AC_SCA = %X'2'; literal IOGEN$M_AC_LAN = %X'4'; literal IOGEN$M_AC_LOG_ALL = %X'8'; literal IOGEN$M_AC_VERIFY = %X'10'; literal IOGEN$S_AUTOCFG = 4; macro IOGEN$L_AUTOCFG_FLAGS = 0,0,32,0 %; ! flags for IOGEN$AUTOCONFIGURE macro IOGEN$V_AC_LOG = 0,0,1,0 %; ! log progress of configuration macro IOGEN$V_AC_SCA = 0,1,1,0 %; ! configure all SCA ports and friends macro IOGEN$V_AC_LAN = 0,2,1,0 %; ! configure all LAN devices macro IOGEN$V_AC_LOG_ALL = 0,3,1,0 %; ! log even the "noisy" messages macro IOGEN$V_AC_VERIFY = 0,4,1,0 %; ! Verify a REBUILD command (done with AUTOCONFIG code) literal IOGEN$S_ABMDEF = 8; ! Old size name, synonym for IOGEN$S_ABM literal IOGEN$S_ABM = 8; macro IOGEN$IL_ABM_ADP = 0,0,32,1 %; ! ADP type code macro IOGEN$PS_ABM_BSR = 4,0,32,1 %; ! pointer to BSR's PD !*** MODULE $IOHANDLEDEF *** ! + ! This data structure contains mapping information for I/O devices. ! - literal IOHANDLE$S_IOHANDLE = 64; macro IOHANDLE$PS_FLINK = 0,0,32,1 %; macro IOHANDLE$PS_BLINK = 4,0,32,1 %; macro IOHANDLE$W_SIZE = 8,0,16,0 %; macro IOHANDLE$B_TYPE = 10,0,8,0 %; macro IOHANDLE$B_SUBTYPE = 11,0,8,0 %; macro IOHANDLE$L_BOFF = 12,0,32,0 %; macro IOHANDLE$Q_BASE_VA = 16,0,0,1 %; literal IOHANDLE$S_BASE_VA = 8; macro IOHANDLE$L_BASE_VA = 16,0,32,1 %; macro IOHANDLE$L_BASE_VA_L = 16,0,32,1 %; macro IOHANDLE$L_BASE_VA_H = 20,0,32,1 %; macro IOHANDLE$Q_PLATFORM_PA = 24,0,0,1 %; literal IOHANDLE$S_PLATFORM_PA = 8; macro IOHANDLE$Q_BUS_PA = 32,0,0,1 %; literal IOHANDLE$S_BUS_PA = 8; macro IOHANDLE$L_BUS_REGION_SIZE = 40,0,32,0 %; macro IOHANDLE$L_MAPPED_REGION_SIZE = 44,0,32,0 %; macro IOHANDLE$L_ATTRIBUTES = 48,0,32,0 %; literal IOHANDLE$K_IOHANDLELEN = 64; !*** MODULE $iovecdef *** literal iovec$c_length = 56; ! Length Of IOVEC literal iovec$k_length = 56; ! Length Of IOVEC literal iovec$S_iovec = 56; macro iovec$pq_flink = 0,0,0,1 %; literal iovec$s_flink = 8; ! IOVEC forward link macro iovec$pl_flink_l = 0,0,32,1 %; macro iovec$il_flink_h = 4,0,32,0 %; macro iovec$pq_blink = 8,0,0,1 %; literal iovec$s_blink = 8; ! IOVEC backward link macro iovec$pl_blink_l = 8,0,32,1 %; macro iovec$il_blink_h = 12,0,32,0 %; macro iovec$pq_btadp_flink = 16,0,0,1 %; literal iovec$s_btadp_flink = 8; ! BTADP forward link macro iovec$pl_btadp_flink_l = 16,0,32,1 %; macro iovec$il_btadp_flink_h = 20,0,32,0 %; macro iovec$pq_btadp_blink = 24,0,0,1 %; literal iovec$s_btadp_blink = 8; ! BTADP backward link macro iovec$pl_btadp_blink_l = 24,0,32,1 %; macro iovec$il_btadp_blink_h = 28,0,32,0 %; macro iovec$pq_bdtab = 32,0,0,1 %; literal iovec$s_bdtab = 8; ! BDTAB address macro iovec$pl_bdtab_l = 32,0,32,1 %; ! Pointer to BDTAB, a type defined in BOOLIB, not LIB macro iovec$il_bdtab_h = 36,0,32,0 %; macro iovec$pq_image_base = 40,0,0,1 %; literal iovec$s_image_base = 8; ! Adr of image base macro iovec$pl_image_base_l = 40,0,32,1 %; macro iovec$il_image_base_h = 44,0,32,0 %; macro iovec$pq_btadp = 48,0,0,1 %; literal iovec$s_btadp = 8; ! Current BTADP adr macro iovec$pl_btadp_l = 48,0,32,1 %; macro iovec$il_btadp_h = 52,0,32,0 %; !*** MODULE $IPFINSDEF *** ! ! BUNDLE: Overall format of a 128-bit instruction bundle ! literal IPFINS$M_TEMPLATE = %X'1F'; literal IPFINS$M_SLOT_0 = %X'3FFFFFFFFFE0'; literal IPFINS$M_SLOT_1 = %X'FFFFC00000000000'; literal IPFINS$M_SLOT_2 = %X'0'; literal IPFINS$S_BUNDLE = 16; macro IPFINS$V_TEMPLATE = 0,0,5,0 %; literal IPFINS$S_TEMPLATE = 5; macro IPFINS$V_SLOT_0 = 0,5,41,0 %; literal IPFINS$S_SLOT_0 = 41; macro IPFINS$V_SLOT_1 = 4,14,41,0 %; literal IPFINS$S_SLOT_1 = 41; macro IPFINS$V_SLOT_2 = 8,23,41,0 %; literal IPFINS$S_SLOT_2 = 41; macro IPFINS$Q_BUNDLE_L = 0,0,0,0 %; literal IPFINS$S_BUNDLE_L = 8; macro IPFINS$Q_BUNDLE_H = 8,0,0,0 %; literal IPFINS$S_BUNDLE_H = 8; ! ! SLOT: Each slot has an opcode and some operands ! literal IPFINS$M_OPERANDS = %X'1FFFFFFFFF'; literal IPFINS$M_OPCODE = %X'1E000000000'; literal IPFINS$M_SLOT_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_SLOT = 8; macro IPFINS$V_OPERANDS = 0,0,37,0 %; literal IPFINS$S_OPERANDS = 37; macro IPFINS$V_OPCODE = 4,5,4,0 %; literal IPFINS$S_OPCODE = 4; macro IPFINS$Q_TOTAL_SLOT = 0,0,0,0 %; literal IPFINS$S_TOTAL_SLOT = 8; ! ! A-Unit Formats ! ! ! A1: Integer ALU - Register-Register ! literal IPFINS$M_A1_QP = %X'3F'; literal IPFINS$M_A1_R1 = %X'1FC0'; literal IPFINS$M_A1_R2 = %X'FE000'; literal IPFINS$M_A1_R3 = %X'7F00000'; literal IPFINS$M_A1_X2B = %X'18000000'; literal IPFINS$M_A1_X4 = %X'1E0000000'; literal IPFINS$M_A1_VE = %X'200000000'; literal IPFINS$M_A1_X2A = %X'C00000000'; literal IPFINS$M_A1_36 = %X'1000000000'; literal IPFINS$M_A1_OPCODE = %X'1E000000000'; literal IPFINS$M_A1_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_A1_FORMAT = 8; macro IPFINS$V_A1_QP = 0,0,6,0 %; literal IPFINS$S_A1_QP = 6; macro IPFINS$V_A1_R1 = 0,6,7,0 %; literal IPFINS$S_A1_R1 = 7; macro IPFINS$V_A1_R2 = 0,13,7,0 %; literal IPFINS$S_A1_R2 = 7; macro IPFINS$V_A1_R3 = 0,20,7,0 %; literal IPFINS$S_A1_R3 = 7; macro IPFINS$V_A1_X2B = 0,27,2,0 %; literal IPFINS$S_A1_X2B = 2; macro IPFINS$V_A1_X4 = 0,29,4,0 %; literal IPFINS$S_A1_X4 = 4; macro IPFINS$V_A1_VE = 4,1,1,0 %; macro IPFINS$V_A1_X2A = 4,2,2,0 %; literal IPFINS$S_A1_X2A = 2; macro IPFINS$V_A1_36 = 4,4,1,0 %; macro IPFINS$V_A1_OPCODE = 4,5,4,0 %; literal IPFINS$S_A1_OPCODE = 4; macro IPFINS$Q_A1 = 0,0,0,0 %; literal IPFINS$S_A1 = 8; ! ! A2: Shift Left and Add ! literal IPFINS$M_A2_QP = %X'3F'; literal IPFINS$M_A2_R1 = %X'1FC0'; literal IPFINS$M_A2_R2 = %X'FE000'; literal IPFINS$M_A2_R3 = %X'7F00000'; literal IPFINS$M_A2_CT2D = %X'18000000'; literal IPFINS$M_A2_X4 = %X'1E0000000'; literal IPFINS$M_A2_VE = %X'200000000'; literal IPFINS$M_A2_X2A = %X'C00000000'; literal IPFINS$M_A2_36 = %X'1000000000'; literal IPFINS$M_A2_OPCODE = %X'1E000000000'; literal IPFINS$M_A2_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_A2_FORMAT = 8; macro IPFINS$V_A2_QP = 0,0,6,0 %; literal IPFINS$S_A2_QP = 6; macro IPFINS$V_A2_R1 = 0,6,7,0 %; literal IPFINS$S_A2_R1 = 7; macro IPFINS$V_A2_R2 = 0,13,7,0 %; literal IPFINS$S_A2_R2 = 7; macro IPFINS$V_A2_R3 = 0,20,7,0 %; literal IPFINS$S_A2_R3 = 7; macro IPFINS$V_A2_CT2D = 0,27,2,0 %; literal IPFINS$S_A2_CT2D = 2; macro IPFINS$V_A2_X4 = 0,29,4,0 %; literal IPFINS$S_A2_X4 = 4; macro IPFINS$V_A2_VE = 4,1,1,0 %; macro IPFINS$V_A2_X2A = 4,2,2,0 %; literal IPFINS$S_A2_X2A = 2; macro IPFINS$V_A2_36 = 4,4,1,0 %; macro IPFINS$V_A2_OPCODE = 4,5,4,0 %; literal IPFINS$S_A2_OPCODE = 4; macro IPFINS$Q_A2 = 0,0,0,0 %; literal IPFINS$S_A2 = 8; ! ! A3: Integer ALU - Immediate(8)-Register ! literal IPFINS$M_A3_QP = %X'3F'; literal IPFINS$M_A3_R1 = %X'1FC0'; literal IPFINS$M_A3_IMM7B = %X'FE000'; literal IPFINS$M_A3_R3 = %X'7F00000'; literal IPFINS$M_A3_X2B = %X'18000000'; literal IPFINS$M_A3_X4 = %X'1E0000000'; literal IPFINS$M_A3_VE = %X'200000000'; literal IPFINS$M_A3_X2A = %X'C00000000'; literal IPFINS$M_A3_S = %X'1000000000'; literal IPFINS$M_A3_OPCODE = %X'1E000000000'; literal IPFINS$M_A3_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_A3_FORMAT = 8; macro IPFINS$V_A3_QP = 0,0,6,0 %; literal IPFINS$S_A3_QP = 6; macro IPFINS$V_A3_R1 = 0,6,7,0 %; literal IPFINS$S_A3_R1 = 7; macro IPFINS$V_A3_IMM7B = 0,13,7,0 %; literal IPFINS$S_A3_IMM7B = 7; macro IPFINS$V_A3_R3 = 0,20,7,0 %; literal IPFINS$S_A3_R3 = 7; macro IPFINS$V_A3_X2B = 0,27,2,0 %; literal IPFINS$S_A3_X2B = 2; macro IPFINS$V_A3_X4 = 0,29,4,0 %; literal IPFINS$S_A3_X4 = 4; macro IPFINS$V_A3_VE = 4,1,1,0 %; macro IPFINS$V_A3_X2A = 4,2,2,0 %; literal IPFINS$S_A3_X2A = 2; macro IPFINS$V_A3_S = 4,4,1,1 %; macro IPFINS$V_A3_OPCODE = 4,5,4,0 %; literal IPFINS$S_A3_OPCODE = 4; macro IPFINS$Q_A3 = 0,0,0,0 %; literal IPFINS$S_A3 = 8; ! ! A4: Add Immediate(14) ! literal IPFINS$M_A4_QP = %X'3F'; literal IPFINS$M_A4_R1 = %X'1FC0'; literal IPFINS$M_A4_IMM7B = %X'FE000'; literal IPFINS$M_A4_R3 = %X'7F00000'; literal IPFINS$M_A4_IMM6D = %X'1F8000000'; literal IPFINS$M_A4_VE = %X'200000000'; literal IPFINS$M_A4_X2A = %X'C00000000'; literal IPFINS$M_A4_S = %X'1000000000'; literal IPFINS$M_A4_OPCODE = %X'1E000000000'; literal IPFINS$M_A4_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_A4_FORMAT = 8; macro IPFINS$V_A4_QP = 0,0,6,0 %; literal IPFINS$S_A4_QP = 6; macro IPFINS$V_A4_R1 = 0,6,7,0 %; literal IPFINS$S_A4_R1 = 7; macro IPFINS$V_A4_IMM7B = 0,13,7,0 %; literal IPFINS$S_A4_IMM7B = 7; macro IPFINS$V_A4_R3 = 0,20,7,0 %; literal IPFINS$S_A4_R3 = 7; macro IPFINS$V_A4_IMM6D = 0,27,6,0 %; literal IPFINS$S_A4_IMM6D = 6; macro IPFINS$V_A4_VE = 4,1,1,0 %; macro IPFINS$V_A4_X2A = 4,2,2,0 %; literal IPFINS$S_A4_X2A = 2; macro IPFINS$V_A4_S = 4,4,1,1 %; macro IPFINS$V_A4_OPCODE = 4,5,4,0 %; literal IPFINS$S_A4_OPCODE = 4; macro IPFINS$Q_A4 = 0,0,0,0 %; literal IPFINS$S_A4 = 8; ! ! A5: Add Immediate(22) ! literal IPFINS$M_A5_QP = %X'3F'; literal IPFINS$M_A5_R1 = %X'1FC0'; literal IPFINS$M_A5_IMM7B = %X'FE000'; literal IPFINS$M_A5_R3 = %X'300000'; literal IPFINS$M_A5_IMM5C = %X'7C00000'; literal IPFINS$M_A5_IMM9D = %X'FF8000000'; literal IPFINS$M_A5_S = %X'1000000000'; literal IPFINS$M_A5_OPCODE = %X'1E000000000'; literal IPFINS$M_A5_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_A5_FORMAT = 8; macro IPFINS$V_A5_QP = 0,0,6,0 %; literal IPFINS$S_A5_QP = 6; macro IPFINS$V_A5_R1 = 0,6,7,0 %; literal IPFINS$S_A5_R1 = 7; macro IPFINS$V_A5_IMM7B = 0,13,7,0 %; literal IPFINS$S_A5_IMM7B = 7; macro IPFINS$V_A5_R3 = 0,20,2,0 %; literal IPFINS$S_A5_R3 = 2; macro IPFINS$V_A5_IMM5C = 0,22,5,0 %; literal IPFINS$S_A5_IMM5C = 5; macro IPFINS$V_A5_IMM9D = 0,27,9,0 %; literal IPFINS$S_A5_IMM9D = 9; macro IPFINS$V_A5_S = 4,4,1,1 %; macro IPFINS$V_A5_OPCODE = 4,5,4,0 %; literal IPFINS$S_A5_OPCODE = 4; macro IPFINS$Q_A5 = 0,0,0,0 %; literal IPFINS$S_A5 = 8; ! ! A6: Integer Compare - Register-Register ! literal IPFINS$M_A6_QP = %X'3F'; literal IPFINS$M_A6_P1 = %X'FC0'; literal IPFINS$M_A6_C = %X'1000'; literal IPFINS$M_A6_R2 = %X'FE000'; literal IPFINS$M_A6_R3 = %X'7F00000'; literal IPFINS$M_A6_P2 = %X'1F8000000'; literal IPFINS$M_A6_TA = %X'200000000'; literal IPFINS$M_A6_X2 = %X'C00000000'; literal IPFINS$M_A6_TB = %X'1000000000'; literal IPFINS$M_A6_OPCODE = %X'1E000000000'; literal IPFINS$M_A6_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_A6_FORMAT = 8; macro IPFINS$V_A6_QP = 0,0,6,0 %; literal IPFINS$S_A6_QP = 6; macro IPFINS$V_A6_P1 = 0,6,6,0 %; literal IPFINS$S_A6_P1 = 6; macro IPFINS$V_A6_C = 0,12,1,0 %; macro IPFINS$V_A6_R2 = 0,13,7,0 %; literal IPFINS$S_A6_R2 = 7; macro IPFINS$V_A6_R3 = 0,20,7,0 %; literal IPFINS$S_A6_R3 = 7; macro IPFINS$V_A6_P2 = 0,27,6,0 %; literal IPFINS$S_A6_P2 = 6; macro IPFINS$V_A6_TA = 4,1,1,0 %; macro IPFINS$V_A6_X2 = 4,2,2,0 %; literal IPFINS$S_A6_X2 = 2; macro IPFINS$V_A6_TB = 4,4,1,0 %; macro IPFINS$V_A6_OPCODE = 4,5,4,0 %; literal IPFINS$S_A6_OPCODE = 4; macro IPFINS$Q_A6 = 0,0,0,0 %; literal IPFINS$S_A6 = 8; ! ! A7: Integer Compare to Zero - Register ! literal IPFINS$M_A7_QP = %X'3F'; literal IPFINS$M_A7_P1 = %X'FC0'; literal IPFINS$M_A7_C = %X'1000'; literal IPFINS$M_A7_ZERO = %X'FE000'; literal IPFINS$M_A7_R3 = %X'7F00000'; literal IPFINS$M_A7_P2 = %X'1F8000000'; literal IPFINS$M_A7_TA = %X'200000000'; literal IPFINS$M_A7_X2 = %X'C00000000'; literal IPFINS$M_A7_TB = %X'1000000000'; literal IPFINS$M_A7_OPCODE = %X'1E000000000'; literal IPFINS$M_A7_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_A7_FORMAT = 8; macro IPFINS$V_A7_QP = 0,0,6,0 %; literal IPFINS$S_A7_QP = 6; macro IPFINS$V_A7_P1 = 0,6,6,0 %; literal IPFINS$S_A7_P1 = 6; macro IPFINS$V_A7_C = 0,12,1,0 %; macro IPFINS$V_A7_ZERO = 0,13,7,0 %; literal IPFINS$S_A7_ZERO = 7; macro IPFINS$V_A7_R3 = 0,20,7,0 %; literal IPFINS$S_A7_R3 = 7; macro IPFINS$V_A7_P2 = 0,27,6,0 %; literal IPFINS$S_A7_P2 = 6; macro IPFINS$V_A7_TA = 4,1,1,0 %; macro IPFINS$V_A7_X2 = 4,2,2,0 %; literal IPFINS$S_A7_X2 = 2; macro IPFINS$V_A7_TB = 4,4,1,0 %; macro IPFINS$V_A7_OPCODE = 4,5,4,0 %; literal IPFINS$S_A7_OPCODE = 4; macro IPFINS$Q_A7 = 0,0,0,0 %; literal IPFINS$S_A7 = 8; ! ! A8: Integer Compare - Immediate-Register ! literal IPFINS$M_A8_QP = %X'3F'; literal IPFINS$M_A8_P1 = %X'FC0'; literal IPFINS$M_A8_C = %X'1000'; literal IPFINS$M_A8_IMM7B = %X'FE000'; literal IPFINS$M_A8_R3 = %X'7F00000'; literal IPFINS$M_A8_P2 = %X'1F8000000'; literal IPFINS$M_A8_TA = %X'200000000'; literal IPFINS$M_A8_X2 = %X'C00000000'; literal IPFINS$M_A8_S = %X'1000000000'; literal IPFINS$M_A8_OPCODE = %X'1E000000000'; literal IPFINS$M_A8_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_A8_FORMAT = 8; macro IPFINS$V_A8_QP = 0,0,6,0 %; literal IPFINS$S_A8_QP = 6; macro IPFINS$V_A8_P1 = 0,6,6,0 %; literal IPFINS$S_A8_P1 = 6; macro IPFINS$V_A8_C = 0,12,1,0 %; macro IPFINS$V_A8_IMM7B = 0,13,7,0 %; literal IPFINS$S_A8_IMM7B = 7; macro IPFINS$V_A8_R3 = 0,20,7,0 %; literal IPFINS$S_A8_R3 = 7; macro IPFINS$V_A8_P2 = 0,27,6,0 %; literal IPFINS$S_A8_P2 = 6; macro IPFINS$V_A8_TA = 4,1,1,0 %; macro IPFINS$V_A8_X2 = 4,2,2,0 %; literal IPFINS$S_A8_X2 = 2; macro IPFINS$V_A8_S = 4,4,1,1 %; macro IPFINS$V_A8_OPCODE = 4,5,4,0 %; literal IPFINS$S_A8_OPCODE = 4; macro IPFINS$Q_A8 = 0,0,0,0 %; literal IPFINS$S_A8 = 8; ! ! A9: Multimedia ALU ! literal IPFINS$M_A9_QP = %X'3F'; literal IPFINS$M_A9_R1 = %X'1FC0'; literal IPFINS$M_A9_R2 = %X'FE000'; literal IPFINS$M_A9_R3 = %X'7F00000'; literal IPFINS$M_A9_X2B = %X'18000000'; literal IPFINS$M_A9_X4 = %X'1E0000000'; literal IPFINS$M_A9_ZB = %X'200000000'; literal IPFINS$M_A9_X2A = %X'C00000000'; literal IPFINS$M_A9_ZA = %X'1000000000'; literal IPFINS$M_A9_OPCODE = %X'1E000000000'; literal IPFINS$M_A9_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_A9_FORMAT = 8; macro IPFINS$V_A9_QP = 0,0,6,0 %; literal IPFINS$S_A9_QP = 6; macro IPFINS$V_A9_R1 = 0,6,7,0 %; literal IPFINS$S_A9_R1 = 7; macro IPFINS$V_A9_R2 = 0,13,7,0 %; literal IPFINS$S_A9_R2 = 7; macro IPFINS$V_A9_R3 = 0,20,7,0 %; literal IPFINS$S_A9_R3 = 7; macro IPFINS$V_A9_X2B = 0,27,2,0 %; literal IPFINS$S_A9_X2B = 2; macro IPFINS$V_A9_X4 = 0,29,4,0 %; literal IPFINS$S_A9_X4 = 4; macro IPFINS$V_A9_ZB = 4,1,1,0 %; macro IPFINS$V_A9_X2A = 4,2,2,0 %; literal IPFINS$S_A9_X2A = 2; macro IPFINS$V_A9_ZA = 4,4,1,0 %; macro IPFINS$V_A9_OPCODE = 4,5,4,0 %; literal IPFINS$S_A9_OPCODE = 4; macro IPFINS$Q_A9 = 0,0,0,0 %; literal IPFINS$S_A9 = 8; ! ! A10: Multimedia Shift and Add ! literal IPFINS$M_A10_QP = %X'3F'; literal IPFINS$M_A10_R1 = %X'1FC0'; literal IPFINS$M_A10_R2 = %X'FE000'; literal IPFINS$M_A10_R3 = %X'7F00000'; literal IPFINS$M_A10_CT2D = %X'18000000'; literal IPFINS$M_A10_X4 = %X'1E0000000'; literal IPFINS$M_A10_ZB = %X'200000000'; literal IPFINS$M_A10_X2A = %X'C00000000'; literal IPFINS$M_A10_ZA = %X'1000000000'; literal IPFINS$M_A10_OPCODE = %X'1E000000000'; literal IPFINS$M_A10_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_A10_FORMAT = 8; macro IPFINS$V_A10_QP = 0,0,6,0 %; literal IPFINS$S_A10_QP = 6; macro IPFINS$V_A10_R1 = 0,6,7,0 %; literal IPFINS$S_A10_R1 = 7; macro IPFINS$V_A10_R2 = 0,13,7,0 %; literal IPFINS$S_A10_R2 = 7; macro IPFINS$V_A10_R3 = 0,20,7,0 %; literal IPFINS$S_A10_R3 = 7; macro IPFINS$V_A10_CT2D = 0,27,2,0 %; literal IPFINS$S_A10_CT2D = 2; macro IPFINS$V_A10_X4 = 0,29,4,0 %; literal IPFINS$S_A10_X4 = 4; macro IPFINS$V_A10_ZB = 4,1,1,0 %; macro IPFINS$V_A10_X2A = 4,2,2,0 %; literal IPFINS$S_A10_X2A = 2; macro IPFINS$V_A10_ZA = 4,4,1,0 %; macro IPFINS$V_A10_OPCODE = 4,5,4,0 %; literal IPFINS$S_A10_OPCODE = 4; macro IPFINS$Q_A10 = 0,0,0,0 %; literal IPFINS$S_A10 = 8; ! ! I-Unit Formats ! ! ! I1: Multimedia Multiply and Shift ! literal IPFINS$M_I1_QP = %X'3F'; literal IPFINS$M_I1_R1 = %X'1FC0'; literal IPFINS$M_I1_R2 = %X'FE000'; literal IPFINS$M_I1_R3 = %X'7F00000'; literal IPFINS$M_I1_27 = %X'8000000'; literal IPFINS$M_I1_X2B = %X'30000000'; literal IPFINS$M_I1_CT2D = %X'C0000000'; literal IPFINS$M_I1_VE = %X'100000000'; literal IPFINS$M_I1_ZB = %X'200000000'; literal IPFINS$M_I1_X2A = %X'C00000000'; literal IPFINS$M_I1_ZA = %X'1000000000'; literal IPFINS$M_I1_OPCODE = %X'1E000000000'; literal IPFINS$M_I1_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I1_FORMAT = 8; macro IPFINS$V_I1_QP = 0,0,6,0 %; literal IPFINS$S_I1_QP = 6; macro IPFINS$V_I1_R1 = 0,6,7,0 %; literal IPFINS$S_I1_R1 = 7; macro IPFINS$V_I1_R2 = 0,13,7,0 %; literal IPFINS$S_I1_R2 = 7; macro IPFINS$V_I1_R3 = 0,20,7,0 %; literal IPFINS$S_I1_R3 = 7; macro IPFINS$V_I1_27 = 0,27,1,0 %; macro IPFINS$V_I1_X2B = 0,28,2,0 %; literal IPFINS$S_I1_X2B = 2; macro IPFINS$V_I1_CT2D = 0,30,2,0 %; literal IPFINS$S_I1_CT2D = 2; macro IPFINS$V_I1_VE = 4,0,1,0 %; macro IPFINS$V_I1_ZB = 4,1,1,0 %; macro IPFINS$V_I1_X2A = 4,2,2,0 %; literal IPFINS$S_I1_X2A = 2; macro IPFINS$V_I1_ZA = 4,4,1,0 %; macro IPFINS$V_I1_OPCODE = 4,5,4,0 %; literal IPFINS$S_I1_OPCODE = 4; macro IPFINS$Q_I1 = 0,0,0,0 %; literal IPFINS$S_I1 = 8; ! ! I2: Multimedia Multiply/Mix/Pack/Unpack ! literal IPFINS$M_I2_QP = %X'3F'; literal IPFINS$M_I2_R1 = %X'1FC0'; literal IPFINS$M_I2_R2 = %X'FE000'; literal IPFINS$M_I2_R3 = %X'7F00000'; literal IPFINS$M_I2_27 = %X'8000000'; literal IPFINS$M_I2_X2B = %X'30000000'; literal IPFINS$M_I2_X2C = %X'C0000000'; literal IPFINS$M_I2_VE = %X'100000000'; literal IPFINS$M_I2_ZB = %X'200000000'; literal IPFINS$M_I2_X2A = %X'C00000000'; literal IPFINS$M_I2_ZA = %X'1000000000'; literal IPFINS$M_I2_OPCODE = %X'1E000000000'; literal IPFINS$M_I2_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I2_FORMAT = 8; macro IPFINS$V_I2_QP = 0,0,6,0 %; literal IPFINS$S_I2_QP = 6; macro IPFINS$V_I2_R1 = 0,6,7,0 %; literal IPFINS$S_I2_R1 = 7; macro IPFINS$V_I2_R2 = 0,13,7,0 %; literal IPFINS$S_I2_R2 = 7; macro IPFINS$V_I2_R3 = 0,20,7,0 %; literal IPFINS$S_I2_R3 = 7; macro IPFINS$V_I2_27 = 0,27,1,0 %; macro IPFINS$V_I2_X2B = 0,28,2,0 %; literal IPFINS$S_I2_X2B = 2; macro IPFINS$V_I2_X2C = 0,30,2,0 %; literal IPFINS$S_I2_X2C = 2; macro IPFINS$V_I2_VE = 4,0,1,0 %; macro IPFINS$V_I2_ZB = 4,1,1,0 %; macro IPFINS$V_I2_X2A = 4,2,2,0 %; literal IPFINS$S_I2_X2A = 2; macro IPFINS$V_I2_ZA = 4,4,1,0 %; macro IPFINS$V_I2_OPCODE = 4,5,4,0 %; literal IPFINS$S_I2_OPCODE = 4; macro IPFINS$Q_I2 = 0,0,0,0 %; literal IPFINS$S_I2 = 8; ! ! I3: Multimedia Mux1 ! literal IPFINS$M_I3_QP = %X'3F'; literal IPFINS$M_I3_R1 = %X'1FC0'; literal IPFINS$M_I3_R2 = %X'FE000'; literal IPFINS$M_I3_MBT4C = %X'F00000'; literal IPFINS$M_I3_24_27 = %X'F000000'; literal IPFINS$M_I3_X2B = %X'30000000'; literal IPFINS$M_I3_X2C = %X'C0000000'; literal IPFINS$M_I3_VE = %X'100000000'; literal IPFINS$M_I3_ZB = %X'200000000'; literal IPFINS$M_I3_X2A = %X'C00000000'; literal IPFINS$M_I3_ZA = %X'1000000000'; literal IPFINS$M_I3_OPCODE = %X'1E000000000'; literal IPFINS$M_I3_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I3_FORMAT = 8; macro IPFINS$V_I3_QP = 0,0,6,0 %; literal IPFINS$S_I3_QP = 6; macro IPFINS$V_I3_R1 = 0,6,7,0 %; literal IPFINS$S_I3_R1 = 7; macro IPFINS$V_I3_R2 = 0,13,7,0 %; literal IPFINS$S_I3_R2 = 7; macro IPFINS$V_I3_MBT4C = 0,20,4,0 %; literal IPFINS$S_I3_MBT4C = 4; macro IPFINS$V_I3_24_27 = 0,24,4,0 %; literal IPFINS$S_I3_24_27 = 4; macro IPFINS$V_I3_X2B = 0,28,2,0 %; literal IPFINS$S_I3_X2B = 2; macro IPFINS$V_I3_X2C = 0,30,2,0 %; literal IPFINS$S_I3_X2C = 2; macro IPFINS$V_I3_VE = 4,0,1,0 %; macro IPFINS$V_I3_ZB = 4,1,1,0 %; macro IPFINS$V_I3_X2A = 4,2,2,0 %; literal IPFINS$S_I3_X2A = 2; macro IPFINS$V_I3_ZA = 4,4,1,0 %; macro IPFINS$V_I3_OPCODE = 4,5,4,0 %; literal IPFINS$S_I3_OPCODE = 4; macro IPFINS$Q_I3 = 0,0,0,0 %; literal IPFINS$S_I3 = 8; ! ! I4: Multimedia Mux2 ! literal IPFINS$M_I4_QP = %X'3F'; literal IPFINS$M_I4_R1 = %X'1FC0'; literal IPFINS$M_I4_R2 = %X'FE000'; literal IPFINS$M_I4_MHT8C = %X'FF00000'; literal IPFINS$M_I4_X2B = %X'30000000'; literal IPFINS$M_I4_X2C = %X'C0000000'; literal IPFINS$M_I4_VE = %X'100000000'; literal IPFINS$M_I4_ZB = %X'200000000'; literal IPFINS$M_I4_X2A = %X'C00000000'; literal IPFINS$M_I4_ZA = %X'1000000000'; literal IPFINS$M_I4_OPCODE = %X'1E000000000'; literal IPFINS$M_I4_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I4_FORMAT = 8; macro IPFINS$V_I4_QP = 0,0,6,0 %; literal IPFINS$S_I4_QP = 6; macro IPFINS$V_I4_R1 = 0,6,7,0 %; literal IPFINS$S_I4_R1 = 7; macro IPFINS$V_I4_R2 = 0,13,7,0 %; literal IPFINS$S_I4_R2 = 7; macro IPFINS$V_I4_MHT8C = 0,20,8,0 %; literal IPFINS$S_I4_MHT8C = 8; macro IPFINS$V_I4_X2B = 0,28,2,0 %; literal IPFINS$S_I4_X2B = 2; macro IPFINS$V_I4_X2C = 0,30,2,0 %; literal IPFINS$S_I4_X2C = 2; macro IPFINS$V_I4_VE = 4,0,1,0 %; macro IPFINS$V_I4_ZB = 4,1,1,0 %; macro IPFINS$V_I4_X2A = 4,2,2,0 %; literal IPFINS$S_I4_X2A = 2; macro IPFINS$V_I4_ZA = 4,4,1,0 %; macro IPFINS$V_I4_OPCODE = 4,5,4,0 %; literal IPFINS$S_I4_OPCODE = 4; macro IPFINS$Q_I4 = 0,0,0,0 %; literal IPFINS$S_I4 = 8; ! ! I5: Shift Right - Variable ! literal IPFINS$M_I5_QP = %X'3F'; literal IPFINS$M_I5_R1 = %X'1FC0'; literal IPFINS$M_I5_R2 = %X'FE000'; literal IPFINS$M_I5_R3 = %X'7F00000'; literal IPFINS$M_I5_27 = %X'8000000'; literal IPFINS$M_I5_X2B = %X'30000000'; literal IPFINS$M_I5_X2C = %X'C0000000'; literal IPFINS$M_I5_VE = %X'100000000'; literal IPFINS$M_I5_ZB = %X'200000000'; literal IPFINS$M_I5_X2A = %X'C00000000'; literal IPFINS$M_I5_ZA = %X'1000000000'; literal IPFINS$M_I5_OPCODE = %X'1E000000000'; literal IPFINS$M_I5_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I5_FORMAT = 8; macro IPFINS$V_I5_QP = 0,0,6,0 %; literal IPFINS$S_I5_QP = 6; macro IPFINS$V_I5_R1 = 0,6,7,0 %; literal IPFINS$S_I5_R1 = 7; macro IPFINS$V_I5_R2 = 0,13,7,0 %; literal IPFINS$S_I5_R2 = 7; macro IPFINS$V_I5_R3 = 0,20,7,0 %; literal IPFINS$S_I5_R3 = 7; macro IPFINS$V_I5_27 = 0,27,1,0 %; macro IPFINS$V_I5_X2B = 0,28,2,0 %; literal IPFINS$S_I5_X2B = 2; macro IPFINS$V_I5_X2C = 0,30,2,0 %; literal IPFINS$S_I5_X2C = 2; macro IPFINS$V_I5_VE = 4,0,1,0 %; macro IPFINS$V_I5_ZB = 4,1,1,0 %; macro IPFINS$V_I5_X2A = 4,2,2,0 %; literal IPFINS$S_I5_X2A = 2; macro IPFINS$V_I5_ZA = 4,4,1,0 %; macro IPFINS$V_I5_OPCODE = 4,5,4,0 %; literal IPFINS$S_I5_OPCODE = 4; macro IPFINS$Q_I5 = 0,0,0,0 %; literal IPFINS$S_I5 = 8; ! ! I6: Multimedia Shift Right - Fixed ! literal IPFINS$M_I6_QP = %X'3F'; literal IPFINS$M_I6_R1 = %X'1FC0'; literal IPFINS$M_I6_13 = %X'2000'; literal IPFINS$M_I6_COUNT5B = %X'7C000'; literal IPFINS$M_I6_19 = %X'80000'; literal IPFINS$M_I6_R3 = %X'7F00000'; literal IPFINS$M_I6_27 = %X'8000000'; literal IPFINS$M_I6_X2B = %X'30000000'; literal IPFINS$M_I6_X2C = %X'C0000000'; literal IPFINS$M_I6_VE = %X'100000000'; literal IPFINS$M_I6_ZB = %X'200000000'; literal IPFINS$M_I6_X2A = %X'C00000000'; literal IPFINS$M_I6_ZA = %X'1000000000'; literal IPFINS$M_I6_OPCODE = %X'1E000000000'; literal IPFINS$M_I6_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I6_FORMAT = 8; macro IPFINS$V_I6_QP = 0,0,6,0 %; literal IPFINS$S_I6_QP = 6; macro IPFINS$V_I6_R1 = 0,6,7,0 %; literal IPFINS$S_I6_R1 = 7; macro IPFINS$V_I6_13 = 0,13,1,0 %; macro IPFINS$V_I6_COUNT5B = 0,14,5,0 %; literal IPFINS$S_I6_COUNT5B = 5; macro IPFINS$V_I6_19 = 0,19,1,0 %; macro IPFINS$V_I6_R3 = 0,20,7,0 %; literal IPFINS$S_I6_R3 = 7; macro IPFINS$V_I6_27 = 0,27,1,0 %; macro IPFINS$V_I6_X2B = 0,28,2,0 %; literal IPFINS$S_I6_X2B = 2; macro IPFINS$V_I6_X2C = 0,30,2,0 %; literal IPFINS$S_I6_X2C = 2; macro IPFINS$V_I6_VE = 4,0,1,0 %; macro IPFINS$V_I6_ZB = 4,1,1,0 %; macro IPFINS$V_I6_X2A = 4,2,2,0 %; literal IPFINS$S_I6_X2A = 2; macro IPFINS$V_I6_ZA = 4,4,1,0 %; macro IPFINS$V_I6_OPCODE = 4,5,4,0 %; literal IPFINS$S_I6_OPCODE = 4; macro IPFINS$Q_I6 = 0,0,0,0 %; literal IPFINS$S_I6 = 8; ! ! I7: Shift Left - Variable ! literal IPFINS$M_I7_QP = %X'3F'; literal IPFINS$M_I7_R1 = %X'1FC0'; literal IPFINS$M_I7_R2 = %X'FE000'; literal IPFINS$M_I7_R3 = %X'7F00000'; literal IPFINS$M_I7_27 = %X'8000000'; literal IPFINS$M_I7_X2B = %X'30000000'; literal IPFINS$M_I7_X2C = %X'C0000000'; literal IPFINS$M_I7_VE = %X'100000000'; literal IPFINS$M_I7_ZB = %X'200000000'; literal IPFINS$M_I7_X2A = %X'C00000000'; literal IPFINS$M_I7_ZA = %X'1000000000'; literal IPFINS$M_I7_OPCODE = %X'1E000000000'; literal IPFINS$M_I7_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I7_FORMAT = 8; macro IPFINS$V_I7_QP = 0,0,6,0 %; literal IPFINS$S_I7_QP = 6; macro IPFINS$V_I7_R1 = 0,6,7,0 %; literal IPFINS$S_I7_R1 = 7; macro IPFINS$V_I7_R2 = 0,13,7,0 %; literal IPFINS$S_I7_R2 = 7; macro IPFINS$V_I7_R3 = 0,20,7,0 %; literal IPFINS$S_I7_R3 = 7; macro IPFINS$V_I7_27 = 0,27,1,0 %; macro IPFINS$V_I7_X2B = 0,28,2,0 %; literal IPFINS$S_I7_X2B = 2; macro IPFINS$V_I7_X2C = 0,30,2,0 %; literal IPFINS$S_I7_X2C = 2; macro IPFINS$V_I7_VE = 4,0,1,0 %; macro IPFINS$V_I7_ZB = 4,1,1,0 %; macro IPFINS$V_I7_X2A = 4,2,2,0 %; literal IPFINS$S_I7_X2A = 2; macro IPFINS$V_I7_ZA = 4,4,1,0 %; macro IPFINS$V_I7_OPCODE = 4,5,4,0 %; literal IPFINS$S_I7_OPCODE = 4; macro IPFINS$Q_I7 = 0,0,0,0 %; literal IPFINS$S_I7 = 8; ! ! I8: Multimedia Shift Left - Fixed ! literal IPFINS$M_I8_QP = %X'3F'; literal IPFINS$M_I8_R1 = %X'1FC0'; literal IPFINS$M_I8_R2 = %X'FE000'; literal IPFINS$M_I8_CCOUNT5C = %X'1F00000'; literal IPFINS$M_I8_25_27 = %X'E000000'; literal IPFINS$M_I8_X2B = %X'30000000'; literal IPFINS$M_I8_X2C = %X'C0000000'; literal IPFINS$M_I8_VE = %X'100000000'; literal IPFINS$M_I8_ZB = %X'200000000'; literal IPFINS$M_I8_X2A = %X'C00000000'; literal IPFINS$M_I8_ZA = %X'1000000000'; literal IPFINS$M_I8_OPCODE = %X'1E000000000'; literal IPFINS$M_I8_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I8_FORMAT = 8; macro IPFINS$V_I8_QP = 0,0,6,0 %; literal IPFINS$S_I8_QP = 6; macro IPFINS$V_I8_R1 = 0,6,7,0 %; literal IPFINS$S_I8_R1 = 7; macro IPFINS$V_I8_R2 = 0,13,7,0 %; literal IPFINS$S_I8_R2 = 7; macro IPFINS$V_I8_CCOUNT5C = 0,20,5,0 %; literal IPFINS$S_I8_CCOUNT5C = 5; macro IPFINS$V_I8_25_27 = 0,25,3,0 %; literal IPFINS$S_I8_25_27 = 3; macro IPFINS$V_I8_X2B = 0,28,2,0 %; literal IPFINS$S_I8_X2B = 2; macro IPFINS$V_I8_X2C = 0,30,2,0 %; literal IPFINS$S_I8_X2C = 2; macro IPFINS$V_I8_VE = 4,0,1,0 %; macro IPFINS$V_I8_ZB = 4,1,1,0 %; macro IPFINS$V_I8_X2A = 4,2,2,0 %; literal IPFINS$S_I8_X2A = 2; macro IPFINS$V_I8_ZA = 4,4,1,0 %; macro IPFINS$V_I8_OPCODE = 4,5,4,0 %; literal IPFINS$S_I8_OPCODE = 4; macro IPFINS$Q_I8 = 0,0,0,0 %; literal IPFINS$S_I8 = 8; ! ! I9: Population Count ! literal IPFINS$M_I9_QP = %X'3F'; literal IPFINS$M_I9_R1 = %X'1FC0'; literal IPFINS$M_I9_ZERO = %X'FE000'; literal IPFINS$M_I9_R3 = %X'7F00000'; literal IPFINS$M_I9_27 = %X'8000000'; literal IPFINS$M_I9_X2B = %X'30000000'; literal IPFINS$M_I9_X2C = %X'C0000000'; literal IPFINS$M_I9_VE = %X'100000000'; literal IPFINS$M_I9_ZB = %X'200000000'; literal IPFINS$M_I9_X2A = %X'C00000000'; literal IPFINS$M_I9_ZA = %X'1000000000'; literal IPFINS$M_I9_OPCODE = %X'1E000000000'; literal IPFINS$M_I9_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I9_FORMAT = 8; macro IPFINS$V_I9_QP = 0,0,6,0 %; literal IPFINS$S_I9_QP = 6; macro IPFINS$V_I9_R1 = 0,6,7,0 %; literal IPFINS$S_I9_R1 = 7; macro IPFINS$V_I9_ZERO = 0,13,7,0 %; literal IPFINS$S_I9_ZERO = 7; macro IPFINS$V_I9_R3 = 0,20,7,0 %; literal IPFINS$S_I9_R3 = 7; macro IPFINS$V_I9_27 = 0,27,1,0 %; macro IPFINS$V_I9_X2B = 0,28,2,0 %; literal IPFINS$S_I9_X2B = 2; macro IPFINS$V_I9_X2C = 0,30,2,0 %; literal IPFINS$S_I9_X2C = 2; macro IPFINS$V_I9_VE = 4,0,1,0 %; macro IPFINS$V_I9_ZB = 4,1,1,0 %; macro IPFINS$V_I9_X2A = 4,2,2,0 %; literal IPFINS$S_I9_X2A = 2; macro IPFINS$V_I9_ZA = 4,4,1,0 %; macro IPFINS$V_I9_OPCODE = 4,5,4,0 %; literal IPFINS$S_I9_OPCODE = 4; macro IPFINS$Q_I9 = 0,0,0,0 %; literal IPFINS$S_I9 = 8; ! ! I10: Shift Right Pair ! literal IPFINS$M_I10_QP = %X'3F'; literal IPFINS$M_I10_R1 = %X'1FC0'; literal IPFINS$M_I10_R2 = %X'FE000'; literal IPFINS$M_I10_R3 = %X'7F00000'; literal IPFINS$M_I10_COUNT6D = %X'1F8000000'; literal IPFINS$M_I10_X = %X'200000000'; literal IPFINS$M_I10_X2 = %X'C00000000'; literal IPFINS$M_I10_36 = %X'1000000000'; literal IPFINS$M_I10_OPCODE = %X'1E000000000'; literal IPFINS$M_I10_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I10_FORMAT = 8; macro IPFINS$V_I10_QP = 0,0,6,0 %; literal IPFINS$S_I10_QP = 6; macro IPFINS$V_I10_R1 = 0,6,7,0 %; literal IPFINS$S_I10_R1 = 7; macro IPFINS$V_I10_R2 = 0,13,7,0 %; literal IPFINS$S_I10_R2 = 7; macro IPFINS$V_I10_R3 = 0,20,7,0 %; literal IPFINS$S_I10_R3 = 7; macro IPFINS$V_I10_COUNT6D = 0,27,6,0 %; literal IPFINS$S_I10_COUNT6D = 6; macro IPFINS$V_I10_X = 4,1,1,0 %; macro IPFINS$V_I10_X2 = 4,2,2,0 %; literal IPFINS$S_I10_X2 = 2; macro IPFINS$V_I10_36 = 4,4,1,0 %; macro IPFINS$V_I10_OPCODE = 4,5,4,0 %; literal IPFINS$S_I10_OPCODE = 4; macro IPFINS$Q_I10 = 0,0,0,0 %; literal IPFINS$S_I10 = 8; ! ! I11: Extract ! literal IPFINS$M_I11_QP = %X'3F'; literal IPFINS$M_I11_R1 = %X'1FC0'; literal IPFINS$M_I11_Y = %X'2000'; literal IPFINS$M_I11_POS6B = %X'FC000'; literal IPFINS$M_I11_R3 = %X'7F00000'; literal IPFINS$M_I11_LEN6D = %X'1F8000000'; literal IPFINS$M_I11_X = %X'200000000'; literal IPFINS$M_I11_X2 = %X'C00000000'; literal IPFINS$M_I11_36 = %X'1000000000'; literal IPFINS$M_I11_OPCODE = %X'1E000000000'; literal IPFINS$M_I11_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I11_FORMAT = 8; macro IPFINS$V_I11_QP = 0,0,6,0 %; literal IPFINS$S_I11_QP = 6; macro IPFINS$V_I11_R1 = 0,6,7,0 %; literal IPFINS$S_I11_R1 = 7; macro IPFINS$V_I11_Y = 0,13,1,0 %; macro IPFINS$V_I11_POS6B = 0,14,6,0 %; literal IPFINS$S_I11_POS6B = 6; macro IPFINS$V_I11_R3 = 0,20,7,0 %; literal IPFINS$S_I11_R3 = 7; macro IPFINS$V_I11_LEN6D = 0,27,6,0 %; literal IPFINS$S_I11_LEN6D = 6; macro IPFINS$V_I11_X = 4,1,1,0 %; macro IPFINS$V_I11_X2 = 4,2,2,0 %; literal IPFINS$S_I11_X2 = 2; macro IPFINS$V_I11_36 = 4,4,1,0 %; macro IPFINS$V_I11_OPCODE = 4,5,4,0 %; literal IPFINS$S_I11_OPCODE = 4; macro IPFINS$Q_I11 = 0,0,0,0 %; literal IPFINS$S_I11 = 8; ! ! I12: Zero and Deposit ! literal IPFINS$M_I12_QP = %X'3F'; literal IPFINS$M_I12_R1 = %X'1FC0'; literal IPFINS$M_I12_R2 = %X'FE000'; literal IPFINS$M_I12_CPOS6C = %X'3F00000'; literal IPFINS$M_I12_Y = %X'4000000'; literal IPFINS$M_I12_LEN6D = %X'1F8000000'; literal IPFINS$M_I12_X = %X'200000000'; literal IPFINS$M_I12_X2 = %X'C00000000'; literal IPFINS$M_I12_36 = %X'1000000000'; literal IPFINS$M_I12_OPCODE = %X'1E000000000'; literal IPFINS$M_I12_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I12_FORMAT = 8; macro IPFINS$V_I12_QP = 0,0,6,0 %; literal IPFINS$S_I12_QP = 6; macro IPFINS$V_I12_R1 = 0,6,7,0 %; literal IPFINS$S_I12_R1 = 7; macro IPFINS$V_I12_R2 = 0,13,7,0 %; literal IPFINS$S_I12_R2 = 7; macro IPFINS$V_I12_CPOS6C = 0,20,6,0 %; literal IPFINS$S_I12_CPOS6C = 6; macro IPFINS$V_I12_Y = 0,26,1,0 %; macro IPFINS$V_I12_LEN6D = 0,27,6,0 %; literal IPFINS$S_I12_LEN6D = 6; macro IPFINS$V_I12_X = 4,1,1,0 %; macro IPFINS$V_I12_X2 = 4,2,2,0 %; literal IPFINS$S_I12_X2 = 2; macro IPFINS$V_I12_36 = 4,4,1,0 %; macro IPFINS$V_I12_OPCODE = 4,5,4,0 %; literal IPFINS$S_I12_OPCODE = 4; macro IPFINS$Q_I12 = 0,0,0,0 %; literal IPFINS$S_I12 = 8; ! ! I13: Zero and Deposit Immediate(8) ! literal IPFINS$M_I13_QP = %X'3F'; literal IPFINS$M_I13_R1 = %X'1FC0'; literal IPFINS$M_I13_IMM7B = %X'FE000'; literal IPFINS$M_I13_CPOS6C = %X'3F00000'; literal IPFINS$M_I13_Y = %X'4000000'; literal IPFINS$M_I13_LEN6D = %X'1F8000000'; literal IPFINS$M_I13_X = %X'200000000'; literal IPFINS$M_I13_X2 = %X'C00000000'; literal IPFINS$M_I13_S = %X'1000000000'; literal IPFINS$M_I13_OPCODE = %X'1E000000000'; literal IPFINS$M_I13_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I13_FORMAT = 8; macro IPFINS$V_I13_QP = 0,0,6,0 %; literal IPFINS$S_I13_QP = 6; macro IPFINS$V_I13_R1 = 0,6,7,0 %; literal IPFINS$S_I13_R1 = 7; macro IPFINS$V_I13_IMM7B = 0,13,7,0 %; literal IPFINS$S_I13_IMM7B = 7; macro IPFINS$V_I13_CPOS6C = 0,20,6,0 %; literal IPFINS$S_I13_CPOS6C = 6; macro IPFINS$V_I13_Y = 0,26,1,0 %; macro IPFINS$V_I13_LEN6D = 0,27,6,0 %; literal IPFINS$S_I13_LEN6D = 6; macro IPFINS$V_I13_X = 4,1,1,0 %; macro IPFINS$V_I13_X2 = 4,2,2,0 %; literal IPFINS$S_I13_X2 = 2; macro IPFINS$V_I13_S = 4,4,1,1 %; macro IPFINS$V_I13_OPCODE = 4,5,4,0 %; literal IPFINS$S_I13_OPCODE = 4; macro IPFINS$Q_I13 = 0,0,0,0 %; literal IPFINS$S_I13 = 8; ! ! I14: Deposit Immediate(1) ! literal IPFINS$M_I14_QP = %X'3F'; literal IPFINS$M_I14_R1 = %X'1FC0'; literal IPFINS$M_I14_13 = %X'2000'; literal IPFINS$M_I14_CPOS6B = %X'FC000'; literal IPFINS$M_I14_R3 = %X'7F00000'; literal IPFINS$M_I14_LEN6D = %X'1F8000000'; literal IPFINS$M_I14_X = %X'200000000'; literal IPFINS$M_I14_X2 = %X'C00000000'; literal IPFINS$M_I14_S = %X'1000000000'; literal IPFINS$M_I14_OPCODE = %X'1E000000000'; literal IPFINS$M_I14_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I14_FORMAT = 8; macro IPFINS$V_I14_QP = 0,0,6,0 %; literal IPFINS$S_I14_QP = 6; macro IPFINS$V_I14_R1 = 0,6,7,0 %; literal IPFINS$S_I14_R1 = 7; macro IPFINS$V_I14_13 = 0,13,1,0 %; macro IPFINS$V_I14_CPOS6B = 0,14,6,0 %; literal IPFINS$S_I14_CPOS6B = 6; macro IPFINS$V_I14_R3 = 0,20,7,0 %; literal IPFINS$S_I14_R3 = 7; macro IPFINS$V_I14_LEN6D = 0,27,6,0 %; literal IPFINS$S_I14_LEN6D = 6; macro IPFINS$V_I14_X = 4,1,1,0 %; macro IPFINS$V_I14_X2 = 4,2,2,0 %; literal IPFINS$S_I14_X2 = 2; macro IPFINS$V_I14_S = 4,4,1,1 %; macro IPFINS$V_I14_OPCODE = 4,5,4,0 %; literal IPFINS$S_I14_OPCODE = 4; macro IPFINS$Q_I14 = 0,0,0,0 %; literal IPFINS$S_I14 = 8; ! ! I15: Deposit ! literal IPFINS$M_I15_QP = %X'3F'; literal IPFINS$M_I15_R1 = %X'1FC0'; literal IPFINS$M_I15_R2 = %X'FE000'; literal IPFINS$M_I15_R3 = %X'7F00000'; literal IPFINS$M_I15_LEN4D = %X'78000000'; literal IPFINS$M_I15_CPOS6D = %X'1F80000000'; literal IPFINS$M_I15_OPCODE = %X'1E000000000'; literal IPFINS$M_I15_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I15_FORMAT = 8; macro IPFINS$V_I15_QP = 0,0,6,0 %; literal IPFINS$S_I15_QP = 6; macro IPFINS$V_I15_R1 = 0,6,7,0 %; literal IPFINS$S_I15_R1 = 7; macro IPFINS$V_I15_R2 = 0,13,7,0 %; literal IPFINS$S_I15_R2 = 7; macro IPFINS$V_I15_R3 = 0,20,7,0 %; literal IPFINS$S_I15_R3 = 7; macro IPFINS$V_I15_LEN4D = 0,27,4,0 %; literal IPFINS$S_I15_LEN4D = 4; macro IPFINS$V_I15_CPOS6D = 0,31,6,0 %; literal IPFINS$S_I15_CPOS6D = 6; macro IPFINS$V_I15_OPCODE = 4,5,4,0 %; literal IPFINS$S_I15_OPCODE = 4; macro IPFINS$Q_I15 = 0,0,0,0 %; literal IPFINS$S_I15 = 8; ! ! I16: Test Bit ! literal IPFINS$M_I16_QP = %X'3F'; literal IPFINS$M_I16_P1 = %X'FC0'; literal IPFINS$M_I16_C = %X'1000'; literal IPFINS$M_I16_Y = %X'2000'; literal IPFINS$M_I16_POS6B = %X'FC000'; literal IPFINS$M_I16_R3 = %X'7F00000'; literal IPFINS$M_I16_P2 = %X'1F8000000'; literal IPFINS$M_I16_TA = %X'200000000'; literal IPFINS$M_I16_X2 = %X'C00000000'; literal IPFINS$M_I16_TB = %X'1000000000'; literal IPFINS$M_I16_OPCODE = %X'1E000000000'; literal IPFINS$M_I16_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I16_FORMAT = 8; macro IPFINS$V_I16_QP = 0,0,6,0 %; literal IPFINS$S_I16_QP = 6; macro IPFINS$V_I16_P1 = 0,6,6,0 %; literal IPFINS$S_I16_P1 = 6; macro IPFINS$V_I16_C = 0,12,1,0 %; macro IPFINS$V_I16_Y = 0,13,1,0 %; macro IPFINS$V_I16_POS6B = 0,14,6,0 %; literal IPFINS$S_I16_POS6B = 6; macro IPFINS$V_I16_R3 = 0,20,7,0 %; literal IPFINS$S_I16_R3 = 7; macro IPFINS$V_I16_P2 = 0,27,6,0 %; literal IPFINS$S_I16_P2 = 6; macro IPFINS$V_I16_TA = 4,1,1,0 %; macro IPFINS$V_I16_X2 = 4,2,2,0 %; literal IPFINS$S_I16_X2 = 2; macro IPFINS$V_I16_TB = 4,4,1,0 %; macro IPFINS$V_I16_OPCODE = 4,5,4,0 %; literal IPFINS$S_I16_OPCODE = 4; macro IPFINS$Q_I16 = 0,0,0,0 %; literal IPFINS$S_I16 = 8; ! ! I17: Test NaT ! literal IPFINS$M_I17_QP = %X'3F'; literal IPFINS$M_I17_P1 = %X'FC0'; literal IPFINS$M_I17_C = %X'1000'; literal IPFINS$M_I17_Y = %X'2000'; literal IPFINS$M_I17_14_18 = %X'7C000'; literal IPFINS$M_I17_X = %X'80000'; literal IPFINS$M_I17_R3 = %X'7F00000'; literal IPFINS$M_I17_P2 = %X'1F8000000'; literal IPFINS$M_I17_TA = %X'200000000'; literal IPFINS$M_I17_X2 = %X'C00000000'; literal IPFINS$M_I17_TB = %X'1000000000'; literal IPFINS$M_I17_OPCODE = %X'1E000000000'; literal IPFINS$M_I17_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I17_FORMAT = 8; macro IPFINS$V_I17_QP = 0,0,6,0 %; literal IPFINS$S_I17_QP = 6; macro IPFINS$V_I17_P1 = 0,6,6,0 %; literal IPFINS$S_I17_P1 = 6; macro IPFINS$V_I17_C = 0,12,1,0 %; macro IPFINS$V_I17_Y = 0,13,1,0 %; macro IPFINS$V_I17_14_18 = 0,14,5,0 %; literal IPFINS$S_I17_14_18 = 5; macro IPFINS$V_I17_X = 0,19,1,0 %; macro IPFINS$V_I17_R3 = 0,20,7,0 %; literal IPFINS$S_I17_R3 = 7; macro IPFINS$V_I17_P2 = 0,27,6,0 %; literal IPFINS$S_I17_P2 = 6; macro IPFINS$V_I17_TA = 4,1,1,0 %; macro IPFINS$V_I17_X2 = 4,2,2,0 %; literal IPFINS$S_I17_X2 = 2; macro IPFINS$V_I17_TB = 4,4,1,0 %; macro IPFINS$V_I17_OPCODE = 4,5,4,0 %; literal IPFINS$S_I17_OPCODE = 4; macro IPFINS$Q_I17 = 0,0,0,0 %; literal IPFINS$S_I17 = 8; ! ! I18: Nop/Hint (I-Unit) ! literal IPFINS$M_I18_QP = %X'3F'; literal IPFINS$M_I18_IMM20A = %X'3FFFFC0'; literal IPFINS$M_I18_Y = %X'4000000'; literal IPFINS$M_I18_X6 = %X'1F8000000'; literal IPFINS$M_I18_X3 = %X'E00000000'; literal IPFINS$M_I18_I = %X'1000000000'; literal IPFINS$M_I18_OPCODE = %X'1E000000000'; literal IPFINS$M_I18_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I18_FORMAT = 8; macro IPFINS$V_I18_QP = 0,0,6,0 %; literal IPFINS$S_I18_QP = 6; macro IPFINS$V_I18_IMM20A = 0,6,20,0 %; literal IPFINS$S_I18_IMM20A = 20; macro IPFINS$V_I18_Y = 0,26,1,0 %; macro IPFINS$V_I18_X6 = 0,27,6,0 %; literal IPFINS$S_I18_X6 = 6; macro IPFINS$V_I18_X3 = 4,1,3,0 %; literal IPFINS$S_I18_X3 = 3; macro IPFINS$V_I18_I = 4,4,1,0 %; macro IPFINS$V_I18_OPCODE = 4,5,4,0 %; literal IPFINS$S_I18_OPCODE = 4; macro IPFINS$Q_I18 = 0,0,0,0 %; literal IPFINS$S_I18 = 8; ! ! I19: Break (I-Unit) ! literal IPFINS$M_I19_QP = %X'3F'; literal IPFINS$M_I19_IMM20A = %X'3FFFFC0'; literal IPFINS$M_I19_26 = %X'4000000'; literal IPFINS$M_I19_X6 = %X'1F8000000'; literal IPFINS$M_I19_X3 = %X'E00000000'; literal IPFINS$M_I19_I = %X'1000000000'; literal IPFINS$M_I19_OPCODE = %X'1E000000000'; literal IPFINS$M_I19_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I19_FORMAT = 8; macro IPFINS$V_I19_QP = 0,0,6,0 %; literal IPFINS$S_I19_QP = 6; macro IPFINS$V_I19_IMM20A = 0,6,20,0 %; literal IPFINS$S_I19_IMM20A = 20; macro IPFINS$V_I19_26 = 0,26,1,0 %; macro IPFINS$V_I19_X6 = 0,27,6,0 %; literal IPFINS$S_I19_X6 = 6; macro IPFINS$V_I19_X3 = 4,1,3,0 %; literal IPFINS$S_I19_X3 = 3; macro IPFINS$V_I19_I = 4,4,1,0 %; macro IPFINS$V_I19_OPCODE = 4,5,4,0 %; literal IPFINS$S_I19_OPCODE = 4; macro IPFINS$Q_I19 = 0,0,0,0 %; literal IPFINS$S_I19 = 8; ! ! I20: Integer Speculation Check (I-Unit) ! literal IPFINS$M_I20_QP = %X'3F'; literal IPFINS$M_I20_IMM7A = %X'1FC0'; literal IPFINS$M_I20_R2 = %X'FE000'; literal IPFINS$M_I20_IMM13C = %X'1FFF00000'; literal IPFINS$M_I20_X3 = %X'E00000000'; literal IPFINS$M_I20_S = %X'1000000000'; literal IPFINS$M_I20_OPCODE = %X'1E000000000'; literal IPFINS$M_I20_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I20_FORMAT = 8; macro IPFINS$V_I20_QP = 0,0,6,0 %; literal IPFINS$S_I20_QP = 6; macro IPFINS$V_I20_IMM7A = 0,6,7,0 %; literal IPFINS$S_I20_IMM7A = 7; macro IPFINS$V_I20_R2 = 0,13,7,0 %; literal IPFINS$S_I20_R2 = 7; macro IPFINS$V_I20_IMM13C = 0,20,13,0 %; literal IPFINS$S_I20_IMM13C = 13; macro IPFINS$V_I20_X3 = 4,1,3,0 %; literal IPFINS$S_I20_X3 = 3; macro IPFINS$V_I20_S = 4,4,1,1 %; macro IPFINS$V_I20_OPCODE = 4,5,4,0 %; literal IPFINS$S_I20_OPCODE = 4; macro IPFINS$Q_I20 = 0,0,0,0 %; literal IPFINS$S_I20 = 8; ! ! I21: Move to BR ! literal IPFINS$M_I21_QP = %X'3F'; literal IPFINS$M_I21_B1 = %X'1C0'; literal IPFINS$M_I21_9_12 = %X'1E00'; literal IPFINS$M_I21_R2 = %X'FE000'; literal IPFINS$M_I21_WH = %X'300000'; literal IPFINS$M_I21_X = %X'400000'; literal IPFINS$M_I21_IH = %X'800000'; literal IPFINS$M_I21_TIMM9C = %X'1FF000000'; literal IPFINS$M_I21_X3 = %X'E00000000'; literal IPFINS$M_I21_36 = %X'1000000000'; literal IPFINS$M_I21_OPCODE = %X'1E000000000'; literal IPFINS$M_I21_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I21_FORMAT = 8; macro IPFINS$V_I21_QP = 0,0,6,0 %; literal IPFINS$S_I21_QP = 6; macro IPFINS$V_I21_B1 = 0,6,3,0 %; literal IPFINS$S_I21_B1 = 3; macro IPFINS$V_I21_9_12 = 0,9,4,0 %; literal IPFINS$S_I21_9_12 = 4; macro IPFINS$V_I21_R2 = 0,13,7,0 %; literal IPFINS$S_I21_R2 = 7; macro IPFINS$V_I21_WH = 0,20,2,0 %; literal IPFINS$S_I21_WH = 2; macro IPFINS$V_I21_X = 0,22,1,0 %; macro IPFINS$V_I21_IH = 0,23,1,0 %; macro IPFINS$V_I21_TIMM9C = 0,24,9,1 %; literal IPFINS$S_I21_TIMM9C = 9; macro IPFINS$V_I21_X3 = 4,1,3,0 %; literal IPFINS$S_I21_X3 = 3; macro IPFINS$V_I21_36 = 4,4,1,0 %; macro IPFINS$V_I21_OPCODE = 4,5,4,0 %; literal IPFINS$S_I21_OPCODE = 4; macro IPFINS$Q_I21 = 0,0,0,0 %; literal IPFINS$S_I21 = 8; ! ! I22: Move from BR ! literal IPFINS$M_I22_QP = %X'3F'; literal IPFINS$M_I22_R1 = %X'1FC0'; literal IPFINS$M_I22_B2 = %X'E000'; literal IPFINS$M_I22_16_26 = %X'7FF0000'; literal IPFINS$M_I22_X6 = %X'1F8000000'; literal IPFINS$M_I22_X3 = %X'E00000000'; literal IPFINS$M_I22_36 = %X'1000000000'; literal IPFINS$M_I22_OPCODE = %X'1E000000000'; literal IPFINS$M_I22_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I22_FORMAT = 8; macro IPFINS$V_I22_QP = 0,0,6,0 %; literal IPFINS$S_I22_QP = 6; macro IPFINS$V_I22_R1 = 0,6,7,0 %; literal IPFINS$S_I22_R1 = 7; macro IPFINS$V_I22_B2 = 0,13,3,0 %; literal IPFINS$S_I22_B2 = 3; macro IPFINS$V_I22_16_26 = 0,16,11,0 %; literal IPFINS$S_I22_16_26 = 11; macro IPFINS$V_I22_X6 = 0,27,6,0 %; literal IPFINS$S_I22_X6 = 6; macro IPFINS$V_I22_X3 = 4,1,3,0 %; literal IPFINS$S_I22_X3 = 3; macro IPFINS$V_I22_36 = 4,4,1,0 %; macro IPFINS$V_I22_OPCODE = 4,5,4,0 %; literal IPFINS$S_I22_OPCODE = 4; macro IPFINS$Q_I22 = 0,0,0,0 %; literal IPFINS$S_I22 = 8; ! ! I23: Move to Predicates - Register ! literal IPFINS$M_I23_QP = %X'3F'; literal IPFINS$M_I23_MASK7A = %X'1FC0'; literal IPFINS$M_I23_R2 = %X'FE000'; literal IPFINS$M_I23_20_23 = %X'F00000'; literal IPFINS$M_I23_MASK8C = %X'FF000000'; literal IPFINS$M_I23_32 = %X'100000000'; literal IPFINS$M_I23_X3 = %X'E00000000'; literal IPFINS$M_I23_S = %X'1000000000'; literal IPFINS$M_I23_OPCODE = %X'1E000000000'; literal IPFINS$M_I23_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I23_FORMAT = 8; macro IPFINS$V_I23_QP = 0,0,6,0 %; literal IPFINS$S_I23_QP = 6; macro IPFINS$V_I23_MASK7A = 0,6,7,0 %; literal IPFINS$S_I23_MASK7A = 7; macro IPFINS$V_I23_R2 = 0,13,7,0 %; literal IPFINS$S_I23_R2 = 7; macro IPFINS$V_I23_20_23 = 0,20,4,0 %; literal IPFINS$S_I23_20_23 = 4; macro IPFINS$V_I23_MASK8C = 0,24,8,0 %; literal IPFINS$S_I23_MASK8C = 8; macro IPFINS$V_I23_32 = 4,0,1,0 %; macro IPFINS$V_I23_X3 = 4,1,3,0 %; literal IPFINS$S_I23_X3 = 3; macro IPFINS$V_I23_S = 4,4,1,1 %; macro IPFINS$V_I23_OPCODE = 4,5,4,0 %; literal IPFINS$S_I23_OPCODE = 4; macro IPFINS$Q_I23 = 0,0,0,0 %; literal IPFINS$S_I23 = 8; ! ! I24: Move to Predicates - Immediate(44) ! literal IPFINS$M_I24_QP = %X'3F'; literal IPFINS$M_I24_IMM27A = %X'1FFFFFFC0'; literal IPFINS$M_I24_X3 = %X'E00000000'; literal IPFINS$M_I24_S = %X'1000000000'; literal IPFINS$M_I24_OPCODE = %X'1E000000000'; literal IPFINS$M_I24_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I24_FORMAT = 8; macro IPFINS$V_I24_QP = 0,0,6,0 %; literal IPFINS$S_I24_QP = 6; macro IPFINS$V_I24_IMM27A = 0,6,27,0 %; literal IPFINS$S_I24_IMM27A = 27; macro IPFINS$V_I24_X3 = 4,1,3,0 %; literal IPFINS$S_I24_X3 = 3; macro IPFINS$V_I24_S = 4,4,1,1 %; macro IPFINS$V_I24_OPCODE = 4,5,4,0 %; literal IPFINS$S_I24_OPCODE = 4; macro IPFINS$Q_I24 = 0,0,0,0 %; literal IPFINS$S_I24 = 8; ! ! I25: Move from Predicates/IP ! literal IPFINS$M_I25_QP = %X'3F'; literal IPFINS$M_I25_R1 = %X'1FC0'; literal IPFINS$M_I25_13_26 = %X'7FFE000'; literal IPFINS$M_I25_X6 = %X'1F8000000'; literal IPFINS$M_I25_X3 = %X'E00000000'; literal IPFINS$M_I25_36 = %X'1000000000'; literal IPFINS$M_I25_OPCODE = %X'1E000000000'; literal IPFINS$M_I25_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I25_FORMAT = 8; macro IPFINS$V_I25_QP = 0,0,6,0 %; literal IPFINS$S_I25_QP = 6; macro IPFINS$V_I25_R1 = 0,6,7,0 %; literal IPFINS$S_I25_R1 = 7; macro IPFINS$V_I25_13_26 = 0,13,14,0 %; literal IPFINS$S_I25_13_26 = 14; macro IPFINS$V_I25_X6 = 0,27,6,0 %; literal IPFINS$S_I25_X6 = 6; macro IPFINS$V_I25_X3 = 4,1,3,0 %; literal IPFINS$S_I25_X3 = 3; macro IPFINS$V_I25_36 = 4,4,1,0 %; macro IPFINS$V_I25_OPCODE = 4,5,4,0 %; literal IPFINS$S_I25_OPCODE = 4; macro IPFINS$Q_I25 = 0,0,0,0 %; literal IPFINS$S_I25 = 8; ! ! I26: Move to AR - Register (I-Unit) ! literal IPFINS$M_I26_QP = %X'3F'; literal IPFINS$M_I26_6_12 = %X'1FC0'; literal IPFINS$M_I26_R2 = %X'FE000'; literal IPFINS$M_I26_AR3 = %X'7F00000'; literal IPFINS$M_I26_X6 = %X'1F8000000'; literal IPFINS$M_I26_X3 = %X'E00000000'; literal IPFINS$M_I26_36 = %X'1000000000'; literal IPFINS$M_I26_OPCODE = %X'1E000000000'; literal IPFINS$M_I26_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I26_FORMAT = 8; macro IPFINS$V_I26_QP = 0,0,6,0 %; literal IPFINS$S_I26_QP = 6; macro IPFINS$V_I26_6_12 = 0,6,7,0 %; literal IPFINS$S_I26_6_12 = 7; macro IPFINS$V_I26_R2 = 0,13,7,0 %; literal IPFINS$S_I26_R2 = 7; macro IPFINS$V_I26_AR3 = 0,20,7,0 %; literal IPFINS$S_I26_AR3 = 7; macro IPFINS$V_I26_X6 = 0,27,6,0 %; literal IPFINS$S_I26_X6 = 6; macro IPFINS$V_I26_X3 = 4,1,3,0 %; literal IPFINS$S_I26_X3 = 3; macro IPFINS$V_I26_36 = 4,4,1,0 %; macro IPFINS$V_I26_OPCODE = 4,5,4,0 %; literal IPFINS$S_I26_OPCODE = 4; macro IPFINS$Q_I26 = 0,0,0,0 %; literal IPFINS$S_I26 = 8; ! ! I27: Move to AR - Immediate(8) (I-Unit) ! literal IPFINS$M_I27_QP = %X'3F'; literal IPFINS$M_I27_6_12 = %X'1FC0'; literal IPFINS$M_I27_IMM7B = %X'FE000'; literal IPFINS$M_I27_AR3 = %X'7F00000'; literal IPFINS$M_I27_X6 = %X'1F8000000'; literal IPFINS$M_I27_X3 = %X'E00000000'; literal IPFINS$M_I27_S = %X'1000000000'; literal IPFINS$M_I27_OPCODE = %X'1E000000000'; literal IPFINS$M_I27_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I27_FORMAT = 8; macro IPFINS$V_I27_QP = 0,0,6,0 %; literal IPFINS$S_I27_QP = 6; macro IPFINS$V_I27_6_12 = 0,6,7,0 %; literal IPFINS$S_I27_6_12 = 7; macro IPFINS$V_I27_IMM7B = 0,13,7,0 %; literal IPFINS$S_I27_IMM7B = 7; macro IPFINS$V_I27_AR3 = 0,20,7,0 %; literal IPFINS$S_I27_AR3 = 7; macro IPFINS$V_I27_X6 = 0,27,6,0 %; literal IPFINS$S_I27_X6 = 6; macro IPFINS$V_I27_X3 = 4,1,3,0 %; literal IPFINS$S_I27_X3 = 3; macro IPFINS$V_I27_S = 4,4,1,1 %; macro IPFINS$V_I27_OPCODE = 4,5,4,0 %; literal IPFINS$S_I27_OPCODE = 4; macro IPFINS$Q_I27 = 0,0,0,0 %; literal IPFINS$S_I27 = 8; ! ! I28: Move from AR (I-Unit) ! literal IPFINS$M_I28_QP = %X'3F'; literal IPFINS$M_I28_R1 = %X'1FC0'; literal IPFINS$M_I28_13_19 = %X'FE000'; literal IPFINS$M_I28_AR3 = %X'7F00000'; literal IPFINS$M_I28_X6 = %X'1F8000000'; literal IPFINS$M_I28_X3 = %X'E00000000'; literal IPFINS$M_I28_36 = %X'1000000000'; literal IPFINS$M_I28_OPCODE = %X'1E000000000'; literal IPFINS$M_I28_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I28_FORMAT = 8; macro IPFINS$V_I28_QP = 0,0,6,0 %; literal IPFINS$S_I28_QP = 6; macro IPFINS$V_I28_R1 = 0,6,7,0 %; literal IPFINS$S_I28_R1 = 7; macro IPFINS$V_I28_13_19 = 0,13,7,0 %; literal IPFINS$S_I28_13_19 = 7; macro IPFINS$V_I28_AR3 = 0,20,7,0 %; literal IPFINS$S_I28_AR3 = 7; macro IPFINS$V_I28_X6 = 0,27,6,0 %; literal IPFINS$S_I28_X6 = 6; macro IPFINS$V_I28_X3 = 4,1,3,0 %; literal IPFINS$S_I28_X3 = 3; macro IPFINS$V_I28_36 = 4,4,1,0 %; macro IPFINS$V_I28_OPCODE = 4,5,4,0 %; literal IPFINS$S_I28_OPCODE = 4; macro IPFINS$Q_I28 = 0,0,0,0 %; literal IPFINS$S_I28 = 8; ! ! I29: Sign/Zero Extend/Compute Zero Index ! literal IPFINS$M_I29_QP = %X'3F'; literal IPFINS$M_I29_R1 = %X'1FC0'; literal IPFINS$M_I29_13_19 = %X'FE000'; literal IPFINS$M_I29_R3 = %X'7F00000'; literal IPFINS$M_I29_X6 = %X'1F8000000'; literal IPFINS$M_I29_X3 = %X'E00000000'; literal IPFINS$M_I29_36 = %X'1000000000'; literal IPFINS$M_I29_OPCODE = %X'1E000000000'; literal IPFINS$M_I29_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I29_FORMAT = 8; macro IPFINS$V_I29_QP = 0,0,6,0 %; literal IPFINS$S_I29_QP = 6; macro IPFINS$V_I29_R1 = 0,6,7,0 %; literal IPFINS$S_I29_R1 = 7; macro IPFINS$V_I29_13_19 = 0,13,7,0 %; literal IPFINS$S_I29_13_19 = 7; macro IPFINS$V_I29_R3 = 0,20,7,0 %; literal IPFINS$S_I29_R3 = 7; macro IPFINS$V_I29_X6 = 0,27,6,0 %; literal IPFINS$S_I29_X6 = 6; macro IPFINS$V_I29_X3 = 4,1,3,0 %; literal IPFINS$S_I29_X3 = 3; macro IPFINS$V_I29_36 = 4,4,1,0 %; macro IPFINS$V_I29_OPCODE = 4,5,4,0 %; literal IPFINS$S_I29_OPCODE = 4; macro IPFINS$Q_I29 = 0,0,0,0 %; literal IPFINS$S_I29 = 8; ! ! I30: Test Feature ! literal IPFINS$M_I30_QP = %X'3F'; literal IPFINS$M_I30_P1 = %X'FC0'; literal IPFINS$M_I30_C = %X'1000'; literal IPFINS$M_I30_Y = %X'2000'; literal IPFINS$M_I30_IMM5B = %X'7C000'; literal IPFINS$M_I30_X = %X'80000'; literal IPFINS$M_I30_ZERO = %X'7F00000'; literal IPFINS$M_I30_P2 = %X'1F8000000'; literal IPFINS$M_I30_TA = %X'200000000'; literal IPFINS$M_I30_X2 = %X'C00000000'; literal IPFINS$M_I30_TB = %X'1000000000'; literal IPFINS$M_I30_OPCODE = %X'1E000000000'; literal IPFINS$M_I30_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_I30_FORMAT = 8; macro IPFINS$V_I30_QP = 0,0,6,0 %; literal IPFINS$S_I30_QP = 6; macro IPFINS$V_I30_P1 = 0,6,6,0 %; literal IPFINS$S_I30_P1 = 6; macro IPFINS$V_I30_C = 0,12,1,0 %; macro IPFINS$V_I30_Y = 0,13,1,0 %; macro IPFINS$V_I30_IMM5B = 0,14,5,0 %; literal IPFINS$S_I30_IMM5B = 5; macro IPFINS$V_I30_X = 0,19,1,0 %; macro IPFINS$V_I30_ZERO = 0,20,7,0 %; literal IPFINS$S_I30_ZERO = 7; macro IPFINS$V_I30_P2 = 0,27,6,0 %; literal IPFINS$S_I30_P2 = 6; macro IPFINS$V_I30_TA = 4,1,1,0 %; macro IPFINS$V_I30_X2 = 4,2,2,0 %; literal IPFINS$S_I30_X2 = 2; macro IPFINS$V_I30_TB = 4,4,1,0 %; macro IPFINS$V_I30_OPCODE = 4,5,4,0 %; literal IPFINS$S_I30_OPCODE = 4; macro IPFINS$Q_I30 = 0,0,0,0 %; literal IPFINS$S_I30 = 8; ! ! M-Unit Formats ! ! ! M1: Integer Load ! literal IPFINS$M_M1_QP = %X'3F'; literal IPFINS$M_M1_R1 = %X'1FC0'; literal IPFINS$M_M1_13_19 = %X'FE000'; literal IPFINS$M_M1_R3 = %X'7F00000'; literal IPFINS$M_M1_X = %X'8000000'; literal IPFINS$M_M1_HINT = %X'30000000'; literal IPFINS$M_M1_X6 = %X'FC0000000'; literal IPFINS$M_M1_M = %X'1000000000'; literal IPFINS$M_M1_OPCODE = %X'1E000000000'; literal IPFINS$M_M1_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M1_FORMAT = 8; macro IPFINS$V_M1_QP = 0,0,6,0 %; literal IPFINS$S_M1_QP = 6; macro IPFINS$V_M1_R1 = 0,6,7,0 %; literal IPFINS$S_M1_R1 = 7; macro IPFINS$V_M1_13_19 = 0,13,7,0 %; literal IPFINS$S_M1_13_19 = 7; macro IPFINS$V_M1_R3 = 0,20,7,0 %; literal IPFINS$S_M1_R3 = 7; macro IPFINS$V_M1_X = 0,27,1,0 %; macro IPFINS$V_M1_HINT = 0,28,2,0 %; literal IPFINS$S_M1_HINT = 2; macro IPFINS$V_M1_X6 = 0,30,6,0 %; literal IPFINS$S_M1_X6 = 6; macro IPFINS$V_M1_M = 4,4,1,0 %; macro IPFINS$V_M1_OPCODE = 4,5,4,0 %; literal IPFINS$S_M1_OPCODE = 4; macro IPFINS$Q_M1 = 0,0,0,0 %; literal IPFINS$S_M1 = 8; ! ! M2: Integer Load - Increment by Register ! literal IPFINS$M_M2_QP = %X'3F'; literal IPFINS$M_M2_R1 = %X'1FC0'; literal IPFINS$M_M2_R2 = %X'FE000'; literal IPFINS$M_M2_R3 = %X'7F00000'; literal IPFINS$M_M2_X = %X'8000000'; literal IPFINS$M_M2_HINT = %X'30000000'; literal IPFINS$M_M2_X6 = %X'FC0000000'; literal IPFINS$M_M2_M = %X'1000000000'; literal IPFINS$M_M2_OPCODE = %X'1E000000000'; literal IPFINS$M_M2_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M2_FORMAT = 8; macro IPFINS$V_M2_QP = 0,0,6,0 %; literal IPFINS$S_M2_QP = 6; macro IPFINS$V_M2_R1 = 0,6,7,0 %; literal IPFINS$S_M2_R1 = 7; macro IPFINS$V_M2_R2 = 0,13,7,0 %; literal IPFINS$S_M2_R2 = 7; macro IPFINS$V_M2_R3 = 0,20,7,0 %; literal IPFINS$S_M2_R3 = 7; macro IPFINS$V_M2_X = 0,27,1,0 %; macro IPFINS$V_M2_HINT = 0,28,2,0 %; literal IPFINS$S_M2_HINT = 2; macro IPFINS$V_M2_X6 = 0,30,6,0 %; literal IPFINS$S_M2_X6 = 6; macro IPFINS$V_M2_M = 4,4,1,0 %; macro IPFINS$V_M2_OPCODE = 4,5,4,0 %; literal IPFINS$S_M2_OPCODE = 4; macro IPFINS$Q_M2 = 0,0,0,0 %; literal IPFINS$S_M2 = 8; ! ! M3: Integer Load - Increment by Immediate ! literal IPFINS$M_M3_QP = %X'3F'; literal IPFINS$M_M3_R1 = %X'1FC0'; literal IPFINS$M_M3_IMM7B = %X'FE000'; literal IPFINS$M_M3_R3 = %X'7F00000'; literal IPFINS$M_M3_I = %X'8000000'; literal IPFINS$M_M3_HINT = %X'30000000'; literal IPFINS$M_M3_X6 = %X'FC0000000'; literal IPFINS$M_M3_S = %X'1000000000'; literal IPFINS$M_M3_OPCODE = %X'1E000000000'; literal IPFINS$M_M3_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M3_FORMAT = 8; macro IPFINS$V_M3_QP = 0,0,6,0 %; literal IPFINS$S_M3_QP = 6; macro IPFINS$V_M3_R1 = 0,6,7,0 %; literal IPFINS$S_M3_R1 = 7; macro IPFINS$V_M3_IMM7B = 0,13,7,0 %; literal IPFINS$S_M3_IMM7B = 7; macro IPFINS$V_M3_R3 = 0,20,7,0 %; literal IPFINS$S_M3_R3 = 7; macro IPFINS$V_M3_I = 0,27,1,0 %; macro IPFINS$V_M3_HINT = 0,28,2,0 %; literal IPFINS$S_M3_HINT = 2; macro IPFINS$V_M3_X6 = 0,30,6,0 %; literal IPFINS$S_M3_X6 = 6; macro IPFINS$V_M3_S = 4,4,1,1 %; macro IPFINS$V_M3_OPCODE = 4,5,4,0 %; literal IPFINS$S_M3_OPCODE = 4; macro IPFINS$Q_M3 = 0,0,0,0 %; literal IPFINS$S_M3 = 8; ! ! M4: Integer Store ! literal IPFINS$M_M4_QP = %X'3F'; literal IPFINS$M_M4_6_12 = %X'1FC0'; literal IPFINS$M_M4_R2 = %X'FE000'; literal IPFINS$M_M4_R3 = %X'7F00000'; literal IPFINS$M_M4_X = %X'8000000'; literal IPFINS$M_M4_HINT = %X'30000000'; literal IPFINS$M_M4_X6 = %X'FC0000000'; literal IPFINS$M_M4_M = %X'1000000000'; literal IPFINS$M_M4_OPCODE = %X'1E000000000'; literal IPFINS$M_M4_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M4_FORMAT = 8; macro IPFINS$V_M4_QP = 0,0,6,0 %; literal IPFINS$S_M4_QP = 6; macro IPFINS$V_M4_6_12 = 0,6,7,0 %; literal IPFINS$S_M4_6_12 = 7; macro IPFINS$V_M4_R2 = 0,13,7,0 %; literal IPFINS$S_M4_R2 = 7; macro IPFINS$V_M4_R3 = 0,20,7,0 %; literal IPFINS$S_M4_R3 = 7; macro IPFINS$V_M4_X = 0,27,1,0 %; macro IPFINS$V_M4_HINT = 0,28,2,0 %; literal IPFINS$S_M4_HINT = 2; macro IPFINS$V_M4_X6 = 0,30,6,0 %; literal IPFINS$S_M4_X6 = 6; macro IPFINS$V_M4_M = 4,4,1,0 %; macro IPFINS$V_M4_OPCODE = 4,5,4,0 %; literal IPFINS$S_M4_OPCODE = 4; macro IPFINS$Q_M4 = 0,0,0,0 %; literal IPFINS$S_M4 = 8; ! ! M5: Integer Store - Increment by Immediate ! literal IPFINS$M_M5_QP = %X'3F'; literal IPFINS$M_M5_IMM7A = %X'1FC0'; literal IPFINS$M_M5_R2 = %X'FE000'; literal IPFINS$M_M5_R3 = %X'7F00000'; literal IPFINS$M_M5_I = %X'8000000'; literal IPFINS$M_M5_HINT = %X'30000000'; literal IPFINS$M_M5_X6 = %X'FC0000000'; literal IPFINS$M_M5_S = %X'1000000000'; literal IPFINS$M_M5_OPCODE = %X'1E000000000'; literal IPFINS$M_M5_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M5_FORMAT = 8; macro IPFINS$V_M5_QP = 0,0,6,0 %; literal IPFINS$S_M5_QP = 6; macro IPFINS$V_M5_IMM7A = 0,6,7,0 %; literal IPFINS$S_M5_IMM7A = 7; macro IPFINS$V_M5_R2 = 0,13,7,0 %; literal IPFINS$S_M5_R2 = 7; macro IPFINS$V_M5_R3 = 0,20,7,0 %; literal IPFINS$S_M5_R3 = 7; macro IPFINS$V_M5_I = 0,27,1,0 %; macro IPFINS$V_M5_HINT = 0,28,2,0 %; literal IPFINS$S_M5_HINT = 2; macro IPFINS$V_M5_X6 = 0,30,6,0 %; literal IPFINS$S_M5_X6 = 6; macro IPFINS$V_M5_S = 4,4,1,1 %; macro IPFINS$V_M5_OPCODE = 4,5,4,0 %; literal IPFINS$S_M5_OPCODE = 4; macro IPFINS$Q_M5 = 0,0,0,0 %; literal IPFINS$S_M5 = 8; ! ! M6: Floating-point Load ! literal IPFINS$M_M6_QP = %X'3F'; literal IPFINS$M_M6_F1 = %X'1FC0'; literal IPFINS$M_M6_13_19 = %X'FE000'; literal IPFINS$M_M6_R3 = %X'7F00000'; literal IPFINS$M_M6_X = %X'8000000'; literal IPFINS$M_M6_HINT = %X'30000000'; literal IPFINS$M_M6_X6 = %X'FC0000000'; literal IPFINS$M_M6_M = %X'1000000000'; literal IPFINS$M_M6_OPCODE = %X'1E000000000'; literal IPFINS$M_M6_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M6_FORMAT = 8; macro IPFINS$V_M6_QP = 0,0,6,0 %; literal IPFINS$S_M6_QP = 6; macro IPFINS$V_M6_F1 = 0,6,7,0 %; literal IPFINS$S_M6_F1 = 7; macro IPFINS$V_M6_13_19 = 0,13,7,0 %; literal IPFINS$S_M6_13_19 = 7; macro IPFINS$V_M6_R3 = 0,20,7,0 %; literal IPFINS$S_M6_R3 = 7; macro IPFINS$V_M6_X = 0,27,1,0 %; macro IPFINS$V_M6_HINT = 0,28,2,0 %; literal IPFINS$S_M6_HINT = 2; macro IPFINS$V_M6_X6 = 0,30,6,0 %; literal IPFINS$S_M6_X6 = 6; macro IPFINS$V_M6_M = 4,4,1,0 %; macro IPFINS$V_M6_OPCODE = 4,5,4,0 %; literal IPFINS$S_M6_OPCODE = 4; macro IPFINS$Q_M6 = 0,0,0,0 %; literal IPFINS$S_M6 = 8; ! ! M7: Floating-point Load - Increment by Register ! literal IPFINS$M_M7_QP = %X'3F'; literal IPFINS$M_M7_F1 = %X'1FC0'; literal IPFINS$M_M7_R2 = %X'FE000'; literal IPFINS$M_M7_R3 = %X'7F00000'; literal IPFINS$M_M7_X = %X'8000000'; literal IPFINS$M_M7_HINT = %X'30000000'; literal IPFINS$M_M7_X6 = %X'FC0000000'; literal IPFINS$M_M7_M = %X'1000000000'; literal IPFINS$M_M7_OPCODE = %X'1E000000000'; literal IPFINS$M_M7_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M7_FORMAT = 8; macro IPFINS$V_M7_QP = 0,0,6,0 %; literal IPFINS$S_M7_QP = 6; macro IPFINS$V_M7_F1 = 0,6,7,0 %; literal IPFINS$S_M7_F1 = 7; macro IPFINS$V_M7_R2 = 0,13,7,0 %; literal IPFINS$S_M7_R2 = 7; macro IPFINS$V_M7_R3 = 0,20,7,0 %; literal IPFINS$S_M7_R3 = 7; macro IPFINS$V_M7_X = 0,27,1,0 %; macro IPFINS$V_M7_HINT = 0,28,2,0 %; literal IPFINS$S_M7_HINT = 2; macro IPFINS$V_M7_X6 = 0,30,6,0 %; literal IPFINS$S_M7_X6 = 6; macro IPFINS$V_M7_M = 4,4,1,0 %; macro IPFINS$V_M7_OPCODE = 4,5,4,0 %; literal IPFINS$S_M7_OPCODE = 4; macro IPFINS$Q_M7 = 0,0,0,0 %; literal IPFINS$S_M7 = 8; ! ! M8: Floating-point Load - Increment by Immediate ! literal IPFINS$M_M8_QP = %X'3F'; literal IPFINS$M_M8_F1 = %X'1FC0'; literal IPFINS$M_M8_IMM7B = %X'FE000'; literal IPFINS$M_M8_R3 = %X'7F00000'; literal IPFINS$M_M8_I = %X'8000000'; literal IPFINS$M_M8_HINT = %X'30000000'; literal IPFINS$M_M8_X6 = %X'FC0000000'; literal IPFINS$M_M8_S = %X'1000000000'; literal IPFINS$M_M8_OPCODE = %X'1E000000000'; literal IPFINS$M_M8_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M8_FORMAT = 8; macro IPFINS$V_M8_QP = 0,0,6,0 %; literal IPFINS$S_M8_QP = 6; macro IPFINS$V_M8_F1 = 0,6,7,0 %; literal IPFINS$S_M8_F1 = 7; macro IPFINS$V_M8_IMM7B = 0,13,7,0 %; literal IPFINS$S_M8_IMM7B = 7; macro IPFINS$V_M8_R3 = 0,20,7,0 %; literal IPFINS$S_M8_R3 = 7; macro IPFINS$V_M8_I = 0,27,1,0 %; macro IPFINS$V_M8_HINT = 0,28,2,0 %; literal IPFINS$S_M8_HINT = 2; macro IPFINS$V_M8_X6 = 0,30,6,0 %; literal IPFINS$S_M8_X6 = 6; macro IPFINS$V_M8_S = 4,4,1,1 %; macro IPFINS$V_M8_OPCODE = 4,5,4,0 %; literal IPFINS$S_M8_OPCODE = 4; macro IPFINS$Q_M8 = 0,0,0,0 %; literal IPFINS$S_M8 = 8; ! ! M9: Floating-point Store ! literal IPFINS$M_M9_QP = %X'3F'; literal IPFINS$M_M9_6_12 = %X'1FC0'; literal IPFINS$M_M9_F2 = %X'FE000'; literal IPFINS$M_M9_R3 = %X'7F00000'; literal IPFINS$M_M9_X = %X'8000000'; literal IPFINS$M_M9_HINT = %X'30000000'; literal IPFINS$M_M9_X6 = %X'FC0000000'; literal IPFINS$M_M9_M = %X'1000000000'; literal IPFINS$M_M9_OPCODE = %X'1E000000000'; literal IPFINS$M_M9_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M9_FORMAT = 8; macro IPFINS$V_M9_QP = 0,0,6,0 %; literal IPFINS$S_M9_QP = 6; macro IPFINS$V_M9_6_12 = 0,6,7,0 %; literal IPFINS$S_M9_6_12 = 7; macro IPFINS$V_M9_F2 = 0,13,7,0 %; literal IPFINS$S_M9_F2 = 7; macro IPFINS$V_M9_R3 = 0,20,7,0 %; literal IPFINS$S_M9_R3 = 7; macro IPFINS$V_M9_X = 0,27,1,0 %; macro IPFINS$V_M9_HINT = 0,28,2,0 %; literal IPFINS$S_M9_HINT = 2; macro IPFINS$V_M9_X6 = 0,30,6,0 %; literal IPFINS$S_M9_X6 = 6; macro IPFINS$V_M9_M = 4,4,1,0 %; macro IPFINS$V_M9_OPCODE = 4,5,4,0 %; literal IPFINS$S_M9_OPCODE = 4; macro IPFINS$Q_M9 = 0,0,0,0 %; literal IPFINS$S_M9 = 8; ! ! M10: Floating-point Store - Increment by Immediate ! literal IPFINS$M_M10_QP = %X'3F'; literal IPFINS$M_M10_IMM7A = %X'1FC0'; literal IPFINS$M_M10_F2 = %X'FE000'; literal IPFINS$M_M10_R3 = %X'7F00000'; literal IPFINS$M_M10_I = %X'8000000'; literal IPFINS$M_M10_HINT = %X'30000000'; literal IPFINS$M_M10_X6 = %X'FC0000000'; literal IPFINS$M_M10_S = %X'1000000000'; literal IPFINS$M_M10_OPCODE = %X'1E000000000'; literal IPFINS$M_M10_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M10_FORMAT = 8; macro IPFINS$V_M10_QP = 0,0,6,0 %; literal IPFINS$S_M10_QP = 6; macro IPFINS$V_M10_IMM7A = 0,6,7,0 %; literal IPFINS$S_M10_IMM7A = 7; macro IPFINS$V_M10_F2 = 0,13,7,0 %; literal IPFINS$S_M10_F2 = 7; macro IPFINS$V_M10_R3 = 0,20,7,0 %; literal IPFINS$S_M10_R3 = 7; macro IPFINS$V_M10_I = 0,27,1,0 %; macro IPFINS$V_M10_HINT = 0,28,2,0 %; literal IPFINS$S_M10_HINT = 2; macro IPFINS$V_M10_X6 = 0,30,6,0 %; literal IPFINS$S_M10_X6 = 6; macro IPFINS$V_M10_S = 4,4,1,1 %; macro IPFINS$V_M10_OPCODE = 4,5,4,0 %; literal IPFINS$S_M10_OPCODE = 4; macro IPFINS$Q_M10 = 0,0,0,0 %; literal IPFINS$S_M10 = 8; ! ! M11: Floating-point Load Pair ! literal IPFINS$M_M11_QP = %X'3F'; literal IPFINS$M_M11_F1 = %X'1FC0'; literal IPFINS$M_M11_F2 = %X'FE000'; literal IPFINS$M_M11_R3 = %X'7F00000'; literal IPFINS$M_M11_X = %X'8000000'; literal IPFINS$M_M11_HINT = %X'30000000'; literal IPFINS$M_M11_X6 = %X'FC0000000'; literal IPFINS$M_M11_M = %X'1000000000'; literal IPFINS$M_M11_OPCODE = %X'1E000000000'; literal IPFINS$M_M11_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M11_FORMAT = 8; macro IPFINS$V_M11_QP = 0,0,6,0 %; literal IPFINS$S_M11_QP = 6; macro IPFINS$V_M11_F1 = 0,6,7,0 %; literal IPFINS$S_M11_F1 = 7; macro IPFINS$V_M11_F2 = 0,13,7,0 %; literal IPFINS$S_M11_F2 = 7; macro IPFINS$V_M11_R3 = 0,20,7,0 %; literal IPFINS$S_M11_R3 = 7; macro IPFINS$V_M11_X = 0,27,1,0 %; macro IPFINS$V_M11_HINT = 0,28,2,0 %; literal IPFINS$S_M11_HINT = 2; macro IPFINS$V_M11_X6 = 0,30,6,0 %; literal IPFINS$S_M11_X6 = 6; macro IPFINS$V_M11_M = 4,4,1,0 %; macro IPFINS$V_M11_OPCODE = 4,5,4,0 %; literal IPFINS$S_M11_OPCODE = 4; macro IPFINS$Q_M11 = 0,0,0,0 %; literal IPFINS$S_M11 = 8; ! ! M12: Floating-point Load Pair - Increment by Immediate ! literal IPFINS$M_M12_QP = %X'3F'; literal IPFINS$M_M12_F1 = %X'1FC0'; literal IPFINS$M_M12_F2 = %X'FE000'; literal IPFINS$M_M12_R3 = %X'7F00000'; literal IPFINS$M_M12_X = %X'8000000'; literal IPFINS$M_M12_HINT = %X'30000000'; literal IPFINS$M_M12_X6 = %X'FC0000000'; literal IPFINS$M_M12_M = %X'1000000000'; literal IPFINS$M_M12_OPCODE = %X'1E000000000'; literal IPFINS$M_M12_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M12_FORMAT = 8; macro IPFINS$V_M12_QP = 0,0,6,0 %; literal IPFINS$S_M12_QP = 6; macro IPFINS$V_M12_F1 = 0,6,7,0 %; literal IPFINS$S_M12_F1 = 7; macro IPFINS$V_M12_F2 = 0,13,7,0 %; literal IPFINS$S_M12_F2 = 7; macro IPFINS$V_M12_R3 = 0,20,7,0 %; literal IPFINS$S_M12_R3 = 7; macro IPFINS$V_M12_X = 0,27,1,0 %; macro IPFINS$V_M12_HINT = 0,28,2,0 %; literal IPFINS$S_M12_HINT = 2; macro IPFINS$V_M12_X6 = 0,30,6,0 %; literal IPFINS$S_M12_X6 = 6; macro IPFINS$V_M12_M = 4,4,1,0 %; macro IPFINS$V_M12_OPCODE = 4,5,4,0 %; literal IPFINS$S_M12_OPCODE = 4; macro IPFINS$Q_M12 = 0,0,0,0 %; literal IPFINS$S_M12 = 8; ! ! M13: Line Prefetch ! literal IPFINS$M_M13_QP = %X'3F'; literal IPFINS$M_M13_6_19 = %X'FFFC0'; literal IPFINS$M_M13_R3 = %X'7F00000'; literal IPFINS$M_M13_X = %X'8000000'; literal IPFINS$M_M13_HINT = %X'30000000'; literal IPFINS$M_M13_X6 = %X'FC0000000'; literal IPFINS$M_M13_M = %X'1000000000'; literal IPFINS$M_M13_OPCODE = %X'1E000000000'; literal IPFINS$M_M13_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M13_FORMAT = 8; macro IPFINS$V_M13_QP = 0,0,6,0 %; literal IPFINS$S_M13_QP = 6; macro IPFINS$V_M13_6_19 = 0,6,14,0 %; literal IPFINS$S_M13_6_19 = 14; macro IPFINS$V_M13_R3 = 0,20,7,0 %; literal IPFINS$S_M13_R3 = 7; macro IPFINS$V_M13_X = 0,27,1,0 %; macro IPFINS$V_M13_HINT = 0,28,2,0 %; literal IPFINS$S_M13_HINT = 2; macro IPFINS$V_M13_X6 = 0,30,6,0 %; literal IPFINS$S_M13_X6 = 6; macro IPFINS$V_M13_M = 4,4,1,0 %; macro IPFINS$V_M13_OPCODE = 4,5,4,0 %; literal IPFINS$S_M13_OPCODE = 4; macro IPFINS$Q_M13 = 0,0,0,0 %; literal IPFINS$S_M13 = 8; ! ! M14: Line Prefetch - Increment by Register ! literal IPFINS$M_M14_QP = %X'3F'; literal IPFINS$M_M14_6_12 = %X'1FC0'; literal IPFINS$M_M14_R2 = %X'FE000'; literal IPFINS$M_M14_R3 = %X'7F00000'; literal IPFINS$M_M14_X = %X'8000000'; literal IPFINS$M_M14_HINT = %X'30000000'; literal IPFINS$M_M14_X6 = %X'FC0000000'; literal IPFINS$M_M14_M = %X'1000000000'; literal IPFINS$M_M14_OPCODE = %X'1E000000000'; literal IPFINS$M_M14_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M14_FORMAT = 8; macro IPFINS$V_M14_QP = 0,0,6,0 %; literal IPFINS$S_M14_QP = 6; macro IPFINS$V_M14_6_12 = 0,6,7,0 %; literal IPFINS$S_M14_6_12 = 7; macro IPFINS$V_M14_R2 = 0,13,7,0 %; literal IPFINS$S_M14_R2 = 7; macro IPFINS$V_M14_R3 = 0,20,7,0 %; literal IPFINS$S_M14_R3 = 7; macro IPFINS$V_M14_X = 0,27,1,0 %; macro IPFINS$V_M14_HINT = 0,28,2,0 %; literal IPFINS$S_M14_HINT = 2; macro IPFINS$V_M14_X6 = 0,30,6,0 %; literal IPFINS$S_M14_X6 = 6; macro IPFINS$V_M14_M = 4,4,1,0 %; macro IPFINS$V_M14_OPCODE = 4,5,4,0 %; literal IPFINS$S_M14_OPCODE = 4; macro IPFINS$Q_M14 = 0,0,0,0 %; literal IPFINS$S_M14 = 8; ! ! M15: Line Prefetch - Increment by Immediate ! literal IPFINS$M_M15_QP = %X'3F'; literal IPFINS$M_M15_6_12 = %X'1FC0'; literal IPFINS$M_M15_IMM7B = %X'FE000'; literal IPFINS$M_M15_R3 = %X'7F00000'; literal IPFINS$M_M15_I = %X'8000000'; literal IPFINS$M_M15_HINT = %X'30000000'; literal IPFINS$M_M15_X6 = %X'FC0000000'; literal IPFINS$M_M15_S = %X'1000000000'; literal IPFINS$M_M15_OPCODE = %X'1E000000000'; literal IPFINS$M_M15_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M15_FORMAT = 8; macro IPFINS$V_M15_QP = 0,0,6,0 %; literal IPFINS$S_M15_QP = 6; macro IPFINS$V_M15_6_12 = 0,6,7,0 %; literal IPFINS$S_M15_6_12 = 7; macro IPFINS$V_M15_IMM7B = 0,13,7,0 %; literal IPFINS$S_M15_IMM7B = 7; macro IPFINS$V_M15_R3 = 0,20,7,0 %; literal IPFINS$S_M15_R3 = 7; macro IPFINS$V_M15_I = 0,27,1,0 %; macro IPFINS$V_M15_HINT = 0,28,2,0 %; literal IPFINS$S_M15_HINT = 2; macro IPFINS$V_M15_X6 = 0,30,6,0 %; literal IPFINS$S_M15_X6 = 6; macro IPFINS$V_M15_S = 4,4,1,1 %; macro IPFINS$V_M15_OPCODE = 4,5,4,0 %; literal IPFINS$S_M15_OPCODE = 4; macro IPFINS$Q_M15 = 0,0,0,0 %; literal IPFINS$S_M15 = 8; ! ! M16: Exchange/Compare and Exchange ! literal IPFINS$M_M16_QP = %X'3F'; literal IPFINS$M_M16_R1 = %X'1FC0'; literal IPFINS$M_M16_R2 = %X'FE000'; literal IPFINS$M_M16_R3 = %X'7F00000'; literal IPFINS$M_M16_X = %X'8000000'; literal IPFINS$M_M16_HINT = %X'30000000'; literal IPFINS$M_M16_X6 = %X'FC0000000'; literal IPFINS$M_M16_M = %X'1000000000'; literal IPFINS$M_M16_OPCODE = %X'1E000000000'; literal IPFINS$M_M16_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M16_FORMAT = 8; macro IPFINS$V_M16_QP = 0,0,6,0 %; literal IPFINS$S_M16_QP = 6; macro IPFINS$V_M16_R1 = 0,6,7,0 %; literal IPFINS$S_M16_R1 = 7; macro IPFINS$V_M16_R2 = 0,13,7,0 %; literal IPFINS$S_M16_R2 = 7; macro IPFINS$V_M16_R3 = 0,20,7,0 %; literal IPFINS$S_M16_R3 = 7; macro IPFINS$V_M16_X = 0,27,1,0 %; macro IPFINS$V_M16_HINT = 0,28,2,0 %; literal IPFINS$S_M16_HINT = 2; macro IPFINS$V_M16_X6 = 0,30,6,0 %; literal IPFINS$S_M16_X6 = 6; macro IPFINS$V_M16_M = 4,4,1,0 %; macro IPFINS$V_M16_OPCODE = 4,5,4,0 %; literal IPFINS$S_M16_OPCODE = 4; macro IPFINS$Q_M16 = 0,0,0,0 %; literal IPFINS$S_M16 = 8; ! ! M17: Fetch and Add - Immediate ! literal IPFINS$M_M17_QP = %X'3F'; literal IPFINS$M_M17_R1 = %X'1FC0'; literal IPFINS$M_M17_I2B = %X'6000'; literal IPFINS$M_M17_S = %X'8000'; literal IPFINS$M_M17_16_19 = %X'F0000'; literal IPFINS$M_M17_R3 = %X'7F00000'; literal IPFINS$M_M17_X = %X'8000000'; literal IPFINS$M_M17_HINT = %X'30000000'; literal IPFINS$M_M17_X6 = %X'FC0000000'; literal IPFINS$M_M17_M = %X'1000000000'; literal IPFINS$M_M17_OPCODE = %X'1E000000000'; literal IPFINS$M_M17_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M17_FORMAT = 8; macro IPFINS$V_M17_QP = 0,0,6,0 %; literal IPFINS$S_M17_QP = 6; macro IPFINS$V_M17_R1 = 0,6,7,0 %; literal IPFINS$S_M17_R1 = 7; macro IPFINS$V_M17_I2B = 0,13,2,0 %; literal IPFINS$S_M17_I2B = 2; macro IPFINS$V_M17_S = 0,15,1,1 %; macro IPFINS$V_M17_16_19 = 0,16,4,0 %; literal IPFINS$S_M17_16_19 = 4; macro IPFINS$V_M17_R3 = 0,20,7,0 %; literal IPFINS$S_M17_R3 = 7; macro IPFINS$V_M17_X = 0,27,1,0 %; macro IPFINS$V_M17_HINT = 0,28,2,0 %; literal IPFINS$S_M17_HINT = 2; macro IPFINS$V_M17_X6 = 0,30,6,0 %; literal IPFINS$S_M17_X6 = 6; macro IPFINS$V_M17_M = 4,4,1,0 %; macro IPFINS$V_M17_OPCODE = 4,5,4,0 %; literal IPFINS$S_M17_OPCODE = 4; macro IPFINS$Q_M17 = 0,0,0,0 %; literal IPFINS$S_M17 = 8; ! ! M18: Set FR ! literal IPFINS$M_M18_QP = %X'3F'; literal IPFINS$M_M18_F1 = %X'1FC0'; literal IPFINS$M_M18_R2 = %X'FE000'; literal IPFINS$M_M18_20_26 = %X'7F00000'; literal IPFINS$M_M18_X = %X'8000000'; literal IPFINS$M_M18_28_29 = %X'30000000'; literal IPFINS$M_M18_X6 = %X'FC0000000'; literal IPFINS$M_M18_M = %X'1000000000'; literal IPFINS$M_M18_OPCODE = %X'1E000000000'; literal IPFINS$M_M18_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M18_FORMAT = 8; macro IPFINS$V_M18_QP = 0,0,6,0 %; literal IPFINS$S_M18_QP = 6; macro IPFINS$V_M18_F1 = 0,6,7,0 %; literal IPFINS$S_M18_F1 = 7; macro IPFINS$V_M18_R2 = 0,13,7,0 %; literal IPFINS$S_M18_R2 = 7; macro IPFINS$V_M18_20_26 = 0,20,7,0 %; literal IPFINS$S_M18_20_26 = 7; macro IPFINS$V_M18_X = 0,27,1,0 %; macro IPFINS$V_M18_28_29 = 0,28,2,0 %; literal IPFINS$S_M18_28_29 = 2; macro IPFINS$V_M18_X6 = 0,30,6,0 %; literal IPFINS$S_M18_X6 = 6; macro IPFINS$V_M18_M = 4,4,1,0 %; macro IPFINS$V_M18_OPCODE = 4,5,4,0 %; literal IPFINS$S_M18_OPCODE = 4; macro IPFINS$Q_M18 = 0,0,0,0 %; literal IPFINS$S_M18 = 8; ! ! M19: Get FR ! literal IPFINS$M_M19_QP = %X'3F'; literal IPFINS$M_M19_R1 = %X'1FC0'; literal IPFINS$M_M19_F2 = %X'FE000'; literal IPFINS$M_M19_20_26 = %X'7F00000'; literal IPFINS$M_M19_X = %X'8000000'; literal IPFINS$M_M19_28_29 = %X'30000000'; literal IPFINS$M_M19_X6 = %X'FC0000000'; literal IPFINS$M_M19_M = %X'1000000000'; literal IPFINS$M_M19_OPCODE = %X'1E000000000'; literal IPFINS$M_M19_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M19_FORMAT = 8; macro IPFINS$V_M19_QP = 0,0,6,0 %; literal IPFINS$S_M19_QP = 6; macro IPFINS$V_M19_R1 = 0,6,7,0 %; literal IPFINS$S_M19_R1 = 7; macro IPFINS$V_M19_F2 = 0,13,7,0 %; literal IPFINS$S_M19_F2 = 7; macro IPFINS$V_M19_20_26 = 0,20,7,0 %; literal IPFINS$S_M19_20_26 = 7; macro IPFINS$V_M19_X = 0,27,1,0 %; macro IPFINS$V_M19_28_29 = 0,28,2,0 %; literal IPFINS$S_M19_28_29 = 2; macro IPFINS$V_M19_X6 = 0,30,6,0 %; literal IPFINS$S_M19_X6 = 6; macro IPFINS$V_M19_M = 4,4,1,0 %; macro IPFINS$V_M19_OPCODE = 4,5,4,0 %; literal IPFINS$S_M19_OPCODE = 4; macro IPFINS$Q_M19 = 0,0,0,0 %; literal IPFINS$S_M19 = 8; ! ! M20: Integer Speculation Check (M-Unit) ! literal IPFINS$M_M20_QP = %X'3F'; literal IPFINS$M_M20_IMM7A = %X'1FC0'; literal IPFINS$M_M20_R2 = %X'FE000'; literal IPFINS$M_M20_IMM13C = %X'1FFF00000'; literal IPFINS$M_M20_X3 = %X'E00000000'; literal IPFINS$M_M20_S = %X'1000000000'; literal IPFINS$M_M20_OPCODE = %X'1E000000000'; literal IPFINS$M_M20_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M20_FORMAT = 8; macro IPFINS$V_M20_QP = 0,0,6,0 %; literal IPFINS$S_M20_QP = 6; macro IPFINS$V_M20_IMM7A = 0,6,7,0 %; literal IPFINS$S_M20_IMM7A = 7; macro IPFINS$V_M20_R2 = 0,13,7,0 %; literal IPFINS$S_M20_R2 = 7; macro IPFINS$V_M20_IMM13C = 0,20,13,0 %; literal IPFINS$S_M20_IMM13C = 13; macro IPFINS$V_M20_X3 = 4,1,3,0 %; literal IPFINS$S_M20_X3 = 3; macro IPFINS$V_M20_S = 4,4,1,1 %; macro IPFINS$V_M20_OPCODE = 4,5,4,0 %; literal IPFINS$S_M20_OPCODE = 4; macro IPFINS$Q_M20 = 0,0,0,0 %; literal IPFINS$S_M20 = 8; ! ! M21: Floating-point Speculation Check ! literal IPFINS$M_M21_QP = %X'3F'; literal IPFINS$M_M21_IMM7A = %X'1FC0'; literal IPFINS$M_M21_F2 = %X'FE000'; literal IPFINS$M_M21_IMM13C = %X'1FFF00000'; literal IPFINS$M_M21_X3 = %X'E00000000'; literal IPFINS$M_M21_S = %X'1000000000'; literal IPFINS$M_M21_OPCODE = %X'1E000000000'; literal IPFINS$M_M21_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M21_FORMAT = 8; macro IPFINS$V_M21_QP = 0,0,6,0 %; literal IPFINS$S_M21_QP = 6; macro IPFINS$V_M21_IMM7A = 0,6,7,0 %; literal IPFINS$S_M21_IMM7A = 7; macro IPFINS$V_M21_F2 = 0,13,7,0 %; literal IPFINS$S_M21_F2 = 7; macro IPFINS$V_M21_IMM13C = 0,20,13,0 %; literal IPFINS$S_M21_IMM13C = 13; macro IPFINS$V_M21_X3 = 4,1,3,0 %; literal IPFINS$S_M21_X3 = 3; macro IPFINS$V_M21_S = 4,4,1,1 %; macro IPFINS$V_M21_OPCODE = 4,5,4,0 %; literal IPFINS$S_M21_OPCODE = 4; macro IPFINS$Q_M21 = 0,0,0,0 %; literal IPFINS$S_M21 = 8; ! ! M22: Integer Advanced Load Check ! literal IPFINS$M_M22_QP = %X'3F'; literal IPFINS$M_M22_R1 = %X'1FC0'; literal IPFINS$M_M22_IMM20B = %X'1FFFFE000'; literal IPFINS$M_M22_X3 = %X'E00000000'; literal IPFINS$M_M22_S = %X'1000000000'; literal IPFINS$M_M22_OPCODE = %X'1E000000000'; literal IPFINS$M_M22_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M22_FORMAT = 8; macro IPFINS$V_M22_QP = 0,0,6,0 %; literal IPFINS$S_M22_QP = 6; macro IPFINS$V_M22_R1 = 0,6,7,0 %; literal IPFINS$S_M22_R1 = 7; macro IPFINS$V_M22_IMM20B = 0,13,20,0 %; literal IPFINS$S_M22_IMM20B = 20; macro IPFINS$V_M22_X3 = 4,1,3,0 %; literal IPFINS$S_M22_X3 = 3; macro IPFINS$V_M22_S = 4,4,1,1 %; macro IPFINS$V_M22_OPCODE = 4,5,4,0 %; literal IPFINS$S_M22_OPCODE = 4; macro IPFINS$Q_M22 = 0,0,0,0 %; literal IPFINS$S_M22 = 8; ! ! M23: Floating-point Advanced Load Check ! literal IPFINS$M_M23_QP = %X'3F'; literal IPFINS$M_M23_F1 = %X'1FC0'; literal IPFINS$M_M23_IMM20B = %X'1FFFFE000'; literal IPFINS$M_M23_X3 = %X'E00000000'; literal IPFINS$M_M23_S = %X'1000000000'; literal IPFINS$M_M23_OPCODE = %X'1E000000000'; literal IPFINS$M_M23_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M23_FORMAT = 8; macro IPFINS$V_M23_QP = 0,0,6,0 %; literal IPFINS$S_M23_QP = 6; macro IPFINS$V_M23_F1 = 0,6,7,0 %; literal IPFINS$S_M23_F1 = 7; macro IPFINS$V_M23_IMM20B = 0,13,20,0 %; literal IPFINS$S_M23_IMM20B = 20; macro IPFINS$V_M23_X3 = 4,1,3,0 %; literal IPFINS$S_M23_X3 = 3; macro IPFINS$V_M23_S = 4,4,1,1 %; macro IPFINS$V_M23_OPCODE = 4,5,4,0 %; literal IPFINS$S_M23_OPCODE = 4; macro IPFINS$Q_M23 = 0,0,0,0 %; literal IPFINS$S_M23 = 8; ! ! M24: Sync/Fence/Serialize/ALAT Control ! literal IPFINS$M_M24_QP = %X'3F'; literal IPFINS$M_M24_6_26 = %X'7FFFFC0'; literal IPFINS$M_M24_X4 = %X'78000000'; literal IPFINS$M_M24_X2 = %X'180000000'; literal IPFINS$M_M24_X3 = %X'E00000000'; literal IPFINS$M_M24_36 = %X'1000000000'; literal IPFINS$M_M24_OPCODE = %X'1E000000000'; literal IPFINS$M_M24_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M24_FORMAT = 8; macro IPFINS$V_M24_QP = 0,0,6,0 %; literal IPFINS$S_M24_QP = 6; macro IPFINS$V_M24_6_26 = 0,6,21,0 %; literal IPFINS$S_M24_6_26 = 21; macro IPFINS$V_M24_X4 = 0,27,4,0 %; literal IPFINS$S_M24_X4 = 4; macro IPFINS$V_M24_X2 = 0,31,2,0 %; literal IPFINS$S_M24_X2 = 2; macro IPFINS$V_M24_X3 = 4,1,3,0 %; literal IPFINS$S_M24_X3 = 3; macro IPFINS$V_M24_36 = 4,4,1,0 %; macro IPFINS$V_M24_OPCODE = 4,5,4,0 %; literal IPFINS$S_M24_OPCODE = 4; macro IPFINS$Q_M24 = 0,0,0,0 %; literal IPFINS$S_M24 = 8; ! ! M25: RSE Control ! literal IPFINS$M_M25_ZERO = %X'3F'; literal IPFINS$M_M25_6_26 = %X'7FFFFC0'; literal IPFINS$M_M25_X4 = %X'78000000'; literal IPFINS$M_M25_X2 = %X'180000000'; literal IPFINS$M_M25_X3 = %X'E00000000'; literal IPFINS$M_M25_36 = %X'1000000000'; literal IPFINS$M_M25_OPCODE = %X'1E000000000'; literal IPFINS$M_M25_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M25_FORMAT = 8; macro IPFINS$V_M25_ZERO = 0,0,6,0 %; literal IPFINS$S_M25_ZERO = 6; macro IPFINS$V_M25_6_26 = 0,6,21,0 %; literal IPFINS$S_M25_6_26 = 21; macro IPFINS$V_M25_X4 = 0,27,4,0 %; literal IPFINS$S_M25_X4 = 4; macro IPFINS$V_M25_X2 = 0,31,2,0 %; literal IPFINS$S_M25_X2 = 2; macro IPFINS$V_M25_X3 = 4,1,3,0 %; literal IPFINS$S_M25_X3 = 3; macro IPFINS$V_M25_36 = 4,4,1,0 %; macro IPFINS$V_M25_OPCODE = 4,5,4,0 %; literal IPFINS$S_M25_OPCODE = 4; macro IPFINS$Q_M25 = 0,0,0,0 %; literal IPFINS$S_M25 = 8; ! ! M26: Integer ALAT Entry Invalidate ! literal IPFINS$M_M26_QP = %X'3F'; literal IPFINS$M_M26_R1 = %X'1FC0'; literal IPFINS$M_M26_13_26 = %X'7FFE000'; literal IPFINS$M_M26_X4 = %X'78000000'; literal IPFINS$M_M26_X2 = %X'180000000'; literal IPFINS$M_M26_X3 = %X'E00000000'; literal IPFINS$M_M26_36 = %X'1000000000'; literal IPFINS$M_M26_OPCODE = %X'1E000000000'; literal IPFINS$M_M26_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M26_FORMAT = 8; macro IPFINS$V_M26_QP = 0,0,6,0 %; literal IPFINS$S_M26_QP = 6; macro IPFINS$V_M26_R1 = 0,6,7,0 %; literal IPFINS$S_M26_R1 = 7; macro IPFINS$V_M26_13_26 = 0,13,14,0 %; literal IPFINS$S_M26_13_26 = 14; macro IPFINS$V_M26_X4 = 0,27,4,0 %; literal IPFINS$S_M26_X4 = 4; macro IPFINS$V_M26_X2 = 0,31,2,0 %; literal IPFINS$S_M26_X2 = 2; macro IPFINS$V_M26_X3 = 4,1,3,0 %; literal IPFINS$S_M26_X3 = 3; macro IPFINS$V_M26_36 = 4,4,1,0 %; macro IPFINS$V_M26_OPCODE = 4,5,4,0 %; literal IPFINS$S_M26_OPCODE = 4; macro IPFINS$Q_M26 = 0,0,0,0 %; literal IPFINS$S_M26 = 8; ! ! M27: Floating-point ALAT Entry Invalidate ! literal IPFINS$M_M27_QP = %X'3F'; literal IPFINS$M_M27_F1 = %X'1FC0'; literal IPFINS$M_M27_13_26 = %X'7FFE000'; literal IPFINS$M_M27_X4 = %X'78000000'; literal IPFINS$M_M27_X2 = %X'180000000'; literal IPFINS$M_M27_X3 = %X'E00000000'; literal IPFINS$M_M27_36 = %X'1000000000'; literal IPFINS$M_M27_OPCODE = %X'1E000000000'; literal IPFINS$M_M27_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M27_FORMAT = 8; macro IPFINS$V_M27_QP = 0,0,6,0 %; literal IPFINS$S_M27_QP = 6; macro IPFINS$V_M27_F1 = 0,6,7,0 %; literal IPFINS$S_M27_F1 = 7; macro IPFINS$V_M27_13_26 = 0,13,14,0 %; literal IPFINS$S_M27_13_26 = 14; macro IPFINS$V_M27_X4 = 0,27,4,0 %; literal IPFINS$S_M27_X4 = 4; macro IPFINS$V_M27_X2 = 0,31,2,0 %; literal IPFINS$S_M27_X2 = 2; macro IPFINS$V_M27_X3 = 4,1,3,0 %; literal IPFINS$S_M27_X3 = 3; macro IPFINS$V_M27_36 = 4,4,1,0 %; macro IPFINS$V_M27_OPCODE = 4,5,4,0 %; literal IPFINS$S_M27_OPCODE = 4; macro IPFINS$Q_M27 = 0,0,0,0 %; literal IPFINS$S_M27 = 8; ! ! M28: Flush Cache ! literal IPFINS$M_M28_QP = %X'3F'; literal IPFINS$M_M28_6_19 = %X'FFFC0'; literal IPFINS$M_M28_R3 = %X'7F00000'; literal IPFINS$M_M28_X6 = %X'1F8000000'; literal IPFINS$M_M28_X3 = %X'E00000000'; literal IPFINS$M_M28_X = %X'1000000000'; literal IPFINS$M_M28_OPCODE = %X'1E000000000'; literal IPFINS$M_M28_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M28_FORMAT = 8; macro IPFINS$V_M28_QP = 0,0,6,0 %; literal IPFINS$S_M28_QP = 6; macro IPFINS$V_M28_6_19 = 0,6,14,0 %; literal IPFINS$S_M28_6_19 = 14; macro IPFINS$V_M28_R3 = 0,20,7,0 %; literal IPFINS$S_M28_R3 = 7; macro IPFINS$V_M28_X6 = 0,27,6,0 %; literal IPFINS$S_M28_X6 = 6; macro IPFINS$V_M28_X3 = 4,1,3,0 %; literal IPFINS$S_M28_X3 = 3; macro IPFINS$V_M28_X = 4,4,1,0 %; macro IPFINS$V_M28_OPCODE = 4,5,4,0 %; literal IPFINS$S_M28_OPCODE = 4; macro IPFINS$Q_M28 = 0,0,0,0 %; literal IPFINS$S_M28 = 8; ! ! M29: Move to AR - Register (M-Unit) ! literal IPFINS$M_M29_QP = %X'3F'; literal IPFINS$M_M29_6_12 = %X'1FC0'; literal IPFINS$M_M29_R2 = %X'FE000'; literal IPFINS$M_M29_AR3 = %X'7F00000'; literal IPFINS$M_M29_X6 = %X'1F8000000'; literal IPFINS$M_M29_X3 = %X'E00000000'; literal IPFINS$M_M29_36 = %X'1000000000'; literal IPFINS$M_M29_OPCODE = %X'1E000000000'; literal IPFINS$M_M29_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M29_FORMAT = 8; macro IPFINS$V_M29_QP = 0,0,6,0 %; literal IPFINS$S_M29_QP = 6; macro IPFINS$V_M29_6_12 = 0,6,7,0 %; literal IPFINS$S_M29_6_12 = 7; macro IPFINS$V_M29_R2 = 0,13,7,0 %; literal IPFINS$S_M29_R2 = 7; macro IPFINS$V_M29_AR3 = 0,20,7,0 %; literal IPFINS$S_M29_AR3 = 7; macro IPFINS$V_M29_X6 = 0,27,6,0 %; literal IPFINS$S_M29_X6 = 6; macro IPFINS$V_M29_X3 = 4,1,3,0 %; literal IPFINS$S_M29_X3 = 3; macro IPFINS$V_M29_36 = 4,4,1,0 %; macro IPFINS$V_M29_OPCODE = 4,5,4,0 %; literal IPFINS$S_M29_OPCODE = 4; macro IPFINS$Q_M29 = 0,0,0,0 %; literal IPFINS$S_M29 = 8; ! ! M30: Move to AR - Immediate(8) (M-Unit) ! literal IPFINS$M_M30_QP = %X'3F'; literal IPFINS$M_M30_6_12 = %X'1FC0'; literal IPFINS$M_M30_IMM7B = %X'FE000'; literal IPFINS$M_M30_AR3 = %X'7F00000'; literal IPFINS$M_M30_X4 = %X'78000000'; literal IPFINS$M_M30_X2 = %X'180000000'; literal IPFINS$M_M30_X3 = %X'E00000000'; literal IPFINS$M_M30_S = %X'1000000000'; literal IPFINS$M_M30_OPCODE = %X'1E000000000'; literal IPFINS$M_M30_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M30_FORMAT = 8; macro IPFINS$V_M30_QP = 0,0,6,0 %; literal IPFINS$S_M30_QP = 6; macro IPFINS$V_M30_6_12 = 0,6,7,0 %; literal IPFINS$S_M30_6_12 = 7; macro IPFINS$V_M30_IMM7B = 0,13,7,0 %; literal IPFINS$S_M30_IMM7B = 7; macro IPFINS$V_M30_AR3 = 0,20,7,0 %; literal IPFINS$S_M30_AR3 = 7; macro IPFINS$V_M30_X4 = 0,27,4,0 %; literal IPFINS$S_M30_X4 = 4; macro IPFINS$V_M30_X2 = 0,31,2,0 %; literal IPFINS$S_M30_X2 = 2; macro IPFINS$V_M30_X3 = 4,1,3,0 %; literal IPFINS$S_M30_X3 = 3; macro IPFINS$V_M30_S = 4,4,1,1 %; macro IPFINS$V_M30_OPCODE = 4,5,4,0 %; literal IPFINS$S_M30_OPCODE = 4; macro IPFINS$Q_M30 = 0,0,0,0 %; literal IPFINS$S_M30 = 8; ! ! M31: Move from AR (M-Unit) ! literal IPFINS$M_M31_QP = %X'3F'; literal IPFINS$M_M31_R1 = %X'1FC0'; literal IPFINS$M_M31_13_19 = %X'FE000'; literal IPFINS$M_M31_AR3 = %X'7F00000'; literal IPFINS$M_M31_X6 = %X'1F8000000'; literal IPFINS$M_M31_X3 = %X'E00000000'; literal IPFINS$M_M31_36 = %X'1000000000'; literal IPFINS$M_M31_OPCODE = %X'1E000000000'; literal IPFINS$M_M31_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M31_FORMAT = 8; macro IPFINS$V_M31_QP = 0,0,6,0 %; literal IPFINS$S_M31_QP = 6; macro IPFINS$V_M31_R1 = 0,6,7,0 %; literal IPFINS$S_M31_R1 = 7; macro IPFINS$V_M31_13_19 = 0,13,7,0 %; literal IPFINS$S_M31_13_19 = 7; macro IPFINS$V_M31_AR3 = 0,20,7,0 %; literal IPFINS$S_M31_AR3 = 7; macro IPFINS$V_M31_X6 = 0,27,6,0 %; literal IPFINS$S_M31_X6 = 6; macro IPFINS$V_M31_X3 = 4,1,3,0 %; literal IPFINS$S_M31_X3 = 3; macro IPFINS$V_M31_36 = 4,4,1,0 %; macro IPFINS$V_M31_OPCODE = 4,5,4,0 %; literal IPFINS$S_M31_OPCODE = 4; macro IPFINS$Q_M31 = 0,0,0,0 %; literal IPFINS$S_M31 = 8; ! ! M32: Move to CR ! literal IPFINS$M_M32_QP = %X'3F'; literal IPFINS$M_M32_6_12 = %X'1FC0'; literal IPFINS$M_M32_R2 = %X'FE000'; literal IPFINS$M_M32_CR3 = %X'7F00000'; literal IPFINS$M_M32_X6 = %X'1F8000000'; literal IPFINS$M_M32_X3 = %X'E00000000'; literal IPFINS$M_M32_36 = %X'1000000000'; literal IPFINS$M_M32_OPCODE = %X'1E000000000'; literal IPFINS$M_M32_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M32_FORMAT = 8; macro IPFINS$V_M32_QP = 0,0,6,0 %; literal IPFINS$S_M32_QP = 6; macro IPFINS$V_M32_6_12 = 0,6,7,0 %; literal IPFINS$S_M32_6_12 = 7; macro IPFINS$V_M32_R2 = 0,13,7,0 %; literal IPFINS$S_M32_R2 = 7; macro IPFINS$V_M32_CR3 = 0,20,7,0 %; literal IPFINS$S_M32_CR3 = 7; macro IPFINS$V_M32_X6 = 0,27,6,0 %; literal IPFINS$S_M32_X6 = 6; macro IPFINS$V_M32_X3 = 4,1,3,0 %; literal IPFINS$S_M32_X3 = 3; macro IPFINS$V_M32_36 = 4,4,1,0 %; macro IPFINS$V_M32_OPCODE = 4,5,4,0 %; literal IPFINS$S_M32_OPCODE = 4; macro IPFINS$Q_M32 = 0,0,0,0 %; literal IPFINS$S_M32 = 8; ! ! M33: Move from CR ! literal IPFINS$M_M33_QP = %X'3F'; literal IPFINS$M_M33_R1 = %X'1FC0'; literal IPFINS$M_M33_13_19 = %X'FE000'; literal IPFINS$M_M33_CR3 = %X'7F00000'; literal IPFINS$M_M33_X6 = %X'1F8000000'; literal IPFINS$M_M33_X3 = %X'E00000000'; literal IPFINS$M_M33_36 = %X'1000000000'; literal IPFINS$M_M33_OPCODE = %X'1E000000000'; literal IPFINS$M_M33_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M33_FORMAT = 8; macro IPFINS$V_M33_QP = 0,0,6,0 %; literal IPFINS$S_M33_QP = 6; macro IPFINS$V_M33_R1 = 0,6,7,0 %; literal IPFINS$S_M33_R1 = 7; macro IPFINS$V_M33_13_19 = 0,13,7,0 %; literal IPFINS$S_M33_13_19 = 7; macro IPFINS$V_M33_CR3 = 0,20,7,0 %; literal IPFINS$S_M33_CR3 = 7; macro IPFINS$V_M33_X6 = 0,27,6,0 %; literal IPFINS$S_M33_X6 = 6; macro IPFINS$V_M33_X3 = 4,1,3,0 %; literal IPFINS$S_M33_X3 = 3; macro IPFINS$V_M33_36 = 4,4,1,0 %; macro IPFINS$V_M33_OPCODE = 4,5,4,0 %; literal IPFINS$S_M33_OPCODE = 4; macro IPFINS$Q_M33 = 0,0,0,0 %; literal IPFINS$S_M33 = 8; ! ! M34: Allocate Register Stack Frame ! literal IPFINS$M_M34_QP = %X'3F'; literal IPFINS$M_M34_R1 = %X'1FC0'; literal IPFINS$M_M34_SOF = %X'FE000'; literal IPFINS$M_M34_SOL = %X'7F00000'; literal IPFINS$M_M34_SOR = %X'78000000'; literal IPFINS$M_M34_31_32 = %X'180000000'; literal IPFINS$M_M34_X3 = %X'E00000000'; literal IPFINS$M_M34_36 = %X'1000000000'; literal IPFINS$M_M34_OPCODE = %X'1E000000000'; literal IPFINS$M_M34_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M34_FORMAT = 8; macro IPFINS$V_M34_QP = 0,0,6,0 %; literal IPFINS$S_M34_QP = 6; macro IPFINS$V_M34_R1 = 0,6,7,0 %; literal IPFINS$S_M34_R1 = 7; macro IPFINS$V_M34_SOF = 0,13,7,0 %; literal IPFINS$S_M34_SOF = 7; macro IPFINS$V_M34_SOL = 0,20,7,0 %; literal IPFINS$S_M34_SOL = 7; macro IPFINS$V_M34_SOR = 0,27,4,0 %; literal IPFINS$S_M34_SOR = 4; macro IPFINS$V_M34_31_32 = 0,31,2,0 %; literal IPFINS$S_M34_31_32 = 2; macro IPFINS$V_M34_X3 = 4,1,3,0 %; literal IPFINS$S_M34_X3 = 3; macro IPFINS$V_M34_36 = 4,4,1,0 %; macro IPFINS$V_M34_OPCODE = 4,5,4,0 %; literal IPFINS$S_M34_OPCODE = 4; macro IPFINS$Q_M34 = 0,0,0,0 %; literal IPFINS$S_M34 = 8; ! ! M35: Move to PSR ! literal IPFINS$M_M35_QP = %X'3F'; literal IPFINS$M_M35_6_12 = %X'1FC0'; literal IPFINS$M_M35_R2 = %X'FE000'; literal IPFINS$M_M35_20_26 = %X'7F00000'; literal IPFINS$M_M35_X6 = %X'1F8000000'; literal IPFINS$M_M35_X3 = %X'E00000000'; literal IPFINS$M_M35_36 = %X'1000000000'; literal IPFINS$M_M35_OPCODE = %X'1E000000000'; literal IPFINS$M_M35_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M35_FORMAT = 8; macro IPFINS$V_M35_QP = 0,0,6,0 %; literal IPFINS$S_M35_QP = 6; macro IPFINS$V_M35_6_12 = 0,6,7,0 %; literal IPFINS$S_M35_6_12 = 7; macro IPFINS$V_M35_R2 = 0,13,7,0 %; literal IPFINS$S_M35_R2 = 7; macro IPFINS$V_M35_20_26 = 0,20,7,0 %; literal IPFINS$S_M35_20_26 = 7; macro IPFINS$V_M35_X6 = 0,27,6,0 %; literal IPFINS$S_M35_X6 = 6; macro IPFINS$V_M35_X3 = 4,1,3,0 %; literal IPFINS$S_M35_X3 = 3; macro IPFINS$V_M35_36 = 4,4,1,0 %; macro IPFINS$V_M35_OPCODE = 4,5,4,0 %; literal IPFINS$S_M35_OPCODE = 4; macro IPFINS$Q_M35 = 0,0,0,0 %; literal IPFINS$S_M35 = 8; ! ! M36: Move from PSR ! literal IPFINS$M_M36_QP = %X'3F'; literal IPFINS$M_M36_R1 = %X'1FC0'; literal IPFINS$M_M36_13_26 = %X'7FFE000'; literal IPFINS$M_M36_X6 = %X'1F8000000'; literal IPFINS$M_M36_X3 = %X'E00000000'; literal IPFINS$M_M36_36 = %X'1000000000'; literal IPFINS$M_M36_OPCODE = %X'1E000000000'; literal IPFINS$M_M36_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M36_FORMAT = 8; macro IPFINS$V_M36_QP = 0,0,6,0 %; literal IPFINS$S_M36_QP = 6; macro IPFINS$V_M36_R1 = 0,6,7,0 %; literal IPFINS$S_M36_R1 = 7; macro IPFINS$V_M36_13_26 = 0,13,14,0 %; literal IPFINS$S_M36_13_26 = 14; macro IPFINS$V_M36_X6 = 0,27,6,0 %; literal IPFINS$S_M36_X6 = 6; macro IPFINS$V_M36_X3 = 4,1,3,0 %; literal IPFINS$S_M36_X3 = 3; macro IPFINS$V_M36_36 = 4,4,1,0 %; macro IPFINS$V_M36_OPCODE = 4,5,4,0 %; literal IPFINS$S_M36_OPCODE = 4; macro IPFINS$Q_M36 = 0,0,0,0 %; literal IPFINS$S_M36 = 8; ! ! M37: Break (M-Unit) ! literal IPFINS$M_M37_QP = %X'3F'; literal IPFINS$M_M37_IMM20A = %X'3FFFFC0'; literal IPFINS$M_M37_26 = %X'4000000'; literal IPFINS$M_M37_X4 = %X'78000000'; literal IPFINS$M_M37_X2 = %X'180000000'; literal IPFINS$M_M37_X3 = %X'E00000000'; literal IPFINS$M_M37_I = %X'1000000000'; literal IPFINS$M_M37_OPCODE = %X'1E000000000'; literal IPFINS$M_M37_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M37_FORMAT = 8; macro IPFINS$V_M37_QP = 0,0,6,0 %; literal IPFINS$S_M37_QP = 6; macro IPFINS$V_M37_IMM20A = 0,6,20,0 %; literal IPFINS$S_M37_IMM20A = 20; macro IPFINS$V_M37_26 = 0,26,1,0 %; macro IPFINS$V_M37_X4 = 0,27,4,0 %; literal IPFINS$S_M37_X4 = 4; macro IPFINS$V_M37_X2 = 0,31,2,0 %; literal IPFINS$S_M37_X2 = 2; macro IPFINS$V_M37_X3 = 4,1,3,0 %; literal IPFINS$S_M37_X3 = 3; macro IPFINS$V_M37_I = 4,4,1,0 %; macro IPFINS$V_M37_OPCODE = 4,5,4,0 %; literal IPFINS$S_M37_OPCODE = 4; macro IPFINS$Q_M37 = 0,0,0,0 %; literal IPFINS$S_M37 = 8; ! ! M38: Probe - Register ! literal IPFINS$M_M38_QP = %X'3F'; literal IPFINS$M_M38_R1 = %X'1FC0'; literal IPFINS$M_M38_R2 = %X'FE000'; literal IPFINS$M_M38_R3 = %X'7F00000'; literal IPFINS$M_M38_X6 = %X'1F8000000'; literal IPFINS$M_M38_X3 = %X'E00000000'; literal IPFINS$M_M38_36 = %X'1000000000'; literal IPFINS$M_M38_OPCODE = %X'1E000000000'; literal IPFINS$M_M38_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M38_FORMAT = 8; macro IPFINS$V_M38_QP = 0,0,6,0 %; literal IPFINS$S_M38_QP = 6; macro IPFINS$V_M38_R1 = 0,6,7,0 %; literal IPFINS$S_M38_R1 = 7; macro IPFINS$V_M38_R2 = 0,13,7,0 %; literal IPFINS$S_M38_R2 = 7; macro IPFINS$V_M38_R3 = 0,20,7,0 %; literal IPFINS$S_M38_R3 = 7; macro IPFINS$V_M38_X6 = 0,27,6,0 %; literal IPFINS$S_M38_X6 = 6; macro IPFINS$V_M38_X3 = 4,1,3,0 %; literal IPFINS$S_M38_X3 = 3; macro IPFINS$V_M38_36 = 4,4,1,0 %; macro IPFINS$V_M38_OPCODE = 4,5,4,0 %; literal IPFINS$S_M38_OPCODE = 4; macro IPFINS$Q_M38 = 0,0,0,0 %; literal IPFINS$S_M38 = 8; ! ! M39: Probe - Immediate(2) ! literal IPFINS$M_M39_QP = %X'3F'; literal IPFINS$M_M39_R1 = %X'1FC0'; literal IPFINS$M_M39_I2B = %X'6000'; literal IPFINS$M_M39_15_19 = %X'F8000'; literal IPFINS$M_M39_R3 = %X'7F00000'; literal IPFINS$M_M39_X6 = %X'1F8000000'; literal IPFINS$M_M39_X3 = %X'E00000000'; literal IPFINS$M_M39_36 = %X'1000000000'; literal IPFINS$M_M39_OPCODE = %X'1E000000000'; literal IPFINS$M_M39_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M39_FORMAT = 8; macro IPFINS$V_M39_QP = 0,0,6,0 %; literal IPFINS$S_M39_QP = 6; macro IPFINS$V_M39_R1 = 0,6,7,0 %; literal IPFINS$S_M39_R1 = 7; macro IPFINS$V_M39_I2B = 0,13,2,0 %; literal IPFINS$S_M39_I2B = 2; macro IPFINS$V_M39_15_19 = 0,15,5,0 %; literal IPFINS$S_M39_15_19 = 5; macro IPFINS$V_M39_R3 = 0,20,7,0 %; literal IPFINS$S_M39_R3 = 7; macro IPFINS$V_M39_X6 = 0,27,6,0 %; literal IPFINS$S_M39_X6 = 6; macro IPFINS$V_M39_X3 = 4,1,3,0 %; literal IPFINS$S_M39_X3 = 3; macro IPFINS$V_M39_36 = 4,4,1,0 %; macro IPFINS$V_M39_OPCODE = 4,5,4,0 %; literal IPFINS$S_M39_OPCODE = 4; macro IPFINS$Q_M39 = 0,0,0,0 %; literal IPFINS$S_M39 = 8; ! ! M40: Probe Fault - Immediate(2) ! literal IPFINS$M_M40_QP = %X'3F'; literal IPFINS$M_M40_6_12 = %X'1FC0'; literal IPFINS$M_M40_I2B = %X'6000'; literal IPFINS$M_M40_15_19 = %X'F8000'; literal IPFINS$M_M40_R3 = %X'7F00000'; literal IPFINS$M_M40_X6 = %X'1F8000000'; literal IPFINS$M_M40_X3 = %X'E00000000'; literal IPFINS$M_M40_36 = %X'1000000000'; literal IPFINS$M_M40_OPCODE = %X'1E000000000'; literal IPFINS$M_M40_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M40_FORMAT = 8; macro IPFINS$V_M40_QP = 0,0,6,0 %; literal IPFINS$S_M40_QP = 6; macro IPFINS$V_M40_6_12 = 0,6,7,0 %; literal IPFINS$S_M40_6_12 = 7; macro IPFINS$V_M40_I2B = 0,13,2,0 %; literal IPFINS$S_M40_I2B = 2; macro IPFINS$V_M40_15_19 = 0,15,5,0 %; literal IPFINS$S_M40_15_19 = 5; macro IPFINS$V_M40_R3 = 0,20,7,0 %; literal IPFINS$S_M40_R3 = 7; macro IPFINS$V_M40_X6 = 0,27,6,0 %; literal IPFINS$S_M40_X6 = 6; macro IPFINS$V_M40_X3 = 4,1,3,0 %; literal IPFINS$S_M40_X3 = 3; macro IPFINS$V_M40_36 = 4,4,1,0 %; macro IPFINS$V_M40_OPCODE = 4,5,4,0 %; literal IPFINS$S_M40_OPCODE = 4; macro IPFINS$Q_M40 = 0,0,0,0 %; literal IPFINS$S_M40 = 8; ! ! M41: Translation Cache Insert ! literal IPFINS$M_M41_QP = %X'3F'; literal IPFINS$M_M41_6_12 = %X'1FC0'; literal IPFINS$M_M41_R2 = %X'FE000'; literal IPFINS$M_M41_20_26 = %X'7F00000'; literal IPFINS$M_M41_X6 = %X'1F8000000'; literal IPFINS$M_M41_X3 = %X'E00000000'; literal IPFINS$M_M41_36 = %X'1000000000'; literal IPFINS$M_M41_OPCODE = %X'1E000000000'; literal IPFINS$M_M41_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M41_FORMAT = 8; macro IPFINS$V_M41_QP = 0,0,6,0 %; literal IPFINS$S_M41_QP = 6; macro IPFINS$V_M41_6_12 = 0,6,7,0 %; literal IPFINS$S_M41_6_12 = 7; macro IPFINS$V_M41_R2 = 0,13,7,0 %; literal IPFINS$S_M41_R2 = 7; macro IPFINS$V_M41_20_26 = 0,20,7,0 %; literal IPFINS$S_M41_20_26 = 7; macro IPFINS$V_M41_X6 = 0,27,6,0 %; literal IPFINS$S_M41_X6 = 6; macro IPFINS$V_M41_X3 = 4,1,3,0 %; literal IPFINS$S_M41_X3 = 3; macro IPFINS$V_M41_36 = 4,4,1,0 %; macro IPFINS$V_M41_OPCODE = 4,5,4,0 %; literal IPFINS$S_M41_OPCODE = 4; macro IPFINS$Q_M41 = 0,0,0,0 %; literal IPFINS$S_M41 = 8; ! ! M42: Move to Indirect Register/Translation Register Insert ! literal IPFINS$M_M42_QP = %X'3F'; literal IPFINS$M_M42_6_12 = %X'1FC0'; literal IPFINS$M_M42_R2 = %X'FE000'; literal IPFINS$M_M42_R3 = %X'7F00000'; literal IPFINS$M_M42_X6 = %X'1F8000000'; literal IPFINS$M_M42_X3 = %X'E00000000'; literal IPFINS$M_M42_36 = %X'1000000000'; literal IPFINS$M_M42_OPCODE = %X'1E000000000'; literal IPFINS$M_M42_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M42_FORMAT = 8; macro IPFINS$V_M42_QP = 0,0,6,0 %; literal IPFINS$S_M42_QP = 6; macro IPFINS$V_M42_6_12 = 0,6,7,0 %; literal IPFINS$S_M42_6_12 = 7; macro IPFINS$V_M42_R2 = 0,13,7,0 %; literal IPFINS$S_M42_R2 = 7; macro IPFINS$V_M42_R3 = 0,20,7,0 %; literal IPFINS$S_M42_R3 = 7; macro IPFINS$V_M42_X6 = 0,27,6,0 %; literal IPFINS$S_M42_X6 = 6; macro IPFINS$V_M42_X3 = 4,1,3,0 %; literal IPFINS$S_M42_X3 = 3; macro IPFINS$V_M42_36 = 4,4,1,0 %; macro IPFINS$V_M42_OPCODE = 4,5,4,0 %; literal IPFINS$S_M42_OPCODE = 4; macro IPFINS$Q_M42 = 0,0,0,0 %; literal IPFINS$S_M42 = 8; ! ! M43: Move from Indirect Register ! literal IPFINS$M_M43_QP = %X'3F'; literal IPFINS$M_M43_R1 = %X'1FC0'; literal IPFINS$M_M43_13_19 = %X'FE000'; literal IPFINS$M_M43_R3 = %X'7F00000'; literal IPFINS$M_M43_X6 = %X'1F8000000'; literal IPFINS$M_M43_X3 = %X'E00000000'; literal IPFINS$M_M43_36 = %X'1000000000'; literal IPFINS$M_M43_OPCODE = %X'1E000000000'; literal IPFINS$M_M43_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M43_FORMAT = 8; macro IPFINS$V_M43_QP = 0,0,6,0 %; literal IPFINS$S_M43_QP = 6; macro IPFINS$V_M43_R1 = 0,6,7,0 %; literal IPFINS$S_M43_R1 = 7; macro IPFINS$V_M43_13_19 = 0,13,7,0 %; literal IPFINS$S_M43_13_19 = 7; macro IPFINS$V_M43_R3 = 0,20,7,0 %; literal IPFINS$S_M43_R3 = 7; macro IPFINS$V_M43_X6 = 0,27,6,0 %; literal IPFINS$S_M43_X6 = 6; macro IPFINS$V_M43_X3 = 4,1,3,0 %; literal IPFINS$S_M43_X3 = 3; macro IPFINS$V_M43_36 = 4,4,1,0 %; macro IPFINS$V_M43_OPCODE = 4,5,4,0 %; literal IPFINS$S_M43_OPCODE = 4; macro IPFINS$Q_M43 = 0,0,0,0 %; literal IPFINS$S_M43 = 8; ! ! M44: Set/Reset User/System Mask ! literal IPFINS$M_M44_QP = %X'3F'; literal IPFINS$M_M44_IMM21A = %X'7FFFFC0'; literal IPFINS$M_M44_X4 = %X'78000000'; literal IPFINS$M_M44_I2D = %X'180000000'; literal IPFINS$M_M44_X3 = %X'E00000000'; literal IPFINS$M_M44_I = %X'1000000000'; literal IPFINS$M_M44_OPCODE = %X'1E000000000'; literal IPFINS$M_M44_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M44_FORMAT = 8; macro IPFINS$V_M44_QP = 0,0,6,0 %; literal IPFINS$S_M44_QP = 6; macro IPFINS$V_M44_IMM21A = 0,6,21,0 %; literal IPFINS$S_M44_IMM21A = 21; macro IPFINS$V_M44_X4 = 0,27,4,0 %; literal IPFINS$S_M44_X4 = 4; macro IPFINS$V_M44_I2D = 0,31,2,0 %; literal IPFINS$S_M44_I2D = 2; macro IPFINS$V_M44_X3 = 4,1,3,0 %; literal IPFINS$S_M44_X3 = 3; macro IPFINS$V_M44_I = 4,4,1,0 %; macro IPFINS$V_M44_OPCODE = 4,5,4,0 %; literal IPFINS$S_M44_OPCODE = 4; macro IPFINS$Q_M44 = 0,0,0,0 %; literal IPFINS$S_M44 = 8; ! ! M45: Translation Purge ! literal IPFINS$M_M45_QP = %X'3F'; literal IPFINS$M_M45_6_12 = %X'1FC0'; literal IPFINS$M_M45_R2 = %X'FE000'; literal IPFINS$M_M45_R3 = %X'7F00000'; literal IPFINS$M_M45_X6 = %X'1F8000000'; literal IPFINS$M_M45_X3 = %X'E00000000'; literal IPFINS$M_M45_36 = %X'1000000000'; literal IPFINS$M_M45_OPCODE = %X'1E000000000'; literal IPFINS$M_M45_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M45_FORMAT = 8; macro IPFINS$V_M45_QP = 0,0,6,0 %; literal IPFINS$S_M45_QP = 6; macro IPFINS$V_M45_6_12 = 0,6,7,0 %; literal IPFINS$S_M45_6_12 = 7; macro IPFINS$V_M45_R2 = 0,13,7,0 %; literal IPFINS$S_M45_R2 = 7; macro IPFINS$V_M45_R3 = 0,20,7,0 %; literal IPFINS$S_M45_R3 = 7; macro IPFINS$V_M45_X6 = 0,27,6,0 %; literal IPFINS$S_M45_X6 = 6; macro IPFINS$V_M45_X3 = 4,1,3,0 %; literal IPFINS$S_M45_X3 = 3; macro IPFINS$V_M45_36 = 4,4,1,0 %; macro IPFINS$V_M45_OPCODE = 4,5,4,0 %; literal IPFINS$S_M45_OPCODE = 4; macro IPFINS$Q_M45 = 0,0,0,0 %; literal IPFINS$S_M45 = 8; ! ! M46: Translation Access ! literal IPFINS$M_M46_QP = %X'3F'; literal IPFINS$M_M46_R1 = %X'1FC0'; literal IPFINS$M_M46_13_19 = %X'FE000'; literal IPFINS$M_M46_R3 = %X'7F00000'; literal IPFINS$M_M46_X6 = %X'1F8000000'; literal IPFINS$M_M46_X3 = %X'E00000000'; literal IPFINS$M_M46_36 = %X'1000000000'; literal IPFINS$M_M46_OPCODE = %X'1E000000000'; literal IPFINS$M_M46_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M46_FORMAT = 8; macro IPFINS$V_M46_QP = 0,0,6,0 %; literal IPFINS$S_M46_QP = 6; macro IPFINS$V_M46_R1 = 0,6,7,0 %; literal IPFINS$S_M46_R1 = 7; macro IPFINS$V_M46_13_19 = 0,13,7,0 %; literal IPFINS$S_M46_13_19 = 7; macro IPFINS$V_M46_R3 = 0,20,7,0 %; literal IPFINS$S_M46_R3 = 7; macro IPFINS$V_M46_X6 = 0,27,6,0 %; literal IPFINS$S_M46_X6 = 6; macro IPFINS$V_M46_X3 = 4,1,3,0 %; literal IPFINS$S_M46_X3 = 3; macro IPFINS$V_M46_36 = 4,4,1,0 %; macro IPFINS$V_M46_OPCODE = 4,5,4,0 %; literal IPFINS$S_M46_OPCODE = 4; macro IPFINS$Q_M46 = 0,0,0,0 %; literal IPFINS$S_M46 = 8; ! ! M47: Purge Translation Cache Entry ! literal IPFINS$M_M47_QP = %X'3F'; literal IPFINS$M_M47_6_19 = %X'FFFC0'; literal IPFINS$M_M47_R3 = %X'7F00000'; literal IPFINS$M_M47_X6 = %X'1F8000000'; literal IPFINS$M_M47_X3 = %X'E00000000'; literal IPFINS$M_M47_36 = %X'1000000000'; literal IPFINS$M_M47_OPCODE = %X'1E000000000'; literal IPFINS$M_M47_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M47_FORMAT = 8; macro IPFINS$V_M47_QP = 0,0,6,0 %; literal IPFINS$S_M47_QP = 6; macro IPFINS$V_M47_6_19 = 0,6,14,0 %; literal IPFINS$S_M47_6_19 = 14; macro IPFINS$V_M47_R3 = 0,20,7,0 %; literal IPFINS$S_M47_R3 = 7; macro IPFINS$V_M47_X6 = 0,27,6,0 %; literal IPFINS$S_M47_X6 = 6; macro IPFINS$V_M47_X3 = 4,1,3,0 %; literal IPFINS$S_M47_X3 = 3; macro IPFINS$V_M47_36 = 4,4,1,0 %; macro IPFINS$V_M47_OPCODE = 4,5,4,0 %; literal IPFINS$S_M47_OPCODE = 4; macro IPFINS$Q_M47 = 0,0,0,0 %; literal IPFINS$S_M47 = 8; ! ! M48: Nop/Hint (M-Unit) ! literal IPFINS$M_M48_QP = %X'3F'; literal IPFINS$M_M48_IMM20A = %X'3FFFFC0'; literal IPFINS$M_M48_Y = %X'4000000'; literal IPFINS$M_M48_X4 = %X'78000000'; literal IPFINS$M_M48_X2 = %X'180000000'; literal IPFINS$M_M48_X3 = %X'E00000000'; literal IPFINS$M_M48_I = %X'1000000000'; literal IPFINS$M_M48_OPCODE = %X'1E000000000'; literal IPFINS$M_M48_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_M48_FORMAT = 8; macro IPFINS$V_M48_QP = 0,0,6,0 %; literal IPFINS$S_M48_QP = 6; macro IPFINS$V_M48_IMM20A = 0,6,20,0 %; literal IPFINS$S_M48_IMM20A = 20; macro IPFINS$V_M48_Y = 0,26,1,0 %; macro IPFINS$V_M48_X4 = 0,27,4,0 %; literal IPFINS$S_M48_X4 = 4; macro IPFINS$V_M48_X2 = 0,31,2,0 %; literal IPFINS$S_M48_X2 = 2; macro IPFINS$V_M48_X3 = 4,1,3,0 %; literal IPFINS$S_M48_X3 = 3; macro IPFINS$V_M48_I = 4,4,1,0 %; macro IPFINS$V_M48_OPCODE = 4,5,4,0 %; literal IPFINS$S_M48_OPCODE = 4; macro IPFINS$Q_M48 = 0,0,0,0 %; literal IPFINS$S_M48 = 8; ! ! B-Unit Formats ! ! ! B1: IP-Relative Branch ! literal IPFINS$M_B1_QP = %X'3F'; literal IPFINS$M_B1_BTYPE = %X'1C0'; literal IPFINS$M_B1_9_11 = %X'E00'; literal IPFINS$M_B1_P = %X'1000'; literal IPFINS$M_B1_IMM20B = %X'1FFFFE000'; literal IPFINS$M_B1_WH = %X'600000000'; literal IPFINS$M_B1_D = %X'800000000'; literal IPFINS$M_B1_S = %X'1000000000'; literal IPFINS$M_B1_OPCODE = %X'1E000000000'; literal IPFINS$M_B1_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_B1_FORMAT = 8; macro IPFINS$V_B1_QP = 0,0,6,0 %; literal IPFINS$S_B1_QP = 6; macro IPFINS$V_B1_BTYPE = 0,6,3,0 %; literal IPFINS$S_B1_BTYPE = 3; macro IPFINS$V_B1_9_11 = 0,9,3,0 %; literal IPFINS$S_B1_9_11 = 3; macro IPFINS$V_B1_P = 0,12,1,0 %; macro IPFINS$V_B1_IMM20B = 0,13,20,0 %; literal IPFINS$S_B1_IMM20B = 20; macro IPFINS$V_B1_WH = 4,1,2,0 %; literal IPFINS$S_B1_WH = 2; macro IPFINS$V_B1_D = 4,3,1,0 %; macro IPFINS$V_B1_S = 4,4,1,1 %; macro IPFINS$V_B1_OPCODE = 4,5,4,0 %; literal IPFINS$S_B1_OPCODE = 4; macro IPFINS$Q_B1 = 0,0,0,0 %; literal IPFINS$S_B1 = 8; ! ! B2: IP-Relative Counted Branch ! literal IPFINS$M_B2_ZERO = %X'3F'; literal IPFINS$M_B2_BTYPE = %X'1C0'; literal IPFINS$M_B2_9_11 = %X'E00'; literal IPFINS$M_B2_P = %X'1000'; literal IPFINS$M_B2_IMM20B = %X'1FFFFE000'; literal IPFINS$M_B2_WH = %X'600000000'; literal IPFINS$M_B2_D = %X'800000000'; literal IPFINS$M_B2_S = %X'1000000000'; literal IPFINS$M_B2_OPCODE = %X'1E000000000'; literal IPFINS$M_B2_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_B2_FORMAT = 8; macro IPFINS$V_B2_ZERO = 0,0,6,0 %; literal IPFINS$S_B2_ZERO = 6; macro IPFINS$V_B2_BTYPE = 0,6,3,0 %; literal IPFINS$S_B2_BTYPE = 3; macro IPFINS$V_B2_9_11 = 0,9,3,0 %; literal IPFINS$S_B2_9_11 = 3; macro IPFINS$V_B2_P = 0,12,1,0 %; macro IPFINS$V_B2_IMM20B = 0,13,20,0 %; literal IPFINS$S_B2_IMM20B = 20; macro IPFINS$V_B2_WH = 4,1,2,0 %; literal IPFINS$S_B2_WH = 2; macro IPFINS$V_B2_D = 4,3,1,0 %; macro IPFINS$V_B2_S = 4,4,1,1 %; macro IPFINS$V_B2_OPCODE = 4,5,4,0 %; literal IPFINS$S_B2_OPCODE = 4; macro IPFINS$Q_B2 = 0,0,0,0 %; literal IPFINS$S_B2 = 8; ! ! B3: IP-Relative Call ! literal IPFINS$M_B3_QP = %X'3F'; literal IPFINS$M_B3_B1 = %X'1C0'; literal IPFINS$M_B3_9_11 = %X'E00'; literal IPFINS$M_B3_P = %X'1000'; literal IPFINS$M_B3_IMM20B = %X'1FFFFE000'; literal IPFINS$M_B3_WH = %X'600000000'; literal IPFINS$M_B3_D = %X'800000000'; literal IPFINS$M_B3_S = %X'1000000000'; literal IPFINS$M_B3_OPCODE = %X'1E000000000'; literal IPFINS$M_B3_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_B3_FORMAT = 8; macro IPFINS$V_B3_QP = 0,0,6,0 %; literal IPFINS$S_B3_QP = 6; macro IPFINS$V_B3_B1 = 0,6,3,0 %; literal IPFINS$S_B3_B1 = 3; macro IPFINS$V_B3_9_11 = 0,9,3,0 %; literal IPFINS$S_B3_9_11 = 3; macro IPFINS$V_B3_P = 0,12,1,0 %; macro IPFINS$V_B3_IMM20B = 0,13,20,0 %; literal IPFINS$S_B3_IMM20B = 20; macro IPFINS$V_B3_WH = 4,1,2,0 %; literal IPFINS$S_B3_WH = 2; macro IPFINS$V_B3_D = 4,3,1,0 %; macro IPFINS$V_B3_S = 4,4,1,1 %; macro IPFINS$V_B3_OPCODE = 4,5,4,0 %; literal IPFINS$S_B3_OPCODE = 4; macro IPFINS$Q_B3 = 0,0,0,0 %; literal IPFINS$S_B3 = 8; ! ! B4: Indirect Branch ! literal IPFINS$M_B4_QP = %X'3F'; literal IPFINS$M_B4_BTYPE = %X'1C0'; literal IPFINS$M_B4_9_11 = %X'E00'; literal IPFINS$M_B4_P = %X'1000'; literal IPFINS$M_B4_B2 = %X'E000'; literal IPFINS$M_B4_16_26 = %X'7FF0000'; literal IPFINS$M_B4_X6 = %X'1F8000000'; literal IPFINS$M_B4_WH = %X'600000000'; literal IPFINS$M_B4_D = %X'800000000'; literal IPFINS$M_B4_36 = %X'1000000000'; literal IPFINS$M_B4_OPCODE = %X'1E000000000'; literal IPFINS$M_B4_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_B4_FORMAT = 8; macro IPFINS$V_B4_QP = 0,0,6,0 %; literal IPFINS$S_B4_QP = 6; macro IPFINS$V_B4_BTYPE = 0,6,3,0 %; literal IPFINS$S_B4_BTYPE = 3; macro IPFINS$V_B4_9_11 = 0,9,3,0 %; literal IPFINS$S_B4_9_11 = 3; macro IPFINS$V_B4_P = 0,12,1,0 %; macro IPFINS$V_B4_B2 = 0,13,3,0 %; literal IPFINS$S_B4_B2 = 3; macro IPFINS$V_B4_16_26 = 0,16,11,0 %; literal IPFINS$S_B4_16_26 = 11; macro IPFINS$V_B4_X6 = 0,27,6,0 %; literal IPFINS$S_B4_X6 = 6; macro IPFINS$V_B4_WH = 4,1,2,0 %; literal IPFINS$S_B4_WH = 2; macro IPFINS$V_B4_D = 4,3,1,0 %; macro IPFINS$V_B4_36 = 4,4,1,0 %; macro IPFINS$V_B4_OPCODE = 4,5,4,0 %; literal IPFINS$S_B4_OPCODE = 4; macro IPFINS$Q_B4 = 0,0,0,0 %; literal IPFINS$S_B4 = 8; ! ! B5: Indirect Call ! literal IPFINS$M_B5_QP = %X'3F'; literal IPFINS$M_B5_B1 = %X'1C0'; literal IPFINS$M_B5_9_11 = %X'E00'; literal IPFINS$M_B5_P = %X'1000'; literal IPFINS$M_B5_B2 = %X'E000'; literal IPFINS$M_B5_16_31 = %X'FFFF0000'; literal IPFINS$M_B5_WH = %X'700000000'; literal IPFINS$M_B5_D = %X'800000000'; literal IPFINS$M_B5_36 = %X'1000000000'; literal IPFINS$M_B5_OPCODE = %X'1E000000000'; literal IPFINS$M_B5_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_B5_FORMAT = 8; macro IPFINS$V_B5_QP = 0,0,6,0 %; literal IPFINS$S_B5_QP = 6; macro IPFINS$V_B5_B1 = 0,6,3,0 %; literal IPFINS$S_B5_B1 = 3; macro IPFINS$V_B5_9_11 = 0,9,3,0 %; literal IPFINS$S_B5_9_11 = 3; macro IPFINS$V_B5_P = 0,12,1,0 %; macro IPFINS$V_B5_B2 = 0,13,3,0 %; literal IPFINS$S_B5_B2 = 3; macro IPFINS$V_B5_16_31 = 0,16,16,0 %; literal IPFINS$S_B5_16_31 = 16; macro IPFINS$V_B5_WH = 4,0,3,0 %; literal IPFINS$S_B5_WH = 3; macro IPFINS$V_B5_D = 4,3,1,0 %; macro IPFINS$V_B5_36 = 4,4,1,0 %; macro IPFINS$V_B5_OPCODE = 4,5,4,0 %; literal IPFINS$S_B5_OPCODE = 4; macro IPFINS$Q_B5 = 0,0,0,0 %; literal IPFINS$S_B5 = 8; ! ! B6: IP-Relative Predict ! literal IPFINS$M_B6_0_2 = %X'7'; literal IPFINS$M_B6_WH = %X'18'; literal IPFINS$M_B6_5 = %X'20'; literal IPFINS$M_B6_TIMM7A = %X'1FC0'; literal IPFINS$M_B6_IMM20B = %X'1FFFFE000'; literal IPFINS$M_B6_T2E = %X'600000000'; literal IPFINS$M_B6_IH = %X'800000000'; literal IPFINS$M_B6_S = %X'1000000000'; literal IPFINS$M_B6_OPCODE = %X'1E000000000'; literal IPFINS$M_B6_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_B6_FORMAT = 8; macro IPFINS$V_B6_0_2 = 0,0,3,0 %; literal IPFINS$S_B6_0_2 = 3; macro IPFINS$V_B6_WH = 0,3,2,0 %; literal IPFINS$S_B6_WH = 2; macro IPFINS$V_B6_5 = 0,5,1,0 %; macro IPFINS$V_B6_TIMM7A = 0,6,7,0 %; literal IPFINS$S_B6_TIMM7A = 7; macro IPFINS$V_B6_IMM20B = 0,13,20,0 %; literal IPFINS$S_B6_IMM20B = 20; macro IPFINS$V_B6_T2E = 4,1,2,1 %; literal IPFINS$S_B6_T2E = 2; macro IPFINS$V_B6_IH = 4,3,1,0 %; macro IPFINS$V_B6_S = 4,4,1,1 %; macro IPFINS$V_B6_OPCODE = 4,5,4,0 %; literal IPFINS$S_B6_OPCODE = 4; macro IPFINS$Q_B6 = 0,0,0,0 %; literal IPFINS$S_B6 = 8; ! ! B7: Indirect Predict ! literal IPFINS$M_B7_0_2 = %X'7'; literal IPFINS$M_B7_WH = %X'18'; literal IPFINS$M_B7_5 = %X'20'; literal IPFINS$M_B7_TIMM7A = %X'1FC0'; literal IPFINS$M_B7_B2 = %X'E000'; literal IPFINS$M_B7_16_26 = %X'7FF0000'; literal IPFINS$M_B7_X6 = %X'1F8000000'; literal IPFINS$M_B7_T2E = %X'600000000'; literal IPFINS$M_B7_IH = %X'800000000'; literal IPFINS$M_B7_36 = %X'1000000000'; literal IPFINS$M_B7_OPCODE = %X'1E000000000'; literal IPFINS$M_B7_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_B7_FORMAT = 8; macro IPFINS$V_B7_0_2 = 0,0,3,0 %; literal IPFINS$S_B7_0_2 = 3; macro IPFINS$V_B7_WH = 0,3,2,0 %; literal IPFINS$S_B7_WH = 2; macro IPFINS$V_B7_5 = 0,5,1,0 %; macro IPFINS$V_B7_TIMM7A = 0,6,7,0 %; literal IPFINS$S_B7_TIMM7A = 7; macro IPFINS$V_B7_B2 = 0,13,3,0 %; literal IPFINS$S_B7_B2 = 3; macro IPFINS$V_B7_16_26 = 0,16,11,0 %; literal IPFINS$S_B7_16_26 = 11; macro IPFINS$V_B7_X6 = 0,27,6,0 %; literal IPFINS$S_B7_X6 = 6; macro IPFINS$V_B7_T2E = 4,1,2,1 %; literal IPFINS$S_B7_T2E = 2; macro IPFINS$V_B7_IH = 4,3,1,0 %; macro IPFINS$V_B7_36 = 4,4,1,0 %; macro IPFINS$V_B7_OPCODE = 4,5,4,0 %; literal IPFINS$S_B7_OPCODE = 4; macro IPFINS$Q_B7 = 0,0,0,0 %; literal IPFINS$S_B7 = 8; ! ! B8: Miscellaneous (B-Unit) ! literal IPFINS$M_B8_ZERO = %X'3F'; literal IPFINS$M_B8_6_26 = %X'7FFFFC0'; literal IPFINS$M_B8_X6 = %X'1F8000000'; literal IPFINS$M_B8_33_36 = %X'1E00000000'; literal IPFINS$M_B8_OPCODE = %X'1E000000000'; literal IPFINS$M_B8_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_B8_FORMAT = 8; macro IPFINS$V_B8_ZERO = 0,0,6,0 %; literal IPFINS$S_B8_ZERO = 6; macro IPFINS$V_B8_6_26 = 0,6,21,0 %; literal IPFINS$S_B8_6_26 = 21; macro IPFINS$V_B8_X6 = 0,27,6,0 %; literal IPFINS$S_B8_X6 = 6; macro IPFINS$V_B8_33_36 = 4,1,4,0 %; literal IPFINS$S_B8_33_36 = 4; macro IPFINS$V_B8_OPCODE = 4,5,4,0 %; literal IPFINS$S_B8_OPCODE = 4; macro IPFINS$Q_B8 = 0,0,0,0 %; literal IPFINS$S_B8 = 8; ! ! B9: Break/Nop/Hint (B-Unit) ! literal IPFINS$M_B9_QP = %X'3F'; literal IPFINS$M_B9_IMM20A = %X'3FFFFC0'; literal IPFINS$M_B9_26 = %X'4000000'; literal IPFINS$M_B9_X6 = %X'1F8000000'; literal IPFINS$M_B9_33_35 = %X'E00000000'; literal IPFINS$M_B9_I = %X'1000000000'; literal IPFINS$M_B9_OPCODE = %X'1E000000000'; literal IPFINS$M_B9_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_B9_FORMAT = 8; macro IPFINS$V_B9_QP = 0,0,6,0 %; literal IPFINS$S_B9_QP = 6; macro IPFINS$V_B9_IMM20A = 0,6,20,0 %; literal IPFINS$S_B9_IMM20A = 20; macro IPFINS$V_B9_26 = 0,26,1,0 %; macro IPFINS$V_B9_X6 = 0,27,6,0 %; literal IPFINS$S_B9_X6 = 6; macro IPFINS$V_B9_33_35 = 4,1,3,0 %; literal IPFINS$S_B9_33_35 = 3; macro IPFINS$V_B9_I = 4,4,1,0 %; macro IPFINS$V_B9_OPCODE = 4,5,4,0 %; literal IPFINS$S_B9_OPCODE = 4; macro IPFINS$Q_B9 = 0,0,0,0 %; literal IPFINS$S_B9 = 8; ! ! F-Unit Formats ! ! ! F1: Floating-point Multiply Add ! literal IPFINS$M_F1_QP = %X'3F'; literal IPFINS$M_F1_F1 = %X'1FC0'; literal IPFINS$M_F1_F2 = %X'FE000'; literal IPFINS$M_F1_F3 = %X'7F00000'; literal IPFINS$M_F1_F4 = %X'3F8000000'; literal IPFINS$M_F1_SF = %X'C00000000'; literal IPFINS$M_F1_X = %X'1000000000'; literal IPFINS$M_F1_OPCODE = %X'1E000000000'; literal IPFINS$M_F1_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F1_FORMAT = 8; macro IPFINS$V_F1_QP = 0,0,6,0 %; literal IPFINS$S_F1_QP = 6; macro IPFINS$V_F1_F1 = 0,6,7,0 %; literal IPFINS$S_F1_F1 = 7; macro IPFINS$V_F1_F2 = 0,13,7,0 %; literal IPFINS$S_F1_F2 = 7; macro IPFINS$V_F1_F3 = 0,20,7,0 %; literal IPFINS$S_F1_F3 = 7; macro IPFINS$V_F1_F4 = 0,27,7,0 %; literal IPFINS$S_F1_F4 = 7; macro IPFINS$V_F1_SF = 4,2,2,0 %; literal IPFINS$S_F1_SF = 2; macro IPFINS$V_F1_X = 4,4,1,0 %; macro IPFINS$V_F1_OPCODE = 4,5,4,0 %; literal IPFINS$S_F1_OPCODE = 4; macro IPFINS$Q_F1 = 0,0,0,0 %; literal IPFINS$S_F1 = 8; ! ! F2: Fixed-point Multiply Add ! literal IPFINS$M_F2_QP = %X'3F'; literal IPFINS$M_F2_F1 = %X'1FC0'; literal IPFINS$M_F2_F2 = %X'FE000'; literal IPFINS$M_F2_F3 = %X'7F00000'; literal IPFINS$M_F2_F4 = %X'3F8000000'; literal IPFINS$M_F2_X2 = %X'C00000000'; literal IPFINS$M_F2_X = %X'1000000000'; literal IPFINS$M_F2_OPCODE = %X'1E000000000'; literal IPFINS$M_F2_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F2_FORMAT = 8; macro IPFINS$V_F2_QP = 0,0,6,0 %; literal IPFINS$S_F2_QP = 6; macro IPFINS$V_F2_F1 = 0,6,7,0 %; literal IPFINS$S_F2_F1 = 7; macro IPFINS$V_F2_F2 = 0,13,7,0 %; literal IPFINS$S_F2_F2 = 7; macro IPFINS$V_F2_F3 = 0,20,7,0 %; literal IPFINS$S_F2_F3 = 7; macro IPFINS$V_F2_F4 = 0,27,7,0 %; literal IPFINS$S_F2_F4 = 7; macro IPFINS$V_F2_X2 = 4,2,2,0 %; literal IPFINS$S_F2_X2 = 2; macro IPFINS$V_F2_X = 4,4,1,0 %; macro IPFINS$V_F2_OPCODE = 4,5,4,0 %; literal IPFINS$S_F2_OPCODE = 4; macro IPFINS$Q_F2 = 0,0,0,0 %; literal IPFINS$S_F2 = 8; ! ! F3: Parallel Floating-point Select ! literal IPFINS$M_F3_QP = %X'3F'; literal IPFINS$M_F3_F1 = %X'1FC0'; literal IPFINS$M_F3_F2 = %X'FE000'; literal IPFINS$M_F3_F3 = %X'7F00000'; literal IPFINS$M_F3_F4 = %X'3F8000000'; literal IPFINS$M_F3_34_35 = %X'C00000000'; literal IPFINS$M_F3_X = %X'1000000000'; literal IPFINS$M_F3_OPCODE = %X'1E000000000'; literal IPFINS$M_F3_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F3_FORMAT = 8; macro IPFINS$V_F3_QP = 0,0,6,0 %; literal IPFINS$S_F3_QP = 6; macro IPFINS$V_F3_F1 = 0,6,7,0 %; literal IPFINS$S_F3_F1 = 7; macro IPFINS$V_F3_F2 = 0,13,7,0 %; literal IPFINS$S_F3_F2 = 7; macro IPFINS$V_F3_F3 = 0,20,7,0 %; literal IPFINS$S_F3_F3 = 7; macro IPFINS$V_F3_F4 = 0,27,7,0 %; literal IPFINS$S_F3_F4 = 7; macro IPFINS$V_F3_34_35 = 4,2,2,0 %; literal IPFINS$S_F3_34_35 = 2; macro IPFINS$V_F3_X = 4,4,1,0 %; macro IPFINS$V_F3_OPCODE = 4,5,4,0 %; literal IPFINS$S_F3_OPCODE = 4; macro IPFINS$Q_F3 = 0,0,0,0 %; literal IPFINS$S_F3 = 8; ! ! F4: Floating-point Compare ! literal IPFINS$M_F4_QP = %X'3F'; literal IPFINS$M_F4_P1 = %X'FC0'; literal IPFINS$M_F4_TA = %X'1000'; literal IPFINS$M_F4_F2 = %X'FE000'; literal IPFINS$M_F4_F3 = %X'7F00000'; literal IPFINS$M_F4_P2 = %X'1F8000000'; literal IPFINS$M_F4_RA = %X'200000000'; literal IPFINS$M_F4_SF = %X'C00000000'; literal IPFINS$M_F4_RB = %X'1000000000'; literal IPFINS$M_F4_OPCODE = %X'1E000000000'; literal IPFINS$M_F4_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F4_FORMAT = 8; macro IPFINS$V_F4_QP = 0,0,6,0 %; literal IPFINS$S_F4_QP = 6; macro IPFINS$V_F4_P1 = 0,6,6,0 %; literal IPFINS$S_F4_P1 = 6; macro IPFINS$V_F4_TA = 0,12,1,0 %; macro IPFINS$V_F4_F2 = 0,13,7,0 %; literal IPFINS$S_F4_F2 = 7; macro IPFINS$V_F4_F3 = 0,20,7,0 %; literal IPFINS$S_F4_F3 = 7; macro IPFINS$V_F4_P2 = 0,27,6,0 %; literal IPFINS$S_F4_P2 = 6; macro IPFINS$V_F4_RA = 4,1,1,0 %; macro IPFINS$V_F4_SF = 4,2,2,0 %; literal IPFINS$S_F4_SF = 2; macro IPFINS$V_F4_RB = 4,4,1,0 %; macro IPFINS$V_F4_OPCODE = 4,5,4,0 %; literal IPFINS$S_F4_OPCODE = 4; macro IPFINS$Q_F4 = 0,0,0,0 %; literal IPFINS$S_F4 = 8; ! ! F5: Floating-point Class ! literal IPFINS$M_F5_QP = %X'3F'; literal IPFINS$M_F5_P1 = %X'FC0'; literal IPFINS$M_F5_TA = %X'1000'; literal IPFINS$M_F5_F2 = %X'FE000'; literal IPFINS$M_F5_FCLASS7C = %X'7F00000'; literal IPFINS$M_F5_P2 = %X'1F8000000'; literal IPFINS$M_F5_FC2 = %X'600000000'; literal IPFINS$M_F5_35_36 = %X'1800000000'; literal IPFINS$M_F5_OPCODE = %X'1E000000000'; literal IPFINS$M_F5_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F5_FORMAT = 8; macro IPFINS$V_F5_QP = 0,0,6,0 %; literal IPFINS$S_F5_QP = 6; macro IPFINS$V_F5_P1 = 0,6,6,0 %; literal IPFINS$S_F5_P1 = 6; macro IPFINS$V_F5_TA = 0,12,1,0 %; macro IPFINS$V_F5_F2 = 0,13,7,0 %; literal IPFINS$S_F5_F2 = 7; macro IPFINS$V_F5_FCLASS7C = 0,20,7,0 %; literal IPFINS$S_F5_FCLASS7C = 7; macro IPFINS$V_F5_P2 = 0,27,6,0 %; literal IPFINS$S_F5_P2 = 6; macro IPFINS$V_F5_FC2 = 4,1,2,0 %; literal IPFINS$S_F5_FC2 = 2; macro IPFINS$V_F5_35_36 = 4,3,2,0 %; literal IPFINS$S_F5_35_36 = 2; macro IPFINS$V_F5_OPCODE = 4,5,4,0 %; literal IPFINS$S_F5_OPCODE = 4; macro IPFINS$Q_F5 = 0,0,0,0 %; literal IPFINS$S_F5 = 8; ! ! F6: Floating-point Reciprocal Approximation ! literal IPFINS$M_F6_QP = %X'3F'; literal IPFINS$M_F6_F1 = %X'1FC0'; literal IPFINS$M_F6_F2 = %X'FE000'; literal IPFINS$M_F6_F3 = %X'7F00000'; literal IPFINS$M_F6_P2 = %X'1F8000000'; literal IPFINS$M_F6_X = %X'200000000'; literal IPFINS$M_F6_SF = %X'C00000000'; literal IPFINS$M_F6_Q = %X'1000000000'; literal IPFINS$M_F6_OPCODE = %X'1E000000000'; literal IPFINS$M_F6_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F6_FORMAT = 8; macro IPFINS$V_F6_QP = 0,0,6,0 %; literal IPFINS$S_F6_QP = 6; macro IPFINS$V_F6_F1 = 0,6,7,0 %; literal IPFINS$S_F6_F1 = 7; macro IPFINS$V_F6_F2 = 0,13,7,0 %; literal IPFINS$S_F6_F2 = 7; macro IPFINS$V_F6_F3 = 0,20,7,0 %; literal IPFINS$S_F6_F3 = 7; macro IPFINS$V_F6_P2 = 0,27,6,0 %; literal IPFINS$S_F6_P2 = 6; macro IPFINS$V_F6_X = 4,1,1,0 %; macro IPFINS$V_F6_SF = 4,2,2,0 %; literal IPFINS$S_F6_SF = 2; macro IPFINS$V_F6_Q = 4,4,1,0 %; macro IPFINS$V_F6_OPCODE = 4,5,4,0 %; literal IPFINS$S_F6_OPCODE = 4; macro IPFINS$Q_F6 = 0,0,0,0 %; literal IPFINS$S_F6 = 8; ! ! F7: Floating-point Reciprocal Square Root Approximation ! literal IPFINS$M_F7_QP = %X'3F'; literal IPFINS$M_F7_F1 = %X'1FC0'; literal IPFINS$M_F7_ZERO = %X'FE000'; literal IPFINS$M_F7_F3 = %X'7F00000'; literal IPFINS$M_F7_P2 = %X'1F8000000'; literal IPFINS$M_F7_X = %X'200000000'; literal IPFINS$M_F7_SF = %X'C00000000'; literal IPFINS$M_F7_Q = %X'1000000000'; literal IPFINS$M_F7_OPCODE = %X'1E000000000'; literal IPFINS$M_F7_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F7_FORMAT = 8; macro IPFINS$V_F7_QP = 0,0,6,0 %; literal IPFINS$S_F7_QP = 6; macro IPFINS$V_F7_F1 = 0,6,7,0 %; literal IPFINS$S_F7_F1 = 7; macro IPFINS$V_F7_ZERO = 0,13,7,0 %; literal IPFINS$S_F7_ZERO = 7; macro IPFINS$V_F7_F3 = 0,20,7,0 %; literal IPFINS$S_F7_F3 = 7; macro IPFINS$V_F7_P2 = 0,27,6,0 %; literal IPFINS$S_F7_P2 = 6; macro IPFINS$V_F7_X = 4,1,1,0 %; macro IPFINS$V_F7_SF = 4,2,2,0 %; literal IPFINS$S_F7_SF = 2; macro IPFINS$V_F7_Q = 4,4,1,0 %; macro IPFINS$V_F7_OPCODE = 4,5,4,0 %; literal IPFINS$S_F7_OPCODE = 4; macro IPFINS$Q_F7 = 0,0,0,0 %; literal IPFINS$S_F7 = 8; ! ! F8: Minimum/Maximum and Parallel Compare ! literal IPFINS$M_F8_QP = %X'3F'; literal IPFINS$M_F8_F1 = %X'1FC0'; literal IPFINS$M_F8_F2 = %X'FE000'; literal IPFINS$M_F8_F3 = %X'7F00000'; literal IPFINS$M_F8_X6 = %X'1F8000000'; literal IPFINS$M_F8_X = %X'200000000'; literal IPFINS$M_F8_SF = %X'C00000000'; literal IPFINS$M_F8_36 = %X'1000000000'; literal IPFINS$M_F8_OPCODE = %X'1E000000000'; literal IPFINS$M_F8_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F8_FORMAT = 8; macro IPFINS$V_F8_QP = 0,0,6,0 %; literal IPFINS$S_F8_QP = 6; macro IPFINS$V_F8_F1 = 0,6,7,0 %; literal IPFINS$S_F8_F1 = 7; macro IPFINS$V_F8_F2 = 0,13,7,0 %; literal IPFINS$S_F8_F2 = 7; macro IPFINS$V_F8_F3 = 0,20,7,0 %; literal IPFINS$S_F8_F3 = 7; macro IPFINS$V_F8_X6 = 0,27,6,0 %; literal IPFINS$S_F8_X6 = 6; macro IPFINS$V_F8_X = 4,1,1,0 %; macro IPFINS$V_F8_SF = 4,2,2,0 %; literal IPFINS$S_F8_SF = 2; macro IPFINS$V_F8_36 = 4,4,1,0 %; macro IPFINS$V_F8_OPCODE = 4,5,4,0 %; literal IPFINS$S_F8_OPCODE = 4; macro IPFINS$Q_F8 = 0,0,0,0 %; literal IPFINS$S_F8 = 8; ! ! F9: Merge and Logical ! literal IPFINS$M_F9_QP = %X'3F'; literal IPFINS$M_F9_F1 = %X'1FC0'; literal IPFINS$M_F9_F2 = %X'FE000'; literal IPFINS$M_F9_F3 = %X'7F00000'; literal IPFINS$M_F9_X6 = %X'1F8000000'; literal IPFINS$M_F9_X = %X'200000000'; literal IPFINS$M_F9_34_36 = %X'1C00000000'; literal IPFINS$M_F9_OPCODE = %X'1E000000000'; literal IPFINS$M_F9_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F9_FORMAT = 8; macro IPFINS$V_F9_QP = 0,0,6,0 %; literal IPFINS$S_F9_QP = 6; macro IPFINS$V_F9_F1 = 0,6,7,0 %; literal IPFINS$S_F9_F1 = 7; macro IPFINS$V_F9_F2 = 0,13,7,0 %; literal IPFINS$S_F9_F2 = 7; macro IPFINS$V_F9_F3 = 0,20,7,0 %; literal IPFINS$S_F9_F3 = 7; macro IPFINS$V_F9_X6 = 0,27,6,0 %; literal IPFINS$S_F9_X6 = 6; macro IPFINS$V_F9_X = 4,1,1,0 %; macro IPFINS$V_F9_34_36 = 4,2,3,0 %; literal IPFINS$S_F9_34_36 = 3; macro IPFINS$V_F9_OPCODE = 4,5,4,0 %; literal IPFINS$S_F9_OPCODE = 4; macro IPFINS$Q_F9 = 0,0,0,0 %; literal IPFINS$S_F9 = 8; ! ! F10: Convert Floating-point to Fixed-point ! literal IPFINS$M_F10_QP = %X'3F'; literal IPFINS$M_F10_F1 = %X'1FC0'; literal IPFINS$M_F10_F2 = %X'FE000'; literal IPFINS$M_F10_20_26 = %X'7F00000'; literal IPFINS$M_F10_X6 = %X'1F8000000'; literal IPFINS$M_F10_X = %X'200000000'; literal IPFINS$M_F10_SF = %X'C00000000'; literal IPFINS$M_F10_36 = %X'1000000000'; literal IPFINS$M_F10_OPCODE = %X'1E000000000'; literal IPFINS$M_F10_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F10_FORMAT = 8; macro IPFINS$V_F10_QP = 0,0,6,0 %; literal IPFINS$S_F10_QP = 6; macro IPFINS$V_F10_F1 = 0,6,7,0 %; literal IPFINS$S_F10_F1 = 7; macro IPFINS$V_F10_F2 = 0,13,7,0 %; literal IPFINS$S_F10_F2 = 7; macro IPFINS$V_F10_20_26 = 0,20,7,0 %; literal IPFINS$S_F10_20_26 = 7; macro IPFINS$V_F10_X6 = 0,27,6,0 %; literal IPFINS$S_F10_X6 = 6; macro IPFINS$V_F10_X = 4,1,1,0 %; macro IPFINS$V_F10_SF = 4,2,2,0 %; literal IPFINS$S_F10_SF = 2; macro IPFINS$V_F10_36 = 4,4,1,0 %; macro IPFINS$V_F10_OPCODE = 4,5,4,0 %; literal IPFINS$S_F10_OPCODE = 4; macro IPFINS$Q_F10 = 0,0,0,0 %; literal IPFINS$S_F10 = 8; ! ! F11: Convert Fixed-point to Floating-point ! literal IPFINS$M_F11_QP = %X'3F'; literal IPFINS$M_F11_F1 = %X'1FC0'; literal IPFINS$M_F11_F2 = %X'FE000'; literal IPFINS$M_F11_20_26 = %X'7F00000'; literal IPFINS$M_F11_X6 = %X'1F8000000'; literal IPFINS$M_F11_X = %X'200000000'; literal IPFINS$M_F11_34_36 = %X'1C00000000'; literal IPFINS$M_F11_OPCODE = %X'1E000000000'; literal IPFINS$M_F11_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F11_FORMAT = 8; macro IPFINS$V_F11_QP = 0,0,6,0 %; literal IPFINS$S_F11_QP = 6; macro IPFINS$V_F11_F1 = 0,6,7,0 %; literal IPFINS$S_F11_F1 = 7; macro IPFINS$V_F11_F2 = 0,13,7,0 %; literal IPFINS$S_F11_F2 = 7; macro IPFINS$V_F11_20_26 = 0,20,7,0 %; literal IPFINS$S_F11_20_26 = 7; macro IPFINS$V_F11_X6 = 0,27,6,0 %; literal IPFINS$S_F11_X6 = 6; macro IPFINS$V_F11_X = 4,1,1,0 %; macro IPFINS$V_F11_34_36 = 4,2,3,0 %; literal IPFINS$S_F11_34_36 = 3; macro IPFINS$V_F11_OPCODE = 4,5,4,0 %; literal IPFINS$S_F11_OPCODE = 4; macro IPFINS$Q_F11 = 0,0,0,0 %; literal IPFINS$S_F11 = 8; ! ! F12: Floating-point Set Controls ! literal IPFINS$M_F12_QP = %X'3F'; literal IPFINS$M_F12_6_12 = %X'1FC0'; literal IPFINS$M_F12_AMASK7B = %X'FE000'; literal IPFINS$M_F12_OMASK7C = %X'7F00000'; literal IPFINS$M_F12_X6 = %X'1F8000000'; literal IPFINS$M_F12_X = %X'200000000'; literal IPFINS$M_F12_SF = %X'C00000000'; literal IPFINS$M_F12_36 = %X'1000000000'; literal IPFINS$M_F12_OPCODE = %X'1E000000000'; literal IPFINS$M_F12_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F12_FORMAT = 8; macro IPFINS$V_F12_QP = 0,0,6,0 %; literal IPFINS$S_F12_QP = 6; macro IPFINS$V_F12_6_12 = 0,6,7,0 %; literal IPFINS$S_F12_6_12 = 7; macro IPFINS$V_F12_AMASK7B = 0,13,7,0 %; literal IPFINS$S_F12_AMASK7B = 7; macro IPFINS$V_F12_OMASK7C = 0,20,7,0 %; literal IPFINS$S_F12_OMASK7C = 7; macro IPFINS$V_F12_X6 = 0,27,6,0 %; literal IPFINS$S_F12_X6 = 6; macro IPFINS$V_F12_X = 4,1,1,0 %; macro IPFINS$V_F12_SF = 4,2,2,0 %; literal IPFINS$S_F12_SF = 2; macro IPFINS$V_F12_36 = 4,4,1,0 %; macro IPFINS$V_F12_OPCODE = 4,5,4,0 %; literal IPFINS$S_F12_OPCODE = 4; macro IPFINS$Q_F12 = 0,0,0,0 %; literal IPFINS$S_F12 = 8; ! ! F13: Floating-point Clear Flags ! literal IPFINS$M_F13_QP = %X'3F'; literal IPFINS$M_F13_6_26 = %X'7FFFFC0'; literal IPFINS$M_F13_X6 = %X'1F8000000'; literal IPFINS$M_F13_X = %X'200000000'; literal IPFINS$M_F13_SF = %X'C00000000'; literal IPFINS$M_F13_36 = %X'1000000000'; literal IPFINS$M_F13_OPCODE = %X'1E000000000'; literal IPFINS$M_F13_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F13_FORMAT = 8; macro IPFINS$V_F13_QP = 0,0,6,0 %; literal IPFINS$S_F13_QP = 6; macro IPFINS$V_F13_6_26 = 0,6,21,0 %; literal IPFINS$S_F13_6_26 = 21; macro IPFINS$V_F13_X6 = 0,27,6,0 %; literal IPFINS$S_F13_X6 = 6; macro IPFINS$V_F13_X = 4,1,1,0 %; macro IPFINS$V_F13_SF = 4,2,2,0 %; literal IPFINS$S_F13_SF = 2; macro IPFINS$V_F13_36 = 4,4,1,0 %; macro IPFINS$V_F13_OPCODE = 4,5,4,0 %; literal IPFINS$S_F13_OPCODE = 4; macro IPFINS$Q_F13 = 0,0,0,0 %; literal IPFINS$S_F13 = 8; ! ! F14: Floating-point Check Flags ! literal IPFINS$M_F14_QP = %X'3F'; literal IPFINS$M_F14_IMM20A = %X'3FFFFC0'; literal IPFINS$M_F14_26 = %X'4000000'; literal IPFINS$M_F14_X6 = %X'1F8000000'; literal IPFINS$M_F14_X = %X'200000000'; literal IPFINS$M_F14_SF = %X'C00000000'; literal IPFINS$M_F14_S = %X'1000000000'; literal IPFINS$M_F14_OPCODE = %X'1E000000000'; literal IPFINS$M_F14_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F14_FORMAT = 8; macro IPFINS$V_F14_QP = 0,0,6,0 %; literal IPFINS$S_F14_QP = 6; macro IPFINS$V_F14_IMM20A = 0,6,20,0 %; literal IPFINS$S_F14_IMM20A = 20; macro IPFINS$V_F14_26 = 0,26,1,0 %; macro IPFINS$V_F14_X6 = 0,27,6,0 %; literal IPFINS$S_F14_X6 = 6; macro IPFINS$V_F14_X = 4,1,1,0 %; macro IPFINS$V_F14_SF = 4,2,2,0 %; literal IPFINS$S_F14_SF = 2; macro IPFINS$V_F14_S = 4,4,1,1 %; macro IPFINS$V_F14_OPCODE = 4,5,4,0 %; literal IPFINS$S_F14_OPCODE = 4; macro IPFINS$Q_F14 = 0,0,0,0 %; literal IPFINS$S_F14 = 8; ! ! F15: Break (F-Unit) ! literal IPFINS$M_F15_QP = %X'3F'; literal IPFINS$M_F15_IMM20A = %X'3FFFFC0'; literal IPFINS$M_F15_26 = %X'4000000'; literal IPFINS$M_F15_X6 = %X'1F8000000'; literal IPFINS$M_F15_X = %X'200000000'; literal IPFINS$M_F15_34_35 = %X'C00000000'; literal IPFINS$M_F15_I = %X'1000000000'; literal IPFINS$M_F15_OPCODE = %X'1E000000000'; literal IPFINS$M_F15_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F15_FORMAT = 8; macro IPFINS$V_F15_QP = 0,0,6,0 %; literal IPFINS$S_F15_QP = 6; macro IPFINS$V_F15_IMM20A = 0,6,20,0 %; literal IPFINS$S_F15_IMM20A = 20; macro IPFINS$V_F15_26 = 0,26,1,0 %; macro IPFINS$V_F15_X6 = 0,27,6,0 %; literal IPFINS$S_F15_X6 = 6; macro IPFINS$V_F15_X = 4,1,1,0 %; macro IPFINS$V_F15_34_35 = 4,2,2,0 %; literal IPFINS$S_F15_34_35 = 2; macro IPFINS$V_F15_I = 4,4,1,0 %; macro IPFINS$V_F15_OPCODE = 4,5,4,0 %; literal IPFINS$S_F15_OPCODE = 4; macro IPFINS$Q_F15 = 0,0,0,0 %; literal IPFINS$S_F15 = 8; ! ! F16: Nop/Hint (F-Unit) ! literal IPFINS$M_F16_QP = %X'3F'; literal IPFINS$M_F16_IMM20A = %X'3FFFFC0'; literal IPFINS$M_F16_Y = %X'4000000'; literal IPFINS$M_F16_X6 = %X'1F8000000'; literal IPFINS$M_F16_X = %X'200000000'; literal IPFINS$M_F16_34_35 = %X'C00000000'; literal IPFINS$M_F16_I = %X'1000000000'; literal IPFINS$M_F16_OPCODE = %X'1E000000000'; literal IPFINS$M_F16_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_F16_FORMAT = 8; macro IPFINS$V_F16_QP = 0,0,6,0 %; literal IPFINS$S_F16_QP = 6; macro IPFINS$V_F16_IMM20A = 0,6,20,0 %; literal IPFINS$S_F16_IMM20A = 20; macro IPFINS$V_F16_Y = 0,26,1,0 %; macro IPFINS$V_F16_X6 = 0,27,6,0 %; literal IPFINS$S_F16_X6 = 6; macro IPFINS$V_F16_X = 4,1,1,0 %; macro IPFINS$V_F16_34_35 = 4,2,2,0 %; literal IPFINS$S_F16_34_35 = 2; macro IPFINS$V_F16_I = 4,4,1,0 %; macro IPFINS$V_F16_OPCODE = 4,5,4,0 %; literal IPFINS$S_F16_OPCODE = 4; macro IPFINS$Q_F16 = 0,0,0,0 %; literal IPFINS$S_F16 = 8; ! ! X-Unit Formats and Literal Extensions ! ! ! X1: Break (X-Unit) ! literal IPFINS$M_X1_QP = %X'3F'; literal IPFINS$M_X1_IMM20A = %X'3FFFFC0'; literal IPFINS$M_X1_26 = %X'4000000'; literal IPFINS$M_X1_X6 = %X'1F8000000'; literal IPFINS$M_X1_X3 = %X'E00000000'; literal IPFINS$M_X1_I = %X'1000000000'; literal IPFINS$M_X1_OPCODE = %X'1E000000000'; literal IPFINS$M_X1_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_X1_FORMAT = 8; macro IPFINS$V_X1_QP = 0,0,6,0 %; literal IPFINS$S_X1_QP = 6; macro IPFINS$V_X1_IMM20A = 0,6,20,0 %; literal IPFINS$S_X1_IMM20A = 20; macro IPFINS$V_X1_26 = 0,26,1,0 %; macro IPFINS$V_X1_X6 = 0,27,6,0 %; literal IPFINS$S_X1_X6 = 6; macro IPFINS$V_X1_X3 = 4,1,3,0 %; literal IPFINS$S_X1_X3 = 3; macro IPFINS$V_X1_I = 4,4,1,0 %; macro IPFINS$V_X1_OPCODE = 4,5,4,0 %; literal IPFINS$S_X1_OPCODE = 4; macro IPFINS$Q_X1 = 0,0,0,0 %; literal IPFINS$S_X1 = 8; ! ! X2: Move Long Immediate(64) ! literal IPFINS$M_X2_QP = %X'3F'; literal IPFINS$M_X2_R1 = %X'1FC0'; literal IPFINS$M_X2_IMM7B = %X'FE000'; literal IPFINS$M_X2_VC = %X'100000'; literal IPFINS$M_X2_IC = %X'200000'; literal IPFINS$M_X2_IMM5C = %X'7C00000'; literal IPFINS$M_X2_IMM9D = %X'FF8000000'; literal IPFINS$M_X2_I = %X'1000000000'; literal IPFINS$M_X2_OPCODE = %X'1E000000000'; literal IPFINS$M_X2_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_X2_FORMAT = 8; macro IPFINS$V_X2_QP = 0,0,6,0 %; literal IPFINS$S_X2_QP = 6; macro IPFINS$V_X2_R1 = 0,6,7,0 %; literal IPFINS$S_X2_R1 = 7; macro IPFINS$V_X2_IMM7B = 0,13,7,0 %; literal IPFINS$S_X2_IMM7B = 7; macro IPFINS$V_X2_VC = 0,20,1,0 %; macro IPFINS$V_X2_IC = 0,21,1,0 %; macro IPFINS$V_X2_IMM5C = 0,22,5,0 %; literal IPFINS$S_X2_IMM5C = 5; macro IPFINS$V_X2_IMM9D = 0,27,9,0 %; literal IPFINS$S_X2_IMM9D = 9; macro IPFINS$V_X2_I = 4,4,1,0 %; macro IPFINS$V_X2_OPCODE = 4,5,4,0 %; literal IPFINS$S_X2_OPCODE = 4; macro IPFINS$Q_X2 = 0,0,0,0 %; literal IPFINS$S_X2 = 8; ! ! X3: Long Branch ! literal IPFINS$M_X3_QP = %X'3F'; literal IPFINS$M_X3_BTYPE = %X'1C0'; literal IPFINS$M_X3_9_11 = %X'E00'; literal IPFINS$M_X3_P = %X'1000'; literal IPFINS$M_X3_IMM20B = %X'1FFFFE000'; literal IPFINS$M_X3_WH = %X'600000000'; literal IPFINS$M_X3_D = %X'800000000'; literal IPFINS$M_X3_I = %X'1000000000'; literal IPFINS$M_X3_OPCODE = %X'1E000000000'; literal IPFINS$M_X3_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_X3_FORMAT = 8; macro IPFINS$V_X3_QP = 0,0,6,0 %; literal IPFINS$S_X3_QP = 6; macro IPFINS$V_X3_BTYPE = 0,6,3,0 %; literal IPFINS$S_X3_BTYPE = 3; macro IPFINS$V_X3_9_11 = 0,9,3,0 %; literal IPFINS$S_X3_9_11 = 3; macro IPFINS$V_X3_P = 0,12,1,0 %; macro IPFINS$V_X3_IMM20B = 0,13,20,0 %; literal IPFINS$S_X3_IMM20B = 20; macro IPFINS$V_X3_WH = 4,1,2,0 %; literal IPFINS$S_X3_WH = 2; macro IPFINS$V_X3_D = 4,3,1,0 %; macro IPFINS$V_X3_I = 4,4,1,0 %; macro IPFINS$V_X3_OPCODE = 4,5,4,0 %; literal IPFINS$S_X3_OPCODE = 4; macro IPFINS$Q_X3 = 0,0,0,0 %; literal IPFINS$S_X3 = 8; ! ! X4: Long Call ! literal IPFINS$M_X4_QP = %X'3F'; literal IPFINS$M_X4_B1 = %X'1C0'; literal IPFINS$M_X4_9_11 = %X'E00'; literal IPFINS$M_X4_P = %X'1000'; literal IPFINS$M_X4_IMM20B = %X'1FFFFE000'; literal IPFINS$M_X4_WH = %X'600000000'; literal IPFINS$M_X4_D = %X'800000000'; literal IPFINS$M_X4_I = %X'1000000000'; literal IPFINS$M_X4_OPCODE = %X'1E000000000'; literal IPFINS$M_X4_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_X4_FORMAT = 8; macro IPFINS$V_X4_QP = 0,0,6,0 %; literal IPFINS$S_X4_QP = 6; macro IPFINS$V_X4_B1 = 0,6,3,0 %; literal IPFINS$S_X4_B1 = 3; macro IPFINS$V_X4_9_11 = 0,9,3,0 %; literal IPFINS$S_X4_9_11 = 3; macro IPFINS$V_X4_P = 0,12,1,0 %; macro IPFINS$V_X4_IMM20B = 0,13,20,0 %; literal IPFINS$S_X4_IMM20B = 20; macro IPFINS$V_X4_WH = 4,1,2,0 %; literal IPFINS$S_X4_WH = 2; macro IPFINS$V_X4_D = 4,3,1,0 %; macro IPFINS$V_X4_I = 4,4,1,0 %; macro IPFINS$V_X4_OPCODE = 4,5,4,0 %; literal IPFINS$S_X4_OPCODE = 4; macro IPFINS$Q_X4 = 0,0,0,0 %; literal IPFINS$S_X4 = 8; ! ! X5: Nop/Hint (X-Unit) ! literal IPFINS$M_X5_QP = %X'3F'; literal IPFINS$M_X5_IMM20A = %X'3FFFFC0'; literal IPFINS$M_X5_Y = %X'4000000'; literal IPFINS$M_X5_X6 = %X'1F8000000'; literal IPFINS$M_X5_X3 = %X'E00000000'; literal IPFINS$M_X5_I = %X'1000000000'; literal IPFINS$M_X5_OPCODE = %X'1E000000000'; literal IPFINS$M_X5_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_X5_FORMAT = 8; macro IPFINS$V_X5_QP = 0,0,6,0 %; literal IPFINS$S_X5_QP = 6; macro IPFINS$V_X5_IMM20A = 0,6,20,0 %; literal IPFINS$S_X5_IMM20A = 20; macro IPFINS$V_X5_Y = 0,26,1,0 %; macro IPFINS$V_X5_X6 = 0,27,6,0 %; literal IPFINS$S_X5_X6 = 6; macro IPFINS$V_X5_X3 = 4,1,3,0 %; literal IPFINS$S_X5_X3 = 3; macro IPFINS$V_X5_I = 4,4,1,0 %; macro IPFINS$V_X5_OPCODE = 4,5,4,0 %; literal IPFINS$S_X5_OPCODE = 4; macro IPFINS$Q_X5 = 0,0,0,0 %; literal IPFINS$S_X5 = 8; ! ! L125: Literal Extensions for X1, X2, X5 ! literal IPFINS$M_L125_IMM41 = %X'1FFFFFFFFFF'; literal IPFINS$M_L125_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_L125_FORMAT = 8; macro IPFINS$V_L125_IMM41 = 0,0,41,0 %; literal IPFINS$S_L125_IMM41 = 41; macro IPFINS$Q_L125 = 0,0,0,0 %; literal IPFINS$S_L125 = 8; ! ! L34: Literal Extensions for X3, X4 ! literal IPFINS$M_L34_0_1 = %X'3'; literal IPFINS$M_L34_IMM39 = %X'1FFFFFFFFFC'; literal IPFINS$M_L34_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_L34_FORMAT = 8; macro IPFINS$V_L34_0_1 = 0,0,2,0 %; literal IPFINS$S_L34_0_1 = 2; macro IPFINS$V_L34_IMM39 = 0,2,39,0 %; literal IPFINS$S_L34_IMM39 = 39; macro IPFINS$Q_L34 = 0,0,0,0 %; literal IPFINS$S_L34 = 8; ! ! Multi-format overlays - OPnnnx, where n = hex opcode(s) and x = unit ! (Intended only for use by [SDA]IPF_DECODE.C). ! ! ! OP8A: A-Unit Opcode 8 - A1-4,A9-10 ! literal IPFINS$M_OP8A_0_26 = %X'7FFFFFF'; literal IPFINS$M_OP8A_X2B = %X'18000000'; literal IPFINS$M_OP8A_X4 = %X'1E0000000'; literal IPFINS$M_OP8A_VE_ZB = %X'200000000'; literal IPFINS$M_OP8A_X2A = %X'C00000000'; literal IPFINS$M_OP8A_ZA = %X'1000000000'; literal IPFINS$M_OP8A_OPCODE = %X'1E000000000'; literal IPFINS$M_OP8A_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OP8A_OVERLAY = 8; macro IPFINS$V_OP8A_0_26 = 0,0,27,0 %; literal IPFINS$S_OP8A_0_26 = 27; macro IPFINS$V_OP8A_X2B = 0,27,2,0 %; literal IPFINS$S_OP8A_X2B = 2; macro IPFINS$V_OP8A_X4 = 0,29,4,0 %; literal IPFINS$S_OP8A_X4 = 4; macro IPFINS$V_OP8A_VE_ZB = 4,1,1,0 %; macro IPFINS$V_OP8A_X2A = 4,2,2,0 %; literal IPFINS$S_OP8A_X2A = 2; macro IPFINS$V_OP8A_ZA = 4,4,1,0 %; macro IPFINS$V_OP8A_OPCODE = 4,5,4,0 %; literal IPFINS$S_OP8A_OPCODE = 4; macro IPFINS$Q_OP8A = 0,0,0,0 %; literal IPFINS$S_OP8A = 8; ! ! OPCDEA: A-Unit Opcodes C,D,E - A6-8 ! literal IPFINS$M_OPCDEA_0_33 = %X'3FFFFFFFF'; literal IPFINS$M_OPCDEA_X2 = %X'C00000000'; literal IPFINS$M_OPCDEA_TB = %X'1000000000'; literal IPFINS$M_OPCDEA_OPCODE = %X'1E000000000'; literal IPFINS$M_OPCDEA_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OPCDEA_OVERLAY = 8; macro IPFINS$V_OPCDEA_0_33 = 0,0,34,0 %; literal IPFINS$S_OPCDEA_0_33 = 34; macro IPFINS$V_OPCDEA_X2 = 4,2,2,0 %; literal IPFINS$S_OPCDEA_X2 = 2; macro IPFINS$V_OPCDEA_TB = 4,4,1,0 %; macro IPFINS$V_OPCDEA_OPCODE = 4,5,4,0 %; literal IPFINS$S_OPCDEA_OPCODE = 4; macro IPFINS$Q_OPCDEA = 0,0,0,0 %; literal IPFINS$S_OPCDEA = 8; ! ! OP0I: I-Unit Opcode 0 - I18-29 ! literal IPFINS$M_OP0I_0_26 = %X'7FFFFFF'; literal IPFINS$M_OP0I_X6 = %X'1F8000000'; literal IPFINS$M_OP0I_X3 = %X'E00000000'; literal IPFINS$M_OP0I_36 = %X'1000000000'; literal IPFINS$M_OP0I_OPCODE = %X'1E000000000'; literal IPFINS$M_OP0I_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OP0I_OVERLAY = 8; macro IPFINS$V_OP0I_0_26 = 0,0,27,0 %; literal IPFINS$S_OP0I_0_26 = 27; macro IPFINS$V_OP0I_X6 = 0,27,6,0 %; literal IPFINS$S_OP0I_X6 = 6; macro IPFINS$V_OP0I_X3 = 4,1,3,0 %; literal IPFINS$S_OP0I_X3 = 3; macro IPFINS$V_OP0I_36 = 4,4,1,0 %; macro IPFINS$V_OP0I_OPCODE = 4,5,4,0 %; literal IPFINS$S_OP0I_OPCODE = 4; macro IPFINS$Q_OP0I = 0,0,0,0 %; literal IPFINS$S_OP0I = 8; ! ! OP5I: I-Unit Opcode 5 - I10-14,I16-17,I30 ! literal IPFINS$M_OP5I_0_12 = %X'1FFF'; literal IPFINS$M_OP5I_Y_13 = %X'2000'; literal IPFINS$M_OP5I_14_18 = %X'7C000'; literal IPFINS$M_OP5I_X_19 = %X'80000'; literal IPFINS$M_OP5I_20_25 = %X'3F00000'; literal IPFINS$M_OP5I_Y_26 = %X'4000000'; literal IPFINS$M_OP5I_27_32 = %X'1F8000000'; literal IPFINS$M_OP5I_X_33 = %X'200000000'; literal IPFINS$M_OP5I_X2 = %X'C00000000'; literal IPFINS$M_OP5I_36 = %X'1000000000'; literal IPFINS$M_OP5I_OPCODE = %X'1E000000000'; literal IPFINS$M_OP5I_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OP5I_OVERLAY = 8; macro IPFINS$V_OP5I_0_12 = 0,0,13,0 %; literal IPFINS$S_OP5I_0_12 = 13; macro IPFINS$V_OP5I_Y_13 = 0,13,1,0 %; macro IPFINS$V_OP5I_14_18 = 0,14,5,0 %; literal IPFINS$S_OP5I_14_18 = 5; macro IPFINS$V_OP5I_X_19 = 0,19,1,0 %; macro IPFINS$V_OP5I_20_25 = 0,20,6,0 %; literal IPFINS$S_OP5I_20_25 = 6; macro IPFINS$V_OP5I_Y_26 = 0,26,1,0 %; macro IPFINS$V_OP5I_27_32 = 0,27,6,0 %; literal IPFINS$S_OP5I_27_32 = 6; macro IPFINS$V_OP5I_X_33 = 4,1,1,0 %; macro IPFINS$V_OP5I_X2 = 4,2,2,0 %; literal IPFINS$S_OP5I_X2 = 2; macro IPFINS$V_OP5I_36 = 4,4,1,0 %; macro IPFINS$V_OP5I_OPCODE = 4,5,4,0 %; literal IPFINS$S_OP5I_OPCODE = 4; macro IPFINS$Q_OP5I = 0,0,0,0 %; literal IPFINS$S_OP5I = 8; ! ! OP7I: I-Unit Opcode 7 - I1-9 ! literal IPFINS$M_OP7I_0_27 = %X'FFFFFFF'; literal IPFINS$M_OP7I_X2B = %X'30000000'; literal IPFINS$M_OP7I_X2C = %X'C0000000'; literal IPFINS$M_OP7I_VE = %X'100000000'; literal IPFINS$M_OP7I_ZB = %X'200000000'; literal IPFINS$M_OP7I_X2A = %X'C00000000'; literal IPFINS$M_OP7I_ZA = %X'1000000000'; literal IPFINS$M_OP7I_OPCODE = %X'1E000000000'; literal IPFINS$M_OP7I_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OP7I_OVERLAY = 8; macro IPFINS$V_OP7I_0_27 = 0,0,28,0 %; literal IPFINS$S_OP7I_0_27 = 28; macro IPFINS$V_OP7I_X2B = 0,28,2,0 %; literal IPFINS$S_OP7I_X2B = 2; macro IPFINS$V_OP7I_X2C = 0,30,2,0 %; literal IPFINS$S_OP7I_X2C = 2; macro IPFINS$V_OP7I_VE = 4,0,1,0 %; macro IPFINS$V_OP7I_ZB = 4,1,1,0 %; macro IPFINS$V_OP7I_X2A = 4,2,2,0 %; literal IPFINS$S_OP7I_X2A = 2; macro IPFINS$V_OP7I_ZA = 4,4,1,0 %; macro IPFINS$V_OP7I_OPCODE = 4,5,4,0 %; literal IPFINS$S_OP7I_OPCODE = 4; macro IPFINS$Q_OP7I = 0,0,0,0 %; literal IPFINS$S_OP7I = 8; ! ! OP0M: M-Unit Opcode 0 - M22-27,M30,M37,M44,M48 ! literal IPFINS$M_OP0M_0_26 = %X'7FFFFFF'; literal IPFINS$M_OP0M_X4 = %X'78000000'; literal IPFINS$M_OP0M_X2 = %X'180000000'; literal IPFINS$M_OP0M_X3 = %X'E00000000'; literal IPFINS$M_OP0M_36 = %X'1000000000'; literal IPFINS$M_OP0M_OPCODE = %X'1E000000000'; literal IPFINS$M_OP0M_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OP0M_OVERLAY = 8; macro IPFINS$V_OP0M_0_26 = 0,0,27,0 %; literal IPFINS$S_OP0M_0_26 = 27; macro IPFINS$V_OP0M_X4 = 0,27,4,0 %; literal IPFINS$S_OP0M_X4 = 4; macro IPFINS$V_OP0M_X2 = 0,31,2,0 %; literal IPFINS$S_OP0M_X2 = 2; macro IPFINS$V_OP0M_X3 = 4,1,3,0 %; literal IPFINS$S_OP0M_X3 = 3; macro IPFINS$V_OP0M_36 = 4,4,1,0 %; macro IPFINS$V_OP0M_OPCODE = 4,5,4,0 %; literal IPFINS$S_OP0M_OPCODE = 4; macro IPFINS$Q_OP0M = 0,0,0,0 %; literal IPFINS$S_OP0M = 8; ! ! OP1M: M-Unit Opcode 1 - M20-21,M28-29,M31-36,M38-43,M45-47 ! literal IPFINS$M_OP1M_0_26 = %X'7FFFFFF'; literal IPFINS$M_OP1M_X6 = %X'1F8000000'; literal IPFINS$M_OP1M_X3 = %X'E00000000'; literal IPFINS$M_OP1M_36 = %X'1000000000'; literal IPFINS$M_OP1M_OPCODE = %X'1E000000000'; literal IPFINS$M_OP1M_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OP1M_OVERLAY = 8; macro IPFINS$V_OP1M_0_26 = 0,0,27,0 %; literal IPFINS$S_OP1M_0_26 = 27; macro IPFINS$V_OP1M_X6 = 0,27,6,0 %; literal IPFINS$S_OP1M_X6 = 6; macro IPFINS$V_OP1M_X3 = 4,1,3,0 %; literal IPFINS$S_OP1M_X3 = 3; macro IPFINS$V_OP1M_36 = 4,4,1,0 %; macro IPFINS$V_OP1M_OPCODE = 4,5,4,0 %; literal IPFINS$S_OP1M_OPCODE = 4; macro IPFINS$Q_OP1M = 0,0,0,0 %; literal IPFINS$S_OP1M = 8; ! ! OP4M: M-Unit Opcode 4 - M1-2,M4,M16-17,M19 ! literal IPFINS$M_OP4M_0_26 = %X'7FFFFFF'; literal IPFINS$M_OP4M_X = %X'8000000'; literal IPFINS$M_OP4M_28_29 = %X'30000000'; literal IPFINS$M_OP4M_X6 = %X'FC0000000'; literal IPFINS$M_OP4M_M = %X'1000000000'; literal IPFINS$M_OP4M_OPCODE = %X'1E000000000'; literal IPFINS$M_OP4M_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OP4M_OVERLAY = 8; macro IPFINS$V_OP4M_0_26 = 0,0,27,0 %; literal IPFINS$S_OP4M_0_26 = 27; macro IPFINS$V_OP4M_X = 0,27,1,0 %; macro IPFINS$V_OP4M_28_29 = 0,28,2,0 %; literal IPFINS$S_OP4M_28_29 = 2; macro IPFINS$V_OP4M_X6 = 0,30,6,0 %; literal IPFINS$S_OP4M_X6 = 6; macro IPFINS$V_OP4M_M = 4,4,1,0 %; macro IPFINS$V_OP4M_OPCODE = 4,5,4,0 %; literal IPFINS$S_OP4M_OPCODE = 4; macro IPFINS$Q_OP4M = 0,0,0,0 %; literal IPFINS$S_OP4M = 8; ! ! OP5M: M-Unit Opcode 5 - M3,M5 ! literal IPFINS$M_OP5M_0_29 = %X'3FFFFFFF'; literal IPFINS$M_OP5M_X6 = %X'FC0000000'; literal IPFINS$M_OP5M_36 = %X'1000000000'; literal IPFINS$M_OP5M_OPCODE = %X'1E000000000'; literal IPFINS$M_OP5M_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OP5M_OVERLAY = 8; macro IPFINS$V_OP5M_0_29 = 0,0,30,0 %; literal IPFINS$S_OP5M_0_29 = 30; macro IPFINS$V_OP5M_X6 = 0,30,6,0 %; literal IPFINS$S_OP5M_X6 = 6; macro IPFINS$V_OP5M_36 = 4,4,1,0 %; macro IPFINS$V_OP5M_OPCODE = 4,5,4,0 %; literal IPFINS$S_OP5M_OPCODE = 4; macro IPFINS$Q_OP5M = 0,0,0,0 %; literal IPFINS$S_OP5M = 8; ! ! OP6M: M-Unit Opcode 6 - M6-7,M9,M11-14,M18 ! literal IPFINS$M_OP6M_0_26 = %X'7FFFFFF'; literal IPFINS$M_OP6M_X = %X'8000000'; literal IPFINS$M_OP6M_28_29 = %X'30000000'; literal IPFINS$M_OP6M_X6 = %X'FC0000000'; literal IPFINS$M_OP6M_M = %X'1000000000'; literal IPFINS$M_OP6M_OPCODE = %X'1E000000000'; literal IPFINS$M_OP6M_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OP6M_OVERLAY = 8; macro IPFINS$V_OP6M_0_26 = 0,0,27,0 %; literal IPFINS$S_OP6M_0_26 = 27; macro IPFINS$V_OP6M_X = 0,27,1,0 %; macro IPFINS$V_OP6M_28_29 = 0,28,2,0 %; literal IPFINS$S_OP6M_28_29 = 2; macro IPFINS$V_OP6M_X6 = 0,30,6,0 %; literal IPFINS$S_OP6M_X6 = 6; macro IPFINS$V_OP6M_M = 4,4,1,0 %; macro IPFINS$V_OP6M_OPCODE = 4,5,4,0 %; literal IPFINS$S_OP6M_OPCODE = 4; macro IPFINS$Q_OP6M = 0,0,0,0 %; literal IPFINS$S_OP6M = 8; ! ! OP7M: M-Unit Opcode 7 - M8,M10,M15 ! literal IPFINS$M_OP7M_0_29 = %X'3FFFFFFF'; literal IPFINS$M_OP7M_X6 = %X'FC0000000'; literal IPFINS$M_OP7M_36 = %X'1000000000'; literal IPFINS$M_OP7M_OPCODE = %X'1E000000000'; literal IPFINS$M_OP7M_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OP7M_OVERLAY = 8; macro IPFINS$V_OP7M_0_29 = 0,0,30,0 %; literal IPFINS$S_OP7M_0_29 = 30; macro IPFINS$V_OP7M_X6 = 0,30,6,0 %; literal IPFINS$S_OP7M_X6 = 6; macro IPFINS$V_OP7M_36 = 4,4,1,0 %; macro IPFINS$V_OP7M_OPCODE = 4,5,4,0 %; literal IPFINS$S_OP7M_OPCODE = 4; macro IPFINS$Q_OP7M = 0,0,0,0 %; literal IPFINS$S_OP7M = 8; ! ! OP02B: B-Unit Opcode 0,2 - B4,B7-9 ! literal IPFINS$M_OP02B_0_5 = %X'3F'; literal IPFINS$M_OP02B_BTYPE = %X'1C0'; literal IPFINS$M_OP02B_9_26 = %X'7FFFE00'; literal IPFINS$M_OP02B_X6 = %X'1F8000000'; literal IPFINS$M_OP02B_33_36 = %X'1E00000000'; literal IPFINS$M_OP02B_OPCODE = %X'1E000000000'; literal IPFINS$M_OP02B_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OP02B_OVERLAY = 8; macro IPFINS$V_OP02B_0_5 = 0,0,6,0 %; literal IPFINS$S_OP02B_0_5 = 6; macro IPFINS$V_OP02B_BTYPE = 0,6,3,0 %; literal IPFINS$S_OP02B_BTYPE = 3; macro IPFINS$V_OP02B_9_26 = 0,9,18,0 %; literal IPFINS$S_OP02B_9_26 = 18; macro IPFINS$V_OP02B_X6 = 0,27,6,0 %; literal IPFINS$S_OP02B_X6 = 6; macro IPFINS$V_OP02B_33_36 = 4,1,4,0 %; literal IPFINS$S_OP02B_33_36 = 4; macro IPFINS$V_OP02B_OPCODE = 4,5,4,0 %; literal IPFINS$S_OP02B_OPCODE = 4; macro IPFINS$Q_OP02B = 0,0,0,0 %; literal IPFINS$S_OP02B = 8; ! ! OP4B: B-Unit Opcode 4 - B1-2 ! literal IPFINS$M_OP4B_0_5 = %X'3F'; literal IPFINS$M_OP4B_BTYPE = %X'1C0'; literal IPFINS$M_OP4B_9_36 = %X'1FFFFFFE00'; literal IPFINS$M_OP4B_OPCODE = %X'1E000000000'; literal IPFINS$M_OP4B_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OP4B_OVERLAY = 8; macro IPFINS$V_OP4B_0_5 = 0,0,6,0 %; literal IPFINS$S_OP4B_0_5 = 6; macro IPFINS$V_OP4B_BTYPE = 0,6,3,0 %; literal IPFINS$S_OP4B_BTYPE = 3; macro IPFINS$V_OP4B_9_36 = 0,9,28,0 %; literal IPFINS$S_OP4B_9_36 = 28; macro IPFINS$V_OP4B_OPCODE = 4,5,4,0 %; literal IPFINS$S_OP4B_OPCODE = 4; macro IPFINS$Q_OP4B = 0,0,0,0 %; literal IPFINS$S_OP4B = 8; ! ! OP01F: F-Unit Opcodes 0,1 - F6-16 ! literal IPFINS$M_OP01F_0_26 = %X'7FFFFFF'; literal IPFINS$M_OP01F_X6 = %X'1F8000000'; literal IPFINS$M_OP01F_X = %X'200000000'; literal IPFINS$M_OP01F_34_35 = %X'C00000000'; literal IPFINS$M_OP01F_Q = %X'1000000000'; literal IPFINS$M_OP01F_OPCODE = %X'1E000000000'; literal IPFINS$M_OP01F_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OP01F_OVERLAY = 8; macro IPFINS$V_OP01F_0_26 = 0,0,27,0 %; literal IPFINS$S_OP01F_0_26 = 27; macro IPFINS$V_OP01F_X6 = 0,27,6,0 %; literal IPFINS$S_OP01F_X6 = 6; macro IPFINS$V_OP01F_X = 4,1,1,0 %; macro IPFINS$V_OP01F_34_35 = 4,2,2,0 %; literal IPFINS$S_OP01F_34_35 = 2; macro IPFINS$V_OP01F_Q = 4,4,1,0 %; macro IPFINS$V_OP01F_OPCODE = 4,5,4,0 %; literal IPFINS$S_OP01F_OPCODE = 4; macro IPFINS$Q_OP01F = 0,0,0,0 %; literal IPFINS$S_OP01F = 8; ! ! OPEF: F-Unit Opcode E - F2-3 ! literal IPFINS$M_OPEF_0_33 = %X'3FFFFFFFF'; literal IPFINS$M_OPEF_X2 = %X'C00000000'; literal IPFINS$M_OPEF_X = %X'1000000000'; literal IPFINS$M_OPEF_OPCODE = %X'1E000000000'; literal IPFINS$M_OPEF_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OPEF_OVERLAY = 8; macro IPFINS$V_OPEF_0_33 = 0,0,34,0 %; literal IPFINS$S_OPEF_0_33 = 34; macro IPFINS$V_OPEF_X2 = 4,2,2,0 %; literal IPFINS$S_OPEF_X2 = 2; macro IPFINS$V_OPEF_X = 4,4,1,0 %; macro IPFINS$V_OPEF_OPCODE = 4,5,4,0 %; literal IPFINS$S_OPEF_OPCODE = 4; macro IPFINS$Q_OPEF = 0,0,0,0 %; literal IPFINS$S_OPEF = 8; ! ! OP0X: X-Unit Opcode 0 - X1 ! literal IPFINS$M_OP0X_0_26 = %X'7FFFFFF'; literal IPFINS$M_OP0X_X6 = %X'1F8000000'; literal IPFINS$M_OP0X_X3 = %X'E00000000'; literal IPFINS$M_OP0X_36 = %X'1000000000'; literal IPFINS$M_OP0X_OPCODE = %X'1E000000000'; literal IPFINS$M_OP0X_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OP0X_OVERLAY = 8; macro IPFINS$V_OP0X_0_26 = 0,0,27,0 %; literal IPFINS$S_OP0X_0_26 = 27; macro IPFINS$V_OP0X_X6 = 0,27,6,0 %; literal IPFINS$S_OP0X_X6 = 6; macro IPFINS$V_OP0X_X3 = 4,1,3,0 %; literal IPFINS$S_OP0X_X3 = 3; macro IPFINS$V_OP0X_36 = 4,4,1,0 %; macro IPFINS$V_OP0X_OPCODE = 4,5,4,0 %; literal IPFINS$S_OP0X_OPCODE = 4; macro IPFINS$Q_OP0X = 0,0,0,0 %; literal IPFINS$S_OP0X = 8; ! ! OP6X: X-Unit Opcode 6 - X2 ! literal IPFINS$M_OP6X_0_19 = %X'FFFFF'; literal IPFINS$M_OP6X_VC = %X'100000'; literal IPFINS$M_OP6X_21_36 = %X'1FFFE00000'; literal IPFINS$M_OP6X_OPCODE = %X'1E000000000'; literal IPFINS$M_OP6X_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OP6X_OVERLAY = 8; macro IPFINS$V_OP6X_0_19 = 0,0,20,0 %; literal IPFINS$S_OP6X_0_19 = 20; macro IPFINS$V_OP6X_VC = 0,20,1,0 %; macro IPFINS$V_OP6X_21_36 = 0,21,16,0 %; literal IPFINS$S_OP6X_21_36 = 16; macro IPFINS$V_OP6X_OPCODE = 4,5,4,0 %; literal IPFINS$S_OP6X_OPCODE = 4; macro IPFINS$Q_OP6X = 0,0,0,0 %; literal IPFINS$S_OP6X = 8; ! ! OPCX: X-Unit Opcode C - X3 ! literal IPFINS$M_OPCX_0_5 = %X'3F'; literal IPFINS$M_OPCX_BTYPE = %X'1C0'; literal IPFINS$M_OPCX_9_36 = %X'1FFFFFFE00'; literal IPFINS$M_OPCX_OPCODE = %X'1E000000000'; literal IPFINS$M_OPCX_FILL = %X'FFFFFE0000000000'; literal IPFINS$S_OPCX_OVERLAY = 8; macro IPFINS$V_OPCX_0_5 = 0,0,6,0 %; literal IPFINS$S_OPCX_0_5 = 6; macro IPFINS$V_OPCX_BTYPE = 0,6,3,0 %; literal IPFINS$S_OPCX_BTYPE = 3; macro IPFINS$V_OPCX_9_36 = 0,9,28,0 %; literal IPFINS$S_OPCX_9_36 = 28; macro IPFINS$V_OPCX_OPCODE = 4,5,4,0 %; literal IPFINS$S_OPCX_OPCODE = 4; macro IPFINS$Q_OPCX = 0,0,0,0 %; literal IPFINS$S_OPCX = 8; ! ! Memory format: union of all M-Unit formats ! (not all formats yet included, just sufficient for ! fault handling) plus opcode values ! literal IPFINS$M_MEM_QP = %X'3F'; literal IPFINS$M_MEM_R1 = %X'1FC0'; literal IPFINS$M_MEM_R2 = %X'FE000'; literal IPFINS$M_MEM_R3 = %X'7F00000'; literal IPFINS$M_MEM_X = %X'8000000'; literal IPFINS$M_MEM_HINT = %X'30000000'; literal IPFINS$M_MEM_X6 = %X'FC0000000'; literal IPFINS$M_MEM_M = %X'1000000000'; literal IPFINS$M_MEM_OPCODE = %X'1E000000000'; literal IPFINS$M_MEM_FILL1 = %X'FFFFFE0000000000'; literal IPFINS$M_MEM_FILL10 = %X'3F'; literal IPFINS$M_MEM_F1 = %X'1FC0'; literal IPFINS$M_MEM_F2 = %X'FE000'; literal IPFINS$M_MEM_fill11 = %X'7F00000'; literal IPFINS$M_MEM_I = %X'8000000'; literal IPFINS$M_MEM_FILL12 = %X'30000000'; literal IPFINS$M_MEM_FILL13 = %X'FC0000000'; literal IPFINS$M_MEM_S = %X'1000000000'; literal IPFINS$M_MEM_FILL14 = %X'1E000000000'; literal IPFINS$M_MEM_FILL15 = %X'FFFFFE0000000000'; literal IPFINS$M_MEM_FILL20 = %X'3F'; literal IPFINS$M_MEM_IMM7A = %X'1FC0'; literal IPFINS$M_MEM_IMM7B = %X'FE000'; literal IPFINS$M_MEM_FILL21 = %X'7F00000'; literal IPFINS$M_MEM_FILL22 = %X'8000000'; literal IPFINS$M_MEM_FILL23 = %X'30000000'; literal IPFINS$M_MEM_FILL24 = %X'FC0000000'; literal IPFINS$M_MEM_FILL25 = %X'1000000000'; literal IPFINS$M_MEM_FILL26 = %X'1E000000000'; literal IPFINS$M_MEM_FILL27 = %X'FFFFFE0000000000'; literal IPFINS$S_MEM_FORMAT = 8; macro IPFINS$Q_MEM = 0,0,0,0 %; literal IPFINS$S_MEM = 8; macro IPFINS$V_MEM_QP = 0,0,6,0 %; literal IPFINS$S_MEM_QP = 6; macro IPFINS$V_MEM_R1 = 0,6,7,0 %; literal IPFINS$S_MEM_R1 = 7; macro IPFINS$V_MEM_R2 = 0,13,7,0 %; literal IPFINS$S_MEM_R2 = 7; macro IPFINS$V_MEM_R3 = 0,20,7,0 %; literal IPFINS$S_MEM_R3 = 7; macro IPFINS$V_MEM_X = 0,27,1,0 %; macro IPFINS$V_MEM_HINT = 0,28,2,0 %; literal IPFINS$S_MEM_HINT = 2; macro IPFINS$V_MEM_X6 = 0,30,6,0 %; literal IPFINS$S_MEM_X6 = 6; macro IPFINS$V_MEM_M = 4,4,1,0 %; macro IPFINS$V_MEM_OPCODE = 4,5,4,0 %; literal IPFINS$S_MEM_OPCODE = 4; macro IPFINS$V_MEM_F1 = 0,6,7,0 %; literal IPFINS$S_MEM_F1 = 7; macro IPFINS$V_MEM_F2 = 0,13,7,0 %; literal IPFINS$S_MEM_F2 = 7; macro IPFINS$V_MEM_I = 0,27,1,0 %; macro IPFINS$V_MEM_IMM7A = 0,6,7,0 %; literal IPFINS$S_MEM_IMM7A = 7; macro IPFINS$V_MEM_IMM7B = 0,13,7,0 %; literal IPFINS$S_MEM_IMM7B = 7; literal IPFINS$C_MEM_LD = 256; literal IPFINS$C_MEM_LDS = 257; literal IPFINS$C_MEM_LDA = 258; literal IPFINS$C_MEM_LDSA = 259; literal IPFINS$C_MEM_LDBIAS = 260; literal IPFINS$C_MEM_LDACQ = 261; literal IPFINS$C_MEM_LDCCLR = 264; literal IPFINS$C_MEM_LDCNC = 265; literal IPFINS$C_MEM_LDCCLRACQ = 266; literal IPFINS$C_MEM_ST = 268; literal IPFINS$C_MEM_STREL = 269; literal IPFINS$C_MEM_LD_IMM = 320; literal IPFINS$C_MEM_LDS_IMM = 321; literal IPFINS$C_MEM_LDA_IMM = 322; literal IPFINS$C_MEM_LDSA_IMM = 323; literal IPFINS$C_MEM_LDBIAS_IMM = 324; literal IPFINS$C_MEM_LDACQ_IMM = 325; literal IPFINS$C_MEM_LDCCLR_IMM = 328; literal IPFINS$C_MEM_LDCNC_IMM = 329; literal IPFINS$C_MEM_LDCCLRACQ_IMM = 330; literal IPFINS$C_MEM_ST_IMM = 332; literal IPFINS$C_MEM_STREL_IMM = 333; literal IPFINS$C_MEM_LDF = 384; literal IPFINS$C_MEM_LDFS = 385; literal IPFINS$C_MEM_LDFA = 386; literal IPFINS$C_MEM_LDFSA = 387; literal IPFINS$C_MEM_LDFCCLR = 392; literal IPFINS$C_MEM_LDFCNC = 393; literal IPFINS$C_MEM_STF = 396; literal IPFINS$C_MEM_LDF_IMM = 448; literal IPFINS$C_MEM_LDFS_IMM = 449; literal IPFINS$C_MEM_LDFA_IMM = 450; literal IPFINS$C_MEM_LDFSA_IMM = 451; literal IPFINS$C_MEM_LDFCCLR_IMM = 456; literal IPFINS$C_MEM_LDFCNC_IMM = 457; literal IPFINS$C_MEM_STF_IMM = 460; ! Probe opcodes found in MEM_X6 field literal IPFINS$C_PROBE_RR = 56; ! Prober register form literal IPFINS$C_PROBE_WR = 57; ! Probew register form literal IPFINS$C_PROBE_RI = 24; ! Prober immediate form literal IPFINS$C_PROBE_WI = 25; ! Probew immediate form literal IPFINS$C_PROBE_RWF = 49; ! Proberw fault form literal IPFINS$C_PROBE_RF = 50; ! Prober fault form literal IPFINS$C_PROBE_WF = 51; ! Probew fault form ! ! Macros for Immediate Formation (Table 4-74 on Pages 3:349 to 3:351) ! and for Memory Opcode Formation ! !*** MODULE $IPLDEF *** ! + ! TEMPORARY PROCESSOR PRIORITY LEVEL DEFINITIONS ! - ! literal IPL$_HWCLK = 22; ! HARDWARE CLOCK LEVEL literal IPL$_PERFMON = 15; ! PERFORMANCE MONITORING SYNCH LEVEL literal IPL$_IOPOST = 4; ! I/O POST PROCESSING LEVEL literal IPL$_MAILBOX = 11; ! WRITE MAILBOX INTERLOCK LEVEL literal IPL$_POWER = 31; ! POWERFAIL INTERLOCK LEVEL literal IPL$_QUEUEAST = 6; ! QUEUE AST LEVEL literal IPL$_RESCHED = 3; ! SCHEDULER LEVEL literal IPL$_SYNCH = 8; ! SYSTEM DATA BASE SYNCHRONIZATION LEVEL literal IPL$_TIMER = 8; ! TIME QUEUE PROCESSING LEVEL literal IPL$_TIMERFORK = 7; ! TIMER FORK INTERRUPT LEVEL literal IPL$_ASTDEL = 2; ! AST DELIVERY INTERRUPT literal IPL$_SCS = 8; ! SCS SYNCHRONIZATION IPL literal IPL$_IPINTR = 22; ! IP INTERRUPT SYNCHRONIZATION IPL literal IPL$_SCHED = 8; ! SCHEDULING DATABASE IPL literal IPL$_MMG = 8; ! MMG DATABASE IPL literal IPL$_IO_MISC = 8; ! IO_MISC IPL literal IPL$_FILSYS = 8; ! FILSYS DATABASE IPL literal IPL$_TX_SYNCH = 8; ! TX_SYNCH IPL literal IPL$_LCKMGR = 8; ! LOCK MANAGER IPL literal IPL$_IOLOCK8 = 8; ! IOLOCK8 DATABASE IPL literal IPL$_PORT = 8; ! PORTLOCK IPL literal IPL$_IOLOCK9 = 9; ! IOLOCK9 DATABASE IPL literal IPL$_IOLOCK10 = 10; ! IOLOCK10 DATABASE IPL literal IPL$_IOLOCK11 = 11; ! IOLOCK11 DATABASE IPL literal IPL$_POOL = 11; ! POOL DATABASE IPL literal IPL$_INVALIDATE = 21; ! INVALIDATE DATABASE IPL literal IPL$_VIRTCONS = 22; ! VIRTCONS DATABASE IPL literal IPL$_EMB = 31; ! EMB DATABASE IPL literal IPL$_MCHECK = 31; ! MACHINE CHECK IPL literal IPL$_MEGA = 31; ! IPL FOR KITCHEN SINK LOCK literal IPL$_FORKABLE_IPL = 3904; ! Mask of IPL's which are forkable !*** MODULE $IPMIDEF *** ! ! IPMI Max Buffer size literal IPMI$K_MAX_BUFSIZE = 512; ! For both request and response ! ! IMB request flags literal IPMI$K_NO_IMB_RESPONSE = 1; ! don't wait for IMB response ! ! + ! This structure represents a IMB* request directed to the IPMI driver ! The first struct covers the first common part of the request, some IPMI ! commands don't even have any request data. ! - literal IPMI$K_MIN_REQSIZE = 13; ! Request without data literal IPMI$SACPIPWR_REQ$K_DATLEN = 2; ! data length of Set ACPI Power state literal IPMI$SACPIPWR_REQ$K_LENGTH = 15; ! total length of Set ACPI Power state struct literal IPMI$CH_CTRL_REQ$M_CTRL = %X'F'; literal IPMI$CH_CTRL_REQ$K_DATLEN = 1; ! data length of Chassis control literal IPMI$CH_CTRL_REQ$K_LENGTH = 14; ! total length of Chassis control struct literal IPMI$CH_ID_REQ$M_FORCE = %X'1'; literal IPMI$CH_ID_REQ$K_DATLEN = 2; ! data length of Chassis Indentify literal IPMI$CH_ID_REQ$K_LENGTH = 15; ! total length of Chassis Indentify struct literal IPMI$S_EV_R_REQ$M_LUN = %X'3'; literal IPMI$S_EV_R_REQ$K_DATLEN = 2; ! data length of Set event receiver literal IPMI$S_EV_R_REQ$K_LENGTH = 15; ! total length of Set event receiver struct literal IPMI$P_EV_REQ$M_EVENT_TYPE = %X'7F'; literal IPMI$P_EV_REQ$M_EVENT_DIR = %X'80'; literal IPMI$P_EV_REQ$K_DATLEN = 8; ! data length of Platform event literal IPMI$P_EV_REQ$K_LENGTH = 21; ! total length of Platform event struct literal IPMI$GD_SDR_I_REQ$M_COUNT = %X'1'; literal IPMI$GD_SDR_I_REQ$K_DATLEN = 1; ! data length of Get Device SDR info literal IPMI$GD_SDR_I_REQ$K_LENGTH = 14; ! total length of Get Device SDR info struct literal IPMI$G_SEN_RF_REQ$K_DATLEN = 2; ! data length of Get sensor reading factors literal IPMI$G_SEN_RF_REQ$K_LENGTH = 15; ! total length of Get sensor reading factors struct literal IPMI$S_SEN_H_REQ$K_DATLEN = 4; ! data length of Set sensor hysteresis literal IPMI$S_SEN_H_REQ$K_LENGTH = 17; ! total length of Set sensor hysteresis struct literal IPMI$G_SEN_H_REQ$K_DATLEN = 2; ! data length of Get sensor hysteresis literal IPMI$G_SEN_H_REQ$K_LENGTH = 15; ! total length of Get sensor hysteresis struct literal IPMI$S_SEN_TH_REQ$M_L_NC_TF = %X'1'; literal IPMI$S_SEN_TH_REQ$M_L_C_TF = %X'2'; literal IPMI$S_SEN_TH_REQ$M_L_NR_TF = %X'4'; literal IPMI$S_SEN_TH_REQ$M_U_NC_TF = %X'8'; literal IPMI$S_SEN_TH_REQ$M_U_C_TF = %X'10'; literal IPMI$S_SEN_TH_REQ$M_U_NR_TF = %X'20'; literal IPMI$S_SEN_TH_REQ$K_DATLEN = 8; ! data length of Set sensor threshold literal IPMI$S_SEN_TH_REQ$K_LENGTH = 21; ! total length of Set sensor threshold struct literal IPMI$G_SEN_TH_REQ$K_DATLEN = 1; ! data length of Get sensor threshold literal IPMI$G_SEN_TH_REQ$K_LENGTH = 14; ! total length of Get sensor threshold struct literal IPMI$S_SEN_EE_REQ$M_RSVD = %X'F'; literal IPMI$S_SEN_EE_REQ$M_SEL = %X'30'; literal IPMI$S_SEN_EE_REQ$M_DIS_SCAN = %X'40'; literal IPMI$S_SEN_EE_REQ$M_DIS_ALL = %X'80'; literal IPMI$S_SEN_EE_REQ$K_DATLEN = 6; ! data length of Set sensor event enable literal IPMI$S_SEN_EE_REQ$K_LENGTH = 19; ! total length of Set sensor event enable struct literal IPMI$G_SEN_EE_REQ$K_DATLEN = 1; ! data length of Get sensor event enable literal IPMI$G_SEN_EE_REQ$K_LENGTH = 14; ! total length of Get sensor event enable struct literal IPMI$S_SEN_E_REQ$M_RSVD = %X'7F'; literal IPMI$S_SEN_E_REQ$M_DIS_ALL = %X'80'; literal IPMI$S_SEN_E_REQ$K_DATLEN = 6; ! data length of Re-arm sensor events literal IPMI$S_SEN_E_REQ$K_LENGTH = 19; ! total length of Re-arm sensor events struct literal IPMI$G_SEN_ES_REQ$K_DATLEN = 1; ! data length of Get sensor event status literal IPMI$G_SEN_ES_REQ$K_LENGTH = 14; ! total length of Get sensor event status struct literal IPMI$G_SEN_R_REQ$K_DATLEN = 1; ! data length of Get sensor reading literal IPMI$G_SEN_R_REQ$K_LENGTH = 14; ! total length of Get sensor reading struct literal IPMI$S_SEN_TY_REQ$M_EVENT_TYPE = %X'7F'; literal IPMI$S_SEN_TY_REQ$K_DATLEN = 3; ! data length of Set sensor type literal IPMI$S_SEN_TY_REQ$K_LENGTH = 16; ! total length of Set sensor type struct literal IPMI$G_SEN_TY_REQ$K_DATLEN = 1; ! data length of Get sensor type literal IPMI$G_SEN_TY_REQ$K_LENGTH = 14; ! total length of Get sensor type struct literal IPMI$GFRU_I_REQ$K_DATLEN = 1; ! data length of Get FRU Inventory area literal IPMI$GFRU_I_REQ$K_LENGTH = 14; ! total length of Get FRU Inventory area struct literal IPMI$RFRU_REQ$K_DATLEN = 4; ! data length of Read FRU data literal IPMI$RFRU_REQ$K_LENGTH = 17; ! total lenght of Read FRU data struct literal IPMI$GSDR_REQ$K_DATLEN = 6; ! data length of Get SDR entry literal IPMI$GSDR_REQ$K_LENGTH = 19; ! total length of Get SDR entry struct literal IPMI$GSEL_REQ$K_DATLEN = 6; ! data length of Get SEL entry literal IPMI$GSEL_REQ$K_LENGTH = 19; ! total length of Get SEL entry struct literal IPMI$ASEL_REQ$K_DATLEN = 16; ! data length of Add SEL entry literal IPMI$ASEL_REQ$K_LENGTH = 29; ! total length of Add SEL entry struct literal IPMI$DSEL_REQ$K_DATLEN = 4; ! data length of Delete SEL entry request literal IPMI$DSEL_REQ$K_LENGTH = 17; ! total length of Delete SEL entry struct literal IPMI$CSEL_REQ$K_DATLEN = 6; ! data length of Clear SEL request literal IPMI$CSEL_REQ$K_LENGTH = 19; ! total length of Clear SEL struct literal IPMI$SSEL_T_REQ$K_DATLEN = 4; ! data length of Set SEL Time request literal IPMI$SSEL_T_REQ$K_LENGTH = 17; ! total length of Set SEL Time struct literal IPMI$AFPL_REQ$K_DATLEN = 16; ! data length of Add FPL entry request literal IPMI$AFPL_REQ$K_LENGTH = 29; ! total length of Add FPL entry struct literal IPMI$GTOKEN_I_REQ$K_DATLEN = 2; ! data length of Get Token Info request literal IPMI$GTOKEN_I_REQ$K_LENGTH = 15; ! total length of Get Token Info struct literal IPMI$RTOKEN_REQ$K_DATLEN = 2; ! data length of Read Token request literal IPMI$RTOKEN_REQ$K_LENGTH = 15; ! total length of Read Token struct literal IPMI$P_RTOKEN_REQ$K_DATLEN = 5; ! data length of Partial Read Token request literal IPMI$P_RTOKEN_REQ$K_LENGTH = 18; ! total length of Partial Read Token struct literal IPMI$L_PROP_REQ$K_DATLEN = 130; ! data length of Lock Property request literal IPMI$L_PROP_REQ$K_LENGTH = 143; ! total length of Lock Property struct literal IPMI$U_PROP_REQ$K_DATLEN = 2; ! data length of UnLock Property request literal IPMI$U_PROP_REQ$K_LENGTH = 15; ! total length of UnLock Property struct literal IPMI$G_PROP_REQ$K_DATLEN = 11; ! data length of Get Property request literal IPMI$G_PROP_REQ$K_LENGTH = 24; ! total length of Get Property struct literal IPMI$S_IMBREQUEST = 512; macro IPMI$REQ$L_FLAGS = 0,0,32,0 %; ! request flags macro IPMI$REQ$L_TIMEOUT = 4,0,32,0 %; ! in uSec units ignored... macro IPMI$REQ$B_RSSA = 8,0,8,0 %; ! IMB address of responder macro IPMI$REQ$B_CMD = 9,0,8,0 %; ! IMB command macro IPMI$REQ$B_NETFN = 10,0,8,0 %; ! Network Function code for command macro IPMI$REQ$B_RSLUN = 11,0,8,0 %; ! Logical unit on responder macro IPMI$REQ$B_DATLEN = 12,0,8,0 %; ! Length of request data macro IPMI$REQ$B_DATA = 13,0,0,0 %; literal IPMI$REQ$S_DATA = 499; ! Request data ! ! IPMI Set ACPI Power state command ! macro IPMI$SACPIPWR_REQ$B_SYS_PWR_ST = 13,0,8,0 %; ! system power state macro IPMI$SACPIPWR_REQ$B_DEV_PWR_ST = 14,0,8,0 %; ! device power state ! ! IPMI Chassis control command ! macro IPMI$CH_CTRL_REQ$V_CTRL = 13,0,4,0 %; literal IPMI$CH_CTRL_REQ$S_CTRL = 4; ! Chassis control values ! ! IPMI Chassis ID command ! macro IPMI$CH_ID_REQ$B_INTERVAL = 13,0,8,0 %; ! Identify Interval in seconds macro IPMI$CH_ID_REQ$B_FLAGS = 14,0,8,0 %; macro IPMI$CH_ID_REQ$V_FORCE = 14,0,1,0 %; ! Force the Identify ON forever ! ! IPMI Set event receiver command ! macro IPMI$S_EV_R_REQ$B_SLAVE_ADR = 13,0,8,0 %; ! Event receiver slave address macro IPMI$S_EV_R_REQ$B_B2 = 14,0,8,0 %; macro IPMI$S_EV_R_REQ$V_LUN = 14,0,2,0 %; literal IPMI$S_EV_R_REQ$S_LUN = 2; ! LUN of event receiver ! ! IPMI Platform event or event messenger command (System interface format) ! macro IPMI$P_EV_REQ$B_GENERATE_ID = 13,0,8,0 %; ! Generator ID macro IPMI$P_EV_REQ$b_rev = 14,0,8,0 %; ! Event message format rev macro IPMI$P_EV_REQ$B_SENSOR_TYPE = 15,0,8,0 %; ! Sensor Type macro IPMI$P_EV_REQ$B_SENSOR_NUM = 16,0,8,0 %; ! Sensor number macro IPMI$P_EV_REQ$V_EVENT_TYPE = 17,0,7,0 %; literal IPMI$P_EV_REQ$S_EVENT_TYPE = 7; ! Event type macro IPMI$P_EV_REQ$V_EVENT_DIR = 17,7,1,0 %; ! Event direction macro IPMI$P_EV_REQ$B_DATA1 = 18,0,8,0 %; ! Event data 1 macro IPMI$P_EV_REQ$B_DATA2 = 19,0,8,0 %; ! Event data 2 macro IPMI$P_EV_REQ$B_DATA3 = 20,0,8,0 %; ! Event data 3 ! ! IPMI Get Device SDR info command ! macro IPMI$GD_SDR_I_REQ$V_COUNT = 13,0,1,0 %; ! Get SDR or Sensor count ! ! IPMI Get sensor reading factors command ! macro IPMI$G_SEN_RF_REQ$B_SENSOR = 13,0,8,0 %; ! Sensor number macro IPMI$G_SEN_RF_REQ$B_READ_BYTE = 14,0,8,0 %; ! Reading byte ! ! IPMI Set sensor hysteresis command ! macro IPMI$S_SEN_H_REQ$B_SENSOR = 13,0,8,0 %; ! Sensor number macro IPMI$S_SEN_H_REQ$B_MASK = 14,0,8,0 %; ! Future hystereris mask. Write as 'FF' macro IPMI$S_SEN_H_REQ$B_POS = 15,0,8,0 %; ! Positive-going hystereris value macro IPMI$S_SEN_H_REQ$B_NEG = 16,0,8,0 %; ! Negative-going hystereris value ! ! IPMI Get sensor hysteresis command ! macro IPMI$G_SEN_H_REQ$B_SENSOR = 13,0,8,0 %; ! Sensor number macro IPMI$G_SEN_H_REQ$B_MASK = 14,0,8,0 %; ! Future hystereris mask. Write as 'FF' ! ! IPMI Set sensor threshold command ! macro IPMI$S_SEN_TH_REQ$B_SENSOR = 13,0,8,0 %; ! Sensor number macro IPMI$S_SEN_TH_REQ$B_B2 = 14,0,8,0 %; macro IPMI$S_SEN_TH_REQ$V_L_NC_TF = 14,0,1,0 %; ! 1 = set lower non-critical threshold macro IPMI$S_SEN_TH_REQ$V_L_C_TF = 14,1,1,0 %; ! 1 = set lower critical threshold macro IPMI$S_SEN_TH_REQ$V_L_NR_TF = 14,2,1,0 %; ! 1 = set lower non-recoverable threshold macro IPMI$S_SEN_TH_REQ$V_U_NC_TF = 14,3,1,0 %; ! 1 = set upper non-critical threshold macro IPMI$S_SEN_TH_REQ$V_U_C_TF = 14,4,1,0 %; ! 1 = set upper critical threshold macro IPMI$S_SEN_TH_REQ$V_U_NR_TF = 14,5,1,0 %; ! 1 = set upper non-recoverable threshold macro IPMI$S_SEN_TH_REQ$B_L_NC_THRES = 15,0,8,0 %; ! Lower non-critical threshold macro IPMI$S_SEN_TH_REQ$B_L_C_THRES = 16,0,8,0 %; ! Lower critical threshold macro IPMI$S_SEN_TH_REQ$B_L_NR_THRES = 17,0,8,0 %; ! Lower non-recoverable threshold macro IPMI$S_SEN_TH_REQ$B_U_NC_THRES = 18,0,8,0 %; ! Upper non-critical threshold macro IPMI$S_SEN_TH_REQ$B_U_C_THRES = 19,0,8,0 %; ! Upper critical threshold macro IPMI$S_SEN_TH_REQ$B_U_NR_THRES = 20,0,8,0 %; ! Upper non-recoverable threshold ! ! IPMI Get sensor threshold command ! macro IPMI$G_SEN_TH_REQ$B_SENSOR = 13,0,8,0 %; ! Sensor number ! ! IPMI Set sensor event enable command ! macro IPMI$S_SEN_EE_REQ$B_SENSOR = 13,0,8,0 %; ! Sensor number macro IPMI$S_SEN_EE_REQ$B_B2 = 14,0,8,0 %; macro IPMI$S_SEN_EE_REQ$V_RSVD = 14,0,4,0 %; literal IPMI$S_SEN_EE_REQ$S_RSVD = 4; ! Reserved macro IPMI$S_SEN_EE_REQ$V_SEL = 14,4,2,0 %; literal IPMI$S_SEN_EE_REQ$S_SEL = 2; ! enable or disable selected event messages macro IPMI$S_SEN_EE_REQ$V_DIS_SCAN = 14,6,1,0 %; ! 0 = disable scanning on this sensor macro IPMI$S_SEN_EE_REQ$V_DIS_ALL = 14,7,1,0 %; ! 0 = disable all event messages macro IPMI$S_SEN_EE_REQ$W_ASSERT = 15,0,16,0 %; ! Selected assertion events macro IPMI$S_SEN_EE_REQ$W_DEASSERT = 17,0,16,0 %; ! Selected deassertion events ! ! IPMI Get sensor event enable command ! macro IPMI$G_SEN_EE_REQ$B_SENSOR = 13,0,8,0 %; ! Sensor number ! ! IPMI Re-arm sensor events command ! macro IPMI$S_SEN_E_REQ$B_SENSOR = 13,0,8,0 %; ! Sensor number macro IPMI$S_SEN_E_REQ$B_B2 = 14,0,8,0 %; macro IPMI$S_SEN_E_REQ$V_RSVD = 14,0,7,0 %; literal IPMI$S_SEN_E_REQ$S_RSVD = 7; ! Reserved macro IPMI$S_SEN_E_REQ$V_DIS_ALL = 14,7,1,0 %; ! 0 = re-arm all event messages macro IPMI$S_SEN_E_REQ$W_ASSERT = 15,0,16,0 %; ! re-arm selected assertion events macro IPMI$S_SEN_E_REQ$W_DEASSERT = 17,0,16,0 %; ! re-arm selected deassertion events ! ! IPMI Get sensor event status command ! macro IPMI$G_SEN_ES_REQ$B_SENSOR = 13,0,8,0 %; ! Sensor number ! ! IPMI Get sensor reading command ! macro IPMI$G_SEN_R_REQ$B_SENSOR = 13,0,8,0 %; ! Sensor number ! ! IPMI Set sensor type command ! macro IPMI$S_SEN_TY_REQ$B_SENSOR = 13,0,8,0 %; ! Sensor number macro IPMI$S_SEN_TY_REQ$B_SENSOR_TYPE = 14,0,8,0 %; ! Sensor type code macro IPMI$S_SEN_TY_REQ$B_B3 = 15,0,8,0 %; macro IPMI$S_SEN_TY_REQ$V_EVENT_TYPE = 15,0,7,0 %; literal IPMI$S_SEN_TY_REQ$S_EVENT_TYPE = 7; ! Event/reading type code ! ! IPMI Get sensor type command ! macro IPMI$G_SEN_TY_REQ$B_SENSOR = 13,0,8,0 %; ! Sensor number ! ! IPMI Get FRU Inventory Area command ! macro IPMI$GFRU_I_REQ$B_FRU_ID = 13,0,8,0 %; ! Fru Device id ! ! IPMI Read FRU data command ! macro IPMI$RFRU_REQ$B_FRU_ID = 13,0,8,0 %; ! Fru Device id macro IPMI$RFRU_REQ$W_OFFSET = 14,0,16,0 %; ! Offset into the FRU data macro IPMI$RFRU_REQ$B_BCNT = 16,0,8,0 %; ! read bytecount ! ! IPMI Get SDR entry command ! macro IPMI$GSDR_REQ$W_RES_ID = 13,0,16,0 %; ! Reservation id macro IPMI$GSDR_REQ$W_REC_ID = 15,0,16,0 %; ! Record id macro IPMI$GSDR_REQ$B_OFFSET = 17,0,8,0 %; ! Offset into the record macro IPMI$GSDR_REQ$B_BCNT = 18,0,8,0 %; ! read bytecount ! ! IPMI Get SEL entry command ! macro IPMI$GSEL_REQ$W_RES_ID = 13,0,16,0 %; ! Reservation id macro IPMI$GSEL_REQ$W_REC_ID = 15,0,16,0 %; ! Record id 0000 first - ffff last macro IPMI$GSEL_REQ$B_OFFSET = 17,0,8,0 %; ! Offset into the record macro IPMI$GSEL_REQ$B_BCNT = 18,0,8,0 %; ! read bytecount ! ! IPMI ADD SEL entry command ! macro IPMI$ASEL_REQ$B_DATA = 13,0,0,0 %; literal IPMI$ASEL_REQ$S_DATA = 16; ! Add SEL Record Data ! ! IPMI Delete SEL entry command ! macro IPMI$DSEL_REQ$W_RES_ID = 13,0,16,0 %; ! Reservation id macro IPMI$DSEL_REQ$W_REC_ID = 15,0,16,0 %; ! Record id to delete 0000 first - ffff last ! ! IPMI Clear SEL command ! macro IPMI$CSEL_REQ$W_RES_ID = 13,0,16,0 %; ! Reservation id macro IPMI$CSEL_REQ$B_C = 15,0,8,0 %; ! 'C' macro IPMI$CSEL_REQ$B_L = 16,0,8,0 %; ! 'L' macro IPMI$CSEL_REQ$B_R = 17,0,8,0 %; ! 'R' macro IPMI$CSEL_REQ$B_CMD = 18,0,8,0 %; ! Command: 'AA' initiate erase, '00' erase status ! ! IPMI Set SEL Time command ! macro IPMI$SSEL_T_REQ$L_TIME = 13,0,32,0 %; ! Time value to set it with ! ! IPMI Add FPL entry command ! macro IPMI$AFPL_REQ$B_DATA = 13,0,0,0 %; literal IPMI$AFPL_REQ$S_DATA = 16; ! Add FPL Record Data ! ! IPMI Get Token Info command ! macro IPMI$GTOKEN_I_REQ$W_TOKEN_ID = 13,0,16,0 %; ! Token id ! ! IPMI Read Token command ! macro IPMI$RTOKEN_REQ$W_TOKEN_ID = 13,0,16,0 %; ! Token id ! ! IPMI Partial Read Token command ! macro IPMI$P_RTOKEN_REQ$W_TOKEN_ID = 13,0,16,0 %; ! Token id macro IPMI$P_RTOKEN_REQ$W_OFFSET = 15,0,16,0 %; ! Offset into the token macro IPMI$P_RTOKEN_REQ$B_BCNT = 17,0,8,0 %; ! read bytecount ! ! IPMI Lock Property command ! macro IPMI$L_PROP_REQ$B_ID = 13,0,8,0 %; ! Property id to lock macro IPMI$L_PROP_REQ$B_SW_ID = 14,0,0,0 %; literal IPMI$L_PROP_REQ$S_SW_ID = 128; ! Software ID of requester. macro IPMI$L_PROP_REQ$B_TYPE = 142,0,8,0 %; ! Type of lock to acquire ! ! IPMI UnLock Property command ! macro IPMI$U_PROP_REQ$B_ID = 13,0,8,0 %; ! Property id to unlock macro IPMI$U_PROP_REQ$B_TYPE = 14,0,8,0 %; ! Type of lock to unlock ! ! IPMI Get Property command ! macro IPMI$G_PROP_REQ$L_LOCK = 13,0,32,0 %; ! Reservation Lock number for this Property macro IPMI$G_PROP_REQ$B_ID = 17,0,8,0 %; ! Property id macro IPMI$G_PROP_REQ$L_OFFSET = 18,0,32,0 %; ! Offset into the Property macro IPMI$G_PROP_REQ$W_BCNT = 22,0,16,0 %; ! get bytecount ! ! ! ! + ! This structure represents a IMB* response from a command to the IPMI driver ! The first struct is covers the common completion code(ccode) some commands ! only have a completion code for a response. ! - literal IPMI$K_MIN_RESPSIZE = 1; ! Response with only ccode literal IPMI$GDEVID_RSP$M_IPMI_V_MAJOR = %X'F'; literal IPMI$GDEVID_RSP$M_IPMI_V_MINOR = %X'F0'; literal IPMI$GDEVID_RSP$K_NO_AXREV_LEN = 12; ! length of Get Device Id response without optional aux fw rev literal IPMI$GDEVID_RSP$K_LENGTH = 16; ! total length of Get Device Id response struct literal IPMI$GST_RSP$K_LENGTH = 3; ! total length of Get selftest response struct literal IPMI$GACPIPWR_RSP$K_LENGTH = 3; ! total length of Get ACPI Power state response struct literal IPMI$GD_GUID_RSP$K_LENGTH = 17; ! total length of Get Device GUID response struct literal IPMI$G_WATCHDOG_RSP$K_LENGTH = 9; ! total length of Get Watchdog timer response struct literal IPMI$GBTCAP_RSP$K_LENGTH = 6; ! total length of Get BT Interface Capablilities response struct literal IPMI$GS_GUID_RSP$K_LENGTH = 17; ! total length of Get System GUID response struct literal IPMI$GCH_CAP_RSP$M_INTRUDE = %X'1'; literal IPMI$GCH_CAP_RSP$M_LCKED = %X'2'; literal IPMI$GCH_CAP_RSP$M_DIAG_INT = %X'4'; literal IPMI$GCH_CAP_RSP$M_P_LCK = %X'8'; literal IPMI$GCH_CAP_RSP$K_LENGTH = 7; ! total length of Get Chassis Capabilities response struct literal IPMI$GCH_STAT_RSP$M_ON = %X'1'; literal IPMI$GCH_STAT_RSP$M_OVR = %X'2'; literal IPMI$GCH_STAT_RSP$M_P_LOCK = %X'4'; literal IPMI$GCH_STAT_RSP$M_P_FLT = %X'8'; literal IPMI$GCH_STAT_RSP$M_P_CFLT = %X'10'; literal IPMI$GCH_STAT_RSP$M_P_POLICY = %X'60'; literal IPMI$GCH_STAT_RSP$M_AC = %X'1'; literal IPMI$GCH_STAT_RSP$M_L_OVR = %X'2'; literal IPMI$GCH_STAT_RSP$M_L_P_LCK = %X'4'; literal IPMI$GCH_STAT_RSP$m_l_P_FLT = %X'8'; literal IPMI$GCH_STAT_RSP$M_IPMI = %X'10'; literal IPMI$GCH_STAT_RSP$M_INTRUDE = %X'1'; literal IPMI$GCH_STAT_RSP$M_FP_LCK = %X'2'; literal IPMI$GCH_STAT_RSP$M_DRIVE = %X'4'; literal IPMI$GCH_STAT_RSP$M_FAN = %X'8'; literal IPMI$GCH_STAT_RSP$K_LENGTH = 5; ! total length of Get Chassis Status response struct literal IPMI$G_EV_R_RSP$M_LUN = %X'3'; literal IPMI$G_EV_R_RSP$K_LENGTH = 3; ! total length of get event receiver response struct literal IPMI$GD_SDR_I_RSP$M_LUN0 = %X'1'; literal IPMI$GD_SDR_I_RSP$M_LUN1 = %X'2'; literal IPMI$GD_SDR_I_RSP$M_LUN2 = %X'4'; literal IPMI$GD_SDR_I_RSP$M_LUN3 = %X'8'; literal IPMI$GD_SDR_I_RSP$M_RSVD = %X'70'; literal IPMI$GD_SDR_I_RSP$M_POP = %X'80'; literal IPMI$GD_SDR_I_RSP$K_LENGTH = 7; ! total length of Get Device SDR info response struct literal IPMI$G_SEN_RF_RSP$M_TOL = %X'3F'; literal IPMI$G_SEN_RF_RSP$M_M_MS = %X'C0'; literal IPMI$G_SEN_RF_RSP$M_ACC_LS = %X'3F'; literal IPMI$G_SEN_RF_RSP$M_B_MS = %X'C0'; literal IPMI$G_SEN_RF_RSP$M_RSVD = %X'3'; literal IPMI$G_SEN_RF_RSP$M_ACC_EXP = %X'C'; literal IPMI$G_SEN_RF_RSP$M_ACC_MS = %X'F0'; literal IPMI$G_SEN_RF_RSP$M_B_EXP = %X'F'; literal IPMI$G_SEN_RF_RSP$M_RESULT = %X'F0'; literal IPMI$G_SEN_RF_RSP$K_LENGTH = 8; ! total length of Get sensor reading factors response struct literal IPMI$G_SEN_H_RSP$K_LENGTH = 3; ! total length of Get sensor hysteresis response struct literal IPMI$G_SEN_TH_RSP$M_L_NC_TF = %X'1'; literal IPMI$G_SEN_TH_RSP$M_L_C_TF = %X'2'; literal IPMI$G_SEN_TH_RSP$M_L_NR_TF = %X'4'; literal IPMI$G_SEN_TH_RSP$M_U_NC_TF = %X'8'; literal IPMI$G_SEN_TH_RSP$M_U_C_TF = %X'10'; literal IPMI$G_SEN_TH_RSP$M_U_NR_TF = %X'20'; literal IPMI$G_SEN_TH_RSP$K_LENGTH = 8; ! total length of Get sensor threshold response struct literal IPMI$G_SEN_EE_RSP$M_RSVD = %X'3F'; literal IPMI$G_SEN_EE_RSP$M_SCAN_DIS = %X'40'; literal IPMI$G_SEN_EE_RSP$M_ALL_DIS = %X'80'; literal IPMI$G_SEN_EE_RSP$K_LENGTH = 6; ! total length of Get sensor event enable response struct literal IPMI$G_SEN_ES_RSP$M_RSVD = %X'1F'; literal IPMI$G_SEN_ES_RSP$M_BUSY = %X'20'; literal IPMI$G_SEN_ES_RSP$M_SCAN_DIS = %X'40'; literal IPMI$G_SEN_ES_RSP$M_ALL_DIS = %X'80'; literal IPMI$G_SEN_ES_RSP$K_LENGTH = 6; ! total length of Get sensor event status response struct literal IPMI$G_SEN_R_RSP$M_RSVD = %X'1F'; literal IPMI$G_SEN_R_RSP$M_BUSY = %X'20'; literal IPMI$G_SEN_R_RSP$M_SCAN_DIS = %X'40'; literal IPMI$G_SEN_R_RSP$M_ALL_DIS = %X'80'; literal IPMI$G_SEN_R_RSP$K_LENGTH = 7; ! total length of Get sensor reading response struct literal IPMI$G_SEN_TY_RSP$M_EVENT_TYPE = %X'7F'; literal IPMI$G_SEN_TY_RSP$K_LENGTH = 3; ! total length of Get sensor type response struct literal IPMI$GFRU_I_RSP$M_WRD_ACC = %X'1'; literal IPMI$GFRU_I_RSP$K_LENGTH = 4; ! total length of FRU Inventory Area response struct literal IPMI$RFRU_RSP$K_LENGTH = 258; ! total length of Read FRU Data response struct literal IPMI$GSDR_I_RSP$M_SDR_V_MAJOR = %X'F'; literal IPMI$GSDR_I_RSP$M_SDR_V_MINOR = %X'F0'; literal IPMI$GSDR_I_RSP$M_ALLOC_INFO = %X'1'; literal IPMI$GSDR_I_RSP$M_RES = %X'2'; literal IPMI$GSDR_I_RSP$M_P_ADD = %X'4'; literal IPMI$GSDR_I_RSP$M_DEL = %X'8'; literal IPMI$GSDR_I_RSP$M_RSVD = %X'10'; literal IPMI$GSDR_I_RSP$M_NONMODAL = %X'20'; literal IPMI$GSDR_I_RSP$M_MODAL = %X'40'; literal IPMI$GSDR_I_RSP$M_OVR = %X'80'; literal IPMI$GSDR_I_RSP$K_LENGTH = 15; ! total length of Get SDR Repository Info response struct literal IPMI$GSDR_A_RSP$K_LENGTH = 10; ! total length of Get SDR Repository Allocation Info response struct literal IPMI$RESSDR_R_RSP$K_LENGTH = 3; ! total length of Reserve SDR Repository response struct literal IPMI$GSDR_RSP$K_LENGTH = 259; ! total length of get SDR response struct literal IPMI$GSDR_T_RSP$K_LENGTH = 5; ! total length of Get SDR Repository Time response struct literal IPMI$GSEL_I_RSP$M_SEL_V_MAJOR = %X'F'; literal IPMI$GSEL_I_RSP$M_SEL_V_MINOR = %X'F0'; literal IPMI$GSEL_I_RSP$M_ALLOC_INFO = %X'1'; literal IPMI$GSEL_I_RSP$M_RES = %X'2'; literal IPMI$GSEL_I_RSP$M_P_ADD = %X'4'; literal IPMI$GSEL_I_RSP$M_DEL = %X'8'; literal IPMI$GSEL_I_RSP$M_RESVD = %X'70'; literal IPMI$GSEL_I_RSP$M_OVR = %X'80'; literal IPMI$GSEL_I_RSP$K_LENGTH = 15; ! total length of Get SEL Info response struct literal IPMI$GSEL_A_RSP$K_LENGTH = 10; ! total length of Get SEL Allocation Info response struct literal IPMI$RESSEL_RSP$K_LENGTH = 3; ! total length of Reserve SEL response struct literal IPMI$GSEL_RSP$K_LENGTH = 19; ! total length of Get SEL response struct literal IPMI$ASEL_RSP$K_LENGTH = 3; ! total length of Add SEL response struct literal IPMI$DSEL_RSP$K_LENGTH = 3; ! total length of Delete SEL response struct literal IPMI$CSEL_RSP$M_E_PRGRESS = %X'F'; literal IPMI$CSEL_RSP$M_E_P_RSVD = %X'F0'; literal IPMI$CSEL_RSP$K_LENGTH = 2; ! total length of Clear SEL response struct literal IPMI$GSEL_T_RSP$K_LENGTH = 5; ! total length of Get SEL Time response struct literal IPMI$GTOKEN_I_RSP$M_R_GUEST = %X'1'; literal IPMI$GTOKEN_I_RSP$M_R_USER = %X'2'; literal IPMI$GTOKEN_I_RSP$M_R_ADMIN = %X'4'; literal IPMI$GTOKEN_I_RSP$M_W_GUEST = %X'8'; literal IPMI$GTOKEN_I_RSP$M_W_USER = %X'10'; literal IPMI$GTOKEN_I_RSP$M_W_ADMIN = %X'20'; literal IPMI$GTOKEN_I_RSP$M_CHECKSUM = %X'40'; literal IPMI$GTOKEN_I_RSP$M_E_INFO = %X'80'; literal IPMI$GTOKEN_I_RSP$K_LENGTH = 2; ! total length of Get Token Info response struct literal IPMI$RTOKEN_RSP$K_LENGTH = 257; ! total length of Read Token response struct literal IPMI$P_RTOKEN_RSP$K_LENGTH = 257; ! total length of Partial Read Token response struct literal IPMI$L_PROP_RSP$K_LENGTH = 137; ! total length of Lock Property response struct literal IPMI$G_PROP_RSP$K_LENGTH = 257; ! total length of Get Property response struct literal IPMI$S_IMBRESPONSE = 512; macro IPMI$RSP$B_CCODE = 0,0,8,0 %; ! IMB completion code macro IPMI$RSP$B_DATA = 1,0,0,0 %; literal IPMI$RSP$S_DATA = 511; ! Response data ! ! IPMI Get Device ID command response ! macro IPMI$GDEVID_RSP$B_DEV_ID = 1,0,8,0 %; ! Master Device ID macro IPMI$GDEVID_RSP$B_DEV_REV = 2,0,8,0 %; ! macro IPMI$GDEVID_RSP$B_FRMW_REV1 = 3,0,8,0 %; ! Major FW revision macro IPMI$GDEVID_RSP$B_FRMW_REV2 = 4,0,8,0 %; ! Minor FW revision macro IPMI$GDEVID_RSP$B_IPMI_VER = 5,0,8,0 %; ! Combined IPMI version macro IPMI$GDEVID_RSP$V_IPMI_V_MAJOR = 5,0,4,0 %; literal IPMI$GDEVID_RSP$S_IPMI_V_MAJOR = 4; ! IPMI Version Major macro IPMI$GDEVID_RSP$V_IPMI_V_MINOR = 5,4,4,0 %; literal IPMI$GDEVID_RSP$S_IPMI_V_MINOR = 4; ! IPMI Version Minor macro IPMI$GDEVID_RSP$B_DEV_SUPPORT = 6,0,8,0 %; ! Additional Device Support macro IPMI$GDEVID_RSP$B_MANUF_ID = 7,0,24,0 %; literal IPMI$GDEVID_RSP$S_MANUF_ID = 3; ! macro IPMI$GDEVID_RSP$B_PROD_ID = 10,0,16,0 %; literal IPMI$GDEVID_RSP$S_PROD_ID = 2; ! macro IPMI$GDEVID_RSP$B_AX_FIRM_REV = 12,0,32,0 %; literal IPMI$GDEVID_RSP$S_AX_FIRM_REV = 4; ! Auxiliary Firmware Revision (optional) ! ! IPMI Get Selftest command response ! macro IPMI$GST_RSP$B_RSLT1 = 1,0,8,0 %; ! Selftest result 1 macro IPMI$GST_RSP$B_RSLT2 = 2,0,8,0 %; ! Selftest resule 2 ! ! IPMI Get ACPI Power state command response ! macro IPMI$GACPIPWR_RSP$B_SYS_PWR_ST = 1,0,8,0 %; ! system power state macro IPMI$GACPIPWR_RSP$B_DEV_PWR_ST = 2,0,8,0 %; ! device power state ! ! IPMI Get Device GUID command response ! macro IPMI$GD_GUID_RSP$B_GUID = 1,0,0,0 %; literal IPMI$GD_GUID_RSP$S_GUID = 16; ! Device GUID data ! ! IPMI Get Watchdog timer command response ! macro IPMI$G_WATCHDOG_RSP$B_USE = 1,0,8,0 %; ! Timer use macro IPMI$G_WATCHDOG_RSP$B_ACTION = 2,0,8,0 %; ! Timer actions macro IPMI$G_WATCHDOG_RSP$B_PRETIME = 3,0,8,0 %; ! Pre-timeout interval macro IPMI$G_WATCHDOG_RSP$B_USE_EXP = 4,0,8,0 %; ! Timer use expiration flags macro IPMI$G_WATCHDOG_RSP$W_I_COUNT = 5,0,16,0 %; ! Initial countdown value macro IPMI$G_WATCHDOG_RSP$W_P_COUNT = 7,0,16,0 %; ! Preset countdown value ! ! IPMI Get BT Interface Capapbilities command response ! macro IPMI$GBTCAP_RSP$B_MAX_REQ = 1,0,8,0 %; ! Maximum outstanding requests macro IPMI$GBTCAP_RSP$B_IN_SIZE = 2,0,8,0 %; ! Input buffer size macro IPMI$GBTCAP_RSP$B_OUT_SIZE = 3,0,8,0 %; ! Output buffer size macro IPMI$GBTCAP_RSP$B_MAX_TIME = 4,0,8,0 %; ! BMC Request-to-Response time in seconds; 30 max macro IPMI$GBTCAP_RSP$B_MAX_RTRY = 5,0,8,0 %; ! Maximum recommened retrys ! ! IPMI Get System GUID command response ! macro IPMI$GS_GUID_RSP$B_GUID = 1,0,0,0 %; literal IPMI$GS_GUID_RSP$S_GUID = 16; ! System GUID data ! ! IPMI Get Chassis Capabilities command response ! macro IPMI$GCH_CAP_RSP$B_FLGS = 1,0,8,0 %; ! Capabilities Flags macro IPMI$GCH_CAP_RSP$V_INTRUDE = 1,0,1,0 %; ! Provides intrusion (physical security) sensor macro IPMI$GCH_CAP_RSP$V_LCKED = 1,1,1,0 %; ! Provides front panel lockout macro IPMI$GCH_CAP_RSP$V_DIAG_INT = 1,2,1,0 %; ! Provides Diagnostic Interrupt (FP NMI) (IPMI 1.5) macro IPMI$GCH_CAP_RSP$V_P_LCK = 1,3,1,0 %; ! Provides power interlock (IPMI 1.5) macro IPMI$GCH_CAP_RSP$B_FRU_ADR = 2,0,8,0 %; ! Chassis FRU Info Device Address macro IPMI$GCH_CAP_RSP$B_SDR_ADR = 3,0,8,0 %; ! Chassis SDR Device Address macro IPMI$GCH_CAP_RSP$B_SEL_ADR = 4,0,8,0 %; ! Chassis SEL Device Address macro IPMI$GCH_CAP_RSP$B_SM_ADR = 5,0,8,0 %; ! Chassis System Mamangement Device Address macro IPMI$GCH_CAP_RSP$B_BR_ADR = 6,0,8,0 %; ! Chassis Bridge Device Address ! ! IPMI Get Chassis Status command response ! macro IPMI$GCH_STAT_RSP$B_CUR_PWR = 1,0,8,0 %; ! Current power state macro IPMI$GCH_STAT_RSP$V_ON = 1,0,1,0 %; ! Power is on macro IPMI$GCH_STAT_RSP$V_OVR = 1,1,1,0 %; ! Power Overload macro IPMI$GCH_STAT_RSP$V_P_LOCK = 1,2,1,0 %; ! Power interlock (IPMI 1.5) macro IPMI$GCH_STAT_RSP$V_P_FLT = 1,3,1,0 %; ! Power Fault macro IPMI$GCH_STAT_RSP$V_P_CFLT = 1,4,1,0 %; ! Power Control Fault macro IPMI$GCH_STAT_RSP$V_P_POLICY = 1,5,2,0 %; literal IPMI$GCH_STAT_RSP$S_P_POLICY = 2; ! Power Restore Policy macro IPMI$GCH_STAT_RSP$B_LST_PWR = 2,0,8,0 %; ! Last power event macro IPMI$GCH_STAT_RSP$V_AC = 2,0,1,0 %; ! AC failed macro IPMI$GCH_STAT_RSP$V_L_OVR = 2,1,1,0 %; ! Last power down caused by Power Overload macro IPMI$GCH_STAT_RSP$V_L_P_LCK = 2,2,1,0 %; ! Last power down caused by Power interlock (IPMI 1.5) macro IPMI$GCH_STAT_RSP$v_l_P_FLT = 2,3,1,0 %; ! Last power down caused by Power Fault macro IPMI$GCH_STAT_RSP$V_IPMI = 2,4,1,0 %; ! Last 'power is on' state was done via IPMI macro IPMI$GCH_STAT_RSP$B_CHAS_STA = 3,0,8,0 %; ! Misc Chassis State macro IPMI$GCH_STAT_RSP$V_INTRUDE = 3,0,1,0 %; ! Chassis intrusion active macro IPMI$GCH_STAT_RSP$V_FP_LCK = 3,1,1,0 %; ! Front Panel Lockout Active macro IPMI$GCH_STAT_RSP$V_DRIVE = 3,2,1,0 %; ! Drive fault macro IPMI$GCH_STAT_RSP$V_FAN = 3,3,1,0 %; ! Cooling/Fan Fault detected macro IPMI$GCH_STAT_RSP$B_FRNT_PANL = 4,0,8,0 %; ! Front Panel Button Capabilities and disable/enable status (Optional) ! ! IPMI Get event receiver command response ! macro IPMI$G_EV_R_RSP$B_SLAVE_ADR = 1,0,8,0 %; ! Event receiver slave address macro IPMI$G_EV_R_RSP$B_B2 = 2,0,8,0 %; macro IPMI$G_EV_R_RSP$V_LUN = 2,0,2,0 %; literal IPMI$G_EV_R_RSP$S_LUN = 2; ! LUN of event receiver ! ! IPMI Get Device SDR info command response ! macro IPMI$GD_SDR_I_RSP$B_COUNT = 1,0,8,0 %; ! Number of Sensors per LUN or SDRs in the device macro IPMI$GD_SDR_I_RSP$B_FLAG = 2,0,8,0 %; macro IPMI$GD_SDR_I_RSP$V_LUN0 = 2,0,1,0 %; ! 1 = Device LUN 0 has sensors macro IPMI$GD_SDR_I_RSP$V_LUN1 = 2,1,1,0 %; ! 1 = Device LUN 1 has sensors macro IPMI$GD_SDR_I_RSP$V_LUN2 = 2,2,1,0 %; ! 1 = Device LUN 2 has sensors macro IPMI$GD_SDR_I_RSP$V_LUN3 = 2,3,1,0 %; ! 1 = Device LUN 3 has sensors macro IPMI$GD_SDR_I_RSP$V_POP = 2,7,1,0 %; ! Dynamic or static Sensor population macro IPMI$GD_SDR_I_RSP$L_CHANGE = 3,0,32,0 %; ! Sensor population change indicator ! ! IPMI Get sensor reading factors command response ! macro IPMI$G_SEN_RF_RSP$B_NREAD = 1,0,8,0 %; ! Next reading factor macro IPMI$G_SEN_RF_RSP$B_M_LS = 2,0,8,0 %; ! M: ls 8 bits macro IPMI$G_SEN_RF_RSP$B_BYTE4 = 3,0,8,0 %; macro IPMI$G_SEN_RF_RSP$V_TOL = 3,0,6,0 %; literal IPMI$G_SEN_RF_RSP$S_TOL = 6; ! Tolerance macro IPMI$G_SEN_RF_RSP$V_M_MS = 3,6,2,0 %; literal IPMI$G_SEN_RF_RSP$S_M_MS = 2; ! M: ms 2 bits macro IPMI$G_SEN_RF_RSP$B_B_LS = 4,0,8,0 %; ! B: ls 8 bits macro IPMI$G_SEN_RF_RSP$B_BYTE6 = 5,0,8,0 %; macro IPMI$G_SEN_RF_RSP$V_ACC_LS = 5,0,6,0 %; literal IPMI$G_SEN_RF_RSP$S_ACC_LS = 6; ! Accuracy ls 6 bits macro IPMI$G_SEN_RF_RSP$V_B_MS = 5,6,2,0 %; literal IPMI$G_SEN_RF_RSP$S_B_MS = 2; ! B: ms 2 bits macro IPMI$G_SEN_RF_RSP$B_BYTE7 = 6,0,8,0 %; macro IPMI$G_SEN_RF_RSP$V_RSVD = 6,0,2,0 %; literal IPMI$G_SEN_RF_RSP$S_RSVD = 2; ! Reserved macro IPMI$G_SEN_RF_RSP$V_ACC_EXP = 6,2,2,0 %; literal IPMI$G_SEN_RF_RSP$S_ACC_EXP = 2; ! Accuracy exponent 2 bits, unsigned macro IPMI$G_SEN_RF_RSP$V_ACC_MS = 6,4,4,0 %; literal IPMI$G_SEN_RF_RSP$S_ACC_MS = 4; ! Accuracy ms 4 bits macro IPMI$G_SEN_RF_RSP$B_BYTE8 = 7,0,8,0 %; macro IPMI$G_SEN_RF_RSP$V_B_EXP = 7,0,4,0 %; literal IPMI$G_SEN_RF_RSP$S_B_EXP = 4; ! B exponent 4 bits, signed macro IPMI$G_SEN_RF_RSP$V_RESULT = 7,4,4,0 %; literal IPMI$G_SEN_RF_RSP$S_RESULT = 4; ! Result exponent 4 bits, signed ! ! IPMI Get sensor hysteresis command response ! macro IPMI$G_SEN_H_RSP$B_POS = 1,0,8,0 %; ! Positive-going hystereris value macro IPMI$G_SEN_H_RSP$B_NEG = 2,0,8,0 %; ! Negative-going hystereris value ! ! IPMI Get sensor threshold command response ! macro IPMI$G_SEN_TH_RSP$B_B2 = 1,0,8,0 %; macro IPMI$G_SEN_TH_RSP$V_L_NC_TF = 1,0,1,0 %; ! 1 = Lower non-critical threshold macro IPMI$G_SEN_TH_RSP$V_L_C_TF = 1,1,1,0 %; ! 1 = Lower critical threshold macro IPMI$G_SEN_TH_RSP$V_L_NR_TF = 1,2,1,0 %; ! 1 = Lower non-recoverable threshold macro IPMI$G_SEN_TH_RSP$V_U_NC_TF = 1,3,1,0 %; ! 1 = Upper non-critical threshold macro IPMI$G_SEN_TH_RSP$V_U_C_TF = 1,4,1,0 %; ! 1 = Upper critical threshold macro IPMI$G_SEN_TH_RSP$V_U_NR_TF = 1,5,1,0 %; ! 1 = Upper non-recoverable threshold macro IPMI$G_SEN_TH_RSP$B_L_NC_THRES = 2,0,8,0 %; ! Lower non-critical threshold macro IPMI$G_SEN_TH_RSP$B_L_C_THRES = 3,0,8,0 %; ! Lower critical threshold macro IPMI$G_SEN_TH_RSP$B_L_NR_THRES = 4,0,8,0 %; ! Lower non-recoverable threshold macro IPMI$G_SEN_TH_RSP$B_U_NC_THRES = 5,0,8,0 %; ! Upper non-critical threshold macro IPMI$G_SEN_TH_RSP$B_U_C_THRES = 6,0,8,0 %; ! Upper critical threshold macro IPMI$G_SEN_TH_RSP$B_U_NR_THRES = 7,0,8,0 %; ! Upper non-recoverable threshold ! ! IPMI Get sensor event enable command response ! macro IPMI$G_SEN_EE_RSP$B_B2 = 1,0,8,0 %; macro IPMI$G_SEN_EE_RSP$V_RSVD = 1,0,6,0 %; literal IPMI$G_SEN_EE_RSP$S_RSVD = 6; ! Reserved macro IPMI$G_SEN_EE_RSP$V_SCAN_DIS = 1,6,1,0 %; ! 0 = sensor scanning disabled macro IPMI$G_SEN_EE_RSP$V_ALL_DIS = 1,7,1,0 %; ! 0 = all event messages disabled macro IPMI$G_SEN_EE_RSP$W_ASSERT = 2,0,16,0 %; ! assertion events enabled macro IPMI$G_SEN_EE_RSP$W_DEASSERT = 4,0,16,0 %; ! deassertion events enabled ! ! IPMI Get sensor event status command response ! macro IPMI$G_SEN_ES_RSP$B_B2 = 1,0,8,0 %; macro IPMI$G_SEN_ES_RSP$V_RSVD = 1,0,5,0 %; literal IPMI$G_SEN_ES_RSP$S_RSVD = 5; ! Reserved macro IPMI$G_SEN_ES_RSP$V_BUSY = 1,5,1,0 %; ! 1 = reading/state unavailable (busy being updated) macro IPMI$G_SEN_ES_RSP$V_SCAN_DIS = 1,6,1,0 %; ! 0 = sensor scanning disabled macro IPMI$G_SEN_ES_RSP$V_ALL_DIS = 1,7,1,0 %; ! 0 = all event messages disabled macro IPMI$G_SEN_ES_RSP$W_ASSERT = 2,0,16,0 %; ! assertion events occurred macro IPMI$G_SEN_ES_RSP$W_DEASSERT = 4,0,16,0 %; ! deassertion events occurred ! ! IPMI Get sensor reading command response ! macro IPMI$G_SEN_R_RSP$B_VALUE = 1,0,8,0 %; ! Sensor value (ignore if not analog sensor) macro IPMI$G_SEN_R_RSP$B_B3 = 2,0,8,0 %; macro IPMI$G_SEN_R_RSP$V_RSVD = 2,0,5,0 %; literal IPMI$G_SEN_R_RSP$S_RSVD = 5; ! Reserved macro IPMI$G_SEN_R_RSP$V_BUSY = 2,5,1,0 %; ! 1 = reading/state unavailable (busy being updated) macro IPMI$G_SEN_R_RSP$V_SCAN_DIS = 2,6,1,0 %; ! 0 = sensor scanning disabled macro IPMI$G_SEN_R_RSP$V_ALL_DIS = 2,7,1,0 %; ! 0 = all event messages disabled macro IPMI$G_SEN_R_RSP$W_ASSERT = 3,0,16,0 %; ! assertion events occurred macro IPMI$G_SEN_R_RSP$W_DEASSERT = 5,0,16,0 %; ! deassertion events occurred ! ! IPMI Get sensor type command response ! macro IPMI$G_SEN_TY_RSP$B_SENSOR_TYPE = 1,0,8,0 %; ! Sensor type code macro IPMI$G_SEN_TY_RSP$B_B3 = 2,0,8,0 %; macro IPMI$G_SEN_TY_RSP$V_EVENT_TYPE = 2,0,7,0 %; literal IPMI$G_SEN_TY_RSP$S_EVENT_TYPE = 7; ! Event/reading type code ! ! IPMI Get FRU Inventory Area command response ! macro IPMI$GFRU_I_RSP$W_AREA_SZE = 1,0,16,0 %; ! FRU Inventory area size macro IPMI$GFRU_I_RSP$B_FLG = 3,0,8,0 %; macro IPMI$GFRU_I_RSP$V_WRD_ACC = 3,0,1,0 %; ! Device is accessed by words not bytes. ! ! IPMI Read FRU data command response ! macro IPMI$RFRU_RSP$B_CNT = 1,0,8,0 %; ! Count of how many FRU bytes read macro IPMI$RFRU_RSP$B_DATA = 2,0,0,0 %; literal IPMI$RFRU_RSP$S_DATA = 256; ! Possible returned from the FRU read (typical 32 max) ! ! IPMI Get SDR Repository Info command response ! macro IPMI$GSDR_I_RSP$B_SDR_VER = 1,0,8,0 %; ! Combined SDR version macro IPMI$GSDR_I_RSP$V_SDR_V_MAJOR = 1,0,4,0 %; literal IPMI$GSDR_I_RSP$S_SDR_V_MAJOR = 4; ! SDR Version Major macro IPMI$GSDR_I_RSP$V_SDR_V_MINOR = 1,4,4,0 %; literal IPMI$GSDR_I_RSP$S_SDR_V_MINOR = 4; ! SDR Version Minor macro IPMI$GSDR_I_RSP$W_RECORD_CNT = 2,0,16,0 %; ! Number of records in the SDR Repository macro IPMI$GSDR_I_RSP$W_FREE_SPACE = 4,0,16,0 %; ! Free space left in bytes macro IPMI$GSDR_I_RSP$L_ADD_TIME = 6,0,32,0 %; ! Most recent addition timestamp macro IPMI$GSDR_I_RSP$L_ERASE_TIME = 10,0,32,0 %; ! Most recent erase(delete or clear) timestamp macro IPMI$GSDR_I_RSP$B_OP_SUP = 14,0,8,0 %; ! Operation Supported macro IPMI$GSDR_I_RSP$V_ALLOC_INFO = 14,0,1,0 %; ! Get SDR Repository Allocation Information command supported macro IPMI$GSDR_I_RSP$V_RES = 14,1,1,0 %; ! Reserve SDR Repository command supported macro IPMI$GSDR_I_RSP$V_P_ADD = 14,2,1,0 %; ! Partial add SDR command supported macro IPMI$GSDR_I_RSP$V_DEL = 14,3,1,0 %; ! Delete SDR command supported macro IPMI$GSDR_I_RSP$V_NONMODAL = 14,5,1,0 %; ! Non-Modal SDR Repository update operation supported macro IPMI$GSDR_I_RSP$V_MODAL = 14,6,1,0 %; ! Modal SDR Repository update operation supported macro IPMI$GSDR_I_RSP$V_OVR = 14,7,1,0 %; ! Overflow Flag; SDR could not be written due to lack of space ! ! IPMI Get SDR Repository Allocation Info command response ! macro IPMI$GSDR_A_RSP$W_ALLOC = 1,0,16,0 %; ! Number of posible allocation units macro IPMI$GSDR_A_RSP$W_UNIT_SIZE = 3,0,16,0 %; ! Allocation unit size in bytes macro IPMI$GSDR_A_RSP$W_F_UNITS = 5,0,16,0 %; ! Number of free allocation units macro IPMI$GSDR_A_RSP$W_F_BLOCK = 7,0,16,0 %; ! Largest free block in allocation units macro IPMI$GSDR_A_RSP$B_MAX_SIZE = 9,0,8,0 %; ! Maximum record size in allocation units ! ! IPMI Reserve SDR Repository command response ! and/or ! IPMI Reserve Device SDR repository command response ! macro IPMI$RESSDR_R_RSP$W_RES_ID = 1,0,16,0 %; ! Reservation id ! ! IPMI Get SDR command response ! and/or ! IPMI Get Device SDR response ! macro IPMI$GSDR_RSP$W_REC_ID = 1,0,16,0 %; ! Record ID of the next record in the SDR macro IPMI$GSDR_RSP$B_DATA = 3,0,0,0 %; literal IPMI$GSDR_RSP$S_DATA = 256; ! Possible returned from the get SDR (typical 32 max) ! ! IPMI Get SDR Repository Time command response ! macro IPMI$GSDR_T_RSP$L_TIME = 1,0,32,0 %; ! Present time ! ! IPMI Get SEL Info command response ! macro IPMI$GSEL_I_RSP$B_SEL_VER = 1,0,8,0 %; ! Combined SEL version macro IPMI$GSEL_I_RSP$V_SEL_V_MAJOR = 1,0,4,0 %; literal IPMI$GSEL_I_RSP$S_SEL_V_MAJOR = 4; ! SEL Version Major macro IPMI$GSEL_I_RSP$V_SEL_V_MINOR = 1,4,4,0 %; literal IPMI$GSEL_I_RSP$S_SEL_V_MINOR = 4; ! SEL Version Minor macro IPMI$GSEL_I_RSP$W_ENTRY_CNT = 2,0,16,0 %; ! Number of log entries macro IPMI$GSEL_I_RSP$W_FREE_SPACE = 4,0,16,0 %; ! Free space left in bytes macro IPMI$GSEL_I_RSP$L_ADD_TIME = 6,0,32,0 %; ! Most recent addition timestamp macro IPMI$GSEL_I_RSP$L_ERASE_TIME = 10,0,32,0 %; ! Most recent erase(delete or clear) timestamp macro IPMI$GSEL_I_RSP$B_OP_SUP = 14,0,8,0 %; ! Operation Support macro IPMI$GSEL_I_RSP$V_ALLOC_INFO = 14,0,1,0 %; ! Get SEL Allocation Information command supported macro IPMI$GSEL_I_RSP$V_RES = 14,1,1,0 %; ! Resereve SEL command supported macro IPMI$GSEL_I_RSP$V_P_ADD = 14,2,1,0 %; ! Partial add SEL command supported macro IPMI$GSEL_I_RSP$V_DEL = 14,3,1,0 %; ! Delete SEL command supported macro IPMI$GSEL_I_RSP$V_OVR = 14,7,1,0 %; ! Overflow Flag; Events have been dropped due to lack of space ! ! IPMI Get SEL Allocation Info command response ! macro IPMI$GSEL_A_RSP$W_ALLOC_UNITS = 1,0,16,0 %; ! Number of posible allocation units macro IPMI$GSEL_A_RSP$W_UNIT_SIZE = 3,0,16,0 %; ! Allocation unit size in bytes macro IPMI$GSEL_A_RSP$W_F_UNITS = 5,0,16,0 %; ! Number of free allocation units macro IPMI$GSEL_A_RSP$W_F_BLOCK = 7,0,16,0 %; ! Largest free block in allocation units macro IPMI$GSEL_A_RSP$B_MAX_SIZE = 9,0,8,0 %; ! Maximum record size in allocation units ! ! IPMI Reserve SEL command response ! macro IPMI$RESSEL_RSP$W_RES_ID = 1,0,16,0 %; ! Reservation id ! ! IPMI Get SEL command response ! macro IPMI$GSEL_RSP$W_REC_ID = 1,0,16,0 %; ! Record ID of the next record in the SEL macro IPMI$GSEL_RSP$B_DATA = 3,0,0,0 %; literal IPMI$GSEL_RSP$S_DATA = 16; ! Data returned from the Get SEL record ! ! IPMI Add SEL command response ! macro IPMI$ASEL_RSP$W_REC_ID = 1,0,16,0 %; ! Record ID of the SEL record added ! ! IPMI Delete SEL command response ! macro IPMI$DSEL_RSP$W_REC_ID = 1,0,16,0 %; ! Record ID for the deleted SEL record ! ! IPMI Clear SEL command response ! macro IPMI$CSEL_RSP$V_E_PRGRESS = 1,0,4,0 %; literal IPMI$CSEL_RSP$S_E_PRGRESS = 4; ! Erasure Progress 1 == erase completed ! ! IPMI Get SEL Time command response ! macro IPMI$GSEL_T_RSP$L_TIME = 1,0,32,0 %; ! Present time ! ! IPMI Get Token Info command response ! macro IPMI$GTOKEN_I_RSP$B_ATTR = 1,0,8,0 %; ! Token attributes macro IPMI$GTOKEN_I_RSP$V_R_GUEST = 1,0,1,0 %; ! Read access: Guest macro IPMI$GTOKEN_I_RSP$V_R_USER = 1,1,1,0 %; ! Read access: User macro IPMI$GTOKEN_I_RSP$V_R_ADMIN = 1,2,1,0 %; ! Read access: Administrator macro IPMI$GTOKEN_I_RSP$V_W_GUEST = 1,3,1,0 %; ! Write access: Guest macro IPMI$GTOKEN_I_RSP$V_W_USER = 1,4,1,0 %; ! Write access: User macro IPMI$GTOKEN_I_RSP$V_W_ADMIN = 1,5,1,0 %; ! Write access: Administrator macro IPMI$GTOKEN_I_RSP$V_CHECKSUM = 1,6,1,0 %; ! Token is checksumed macro IPMI$GTOKEN_I_RSP$V_E_INFO = 1,7,1,0 %; ! Extended info available (not used) ! ! IPMI Read Token command response ! macro IPMI$RTOKEN_RSP$B_DATA = 1,0,0,0 %; literal IPMI$RTOKEN_RSP$S_DATA = 256; ! Possible returned from the read token (typical 30 max) ! ! IPMI Partial Read Token command response ! macro IPMI$P_RTOKEN_RSP$B_DATA = 1,0,0,0 %; literal IPMI$P_RTOKEN_RSP$S_DATA = 256; ! Possible returned from the partial read token (typical 30 max) ! ! IPMI Lock Property command response ! macro IPMI$L_PROP_RSP$L_LOCK = 1,0,32,0 %; ! Lock number if lock succeeds macro IPMI$L_PROP_RSP$L_LOCK_TIME = 5,0,32,0 %; ! Time the last lock of this property was given macro IPMI$L_PROP_RSP$B_SW_ID = 9,0,0,0 %; literal IPMI$L_PROP_RSP$S_SW_ID = 128; ! Software ID of last requester ! ! IPMI Get Property command response ! macro IPMI$G_PROP_RSP$W_CNT = 1,0,16,0 %; ! Count of how many Get Property bytes returned macro IPMI$G_PROP_RSP$B_DATA = 3,0,0,0 %; literal IPMI$G_PROP_RSP$S_DATA = 254; ! Possible returned data from the Get Property ! ! ! + ! IPMI IMB command codes ! - ! literal IPMI$K_CMD_G_DEVICE_ID = 1; ! Get device ID command literal IPMI$K_CMD_COLD_RESET = 2; ! Cold reset (unsupported) literal IPMI$K_CMD_WARM_RESET = 3; ! Warm reset (unsupported) literal IPMI$K_CMD_G_SELFTEST = 4; ! Get selftest results literal IPMI$K_CMD_MFG_ON = 5; ! Manufacturing Test on (unsupported) literal IPMI$K_CMD_S_ACPI_POWER = 6; ! Set acpi power state literal IPMI$K_CMD_G_ACPI_POWER = 7; ! Get acpi power state literal IPMI$K_CMD_G_DEVICE_GUID = 8; ! Get device guid literal IPMI$K_CMD_R_WATCHDOG = 34; ! Reset Watchdog timer (unsupported) literal IPMI$K_CMD_S_WATCHDOG = 36; ! Set Watchdog timer (unsupported) literal IPMI$K_CMD_G_WATCHDOG = 37; ! Get Watchdog timer literal IPMI$K_CMD_G_BT_CAPABILITY = 54; ! Get bt capability literal IPMI$K_CMD_G_SYSTEM_GUID = 55; ! Get system guid literal IPMI$K_CMD_G_CHASSIS_CAPA = 0; ! Get chassis capability literal IPMI$K_CMD_G_CHASSIS_STAT = 1; ! Get chassis status literal IPMI$K_CMD_CHASSIS_CTRL = 2; ! Chassis control literal IPMI$K_CMD_CHASSIS_RESET = 3; ! Chassis reset (obsolete) literal IPMI$K_CMD_CHAS_ID = 4; ! Chassis Identify command literal IPMI$K_CMD_S_EVENT_RCVR = 0; ! Set event receiver literal IPMI$K_CMD_G_EVENT_RCVR = 1; ! Get event receiver literal IPMI$K_CMD_PLATFORM_EVENT = 2; ! Platform event or event messenger literal IPMI$K_CMD_G_DEV_SDR_INFO = 32; ! Get Device SDR info literal IPMI$K_CMD_G_DEV_SDR = 33; ! Get Device SDR literal IPMI$K_CMD_RES_DEV_SDR_REPOS = 34; ! Reserve Device SDR repository literal IPMI$K_CMD_G_SENSOR_READ_FAC = 35; ! Get sensor reading factors literal IPMI$K_CMD_S_SENSOR_HYSTER = 36; ! Set sensor hysteresis literal IPMI$K_CMD_G_SENSOR_HYSTER = 37; ! Get sensor hysteresis literal IPMI$K_CMD_S_SENSOR_THRES = 38; ! Set sensor threshold literal IPMI$K_CMD_G_SENSOR_THRES = 39; ! Get sensor threshold literal IPMI$K_CMD_S_SENSOR_EVENT_ENA = 40; ! Set sensor event enable literal IPMI$K_CMD_G_SENSOR_EVENT_ENA = 41; ! Get sensor event enable literal IPMI$K_CMD_RARM_SENSOR_EVENT = 42; ! Re-arm sensor events literal IPMI$K_CMD_G_SENSOR_EVENT_STAT = 43; ! Get sensor event status literal IPMI$K_CMD_G_SENSOR_READING = 45; ! Get sensor reading literal IPMI$K_CMD_S_SENSOR_TYPE = 46; ! Set sensor type literal IPMI$K_CMD_G_SENSOR_TYPE = 47; ! Get sensor type literal IPMI$K_CMD_G_FRU_INV = 16; ! Get FRU Inventory Area command literal IPMI$K_CMD_READ_FRU = 17; ! Read FRU data command literal IPMI$K_CMD_G_SDR_REPOS_INFO = 32; ! Get SDR repository info literal IPMI$K_CMD_G_SDR_REPOS_ALLOC = 33; ! Get SDR repository allocation info literal IPMI$K_CMD_RES_SDR_REPOS = 34; ! Reserve SDR repository literal IPMI$K_CMD_G_SDR_ENTRY = 35; ! Get SDR entry command literal IPMI$K_CMD_G_SDR_REPOS_TIME = 40; ! Get SDR repository Time literal IPMI$K_CMD_G_SEL_INFO = 64; ! Get SEL info literal IPMI$K_CMD_G_SEL_ALLOC_INFO = 65; ! Get SEL allocation info literal IPMI$K_CMD_RES_SEL = 66; ! Reserve SEL literal IPMI$K_CMD_G_SEL_ENTRY = 67; ! Get SEL entry command literal IPMI$K_CMD_A_SEL_ENTRY = 68; ! Add SEL entry command literal IPMI$K_CMD_DEL_SEL_ENTRY = 70; ! delete SEL entry command literal IPMI$K_CMD_CLEAR_SEL = 71; ! Clear SEL command literal IPMI$K_CMD_G_SEL_TIME = 72; ! Get SEL time literal IPMI$K_CMD_S_SEL_TIME = 73; ! Set SEL time literal IPMI$K_CMD_A_FPL_ENTRY = 196; ! Add FPL entry command literal IPMI$K_CMD_GET_TOKEN_INFO = 1; ! Get Token Info command literal IPMI$K_CMD_READ_TOKEN = 2; ! Read Token command literal IPMI$K_CMD_PART_READ_TOKEN = 8; ! Partial Read Token command literal IPMI$K_CMD_LOCK_PROPERTY = 0; ! Lock Property command literal IPMI$K_CMD_UNLOCK_PROPERTY = 1; ! Unlock Property command literal IPMI$K_CMD_GET_PROPERTY = 2; ! Get Property command ! ! ! + ! IPMI IMB Completion Codes ! - ! These are the generic Completion codes. Codes specific to a ! message are listed below. ! literal IPMI$K_CCODE_OK = 0; ! Good response literal IPMI$K_CCODE_NO_DATA = 128; ! No data literal IPMI$K_CCODE_BUSY = 192; ! device is busy literal IPMI$K_CCODE_CMD_INVALID = 193; literal IPMI$K_CCODE_CMD_LUN_INVALID = 194; literal IPMI$K_CCODE_TIMEOUT = 195; literal IPMI$K_CCODE_NOSPACE = 196; literal IPMI$K_CCODE_RESID_BAD = 197; literal IPMI$K_CCODE_DATA_TRUNC = 198; literal IPMI$K_CCODE_DATALEN_INVALID = 199; literal IPMI$K_CCODE_DATALEN_EXCEED = 200; literal IPMI$K_CCODE_PARAM_BAD_RANGE = 201; literal IPMI$K_CCODE_DATA_BAD_RET = 202; literal IPMI$K_CCODE_OBJ_NOEXIST = 203; literal IPMI$K_CCODE_DATAFIELD_INVALID = 204; literal IPMI$K_CCODE_CMD_OBJ_INVALID = 205; literal IPMI$K_CCODE_NO_RESPONSE = 206; literal IPMI$K_CCODE_DUP_REQUEST = 207; literal IPMI$K_CCODE_SDR_NO_RESPONSE = 208; literal IPMI$K_CCODE_FW_NO_RESPONSE = 209; literal IPMI$K_CCODE_INIT_NO_RESPONSE = 210; literal IPMI$K_CCODE_NO_DEST = 211; literal IPMI$K_CCODE_NO_PRIV = 212; literal IPMI$K_CCODE_NOSUPPORT_STATE = 213; literal IPMI$K_CCODE_DISABLED = 214; literal IPMI$K_CCODE_UNKNOWN = 255; ! Unknown Completion code ! ! ! Specific Completion codes ! literal IPMI$K_CCODE_TOKEN_BAD_CHKSUM = 112; ! Invalid Token checksum literal IPMI$K_CCODE_FRU_BUSY = 129; ! FRU device is busy literal IPMI$K_CCODE_SEL_ERASING = 129; ! Cannot execute command, SEL erase in progress literal IPMI$K_CCODE_SEL_NOSUPPORT = 128; ! SEL Option not supported ! ! ! ! ! + ! These are the QIO IOCTL commands that the IPMI driver supports ! - ! literal IPMI$K_IOCTL_SEND_MESSAGE_CMD = 100; literal IPMI$K_IOCTL_IPMI_VERSION_CMD = 101; ! ! + ! IPMI Slave Address ! - ! literal IPMI$K_BMC_SA = 32; ! BMC slave address literal IPMI$K_MP_SA = 70; ! MP slave address (foundation systems) ! ! + ! The Logical Unit Number LUN. This is a sub-address that allows ! messages to be routed to different "logical units" that reside ! behind the same I2C slave address. ! - ! literal IPMI$K_BMC_LUN = 0; ! BMC only responds to this LUN literal IPMI$K_OEM1_LUN = 1; ! OEM1 defined LUN literal IPMI$K_SMS_LUN = 2; ! BMC forwards to SMS buffer literal IPMI$K_OEM2_LUN = 3; ! OEM2 defined LUN ! ! + ! IPMI Network Function Codes. ! The network function is used to cluster commands into functional ! command sets. In a parsing hierarchy, the LUN field may be thought ! of as the selector for a particular Network Function handler in ! the node, and the Network Function may be considered the selector ! for a particular command set handler within the node. ! - ! literal IPMI$K_CHASSIS_NETFN = 0; literal IPMI$K_BRIDGE_NETFN = 2; literal IPMI$K_SE_NETFN = 4; literal IPMI$K_APP_NETFN = 6; literal IPMI$K_FIRMWARE_NETFN = 8; literal IPMI$K_STORAGE_NETFN = 10; literal IPMI$K_TRANSPORT_NETFN = 12; literal IPMI$K_OEM30_NETFN = 48; literal IPMI$K_OEM32_NETFN = 50; literal IPMI$K_OEM34_NETFN = 52; ! ! + ! IPMI versions that we support and see. ! - ! literal IPMI$K_VERSION_1_0 = 1; literal IPMI$K_VERSION_1_5 = 81; literal IPMI$K_VERSION_2_0 = 2; literal IPMI$K_VERSION_UNKNOWN = 255; ! ! + ! IPMI Event structures. ! The event IDs are allocated in the CCODE event database ! at http://callahan.rose.hp.com/FMT/eventdb/index.html ! Other constants here are defined in "Event Architecture ! Specification" Revision 1.70 (6/23/05) or later. ! - ! literal IPMI$E0$M_EVENT_ID = %X'3FFFF'; literal IPMI$E0$K_OS_BOOT_COMPLETE = 5857; ! See CCODE event database literal IPMI$E0$K_OS_OPENVMS_BUGCHECK = 7319; ! See CCODE event database literal IPMI$E0$K_OS_OPENVMS_SHUTDOWN = 7321; ! See CCODE event database literal IPMI$E0$M_RSVD1 = %X'7C0000'; literal IPMI$E0$M_TIME_FLG = %X'800000'; literal IPMI$E0$M_DATA_TYPE = %X'1F000000'; literal IPMI$E0$K_MAJOR_CHANGE = 20; ! Major change in system state literal IPMI$E0$M_ALERT_LVL = %X'E0000000'; literal IPMI$E0$K_MINOR_FORWARD = 0; ! Minor forward progress literal IPMI$E0$K_MAJOR_FORWARD = 1; ! Major forward progress literal IPMI$E0$K_INFORMATIONAL = 2; ! Informational event (VMS boot/shutdown) literal IPMI$E0$K_WARNING = 3; ! Warning (non-critical error) literal IPMI$E0$K_CRITICAL = 5; ! Critical (VMS system crash) literal IPMI$E0$K_FATAL = 7; ! Fatal literal IPMI$E0$M_SYSTEM_STATE = %X'F'; literal IPMI$E0$K_BOOT_COMPLETE = 1; ! Boot complete literal IPMI$E0$K_STATE_CHANGE = 12; ! State change literal IPMI$E0$M_LEDS_COMMAND = %X'3F0'; literal IPMI$E0$M_LCV = %X'400'; literal IPMI$E0$M_FLAGS = %X'3800'; literal IPMI$E0$M_RSVD2 = %X'C000'; literal IPMI$E0$K_CRITICAL_SHUTDOWN = 25; ! Critical shutdown (VMS system crash) literal IPMI$E0$K_SHUTDOWN = 26; ! Normal shutdown (VMS operator shutdown) literal IPMI$E0$K_LENGTH = 16; ! total length of e0 event struct literal IPMI$E0$S_E0_EVENT = 16; macro IPMI$E0$W_REC_ID = 0,0,16,0 %; ! Record ID for the E0 record macro IPMI$E0$B_REC_TYPE = 2,0,8,0 %; ! Record Type "E0 hex" macro IPMI$E0$B_REPORT_ID = 3,0,8,0 %; ! Reporting Entity ID macro IPMI$E0$V_EVENT_ID = 4,0,18,0 %; literal IPMI$E0$S_EVENT_ID = 18; ! Event ID macro IPMI$E0$V_TIME_FLG = 4,23,1,0 %; ! Timestamp flag macro IPMI$E0$V_DATA_TYPE = 4,24,5,0 %; literal IPMI$E0$S_DATA_TYPE = 5; ! Event Data type macro IPMI$E0$V_ALERT_LVL = 4,29,3,0 %; literal IPMI$E0$S_ALERT_LVL = 3; ! Alert level macro IPMI$E0$V_SYSTEM_STATE = 8,0,4,0 %; literal IPMI$E0$S_SYSTEM_STATE = 4; ! System state macro IPMI$E0$V_LEDS_COMMAND = 8,4,6,0 %; literal IPMI$E0$S_LEDS_COMMAND = 6; ! Deprecated macro IPMI$E0$V_LCV = 8,10,1,0 %; ! Deprecated macro IPMI$E0$V_FLAGS = 8,11,3,0 %; literal IPMI$E0$S_FLAGS = 3; ! nPar vs. cell macro IPMI$E0$B_STATE_CHANGE = 10,0,8,0 %; ! State change event macro IPMI$E0$B_ADDNL_TYPE = 11,0,8,0 %; ! Additional change information type macro IPMI$E0$L_ADDNL_INFO = 12,0,32,0 %; ! Additional change information literal IPMI$T2$M_EVENT_TYPE = %X'7F'; literal IPMI$T2$M_EVENT_DIR = %X'80'; literal IPMI$T2$K_LENGTH = 16; ! total length of Type 2 event struct literal IPMI$T2$S_T2_EVENT = 16; macro IPMI$T2$W_REC_ID = 0,0,16,0 %; ! Record ID for the Type 2 record macro IPMI$T2$B_REC_TYPE = 2,0,8,0 %; ! Record Type "02 hex" macro IPMI$T2$L_TIME = 3,0,32,0 %; ! Timestamp macro IPMI$T2$W_GENERATE_ID = 7,0,16,0 %; ! Generator ID macro IPMI$T2$B_REV = 9,0,8,0 %; ! Event message format rev macro IPMI$T2$B_SENSOR_TYPE = 10,0,8,0 %; ! Sensor Type macro IPMI$T2$B_SENSOR_NUM = 11,0,8,0 %; ! Sensor number macro IPMI$T2$V_EVENT_TYPE = 12,0,7,0 %; literal IPMI$T2$S_EVENT_TYPE = 7; ! Event type macro IPMI$T2$V_EVENT_DIR = 12,7,1,0 %; ! Event direction macro IPMI$T2$B_DATA1 = 13,0,8,0 %; ! Event data 1 macro IPMI$T2$B_DATA2 = 14,0,8,0 %; ! Event data 2 macro IPMI$T2$B_DATA3 = 15,0,8,0 %; ! Event data 3 ! ! ! Flags for Send/Get Messages for bridge IPMI commands ! literal IPMI$K_USE_SEND_MSG_CMD = 65536; literal IPMI$K_USE_GET_MSG_CMD = 131072; ! ! Flag for Satellite controller Support on Kauai Systems ! literal IPMI$K_SEND_TO_SAT_CNTRL = 262144; ! !*** MODULE $IRPEDEF *** ! + ! IRPE - I/O REQUEST PACKET EXTENSION ! ! I/O REQUEST PACKET EXTENSIONS ARE USED TO HOLD ADDITIONAL INFORMATION ! ABOUT I/O REQUESTS FOR DEVICES THAT REQUIRE MORE CONTEXT THAN CAN FIT INTO ! THE STANDARD IRP. IRPE'S ARE BUILT AND LINKED ONTO IRP'S BY DEVICE ! DRIVER FDT ROUTINES. ANY FIELDS THAT ARE NOT DEFINED IN THIS STRUCTURE ! MAY BE USED TO HOLD DRIVER DEPENDENT DATA. ! ! THE CURRENTLY DEFINED FIELDS IN THE IRPE WERE POSITIONED SO THAT THE ! PACKET COULD BE USED AS A FORK BLOCK. THIS SHOULD BE KEPT IN MIND IF ! AND WHEN NEW FIELDS ARE DEFINED. ! ! NOTE: Most of the fields of the IRPE must be at the same offsets as their ! corresponding fields in the IRP. The equivalency of these offsets is ! verified by ASSUME statements in the [LIB]VFY_IRP_A_LIKES.MAR module. ! These ASSUMEs may need to be altered as well whenever an IRPE or IRP field ! is removed or altered. ! - literal IRPE$M_FUNC = %X'2'; literal IRPE$M_EXTEND = %X'800'; literal IRPE$M_QSVD = %X'8000'; literal IRPE$M_QCOMPLEX = %X'10000'; literal IRPE$M_NORETRY = %X'20000'; literal IRPE$M_QBARRIER = %X'40000'; literal IRPE$S_IRPE = 208; macro IRPE$W_SIZE = 8,0,16,0 %; ! SIZE OF IRPE IN BYTES macro IRPE$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE FOR IRPE macro IRPE$B_RMOD = 11,0,8,0 %; ! RMOD BYTE macro IRPE$Q_DRIVER_P0 = 16,0,0,1 %; literal IRPE$S_DRIVER_P0 = 8; ! Available for driver-specific use macro IRPE$L_DRIVER_P0 = 16,0,32,0 %; ! (low-order 32-bits) macro IRPE$L_DRIVER_P1 = 20,0,32,0 %; ! (high-order 32-bits) macro IRPE$Q_DRIVER_P2 = 24,0,0,1 %; literal IRPE$S_DRIVER_P2 = 8; ! Available for driver-specific use macro IRPE$L_DRIVER_P2 = 24,0,32,0 %; ! (low-order 32-bits) macro IRPE$L_DRIVER_P3 = 28,0,32,0 %; ! (high-order 32-bits) macro IRPE$Q_STATUS = 80,0,0,0 %; literal IRPE$S_STATUS = 8; macro IRPE$L_STS = 80,0,32,0 %; ! Status bits macro IRPE$V_FUNC = 80,1,1,0 %; ! 1=>read function, 0=>write function macro IRPE$V_EXTEND = 80,11,1,0 %; ! ANOTHER IRPE IS LINKED TO THIS ONE macro IRPE$L_STS2 = 84,0,32,0 %; macro IRPE$V_QSVD = 84,15,1,0 %; ! Set if QIOserver function macro IRPE$V_QCOMPLEX = 84,16,1,0 %; ! Set if QIOserver complex function macro IRPE$V_NORETRY = 84,17,1,0 %; ! Do not retry this operation if QIOserver path fails macro IRPE$V_QBARRIER = 84,18,1,0 %; ! This is a QIOserver barrier operation macro IRPE$PQ_VA_PTE = 88,0,0,1 %; literal IRPE$S_VA_PTE = 8; ! 64-bit process virtual addr of PTE macro IRPE$L_SVAPTE = 96,0,32,1 %; ! 32-bit S0/S1 address of first PTE macro IRPE$PS_BUFIO_PKT = 96,0,32,1 %; ! Pointer to buffered I/O packet macro IRPE$L_BCNT = 100,0,32,0 %; ! Byte count for locked buffer macro IRPE$L_BOFF = 104,0,32,0 %; ! Byte offset in page for locked buffer macro IRPE$L_OBOFF = 108,0,32,0 %; ! Original BOFF, for segmented DIO macro IRPE$L_EXTEND = 112,0,32,1 %; ! ADDRESS OF NEXT IRPE macro IRPE$R_DIOBM = 120,0,0,0 %; literal IRPE$S_DIOBM = 88; ! Embedded DIOBM to handle cross-process 32-bit PTE access literal IRPE$K_LENGTH = 208; ! LENGTH OF IRPE literal IRPE$C_LENGTH = 208; ! LENGTH OF IRPE literal IRPE$S_IRPEDEF = 208; ! Old size name, synonym for IRPE$S_IRPE !*** MODULE $ISACFGDEF *** ! ! This file describes the layout of the configuration data blocks ! for ISA devices. There are two data structures described in this ! file. The first is the ISA_CFG_DATA block that VMS uses to store ! ISA configuration information for ISA devices. There is an ! ISA_CFG_DATA block for each ISA device in the system. The second data ! structure described in this file is the console supplied ISA config ! information, stored in nvram. The console ISA configuration ! information actually consists of a header and a number of entries. ! The console ISA config header is defined as ISACFG_HDR and the console ! ISA config entries are defined as ISACFG_ENTRY. ! ! During ISA configuration, data is read from the console ISA config ! information and stored in ISA_CFG_DATA blocks. Then, data is also ! read from the user-editable file SYS$MANAGER:ISA_CONFIG.DAT and stored ! in ISA_CFG_DATA blocks. Then the drivers are loaded for the ISA ! devices. ! ! The ISA_CFG_DATA block contains ISA Bus resource information ! for each device, sych as IRQ, DMA channels, IO Ports, Memory addr, ! slot number. ! literal ISACFG$S_ISA_CFG_DATA = 208; macro ISACFG$PS_FLINK = 0,0,32,1 %; macro ISACFG$PS_BLINK = 4,0,32,1 %; macro ISACFG$W_SIZE = 8,0,16,0 %; macro ISACFG$B_TYPE = 10,0,8,0 %; macro ISACFG$B_SUBTYPE = 11,0,8,0 %; macro ISACFG$L_IRQ = 12,0,32,0 %; macro ISACFG$L_MEMBUFF0 = 16,0,32,0 %; macro ISACFG$L_MEMLEN0 = 20,0,32,0 %; macro ISACFG$L_MEMBUFF1 = 24,0,32,0 %; macro ISACFG$L_MEMLEN1 = 28,0,32,0 %; macro ISACFG$L_MEMBUFF2 = 32,0,32,0 %; macro ISACFG$L_MEMLEN2 = 36,0,32,0 %; macro ISACFG$L_MEMBUFF3 = 40,0,32,0 %; macro ISACFG$L_MEMLEN3 = 44,0,32,0 %; macro ISACFG$L_DMACHAN0 = 48,0,32,0 %; macro ISACFG$L_DMACHAN1 = 52,0,32,0 %; macro ISACFG$L_DMACHAN2 = 56,0,32,0 %; macro ISACFG$L_DMACHAN3 = 60,0,32,0 %; macro ISACFG$W_IO_PORT0 = 64,0,16,0 %; macro ISACFG$W_IO_LEN0 = 66,0,16,0 %; macro ISACFG$W_IO_PORT1 = 68,0,16,0 %; macro ISACFG$W_IO_LEN1 = 70,0,16,0 %; macro ISACFG$W_IO_PORT2 = 72,0,16,0 %; macro ISACFG$W_IO_LEN2 = 74,0,16,0 %; macro ISACFG$W_IO_PORT3 = 76,0,16,0 %; macro ISACFG$W_IO_LEN3 = 78,0,16,0 %; macro ISACFG$W_IO_PORT4 = 80,0,16,0 %; macro ISACFG$W_IO_LEN4 = 82,0,16,0 %; macro ISACFG$W_IO_PORT5 = 84,0,16,0 %; macro ISACFG$W_IO_LEN5 = 86,0,16,0 %; macro ISACFG$W_IO_PORT6 = 88,0,16,0 %; macro ISACFG$W_IO_LEN6 = 90,0,16,0 %; macro ISACFG$W_IO_PORT7 = 92,0,16,0 %; macro ISACFG$W_IO_LEN7 = 94,0,16,0 %; macro ISACFG$W_IO_PORT8 = 96,0,16,0 %; macro ISACFG$W_IO_LEN8 = 98,0,16,0 %; macro ISACFG$B_DEV_NAME = 100,0,32,0 %; literal ISACFG$S_DEV_NAME = 4; macro ISACFG$B_DRIVER = 104,0,0,0 %; literal ISACFG$S_DRIVER = 16; macro ISACFG$L_FLAGS = 120,0,32,0 %; macro ISACFG$L_NODE = 124,0,32,0 %; macro ISACFG$B_USER_PARAM = 128,0,0,0 %; literal ISACFG$S_USER_PARAM = 72; macro ISACFG$L_IRQ2 = 200,0,32,0 %; macro ISACFG$L_RSV1 = 200,0,32,0 %; macro ISACFG$L_RSV2 = 204,0,32,0 %; literal ISA$K_ISA_CFG_DATA_LENGTH = 208; literal ISACFG$K_PORT = 0; literal ISACFG$K_MEM = 1; literal ISACFG$K_IRQ = 2; literal ISACFG$K_NAME = 3; literal ISACFG$K_NODE = 4; literal ISACFG$K_DRIVER = 5; literal ISACFG$K_DMA = 6; literal ISACFG$K_USER_PARAM = 7; literal ISACFG_HDR$S_ISACFG_HDR = 32; macro ISACFG_HDR$B_IDENTIFIER = 0,0,0,0 %; literal ISACFG_HDR$S_IDENTIFIER = 8; macro ISACFG_HDR$W_MAJOR_VERSION = 8,0,16,0 %; macro ISACFG_HDR$W_MINOR_VERSION = 10,0,16,0 %; macro ISACFG_HDR$l_fill1 = 12,0,32,0 %; macro ISACFG_HDR$L_NUM_ENTRIES = 16,0,32,0 %; macro ISACFG_HDR$L_FIRST_ENTRY_OFFSET = 20,0,32,0 %; macro ISACFG_HDR$L_TABLE_CHECKSUM = 24,0,32,0 %; macro ISACFG_HDR$L_HEADER_CHECKSUM = 28,0,32,0 %; literal ISACFG_HDR$K_LENGTH = 32; literal ISACFG_ENTRY$S_ISACFG_ENTRY = 200; macro ISACFG_ENTRY$L_ENTRY_TYPE = 0,0,32,0 %; macro ISACFG_ENTRY$L_RESERVED0 = 4,0,32,0 %; macro ISACFG_ENTRY$L_ISA_SLOT = 8,0,32,0 %; macro ISACFG_ENTRY$L_RESERVED1 = 12,0,32,0 %; macro ISACFG_ENTRY$L_DEV_NUM = 16,0,32,0 %; macro ISACFG_ENTRY$L_RESERVED2 = 20,0,32,0 %; macro ISACFG_ENTRY$L_TOTAL_DEVICES = 24,0,32,0 %; macro ISACFG_ENTRY$L_RESERVED3 = 28,0,32,0 %; macro ISACFG_ENTRY$Q_IO_BASE_ADDR0 = 32,0,0,0 %; literal ISACFG_ENTRY$S_IO_BASE_ADDR0 = 8; macro ISACFG_ENTRY$Q_IO_BASE_ADDR1 = 40,0,0,0 %; literal ISACFG_ENTRY$S_IO_BASE_ADDR1 = 8; macro ISACFG_ENTRY$Q_IO_BASE_ADDR2 = 48,0,0,0 %; literal ISACFG_ENTRY$S_IO_BASE_ADDR2 = 8; macro ISACFG_ENTRY$Q_IO_BASE_ADDR3 = 56,0,0,0 %; literal ISACFG_ENTRY$S_IO_BASE_ADDR3 = 8; macro ISACFG_ENTRY$Q_IO_BASE_ADDR4 = 64,0,0,0 %; literal ISACFG_ENTRY$S_IO_BASE_ADDR4 = 8; macro ISACFG_ENTRY$Q_IO_BASE_ADDR5 = 72,0,0,0 %; literal ISACFG_ENTRY$S_IO_BASE_ADDR5 = 8; macro ISACFG_ENTRY$Q_MEM0_BASE_ADDR = 80,0,0,0 %; literal ISACFG_ENTRY$S_MEM0_BASE_ADDR = 8; macro ISACFG_ENTRY$Q_MEM0_LENGTH = 88,0,0,0 %; literal ISACFG_ENTRY$S_MEM0_LENGTH = 8; macro ISACFG_ENTRY$Q_MEM1_BASE_ADDR = 96,0,0,0 %; literal ISACFG_ENTRY$S_MEM1_BASE_ADDR = 8; macro ISACFG_ENTRY$Q_MEM1_LENGTH = 104,0,0,0 %; literal ISACFG_ENTRY$S_MEM1_LENGTH = 8; macro ISACFG_ENTRY$Q_MEM2_BASE_ADDR = 112,0,0,0 %; literal ISACFG_ENTRY$S_MEM2_BASE_ADDR = 8; macro ISACFG_ENTRY$Q_MEM2_LENGTH = 120,0,0,0 %; literal ISACFG_ENTRY$S_MEM2_LENGTH = 8; macro ISACFG_ENTRY$Q_ROM_BASE_ADDR = 128,0,0,0 %; literal ISACFG_ENTRY$S_ROM_BASE_ADDR = 8; macro ISACFG_ENTRY$Q_ROM_LENGTH = 136,0,0,0 %; literal ISACFG_ENTRY$S_ROM_LENGTH = 8; macro ISACFG_ENTRY$L_DEVICE_ENABLE = 144,0,32,0 %; macro ISACFG_ENTRY$L_RESERVED4 = 148,0,32,0 %; macro ISACFG_ENTRY$L_DMA0 = 152,0,32,0 %; macro ISACFG_ENTRY$L_DMA1 = 156,0,32,0 %; macro ISACFG_ENTRY$L_DMA2 = 160,0,32,0 %; macro ISACFG_ENTRY$L_DMA3 = 164,0,32,0 %; macro ISACFG_ENTRY$L_IRQ0_ASSIGNMENT = 168,0,32,0 %; macro ISACFG_ENTRY$L_IRQ1_ASSIGNMENT = 172,0,32,0 %; macro ISACFG_ENTRY$L_IRQ2_ASSIGNMENT = 176,0,32,0 %; macro ISACFG_ENTRY$L_IRQ3_ASSIGNMENT = 180,0,32,0 %; macro ISACFG_ENTRY$B_HANDLE = 184,0,0,0 %; literal ISACFG_ENTRY$S_HANDLE = 16; literal ISACFG_ENTRY$K_LENGTH = 200; literal ISACFG$K_NOT_USED = 0; literal ISACFG$K_SINGLE_DEV = 1; literal ISACFG$K_MULTI_EMBED_DEV = 2; literal ISACFG$K_MULTI_DEV = 3; literal ISACFG$K_ISACFG_HDR_SIZE = 32; !*** MODULE $ISDDEF *** ! + ! IMAGE SECTION DESCRIPTOR DEFINITIONS ! - literal ISD$K_LENDZRO = 12; ! LENGTH OF DEMAND ZERO ISD literal ISD$C_LENDZRO = 12; ! LENGTH OF DEMAND ZERO ISD literal ISD$M_GBL = %X'1'; literal ISD$M_CRF = %X'2'; literal ISD$M_DZRO = %X'4'; literal ISD$M_WRT = %X'8'; literal ISD$M_MATCHCTL = %X'70'; literal ISD$M_LASTCLU = %X'80'; literal ISD$M_INITALCODE = %X'100'; literal ISD$M_BASED = %X'200'; literal ISD$M_FIXUPVEC = %X'400'; literal ISD$M_RESIDENT = %X'800'; literal ISD$M_VECTOR = %X'20000'; literal ISD$M_PROTECT = %X'40000'; literal ISD$S_FLAGSIZ = 24; ! NUMBER OF FLAG BITS, ISD TYPE EXCLUDED literal ISD$K_LENPRIV = 16; ! LENGTH OF PRIVATE ISD literal ISD$C_LENPRIV = 16; ! LENGTH OF PRIVATE ISD literal ISD$K_LENGLBL = 36; ! LENGTH OF OLD GLOBAL ISD literal ISD$C_LENGLBL = 36; ! LENGTH OF OLD GLOBAL ISD literal ISD$K_MAXLENGLBL = 64; ! MAX LENGTH OF NEW GLOBAL ISD literal ISD$C_MAXLENGLBL = 64; ! MAX LENGTH OF NEW GLOBAL ISD ! + literal ISD$K_MATALL = 0; ! MATCH ALWAYS, USE GLOBAL SECTION literal ISD$K_MATEQU = 1; ! MATCH IF ISD$L_IDENT EQU GBL ID literal ISD$K_MATLEQ = 2; ! MATCH IF ISD$L_IDENT LEQ GBL ID literal ISD$K_MATNEV = 3; ! MATCH NEVER, USE PRIVATE COPY ! + literal ISD$K_NORMAL = 0; ! NORMAL PROGRAM IMAGE SECTION ! NO SPECIAL ACTION REQUIRED literal ISD$K_SHRFXD = 1; ! SHAREABLE FIXED SECTION literal ISD$K_PRVFXD = 2; ! PRIVATE FIXED SECTION literal ISD$K_SHRPIC = 3; ! SHAREABLE PIC SECTION literal ISD$K_PRVPIC = 4; ! PRIVATE PIC SECTION literal ISD$K_USRSTACK = 253; ! USER STACK SECTION literal ISD$S_ISDDEF = 64; ! Old size name - synonym literal ISD$S_ISD = 64; macro ISD$W_SIZE = 0,0,16,0 %; ! SIZE IN BYTES OF THIS ISD macro ISD$W_PAGCNT = 2,0,16,0 %; ! ! OF PAGES DESCRIBED BY THIS ISD macro ISD$L_VPNPFC = 4,0,32,0 %; ! VPN & PFC VIELDS macro ISD$V_VPN = 4,0,21,0 %; literal ISD$S_VPN = 21; ! STARTING VIRTUAL PAGE NUMBER macro ISD$V_P1 = 4,21,1,0 %; ! P1 SPACE macro ISD$V_SYSTEM = 4,22,1,0 %; ! SYSTEM SPACE macro ISD$V_PFC = 4,24,8,0 %; literal ISD$S_PFC = 8; ! PAGE FAULT CLUSTER macro ISD$V_VPG = 4,0,23,0 %; literal ISD$S_VPG = 23; ! VIRTUAL PAGE INCLUDING P1 & S macro ISD$B_PFC = 7,0,8,0 %; ! PAGE FAULT CLUSTER macro ISD$L_FLAGS = 8,0,32,0 %; ! FLAGS AND ISD TYPE macro ISD$V_GBL = 8,0,1,0 %; ! GLOBAL macro ISD$V_CRF = 8,1,1,0 %; ! COPY ON REFERENCE macro ISD$V_DZRO = 8,2,1,0 %; ! DEMAND ZERO PAGE macro ISD$V_WRT = 8,3,1,0 %; ! WRITABLE macro ISD$V_MATCHCTL = 8,4,3,0 %; literal ISD$S_MATCHCTL = 3; ! IDENT MATCH CONTROL FIELD macro ISD$V_LASTCLU = 8,7,1,0 %; ! ISD IS PART OF LAST P0 SPACE CLUSTER macro ISD$V_INITALCODE = 8,8,1,0 %; ! ISD IS PART OF INITIALIZATION CODE macro ISD$V_BASED = 8,9,1,0 %; ! ISECT IS BASED macro ISD$V_FIXUPVEC = 8,10,1,0 %; ! ISECT IS FIXUP SECTION macro ISD$V_RESIDENT = 8,11,1,0 %; ! ISECT IS MEMORY-RESIDENT macro ISD$V_VECTOR = 8,17,1,0 %; ! VECTOR CONTAINED IN IMAGE SECTION macro ISD$V_PROTECT = 8,18,1,0 %; ! IMAGE SECTION IS PROTECTED macro ISD$B_TYPE = 11,0,8,0 %; ! ISD TYPE CODE macro ISD$L_VBN = 12,0,32,0 %; ! BASE VIRTUAL BLOCK NUMBER macro ISD$L_IDENT = 16,0,32,0 %; ! IDENT FOR GLOBAL SECTION macro ISD$T_GBLNAM = 20,0,0,0 %; literal ISD$S_GBLNAM = 44; ! GLOBAL NAME COUNTED STRING ! MATCH CONTROL VIELD VALUES ! - ! BASE OF ZERO , INCR 1 ! ISD TYPE FIELD DEFINITIONS ! - !*** MODULE ISDOLDDEF *** ! + ! OLD IMAGE SECTION DESCRIPTOR DEFINITIONS ! - literal ISD_K_LENDZRO = 12; ! LENGTH OF DEMAND ZERO ISD literal ISD_C_LENDZRO = 12; ! LENGTH OF DEMAND ZERO ISD literal ISD_M_GBL = %X'1'; literal ISD_M_CRF = %X'2'; literal ISD_M_DZRO = %X'4'; literal ISD_M_WRT = %X'8'; literal ISD_M_MATCHCTL = %X'70'; literal ISD_M_LASTCLU = %X'80'; literal ISD_M_COPYALWAY = %X'100'; literal ISD_M_BASED = %X'200'; literal ISD_M_FIXUPVEC = %X'400'; literal ISD_M_VECTOR = %X'20000'; literal ISD_M_PROTECT = %X'40000'; literal ISD_S_FLAGSIZ = 24; ! NUMBER OF FLAG BITS, ISD TYPE EXCLUDED literal ISD_K_LENPRIV = 16; ! LENGTH OF PRIVATE ISD literal ISD_C_LENPRIV = 16; ! LENGTH OF PRIVATE ISD literal ISD_K_LENGLBL = 36; ! LENGTH OF GLOBAL ISD literal ISD_C_LENGLBL = 36; ! LENGTH OF GLOBAL ISD ! + literal ISD_K_MATALL = 0; ! MATCH ALWAYS, USE GLOBAL SECTION literal ISD_K_MATEQU = 1; ! MATCH IF ISD_L_IDENT EQU GBL ID literal ISD_K_MATLEQ = 2; ! MATCH IF ISD_L_IDENT LEQ GBL ID literal ISD_K_MATNEV = 3; ! MATCH NEVER, USE PRIVATE COPY ! + literal ISD_K_NORMAL = 0; ! NORMAL PROGRAM IMAGE SECTION ! NO SPECIAL ACTION REQUIRED literal ISD_K_SHRFXD = 1; ! SHAREABLE FIXED SECTION literal ISD_K_PRVFXD = 2; ! PRIVATE FIXED SECTION literal ISD_K_SHRPIC = 3; ! SHAREABLE PIC SECTION literal ISD_K_PRVPIC = 4; ! PRIVATE PIC SECTION literal ISD_K_USRSTACK = 253; ! USER STACK SECTION literal ISD_S_ISDOLDDEF = 36; ! Old size name - synonym literal ISD_S_ISDOLD = 36; macro ISD_W_SIZE = 0,0,16,0 %; ! SIZE IN BYTES OF THIS ISD macro ISD_W_PAGCNT = 2,0,16,0 %; ! ! OF PAGES DESCRIBED BY THIS ISD macro ISD_R_VPNPFC_OVERLAY = 4,0,32,0 %; macro ISD_L_VPNPFC = 4,0,32,0 %; ! VPN & PFC VIELDS macro ISD_R_VPNPFC_BITS0 = 4,0,32,0 %; macro ISD_V_VPN = 4,0,21,0 %; literal ISD_S_VPN = 21; ! STARTING VIRTUAL PAGE NUMBER macro ISD_V_P1 = 4,21,1,0 %; ! P1 SPACE macro ISD_V_SYSTEM = 4,22,1,0 %; ! SYSTEM SPACE macro ISD_V_PFC = 4,24,8,0 %; literal ISD_S_PFC = 8; ! PAGE FAULT CLUSTER macro ISD_R_VPNPFC_BITS1 = 4,0,24,0 %; macro ISD_V_VPG = 4,0,23,0 %; literal ISD_S_VPG = 23; ! VIRTUAL PAGE INCLUDING P1 & S macro ISD_R_VPNPFC_FIELDS2 = 4,0,32,0 %; macro ISD_B_PFC = 7,0,8,0 %; ! PAGE FAULT CLUSTER macro ISD_R_FLAGS_OVERLAY = 8,0,32,0 %; macro ISD_L_FLAGS = 8,0,32,0 %; ! FLAGS AND ISD TYPE macro ISD_R_FLAGS_BITS = 8,0,24,0 %; macro ISD_V_GBL = 8,0,1,0 %; ! GLOBAL macro ISD_V_CRF = 8,1,1,0 %; ! COPY ON REFERENCE macro ISD_V_DZRO = 8,2,1,0 %; ! DEMAND ZERO PAGE macro ISD_V_WRT = 8,3,1,0 %; ! WRITABLE macro ISD_V_MATCHCTL = 8,4,3,0 %; literal ISD_S_MATCHCTL = 3; ! IDENT MATCH CONTROL FIELD macro ISD_V_LASTCLU = 8,7,1,0 %; ! ISD IS PART OF LAST P0 SPACE CLUSTER macro ISD_V_COPYALWAY = 8,8,1,0 %; ! COPY ALWAYS FROM USER IMAGE macro ISD_V_BASED = 8,9,1,0 %; ! ISECT IS BASED macro ISD_V_FIXUPVEC = 8,10,1,0 %; ! ISECT IS FIXUP SECTION macro ISD_V_VECTOR = 8,17,1,0 %; ! VECTOR CONTAINED IN IMAGE SECTION macro ISD_V_PROTECT = 8,18,1,0 %; ! IMAGE SECTION IS PROTECTED macro ISD_R_FLAGS_FIELDS = 8,0,32,0 %; macro ISD_B_TYPE = 11,0,8,0 %; ! ISD TYPE CODE macro ISD_L_VBN = 12,0,32,0 %; ! BASE VIRTUAL BLOCK NUMBER macro ISD_L_IDENT = 16,0,32,0 %; ! IDENT FOR GLOBAL SECTION macro ISD_T_GBLNAM = 20,0,0,0 %; literal ISD_S_GBLNAM = 16; ! GLOBAL NAME COUNTED STRING ! MATCH CONTROL VIELD VALUES ! - ! BASE OF ZERO , INCR 1 ! ISD TYPE FIELD DEFINITIONS ! - !*** MODULE $ISRDEF *** ! ! Definitions for Interruption Status Register ! literal ISR$M_CODE = %X'FFFF'; literal ISR$M_SHORT_CODE = %X'F'; literal ISR$M_SHORT_CODE4_7 = %X'F0'; literal ISR$M_HIGH_CODE = %X'FF00'; literal ISR$M_FD_DFL = %X'1'; literal ISR$M_FD_DFH = %X'2'; literal ISR$M_FF_VH = %X'1'; literal ISR$M_FF_DH = %X'2'; literal ISR$M_FF_ZH = %X'4'; literal ISR$M_FF_SWAH = %X'8'; literal ISR$M_FF_VL = %X'10'; literal ISR$M_FF_DL = %X'20'; literal ISR$M_FF_ZL = %X'40'; literal ISR$M_FF_SWAL = %X'80'; literal ISR$M_FT_FP = %X'1'; literal ISR$M_FT_MBZ1 = %X'2'; literal ISR$M_FT_MBZ2 = %X'4'; literal ISR$M_FT_SS = %X'8'; literal ISR$M_FT_MBZ4 = %X'10'; literal ISR$M_FT_MBZ5 = %X'20'; literal ISR$M_FT_MBZ6 = %X'40'; literal ISR$M_FT_OL = %X'80'; literal ISR$M_FT_UL = %X'100'; literal ISR$M_FT_IL = %X'200'; literal ISR$M_FT_FPAL = %X'400'; literal ISR$M_FT_OH = %X'800'; literal ISR$M_FT_UH = %X'1000'; literal ISR$M_FT_IH = %X'2000'; literal ISR$M_FT_FPAH = %X'4000'; literal ISR$M_FP = %X'1'; literal ISR$M_LP = %X'2'; literal ISR$M_TB = %X'4'; literal ISR$M_SS = %X'8'; literal ISR$M_UI = %X'10'; literal ISR$M_FILL1 = %X'FFE0'; literal ISR$M_VECTOR = %X'FF0000'; literal ISR$M_MBZ0 = %X'FF000000'; literal ISR$M_X = %X'100000000'; literal ISR$M_W = %X'200000000'; literal ISR$M_R = %X'400000000'; literal ISR$M_NA = %X'800000000'; literal ISR$M_SP = %X'1000000000'; literal ISR$M_RS = %X'2000000000'; literal ISR$M_IR = %X'4000000000'; literal ISR$M_NI = %X'8000000000'; literal ISR$M_SO = %X'10000000000'; literal ISR$M_EI = %X'60000000000'; literal ISR$M_ED = %X'80000000000'; literal ISR$M_MBZ2 = %X'FFFFF00000000000'; literal ISR$S_ISR = 8; macro ISR$R_ISR_UNION = 0,0,0,0 %; literal ISR$S_ISR_UNION = 8; macro ISR$Q_INTERRUPTION_STATUS = 0,0,0,0 %; literal ISR$S_INTERRUPTION_STATUS = 8; macro ISR$V_CODE = 0,0,16,0 %; literal ISR$S_CODE = 16; ! 0 Interruption Code macro ISR$V_SHORT_CODE = 0,0,4,0 %; literal ISR$S_SHORT_CODE = 4; ! Low 4 bits of code, aka code(3:0) macro ISR$V_SHORT_CODE4_7 = 0,4,4,0 %; literal ISR$S_SHORT_CODE4_7 = 4; ! Next 4 bits of code, aka code(4:7) macro ISR$V_HIGH_CODE = 0,8,8,0 %; literal ISR$S_HIGH_CODE = 8; ! In case anyone uses this separately macro ISR$V_FD_DFL = 0,0,1,0 %; ! Fault came from low FP registers disabled macro ISR$V_FD_DFH = 0,1,1,0 %; ! Fault camae from high FP registers disabled macro ISR$V_FF_VH = 0,0,1,0 %; macro ISR$V_FF_DH = 0,1,1,0 %; macro ISR$V_FF_ZH = 0,2,1,0 %; macro ISR$V_FF_SWAH = 0,3,1,0 %; macro ISR$V_FF_VL = 0,4,1,0 %; macro ISR$V_FF_DL = 0,5,1,0 %; macro ISR$V_FF_ZL = 0,6,1,0 %; macro ISR$V_FF_SWAL = 0,7,1,0 %; macro ISR$V_FT_FP = 0,0,1,0 %; macro ISR$V_FT_MBZ1 = 0,1,1,0 %; macro ISR$V_FT_MBZ2 = 0,2,1,0 %; macro ISR$V_FT_SS = 0,3,1,0 %; macro ISR$V_FT_MBZ4 = 0,4,1,0 %; macro ISR$V_FT_MBZ5 = 0,5,1,0 %; macro ISR$V_FT_MBZ6 = 0,6,1,0 %; macro ISR$V_FT_OL = 0,7,1,0 %; macro ISR$V_FT_UL = 0,8,1,0 %; macro ISR$V_FT_IL = 0,9,1,0 %; macro ISR$V_FT_FPAL = 0,10,1,0 %; macro ISR$V_FT_OH = 0,11,1,0 %; macro ISR$V_FT_UH = 0,12,1,0 %; macro ISR$V_FT_IH = 0,13,1,0 %; macro ISR$V_FT_FPAH = 0,14,1,0 %; macro ISR$V_FP = 0,0,1,0 %; ! Floating point exception macro ISR$V_LP = 0,1,1,0 %; ! Lower privilege transfer trap macro ISR$V_TB = 0,2,1,0 %; ! Taken branch trap macro ISR$V_SS = 0,3,1,0 %; ! Single step trap macro ISR$V_UI = 0,4,1,0 %; ! Unimplemented instruction address trap macro ISR$V_FILL1 = 0,5,11,0 %; literal ISR$S_FILL1 = 11; macro ISR$V_VECTOR = 0,16,8,0 %; literal ISR$S_VECTOR = 8; ! 16 IA-32 exception/interception vector number macro ISR$V_MBZ0 = 0,24,8,0 %; literal ISR$S_MBZ0 = 8; ! 24 Reserved ISR{31:24} (MBZ) macro ISR$V_X = 4,0,1,0 %; ! 32 Execute excpetion macro ISR$V_W = 4,1,1,0 %; ! 33 Write exception macro ISR$V_R = 4,2,1,0 %; ! 34 Read exception macro ISR$V_NA = 4,3,1,0 %; ! 35 Non-access exception macro ISR$V_SP = 4,4,1,0 %; ! 36 Speculative load exception macro ISR$V_RS = 4,5,1,0 %; ! 37 Register Stack frame macro ISR$V_IR = 4,6,1,0 %; ! 38 Incomplete Register frame macro ISR$V_NI = 4,7,1,0 %; ! 39 Nested interruption macro ISR$V_SO = 4,8,1,0 %; ! 40 IA-32 Supervisor Override macro ISR$V_EI = 4,9,2,0 %; literal ISR$S_EI = 2; ! 41 Excepting IA-64 instruction slot number macro ISR$V_ED = 4,11,1,0 %; ! 43 Exception Deferral macro ISR$V_MBZ2 = 4,12,20,0 %; literal ISR$S_MBZ2 = 20; ! 44 Reserved ISR{63:44} ! ISR codes, for general exceptions: ISR{3:0} literal ISR$C_ILLEGAL_OP = 0; ! Illegal operation fault literal ISR$C_PRIV_OP = 1; ! Privileged operation fault literal ISR$C_PRIV_REG = 2; ! Privileged register faults literal ISR$C_RESVD_REG = 3; ! Privileged operation fault literal ISR$C_ILLEGAL_ISA = 4; ! Disabled instruction set transition fault ! ISR codes, for non-access instructions ISR{3:0} literal ISR$C_TPA = 0; ! Translate physical literal ISR$C_FC = 1; ! Flush cache literal ISR$C_PROBE = 2; ! Non-faulting probe literal ISR$C_TAK = 3; ! Translation access key literal ISR$C_LFETCH = 4; ! Line fetch (faulting and non-faulting) literal ISR$C_PROBE_FAULT = 5; ! Faulting probe !*** MODULE $ITEMLDEF IDENT X-1 *** ! ! Structure used by DECnet-VAX internally used itemlists ! literal ITEML$K_LENGTH = 12; ! Length of ItemList Header literal ITEML$S_ITEM_ALLOC = 12; macro ITEML$L_ACTLEN = 0,0,32,0 %; ! Actual length of itemlist macro ITEML$A_POINTER = 4,0,32,0 %; ! Pointer to the start of the list macro ITEML$W_SIZE = 8,0,16,0 %; ! Allocated size of the structure macro ITEML$B_TYPE = 10,0,8,0 %; ! DYN$C_NET macro ITEML$B_SUBTYPE = 11,0,8,0 %; ! DYN$C_NET_ITEM macro ITEML$T_ITEMLIST = 12,0,0,0 %; ! Start of the itemlist !*** MODULE $ITIRDEF *** ! ! Definitions for Interruption TLB Insertion Register (ITIR - CR21) ! literal ITIR$M_MBZ0 = %X'3'; literal ITIR$M_PS = %X'FC'; literal ITIR$M_KEY = %X'FFFFFF00'; literal ITIR$M_MBZ2 = %X'FFFFFFFF00000000'; literal ITIR$S_ITIR = 8; macro ITIR$R_ITIR_UNION = 0,0,0,0 %; literal ITIR$S_ITIR_UNION = 8; macro ITIR$Q_REGISTER = 0,0,0,0 %; literal ITIR$S_REGISTER = 8; macro ITIR$V_MBZ0 = 0,0,2,0 %; literal ITIR$S_MBZ0 = 2; ! CWI2 - reserved macro ITIR$V_PS = 0,2,6,0 %; literal ITIR$S_PS = 6; ! Page size macro ITIR$V_KEY = 0,8,24,0 %; literal ITIR$S_KEY = 24; ! Protection key macro ITIR$V_MBZ2 = 4,0,32,0 %; literal ITIR$S_MBZ2 = 32; ! CWI1 - reserved !*** MODULE $IVRDEF *** literal IVR$M_VECTOR = %X'FF'; literal IVR$S_IVR = 8; ! ! Previous Function State Register ! *************************************** macro IVR$IQ_INTERRUPT_VECTOR = 0,0,0,0 %; literal IVR$S_INTERRUPT_VECTOR = 8; macro IVR$V_VECTOR = 0,0,8,0 %; literal IVR$S_VECTOR = 8; ! Vector number macro IVR$V_RV1 = 0,8,24,0 %; literal IVR$S_RV1 = 24; ! Reserved macro IVR$V_RV2 = 4,0,32,0 %; literal IVR$S_RV2 = 32; ! Reserved literal IVR$C_VECTOR_NMI = 2; literal IVR$C_VECTOR_SPURIOUS = 15; literal IVR$C_VECTOR_RESERVED_1 = 240; ! Boot Rendez on i2000 literal IVR$C_VECTOR_HWCLOCK = 241; literal IVR$C_VECTOR_IPINT = 242; literal IVR$C_VECTOR_PRFMON = 251; literal IVR$C_VECTOR_CPEINT = 252; literal IVR$C_VECTOR_MCHECK_RENDEZ = 253; literal IVR$C_VECTOR_MCHECK_WAKEUP = 254; literal IVR$C_VECTOR_BENIGN_RELEASE = 255; ! BOOT Rendez on rx2600. Also to wake up from HALT_LIGHT literal IRR3$V_BENIGN_RELEASE = 63; ! Bit number in IRR3 !*** MODULE $IVTDEF *** ! Interruption Vector Table offsets. Offsets are from the base of the ! IVA (Interruption Vector Address) literal IVT$C_OFF_VHPTFLT = 0; ! VHPT Translation fault literal IVT$C_OFF_ITLBFLT = 1024; ! Instruction TLB fault literal IVT$C_OFF_DTLBFLT = 2048; ! Data TLB fault literal IVT$C_OFF_ALTITLBFLT = 3072; ! Alternate ITLB fault literal IVT$C_OFF_ALTDTLBFLT = 4096; ! Alternate DTLB fault literal IVT$C_OFF_NESTEDTLBFLT = 5120; ! Nested TLB fault literal IVT$C_OFF_IKEYMISSFLT = 6144; ! Inst Key Miss fault literal IVT$C_OFF_DKEYMISSFLT = 7168; ! Data Key Miss fault literal IVT$C_OFF_DIRTYBITFLT = 8192; ! Dirty-Bit fault literal IVT$C_OFF_IACCESSBITFLT = 9216; ! Inst Access-Bit fault literal IVT$C_OFF_DACCESSBITFLT = 10240; ! Data Access-Bit fault literal IVT$C_OFF_BREAKFLT = 11264; ! Break Inst fault literal IVT$C_OFF_EXTINT = 12288; ! External Interrupt ! Offsets %X3400 to %X4C00 are reserved literal IVT$C_OFF_3400 = 13312; ! Reserved literal IVT$C_OFF_3800 = 14336; ! Reserved literal IVT$C_OFF_3C00 = 15360; ! Reserved literal IVT$C_OFF_4000 = 16384; ! Reserved literal IVT$C_OFF_4400 = 17408; ! Reserved literal IVT$C_OFF_4800 = 18432; ! Reserved literal IVT$C_OFF_4C00 = 19456; ! Reserved literal IVT$C_OFF_PAGENOTPFLT = 20480; ! Page Not Present fault literal IVT$C_OFF_KEYPERMFLT = 20736; ! Key Permission fault literal IVT$C_OFF_IACCESSRTFLT = 20992; ! Inst Access-Rights fault literal IVT$C_OFF_DACCESSRTFLT = 21248; ! Data Access-Rights fault literal IVT$C_OFF_GPFLT = 21504; ! General Exception fault literal IVT$C_OFF_FPDISFLT = 21760; ! Disable-FP fault literal IVT$C_OFF_NATFLT = 22016; ! NAT Consumption fault literal IVT$C_OFF_SPECLNFLT = 22272; ! Speculation fault literal IVT$C_OFF_5800 = 22528; ! Reserved literal IVT$C_OFF_DBGFLT = 22784; ! Debug fault literal IVT$C_OFF_ALIGNFLT = 23040; ! Unaligned Reference fault literal IVT$C_OFF_LOCKDREFFLT = 23296; ! Locked Data Reference fault literal IVT$C_OFF_FPFLT = 23552; ! Floating Point fault literal IVT$C_OFF_FPTRAP = 23808; ! Floating Point Trap literal IVT$C_OFF_LOPRIVTRAP = 24064; ! Lower-Privilege Transfer Trap literal IVT$C_OFF_TAKENBRTRAP = 24320; ! Taken Branch Trap literal IVT$C_OFF_SSTEPTRAP = 24576; ! Single Step Trap ! Offsets %X6100 to %X6800 are reserved literal IVT$C_OFF_6100 = 24832; ! Reserved literal IVT$C_OFF_6200 = 25088; ! Reserved literal IVT$C_OFF_6300 = 25344; ! Reserved literal IVT$C_OFF_6400 = 25600; ! Reserved literal IVT$C_OFF_6500 = 25856; ! Reserved literal IVT$C_OFF_6600 = 26112; ! Reserved literal IVT$C_OFF_6700 = 26368; ! Reserved literal IVT$C_OFF_6800 = 26624; ! Reserved literal IVT$C_OFF_IA32EXCEPTN = 26880; ! iA32 Exception literal IVT$C_OFF_IA32INTERCEPT = 27136; ! iA32 Intercept literal IVT$C_OFF_IA32INT = 27392; ! iA32 Interrupt ! Offsets %X6C00 to %X7F00 are reserved literal IVT$C_OFF_6C00 = 27648; ! Reserved literal IVT$C_OFF_6D00 = 27904; ! Reserved literal IVT$C_OFF_6E00 = 28160; ! Reserved literal IVT$C_OFF_6F00 = 28416; ! Reserved literal IVT$C_OFF_7000 = 28672; ! Reserved literal IVT$C_OFF_7100 = 28928; ! Reserved literal IVT$C_OFF_7200 = 29184; ! Reserved literal IVT$C_OFF_7300 = 29440; ! Reserved literal IVT$C_OFF_7400 = 29696; ! Reserved literal IVT$C_OFF_7500 = 29952; ! Reserved literal IVT$C_OFF_7600 = 30208; ! Reserved literal IVT$C_OFF_7700 = 30464; ! Reserved literal IVT$C_OFF_7800 = 30720; ! Reserved literal IVT$C_OFF_7900 = 30976; ! Reserved literal IVT$C_OFF_7A00 = 31232; ! Reserved literal IVT$C_OFF_7B00 = 31488; ! Reserved literal IVT$C_OFF_7C00 = 31744; ! Reserved literal IVT$C_OFF_7D00 = 32000; ! Reserved literal IVT$C_OFF_7E00 = 32256; ! Reserved literal IVT$C_OFF_7F00 = 32512; ! Reserved ! Size of Interrupt Vector Table literal IVT$C_SIZE = 32768; ! Size in bytes of the IVT !*** MODULE $JIBDEF *** ! + ! Job Information Block - Structure containing common context for a set ! of related processes. ! ! Note: The Executive module SYSCREPRC assumes that the job mount list head ! preceeds the username field in the JIB. ! ! JIB Synchronization: ! ! The JIB is a shared structure across a subprocess tree. Synchronization ! is complex because many of the quota and limit fields have no functional ! relationship whatsoever. So a number of methods of synchronization are ! used, based on exactly what is being manipulated. Below is a list of ! fields with their methods of synch. ! ! Field Synchronization Method ! ----- ---------------------- ! BYTCNT/BYTLM Interlocked arithmetic sequences. Should never be manually ! manipulated: use the EXE$DEBIT/CREDIT routines in the ! EXSUBROUT module. ! ! TQCNT/TQLM Interlocked arithmetic sequences. When waiting because of a ! lack of TQCNT, the JIB FLAGS bit TQCNT_WAITERS must be set; ! the JIB address is the EFWM and the process should be ! placed in the MWAIT queue. When TQCNT is incremented, ! the TQCNT_WAITERS bit must be interrogated. If it is set, ! then waiting process should be made executable via a call ! to EXE$JIB_AVAIL or similar inline code. ! ! PGFLCNT Interlocked arithmetic sequences. Should never be manually ! manipulated to charge for pagefile quota: use $more_pgflquota ! macro. Macros $init_pgflquota and $ret_pgflquota are also ! available. ! ! PGFLQUOTA MMG spinlock. ! ! MTLFL/MTLBL SCH$IOLOCK/UNLOCK. ! ! FILCNT/FILLM, Interlocked arithmetic sequences. These fields are never increased ! ENQCNT/ENQLM, or decreased by more than 1 at a time, and are never waited on. ! PRCCNT/PRCLM ! - literal JIB$C_DETACHED = 0; literal JIB$C_NETWORK = 1; literal JIB$C_BATCH = 2; literal JIB$C_LOCAL = 3; literal JIB$C_DIALUP = 4; literal JIB$C_REMOTE = 5; literal JIB$M_BYTCNT_WAITERS = %X'1'; literal JIB$M_TQCNT_WAITERS = %X'2'; literal JIB$M_MEDDLE = %X'4'; literal JIB$K_LENGTH = 140; ! Structure length literal JIB$C_LENGTH = 140; ! Structure length literal JIB$S_JIBDEF = 140; ! Old JIB sized for compatability literal JIB$S_JIB = 140; macro JIB$L_MTLFL = 0,0,32,1 %; ! Job mounted volume list head forward link macro JIB$L_MTLBL = 4,0,32,1 %; ! Job mounted volume list head back link macro JIB$W_SIZE = 8,0,16,0 %; ! Size of structure in bytes macro JIB$B_TYPE = 10,0,8,0 %; ! Structure type code macro JIB$B_DAYTYPES = 11,0,8,0 %; ! Set bits 0-6 flag non-prime days of week macro JIB$T_USERNAME = 12,0,0,0 %; literal JIB$S_USERNAME = 12; ! User name for easy access macro JIB$T_ACCOUNT = 24,0,0,0 %; literal JIB$S_ACCOUNT = 8; ! Account name for resident access macro JIB$L_BYTCNT = 32,0,32,0 %; ! Buffered I/O byte count avail macro JIB$L_BYTLM = 36,0,32,0 %; ! Original value for Byte count macro JIB$L_PBYTCNT = 40,0,32,0 %; ! Paged pool byte count remaining macro JIB$L_PBYTLIM = 44,0,32,0 %; ! Paged pool byte limit macro JIB$L_FILCNT = 48,0,32,0 %; ! Open File count remaining macro JIB$L_FILLM = 52,0,32,0 %; ! Open file limit macro JIB$L_TQCNT = 56,0,32,0 %; ! Timer queue entry count remaining macro JIB$L_TQLM = 60,0,32,0 %; ! Timer queue entry limit macro JIB$L_PGFLQUOTA = 64,0,32,0 %; ! Paging file quota macro JIB$L_PGFLCNT = 68,0,32,1 %; ! Paging file limit *** signed *** macro JIB$L_CPULIM = 72,0,32,0 %; ! CPU time quota remaining macro JIB$L_PRCCNT = 76,0,32,0 %; ! Count of subprocesses existing macro JIB$L_PRCLIM = 80,0,32,0 %; ! Limit on number of subprocesses macro JIB$W_SHRFCNT = 84,0,16,0 %; ! Shared file block count remaining macro JIB$W_SHRFLIM = 86,0,16,0 %; ! Shared file count limit macro JIB$L_ENQCNT = 88,0,32,0 %; ! Enqueue count avail macro JIB$L_ENQLM = 92,0,32,0 %; ! Enqueue limit macro JIB$W_MAXJOBS = 96,0,16,0 %; ! Max jobs limit on user macro JIB$W_MAXDETACH = 98,0,16,0 %; ! Max detached processes for user macro JIB$L_MPID = 100,0,32,0 %; ! PID of master process macro JIB$L_JLNAMFL = 104,0,32,1 %; ! Forward link for job-wide logical names macro JIB$L_JLNAMBL = 108,0,32,1 %; ! Back link for job-wide logical names macro JIB$L_PDAYHOURS = 112,0,32,0 %; ! Field describing primary day access macro JIB$L_ODAYHOURS = 116,0,32,0 %; ! Field describing off day access macro JIB$L_JOBTYPE = 120,0,32,0 %; ! Job origin type macro JIB$L_FLAGS = 124,0,32,0 %; ! FLAG bits macro JIB$V_BYTCNT_WAITERS = 124,0,1,0 %; ! Processes are waiting on BYTCNT macro JIB$V_TQCNT_WAITERS = 124,1,1,0 %; ! Processes are waiting on TQCNT macro JIB$V_MEDDLE = 124,2,1,0 %; ! Job table has been altered macro JIB$L_ORG_BYTLM = 128,0,32,0 %; ! Original BYTLM macro JIB$L_ORG_PBYTLM = 132,0,32,0 %; ! Original PBYTLM macro JIB$L_JTQUOTA = 136,0,32,0 %; ! Job table quota !*** MODULE $KA0202DEF *** literal KA0202$K_MAX_CPU_MODULES = 2; literal KA0202$K_MAX_MEMORY_MODULES = 4; literal KA0202$M_IOCSR_ENET_HLT_ENA = %X'1'; literal KA0202$M_IOCSR_ENET_HLT = %X'2'; literal KA0202$M_IOCSR_FBUS_HLT_ENA = %X'10'; literal KA0202$M_IOCSR_FBUS_HLT = %X'20'; literal KA0202$M_IOCSR_FBUS_INT_STS = %X'40'; literal KA0202$M_IOCSR_FBUS_RESET_L = %X'80'; literal KA0202$M_IOCSR_FBUS_PWR_FAIL = %X'100'; literal KA0202$M_IOCSR_MBX_ENA_L = %X'200'; literal KA0202$M_IOCSR_FBUS_DMA_ENA_L = %X'400'; literal KA0202$M_IOCSR_LBUS_DMA_ENA_L = %X'800'; literal KA0202$M_IOCSR_CA_WWP_0 = %X'1000'; literal KA0202$M_IOCSR_CA_WWP_2 = %X'2000'; literal KA0202$M_IOCSR_DATA_WWP_L = %X'4000'; literal KA0202$M_IOCSR_FMBPR_RESET_L = %X'8000'; literal KA0202$M_IOCSR_LMBPR_RESET_L = %X'10000'; literal KA0202$M_IOCSR_LBUS_RESET_L = %X'20000'; literal KA0202$M_IOCSR_FBUS_COMP_PE_L = %X'40000'; literal KA0202$M_IOCSR_LBUS_COMP_PE_L = %X'80000'; literal KA0202$M_IOCSR_FBUS_RESET_H = %X'8000000000'; literal KA0202$M_IOCSR_MBX_ENA_H = %X'20000000000'; literal KA0202$M_IOCSR_FBUS_DMA_ENA_H = %X'40000000000'; literal KA0202$M_IOCSR_LBUS_DMA_ENA_H = %X'80000000000'; literal KA0202$M_IOCSR_CA_WWP_1 = %X'100000000000'; literal KA0202$M_IOCSR_CA_WWP_3 = %X'200000000000'; literal KA0202$M_IOCSR_DATA_WWP_H = %X'400000000000'; literal KA0202$M_IOCSR_FMBPR_RESET_H = %X'800000000000'; literal KA0202$M_IOCSR_LMBPR_RESET_H = %X'1000000000000'; literal KA0202$M_IOCSR_LBUS_RESET_H = %X'2000000000000'; literal KA0202$M_IOCSR_FBUS_COMP_PE_H = %X'4000000000000'; literal KA0202$M_IOCSR_LBUS_COMP_PE_H = %X'8000000000000'; literal KA0202$M_CERR1_UNCORR_RDERR_L = %X'1'; literal KA0202$M_CERR1_NOACK_L = %X'2'; literal KA0202$M_CERR1_CMDADR_PE_L = %X'4'; literal KA0202$M_CERR1_MCMDADR_PE_L = %X'8'; literal KA0202$M_CERR1_WRTDAT_PE_L = %X'10'; literal KA0202$M_CERR1_MWRTDAT_PE_L = %X'20'; literal KA0202$M_CERR1_RDDAT_PE_L = %X'40'; literal KA0202$M_CERR1_MRDDAT_PE_L = %X'80'; literal KA0202$M_CERR1_CMDADR_PE_LW0 = %X'100'; literal KA0202$M_CERR1_CMDADR_PE_LW2 = %X'200'; literal KA0202$M_CERR1_DAT_PE_LW0 = %X'400'; literal KA0202$M_CERR1_DAT_PE_LW2 = %X'800'; literal KA0202$M_CERR1_DAT_PE_LW4 = %X'1000'; literal KA0202$M_CERR1_DAT_PE_LW6 = %X'2000'; literal KA0202$M_CERR1_CSTALL_SYNC_H = %X'4000'; literal KA0202$M_CERR1_FBUS_MBX_ERR = %X'8000'; literal KA0202$M_CERR1_CMD_WRTDAT_PE_L = %X'10000'; literal KA0202$M_CERR1_BUS_SYNC = %X'20000'; literal KA0202$M_CERR1_UNCORR_RDERR_H = %X'100000000'; literal KA0202$M_CERR1_NOACK_H = %X'200000000'; literal KA0202$M_CERR1_CMDADR_PE_H = %X'400000000'; literal KA0202$M_CERR1_MCMDADR_PE_H = %X'800000000'; literal KA0202$M_CERR1_WRTDAT_PE_H = %X'1000000000'; literal KA0202$M_CERR1_MWRTDAT_PE_H = %X'2000000000'; literal KA0202$M_CERR1_RDDAT_PE_H = %X'4000000000'; literal KA0202$M_CERR1_MRDDAT_PE_H = %X'8000000000'; literal KA0202$M_CERR1_CMDADR_PE_LW1 = %X'10000000000'; literal KA0202$M_CERR1_CMDADR_PE_LW3 = %X'20000000000'; literal KA0202$M_CERR1_DAT_PE_LW1 = %X'40000000000'; literal KA0202$M_CERR1_DAT_PE_LW3 = %X'80000000000'; literal KA0202$M_CERR1_DAT_PE_LW5 = %X'100000000000'; literal KA0202$M_CERR1_DAT_PE_LW7 = %X'200000000000'; literal KA0202$M_CERR1_CSTALL_SYNC_L = %X'400000000000'; literal KA0202$M_CERR1_LBUS_MBX = %X'800000000000'; literal KA0202$M_CERR1_CMD_WRTDAT_PE_H = %X'1000000000000'; literal KA0202$M_CERR2_L = %X'FFFFFFFF'; literal KA0202$M_CERR2_H = %X'FFFFFFFF00000000'; literal KA0202$M_LMBPR_MBX_ADDR = %X'FFFFFFC0'; literal KA0202$M_FMBPR_MBX_ADDR = %X'FFFFFFC0'; literal KA0202$M_FIVECT_VECTOR = %X'FFFF'; literal KA0202$M_FHVECT_VECTOR = %X'FFFF'; literal KA0202$M_FERR1_DATA_PE_L = %X'1'; literal KA0202$M_FERR1_ADDR_PE_L = %X'2'; literal KA0202$M_FERR1_fill1 = %X'FFFFFFFC'; literal KA0202$M_FERR1_DATA_PE_H = %X'100000000'; literal KA0202$M_FERR1_ADDR_PE_H = %X'200000000'; literal KA0202$M_LINT_SCSI0_IRQ = %X'1'; literal KA0202$M_LINT_SCSI1_IRQ = %X'2'; literal KA0202$M_LINT_SCSI2_IRQ = %X'4'; literal KA0202$M_LINT_SCSI3_IRQ = %X'8'; literal KA0202$M_LINT_SCSI4_IRQ = %X'10'; literal KA0202$M_LINT_SLU_IRQ = %X'100000000'; literal KA0202$M_LINT_NI0_IRQ = %X'200000000'; literal KA0202$M_LINT_NI1_IRQ = %X'400000000'; literal KA0202$M_LINT_SBUS_IRQ = %X'800000000'; literal KA0202$M_LERR1_EVEN = %X'1'; literal KA0202$M_LERR1_ODD = %X'100000000'; literal KA0202$K_LENGTH = 57344; literal KA0202$S_KA0202DEF = 57344; ! Old size name, synonym for KA0202$S_KA0202 literal KA0202$S_KA0202 = 57344; macro KA0202$Q_IOCSR = 0,0,0,1 %; literal KA0202$S_IOCSR = 8; macro KA0202$V_IOCSR_ENET_HLT_ENA = 0,0,1,0 %; ! Ethernet halt enable macro KA0202$V_IOCSR_ENET_HLT = 0,1,1,0 %; ! Ethernet halt macro KA0202$V_IOCSR_FBUS_HLT_ENA = 0,4,1,0 %; ! Futurebus halt enable macro KA0202$V_IOCSR_FBUS_HLT = 0,5,1,0 %; ! Futurebus halt macro KA0202$V_IOCSR_FBUS_INT_STS = 0,6,1,0 %; ! Futurebus interrupt status macro KA0202$V_IOCSR_FBUS_RESET_L = 0,7,1,0 %; ! Fbus reset macro KA0202$V_IOCSR_FBUS_PWR_FAIL = 0,8,1,0 %; ! Fbus power fail msg macro KA0202$V_IOCSR_MBX_ENA_L = 0,9,1,0 %; ! Mailbox enable even macro KA0202$V_IOCSR_FBUS_DMA_ENA_L = 0,10,1,0 %; ! Futurebus DMA enable even macro KA0202$V_IOCSR_LBUS_DMA_ENA_L = 0,11,1,0 %; ! Lbus DMA enable even macro KA0202$V_IOCSR_CA_WWP_0 = 0,12,1,0 %; ! Command/address write wrong parity 0 macro KA0202$V_IOCSR_CA_WWP_2 = 0,13,1,0 %; ! Command/address write wrong parity 2 macro KA0202$V_IOCSR_DATA_WWP_L = 0,14,1,0 %; ! Data write wrong parity even macro KA0202$V_IOCSR_FMBPR_RESET_L = 0,15,1,0 %; ! Reset fbus mbx pointer reg macro KA0202$V_IOCSR_LMBPR_RESET_L = 0,16,1,0 %; ! Reset lbus mbx pointer reg macro KA0202$V_IOCSR_LBUS_RESET_L = 0,17,1,0 %; ! Lbus reset macro KA0202$V_IOCSR_FBUS_COMP_PE_L = 0,18,1,0 %; ! Fbus complement parity even macro KA0202$V_IOCSR_LBUS_COMP_PE_L = 0,19,1,0 %; ! Lbus complement parity even macro KA0202$V_IOCSR_FBUS_RESET_H = 4,7,1,0 %; ! Fbus reset macro KA0202$V_IOCSR_MBX_ENA_H = 4,9,1,0 %; ! Mailbox enable odd macro KA0202$V_IOCSR_FBUS_DMA_ENA_H = 4,10,1,0 %; ! Futurebus DMA enable odd macro KA0202$V_IOCSR_LBUS_DMA_ENA_H = 4,11,1,0 %; ! Lbus DMA enable odd macro KA0202$V_IOCSR_CA_WWP_1 = 4,12,1,0 %; ! Command/address write wrong parity 1 macro KA0202$V_IOCSR_CA_WWP_3 = 4,13,1,0 %; ! Command/address write wrong parity 3 macro KA0202$V_IOCSR_DATA_WWP_H = 4,14,1,0 %; ! Data write wrong parity odd macro KA0202$V_IOCSR_FMBPR_RESET_H = 4,15,1,0 %; ! Reset fbus mbx pointer reg macro KA0202$V_IOCSR_LMBPR_RESET_H = 4,16,1,0 %; ! Reset lbus mbx pointer reg macro KA0202$V_IOCSR_LBUS_RESET_H = 4,17,1,0 %; ! Lbus reset macro KA0202$V_IOCSR_FBUS_COMP_PE_H = 4,18,1,0 %; ! Fbus complement parity even macro KA0202$V_IOCSR_LBUS_COMP_PE_H = 4,19,1,0 %; ! Lbus complement parity even macro KA0202$b_fill1 = 8,0,0,1 %; literal KA0202$s_fill1 = 24; macro KA0202$Q_CERR1 = 32,0,0,1 %; literal KA0202$S_CERR1 = 8; macro KA0202$V_CERR1_UNCORR_RDERR_L = 32,0,1,0 %; ! Uncorrectable read error macro KA0202$V_CERR1_NOACK_L = 32,1,1,0 %; ! No acknowledge error macro KA0202$V_CERR1_CMDADR_PE_L = 32,2,1,0 %; ! Command address parity error even macro KA0202$V_CERR1_MCMDADR_PE_L = 32,3,1,0 %; ! Missed command address parity error even macro KA0202$V_CERR1_WRTDAT_PE_L = 32,4,1,0 %; ! Write data parity error even macro KA0202$V_CERR1_MWRTDAT_PE_L = 32,5,1,0 %; ! Missed write data parity error even macro KA0202$V_CERR1_RDDAT_PE_L = 32,6,1,0 %; ! Read data parity error even macro KA0202$V_CERR1_MRDDAT_PE_L = 32,7,1,0 %; ! Missed read data parity error even macro KA0202$V_CERR1_CMDADR_PE_LW0 = 32,8,1,0 %; ! Command address parity error longword 0 macro KA0202$V_CERR1_CMDADR_PE_LW2 = 32,9,1,0 %; ! Command address parity error longword 2 macro KA0202$V_CERR1_DAT_PE_LW0 = 32,10,1,0 %; ! Data parity error longword 0 macro KA0202$V_CERR1_DAT_PE_LW2 = 32,11,1,0 %; ! Data parity error longword 2 macro KA0202$V_CERR1_DAT_PE_LW4 = 32,12,1,0 %; ! Data parity error longword 4 macro KA0202$V_CERR1_DAT_PE_LW6 = 32,13,1,0 %; ! Data parity error longword 6 macro KA0202$V_CERR1_CSTALL_SYNC_H = 32,14,1,0 %; macro KA0202$V_CERR1_FBUS_MBX_ERR = 32,15,1,0 %; ! Futurebus mailbox error macro KA0202$V_CERR1_CMD_WRTDAT_PE_L = 32,16,1,0 %; macro KA0202$V_CERR1_BUS_SYNC = 32,17,1,0 %; macro KA0202$V_CERR1_UNCORR_RDERR_H = 36,0,1,0 %; ! Uncorrectable read error macro KA0202$V_CERR1_NOACK_H = 36,1,1,0 %; ! No acknowledge error macro KA0202$V_CERR1_CMDADR_PE_H = 36,2,1,0 %; ! Command address parity error even macro KA0202$V_CERR1_MCMDADR_PE_H = 36,3,1,0 %; ! Missed command address parity error even macro KA0202$V_CERR1_WRTDAT_PE_H = 36,4,1,0 %; ! Write data parity error even macro KA0202$V_CERR1_MWRTDAT_PE_H = 36,5,1,0 %; ! Missed write data parity error even macro KA0202$V_CERR1_RDDAT_PE_H = 36,6,1,0 %; ! Read data parity error even macro KA0202$V_CERR1_MRDDAT_PE_H = 36,7,1,0 %; ! Missed read data parity error even macro KA0202$V_CERR1_CMDADR_PE_LW1 = 36,8,1,0 %; ! Command address parity error longword 0 macro KA0202$V_CERR1_CMDADR_PE_LW3 = 36,9,1,0 %; ! Command address parity error longword 2 macro KA0202$V_CERR1_DAT_PE_LW1 = 36,10,1,0 %; ! Data parity error longword 0 macro KA0202$V_CERR1_DAT_PE_LW3 = 36,11,1,0 %; ! Data parity error longword 2 macro KA0202$V_CERR1_DAT_PE_LW5 = 36,12,1,0 %; ! Data parity error longword 4 macro KA0202$V_CERR1_DAT_PE_LW7 = 36,13,1,0 %; ! Data parity error longword 6 macro KA0202$V_CERR1_CSTALL_SYNC_L = 36,14,1,0 %; macro KA0202$V_CERR1_LBUS_MBX = 36,15,1,0 %; ! Lbus mailbox error macro KA0202$V_CERR1_CMD_WRTDAT_PE_H = 36,16,1,0 %; macro KA0202$b_fill2 = 40,0,0,1 %; literal KA0202$s_fill2 = 24; macro KA0202$Q_CERR2 = 64,0,0,0 %; literal KA0202$S_CERR2 = 8; ! Cobra Error register 2 macro KA0202$V_CERR2_L = 64,0,32,0 %; literal KA0202$S_CERR2_L = 32; macro KA0202$V_CERR2_H = 68,0,32,0 %; literal KA0202$S_CERR2_H = 32; macro KA0202$b_fill3 = 72,0,0,1 %; literal KA0202$s_fill3 = 24; macro KA0202$Q_CERR3 = 96,0,0,1 %; literal KA0202$S_CERR3 = 8; macro KA0202$b_fill4 = 104,0,0,1 %; literal KA0202$s_fill4 = 24; macro KA0202$Q_LMBPR = 128,0,0,1 %; literal KA0202$S_LMBPR = 8; macro KA0202$V_LMBPR_MBX_ADDR = 128,6,26,0 %; literal KA0202$S_LMBPR_MBX_ADDR = 26; ! Lbus mailbox address macro KA0202$b_fill5 = 136,0,0,1 %; literal KA0202$s_fill5 = 24; macro KA0202$Q_FMBPR = 160,0,0,1 %; literal KA0202$S_FMBPR = 8; macro KA0202$V_FMBPR_MBX_ADDR = 160,6,26,0 %; literal KA0202$S_FMBPR_MBX_ADDR = 26; ! Futurebus mailbox address macro KA0202$b_fill6 = 168,0,0,1 %; literal KA0202$s_fill6 = 24; macro KA0202$Q_DIAGCSR = 192,0,0,1 %; literal KA0202$S_DIAGCSR = 8; macro KA0202$b_fill7 = 200,0,0,1 %; literal KA0202$s_fill7 = 24; macro KA0202$Q_FIVECT = 224,0,0,1 %; literal KA0202$S_FIVECT = 8; macro KA0202$V_FIVECT_VECTOR = 224,0,16,0 %; literal KA0202$S_FIVECT_VECTOR = 16; ! Futurebus interrupt vector macro KA0202$b_fill8 = 232,0,0,1 %; literal KA0202$s_fill8 = 24; macro KA0202$Q_FHVECT = 256,0,0,1 %; literal KA0202$S_FHVECT = 8; macro KA0202$V_FHVECT_VECTOR = 256,0,16,0 %; literal KA0202$S_FHVECT_VECTOR = 16; ! Futurebus halt vector macro KA0202$b_fill9 = 264,0,0,1 %; literal KA0202$s_fill9 = 24; macro KA0202$Q_FERR1 = 288,0,0,1 %; literal KA0202$S_FERR1 = 8; macro KA0202$V_FERR1_DATA_PE_L = 288,0,1,0 %; macro KA0202$V_FERR1_ADDR_PE_L = 288,1,1,0 %; macro KA0202$V_FERR1_fill1 = 288,2,30,0 %; literal KA0202$S_FERR1_fill1 = 30; macro KA0202$V_FERR1_DATA_PE_H = 292,0,1,0 %; macro KA0202$V_FERR1_ADDR_PE_H = 292,1,1,0 %; macro KA0202$b_fill10 = 296,0,0,1 %; literal KA0202$s_fill10 = 24; macro KA0202$Q_FERR2 = 320,0,0,1 %; literal KA0202$S_FERR2 = 8; macro KA0202$b_fill11 = 328,0,0,1 %; literal KA0202$s_fill11 = 24; macro KA0202$Q_LINT = 352,0,0,1 %; literal KA0202$S_LINT = 8; macro KA0202$V_LINT_SCSI0_IRQ = 352,0,1,0 %; ! SCSI bus 0 interrupt request macro KA0202$V_LINT_SCSI1_IRQ = 352,1,1,0 %; ! SCSI bus 1 interrupt request macro KA0202$V_LINT_SCSI2_IRQ = 352,2,1,0 %; ! SCSI bus 2 interrupt request macro KA0202$V_LINT_SCSI3_IRQ = 352,3,1,0 %; ! SCSI bus 3 interrupt request macro KA0202$V_LINT_SCSI4_IRQ = 352,4,1,0 %; ! SCSI bus 4 interrupt request macro KA0202$V_LINT_SLU_IRQ = 356,0,1,0 %; ! Seriel line unit interrupt request macro KA0202$V_LINT_NI0_IRQ = 356,1,1,0 %; ! Ethernet 0 interrupt request macro KA0202$V_LINT_NI1_IRQ = 356,2,1,0 %; ! Ethernet 1 interrupt request macro KA0202$V_LINT_SBUS_IRQ = 356,3,1,0 %; ! Serial bus interrupt request macro KA0202$b_fill12 = 360,0,0,1 %; literal KA0202$s_fill12 = 24; macro KA0202$Q_LERR1 = 384,0,0,1 %; literal KA0202$S_LERR1 = 8; macro KA0202$V_LERR1_EVEN = 384,0,1,0 %; ! Even error macro KA0202$V_LERR1_ODD = 388,0,1,0 %; ! Odd error macro KA0202$b_fill13 = 392,0,0,1 %; literal KA0202$s_fill13 = 24; macro KA0202$Q_LERR2 = 416,0,0,1 %; literal KA0202$S_LERR2 = 8; macro KA0202$b_fill14 = 424,0,0,1 %; literal KA0202$s_fill14 = 7768; macro KA0202$Q_CPU0 = 8192,0,0,1 %; literal KA0202$S_CPU0 = 8192; macro KA0202$Q_CPU1 = 16384,0,0,1 %; literal KA0202$S_CPU1 = 8192; macro KA0202$Q_CMM0 = 24576,0,0,1 %; literal KA0202$S_CMM0 = 8192; macro KA0202$Q_CMM1 = 32768,0,0,1 %; literal KA0202$S_CMM1 = 8192; macro KA0202$Q_CMM2 = 40960,0,0,1 %; literal KA0202$S_CMM2 = 8192; macro KA0202$Q_CMM3 = 49152,0,0,1 %; literal KA0202$S_CMM3 = 8192; literal KA0202_CPU$M_BCC_ENB_ALLOC_L = %X'1'; literal KA0202_CPU$M_BCC_FRC_FILL_SH_L = %X'2'; literal KA0202_CPU$M_BCC_ENB_TPC_L = %X'4'; literal KA0202_CPU$M_BCC_FILL_WTP_L = %X'8'; literal KA0202_CPU$M_BCC_FILL_WCP_L = %X'10'; literal KA0202_CPU$M_BCC_FILL_WDTP_L = %X'20'; literal KA0202_CPU$M_BCC_ENB_CEI_L = %X'40'; literal KA0202_CPU$M_BCC_ENB_EDCC_L = %X'80'; literal KA0202_CPU$M_BCC_ENB_EDC_CHK_L = %X'100'; literal KA0202_CPU$M_BCC_ENB_BC_CIO_L = %X'200'; literal KA0202_CPU$M_BCC_DIS_BLK_W_L = %X'400'; literal KA0202_CPU$M_BCC_ENB_BC_INIT_L = %X'800'; literal KA0202_CPU$M_BCC_FOR_EDCC_L = %X'1000'; literal KA0202_CPU$M_BCC_SH_D_V_L = %X'E000'; literal KA0202_CPU$M_BCC_EDC_L = %X'3FFF0000'; literal KA0202_CPU$M_BCC_CACHE_SIZE_L = %X'C0000000'; literal KA0202_CPU$M_BCC_ENB_ALLOC_H = %X'100000000'; literal KA0202_CPU$M_BCC_FRC_FILL_SH_H = %X'200000000'; literal KA0202_CPU$M_BCC_ENB_TPC_H = %X'400000000'; literal KA0202_CPU$M_BCC_FILL_WTP_H = %X'800000000'; literal KA0202_CPU$M_BCC_FILL_WCP_H = %X'1000000000'; literal KA0202_CPU$M_BCC_FILL_WDTP_H = %X'2000000000'; literal KA0202_CPU$M_BCC_ENB_CEI_H = %X'4000000000'; literal KA0202_CPU$M_BCC_ENB_EDCC_H = %X'8000000000'; literal KA0202_CPU$M_BCC_ENB_EDC_CHK_H = %X'10000000000'; literal KA0202_CPU$M_BCC_ENB_BC_CIO_H = %X'20000000000'; literal KA0202_CPU$M_BCC_DIS_BLK_W_H = %X'40000000000'; literal KA0202_CPU$M_BCC_ENB_BC_INIT_H = %X'80000000000'; literal KA0202_CPU$M_BCC_FOR_EDCC_H = %X'100000000000'; literal KA0202_CPU$M_BCC_SH_D_V_H = %X'E00000000000'; literal KA0202_CPU$M_BCC_EDC_L_H = %X'3FFF000000000000'; literal KA0202_CPU$M_BCC_CACHE_SIZE_H = %X'C000000000000000'; literal KA0202_BCC$K_CACHE_SIZE_512K = 0; ! Cache size is 512Kb literal KA0202_BCC$K_CACHE_SIZE_1MB = 1; ! Cache size is 1Mb literal KA0202_BCC$K_CACHE_SIZE_4MB = 2; ! Cache size is 4Mb literal KA0202_CPU$M_BCCE_MCE = %X'4'; literal KA0202_CPU$M_BCCE_CE = %X'8'; literal KA0202_CPU$M_BCCE_CNTRL_PAR = %X'100'; literal KA0202_CPU$M_BCCE_SH = %X'200'; literal KA0202_CPU$M_BCCE_DIRTY = %X'400'; literal KA0202_CPU$M_BCCE_VALID = %X'800'; literal KA0202_CPU$M_BCCE_BC_EDC_L = %X'20000'; literal KA0202_CPU$M_BCCE_EDC_SYND_0 = %X'1FC0000'; literal KA0202_CPU$M_BCCE_EDC_SYND_2 = %X'FE000000'; literal KA0202_CPU$M_BCCE_MCE_H = %X'100000000'; literal KA0202_CPU$M_BCCE_CE_H = %X'200000000'; literal KA0202_CPU$M_BCCE_READ_ONLY = %X'7FFC00000000'; literal KA0202_CPU$M_BCCE_BC_EDC_H = %X'800000000000'; literal KA0202_CPU$M_BCCE_EDC_SYND_1 = %X'7F000000000000'; literal KA0202_CPU$M_BCCE_EDC_SYND_3 = %X'3F80000000000000'; literal KA0202_CPU$M_BCCEA_BCMAP_OFF = %X'1FFFF'; literal KA0202_CPU$M_BCCEA_TAG_PAR = %X'40000'; literal KA0202_CPU$M_BCCEA_TAG_VALUE = %X'7FF80000'; literal KA0202_CPU$M_BCCEA_BCMAP_OFF_H = %X'1FFFF00000000'; literal KA0202_CPU$M_BCCEA_TAG_PAR_H = %X'4000000000000'; literal KA0202_CPU$M_BCCEA_TAG_VALUE_H = %X'7FF8000000000000'; literal KA0202_CPU$M_BCUE_MPE = %X'1'; literal KA0202_CPU$M_BCUE_PE = %X'2'; literal KA0202_CPU$M_BCUE_MUNCE_L = %X'4'; literal KA0202_CPU$M_BCUE_UNCE_L = %X'8'; literal KA0202_CPU$M_BCUE_CTRL_PAR = %X'100'; literal KA0202_CPU$M_BCUE_SH = %X'200'; literal KA0202_CPU$M_BCUE_DIRTY = %X'400'; literal KA0202_CPU$M_BCUE_VALID = %X'800'; literal KA0202_CPU$M_BCUE_BC_EDC_L = %X'20000'; literal KA0202_CPU$M_BCUE_EDC_SYND_0 = %X'1FC0000'; literal KA0202_CPU$M_BCUE_EDC_SYND_2 = %X'FE000000'; literal KA0202_CPU$M_BCUE_PE_H = %X'100000000'; literal KA0202_CPU$M_BCUE_MUNCE_H = %X'200000000'; literal KA0202_CPU$M_BCUE_UNCE_H = %X'400000000'; literal KA0202_CPU$M_BCUE_BC_EDC_H = %X'1000000000000'; literal KA0202_CPU$M_BCUE_EDC_SYND_1 = %X'FE000000000000'; literal KA0202_CPU$M_BCUE_EDC_SYND_3 = %X'7F00000000000000'; literal KA0202_CPU$M_BCUEA_BCMAP_OFF = %X'1FFFF'; literal KA0202_CPU$M_BCUEA_PTP = %X'20000'; literal KA0202_CPU$M_BCUEA_TP = %X'40000'; literal KA0202_CPU$M_BCUEA_TV = %X'7FF80000'; literal KA0202_CPU$M_BCUEA_BCMAP_OFF_H = %X'FFFF80000000'; literal KA0202_CPU$M_BCUEA_PTP_H = %X'1000000000000'; literal KA0202_CPU$M_BCUEA_TP_H = %X'2000000000000'; literal KA0202_CPU$M_BCUEA_TV_H = %X'3FFC000000000000'; literal KA0202_CPU$M_MDTER_L = %X'1'; literal KA0202_CPU$M_DTER_L = %X'2'; literal KA0202_CPU$M_DTER_TOFF_L = %X'3FC'; literal KA0202_CPU$M_DTER_DUP_TAG_L = %X'3FFFFC00'; literal KA0202_CPU$M_DTER_DTP = %X'40000000'; literal KA0202_CPU$M_MDTER_H = %X'100000000'; literal KA0202_CPU$M_DTER_H = %X'200000000'; literal KA0202_CPU$M_DTER_DT_H = %X'3FC00000000'; literal KA0202_CPU$M_DTER_DUP_TAG_H = %X'3FFFFC0000000000'; literal KA0202_CPU$M_DTER_DTP_H = %X'4000000000000000'; literal KA0202_CPU$M_CBCTL_DWP = %X'1'; literal KA0202_CPU$M_CBCTL_CAWP = %X'6'; literal KA0202_CPU$M_CBCTL_EPC = %X'8'; literal KA0202_CPU$M_CBCTL_FRC_SH = %X'10'; literal KA0202_CPU$M_CBCTL_CMDER_ID = %X'E0'; literal KA0202_CPU$M_CBCTL_ACM = %X'700'; literal KA0202_CPU$M_CBCTL_ENB_CI = %X'800'; literal KA0202_CPU$M_CBCTL_RD = %X'1000'; literal KA0202_CPU$M_CBCTL_QW_2_SEL = %X'2000'; literal KA0202_CPU$M_CBCTL_SEL_DRACK = %X'4000'; literal KA0202_CPU$M_CBCTL_DWP_H = %X'100000000'; literal KA0202_CPU$M_CBCTL_CAWP_H = %X'600000000'; literal KA0202_CPU$M_CBCTL_EPC_H = %X'800000000'; literal KA0202_CPU$M_CBCTL_FRC_SH_H = %X'1000000000'; literal KA0202_CPU$M_CBCTL_CMDER_ID_H = %X'E000000000'; literal KA0202_CPU$M_CBCTL_ACM_H = %X'70000000000'; literal KA0202_CPU$M_CBCTL_ENB_CI_H = %X'80000000000'; literal KA0202_CPU$M_CBCTL_RD_H = %X'100000000000'; literal KA0202_CPU$M_CBCTL_QW_2_SEL_H = %X'200000000000'; literal KA0202_CPU$M_CBCTL_SEL_DRACK_H = %X'400000000000'; literal KA0202_CPU$M_CBE_RD_L = %X'2'; literal KA0202_CPU$M_CBE_CAP_L = %X'4'; literal KA0202_CPU$M_CBE_MCAP_L = %X'8'; literal KA0202_CPU$M_CBE_PE_WRD_L = %X'10'; literal KA0202_CPU$M_CBE_MPE_WRD_L = %X'20'; literal KA0202_CPU$M_CBE_PE_RD_L = %X'40'; literal KA0202_CPU$M_CBE_MPE_RD_L = %X'80'; literal KA0202_CPU$M_CBE_CA_PE_LW0 = %X'100'; literal KA0202_CPU$M_CBE_CA_PE_LW2 = %X'200'; literal KA0202_CPU$M_CBE_D_PE_LW0 = %X'400'; literal KA0202_CPU$M_CBE_D_PE_LW2 = %X'800'; literal KA0202_CPU$M_CBE_D_PE_LW4 = %X'1000'; literal KA0202_CPU$M_CBE_D_PE_LW6 = %X'2000'; literal KA0202_CPU$M_CBE_CA_NACK = %X'4000'; literal KA0202_CPU$M_CBE_WR_DATA_NACK = %X'8000'; literal KA0202_CPU$M_CBE_MCOUNT = %X'7E000000'; literal KA0202_CPU$M_CBE_MADR_VALID = %X'80000000'; literal KA0202_CPU$M_CBE_RD_H = %X'200000000'; literal KA0202_CPU$M_CBE_CAP_H = %X'400000000'; literal KA0202_CPU$M_CBE_MCAP_H = %X'800000000'; literal KA0202_CPU$M_CBE_PE_WRD_H = %X'1000000000'; literal KA0202_CPU$M_CBE_MPE_WRD_H = %X'2000000000'; literal KA0202_CPU$M_CBE_PE_RD_H = %X'4000000000'; literal KA0202_CPU$M_CBE_MPE_RD_H = %X'8000000000'; literal KA0202_CPU$M_CBE_CA_PE_LW1 = %X'10000000000'; literal KA0202_CPU$M_CBE_CA_PE_LW3 = %X'20000000000'; literal KA0202_CPU$M_CBE_D_PE_LW1 = %X'40000000000'; literal KA0202_CPU$M_CBE_D_PE_LW3 = %X'80000000000'; literal KA0202_CPU$M_CBE_D_PE_LW5 = %X'100000000000'; literal KA0202_CPU$M_CBE_D_PE_LW7 = %X'200000000000'; literal KA0202_CPU$M_CBE_UNDEFINED = %X'400000000000'; literal KA0202_CPU$M_CBE_UNDEFINED2 = %X'800000000000'; literal KA0202_CPU$M_CBE_MCOUNT_H = %X'7E00000000000000'; literal KA0202_CPU$M_CBE_MADR_VALID_H = %X'8000000000000000'; literal KA0202_CPU$M_CBEAL_SBO1 = %X'3'; literal KA0202_CPU$M_CBEAL_ADDR_CAD_L = %X'FFFFFFFC'; literal KA0202_CPU$M_CBEAL_SBO2 = %X'300000000'; literal KA0202_CPU$M_CBEAL_ADDR_CAD_H = %X'FFFFFFFC00000000'; literal KA0202_CPU$M_CBEAH_SBO1 = %X'3'; literal KA0202_CPU$M_CBEAH_EA_L = %X'3FFFC'; literal KA0202_CPU$M_CBEAH_T_TYPE_L = %X'1C0000'; literal KA0202_CPU$M_CBEAH_CMDR_ID_L = %X'E00000'; literal KA0202_CPU$M_CBEAH_SBO2 = %X'FF000000'; literal KA0202_CPU$M_CBEAH_SBO3 = %X'300000000'; literal KA0202_CPU$M_CBEAH_EA_H = %X'3FFFC00000000'; literal KA0202_CPU$M_CBEAH_T_TYPE_H = %X'1C000000000000'; literal KA0202_CPU$M_CBEAH_CMDR_ID_H = %X'E0000000000000'; literal KA0202_CPU$M_CBEAH_SBO4 = %X'FF00000000000000'; literal KA0202_CPU$M_IPIR_UNDEFINED = %X'1'; literal KA0202_CPU$M_IPIR_REQ_INT_CPU = %X'100000000'; literal KA0202_CPU$M_SIC_UNDEFINED = %X'1'; literal KA0202_CPU$M_SIC_UNDEFINED1 = %X'2'; literal KA0202_CPU$M_SIC_EIC = %X'4'; literal KA0202_CPU$M_SIC_IT_ICLEAR = %X'100000000'; literal KA0202_CPU$M_SIC_SYS_EVT_CLR = %X'200000000'; literal KA0202_CPU$M_SIC_UNDEFINED2 = %X'400000000'; literal KA0202_CPU$M_ADLK_LA_V_L = %X'1'; literal KA0202_CPU$M_ADLK_LA_L = %X'FFFFFFF8'; literal KA0202_CPU$M_ADLK_LA_V_H = %X'100000000'; literal KA0202_CPU$M_ADLK_LA_H = %X'FFFFFFF800000000'; literal KA0202_CPU$M_MADRL_VALID_L = %X'1'; literal KA0202_CPU$M_MADRL_T_TYPE_L = %X'2'; literal KA0202_CPU$M_MADRL_ADDRESS_L = %X'FFFFFFFC'; literal KA0202_CPU$M_MADRL_VALID_H = %X'100000000'; literal KA0202_CPU$M_MADRL_T_TYPE_H = %X'200000000'; literal KA0202_CPU$M_MADRL_ADDRESS_H = %X'FFFFFFFC00000000'; literal KA0202_CPU$K_LENGTH = 8192; literal KA0202_CPU$S_CPUDEF = 8192; ! Old size name, synonym for KA0202_CPU$$S_KA0202CPU literal KA0202_CPU$S_KA0202CPU = 8192; macro KA0202_CPU$Q_BCC = 0,0,0,1 %; literal KA0202_CPU$S_BCC = 8; macro KA0202_CPU$V_BCC_ENB_ALLOC_L = 0,0,1,0 %; macro KA0202_CPU$V_BCC_FRC_FILL_SH_L = 0,1,1,0 %; macro KA0202_CPU$V_BCC_ENB_TPC_L = 0,2,1,0 %; macro KA0202_CPU$V_BCC_FILL_WTP_L = 0,3,1,0 %; macro KA0202_CPU$V_BCC_FILL_WCP_L = 0,4,1,0 %; macro KA0202_CPU$V_BCC_FILL_WDTP_L = 0,5,1,0 %; macro KA0202_CPU$V_BCC_ENB_CEI_L = 0,6,1,0 %; macro KA0202_CPU$V_BCC_ENB_EDCC_L = 0,7,1,0 %; macro KA0202_CPU$V_BCC_ENB_EDC_CHK_L = 0,8,1,0 %; macro KA0202_CPU$V_BCC_ENB_BC_CIO_L = 0,9,1,0 %; macro KA0202_CPU$V_BCC_DIS_BLK_W_L = 0,10,1,0 %; macro KA0202_CPU$V_BCC_ENB_BC_INIT_L = 0,11,1,0 %; macro KA0202_CPU$V_BCC_FOR_EDCC_L = 0,12,1,0 %; macro KA0202_CPU$V_BCC_SH_D_V_L = 0,13,3,0 %; literal KA0202_CPU$S_BCC_SH_D_V_L = 3; macro KA0202_CPU$V_BCC_EDC_L = 0,16,14,0 %; literal KA0202_CPU$S_BCC_EDC_L = 14; macro KA0202_CPU$V_BCC_CACHE_SIZE_L = 0,30,2,0 %; literal KA0202_CPU$S_BCC_CACHE_SIZE_L = 2; macro KA0202_CPU$V_BCC_ENB_ALLOC_H = 4,0,1,0 %; macro KA0202_CPU$V_BCC_FRC_FILL_SH_H = 4,1,1,0 %; macro KA0202_CPU$V_BCC_ENB_TPC_H = 4,2,1,0 %; macro KA0202_CPU$V_BCC_FILL_WTP_H = 4,3,1,0 %; macro KA0202_CPU$V_BCC_FILL_WCP_H = 4,4,1,0 %; macro KA0202_CPU$V_BCC_FILL_WDTP_H = 4,5,1,0 %; macro KA0202_CPU$V_BCC_ENB_CEI_H = 4,6,1,0 %; macro KA0202_CPU$V_BCC_ENB_EDCC_H = 4,7,1,0 %; macro KA0202_CPU$V_BCC_ENB_EDC_CHK_H = 4,8,1,0 %; macro KA0202_CPU$V_BCC_ENB_BC_CIO_H = 4,9,1,0 %; macro KA0202_CPU$V_BCC_DIS_BLK_W_H = 4,10,1,0 %; macro KA0202_CPU$V_BCC_ENB_BC_INIT_H = 4,11,1,0 %; macro KA0202_CPU$V_BCC_FOR_EDCC_H = 4,12,1,0 %; macro KA0202_CPU$V_BCC_SH_D_V_H = 4,13,3,0 %; literal KA0202_CPU$S_BCC_SH_D_V_H = 3; macro KA0202_CPU$V_BCC_EDC_L_H = 4,16,14,0 %; literal KA0202_CPU$S_BCC_EDC_L_H = 14; macro KA0202_CPU$V_BCC_CACHE_SIZE_H = 4,30,2,0 %; literal KA0202_CPU$S_BCC_CACHE_SIZE_H = 2; macro KA0202_CPU$b_fill13a = 8,0,0,1 %; literal KA0202_CPU$s_fill13a = 24; macro KA0202_CPU$Q_BCCE = 32,0,0,1 %; literal KA0202_CPU$S_BCCE = 8; macro KA0202_CPU$V_BCCE_MCE = 32,2,1,0 %; macro KA0202_CPU$V_BCCE_CE = 32,3,1,0 %; macro KA0202_CPU$V_BCCE_CNTRL_PAR = 32,8,1,0 %; macro KA0202_CPU$V_BCCE_SH = 32,9,1,0 %; macro KA0202_CPU$V_BCCE_DIRTY = 32,10,1,0 %; macro KA0202_CPU$V_BCCE_VALID = 32,11,1,0 %; macro KA0202_CPU$V_BCCE_BC_EDC_L = 32,17,1,0 %; macro KA0202_CPU$V_BCCE_EDC_SYND_0 = 32,18,7,0 %; literal KA0202_CPU$S_BCCE_EDC_SYND_0 = 7; macro KA0202_CPU$V_BCCE_EDC_SYND_2 = 32,25,7,0 %; literal KA0202_CPU$S_BCCE_EDC_SYND_2 = 7; macro KA0202_CPU$V_BCCE_MCE_H = 36,0,1,0 %; macro KA0202_CPU$V_BCCE_CE_H = 36,1,1,0 %; macro KA0202_CPU$V_BCCE_READ_ONLY = 36,2,13,0 %; literal KA0202_CPU$S_BCCE_READ_ONLY = 13; macro KA0202_CPU$V_BCCE_BC_EDC_H = 36,15,1,0 %; macro KA0202_CPU$V_BCCE_EDC_SYND_1 = 36,16,7,0 %; literal KA0202_CPU$S_BCCE_EDC_SYND_1 = 7; macro KA0202_CPU$V_BCCE_EDC_SYND_3 = 36,23,7,0 %; literal KA0202_CPU$S_BCCE_EDC_SYND_3 = 7; macro KA0202_CPU$b_fill13b = 40,0,0,1 %; literal KA0202_CPU$s_fill13b = 24; macro KA0202_CPU$Q_BCCEA = 64,0,0,1 %; literal KA0202_CPU$S_BCCEA = 8; macro KA0202_CPU$V_BCCEA_BCMAP_OFF = 64,0,17,0 %; literal KA0202_CPU$S_BCCEA_BCMAP_OFF = 17; macro KA0202_CPU$V_BCCEA_TAG_PAR = 64,18,1,0 %; macro KA0202_CPU$V_BCCEA_TAG_VALUE = 64,19,12,0 %; literal KA0202_CPU$S_BCCEA_TAG_VALUE = 12; macro KA0202_CPU$V_BCCEA_BCMAP_OFF_H = 68,0,17,0 %; literal KA0202_CPU$S_BCCEA_BCMAP_OFF_H = 17; macro KA0202_CPU$V_BCCEA_TAG_PAR_H = 68,18,1,0 %; macro KA0202_CPU$V_BCCEA_TAG_VALUE_H = 68,19,12,0 %; literal KA0202_CPU$S_BCCEA_TAG_VALUE_H = 12; macro KA0202_CPU$b_fill13b1 = 72,0,0,1 %; literal KA0202_CPU$s_fill13b1 = 24; macro KA0202_CPU$Q_BCUE = 96,0,0,1 %; literal KA0202_CPU$S_BCUE = 8; macro KA0202_CPU$V_BCUE_MPE = 96,0,1,0 %; macro KA0202_CPU$V_BCUE_PE = 96,1,1,0 %; macro KA0202_CPU$V_BCUE_MUNCE_L = 96,2,1,0 %; macro KA0202_CPU$V_BCUE_UNCE_L = 96,3,1,0 %; macro KA0202_CPU$V_BCUE_CTRL_PAR = 96,8,1,0 %; macro KA0202_CPU$V_BCUE_SH = 96,9,1,0 %; macro KA0202_CPU$V_BCUE_DIRTY = 96,10,1,0 %; macro KA0202_CPU$V_BCUE_VALID = 96,11,1,0 %; macro KA0202_CPU$V_BCUE_BC_EDC_L = 96,17,1,0 %; macro KA0202_CPU$V_BCUE_EDC_SYND_0 = 96,18,7,0 %; literal KA0202_CPU$S_BCUE_EDC_SYND_0 = 7; macro KA0202_CPU$V_BCUE_EDC_SYND_2 = 96,25,7,0 %; literal KA0202_CPU$S_BCUE_EDC_SYND_2 = 7; macro KA0202_CPU$V_BCUE_PE_H = 100,0,1,0 %; macro KA0202_CPU$V_BCUE_MUNCE_H = 100,1,1,0 %; macro KA0202_CPU$V_BCUE_UNCE_H = 100,2,1,0 %; macro KA0202_CPU$V_BCUE_BC_EDC_H = 100,16,1,0 %; macro KA0202_CPU$V_BCUE_EDC_SYND_1 = 100,17,7,0 %; literal KA0202_CPU$S_BCUE_EDC_SYND_1 = 7; macro KA0202_CPU$V_BCUE_EDC_SYND_3 = 100,24,7,0 %; literal KA0202_CPU$S_BCUE_EDC_SYND_3 = 7; macro KA0202_CPU$b_fill13c = 104,0,0,1 %; literal KA0202_CPU$s_fill13c = 24; macro KA0202_CPU$Q_BCUEA = 128,0,0,1 %; literal KA0202_CPU$S_BCUEA = 8; macro KA0202_CPU$V_BCUEA_BCMAP_OFF = 128,0,17,0 %; literal KA0202_CPU$S_BCUEA_BCMAP_OFF = 17; macro KA0202_CPU$V_BCUEA_PTP = 128,17,1,0 %; macro KA0202_CPU$V_BCUEA_TP = 128,18,1,0 %; macro KA0202_CPU$V_BCUEA_TV = 128,19,12,0 %; literal KA0202_CPU$S_BCUEA_TV = 12; macro KA0202_CPU$V_BCUEA_BCMAP_OFF_H = 128,31,17,0 %; literal KA0202_CPU$S_BCUEA_BCMAP_OFF_H = 17; macro KA0202_CPU$V_BCUEA_PTP_H = 132,16,1,0 %; macro KA0202_CPU$V_BCUEA_TP_H = 132,17,1,0 %; macro KA0202_CPU$V_BCUEA_TV_H = 132,18,12,0 %; literal KA0202_CPU$S_BCUEA_TV_H = 12; macro KA0202_CPU$b_fill13d = 136,0,0,1 %; literal KA0202_CPU$s_fill13d = 24; macro KA0202_CPU$Q_DTER = 160,0,0,1 %; literal KA0202_CPU$S_DTER = 8; macro KA0202_CPU$V_MDTER_L = 160,0,1,0 %; macro KA0202_CPU$V_DTER_L = 160,1,1,0 %; macro KA0202_CPU$V_DTER_TOFF_L = 160,2,8,0 %; literal KA0202_CPU$S_DTER_TOFF_L = 8; macro KA0202_CPU$V_DTER_DUP_TAG_L = 160,10,20,0 %; literal KA0202_CPU$S_DTER_DUP_TAG_L = 20; macro KA0202_CPU$V_DTER_DTP = 160,30,1,0 %; macro KA0202_CPU$V_MDTER_H = 164,0,1,0 %; macro KA0202_CPU$V_DTER_H = 164,1,1,0 %; macro KA0202_CPU$V_DTER_DT_H = 164,2,8,0 %; literal KA0202_CPU$S_DTER_DT_H = 8; macro KA0202_CPU$V_DTER_DUP_TAG_H = 164,10,20,0 %; literal KA0202_CPU$S_DTER_DUP_TAG_H = 20; macro KA0202_CPU$V_DTER_DTP_H = 164,30,1,0 %; macro KA0202_CPU$b_fill13e = 168,0,0,1 %; literal KA0202_CPU$s_fill13e = 24; macro KA0202_CPU$Q_CBCTL = 192,0,0,1 %; literal KA0202_CPU$S_CBCTL = 8; macro KA0202_CPU$V_CBCTL_DWP = 192,0,1,0 %; macro KA0202_CPU$V_CBCTL_CAWP = 192,1,2,0 %; literal KA0202_CPU$S_CBCTL_CAWP = 2; macro KA0202_CPU$V_CBCTL_EPC = 192,3,1,0 %; macro KA0202_CPU$V_CBCTL_FRC_SH = 192,4,1,0 %; macro KA0202_CPU$V_CBCTL_CMDER_ID = 192,5,3,0 %; literal KA0202_CPU$S_CBCTL_CMDER_ID = 3; macro KA0202_CPU$V_CBCTL_ACM = 192,8,3,0 %; literal KA0202_CPU$S_CBCTL_ACM = 3; macro KA0202_CPU$V_CBCTL_ENB_CI = 192,11,1,0 %; macro KA0202_CPU$V_CBCTL_RD = 192,12,1,0 %; macro KA0202_CPU$V_CBCTL_QW_2_SEL = 192,13,1,0 %; macro KA0202_CPU$V_CBCTL_SEL_DRACK = 192,14,1,0 %; macro KA0202_CPU$V_CBCTL_DWP_H = 196,0,1,0 %; macro KA0202_CPU$V_CBCTL_CAWP_H = 196,1,2,0 %; literal KA0202_CPU$S_CBCTL_CAWP_H = 2; macro KA0202_CPU$V_CBCTL_EPC_H = 196,3,1,0 %; macro KA0202_CPU$V_CBCTL_FRC_SH_H = 196,4,1,0 %; macro KA0202_CPU$V_CBCTL_CMDER_ID_H = 196,5,3,0 %; literal KA0202_CPU$S_CBCTL_CMDER_ID_H = 3; macro KA0202_CPU$V_CBCTL_ACM_H = 196,8,3,0 %; literal KA0202_CPU$S_CBCTL_ACM_H = 3; macro KA0202_CPU$V_CBCTL_ENB_CI_H = 196,11,1,0 %; macro KA0202_CPU$V_CBCTL_RD_H = 196,12,1,0 %; macro KA0202_CPU$V_CBCTL_QW_2_SEL_H = 196,13,1,0 %; macro KA0202_CPU$V_CBCTL_SEL_DRACK_H = 196,14,1,0 %; macro KA0202_CPU$b_fill13f = 200,0,0,1 %; literal KA0202_CPU$s_fill13f = 24; macro KA0202_CPU$Q_CBE = 224,0,0,1 %; literal KA0202_CPU$S_CBE = 8; macro KA0202_CPU$V_CBE_RD_L = 224,1,1,0 %; macro KA0202_CPU$V_CBE_CAP_L = 224,2,1,0 %; macro KA0202_CPU$V_CBE_MCAP_L = 224,3,1,0 %; macro KA0202_CPU$V_CBE_PE_WRD_L = 224,4,1,0 %; macro KA0202_CPU$V_CBE_MPE_WRD_L = 224,5,1,0 %; macro KA0202_CPU$V_CBE_PE_RD_L = 224,6,1,0 %; macro KA0202_CPU$V_CBE_MPE_RD_L = 224,7,1,0 %; macro KA0202_CPU$V_CBE_CA_PE_LW0 = 224,8,1,0 %; macro KA0202_CPU$V_CBE_CA_PE_LW2 = 224,9,1,0 %; macro KA0202_CPU$V_CBE_D_PE_LW0 = 224,10,1,0 %; macro KA0202_CPU$V_CBE_D_PE_LW2 = 224,11,1,0 %; macro KA0202_CPU$V_CBE_D_PE_LW4 = 224,12,1,0 %; macro KA0202_CPU$V_CBE_D_PE_LW6 = 224,13,1,0 %; macro KA0202_CPU$V_CBE_CA_NACK = 224,14,1,0 %; macro KA0202_CPU$V_CBE_WR_DATA_NACK = 224,15,1,0 %; macro KA0202_CPU$V_CBE_MCOUNT = 224,25,6,0 %; literal KA0202_CPU$S_CBE_MCOUNT = 6; macro KA0202_CPU$V_CBE_MADR_VALID = 224,31,1,0 %; macro KA0202_CPU$V_CBE_RD_H = 228,1,1,0 %; macro KA0202_CPU$V_CBE_CAP_H = 228,2,1,0 %; macro KA0202_CPU$V_CBE_MCAP_H = 228,3,1,0 %; macro KA0202_CPU$V_CBE_PE_WRD_H = 228,4,1,0 %; macro KA0202_CPU$V_CBE_MPE_WRD_H = 228,5,1,0 %; macro KA0202_CPU$V_CBE_PE_RD_H = 228,6,1,0 %; macro KA0202_CPU$V_CBE_MPE_RD_H = 228,7,1,0 %; macro KA0202_CPU$V_CBE_CA_PE_LW1 = 228,8,1,0 %; macro KA0202_CPU$V_CBE_CA_PE_LW3 = 228,9,1,0 %; macro KA0202_CPU$V_CBE_D_PE_LW1 = 228,10,1,0 %; macro KA0202_CPU$V_CBE_D_PE_LW3 = 228,11,1,0 %; macro KA0202_CPU$V_CBE_D_PE_LW5 = 228,12,1,0 %; macro KA0202_CPU$V_CBE_D_PE_LW7 = 228,13,1,0 %; macro KA0202_CPU$V_CBE_UNDEFINED = 228,14,1,0 %; macro KA0202_CPU$V_CBE_UNDEFINED2 = 228,15,1,0 %; macro KA0202_CPU$V_CBE_MCOUNT_H = 228,25,6,0 %; literal KA0202_CPU$S_CBE_MCOUNT_H = 6; macro KA0202_CPU$V_CBE_MADR_VALID_H = 228,31,1,0 %; macro KA0202_CPU$b_fill13g = 232,0,0,1 %; literal KA0202_CPU$s_fill13g = 24; macro KA0202_CPU$Q_CBEAL = 256,0,0,1 %; literal KA0202_CPU$S_CBEAL = 8; macro KA0202_CPU$V_CBEAL_SBO1 = 256,0,2,0 %; literal KA0202_CPU$S_CBEAL_SBO1 = 2; macro KA0202_CPU$V_CBEAL_ADDR_CAD_L = 256,2,30,0 %; literal KA0202_CPU$S_CBEAL_ADDR_CAD_L = 30; macro KA0202_CPU$V_CBEAL_SBO2 = 260,0,2,0 %; literal KA0202_CPU$S_CBEAL_SBO2 = 2; macro KA0202_CPU$V_CBEAL_ADDR_CAD_H = 260,2,30,0 %; literal KA0202_CPU$S_CBEAL_ADDR_CAD_H = 30; macro KA0202_CPU$b_fill13h = 264,0,0,1 %; literal KA0202_CPU$s_fill13h = 24; macro KA0202_CPU$Q_CBEAH = 288,0,0,1 %; literal KA0202_CPU$S_CBEAH = 8; macro KA0202_CPU$V_CBEAH_SBO1 = 288,0,2,0 %; literal KA0202_CPU$S_CBEAH_SBO1 = 2; macro KA0202_CPU$V_CBEAH_EA_L = 288,2,16,0 %; literal KA0202_CPU$S_CBEAH_EA_L = 16; macro KA0202_CPU$V_CBEAH_T_TYPE_L = 288,18,3,0 %; literal KA0202_CPU$S_CBEAH_T_TYPE_L = 3; macro KA0202_CPU$V_CBEAH_CMDR_ID_L = 288,21,3,0 %; literal KA0202_CPU$S_CBEAH_CMDR_ID_L = 3; macro KA0202_CPU$V_CBEAH_SBO2 = 288,24,8,0 %; literal KA0202_CPU$S_CBEAH_SBO2 = 8; macro KA0202_CPU$V_CBEAH_SBO3 = 292,0,2,0 %; literal KA0202_CPU$S_CBEAH_SBO3 = 2; macro KA0202_CPU$V_CBEAH_EA_H = 292,2,16,0 %; literal KA0202_CPU$S_CBEAH_EA_H = 16; macro KA0202_CPU$V_CBEAH_T_TYPE_H = 292,18,3,0 %; literal KA0202_CPU$S_CBEAH_T_TYPE_H = 3; macro KA0202_CPU$V_CBEAH_CMDR_ID_H = 292,21,3,0 %; literal KA0202_CPU$S_CBEAH_CMDR_ID_H = 3; macro KA0202_CPU$V_CBEAH_SBO4 = 292,24,8,0 %; literal KA0202_CPU$S_CBEAH_SBO4 = 8; macro KA0202_CPU$b_fill13 = 296,0,0,1 %; literal KA0202_CPU$s_fill13 = 24; macro KA0202_CPU$Q_PMBX = 320,0,0,1 %; literal KA0202_CPU$S_PMBX = 8; macro KA0202_CPU$b_fill13j = 328,0,0,1 %; literal KA0202_CPU$s_fill13j = 24; macro KA0202_CPU$Q_IPIR = 352,0,0,1 %; literal KA0202_CPU$S_IPIR = 8; macro KA0202_CPU$V_IPIR_UNDEFINED = 352,0,1,0 %; macro KA0202_CPU$V_IPIR_REQ_INT_CPU = 356,0,1,0 %; macro KA0202_CPU$b_fill13k = 360,0,0,1 %; literal KA0202_CPU$s_fill13k = 24; macro KA0202_CPU$Q_SIC = 384,0,0,1 %; literal KA0202_CPU$S_SIC = 8; macro KA0202_CPU$V_SIC_UNDEFINED = 384,0,1,0 %; macro KA0202_CPU$V_SIC_UNDEFINED1 = 384,1,1,0 %; macro KA0202_CPU$V_SIC_EIC = 384,2,1,0 %; macro KA0202_CPU$V_SIC_IT_ICLEAR = 388,0,1,0 %; macro KA0202_CPU$V_SIC_SYS_EVT_CLR = 388,1,1,0 %; macro KA0202_CPU$V_SIC_UNDEFINED2 = 388,2,1,0 %; macro KA0202_CPU$b_fill13l = 392,0,0,1 %; literal KA0202_CPU$s_fill13l = 24; macro KA0202_CPU$Q_ADLK = 416,0,0,1 %; literal KA0202_CPU$S_ADLK = 8; macro KA0202_CPU$V_ADLK_LA_V_L = 416,0,1,0 %; macro KA0202_CPU$V_ADLK_LA_L = 416,3,29,0 %; literal KA0202_CPU$S_ADLK_LA_L = 29; macro KA0202_CPU$V_ADLK_LA_V_H = 420,0,1,0 %; macro KA0202_CPU$V_ADLK_LA_H = 420,3,29,0 %; literal KA0202_CPU$S_ADLK_LA_H = 29; macro KA0202_CPU$b_fill13m = 424,0,0,1 %; literal KA0202_CPU$s_fill13m = 24; macro KA0202_CPU$Q_MADRL = 448,0,0,1 %; literal KA0202_CPU$S_MADRL = 8; macro KA0202_CPU$V_MADRL_VALID_L = 448,0,1,0 %; macro KA0202_CPU$V_MADRL_T_TYPE_L = 448,1,1,0 %; macro KA0202_CPU$V_MADRL_ADDRESS_L = 448,2,30,0 %; literal KA0202_CPU$S_MADRL_ADDRESS_L = 30; macro KA0202_CPU$V_MADRL_VALID_H = 452,0,1,0 %; macro KA0202_CPU$V_MADRL_T_TYPE_H = 452,1,1,0 %; macro KA0202_CPU$V_MADRL_ADDRESS_H = 452,2,30,0 %; literal KA0202_CPU$S_MADRL_ADDRESS_H = 30; macro KA0202_CPU$b_fill13n = 456,0,0,1 %; literal KA0202_CPU$s_fill13n = 24; macro KA0202_CPU$Q_UNIMP = 480,0,0,1 %; literal KA0202_CPU$S_UNIMP = 8; macro KA0202_CPU$b_fill15 = 488,0,0,1 %; literal KA0202_CPU$s_fill15 = 7704; literal KA0202_CMM$M_CME_ES1 = %X'1'; literal KA0202_CMM$M_CME_SE1 = %X'2'; literal KA0202_CMM$M_CME_CA_PE1 = %X'4'; literal KA0202_CMM$M_CME_MCA_PE1 = %X'8'; literal KA0202_CMM$M_CME_WD_PE1 = %X'10'; literal KA0202_CMM$M_CME_MWD_PE1 = %X'20'; literal KA0202_CMM$M_CME_CA_PE_LW0 = %X'100'; literal KA0202_CMM$M_CME_CA_PE_LW2 = %X'200'; literal KA0202_CMM$M_CME_D_PE_LW0 = %X'400'; literal KA0202_CMM$M_CME_D_PE_LW2 = %X'800'; literal KA0202_CMM$M_CME_D_PE_LW4 = %X'1000'; literal KA0202_CMM$M_CME_D_PE_LW6 = %X'2000'; literal KA0202_CMM$M_CME_EUE1 = %X'10000'; literal KA0202_CMM$M_CME_MEUE1 = %X'20000'; literal KA0202_CMM$M_CME_ECE1 = %X'40000'; literal KA0202_CMM$M_CME_MECE1 = %X'80000'; literal KA0202_CMM$M_CME_ES2 = %X'100000000'; literal KA0202_CMM$M_CME_SE2 = %X'200000000'; literal KA0202_CMM$M_CME_CA_PE2 = %X'400000000'; literal KA0202_CMM$M_CME_MCA_PE2 = %X'800000000'; literal KA0202_CMM$M_CME_WD_PE2 = %X'1000000000'; literal KA0202_CMM$M_CME_MWD_PE2 = %X'2000000000'; literal KA0202_CMM$M_CME_CA_PE_LW1 = %X'10000000000'; literal KA0202_CMM$M_CME_CA_PE_LW3 = %X'20000000000'; literal KA0202_CMM$M_CME_D_PE_LW1 = %X'40000000000'; literal KA0202_CMM$M_CME_D_PE_LW3 = %X'80000000000'; literal KA0202_CMM$M_CME_D_PE_LW5 = %X'100000000000'; literal KA0202_CMM$M_CME_D_PE_LW7 = %X'200000000000'; literal KA0202_CMM$M_CME_EUE2 = %X'1000000000000'; literal KA0202_CMM$M_CME_MEUE2 = %X'2000000000000'; literal KA0202_CMM$M_CME_ECE2 = %X'4000000000000'; literal KA0202_CMM$M_CME_MECE2 = %X'8000000000000'; literal KA0202_CMM$M_CNFG_MOD_ID1 = %X'3'; literal KA0202_CMM$M_CNFG_MOD_SIZE1 = %X'70'; literal KA0202_CMM$M_CNFG_EMD1 = %X'100'; literal KA0202_CMM$M_CNFG_INTR_MODE1 = %X'C0000'; literal KA0202_CMM$M_CNFG_INTR_UNIT1 = %X'300000'; literal KA0202_CMM$M_CNFG_BASE_ADDR1 = %X'7FC00000'; literal KA0202_CMM$M_CNFG_MEM_ENB1 = %X'80000000'; literal KA0202_CMM$M_CNFG_MOD_ID2 = %X'300000000'; literal KA0202_CMM$M_CNFG_MOD_SIZE2 = %X'7000000000'; literal KA0202_CMM$M_CNFG_EMD2 = %X'10000000000'; literal KA0202_CMM$M_CNFG_INTR_MODE2 = %X'C000000000000'; literal KA0202_CMM$M_CNFG_INTR_UNIT2 = %X'30000000000000'; literal KA0202_CMM$M_CNFG_BASE_ADDR2 = %X'7FC0000000000000'; literal KA0202_CMM$M_CNFG_MEM_ENB2 = %X'8000000000000000'; literal KA0202_CMM$M_EDC1_READ_CBITS1 = %X'FFF'; literal KA0202_CMM$M_EDC1_WR_CBITS1 = %X'FFF0000'; literal KA0202_CMM$M_EDC1_READ_CBITS2 = %X'FFF00000000'; literal KA0202_CMM$M_EDC1_WR_CBITS2 = %X'FFF000000000000'; literal KA0202_CMM$M_EDC2_SYNDROME1 = %X'FFF'; literal KA0202_CMM$M_EDC2_SYNDROME2 = %X'FFF00000000'; literal KA0202_CMM$M_EDCTL_SRB1 = %X'FFF'; literal KA0202_CMM$M_EDCTL_USCB1 = %X'1000'; literal KA0202_CMM$M_EDCTL_USWCB1 = %X'2000'; literal KA0202_CMM$M_EDCTL_DIPC1 = %X'4000'; literal KA0202_CMM$M_EDCTL_ENB_ES1 = %X'8000'; literal KA0202_CMM$M_EDCTL_SWCB1 = %X'FFF0000'; literal KA0202_CMM$M_EDCTL_CRDP1 = %X'10000000'; literal KA0202_CMM$M_EDCTL_ENB_CRDR1 = %X'20000000'; literal KA0202_CMM$M_EDCTL_DEDCCORR1 = %X'40000000'; literal KA0202_CMM$M_EDCTL_DEDCREPORT1 = %X'80000000'; literal KA0202_CMM$M_EDCTL_SRB2 = %X'FFF00000000'; literal KA0202_CMM$M_EDCTL_USCB2 = %X'100000000000'; literal KA0202_CMM$M_EDCTL_USWCB2 = %X'200000000000'; literal KA0202_CMM$M_EDCTL_DIPC2 = %X'400000000000'; literal KA0202_CMM$M_EDCTL_ENB_ES2 = %X'800000000000'; literal KA0202_CMM$M_EDCTL_SWCB2 = %X'FFF000000000000'; literal KA0202_CMM$M_EDCTL_CRDP2 = %X'1000000000000000'; literal KA0202_CMM$M_EDCTL_ENB_CRDR2 = %X'2000000000000000'; literal KA0202_CMM$M_EDCTL_DEDCCORR2 = %X'4000000000000000'; literal KA0202_CMM$M_EDCTL_DEDCREPORT2 = %X'8000000000000000'; literal KA0202_CMM$M_SBCTRL_DSD1 = %X'1'; literal KA0202_CMM$M_SBCTRL_DSH1 = %X'2'; literal KA0202_CMM$M_SBCTRL_DSF1 = %X'4'; literal KA0202_CMM$M_SBCTRL_DSI1 = %X'8'; literal KA0202_CMM$M_SBCTRL_ERWD1 = %X'10'; literal KA0202_CMM$M_SBCTRL_FHB1 = %X'20'; literal KA0202_CMM$M_SBCTRL_DSD2 = %X'100000000'; literal KA0202_CMM$M_SBCTRL_DSH2 = %X'200000000'; literal KA0202_CMM$M_SBCTRL_DSF2 = %X'400000000'; literal KA0202_CMM$M_SBCTRL_DSI2 = %X'800000000'; literal KA0202_CMM$M_SBCTRL_ERWD2 = %X'1000000000'; literal KA0202_CMM$M_SBCTRL_FHB2 = %X'2000000000'; literal KA0202_CMM$M_RCTRL_RC1 = %X'FF'; literal KA0202_CMM$M_RCTRL_REF_ENB = %X'100'; literal KA0202_CMM$M_RCTRL_RC2 = %X'FF00000000'; literal KA0202_CMM$M_RCTRL_REF_ENB2 = %X'10000000000'; literal KA0202_CMM$M_CRDCTL_SM1 = %X'FFF'; literal KA0202_CMM$M_CRDCTL_BS1 = %X'3000'; literal KA0202_CMM$M_CRDCTL_CFE1 = %X'4000'; literal KA0202_CMM$M_CRDCTL_SM2 = %X'FFF00000000'; literal KA0202_CMM$M_CRDCTL_BS2 = %X'300000000000'; literal KA0202_CMM$M_CRDCTL_CFE2 = %X'400000000000'; literal KA0202_CMM$K_LENGTH = 8192; literal KA0202_CMM$S_CMMDEF = 8192; ! Old size name, synonym for KA0202_CMM$S_KA0202CMM literal KA0202_CMM$S_KA0202CMM = 8192; macro KA0202_CMM$Q_CME = 0,0,0,1 %; literal KA0202_CMM$S_CME = 8; macro KA0202_CMM$V_CME_ES1 = 0,0,1,0 %; macro KA0202_CMM$V_CME_SE1 = 0,1,1,0 %; macro KA0202_CMM$V_CME_CA_PE1 = 0,2,1,0 %; macro KA0202_CMM$V_CME_MCA_PE1 = 0,3,1,0 %; macro KA0202_CMM$V_CME_WD_PE1 = 0,4,1,0 %; macro KA0202_CMM$V_CME_MWD_PE1 = 0,5,1,0 %; macro KA0202_CMM$V_CME_CA_PE_LW0 = 0,8,1,0 %; macro KA0202_CMM$V_CME_CA_PE_LW2 = 0,9,1,0 %; macro KA0202_CMM$V_CME_D_PE_LW0 = 0,10,1,0 %; macro KA0202_CMM$V_CME_D_PE_LW2 = 0,11,1,0 %; macro KA0202_CMM$V_CME_D_PE_LW4 = 0,12,1,0 %; macro KA0202_CMM$V_CME_D_PE_LW6 = 0,13,1,0 %; macro KA0202_CMM$V_CME_EUE1 = 0,16,1,0 %; macro KA0202_CMM$V_CME_MEUE1 = 0,17,1,0 %; macro KA0202_CMM$V_CME_ECE1 = 0,18,1,0 %; macro KA0202_CMM$V_CME_MECE1 = 0,19,1,0 %; macro KA0202_CMM$V_CME_ES2 = 4,0,1,0 %; macro KA0202_CMM$V_CME_SE2 = 4,1,1,0 %; macro KA0202_CMM$V_CME_CA_PE2 = 4,2,1,0 %; macro KA0202_CMM$V_CME_MCA_PE2 = 4,3,1,0 %; macro KA0202_CMM$V_CME_WD_PE2 = 4,4,1,0 %; macro KA0202_CMM$V_CME_MWD_PE2 = 4,5,1,0 %; macro KA0202_CMM$V_CME_CA_PE_LW1 = 4,8,1,0 %; macro KA0202_CMM$V_CME_CA_PE_LW3 = 4,9,1,0 %; macro KA0202_CMM$V_CME_D_PE_LW1 = 4,10,1,0 %; macro KA0202_CMM$V_CME_D_PE_LW3 = 4,11,1,0 %; macro KA0202_CMM$V_CME_D_PE_LW5 = 4,12,1,0 %; macro KA0202_CMM$V_CME_D_PE_LW7 = 4,13,1,0 %; macro KA0202_CMM$V_CME_EUE2 = 4,16,1,0 %; macro KA0202_CMM$V_CME_MEUE2 = 4,17,1,0 %; macro KA0202_CMM$V_CME_ECE2 = 4,18,1,0 %; macro KA0202_CMM$V_CME_MECE2 = 4,19,1,0 %; macro KA0202_CMM$b_fill_1 = 8,0,0,1 %; literal KA0202_CMM$s_fill_1 = 24; macro KA0202_CMM$Q_TRAP1 = 32,0,0,1 %; literal KA0202_CMM$S_TRAP1 = 8; macro KA0202_CMM$L_TRAP1_L = 32,0,32,0 %; macro KA0202_CMM$L_TRAP1_H = 36,0,32,0 %; macro KA0202_CMM$b_fill_2 = 40,0,0,1 %; literal KA0202_CMM$s_fill_2 = 24; macro KA0202_CMM$Q_TRAP2 = 64,0,0,1 %; literal KA0202_CMM$S_TRAP2 = 8; macro KA0202_CMM$L_TRAP2_L = 64,0,32,0 %; macro KA0202_CMM$L_TRAP2_H = 68,0,32,0 %; macro KA0202_CMM$b_fill_3 = 72,0,0,1 %; literal KA0202_CMM$s_fill_3 = 24; macro KA0202_CMM$Q_CNFG = 96,0,0,1 %; literal KA0202_CMM$S_CNFG = 8; macro KA0202_CMM$V_CNFG_MOD_ID1 = 96,0,2,0 %; literal KA0202_CMM$S_CNFG_MOD_ID1 = 2; macro KA0202_CMM$V_CNFG_MOD_SIZE1 = 96,4,3,0 %; literal KA0202_CMM$S_CNFG_MOD_SIZE1 = 3; macro KA0202_CMM$V_CNFG_EMD1 = 96,8,1,0 %; macro KA0202_CMM$V_CNFG_INTR_MODE1 = 96,18,2,0 %; literal KA0202_CMM$S_CNFG_INTR_MODE1 = 2; macro KA0202_CMM$V_CNFG_INTR_UNIT1 = 96,20,2,0 %; literal KA0202_CMM$S_CNFG_INTR_UNIT1 = 2; macro KA0202_CMM$V_CNFG_BASE_ADDR1 = 96,22,9,0 %; literal KA0202_CMM$S_CNFG_BASE_ADDR1 = 9; macro KA0202_CMM$V_CNFG_MEM_ENB1 = 96,31,1,0 %; macro KA0202_CMM$V_CNFG_MOD_ID2 = 100,0,2,0 %; literal KA0202_CMM$S_CNFG_MOD_ID2 = 2; macro KA0202_CMM$V_CNFG_MOD_SIZE2 = 100,4,3,0 %; literal KA0202_CMM$S_CNFG_MOD_SIZE2 = 3; macro KA0202_CMM$V_CNFG_EMD2 = 100,8,1,0 %; macro KA0202_CMM$V_CNFG_INTR_MODE2 = 100,18,2,0 %; literal KA0202_CMM$S_CNFG_INTR_MODE2 = 2; macro KA0202_CMM$V_CNFG_INTR_UNIT2 = 100,20,2,0 %; literal KA0202_CMM$S_CNFG_INTR_UNIT2 = 2; macro KA0202_CMM$V_CNFG_BASE_ADDR2 = 100,22,9,0 %; literal KA0202_CMM$S_CNFG_BASE_ADDR2 = 9; macro KA0202_CMM$V_CNFG_MEM_ENB2 = 100,31,1,0 %; macro KA0202_CMM$b_fill_4 = 104,0,0,1 %; literal KA0202_CMM$s_fill_4 = 24; macro KA0202_CMM$Q_EDC1 = 128,0,0,1 %; literal KA0202_CMM$S_EDC1 = 8; macro KA0202_CMM$V_EDC1_READ_CBITS1 = 128,0,12,0 %; literal KA0202_CMM$S_EDC1_READ_CBITS1 = 12; macro KA0202_CMM$V_EDC1_WR_CBITS1 = 128,16,12,0 %; literal KA0202_CMM$S_EDC1_WR_CBITS1 = 12; macro KA0202_CMM$V_EDC1_READ_CBITS2 = 132,0,12,0 %; literal KA0202_CMM$S_EDC1_READ_CBITS2 = 12; macro KA0202_CMM$V_EDC1_WR_CBITS2 = 132,16,12,0 %; literal KA0202_CMM$S_EDC1_WR_CBITS2 = 12; macro KA0202_CMM$b_fill_5 = 136,0,0,1 %; literal KA0202_CMM$s_fill_5 = 24; macro KA0202_CMM$Q_EDC2 = 160,0,0,1 %; literal KA0202_CMM$S_EDC2 = 8; macro KA0202_CMM$V_EDC2_SYNDROME1 = 160,0,12,0 %; literal KA0202_CMM$S_EDC2_SYNDROME1 = 12; macro KA0202_CMM$V_EDC2_SYNDROME2 = 164,0,12,0 %; literal KA0202_CMM$S_EDC2_SYNDROME2 = 12; macro KA0202_CMM$b_fill_6 = 168,0,0,1 %; literal KA0202_CMM$s_fill_6 = 24; macro KA0202_CMM$Q_EDCTL = 192,0,0,1 %; literal KA0202_CMM$S_EDCTL = 8; macro KA0202_CMM$V_EDCTL_SRB1 = 192,0,12,0 %; literal KA0202_CMM$S_EDCTL_SRB1 = 12; macro KA0202_CMM$V_EDCTL_USCB1 = 192,12,1,0 %; macro KA0202_CMM$V_EDCTL_USWCB1 = 192,13,1,0 %; macro KA0202_CMM$V_EDCTL_DIPC1 = 192,14,1,0 %; macro KA0202_CMM$V_EDCTL_ENB_ES1 = 192,15,1,0 %; macro KA0202_CMM$V_EDCTL_SWCB1 = 192,16,12,0 %; literal KA0202_CMM$S_EDCTL_SWCB1 = 12; macro KA0202_CMM$V_EDCTL_CRDP1 = 192,28,1,0 %; macro KA0202_CMM$V_EDCTL_ENB_CRDR1 = 192,29,1,0 %; macro KA0202_CMM$V_EDCTL_DEDCCORR1 = 192,30,1,0 %; macro KA0202_CMM$V_EDCTL_DEDCREPORT1 = 192,31,1,0 %; macro KA0202_CMM$V_EDCTL_SRB2 = 196,0,12,0 %; literal KA0202_CMM$S_EDCTL_SRB2 = 12; macro KA0202_CMM$V_EDCTL_USCB2 = 196,12,1,0 %; macro KA0202_CMM$V_EDCTL_USWCB2 = 196,13,1,0 %; macro KA0202_CMM$V_EDCTL_DIPC2 = 196,14,1,0 %; macro KA0202_CMM$V_EDCTL_ENB_ES2 = 196,15,1,0 %; macro KA0202_CMM$V_EDCTL_SWCB2 = 196,16,12,0 %; literal KA0202_CMM$S_EDCTL_SWCB2 = 12; macro KA0202_CMM$V_EDCTL_CRDP2 = 196,28,1,0 %; macro KA0202_CMM$V_EDCTL_ENB_CRDR2 = 196,29,1,0 %; macro KA0202_CMM$V_EDCTL_DEDCCORR2 = 196,30,1,0 %; macro KA0202_CMM$V_EDCTL_DEDCREPORT2 = 196,31,1,0 %; macro KA0202_CMM$b_fill_7 = 200,0,0,1 %; literal KA0202_CMM$s_fill_7 = 24; macro KA0202_CMM$Q_SBCTRL = 224,0,0,1 %; literal KA0202_CMM$S_SBCTRL = 8; macro KA0202_CMM$V_SBCTRL_DSD1 = 224,0,1,0 %; macro KA0202_CMM$V_SBCTRL_DSH1 = 224,1,1,0 %; macro KA0202_CMM$V_SBCTRL_DSF1 = 224,2,1,0 %; macro KA0202_CMM$V_SBCTRL_DSI1 = 224,3,1,0 %; macro KA0202_CMM$V_SBCTRL_ERWD1 = 224,4,1,0 %; macro KA0202_CMM$V_SBCTRL_FHB1 = 224,5,1,0 %; macro KA0202_CMM$V_SBCTRL_DSD2 = 228,0,1,0 %; macro KA0202_CMM$V_SBCTRL_DSH2 = 228,1,1,0 %; macro KA0202_CMM$V_SBCTRL_DSF2 = 228,2,1,0 %; macro KA0202_CMM$V_SBCTRL_DSI2 = 228,3,1,0 %; macro KA0202_CMM$V_SBCTRL_ERWD2 = 228,4,1,0 %; macro KA0202_CMM$V_SBCTRL_FHB2 = 228,5,1,0 %; macro KA0202_CMM$b_fill_8 = 232,0,0,1 %; literal KA0202_CMM$s_fill_8 = 24; macro KA0202_CMM$Q_RCTRL = 256,0,0,1 %; literal KA0202_CMM$S_RCTRL = 8; macro KA0202_CMM$V_RCTRL_RC1 = 256,0,8,0 %; literal KA0202_CMM$S_RCTRL_RC1 = 8; macro KA0202_CMM$V_RCTRL_REF_ENB = 256,8,1,0 %; macro KA0202_CMM$V_RCTRL_RC2 = 260,0,8,0 %; literal KA0202_CMM$S_RCTRL_RC2 = 8; macro KA0202_CMM$V_RCTRL_REF_ENB2 = 260,8,1,0 %; macro KA0202_CMM$b_fill_9 = 264,0,0,1 %; literal KA0202_CMM$s_fill_9 = 24; macro KA0202_CMM$Q_CRDCTL = 288,0,0,1 %; literal KA0202_CMM$S_CRDCTL = 8; macro KA0202_CMM$V_CRDCTL_SM1 = 288,0,12,0 %; literal KA0202_CMM$S_CRDCTL_SM1 = 12; macro KA0202_CMM$V_CRDCTL_BS1 = 288,12,2,0 %; literal KA0202_CMM$S_CRDCTL_BS1 = 2; macro KA0202_CMM$V_CRDCTL_CFE1 = 288,14,1,0 %; macro KA0202_CMM$V_CRDCTL_SM2 = 292,0,12,0 %; literal KA0202_CMM$S_CRDCTL_SM2 = 12; macro KA0202_CMM$V_CRDCTL_BS2 = 292,12,2,0 %; literal KA0202_CMM$S_CRDCTL_BS2 = 2; macro KA0202_CMM$V_CRDCTL_CFE2 = 292,14,1,0 %; macro KA0202_CMM$b_fill_10 = 296,0,0,1 %; literal KA0202_CMM$s_fill_10 = 24; macro KA0202_CMM$Q_CSR10 = 320,0,0,1 %; literal KA0202_CMM$S_CSR10 = 8; macro KA0202_CMM$b_fill_11 = 328,0,0,1 %; literal KA0202_CMM$s_fill_11 = 24; macro KA0202_CMM$Q_CSR11 = 352,0,0,1 %; literal KA0202_CMM$S_CSR11 = 8; macro KA0202_CMM$b_fill_12 = 360,0,0,1 %; literal KA0202_CMM$s_fill_12 = 24; macro KA0202_CMM$Q_CSR12 = 384,0,0,1 %; literal KA0202_CMM$S_CSR12 = 8; macro KA0202_CMM$b_fill_13 = 392,0,0,1 %; literal KA0202_CMM$s_fill_13 = 24; macro KA0202_CMM$Q_CSR13 = 416,0,0,1 %; literal KA0202_CMM$S_CSR13 = 8; macro KA0202_CMM$b_fill_14 = 424,0,0,1 %; literal KA0202_CMM$s_fill_14 = 24; macro KA0202_CMM$Q_CSR14 = 448,0,0,1 %; literal KA0202_CMM$S_CSR14 = 8; macro KA0202_CMM$b_fill_15 = 456,0,0,1 %; literal KA0202_CMM$s_fill_15 = 24; macro KA0202_CMM$Q_CSR15 = 480,0,0,1 %; literal KA0202_CMM$S_CSR15 = 8; macro KA0202_CMM$b_fill17 = 488,0,0,1 %; literal KA0202_CMM$s_fill17 = 7704; !*** MODULE $KA0302DEF *** literal KA0302$M_SLOT0_LDEV_DTYPE = %X'FFFF'; literal KA0302$M_SLOT0_LDEV_DREV = %X'FFFF0000'; literal KA0302$M_SLOT0_LBER_E = %X'1'; literal KA0302$M_SLOT0_LBER_UCE = %X'2'; literal KA0302$M_SLOT0_LBER_UCE2 = %X'4'; literal KA0302$M_SLOT0_LBER_CE = %X'8'; literal KA0302$M_SLOT0_LBER_CE2 = %X'10'; literal KA0302$M_SLOT0_LBER_CPE = %X'20'; literal KA0302$M_SLOT0_LBER_CPE2 = %X'40'; literal KA0302$M_SLOT0_LBER_CDPE = %X'80'; literal KA0302$M_SLOT0_LBER_CDPE2 = %X'100'; literal KA0302$M_SLOT0_LBER_TDE = %X'200'; literal KA0302$M_SLOT0_LBER_STE = %X'400'; literal KA0302$M_SLOT0_LBER_CNFE = %X'800'; literal KA0302$M_SLOT0_LBER_NXAE = %X'1000'; literal KA0302$M_SLOT0_LBER_CAE = %X'2000'; literal KA0302$M_SLOT0_LBER_SHE = %X'4000'; literal KA0302$M_SLOT0_LBER_DIE = %X'8000'; literal KA0302$M_SLOT0_LBER_DTCE = %X'10000'; literal KA0302$M_SLOT0_LBER_CTCE = %X'20000'; literal KA0302$M_SLOT0_LBER_NSES = %X'40000'; literal KA0302$M_SLOT0_LCNR_CEEN = %X'1'; literal KA0302$M_SLOT0_LCNR_RSTSTAT = %X'10000000'; literal KA0302$M_SLOT0_LCNR_NHALT = %X'20000000'; literal KA0302$M_SLOT0_LCNR_NRST = %X'40000000'; literal KA0302$M_SLOT0_LCNR_STF = %X'80000000'; literal KA0302$M_SLOT0_IBR_RCV_SDAT = %X'1'; literal KA0302$M_SLOT0_IBR_XMT_SDAT = %X'2'; literal KA0302$M_SLOT0_IBR_SCLK = %X'4'; literal KA0302$M_SLOT0_LMMR0_EN = %X'1'; literal KA0302$M_SLOT0_LMMR0_INT = %X'6'; literal KA0302$M_SLOT0_LMMR0_IA = %X'18'; literal KA0302$M_SLOT0_LMMR0_AW = %X'1E0'; literal KA0302$M_SLOT0_LMMR0_NBANKS = %X'600'; literal KA0302$M_SLOT0_LMMR0_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT0_LMMR1_EN = %X'1'; literal KA0302$M_SLOT0_LMMR1_INT = %X'6'; literal KA0302$M_SLOT0_LMMR1_IA = %X'18'; literal KA0302$M_SLOT0_LMMR1_AW = %X'1E0'; literal KA0302$M_SLOT0_LMMR1_NBANKS = %X'600'; literal KA0302$M_SLOT0_LMMR1_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT0_LMMR2_EN = %X'1'; literal KA0302$M_SLOT0_LMMR2_INT = %X'6'; literal KA0302$M_SLOT0_LMMR2_IA = %X'18'; literal KA0302$M_SLOT0_LMMR2_AW = %X'1E0'; literal KA0302$M_SLOT0_LMMR2_NBANKS = %X'600'; literal KA0302$M_SLOT0_LMMR2_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT0_LMMR3_EN = %X'1'; literal KA0302$M_SLOT0_LMMR3_INT = %X'6'; literal KA0302$M_SLOT0_LMMR3_IA = %X'18'; literal KA0302$M_SLOT0_LMMR3_AW = %X'1E0'; literal KA0302$M_SLOT0_LMMR3_NBANKS = %X'600'; literal KA0302$M_SLOT0_LMMR3_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT0_LMMR4_EN = %X'1'; literal KA0302$M_SLOT0_LMMR4_INT = %X'6'; literal KA0302$M_SLOT0_LMMR4_IA = %X'18'; literal KA0302$M_SLOT0_LMMR4_AW = %X'1E0'; literal KA0302$M_SLOT0_LMMR4_NBANKS = %X'600'; literal KA0302$M_SLOT0_LMMR4_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT0_LMMR5_EN = %X'1'; literal KA0302$M_SLOT0_LMMR5_INT = %X'6'; literal KA0302$M_SLOT0_LMMR5_IA = %X'18'; literal KA0302$M_SLOT0_LMMR5_AW = %X'1E0'; literal KA0302$M_SLOT0_LMMR5_NBANKS = %X'600'; literal KA0302$M_SLOT0_LMMR5_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT0_LMMR6_EN = %X'1'; literal KA0302$M_SLOT0_LMMR6_INT = %X'6'; literal KA0302$M_SLOT0_LMMR6_IA = %X'18'; literal KA0302$M_SLOT0_LMMR6_AW = %X'1E0'; literal KA0302$M_SLOT0_LMMR6_NBANKS = %X'600'; literal KA0302$M_SLOT0_LMMR6_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT0_LMMR7_EN = %X'1'; literal KA0302$M_SLOT0_LMMR7_INT = %X'6'; literal KA0302$M_SLOT0_LMMR7_IA = %X'18'; literal KA0302$M_SLOT0_LMMR7_AW = %X'1E0'; literal KA0302$M_SLOT0_LMMR7_NBANKS = %X'600'; literal KA0302$M_SLOT0_LMMR7_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT0_LBESR0_SYNDROME = %X'7F'; literal KA0302$M_SLOT0_LBESR1_SYNDROME = %X'7F'; literal KA0302$M_SLOT0_LBESR2_SYNDROME = %X'7F'; literal KA0302$M_SLOT0_LBESR3_SYNDROME = %X'7F'; literal KA0302$M_SLOT0_LBECR1_CA = %X'7F'; literal KA0302$M_SLOT0_LBECR1_CID = %X'780'; literal KA0302$M_SLOT0_LBECR1_RID = %X'7800'; literal KA0302$M_SLOT0_LBECR1_CNF = %X'8000'; literal KA0302$M_SLOT0_LBECR1_SHARED = %X'10000'; literal KA0302$M_SLOT0_LBECR1_DIRTY = %X'20000'; literal KA0302$M_SLOT0_LBECR1_DCYCLE = %X'C0000'; literal KA0302$M_SLOT0_MCR_DTYPE = %X'1'; literal KA0302$M_SLOT0_MCR_STRN = %X'C'; literal KA0302$M_SLOT0_AMR_E = %X'1'; literal KA0302$M_SLOT0_AMR_INTL = %X'6'; literal KA0302$M_SLOT0_AMR_IA = %X'18'; literal KA0302$M_SLOT0_AMR_AW = %X'1E0'; literal KA0302$M_SLOT0_AMR_NBANKS = %X'600'; literal KA0302$M_SLOT0_AMR_MADR = %X'FFFE0000'; literal KA0302$M_SLOT0_MERA_CER = %X'1'; literal KA0302$M_SLOT0_MERA_UCER = %X'2'; literal KA0302$M_SLOT0_MERA_MULE = %X'4'; literal KA0302$M_SLOT0_MERA_APER = %X'8'; literal KA0302$M_SLOT0_MERA_CERA = %X'10'; literal KA0302$M_SLOT0_MERA_CERB = %X'20'; literal KA0302$M_SLOT0_MERA_FSTR = %X'1C0'; literal KA0302$M_SLOT0_MERA_BNKER = %X'200'; literal KA0302$M_SLOT0_MERA_UCERA = %X'400'; literal KA0302$M_SLOT0_MERA_UCERB = %X'800'; literal KA0302$M_SLOT0_MSYNDA_SYND = %X'FF'; literal KA0302$M_SLOT0_MDRA_FCBS = %X'1'; literal KA0302$M_SLOT0_MDRA_DRDC = %X'2'; literal KA0302$M_SLOT0_MDRA_DWDC = %X'4'; literal KA0302$M_SLOT0_MDRA_BPAS = %X'8'; literal KA0302$M_SLOT0_MDRA_EXST = %X'10'; literal KA0302$M_SLOT0_MDRA_STPM = %X'20'; literal KA0302$M_SLOT0_MDRA_MODE = %X'40'; literal KA0302$M_SLOT0_MDRA_IGSB = %X'80'; literal KA0302$M_SLOT0_MDRA_FRPE = %X'100'; literal KA0302$M_SLOT0_MDRA_FCPE = %X'200'; literal KA0302$M_SLOT0_MDRA_DCRD = %X'8000000'; literal KA0302$M_SLOT0_MDRA_RFR = %X'30000000'; literal KA0302$M_SLOT0_MDRA_BRFSH = %X'40000000'; literal KA0302$M_SLOT0_MDRA_DRFSH = %X'80000000'; literal KA0302$M_SLOT0_MCBSA_SCB = %X'FF'; literal KA0302$M_SLOT0_MERB_CER = %X'1'; literal KA0302$M_SLOT0_MERB_UCER = %X'2'; literal KA0302$M_SLOT0_MERB_MULE = %X'4'; literal KA0302$M_SLOT0_MERB_APER = %X'8'; literal KA0302$M_SLOT0_MSYNDB_SYND = %X'FF'; literal KA0302$M_SLOT0_MDRB_FCBS = %X'1'; literal KA0302$M_SLOT0_MDRB_DRDC = %X'2'; literal KA0302$M_SLOT0_MDRB_DWDC = %X'4'; literal KA0302$M_SLOT0_MDRB_BPAS = %X'8'; literal KA0302$M_SLOT0_MDRB_EXST = %X'10'; literal KA0302$M_SLOT0_MDRB_STPM = %X'20'; literal KA0302$M_SLOT0_MDRB_MODE = %X'40'; literal KA0302$M_SLOT0_MDRB_IGSB = %X'80'; literal KA0302$M_SLOT0_MCBSB_SCB = %X'FF'; literal KA0302$K_LSB_SLOT_SIZE = 24576; literal KA0302$M_SLOT1_LDEV_DTYPE = %X'FFFF'; literal KA0302$M_SLOT1_LDEV_DREV = %X'FFFF0000'; literal KA0302$M_SLOT1_LBER_E = %X'1'; literal KA0302$M_SLOT1_LBER_UCE = %X'2'; literal KA0302$M_SLOT1_LBER_UCE2 = %X'4'; literal KA0302$M_SLOT1_LBER_CE = %X'8'; literal KA0302$M_SLOT1_LBER_CE2 = %X'10'; literal KA0302$M_SLOT1_LBER_CPE = %X'20'; literal KA0302$M_SLOT1_LBER_CPE2 = %X'40'; literal KA0302$M_SLOT1_LBER_CDPE = %X'80'; literal KA0302$M_SLOT1_LBER_CDPE2 = %X'100'; literal KA0302$M_SLOT1_LBER_TDE = %X'200'; literal KA0302$M_SLOT1_LBER_STE = %X'400'; literal KA0302$M_SLOT1_LBER_CNFE = %X'800'; literal KA0302$M_SLOT1_LBER_NXAE = %X'1000'; literal KA0302$M_SLOT1_LBER_CAE = %X'2000'; literal KA0302$M_SLOT1_LBER_SHE = %X'4000'; literal KA0302$M_SLOT1_LBER_DIE = %X'8000'; literal KA0302$M_SLOT1_LBER_DTCE = %X'10000'; literal KA0302$M_SLOT1_LBER_CTCE = %X'20000'; literal KA0302$M_SLOT1_LBER_NSES = %X'40000'; literal KA0302$M_SLOT1_LCNR_CEEN = %X'1'; literal KA0302$M_SLOT1_LCNR_RSTSTAT = %X'10000000'; literal KA0302$M_SLOT1_LCNR_NHALT = %X'20000000'; literal KA0302$M_SLOT1_LCNR_NRST = %X'40000000'; literal KA0302$M_SLOT1_LCNR_STF = %X'80000000'; literal KA0302$M_SLOT1_IBR_RCV_SDAT = %X'1'; literal KA0302$M_SLOT1_IBR_XMT_SDAT = %X'2'; literal KA0302$M_SLOT1_IBR_SCLK = %X'4'; literal KA0302$M_SLOT1_LMMR0_EN = %X'1'; literal KA0302$M_SLOT1_LMMR0_INT = %X'6'; literal KA0302$M_SLOT1_LMMR0_IA = %X'18'; literal KA0302$M_SLOT1_LMMR0_AW = %X'1E0'; literal KA0302$M_SLOT1_LMMR0_NBANKS = %X'600'; literal KA0302$M_SLOT1_LMMR0_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT1_LMMR1_EN = %X'1'; literal KA0302$M_SLOT1_LMMR1_INT = %X'6'; literal KA0302$M_SLOT1_LMMR1_IA = %X'18'; literal KA0302$M_SLOT1_LMMR1_AW = %X'1E0'; literal KA0302$M_SLOT1_LMMR1_NBANKS = %X'600'; literal KA0302$M_SLOT1_LMMR1_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT1_LMMR2_EN = %X'1'; literal KA0302$M_SLOT1_LMMR2_INT = %X'6'; literal KA0302$M_SLOT1_LMMR2_IA = %X'18'; literal KA0302$M_SLOT1_LMMR2_AW = %X'1E0'; literal KA0302$M_SLOT1_LMMR2_NBANKS = %X'600'; literal KA0302$M_SLOT1_LMMR2_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT1_LMMR3_EN = %X'1'; literal KA0302$M_SLOT1_LMMR3_INT = %X'6'; literal KA0302$M_SLOT1_LMMR3_IA = %X'18'; literal KA0302$M_SLOT1_LMMR3_AW = %X'1E0'; literal KA0302$M_SLOT1_LMMR3_NBANKS = %X'600'; literal KA0302$M_SLOT1_LMMR3_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT1_LMMR4_EN = %X'1'; literal KA0302$M_SLOT1_LMMR4_INT = %X'6'; literal KA0302$M_SLOT1_LMMR4_IA = %X'18'; literal KA0302$M_SLOT1_LMMR4_AW = %X'1E0'; literal KA0302$M_SLOT1_LMMR4_NBANKS = %X'600'; literal KA0302$M_SLOT1_LMMR4_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT1_LMMR5_EN = %X'1'; literal KA0302$M_SLOT1_LMMR5_INT = %X'6'; literal KA0302$M_SLOT1_LMMR5_IA = %X'18'; literal KA0302$M_SLOT1_LMMR5_AW = %X'1E0'; literal KA0302$M_SLOT1_LMMR5_NBANKS = %X'600'; literal KA0302$M_SLOT1_LMMR5_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT1_LMMR6_EN = %X'1'; literal KA0302$M_SLOT1_LMMR6_INT = %X'6'; literal KA0302$M_SLOT1_LMMR6_IA = %X'18'; literal KA0302$M_SLOT1_LMMR6_AW = %X'1E0'; literal KA0302$M_SLOT1_LMMR6_NBANKS = %X'600'; literal KA0302$M_SLOT1_LMMR6_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT1_LMMR7_EN = %X'1'; literal KA0302$M_SLOT1_LMMR7_INT = %X'6'; literal KA0302$M_SLOT1_LMMR7_IA = %X'18'; literal KA0302$M_SLOT1_LMMR7_AW = %X'1E0'; literal KA0302$M_SLOT1_LMMR7_NBANKS = %X'600'; literal KA0302$M_SLOT1_LMMR7_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT1_LBESR0_SYNDROME = %X'7F'; literal KA0302$M_SLOT1_LBESR1_SYNDROME = %X'7F'; literal KA0302$M_SLOT1_LBESR2_SYNDROME = %X'7F'; literal KA0302$M_SLOT1_LBESR3_SYNDROME = %X'7F'; literal KA0302$M_SLOT1_LBECR1_CA = %X'7F'; literal KA0302$M_SLOT1_LBECR1_CID = %X'780'; literal KA0302$M_SLOT1_LBECR1_RID = %X'7800'; literal KA0302$M_SLOT1_LBECR1_CNF = %X'8000'; literal KA0302$M_SLOT1_LBECR1_SHARED = %X'10000'; literal KA0302$M_SLOT1_LBECR1_DIRTY = %X'20000'; literal KA0302$M_SLOT1_LBECR1_DCYCLE = %X'C0000'; literal KA0302$M_SLOT2_LDEV_DTYPE = %X'FFFF'; literal KA0302$M_SLOT2_LDEV_DREV = %X'FFFF0000'; literal KA0302$M_SLOT2_LBER_E = %X'1'; literal KA0302$M_SLOT2_LBER_UCE = %X'2'; literal KA0302$M_SLOT2_LBER_UCE2 = %X'4'; literal KA0302$M_SLOT2_LBER_CE = %X'8'; literal KA0302$M_SLOT2_LBER_CE2 = %X'10'; literal KA0302$M_SLOT2_LBER_CPE = %X'20'; literal KA0302$M_SLOT2_LBER_CPE2 = %X'40'; literal KA0302$M_SLOT2_LBER_CDPE = %X'80'; literal KA0302$M_SLOT2_LBER_CDPE2 = %X'100'; literal KA0302$M_SLOT2_LBER_TDE = %X'200'; literal KA0302$M_SLOT2_LBER_STE = %X'400'; literal KA0302$M_SLOT2_LBER_CNFE = %X'800'; literal KA0302$M_SLOT2_LBER_NXAE = %X'1000'; literal KA0302$M_SLOT2_LBER_CAE = %X'2000'; literal KA0302$M_SLOT2_LBER_SHE = %X'4000'; literal KA0302$M_SLOT2_LBER_DIE = %X'8000'; literal KA0302$M_SLOT2_LBER_DTCE = %X'10000'; literal KA0302$M_SLOT2_LBER_CTCE = %X'20000'; literal KA0302$M_SLOT2_LBER_NSES = %X'40000'; literal KA0302$M_SLOT2_LCNR_CEEN = %X'1'; literal KA0302$M_SLOT2_LCNR_RSTSTAT = %X'10000000'; literal KA0302$M_SLOT2_LCNR_NHALT = %X'20000000'; literal KA0302$M_SLOT2_LCNR_NRST = %X'40000000'; literal KA0302$M_SLOT2_LCNR_STF = %X'80000000'; literal KA0302$M_SLOT2_IBR_RCV_SDAT = %X'1'; literal KA0302$M_SLOT2_IBR_XMT_SDAT = %X'2'; literal KA0302$M_SLOT2_IBR_SCLK = %X'4'; literal KA0302$M_SLOT2_LMMR0_EN = %X'1'; literal KA0302$M_SLOT2_LMMR0_INT = %X'6'; literal KA0302$M_SLOT2_LMMR0_IA = %X'18'; literal KA0302$M_SLOT2_LMMR0_AW = %X'1E0'; literal KA0302$M_SLOT2_LMMR0_NBANKS = %X'600'; literal KA0302$M_SLOT2_LMMR0_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT2_LMMR1_EN = %X'1'; literal KA0302$M_SLOT2_LMMR1_INT = %X'6'; literal KA0302$M_SLOT2_LMMR1_IA = %X'18'; literal KA0302$M_SLOT2_LMMR1_AW = %X'1E0'; literal KA0302$M_SLOT2_LMMR1_NBANKS = %X'600'; literal KA0302$M_SLOT2_LMMR1_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT2_LMMR2_EN = %X'1'; literal KA0302$M_SLOT2_LMMR2_INT = %X'6'; literal KA0302$M_SLOT2_LMMR2_IA = %X'18'; literal KA0302$M_SLOT2_LMMR2_AW = %X'1E0'; literal KA0302$M_SLOT2_LMMR2_NBANKS = %X'600'; literal KA0302$M_SLOT2_LMMR2_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT2_LMMR3_EN = %X'1'; literal KA0302$M_SLOT2_LMMR3_INT = %X'6'; literal KA0302$M_SLOT2_LMMR3_IA = %X'18'; literal KA0302$M_SLOT2_LMMR3_AW = %X'1E0'; literal KA0302$M_SLOT2_LMMR3_NBANKS = %X'600'; literal KA0302$M_SLOT2_LMMR3_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT2_LMMR4_EN = %X'1'; literal KA0302$M_SLOT2_LMMR4_INT = %X'6'; literal KA0302$M_SLOT2_LMMR4_IA = %X'18'; literal KA0302$M_SLOT2_LMMR4_AW = %X'1E0'; literal KA0302$M_SLOT2_LMMR4_NBANKS = %X'600'; literal KA0302$M_SLOT2_LMMR4_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT2_LMMR5_EN = %X'1'; literal KA0302$M_SLOT2_LMMR5_INT = %X'6'; literal KA0302$M_SLOT2_LMMR5_IA = %X'18'; literal KA0302$M_SLOT2_LMMR5_AW = %X'1E0'; literal KA0302$M_SLOT2_LMMR5_NBANKS = %X'600'; literal KA0302$M_SLOT2_LMMR5_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT2_LMMR6_EN = %X'1'; literal KA0302$M_SLOT2_LMMR6_INT = %X'6'; literal KA0302$M_SLOT2_LMMR6_IA = %X'18'; literal KA0302$M_SLOT2_LMMR6_AW = %X'1E0'; literal KA0302$M_SLOT2_LMMR6_NBANKS = %X'600'; literal KA0302$M_SLOT2_LMMR6_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT2_LMMR7_EN = %X'1'; literal KA0302$M_SLOT2_LMMR7_INT = %X'6'; literal KA0302$M_SLOT2_LMMR7_IA = %X'18'; literal KA0302$M_SLOT2_LMMR7_AW = %X'1E0'; literal KA0302$M_SLOT2_LMMR7_NBANKS = %X'600'; literal KA0302$M_SLOT2_LMMR7_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT2_LBESR0_SYNDROME = %X'7F'; literal KA0302$M_SLOT2_LBESR1_SYNDROME = %X'7F'; literal KA0302$M_SLOT2_LBESR2_SYNDROME = %X'7F'; literal KA0302$M_SLOT2_LBESR3_SYNDROME = %X'7F'; literal KA0302$M_SLOT2_LBECR1_CA = %X'7F'; literal KA0302$M_SLOT2_LBECR1_CID = %X'780'; literal KA0302$M_SLOT2_LBECR1_RID = %X'7800'; literal KA0302$M_SLOT2_LBECR1_CNF = %X'8000'; literal KA0302$M_SLOT2_LBECR1_SHARED = %X'10000'; literal KA0302$M_SLOT2_LBECR1_DIRTY = %X'20000'; literal KA0302$M_SLOT2_LBECR1_DCYCLE = %X'C0000'; literal KA0302$M_SLOT3_LDEV_DTYPE = %X'FFFF'; literal KA0302$M_SLOT3_LDEV_DREV = %X'FFFF0000'; literal KA0302$M_SLOT3_LBER_E = %X'1'; literal KA0302$M_SLOT3_LBER_UCE = %X'2'; literal KA0302$M_SLOT3_LBER_UCE2 = %X'4'; literal KA0302$M_SLOT3_LBER_CE = %X'8'; literal KA0302$M_SLOT3_LBER_CE2 = %X'10'; literal KA0302$M_SLOT3_LBER_CPE = %X'20'; literal KA0302$M_SLOT3_LBER_CPE2 = %X'40'; literal KA0302$M_SLOT3_LBER_CDPE = %X'80'; literal KA0302$M_SLOT3_LBER_CDPE2 = %X'100'; literal KA0302$M_SLOT3_LBER_TDE = %X'200'; literal KA0302$M_SLOT3_LBER_STE = %X'400'; literal KA0302$M_SLOT3_LBER_CNFE = %X'800'; literal KA0302$M_SLOT3_LBER_NXAE = %X'1000'; literal KA0302$M_SLOT3_LBER_CAE = %X'2000'; literal KA0302$M_SLOT3_LBER_SHE = %X'4000'; literal KA0302$M_SLOT3_LBER_DIE = %X'8000'; literal KA0302$M_SLOT3_LBER_DTCE = %X'10000'; literal KA0302$M_SLOT3_LBER_CTCE = %X'20000'; literal KA0302$M_SLOT3_LBER_NSES = %X'40000'; literal KA0302$M_SLOT3_LCNR_CEEN = %X'1'; literal KA0302$M_SLOT3_LCNR_RSTSTAT = %X'10000000'; literal KA0302$M_SLOT3_LCNR_NHALT = %X'20000000'; literal KA0302$M_SLOT3_LCNR_NRST = %X'40000000'; literal KA0302$M_SLOT3_LCNR_STF = %X'80000000'; literal KA0302$M_SLOT3_IBR_RCV_SDAT = %X'1'; literal KA0302$M_SLOT3_IBR_XMT_SDAT = %X'2'; literal KA0302$M_SLOT3_IBR_SCLK = %X'4'; literal KA0302$M_SLOT3_LMMR0_EN = %X'1'; literal KA0302$M_SLOT3_LMMR0_INT = %X'6'; literal KA0302$M_SLOT3_LMMR0_IA = %X'18'; literal KA0302$M_SLOT3_LMMR0_AW = %X'1E0'; literal KA0302$M_SLOT3_LMMR0_NBANKS = %X'600'; literal KA0302$M_SLOT3_LMMR0_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT3_LMMR1_EN = %X'1'; literal KA0302$M_SLOT3_LMMR1_INT = %X'6'; literal KA0302$M_SLOT3_LMMR1_IA = %X'18'; literal KA0302$M_SLOT3_LMMR1_AW = %X'1E0'; literal KA0302$M_SLOT3_LMMR1_NBANKS = %X'600'; literal KA0302$M_SLOT3_LMMR1_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT3_LMMR2_EN = %X'1'; literal KA0302$M_SLOT3_LMMR2_INT = %X'6'; literal KA0302$M_SLOT3_LMMR2_IA = %X'18'; literal KA0302$M_SLOT3_LMMR2_AW = %X'1E0'; literal KA0302$M_SLOT3_LMMR2_NBANKS = %X'600'; literal KA0302$M_SLOT3_LMMR2_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT3_LMMR3_EN = %X'1'; literal KA0302$M_SLOT3_LMMR3_INT = %X'6'; literal KA0302$M_SLOT3_LMMR3_IA = %X'18'; literal KA0302$M_SLOT3_LMMR3_AW = %X'1E0'; literal KA0302$M_SLOT3_LMMR3_NBANKS = %X'600'; literal KA0302$M_SLOT3_LMMR3_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT3_LMMR4_EN = %X'1'; literal KA0302$M_SLOT3_LMMR4_INT = %X'6'; literal KA0302$M_SLOT3_LMMR4_IA = %X'18'; literal KA0302$M_SLOT3_LMMR4_AW = %X'1E0'; literal KA0302$M_SLOT3_LMMR4_NBANKS = %X'600'; literal KA0302$M_SLOT3_LMMR4_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT3_LMMR5_EN = %X'1'; literal KA0302$M_SLOT3_LMMR5_INT = %X'6'; literal KA0302$M_SLOT3_LMMR5_IA = %X'18'; literal KA0302$M_SLOT3_LMMR5_AW = %X'1E0'; literal KA0302$M_SLOT3_LMMR5_NBANKS = %X'600'; literal KA0302$M_SLOT3_LMMR5_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT3_LMMR6_EN = %X'1'; literal KA0302$M_SLOT3_LMMR6_INT = %X'6'; literal KA0302$M_SLOT3_LMMR6_IA = %X'18'; literal KA0302$M_SLOT3_LMMR6_AW = %X'1E0'; literal KA0302$M_SLOT3_LMMR6_NBANKS = %X'600'; literal KA0302$M_SLOT3_LMMR6_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT3_LMMR7_EN = %X'1'; literal KA0302$M_SLOT3_LMMR7_INT = %X'6'; literal KA0302$M_SLOT3_LMMR7_IA = %X'18'; literal KA0302$M_SLOT3_LMMR7_AW = %X'1E0'; literal KA0302$M_SLOT3_LMMR7_NBANKS = %X'600'; literal KA0302$M_SLOT3_LMMR7_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT3_LBESR0_SYNDROME = %X'7F'; literal KA0302$M_SLOT3_LBESR1_SYNDROME = %X'7F'; literal KA0302$M_SLOT3_LBESR2_SYNDROME = %X'7F'; literal KA0302$M_SLOT3_LBESR3_SYNDROME = %X'7F'; literal KA0302$M_SLOT3_LBECR1_CA = %X'7F'; literal KA0302$M_SLOT3_LBECR1_CID = %X'780'; literal KA0302$M_SLOT3_LBECR1_RID = %X'7800'; literal KA0302$M_SLOT3_LBECR1_CNF = %X'8000'; literal KA0302$M_SLOT3_LBECR1_SHARED = %X'10000'; literal KA0302$M_SLOT3_LBECR1_DIRTY = %X'20000'; literal KA0302$M_SLOT3_LBECR1_DCYCLE = %X'C0000'; literal KA0302$M_SLOT4_LDEV_DTYPE = %X'FFFF'; literal KA0302$M_SLOT4_LDEV_DREV = %X'FFFF0000'; literal KA0302$M_SLOT4_LBER_E = %X'1'; literal KA0302$M_SLOT4_LBER_UCE = %X'2'; literal KA0302$M_SLOT4_LBER_UCE2 = %X'4'; literal KA0302$M_SLOT4_LBER_CE = %X'8'; literal KA0302$M_SLOT4_LBER_CE2 = %X'10'; literal KA0302$M_SLOT4_LBER_CPE = %X'20'; literal KA0302$M_SLOT4_LBER_CPE2 = %X'40'; literal KA0302$M_SLOT4_LBER_CDPE = %X'80'; literal KA0302$M_SLOT4_LBER_CDPE2 = %X'100'; literal KA0302$M_SLOT4_LBER_TDE = %X'200'; literal KA0302$M_SLOT4_LBER_STE = %X'400'; literal KA0302$M_SLOT4_LBER_CNFE = %X'800'; literal KA0302$M_SLOT4_LBER_NXAE = %X'1000'; literal KA0302$M_SLOT4_LBER_CAE = %X'2000'; literal KA0302$M_SLOT4_LBER_SHE = %X'4000'; literal KA0302$M_SLOT4_LBER_DIE = %X'8000'; literal KA0302$M_SLOT4_LBER_DTCE = %X'10000'; literal KA0302$M_SLOT4_LBER_CTCE = %X'20000'; literal KA0302$M_SLOT4_LBER_NSES = %X'40000'; literal KA0302$M_SLOT4_LCNR_CEEN = %X'1'; literal KA0302$M_SLOT4_LCNR_RSTSTAT = %X'10000000'; literal KA0302$M_SLOT4_LCNR_NHALT = %X'20000000'; literal KA0302$M_SLOT4_LCNR_NRST = %X'40000000'; literal KA0302$M_SLOT4_LCNR_STF = %X'80000000'; literal KA0302$M_SLOT4_IBR_RCV_SDAT = %X'1'; literal KA0302$M_SLOT4_IBR_XMT_SDAT = %X'2'; literal KA0302$M_SLOT4_IBR_SCLK = %X'4'; literal KA0302$M_SLOT4_LMMR0_EN = %X'1'; literal KA0302$M_SLOT4_LMMR0_INT = %X'6'; literal KA0302$M_SLOT4_LMMR0_IA = %X'18'; literal KA0302$M_SLOT4_LMMR0_AW = %X'1E0'; literal KA0302$M_SLOT4_LMMR0_NBANKS = %X'600'; literal KA0302$M_SLOT4_LMMR0_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT4_LMMR1_EN = %X'1'; literal KA0302$M_SLOT4_LMMR1_INT = %X'6'; literal KA0302$M_SLOT4_LMMR1_IA = %X'18'; literal KA0302$M_SLOT4_LMMR1_AW = %X'1E0'; literal KA0302$M_SLOT4_LMMR1_NBANKS = %X'600'; literal KA0302$M_SLOT4_LMMR1_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT4_LMMR2_EN = %X'1'; literal KA0302$M_SLOT4_LMMR2_INT = %X'6'; literal KA0302$M_SLOT4_LMMR2_IA = %X'18'; literal KA0302$M_SLOT4_LMMR2_AW = %X'1E0'; literal KA0302$M_SLOT4_LMMR2_NBANKS = %X'600'; literal KA0302$M_SLOT4_LMMR2_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT4_LMMR3_EN = %X'1'; literal KA0302$M_SLOT4_LMMR3_INT = %X'6'; literal KA0302$M_SLOT4_LMMR3_IA = %X'18'; literal KA0302$M_SLOT4_LMMR3_AW = %X'1E0'; literal KA0302$M_SLOT4_LMMR3_NBANKS = %X'600'; literal KA0302$M_SLOT4_LMMR3_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT4_LMMR4_EN = %X'1'; literal KA0302$M_SLOT4_LMMR4_INT = %X'6'; literal KA0302$M_SLOT4_LMMR4_IA = %X'18'; literal KA0302$M_SLOT4_LMMR4_AW = %X'1E0'; literal KA0302$M_SLOT4_LMMR4_NBANKS = %X'600'; literal KA0302$M_SLOT4_LMMR4_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT4_LMMR5_EN = %X'1'; literal KA0302$M_SLOT4_LMMR5_INT = %X'6'; literal KA0302$M_SLOT4_LMMR5_IA = %X'18'; literal KA0302$M_SLOT4_LMMR5_AW = %X'1E0'; literal KA0302$M_SLOT4_LMMR5_NBANKS = %X'600'; literal KA0302$M_SLOT4_LMMR5_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT4_LMMR6_EN = %X'1'; literal KA0302$M_SLOT4_LMMR6_INT = %X'6'; literal KA0302$M_SLOT4_LMMR6_IA = %X'18'; literal KA0302$M_SLOT4_LMMR6_AW = %X'1E0'; literal KA0302$M_SLOT4_LMMR6_NBANKS = %X'600'; literal KA0302$M_SLOT4_LMMR6_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT4_LMMR7_EN = %X'1'; literal KA0302$M_SLOT4_LMMR7_INT = %X'6'; literal KA0302$M_SLOT4_LMMR7_IA = %X'18'; literal KA0302$M_SLOT4_LMMR7_AW = %X'1E0'; literal KA0302$M_SLOT4_LMMR7_NBANKS = %X'600'; literal KA0302$M_SLOT4_LMMR7_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT4_LBESR0_SYNDROME = %X'7F'; literal KA0302$M_SLOT4_LBESR1_SYNDROME = %X'7F'; literal KA0302$M_SLOT4_LBESR2_SYNDROME = %X'7F'; literal KA0302$M_SLOT4_LBESR3_SYNDROME = %X'7F'; literal KA0302$M_SLOT4_LBECR1_CA = %X'7F'; literal KA0302$M_SLOT4_LBECR1_CID = %X'780'; literal KA0302$M_SLOT4_LBECR1_RID = %X'7800'; literal KA0302$M_SLOT4_LBECR1_CNF = %X'8000'; literal KA0302$M_SLOT4_LBECR1_SHARED = %X'10000'; literal KA0302$M_SLOT4_LBECR1_DIRTY = %X'20000'; literal KA0302$M_SLOT4_LBECR1_DCYCLE = %X'C0000'; literal KA0302$M_SLOT5_LDEV_DTYPE = %X'FFFF'; literal KA0302$M_SLOT5_LDEV_DREV = %X'FFFF0000'; literal KA0302$M_SLOT5_LBER_E = %X'1'; literal KA0302$M_SLOT5_LBER_UCE = %X'2'; literal KA0302$M_SLOT5_LBER_UCE2 = %X'4'; literal KA0302$M_SLOT5_LBER_CE = %X'8'; literal KA0302$M_SLOT5_LBER_CE2 = %X'10'; literal KA0302$M_SLOT5_LBER_CPE = %X'20'; literal KA0302$M_SLOT5_LBER_CPE2 = %X'40'; literal KA0302$M_SLOT5_LBER_CDPE = %X'80'; literal KA0302$M_SLOT5_LBER_CDPE2 = %X'100'; literal KA0302$M_SLOT5_LBER_TDE = %X'200'; literal KA0302$M_SLOT5_LBER_STE = %X'400'; literal KA0302$M_SLOT5_LBER_CNFE = %X'800'; literal KA0302$M_SLOT5_LBER_NXAE = %X'1000'; literal KA0302$M_SLOT5_LBER_CAE = %X'2000'; literal KA0302$M_SLOT5_LBER_SHE = %X'4000'; literal KA0302$M_SLOT5_LBER_DIE = %X'8000'; literal KA0302$M_SLOT5_LBER_DTCE = %X'10000'; literal KA0302$M_SLOT5_LBER_CTCE = %X'20000'; literal KA0302$M_SLOT5_LBER_NSES = %X'40000'; literal KA0302$M_SLOT5_LCNR_CEEN = %X'1'; literal KA0302$M_SLOT5_LCNR_RSTSTAT = %X'10000000'; literal KA0302$M_SLOT5_LCNR_NHALT = %X'20000000'; literal KA0302$M_SLOT5_LCNR_NRST = %X'40000000'; literal KA0302$M_SLOT5_LCNR_STF = %X'80000000'; literal KA0302$M_SLOT5_IBR_RCV_SDAT = %X'1'; literal KA0302$M_SLOT5_IBR_XMT_SDAT = %X'2'; literal KA0302$M_SLOT5_IBR_SCLK = %X'4'; literal KA0302$M_SLOT5_LMMR0_EN = %X'1'; literal KA0302$M_SLOT5_LMMR0_INT = %X'6'; literal KA0302$M_SLOT5_LMMR0_IA = %X'18'; literal KA0302$M_SLOT5_LMMR0_AW = %X'1E0'; literal KA0302$M_SLOT5_LMMR0_NBANKS = %X'600'; literal KA0302$M_SLOT5_LMMR0_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT5_LMMR1_EN = %X'1'; literal KA0302$M_SLOT5_LMMR1_INT = %X'6'; literal KA0302$M_SLOT5_LMMR1_IA = %X'18'; literal KA0302$M_SLOT5_LMMR1_AW = %X'1E0'; literal KA0302$M_SLOT5_LMMR1_NBANKS = %X'600'; literal KA0302$M_SLOT5_LMMR1_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT5_LMMR2_EN = %X'1'; literal KA0302$M_SLOT5_LMMR2_INT = %X'6'; literal KA0302$M_SLOT5_LMMR2_IA = %X'18'; literal KA0302$M_SLOT5_LMMR2_AW = %X'1E0'; literal KA0302$M_SLOT5_LMMR2_NBANKS = %X'600'; literal KA0302$M_SLOT5_LMMR2_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT5_LMMR3_EN = %X'1'; literal KA0302$M_SLOT5_LMMR3_INT = %X'6'; literal KA0302$M_SLOT5_LMMR3_IA = %X'18'; literal KA0302$M_SLOT5_LMMR3_AW = %X'1E0'; literal KA0302$M_SLOT5_LMMR3_NBANKS = %X'600'; literal KA0302$M_SLOT5_LMMR3_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT5_LMMR4_EN = %X'1'; literal KA0302$M_SLOT5_LMMR4_INT = %X'6'; literal KA0302$M_SLOT5_LMMR4_IA = %X'18'; literal KA0302$M_SLOT5_LMMR4_AW = %X'1E0'; literal KA0302$M_SLOT5_LMMR4_NBANKS = %X'600'; literal KA0302$M_SLOT5_LMMR4_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT5_LMMR5_EN = %X'1'; literal KA0302$M_SLOT5_LMMR5_INT = %X'6'; literal KA0302$M_SLOT5_LMMR5_IA = %X'18'; literal KA0302$M_SLOT5_LMMR5_AW = %X'1E0'; literal KA0302$M_SLOT5_LMMR5_NBANKS = %X'600'; literal KA0302$M_SLOT5_LMMR5_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT5_LMMR6_EN = %X'1'; literal KA0302$M_SLOT5_LMMR6_INT = %X'6'; literal KA0302$M_SLOT5_LMMR6_IA = %X'18'; literal KA0302$M_SLOT5_LMMR6_AW = %X'1E0'; literal KA0302$M_SLOT5_LMMR6_NBANKS = %X'600'; literal KA0302$M_SLOT5_LMMR6_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT5_LMMR7_EN = %X'1'; literal KA0302$M_SLOT5_LMMR7_INT = %X'6'; literal KA0302$M_SLOT5_LMMR7_IA = %X'18'; literal KA0302$M_SLOT5_LMMR7_AW = %X'1E0'; literal KA0302$M_SLOT5_LMMR7_NBANKS = %X'600'; literal KA0302$M_SLOT5_LMMR7_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT5_LBESR0_SYNDROME = %X'7F'; literal KA0302$M_SLOT5_LBESR1_SYNDROME = %X'7F'; literal KA0302$M_SLOT5_LBESR2_SYNDROME = %X'7F'; literal KA0302$M_SLOT5_LBESR3_SYNDROME = %X'7F'; literal KA0302$M_SLOT5_LBECR1_CA = %X'7F'; literal KA0302$M_SLOT5_LBECR1_CID = %X'780'; literal KA0302$M_SLOT5_LBECR1_RID = %X'7800'; literal KA0302$M_SLOT5_LBECR1_CNF = %X'8000'; literal KA0302$M_SLOT5_LBECR1_SHARED = %X'10000'; literal KA0302$M_SLOT5_LBECR1_DIRTY = %X'20000'; literal KA0302$M_SLOT5_LBECR1_DCYCLE = %X'C0000'; literal KA0302$M_SLOT6_LDEV_DTYPE = %X'FFFF'; literal KA0302$M_SLOT6_LDEV_DREV = %X'FFFF0000'; literal KA0302$M_SLOT6_LBER_E = %X'1'; literal KA0302$M_SLOT6_LBER_UCE = %X'2'; literal KA0302$M_SLOT6_LBER_UCE2 = %X'4'; literal KA0302$M_SLOT6_LBER_CE = %X'8'; literal KA0302$M_SLOT6_LBER_CE2 = %X'10'; literal KA0302$M_SLOT6_LBER_CPE = %X'20'; literal KA0302$M_SLOT6_LBER_CPE2 = %X'40'; literal KA0302$M_SLOT6_LBER_CDPE = %X'80'; literal KA0302$M_SLOT6_LBER_CDPE2 = %X'100'; literal KA0302$M_SLOT6_LBER_TDE = %X'200'; literal KA0302$M_SLOT6_LBER_STE = %X'400'; literal KA0302$M_SLOT6_LBER_CNFE = %X'800'; literal KA0302$M_SLOT6_LBER_NXAE = %X'1000'; literal KA0302$M_SLOT6_LBER_CAE = %X'2000'; literal KA0302$M_SLOT6_LBER_SHE = %X'4000'; literal KA0302$M_SLOT6_LBER_DIE = %X'8000'; literal KA0302$M_SLOT6_LBER_DTCE = %X'10000'; literal KA0302$M_SLOT6_LBER_CTCE = %X'20000'; literal KA0302$M_SLOT6_LBER_NSES = %X'40000'; literal KA0302$M_SLOT6_LCNR_CEEN = %X'1'; literal KA0302$M_SLOT6_LCNR_RSTSTAT = %X'10000000'; literal KA0302$M_SLOT6_LCNR_NHALT = %X'20000000'; literal KA0302$M_SLOT6_LCNR_NRST = %X'40000000'; literal KA0302$M_SLOT6_LCNR_STF = %X'80000000'; literal KA0302$M_SLOT6_IBR_RCV_SDAT = %X'1'; literal KA0302$M_SLOT6_IBR_XMT_SDAT = %X'2'; literal KA0302$M_SLOT6_IBR_SCLK = %X'4'; literal KA0302$M_SLOT6_LMMR0_EN = %X'1'; literal KA0302$M_SLOT6_LMMR0_INT = %X'6'; literal KA0302$M_SLOT6_LMMR0_IA = %X'18'; literal KA0302$M_SLOT6_LMMR0_AW = %X'1E0'; literal KA0302$M_SLOT6_LMMR0_NBANKS = %X'600'; literal KA0302$M_SLOT6_LMMR0_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT6_LMMR1_EN = %X'1'; literal KA0302$M_SLOT6_LMMR1_INT = %X'6'; literal KA0302$M_SLOT6_LMMR1_IA = %X'18'; literal KA0302$M_SLOT6_LMMR1_AW = %X'1E0'; literal KA0302$M_SLOT6_LMMR1_NBANKS = %X'600'; literal KA0302$M_SLOT6_LMMR1_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT6_LMMR2_EN = %X'1'; literal KA0302$M_SLOT6_LMMR2_INT = %X'6'; literal KA0302$M_SLOT6_LMMR2_IA = %X'18'; literal KA0302$M_SLOT6_LMMR2_AW = %X'1E0'; literal KA0302$M_SLOT6_LMMR2_NBANKS = %X'600'; literal KA0302$M_SLOT6_LMMR2_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT6_LMMR3_EN = %X'1'; literal KA0302$M_SLOT6_LMMR3_INT = %X'6'; literal KA0302$M_SLOT6_LMMR3_IA = %X'18'; literal KA0302$M_SLOT6_LMMR3_AW = %X'1E0'; literal KA0302$M_SLOT6_LMMR3_NBANKS = %X'600'; literal KA0302$M_SLOT6_LMMR3_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT6_LMMR4_EN = %X'1'; literal KA0302$M_SLOT6_LMMR4_INT = %X'6'; literal KA0302$M_SLOT6_LMMR4_IA = %X'18'; literal KA0302$M_SLOT6_LMMR4_AW = %X'1E0'; literal KA0302$M_SLOT6_LMMR4_NBANKS = %X'600'; literal KA0302$M_SLOT6_LMMR4_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT6_LMMR5_EN = %X'1'; literal KA0302$M_SLOT6_LMMR5_INT = %X'6'; literal KA0302$M_SLOT6_LMMR5_IA = %X'18'; literal KA0302$M_SLOT6_LMMR5_AW = %X'1E0'; literal KA0302$M_SLOT6_LMMR5_NBANKS = %X'600'; literal KA0302$M_SLOT6_LMMR5_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT6_LMMR6_EN = %X'1'; literal KA0302$M_SLOT6_LMMR6_INT = %X'6'; literal KA0302$M_SLOT6_LMMR6_IA = %X'18'; literal KA0302$M_SLOT6_LMMR6_AW = %X'1E0'; literal KA0302$M_SLOT6_LMMR6_NBANKS = %X'600'; literal KA0302$M_SLOT6_LMMR6_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT6_LMMR7_EN = %X'1'; literal KA0302$M_SLOT6_LMMR7_INT = %X'6'; literal KA0302$M_SLOT6_LMMR7_IA = %X'18'; literal KA0302$M_SLOT6_LMMR7_AW = %X'1E0'; literal KA0302$M_SLOT6_LMMR7_NBANKS = %X'600'; literal KA0302$M_SLOT6_LMMR7_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT6_LBESR0_SYNDROME = %X'7F'; literal KA0302$M_SLOT6_LBESR1_SYNDROME = %X'7F'; literal KA0302$M_SLOT6_LBESR2_SYNDROME = %X'7F'; literal KA0302$M_SLOT6_LBESR3_SYNDROME = %X'7F'; literal KA0302$M_SLOT6_LBECR1_CA = %X'7F'; literal KA0302$M_SLOT6_LBECR1_CID = %X'780'; literal KA0302$M_SLOT6_LBECR1_RID = %X'7800'; literal KA0302$M_SLOT6_LBECR1_CNF = %X'8000'; literal KA0302$M_SLOT6_LBECR1_SHARED = %X'10000'; literal KA0302$M_SLOT6_LBECR1_DIRTY = %X'20000'; literal KA0302$M_SLOT6_LBECR1_DCYCLE = %X'C0000'; literal KA0302$M_SLOT7_LDEV_DTYPE = %X'FFFF'; literal KA0302$M_SLOT7_LDEV_DREV = %X'FFFF0000'; literal KA0302$M_SLOT7_LBER_E = %X'1'; literal KA0302$M_SLOT7_LBER_UCE = %X'2'; literal KA0302$M_SLOT7_LBER_UCE2 = %X'4'; literal KA0302$M_SLOT7_LBER_CE = %X'8'; literal KA0302$M_SLOT7_LBER_CE2 = %X'10'; literal KA0302$M_SLOT7_LBER_CPE = %X'20'; literal KA0302$M_SLOT7_LBER_CPE2 = %X'40'; literal KA0302$M_SLOT7_LBER_CDPE = %X'80'; literal KA0302$M_SLOT7_LBER_CDPE2 = %X'100'; literal KA0302$M_SLOT7_LBER_TDE = %X'200'; literal KA0302$M_SLOT7_LBER_STE = %X'400'; literal KA0302$M_SLOT7_LBER_CNFE = %X'800'; literal KA0302$M_SLOT7_LBER_NXAE = %X'1000'; literal KA0302$M_SLOT7_LBER_CAE = %X'2000'; literal KA0302$M_SLOT7_LBER_SHE = %X'4000'; literal KA0302$M_SLOT7_LBER_DIE = %X'8000'; literal KA0302$M_SLOT7_LBER_DTCE = %X'10000'; literal KA0302$M_SLOT7_LBER_CTCE = %X'20000'; literal KA0302$M_SLOT7_LBER_NSES = %X'40000'; literal KA0302$M_SLOT7_LCNR_CEEN = %X'1'; literal KA0302$M_SLOT7_LCNR_RSTSTAT = %X'10000000'; literal KA0302$M_SLOT7_LCNR_NHALT = %X'20000000'; literal KA0302$M_SLOT7_LCNR_NRST = %X'40000000'; literal KA0302$M_SLOT7_LCNR_STF = %X'80000000'; literal KA0302$M_SLOT7_IBR_RCV_SDAT = %X'1'; literal KA0302$M_SLOT7_IBR_XMT_SDAT = %X'2'; literal KA0302$M_SLOT7_IBR_SCLK = %X'4'; literal KA0302$M_SLOT7_LMMR0_EN = %X'1'; literal KA0302$M_SLOT7_LMMR0_INT = %X'6'; literal KA0302$M_SLOT7_LMMR0_IA = %X'18'; literal KA0302$M_SLOT7_LMMR0_AW = %X'1E0'; literal KA0302$M_SLOT7_LMMR0_NBANKS = %X'600'; literal KA0302$M_SLOT7_LMMR0_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT7_LMMR1_EN = %X'1'; literal KA0302$M_SLOT7_LMMR1_INT = %X'6'; literal KA0302$M_SLOT7_LMMR1_IA = %X'18'; literal KA0302$M_SLOT7_LMMR1_AW = %X'1E0'; literal KA0302$M_SLOT7_LMMR1_NBANKS = %X'600'; literal KA0302$M_SLOT7_LMMR1_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT7_LMMR2_EN = %X'1'; literal KA0302$M_SLOT7_LMMR2_INT = %X'6'; literal KA0302$M_SLOT7_LMMR2_IA = %X'18'; literal KA0302$M_SLOT7_LMMR2_AW = %X'1E0'; literal KA0302$M_SLOT7_LMMR2_NBANKS = %X'600'; literal KA0302$M_SLOT7_LMMR2_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT7_LMMR3_EN = %X'1'; literal KA0302$M_SLOT7_LMMR3_INT = %X'6'; literal KA0302$M_SLOT7_LMMR3_IA = %X'18'; literal KA0302$M_SLOT7_LMMR3_AW = %X'1E0'; literal KA0302$M_SLOT7_LMMR3_NBANKS = %X'600'; literal KA0302$M_SLOT7_LMMR3_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT7_LMMR4_EN = %X'1'; literal KA0302$M_SLOT7_LMMR4_INT = %X'6'; literal KA0302$M_SLOT7_LMMR4_IA = %X'18'; literal KA0302$M_SLOT7_LMMR4_AW = %X'1E0'; literal KA0302$M_SLOT7_LMMR4_NBANKS = %X'600'; literal KA0302$M_SLOT7_LMMR4_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT7_LMMR5_EN = %X'1'; literal KA0302$M_SLOT7_LMMR5_INT = %X'6'; literal KA0302$M_SLOT7_LMMR5_IA = %X'18'; literal KA0302$M_SLOT7_LMMR5_AW = %X'1E0'; literal KA0302$M_SLOT7_LMMR5_NBANKS = %X'600'; literal KA0302$M_SLOT7_LMMR5_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT7_LMMR6_EN = %X'1'; literal KA0302$M_SLOT7_LMMR6_INT = %X'6'; literal KA0302$M_SLOT7_LMMR6_IA = %X'18'; literal KA0302$M_SLOT7_LMMR6_AW = %X'1E0'; literal KA0302$M_SLOT7_LMMR6_NBANKS = %X'600'; literal KA0302$M_SLOT7_LMMR6_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT7_LMMR7_EN = %X'1'; literal KA0302$M_SLOT7_LMMR7_INT = %X'6'; literal KA0302$M_SLOT7_LMMR7_IA = %X'18'; literal KA0302$M_SLOT7_LMMR7_AW = %X'1E0'; literal KA0302$M_SLOT7_LMMR7_NBANKS = %X'600'; literal KA0302$M_SLOT7_LMMR7_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT7_LBESR0_SYNDROME = %X'7F'; literal KA0302$M_SLOT7_LBESR1_SYNDROME = %X'7F'; literal KA0302$M_SLOT7_LBESR2_SYNDROME = %X'7F'; literal KA0302$M_SLOT7_LBESR3_SYNDROME = %X'7F'; literal KA0302$M_SLOT7_LBECR1_CA = %X'7F'; literal KA0302$M_SLOT7_LBECR1_CID = %X'780'; literal KA0302$M_SLOT7_LBECR1_RID = %X'7800'; literal KA0302$M_SLOT7_LBECR1_CNF = %X'8000'; literal KA0302$M_SLOT7_LBECR1_SHARED = %X'10000'; literal KA0302$M_SLOT7_LBECR1_DIRTY = %X'20000'; literal KA0302$M_SLOT7_LBECR1_DCYCLE = %X'C0000'; literal KA0302$M_SLOT8_LDEV_DTYPE = %X'FFFF'; literal KA0302$M_SLOT8_LDEV_DREV = %X'FFFF0000'; literal KA0302$M_SLOT8_LBER_E = %X'1'; literal KA0302$M_SLOT8_LBER_UCE = %X'2'; literal KA0302$M_SLOT8_LBER_UCE2 = %X'4'; literal KA0302$M_SLOT8_LBER_CE = %X'8'; literal KA0302$M_SLOT8_LBER_CE2 = %X'10'; literal KA0302$M_SLOT8_LBER_CPE = %X'20'; literal KA0302$M_SLOT8_LBER_CPE2 = %X'40'; literal KA0302$M_SLOT8_LBER_CDPE = %X'80'; literal KA0302$M_SLOT8_LBER_CDPE2 = %X'100'; literal KA0302$M_SLOT8_LBER_TDE = %X'200'; literal KA0302$M_SLOT8_LBER_STE = %X'400'; literal KA0302$M_SLOT8_LBER_CNFE = %X'800'; literal KA0302$M_SLOT8_LBER_NXAE = %X'1000'; literal KA0302$M_SLOT8_LBER_CAE = %X'2000'; literal KA0302$M_SLOT8_LBER_SHE = %X'4000'; literal KA0302$M_SLOT8_LBER_DIE = %X'8000'; literal KA0302$M_SLOT8_LBER_DTCE = %X'10000'; literal KA0302$M_SLOT8_LBER_CTCE = %X'20000'; literal KA0302$M_SLOT8_LBER_NSES = %X'40000'; literal KA0302$M_SLOT8_LCNR_CEEN = %X'1'; literal KA0302$M_SLOT8_LCNR_RSTSTAT = %X'10000000'; literal KA0302$M_SLOT8_LCNR_NHALT = %X'20000000'; literal KA0302$M_SLOT8_LCNR_NRST = %X'40000000'; literal KA0302$M_SLOT8_LCNR_STF = %X'80000000'; literal KA0302$M_SLOT8_IBR_RCV_SDAT = %X'1'; literal KA0302$M_SLOT8_IBR_XMT_SDAT = %X'2'; literal KA0302$M_SLOT8_IBR_SCLK = %X'4'; literal KA0302$M_SLOT8_LMMR0_EN = %X'1'; literal KA0302$M_SLOT8_LMMR0_INT = %X'6'; literal KA0302$M_SLOT8_LMMR0_IA = %X'18'; literal KA0302$M_SLOT8_LMMR0_AW = %X'1E0'; literal KA0302$M_SLOT8_LMMR0_NBANKS = %X'600'; literal KA0302$M_SLOT8_LMMR0_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT8_LMMR1_EN = %X'1'; literal KA0302$M_SLOT8_LMMR1_INT = %X'6'; literal KA0302$M_SLOT8_LMMR1_IA = %X'18'; literal KA0302$M_SLOT8_LMMR1_AW = %X'1E0'; literal KA0302$M_SLOT8_LMMR1_NBANKS = %X'600'; literal KA0302$M_SLOT8_LMMR1_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT8_LMMR2_EN = %X'1'; literal KA0302$M_SLOT8_LMMR2_INT = %X'6'; literal KA0302$M_SLOT8_LMMR2_IA = %X'18'; literal KA0302$M_SLOT8_LMMR2_AW = %X'1E0'; literal KA0302$M_SLOT8_LMMR2_NBANKS = %X'600'; literal KA0302$M_SLOT8_LMMR2_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT8_LMMR3_EN = %X'1'; literal KA0302$M_SLOT8_LMMR3_INT = %X'6'; literal KA0302$M_SLOT8_LMMR3_IA = %X'18'; literal KA0302$M_SLOT8_LMMR3_AW = %X'1E0'; literal KA0302$M_SLOT8_LMMR3_NBANKS = %X'600'; literal KA0302$M_SLOT8_LMMR3_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT8_LMMR4_EN = %X'1'; literal KA0302$M_SLOT8_LMMR4_INT = %X'6'; literal KA0302$M_SLOT8_LMMR4_IA = %X'18'; literal KA0302$M_SLOT8_LMMR4_AW = %X'1E0'; literal KA0302$M_SLOT8_LMMR4_NBANKS = %X'600'; literal KA0302$M_SLOT8_LMMR4_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT8_LMMR5_EN = %X'1'; literal KA0302$M_SLOT8_LMMR5_INT = %X'6'; literal KA0302$M_SLOT8_LMMR5_IA = %X'18'; literal KA0302$M_SLOT8_LMMR5_AW = %X'1E0'; literal KA0302$M_SLOT8_LMMR5_NBANKS = %X'600'; literal KA0302$M_SLOT8_LMMR5_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT8_LMMR6_EN = %X'1'; literal KA0302$M_SLOT8_LMMR6_INT = %X'6'; literal KA0302$M_SLOT8_LMMR6_IA = %X'18'; literal KA0302$M_SLOT8_LMMR6_AW = %X'1E0'; literal KA0302$M_SLOT8_LMMR6_NBANKS = %X'600'; literal KA0302$M_SLOT8_LMMR6_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT8_LMMR7_EN = %X'1'; literal KA0302$M_SLOT8_LMMR7_INT = %X'6'; literal KA0302$M_SLOT8_LMMR7_IA = %X'18'; literal KA0302$M_SLOT8_LMMR7_AW = %X'1E0'; literal KA0302$M_SLOT8_LMMR7_NBANKS = %X'600'; literal KA0302$M_SLOT8_LMMR7_ADDR = %X'FFFE0000'; literal KA0302$M_SLOT8_LBESR0_SYNDROME = %X'7F'; literal KA0302$M_SLOT8_LBESR1_SYNDROME = %X'7F'; literal KA0302$M_SLOT8_LBESR2_SYNDROME = %X'7F'; literal KA0302$M_SLOT8_LBESR3_SYNDROME = %X'7F'; literal KA0302$M_SLOT8_LBECR1_CA = %X'7F'; literal KA0302$M_SLOT8_LBECR1_CID = %X'780'; literal KA0302$M_SLOT8_LBECR1_RID = %X'7800'; literal KA0302$M_SLOT8_LBECR1_CNF = %X'8000'; literal KA0302$M_SLOT8_LBECR1_SHARED = %X'10000'; literal KA0302$M_SLOT8_LBECR1_DIRTY = %X'20000'; literal KA0302$M_SLOT8_LBECR1_DCYCLE = %X'C0000'; literal KA0302$M_LILID0_IDENT = %X'FFFF'; literal KA0302$M_LILID1_IDENT = %X'FFFF'; literal KA0302$M_LILID2_IDENT = %X'FFFF'; literal KA0302$M_LILID3_IDENT = %X'FFFF'; literal KA0302$M_LCPUMASK_CPU0 = %X'F'; literal KA0302$M_LCPUMASK_CPU1 = %X'F0'; literal KA0302$M_LCPUMASK_CPU2 = %X'F00'; literal KA0302$M_LCPUMASK_CPU3 = %X'F000'; literal KA0302$M_IPCNSE_MBX_HOSE0_TIP = %X'1'; literal KA0302$M_IPCNSE_MBX_HOSE1_TIP = %X'2'; literal KA0302$M_IPCNSE_MBX_HOSE2_TIP = %X'4'; literal KA0302$M_IPCNSE_MBX_HOSE3_TIP = %X'8'; literal KA0302$M_IPCNSE_UPHOSE0_OFLO = %X'10'; literal KA0302$M_IPCNSE_UPHOSE1_OFLO = %X'20'; literal KA0302$M_IPCNSE_UPHOSE2_OFLO = %X'40'; literal KA0302$M_IPCNSE_UPHOSE3_OFLO = %X'80'; literal KA0302$M_IPCNSE_UPHOSE0_PKT_ERR = %X'100'; literal KA0302$M_IPCNSE_UPHOSE1_PKT_ERR = %X'200'; literal KA0302$M_IPCNSE_UPHOSE2_PKT_ERR = %X'400'; literal KA0302$M_IPCNSE_UPHOSE3_PKT_ERR = %X'800'; literal KA0302$M_IPCNSE_UPHOSE0_PAR_ERR = %X'1000'; literal KA0302$M_IPCNSE_UPHOSE1_PAR_ERR = %X'2000'; literal KA0302$M_IPCNSE_UPHOSE2_PAR_ERR = %X'4000'; literal KA0302$M_IPCNSE_UPHOSE3_PAR_ERR = %X'8000'; literal KA0302$M_IPCNSE_UP_HIC_IE = %X'10000'; literal KA0302$M_IPCNSE_IPC_INT_ERR = %X'20000'; literal KA0302$M_IPCNSE_UP_VRTX_ERR = %X'40000'; literal KA0302$M_IPCNSE_DN_VRTX_ERR = %X'80000'; literal KA0302$M_IPCNSE_MULT_INTR_ERR = %X'100000'; literal KA0302$M_IPCNSE_INTR_NSES = %X'80000000'; literal KA0302$M_IPCVR_VECTOR = %X'FFFF'; literal KA0302$M_IPCMSR_ARB_HIGH = %X'1'; literal KA0302$M_IPCMSR_ARB_CTL = %X'6'; literal KA0302$M_IPCHST_H0_ERROR = %X'1'; literal KA0302$M_IPCHST_H0_PWROK = %X'2'; literal KA0302$M_IPCHST_H0_CBLOK = %X'4'; literal KA0302$M_IPCHST_H0_PWROK_TRANS = %X'8'; literal KA0302$M_IPCHST_H1_ERROR = %X'10'; literal KA0302$M_IPCHST_H1_PWROK = %X'20'; literal KA0302$M_IPCHST_H1_CBLOK = %X'40'; literal KA0302$M_IPCHST_H1_PWROK_TRANS = %X'80'; literal KA0302$M_IPCHST_H2_ERROR = %X'100'; literal KA0302$M_IPCHST_H2_PWROK = %X'200'; literal KA0302$M_IPCHST_H2_CBLOK = %X'400'; literal KA0302$M_IPCHST_H2_PWROK_TRANS = %X'800'; literal KA0302$M_IPCHST_H3_ERROR = %X'1000'; literal KA0302$M_IPCHST_H3_PWROK = %X'2000'; literal KA0302$M_IPCHST_H3_CBLOK = %X'4000'; literal KA0302$M_IPCHST_H3_PWROK_TRANS = %X'8000'; literal KA0302$M_IPCHST_HOSE0_RST = %X'10000000'; literal KA0302$M_IPCHST_HOSE1_RST = %X'20000000'; literal KA0302$M_IPCHST_HOSE2_RST = %X'40000000'; literal KA0302$M_IPCHST_HOSE3_RST = %X'80000000'; literal KA0302$K_IPCHST_BUS_PRESENT = 6; literal KA0302$M_IPCDR_FRC_DN_ILL_CMD = %X'1'; literal KA0302$M_IPCDR_FRC_DN_SEQ_ERR = %X'2'; literal KA0302$M_IPCDR_FRC_DN_DPE = %X'C'; literal KA0302$M_IPCDR_DIS_LSB_CMD = %X'400'; literal KA0302$M_IPCDR_HIC_LPBCK_EN = %X'800'; literal KA0302$M_IPCDR_FRC_DAT_PE = %X'1000'; literal KA0302$M_IPCDR_FRC_CMD_PE = %X'2000'; literal KA0302$M_IPCDR_FRC_CNFE = %X'400000'; literal KA0302$M_IPCDR_FRC_CAE = %X'800000'; literal KA0302$M_IPCDR_DIAG_ECC = %X'7F000000'; literal KA0302$M_IPCDR_DIAG_ECC_EN = %X'80000000'; literal KA0302$M_LIOINTR_CPU0 = %X'F'; literal KA0302$M_LIOINTR_CPU1 = %X'F0'; literal KA0302$M_LIOINTR_CPU2 = %X'F00'; literal KA0302$M_LIOINTR_CPU3 = %X'F000'; literal KA0302$M_LIPINTR_CPU0 = %X'F'; literal KA0302$M_LIPINTR_CPU1 = %X'F0'; literal KA0302$M_LIPINTR_CPU2 = %X'F00'; literal KA0302$M_LIPINTR_CPU3 = %X'F000'; literal KA0302$M_WATCH_CSRA_RS = %X'F'; literal KA0302$M_WATCH_CSRA_DV = %X'70'; literal KA0302$M_WATCH_CSRA_UIP = %X'80'; literal KA0302$M_WATCH_CSRB_DSE = %X'1'; literal KA0302$M_WATCH_CSRB_24_12 = %X'2'; literal KA0302$M_WATCH_CSRB_DM = %X'4'; literal KA0302$M_WATCH_CSRB_SQWE = %X'8'; literal KA0302$M_WATCH_CSRB_UIE = %X'10'; literal KA0302$M_WATCH_CSRB_AIE = %X'20'; literal KA0302$M_WATCH_CSRB_PIE = %X'40'; literal KA0302$M_WATCH_CSRB_SET = %X'80'; literal KA0302$M_WATCH_CSRC_UF = %X'10'; literal KA0302$M_WATCH_CSRC_AF = %X'20'; literal KA0302$M_WATCH_CSRC_PF = %X'40'; literal KA0302$M_WATCH_CSRC_IRQF = %X'80'; literal KA0302$M_WATCH_CSRD_VRT = %X'80'; literal KA0302$M_GBUS_WHAMI_NID = %X'7'; literal KA0302$M_GBUS_WHAMI_MFG = %X'8'; literal KA0302$M_GBUS_WHAMI_LSB_BAD = %X'10'; literal KA0302$M_GBUS_LEDS_STP = %X'1'; literal KA0302$M_GBUS_LEDS_CONW = %X'2'; literal KA0302$M_GBUS_LEDS_RUN = %X'4'; literal KA0302$M_GBUS_LEDS_LED3 = %X'8'; literal KA0302$M_GBUS_LEDS_LED4 = %X'10'; literal KA0302$M_GBUS_LEDS_LED5 = %X'20'; literal KA0302$M_GBUS_LEDS_LED6 = %X'40'; literal KA0302$M_GBUS_LEDS_LED7 = %X'80'; literal KA0302$M_GBUS_PMASK_HALTEN = %X'1'; literal KA0302$M_GBUS_PMASK_SELTERM = %X'6'; literal KA0302$M_GBUS_INTR_UARTINT0 = %X'1'; literal KA0302$M_GBUS_INTR_UARTINT1 = %X'2'; literal KA0302$M_GBUS_INTR_LSB0 = %X'4'; literal KA0302$M_GBUS_INTR_LSB2 = %X'20'; literal KA0302$M_GBUS_INTR_IP = %X'40'; literal KA0302$M_GBUS_INTR_INTIM = %X'80'; literal KA0302$M_GBUS_HALT_PHALT = %X'40'; literal KA0302$M_GBUS_HALT_NHALT = %X'80'; literal KA0302$M_GBUS_MISC_EXPSEL = %X'3'; literal KA0302$S_KA0302DEF = 262404; ! Old size name, synonym for KA0302$S_KA0302 literal KA0302$S_KA0302 = 262404; macro KA0302$L_SLOT0_LDEV = 0,0,32,0 %; macro KA0302$V_SLOT0_LDEV_DTYPE = 0,0,16,0 %; literal KA0302$S_SLOT0_LDEV_DTYPE = 16; macro KA0302$V_SLOT0_LDEV_DREV = 0,16,16,0 %; literal KA0302$S_SLOT0_LDEV_DREV = 16; macro KA0302$b_fill10 = 4,0,0,0 %; literal KA0302$s_fill10 = 60; macro KA0302$L_SLOT0_LBER = 64,0,32,0 %; macro KA0302$V_SLOT0_LBER_E = 64,0,1,0 %; macro KA0302$V_SLOT0_LBER_UCE = 64,1,1,0 %; macro KA0302$V_SLOT0_LBER_UCE2 = 64,2,1,0 %; macro KA0302$V_SLOT0_LBER_CE = 64,3,1,0 %; macro KA0302$V_SLOT0_LBER_CE2 = 64,4,1,0 %; macro KA0302$V_SLOT0_LBER_CPE = 64,5,1,0 %; macro KA0302$V_SLOT0_LBER_CPE2 = 64,6,1,0 %; macro KA0302$V_SLOT0_LBER_CDPE = 64,7,1,0 %; macro KA0302$V_SLOT0_LBER_CDPE2 = 64,8,1,0 %; macro KA0302$V_SLOT0_LBER_TDE = 64,9,1,0 %; macro KA0302$V_SLOT0_LBER_STE = 64,10,1,0 %; macro KA0302$V_SLOT0_LBER_CNFE = 64,11,1,0 %; macro KA0302$V_SLOT0_LBER_NXAE = 64,12,1,0 %; macro KA0302$V_SLOT0_LBER_CAE = 64,13,1,0 %; macro KA0302$V_SLOT0_LBER_SHE = 64,14,1,0 %; macro KA0302$V_SLOT0_LBER_DIE = 64,15,1,0 %; macro KA0302$V_SLOT0_LBER_DTCE = 64,16,1,0 %; macro KA0302$V_SLOT0_LBER_CTCE = 64,17,1,0 %; macro KA0302$V_SLOT0_LBER_NSES = 64,18,1,0 %; macro KA0302$b_fill20 = 68,0,0,0 %; literal KA0302$s_fill20 = 60; macro KA0302$L_SLOT0_LCNR = 128,0,32,0 %; macro KA0302$V_SLOT0_LCNR_CEEN = 128,0,1,0 %; macro KA0302$V_SLOT0_LCNR_RSTSTAT = 128,28,1,0 %; macro KA0302$V_SLOT0_LCNR_NHALT = 128,29,1,0 %; macro KA0302$V_SLOT0_LCNR_NRST = 128,30,1,0 %; macro KA0302$V_SLOT0_LCNR_STF = 128,31,1,0 %; macro KA0302$b_fill25 = 132,0,0,0 %; literal KA0302$s_fill25 = 60; macro KA0302$L_SLOT0_IBR = 192,0,32,0 %; macro KA0302$V_SLOT0_IBR_RCV_SDAT = 192,0,1,0 %; macro KA0302$V_SLOT0_IBR_XMT_SDAT = 192,1,1,0 %; macro KA0302$V_SLOT0_IBR_SCLK = 192,2,1,0 %; macro KA0302$b_fill30 = 196,0,0,0 %; literal KA0302$s_fill30 = 316; macro KA0302$L_SLOT0_LMMR0 = 512,0,32,0 %; macro KA0302$V_SLOT0_LMMR0_EN = 512,0,1,0 %; macro KA0302$V_SLOT0_LMMR0_INT = 512,1,2,0 %; literal KA0302$S_SLOT0_LMMR0_INT = 2; macro KA0302$V_SLOT0_LMMR0_IA = 512,3,2,0 %; literal KA0302$S_SLOT0_LMMR0_IA = 2; macro KA0302$V_SLOT0_LMMR0_AW = 512,5,4,0 %; literal KA0302$S_SLOT0_LMMR0_AW = 4; macro KA0302$V_SLOT0_LMMR0_NBANKS = 512,9,2,0 %; literal KA0302$S_SLOT0_LMMR0_NBANKS = 2; macro KA0302$V_SLOT0_LMMR0_ADDR = 512,17,15,0 %; literal KA0302$S_SLOT0_LMMR0_ADDR = 15; macro KA0302$b_fill40 = 516,0,0,0 %; literal KA0302$s_fill40 = 60; macro KA0302$L_SLOT0_LMMR1 = 576,0,32,0 %; macro KA0302$V_SLOT0_LMMR1_EN = 576,0,1,0 %; macro KA0302$V_SLOT0_LMMR1_INT = 576,1,2,0 %; literal KA0302$S_SLOT0_LMMR1_INT = 2; macro KA0302$V_SLOT0_LMMR1_IA = 576,3,2,0 %; literal KA0302$S_SLOT0_LMMR1_IA = 2; macro KA0302$V_SLOT0_LMMR1_AW = 576,5,4,0 %; literal KA0302$S_SLOT0_LMMR1_AW = 4; macro KA0302$V_SLOT0_LMMR1_NBANKS = 576,9,2,0 %; literal KA0302$S_SLOT0_LMMR1_NBANKS = 2; macro KA0302$V_SLOT0_LMMR1_ADDR = 576,17,15,0 %; literal KA0302$S_SLOT0_LMMR1_ADDR = 15; macro KA0302$b_fill50 = 580,0,0,0 %; literal KA0302$s_fill50 = 60; macro KA0302$L_SLOT0_LMMR2 = 640,0,32,0 %; macro KA0302$V_SLOT0_LMMR2_EN = 640,0,1,0 %; macro KA0302$V_SLOT0_LMMR2_INT = 640,1,2,0 %; literal KA0302$S_SLOT0_LMMR2_INT = 2; macro KA0302$V_SLOT0_LMMR2_IA = 640,3,2,0 %; literal KA0302$S_SLOT0_LMMR2_IA = 2; macro KA0302$V_SLOT0_LMMR2_AW = 640,5,4,0 %; literal KA0302$S_SLOT0_LMMR2_AW = 4; macro KA0302$V_SLOT0_LMMR2_NBANKS = 640,9,2,0 %; literal KA0302$S_SLOT0_LMMR2_NBANKS = 2; macro KA0302$V_SLOT0_LMMR2_ADDR = 640,17,15,0 %; literal KA0302$S_SLOT0_LMMR2_ADDR = 15; macro KA0302$b_fill60 = 644,0,0,0 %; literal KA0302$s_fill60 = 60; macro KA0302$L_SLOT0_LMMR3 = 704,0,32,0 %; macro KA0302$V_SLOT0_LMMR3_EN = 704,0,1,0 %; macro KA0302$V_SLOT0_LMMR3_INT = 704,1,2,0 %; literal KA0302$S_SLOT0_LMMR3_INT = 2; macro KA0302$V_SLOT0_LMMR3_IA = 704,3,2,0 %; literal KA0302$S_SLOT0_LMMR3_IA = 2; macro KA0302$V_SLOT0_LMMR3_AW = 704,5,4,0 %; literal KA0302$S_SLOT0_LMMR3_AW = 4; macro KA0302$V_SLOT0_LMMR3_NBANKS = 704,9,2,0 %; literal KA0302$S_SLOT0_LMMR3_NBANKS = 2; macro KA0302$V_SLOT0_LMMR3_ADDR = 704,17,15,0 %; literal KA0302$S_SLOT0_LMMR3_ADDR = 15; macro KA0302$b_fill70 = 708,0,0,0 %; literal KA0302$s_fill70 = 60; macro KA0302$L_SLOT0_LMMR4 = 768,0,32,0 %; macro KA0302$V_SLOT0_LMMR4_EN = 768,0,1,0 %; macro KA0302$V_SLOT0_LMMR4_INT = 768,1,2,0 %; literal KA0302$S_SLOT0_LMMR4_INT = 2; macro KA0302$V_SLOT0_LMMR4_IA = 768,3,2,0 %; literal KA0302$S_SLOT0_LMMR4_IA = 2; macro KA0302$V_SLOT0_LMMR4_AW = 768,5,4,0 %; literal KA0302$S_SLOT0_LMMR4_AW = 4; macro KA0302$V_SLOT0_LMMR4_NBANKS = 768,9,2,0 %; literal KA0302$S_SLOT0_LMMR4_NBANKS = 2; macro KA0302$V_SLOT0_LMMR4_ADDR = 768,17,15,0 %; literal KA0302$S_SLOT0_LMMR4_ADDR = 15; macro KA0302$b_fill80 = 772,0,0,0 %; literal KA0302$s_fill80 = 60; macro KA0302$L_SLOT0_LMMR5 = 832,0,32,0 %; macro KA0302$V_SLOT0_LMMR5_EN = 832,0,1,0 %; macro KA0302$V_SLOT0_LMMR5_INT = 832,1,2,0 %; literal KA0302$S_SLOT0_LMMR5_INT = 2; macro KA0302$V_SLOT0_LMMR5_IA = 832,3,2,0 %; literal KA0302$S_SLOT0_LMMR5_IA = 2; macro KA0302$V_SLOT0_LMMR5_AW = 832,5,4,0 %; literal KA0302$S_SLOT0_LMMR5_AW = 4; macro KA0302$V_SLOT0_LMMR5_NBANKS = 832,9,2,0 %; literal KA0302$S_SLOT0_LMMR5_NBANKS = 2; macro KA0302$V_SLOT0_LMMR5_ADDR = 832,17,15,0 %; literal KA0302$S_SLOT0_LMMR5_ADDR = 15; macro KA0302$b_fill90 = 836,0,0,0 %; literal KA0302$s_fill90 = 60; macro KA0302$L_SLOT0_LMMR6 = 896,0,32,0 %; macro KA0302$V_SLOT0_LMMR6_EN = 896,0,1,0 %; macro KA0302$V_SLOT0_LMMR6_INT = 896,1,2,0 %; literal KA0302$S_SLOT0_LMMR6_INT = 2; macro KA0302$V_SLOT0_LMMR6_IA = 896,3,2,0 %; literal KA0302$S_SLOT0_LMMR6_IA = 2; macro KA0302$V_SLOT0_LMMR6_AW = 896,5,4,0 %; literal KA0302$S_SLOT0_LMMR6_AW = 4; macro KA0302$V_SLOT0_LMMR6_NBANKS = 896,9,2,0 %; literal KA0302$S_SLOT0_LMMR6_NBANKS = 2; macro KA0302$V_SLOT0_LMMR6_ADDR = 896,17,15,0 %; literal KA0302$S_SLOT0_LMMR6_ADDR = 15; macro KA0302$b_fill100 = 900,0,0,0 %; literal KA0302$s_fill100 = 60; macro KA0302$L_SLOT0_LMMR7 = 960,0,32,0 %; macro KA0302$V_SLOT0_LMMR7_EN = 960,0,1,0 %; macro KA0302$V_SLOT0_LMMR7_INT = 960,1,2,0 %; literal KA0302$S_SLOT0_LMMR7_INT = 2; macro KA0302$V_SLOT0_LMMR7_IA = 960,3,2,0 %; literal KA0302$S_SLOT0_LMMR7_IA = 2; macro KA0302$V_SLOT0_LMMR7_AW = 960,5,4,0 %; literal KA0302$S_SLOT0_LMMR7_AW = 4; macro KA0302$V_SLOT0_LMMR7_NBANKS = 960,9,2,0 %; literal KA0302$S_SLOT0_LMMR7_NBANKS = 2; macro KA0302$V_SLOT0_LMMR7_ADDR = 960,17,15,0 %; literal KA0302$S_SLOT0_LMMR7_ADDR = 15; macro KA0302$b_fill110 = 964,0,0,0 %; literal KA0302$s_fill110 = 572; macro KA0302$L_SLOT0_LBESR0 = 1536,0,32,0 %; macro KA0302$V_SLOT0_LBESR0_SYNDROME = 1536,0,7,0 %; literal KA0302$S_SLOT0_LBESR0_SYNDROME = 7; macro KA0302$b_fill120 = 1540,0,0,0 %; literal KA0302$s_fill120 = 60; macro KA0302$L_SLOT0_LBESR1 = 1600,0,32,0 %; macro KA0302$V_SLOT0_LBESR1_SYNDROME = 1600,0,7,0 %; literal KA0302$S_SLOT0_LBESR1_SYNDROME = 7; macro KA0302$b_fill130 = 1604,0,0,0 %; literal KA0302$s_fill130 = 60; macro KA0302$L_SLOT0_LBESR2 = 1664,0,32,0 %; macro KA0302$V_SLOT0_LBESR2_SYNDROME = 1664,0,7,0 %; literal KA0302$S_SLOT0_LBESR2_SYNDROME = 7; macro KA0302$b_fill140 = 1668,0,0,0 %; literal KA0302$s_fill140 = 60; macro KA0302$L_SLOT0_LBESR3 = 1728,0,32,0 %; macro KA0302$V_SLOT0_LBESR3_SYNDROME = 1728,0,7,0 %; literal KA0302$S_SLOT0_LBESR3_SYNDROME = 7; macro KA0302$b_fill150 = 1732,0,0,0 %; literal KA0302$s_fill150 = 60; macro KA0302$L_SLOT0_LBECR0 = 1792,0,32,0 %; macro KA0302$L_SLOT0_LBECR0_CA = 1792,0,32,0 %; macro KA0302$b_fill160 = 1796,0,0,0 %; literal KA0302$s_fill160 = 60; macro KA0302$L_SLOT0_LBECR1 = 1856,0,32,0 %; macro KA0302$V_SLOT0_LBECR1_CA = 1856,0,7,0 %; literal KA0302$S_SLOT0_LBECR1_CA = 7; macro KA0302$V_SLOT0_LBECR1_CID = 1856,7,4,0 %; literal KA0302$S_SLOT0_LBECR1_CID = 4; macro KA0302$V_SLOT0_LBECR1_RID = 1856,11,4,0 %; literal KA0302$S_SLOT0_LBECR1_RID = 4; macro KA0302$V_SLOT0_LBECR1_CNF = 1856,15,1,0 %; macro KA0302$V_SLOT0_LBECR1_SHARED = 1856,16,1,0 %; macro KA0302$V_SLOT0_LBECR1_DIRTY = 1856,17,1,0 %; macro KA0302$V_SLOT0_LBECR1_DCYCLE = 1856,18,2,0 %; literal KA0302$S_SLOT0_LBECR1_DCYCLE = 2; macro KA0302$b_fill170 = 1860,0,0,0 %; literal KA0302$s_fill170 = 1212; macro KA0302$L_SLOT0_LMODE = 3072,0,32,0 %; macro KA0302$b_fill180 = 3076,0,0,0 %; literal KA0302$s_fill180 = 60; macro KA0302$L_SLOT0_LMERR = 3136,0,32,0 %; macro KA0302$b_fill190 = 3140,0,0,0 %; literal KA0302$s_fill190 = 60; macro KA0302$L_SLOT0_LLOCK = 3200,0,32,0 %; macro KA0302$b_fill200 = 3204,0,0,0 %; literal KA0302$s_fill200 = 60; macro KA0302$L_SLOT0_LEDTO = 3264,0,32,0 %; macro KA0302$b_fill210 = 3268,0,0,0 %; literal KA0302$s_fill210 = 60; macro KA0302$L_SLOT0_LDIAG = 3328,0,32,0 %; macro KA0302$b_fill220 = 3332,0,0,0 %; literal KA0302$s_fill220 = 60; macro KA0302$L_SLOT0_LTAGA = 3392,0,32,0 %; macro KA0302$b_fill230 = 3396,0,0,0 %; literal KA0302$s_fill230 = 60; macro KA0302$L_SLOT0_LTAGW = 3456,0,32,0 %; macro KA0302$b_fill240 = 3460,0,0,0 %; literal KA0302$s_fill240 = 124; macro KA0302$L_SLOT0_LCON0 = 3584,0,32,0 %; macro KA0302$b_fill250 = 3588,0,0,0 %; literal KA0302$s_fill250 = 60; macro KA0302$L_SLOT0_LCON1 = 3648,0,32,0 %; macro KA0302$b_fill260 = 3652,0,0,0 %; literal KA0302$s_fill260 = 188; macro KA0302$L_SLOT0_LPERF = 3840,0,32,0 %; macro KA0302$b_fill270 = 3844,0,0,0 %; literal KA0302$s_fill270 = 60; macro KA0302$L_SLOT0_LCNTR0 = 3904,0,32,0 %; macro KA0302$b_fill280 = 3908,0,0,0 %; literal KA0302$s_fill280 = 60; macro KA0302$L_SLOT0_LCNTR1 = 3968,0,32,0 %; macro KA0302$b_fill290 = 3972,0,0,0 %; literal KA0302$s_fill290 = 60; macro KA0302$L_SLOT0_LMISSADDR = 4032,0,32,0 %; macro KA0302$b_fill300 = 4036,0,0,0 %; literal KA0302$s_fill300 = 4156; macro KA0302$L_SLOT0_MCR = 8192,0,32,0 %; macro KA0302$V_SLOT0_MCR_DTYPE = 8192,0,1,0 %; macro KA0302$V_SLOT0_MCR_STRN = 8192,2,2,0 %; literal KA0302$S_SLOT0_MCR_STRN = 2; macro KA0302$b_fill305 = 8196,0,0,0 %; literal KA0302$s_fill305 = 60; macro KA0302$L_SLOT0_AMR = 8256,0,32,0 %; macro KA0302$V_SLOT0_AMR_E = 8256,0,1,0 %; macro KA0302$V_SLOT0_AMR_INTL = 8256,1,2,0 %; literal KA0302$S_SLOT0_AMR_INTL = 2; macro KA0302$V_SLOT0_AMR_IA = 8256,3,2,0 %; literal KA0302$S_SLOT0_AMR_IA = 2; macro KA0302$V_SLOT0_AMR_AW = 8256,5,4,0 %; literal KA0302$S_SLOT0_AMR_AW = 4; macro KA0302$V_SLOT0_AMR_NBANKS = 8256,9,2,0 %; literal KA0302$S_SLOT0_AMR_NBANKS = 2; macro KA0302$V_SLOT0_AMR_MADR = 8256,17,15,0 %; literal KA0302$S_SLOT0_AMR_MADR = 15; macro KA0302$b_fill310 = 8260,0,0,0 %; literal KA0302$s_fill310 = 60; macro KA0302$L_SLOT0_MSTR0 = 8320,0,32,0 %; macro KA0302$b_fill320 = 8324,0,0,0 %; literal KA0302$s_fill320 = 60; macro KA0302$L_SLOT0_MSTR1 = 8384,0,32,0 %; macro KA0302$b_fill330 = 8388,0,0,0 %; literal KA0302$s_fill330 = 60; macro KA0302$L_SLOT0_FADR = 8448,0,32,0 %; macro KA0302$b_fill340 = 8452,0,0,0 %; literal KA0302$s_fill340 = 60; macro KA0302$L_SLOT0_MERA = 8512,0,32,0 %; macro KA0302$V_SLOT0_MERA_CER = 8512,0,1,0 %; macro KA0302$V_SLOT0_MERA_UCER = 8512,1,1,0 %; macro KA0302$V_SLOT0_MERA_MULE = 8512,2,1,0 %; macro KA0302$V_SLOT0_MERA_APER = 8512,3,1,0 %; macro KA0302$V_SLOT0_MERA_CERA = 8512,4,1,0 %; macro KA0302$V_SLOT0_MERA_CERB = 8512,5,1,0 %; macro KA0302$V_SLOT0_MERA_FSTR = 8512,6,3,0 %; literal KA0302$S_SLOT0_MERA_FSTR = 3; macro KA0302$V_SLOT0_MERA_BNKER = 8512,9,1,0 %; macro KA0302$V_SLOT0_MERA_UCERA = 8512,10,1,0 %; macro KA0302$V_SLOT0_MERA_UCERB = 8512,11,1,0 %; macro KA0302$b_fill350 = 8516,0,0,0 %; literal KA0302$s_fill350 = 60; macro KA0302$L_SLOT0_MSYNDA = 8576,0,32,0 %; macro KA0302$V_SLOT0_MSYNDA_SYND = 8576,0,8,0 %; literal KA0302$S_SLOT0_MSYNDA_SYND = 8; macro KA0302$b_fill360 = 8580,0,0,0 %; literal KA0302$s_fill360 = 60; macro KA0302$L_SLOT0_MDRA = 8640,0,32,0 %; macro KA0302$V_SLOT0_MDRA_FCBS = 8640,0,1,0 %; macro KA0302$V_SLOT0_MDRA_DRDC = 8640,1,1,0 %; macro KA0302$V_SLOT0_MDRA_DWDC = 8640,2,1,0 %; macro KA0302$V_SLOT0_MDRA_BPAS = 8640,3,1,0 %; macro KA0302$V_SLOT0_MDRA_EXST = 8640,4,1,0 %; macro KA0302$V_SLOT0_MDRA_STPM = 8640,5,1,0 %; macro KA0302$V_SLOT0_MDRA_MODE = 8640,6,1,0 %; macro KA0302$V_SLOT0_MDRA_IGSB = 8640,7,1,0 %; macro KA0302$V_SLOT0_MDRA_FRPE = 8640,8,1,0 %; macro KA0302$V_SLOT0_MDRA_FCPE = 8640,9,1,0 %; macro KA0302$V_SLOT0_MDRA_DCRD = 8640,27,1,0 %; macro KA0302$V_SLOT0_MDRA_RFR = 8640,28,2,0 %; literal KA0302$S_SLOT0_MDRA_RFR = 2; macro KA0302$V_SLOT0_MDRA_BRFSH = 8640,30,1,0 %; macro KA0302$V_SLOT0_MDRA_DRFSH = 8640,31,1,0 %; macro KA0302$b_fill370 = 8644,0,0,0 %; literal KA0302$s_fill370 = 60; macro KA0302$L_SLOT0_MCBSA = 8704,0,32,0 %; macro KA0302$V_SLOT0_MCBSA_SCB = 8704,0,8,0 %; literal KA0302$S_SLOT0_MCBSA_SCB = 8; macro KA0302$b_fill380 = 8708,0,0,0 %; literal KA0302$s_fill380 = 7996; macro KA0302$L_SLOT0_MERB = 16704,0,32,0 %; macro KA0302$V_SLOT0_MERB_CER = 16704,0,1,0 %; macro KA0302$V_SLOT0_MERB_UCER = 16704,1,1,0 %; macro KA0302$V_SLOT0_MERB_MULE = 16704,2,1,0 %; macro KA0302$V_SLOT0_MERB_APER = 16704,3,1,0 %; macro KA0302$b_fill390 = 16708,0,0,0 %; literal KA0302$s_fill390 = 60; macro KA0302$L_SLOT0_MSYNDB = 16768,0,32,0 %; macro KA0302$V_SLOT0_MSYNDB_SYND = 16768,0,8,0 %; literal KA0302$S_SLOT0_MSYNDB_SYND = 8; macro KA0302$b_fill400 = 16772,0,0,0 %; literal KA0302$s_fill400 = 60; macro KA0302$L_SLOT0_MDRB = 16832,0,32,0 %; macro KA0302$V_SLOT0_MDRB_FCBS = 16832,0,1,0 %; macro KA0302$V_SLOT0_MDRB_DRDC = 16832,1,1,0 %; macro KA0302$V_SLOT0_MDRB_DWDC = 16832,2,1,0 %; macro KA0302$V_SLOT0_MDRB_BPAS = 16832,3,1,0 %; macro KA0302$V_SLOT0_MDRB_EXST = 16832,4,1,0 %; macro KA0302$V_SLOT0_MDRB_STPM = 16832,5,1,0 %; macro KA0302$V_SLOT0_MDRB_MODE = 16832,6,1,0 %; macro KA0302$V_SLOT0_MDRB_IGSB = 16832,7,1,0 %; macro KA0302$b_fill410 = 16836,0,0,0 %; literal KA0302$s_fill410 = 60; macro KA0302$L_SLOT0_MCBSB = 16896,0,32,0 %; macro KA0302$V_SLOT0_MCBSB_SCB = 16896,0,8,0 %; literal KA0302$S_SLOT0_MCBSB_SCB = 8; macro KA0302$b_fill420 = 16900,0,0,0 %; literal KA0302$s_fill420 = 7676; macro KA0302$L_SLOT1_LDEV = 24576,0,32,0 %; macro KA0302$V_SLOT1_LDEV_DTYPE = 24576,0,16,0 %; literal KA0302$S_SLOT1_LDEV_DTYPE = 16; macro KA0302$V_SLOT1_LDEV_DREV = 24576,16,16,0 %; literal KA0302$S_SLOT1_LDEV_DREV = 16; macro KA0302$b_fill430 = 24580,0,0,0 %; literal KA0302$s_fill430 = 60; macro KA0302$L_SLOT1_LBER = 24640,0,32,0 %; macro KA0302$V_SLOT1_LBER_E = 24640,0,1,0 %; macro KA0302$V_SLOT1_LBER_UCE = 24640,1,1,0 %; macro KA0302$V_SLOT1_LBER_UCE2 = 24640,2,1,0 %; macro KA0302$V_SLOT1_LBER_CE = 24640,3,1,0 %; macro KA0302$V_SLOT1_LBER_CE2 = 24640,4,1,0 %; macro KA0302$V_SLOT1_LBER_CPE = 24640,5,1,0 %; macro KA0302$V_SLOT1_LBER_CPE2 = 24640,6,1,0 %; macro KA0302$V_SLOT1_LBER_CDPE = 24640,7,1,0 %; macro KA0302$V_SLOT1_LBER_CDPE2 = 24640,8,1,0 %; macro KA0302$V_SLOT1_LBER_TDE = 24640,9,1,0 %; macro KA0302$V_SLOT1_LBER_STE = 24640,10,1,0 %; macro KA0302$V_SLOT1_LBER_CNFE = 24640,11,1,0 %; macro KA0302$V_SLOT1_LBER_NXAE = 24640,12,1,0 %; macro KA0302$V_SLOT1_LBER_CAE = 24640,13,1,0 %; macro KA0302$V_SLOT1_LBER_SHE = 24640,14,1,0 %; macro KA0302$V_SLOT1_LBER_DIE = 24640,15,1,0 %; macro KA0302$V_SLOT1_LBER_DTCE = 24640,16,1,0 %; macro KA0302$V_SLOT1_LBER_CTCE = 24640,17,1,0 %; macro KA0302$V_SLOT1_LBER_NSES = 24640,18,1,0 %; macro KA0302$b_fill440 = 24644,0,0,0 %; literal KA0302$s_fill440 = 60; macro KA0302$L_SLOT1_LCNR = 24704,0,32,0 %; macro KA0302$V_SLOT1_LCNR_CEEN = 24704,0,1,0 %; macro KA0302$V_SLOT1_LCNR_RSTSTAT = 24704,28,1,0 %; macro KA0302$V_SLOT1_LCNR_NHALT = 24704,29,1,0 %; macro KA0302$V_SLOT1_LCNR_NRST = 24704,30,1,0 %; macro KA0302$V_SLOT1_LCNR_STF = 24704,31,1,0 %; macro KA0302$b_fill445 = 24708,0,0,0 %; literal KA0302$s_fill445 = 60; macro KA0302$L_SLOT1_IBR = 24768,0,32,0 %; macro KA0302$V_SLOT1_IBR_RCV_SDAT = 24768,0,1,0 %; macro KA0302$V_SLOT1_IBR_XMT_SDAT = 24768,1,1,0 %; macro KA0302$V_SLOT1_IBR_SCLK = 24768,2,1,0 %; macro KA0302$b_fill450 = 24772,0,0,0 %; literal KA0302$s_fill450 = 316; macro KA0302$L_SLOT1_LMMR0 = 25088,0,32,0 %; macro KA0302$V_SLOT1_LMMR0_EN = 25088,0,1,0 %; macro KA0302$V_SLOT1_LMMR0_INT = 25088,1,2,0 %; literal KA0302$S_SLOT1_LMMR0_INT = 2; macro KA0302$V_SLOT1_LMMR0_IA = 25088,3,2,0 %; literal KA0302$S_SLOT1_LMMR0_IA = 2; macro KA0302$V_SLOT1_LMMR0_AW = 25088,5,4,0 %; literal KA0302$S_SLOT1_LMMR0_AW = 4; macro KA0302$V_SLOT1_LMMR0_NBANKS = 25088,9,2,0 %; literal KA0302$S_SLOT1_LMMR0_NBANKS = 2; macro KA0302$V_SLOT1_LMMR0_ADDR = 25088,17,15,0 %; literal KA0302$S_SLOT1_LMMR0_ADDR = 15; macro KA0302$b_fill460 = 25092,0,0,0 %; literal KA0302$s_fill460 = 60; macro KA0302$L_SLOT1_LMMR1 = 25152,0,32,0 %; macro KA0302$V_SLOT1_LMMR1_EN = 25152,0,1,0 %; macro KA0302$V_SLOT1_LMMR1_INT = 25152,1,2,0 %; literal KA0302$S_SLOT1_LMMR1_INT = 2; macro KA0302$V_SLOT1_LMMR1_IA = 25152,3,2,0 %; literal KA0302$S_SLOT1_LMMR1_IA = 2; macro KA0302$V_SLOT1_LMMR1_AW = 25152,5,4,0 %; literal KA0302$S_SLOT1_LMMR1_AW = 4; macro KA0302$V_SLOT1_LMMR1_NBANKS = 25152,9,2,0 %; literal KA0302$S_SLOT1_LMMR1_NBANKS = 2; macro KA0302$V_SLOT1_LMMR1_ADDR = 25152,17,15,0 %; literal KA0302$S_SLOT1_LMMR1_ADDR = 15; macro KA0302$b_fill470 = 25156,0,0,0 %; literal KA0302$s_fill470 = 60; macro KA0302$L_SLOT1_LMMR2 = 25216,0,32,0 %; macro KA0302$V_SLOT1_LMMR2_EN = 25216,0,1,0 %; macro KA0302$V_SLOT1_LMMR2_INT = 25216,1,2,0 %; literal KA0302$S_SLOT1_LMMR2_INT = 2; macro KA0302$V_SLOT1_LMMR2_IA = 25216,3,2,0 %; literal KA0302$S_SLOT1_LMMR2_IA = 2; macro KA0302$V_SLOT1_LMMR2_AW = 25216,5,4,0 %; literal KA0302$S_SLOT1_LMMR2_AW = 4; macro KA0302$V_SLOT1_LMMR2_NBANKS = 25216,9,2,0 %; literal KA0302$S_SLOT1_LMMR2_NBANKS = 2; macro KA0302$V_SLOT1_LMMR2_ADDR = 25216,17,15,0 %; literal KA0302$S_SLOT1_LMMR2_ADDR = 15; macro KA0302$b_fill480 = 25220,0,0,0 %; literal KA0302$s_fill480 = 60; macro KA0302$L_SLOT1_LMMR3 = 25280,0,32,0 %; macro KA0302$V_SLOT1_LMMR3_EN = 25280,0,1,0 %; macro KA0302$V_SLOT1_LMMR3_INT = 25280,1,2,0 %; literal KA0302$S_SLOT1_LMMR3_INT = 2; macro KA0302$V_SLOT1_LMMR3_IA = 25280,3,2,0 %; literal KA0302$S_SLOT1_LMMR3_IA = 2; macro KA0302$V_SLOT1_LMMR3_AW = 25280,5,4,0 %; literal KA0302$S_SLOT1_LMMR3_AW = 4; macro KA0302$V_SLOT1_LMMR3_NBANKS = 25280,9,2,0 %; literal KA0302$S_SLOT1_LMMR3_NBANKS = 2; macro KA0302$V_SLOT1_LMMR3_ADDR = 25280,17,15,0 %; literal KA0302$S_SLOT1_LMMR3_ADDR = 15; macro KA0302$b_fill490 = 25284,0,0,0 %; literal KA0302$s_fill490 = 60; macro KA0302$L_SLOT1_LMMR4 = 25344,0,32,0 %; macro KA0302$V_SLOT1_LMMR4_EN = 25344,0,1,0 %; macro KA0302$V_SLOT1_LMMR4_INT = 25344,1,2,0 %; literal KA0302$S_SLOT1_LMMR4_INT = 2; macro KA0302$V_SLOT1_LMMR4_IA = 25344,3,2,0 %; literal KA0302$S_SLOT1_LMMR4_IA = 2; macro KA0302$V_SLOT1_LMMR4_AW = 25344,5,4,0 %; literal KA0302$S_SLOT1_LMMR4_AW = 4; macro KA0302$V_SLOT1_LMMR4_NBANKS = 25344,9,2,0 %; literal KA0302$S_SLOT1_LMMR4_NBANKS = 2; macro KA0302$V_SLOT1_LMMR4_ADDR = 25344,17,15,0 %; literal KA0302$S_SLOT1_LMMR4_ADDR = 15; macro KA0302$b_fill500 = 25348,0,0,0 %; literal KA0302$s_fill500 = 60; macro KA0302$L_SLOT1_LMMR5 = 25408,0,32,0 %; macro KA0302$V_SLOT1_LMMR5_EN = 25408,0,1,0 %; macro KA0302$V_SLOT1_LMMR5_INT = 25408,1,2,0 %; literal KA0302$S_SLOT1_LMMR5_INT = 2; macro KA0302$V_SLOT1_LMMR5_IA = 25408,3,2,0 %; literal KA0302$S_SLOT1_LMMR5_IA = 2; macro KA0302$V_SLOT1_LMMR5_AW = 25408,5,4,0 %; literal KA0302$S_SLOT1_LMMR5_AW = 4; macro KA0302$V_SLOT1_LMMR5_NBANKS = 25408,9,2,0 %; literal KA0302$S_SLOT1_LMMR5_NBANKS = 2; macro KA0302$V_SLOT1_LMMR5_ADDR = 25408,17,15,0 %; literal KA0302$S_SLOT1_LMMR5_ADDR = 15; macro KA0302$b_fill510 = 25412,0,0,0 %; literal KA0302$s_fill510 = 60; macro KA0302$L_SLOT1_LMMR6 = 25472,0,32,0 %; macro KA0302$V_SLOT1_LMMR6_EN = 25472,0,1,0 %; macro KA0302$V_SLOT1_LMMR6_INT = 25472,1,2,0 %; literal KA0302$S_SLOT1_LMMR6_INT = 2; macro KA0302$V_SLOT1_LMMR6_IA = 25472,3,2,0 %; literal KA0302$S_SLOT1_LMMR6_IA = 2; macro KA0302$V_SLOT1_LMMR6_AW = 25472,5,4,0 %; literal KA0302$S_SLOT1_LMMR6_AW = 4; macro KA0302$V_SLOT1_LMMR6_NBANKS = 25472,9,2,0 %; literal KA0302$S_SLOT1_LMMR6_NBANKS = 2; macro KA0302$V_SLOT1_LMMR6_ADDR = 25472,17,15,0 %; literal KA0302$S_SLOT1_LMMR6_ADDR = 15; macro KA0302$b_fill520 = 25476,0,0,0 %; literal KA0302$s_fill520 = 60; macro KA0302$L_SLOT1_LMMR7 = 25536,0,32,0 %; macro KA0302$V_SLOT1_LMMR7_EN = 25536,0,1,0 %; macro KA0302$V_SLOT1_LMMR7_INT = 25536,1,2,0 %; literal KA0302$S_SLOT1_LMMR7_INT = 2; macro KA0302$V_SLOT1_LMMR7_IA = 25536,3,2,0 %; literal KA0302$S_SLOT1_LMMR7_IA = 2; macro KA0302$V_SLOT1_LMMR7_AW = 25536,5,4,0 %; literal KA0302$S_SLOT1_LMMR7_AW = 4; macro KA0302$V_SLOT1_LMMR7_NBANKS = 25536,9,2,0 %; literal KA0302$S_SLOT1_LMMR7_NBANKS = 2; macro KA0302$V_SLOT1_LMMR7_ADDR = 25536,17,15,0 %; literal KA0302$S_SLOT1_LMMR7_ADDR = 15; macro KA0302$b_fill530 = 25540,0,0,0 %; literal KA0302$s_fill530 = 572; macro KA0302$L_SLOT1_LBESR0 = 26112,0,32,0 %; macro KA0302$V_SLOT1_LBESR0_SYNDROME = 26112,0,7,0 %; literal KA0302$S_SLOT1_LBESR0_SYNDROME = 7; macro KA0302$b_fill540 = 26116,0,0,0 %; literal KA0302$s_fill540 = 60; macro KA0302$L_SLOT1_LBESR1 = 26176,0,32,0 %; macro KA0302$V_SLOT1_LBESR1_SYNDROME = 26176,0,7,0 %; literal KA0302$S_SLOT1_LBESR1_SYNDROME = 7; macro KA0302$b_fill550 = 26180,0,0,0 %; literal KA0302$s_fill550 = 60; macro KA0302$L_SLOT1_LBESR2 = 26240,0,32,0 %; macro KA0302$V_SLOT1_LBESR2_SYNDROME = 26240,0,7,0 %; literal KA0302$S_SLOT1_LBESR2_SYNDROME = 7; macro KA0302$b_fill560 = 26244,0,0,0 %; literal KA0302$s_fill560 = 60; macro KA0302$L_SLOT1_LBESR3 = 26304,0,32,0 %; macro KA0302$V_SLOT1_LBESR3_SYNDROME = 26304,0,7,0 %; literal KA0302$S_SLOT1_LBESR3_SYNDROME = 7; macro KA0302$b_fill570 = 26308,0,0,0 %; literal KA0302$s_fill570 = 60; macro KA0302$L_SLOT1_LBECR0 = 26368,0,32,0 %; macro KA0302$L_SLOT1_LBECR0_CA = 26368,0,32,0 %; macro KA0302$b_fill580 = 26372,0,0,0 %; literal KA0302$s_fill580 = 60; macro KA0302$L_SLOT1_LBECR1 = 26432,0,32,0 %; macro KA0302$V_SLOT1_LBECR1_CA = 26432,0,7,0 %; literal KA0302$S_SLOT1_LBECR1_CA = 7; macro KA0302$V_SLOT1_LBECR1_CID = 26432,7,4,0 %; literal KA0302$S_SLOT1_LBECR1_CID = 4; macro KA0302$V_SLOT1_LBECR1_RID = 26432,11,4,0 %; literal KA0302$S_SLOT1_LBECR1_RID = 4; macro KA0302$V_SLOT1_LBECR1_CNF = 26432,15,1,0 %; macro KA0302$V_SLOT1_LBECR1_SHARED = 26432,16,1,0 %; macro KA0302$V_SLOT1_LBECR1_DIRTY = 26432,17,1,0 %; macro KA0302$V_SLOT1_LBECR1_DCYCLE = 26432,18,2,0 %; literal KA0302$S_SLOT1_LBECR1_DCYCLE = 2; macro KA0302$b_fill590 = 26436,0,0,0 %; literal KA0302$s_fill590 = 1212; macro KA0302$L_SLOT1_LMODE = 27648,0,32,0 %; macro KA0302$b_fill600 = 27652,0,0,0 %; literal KA0302$s_fill600 = 60; macro KA0302$L_SLOT1_LMERR = 27712,0,32,0 %; macro KA0302$b_fill610 = 27716,0,0,0 %; literal KA0302$s_fill610 = 60; macro KA0302$L_SLOT1_LLOCK = 27776,0,32,0 %; macro KA0302$b_fill620 = 27780,0,0,0 %; literal KA0302$s_fill620 = 60; macro KA0302$L_SLOT1_LEDTO = 27840,0,32,0 %; macro KA0302$b_fill630 = 27844,0,0,0 %; literal KA0302$s_fill630 = 60; macro KA0302$L_SLOT1_LDIAG = 27904,0,32,0 %; macro KA0302$b_fill640 = 27908,0,0,0 %; literal KA0302$s_fill640 = 60; macro KA0302$L_SLOT1_LTAGA = 27968,0,32,0 %; macro KA0302$b_fill650 = 27972,0,0,0 %; literal KA0302$s_fill650 = 60; macro KA0302$L_SLOT1_LTAGW = 28032,0,32,0 %; macro KA0302$b_fill660 = 28036,0,0,0 %; literal KA0302$s_fill660 = 124; macro KA0302$L_SLOT1_LCON0 = 28160,0,32,0 %; macro KA0302$b_fill670 = 28164,0,0,0 %; literal KA0302$s_fill670 = 60; macro KA0302$L_SLOT1_LCON1 = 28224,0,32,0 %; macro KA0302$b_fill680 = 28228,0,0,0 %; literal KA0302$s_fill680 = 188; macro KA0302$L_SLOT1_LPERF = 28416,0,32,0 %; macro KA0302$b_fill690 = 28420,0,0,0 %; literal KA0302$s_fill690 = 60; macro KA0302$L_SLOT1_LCNTR0 = 28480,0,32,0 %; macro KA0302$b_fill700 = 28484,0,0,0 %; literal KA0302$s_fill700 = 60; macro KA0302$L_SLOT1_LCNTR1 = 28544,0,32,0 %; macro KA0302$b_fill705 = 28548,0,0,0 %; literal KA0302$s_fill705 = 60; macro KA0302$L_SLOT1_LMISSADDR = 28608,0,32,0 %; macro KA0302$b_fill706 = 28612,0,0,0 %; literal KA0302$s_fill706 = 4156; macro KA0302$L_SLOT1_MCR = 32768,0,32,0 %; macro KA0302$b_fill710 = 32772,0,0,0 %; literal KA0302$s_fill710 = 60; macro KA0302$L_SLOT1_AMR = 32832,0,32,0 %; macro KA0302$b_fill720 = 32836,0,0,0 %; literal KA0302$s_fill720 = 60; macro KA0302$L_SLOT1_MSTR0 = 32896,0,32,0 %; macro KA0302$b_fill730 = 32900,0,0,0 %; literal KA0302$s_fill730 = 60; macro KA0302$L_SLOT1_MSTR1 = 32960,0,32,0 %; macro KA0302$b_fill740 = 32964,0,0,0 %; literal KA0302$s_fill740 = 60; macro KA0302$L_SLOT1_FADR = 33024,0,32,0 %; macro KA0302$b_fill750 = 33028,0,0,0 %; literal KA0302$s_fill750 = 60; macro KA0302$L_SLOT1_MERA = 33088,0,32,0 %; macro KA0302$b_fill760 = 33092,0,0,0 %; literal KA0302$s_fill760 = 60; macro KA0302$L_SLOT1_MSYNDA = 33152,0,32,0 %; macro KA0302$b_fill770 = 33156,0,0,0 %; literal KA0302$s_fill770 = 60; macro KA0302$L_SLOT1_MDRA = 33216,0,32,0 %; macro KA0302$b_fill780 = 33220,0,0,0 %; literal KA0302$s_fill780 = 60; macro KA0302$L_SLOT1_MCBSA = 33280,0,32,0 %; macro KA0302$b_fill790 = 33284,0,0,0 %; literal KA0302$s_fill790 = 7996; macro KA0302$L_SLOT1_MERB = 41280,0,32,0 %; macro KA0302$b_fill800 = 41284,0,0,0 %; literal KA0302$s_fill800 = 60; macro KA0302$L_SLOT1_MSYNDB = 41344,0,32,0 %; macro KA0302$b_fill810 = 41348,0,0,0 %; literal KA0302$s_fill810 = 60; macro KA0302$L_SLOT1_MDRB = 41408,0,32,0 %; macro KA0302$b_fill820 = 41412,0,0,0 %; literal KA0302$s_fill820 = 60; macro KA0302$L_SLOT1_MCBSB = 41472,0,32,0 %; macro KA0302$b_fill830 = 41476,0,0,0 %; literal KA0302$s_fill830 = 7676; macro KA0302$L_SLOT2_LDEV = 49152,0,32,0 %; macro KA0302$V_SLOT2_LDEV_DTYPE = 49152,0,16,0 %; literal KA0302$S_SLOT2_LDEV_DTYPE = 16; macro KA0302$V_SLOT2_LDEV_DREV = 49152,16,16,0 %; literal KA0302$S_SLOT2_LDEV_DREV = 16; macro KA0302$b_fill840 = 49156,0,0,0 %; literal KA0302$s_fill840 = 60; macro KA0302$L_SLOT2_LBER = 49216,0,32,0 %; macro KA0302$V_SLOT2_LBER_E = 49216,0,1,0 %; macro KA0302$V_SLOT2_LBER_UCE = 49216,1,1,0 %; macro KA0302$V_SLOT2_LBER_UCE2 = 49216,2,1,0 %; macro KA0302$V_SLOT2_LBER_CE = 49216,3,1,0 %; macro KA0302$V_SLOT2_LBER_CE2 = 49216,4,1,0 %; macro KA0302$V_SLOT2_LBER_CPE = 49216,5,1,0 %; macro KA0302$V_SLOT2_LBER_CPE2 = 49216,6,1,0 %; macro KA0302$V_SLOT2_LBER_CDPE = 49216,7,1,0 %; macro KA0302$V_SLOT2_LBER_CDPE2 = 49216,8,1,0 %; macro KA0302$V_SLOT2_LBER_TDE = 49216,9,1,0 %; macro KA0302$V_SLOT2_LBER_STE = 49216,10,1,0 %; macro KA0302$V_SLOT2_LBER_CNFE = 49216,11,1,0 %; macro KA0302$V_SLOT2_LBER_NXAE = 49216,12,1,0 %; macro KA0302$V_SLOT2_LBER_CAE = 49216,13,1,0 %; macro KA0302$V_SLOT2_LBER_SHE = 49216,14,1,0 %; macro KA0302$V_SLOT2_LBER_DIE = 49216,15,1,0 %; macro KA0302$V_SLOT2_LBER_DTCE = 49216,16,1,0 %; macro KA0302$V_SLOT2_LBER_CTCE = 49216,17,1,0 %; macro KA0302$V_SLOT2_LBER_NSES = 49216,18,1,0 %; macro KA0302$b_fill850 = 49220,0,0,0 %; literal KA0302$s_fill850 = 60; macro KA0302$L_SLOT2_LCNR = 49280,0,32,0 %; macro KA0302$V_SLOT2_LCNR_CEEN = 49280,0,1,0 %; macro KA0302$V_SLOT2_LCNR_RSTSTAT = 49280,28,1,0 %; macro KA0302$V_SLOT2_LCNR_NHALT = 49280,29,1,0 %; macro KA0302$V_SLOT2_LCNR_NRST = 49280,30,1,0 %; macro KA0302$V_SLOT2_LCNR_STF = 49280,31,1,0 %; macro KA0302$b_fill855 = 49284,0,0,0 %; literal KA0302$s_fill855 = 60; macro KA0302$L_SLOT2_IBR = 49344,0,32,0 %; macro KA0302$V_SLOT2_IBR_RCV_SDAT = 49344,0,1,0 %; macro KA0302$V_SLOT2_IBR_XMT_SDAT = 49344,1,1,0 %; macro KA0302$V_SLOT2_IBR_SCLK = 49344,2,1,0 %; macro KA0302$b_fill860 = 49348,0,0,0 %; literal KA0302$s_fill860 = 316; macro KA0302$L_SLOT2_LMMR0 = 49664,0,32,0 %; macro KA0302$V_SLOT2_LMMR0_EN = 49664,0,1,0 %; macro KA0302$V_SLOT2_LMMR0_INT = 49664,1,2,0 %; literal KA0302$S_SLOT2_LMMR0_INT = 2; macro KA0302$V_SLOT2_LMMR0_IA = 49664,3,2,0 %; literal KA0302$S_SLOT2_LMMR0_IA = 2; macro KA0302$V_SLOT2_LMMR0_AW = 49664,5,4,0 %; literal KA0302$S_SLOT2_LMMR0_AW = 4; macro KA0302$V_SLOT2_LMMR0_NBANKS = 49664,9,2,0 %; literal KA0302$S_SLOT2_LMMR0_NBANKS = 2; macro KA0302$V_SLOT2_LMMR0_ADDR = 49664,17,15,0 %; literal KA0302$S_SLOT2_LMMR0_ADDR = 15; macro KA0302$b_fill870 = 49668,0,0,0 %; literal KA0302$s_fill870 = 60; macro KA0302$L_SLOT2_LMMR1 = 49728,0,32,0 %; macro KA0302$V_SLOT2_LMMR1_EN = 49728,0,1,0 %; macro KA0302$V_SLOT2_LMMR1_INT = 49728,1,2,0 %; literal KA0302$S_SLOT2_LMMR1_INT = 2; macro KA0302$V_SLOT2_LMMR1_IA = 49728,3,2,0 %; literal KA0302$S_SLOT2_LMMR1_IA = 2; macro KA0302$V_SLOT2_LMMR1_AW = 49728,5,4,0 %; literal KA0302$S_SLOT2_LMMR1_AW = 4; macro KA0302$V_SLOT2_LMMR1_NBANKS = 49728,9,2,0 %; literal KA0302$S_SLOT2_LMMR1_NBANKS = 2; macro KA0302$V_SLOT2_LMMR1_ADDR = 49728,17,15,0 %; literal KA0302$S_SLOT2_LMMR1_ADDR = 15; macro KA0302$b_fill880 = 49732,0,0,0 %; literal KA0302$s_fill880 = 60; macro KA0302$L_SLOT2_LMMR2 = 49792,0,32,0 %; macro KA0302$V_SLOT2_LMMR2_EN = 49792,0,1,0 %; macro KA0302$V_SLOT2_LMMR2_INT = 49792,1,2,0 %; literal KA0302$S_SLOT2_LMMR2_INT = 2; macro KA0302$V_SLOT2_LMMR2_IA = 49792,3,2,0 %; literal KA0302$S_SLOT2_LMMR2_IA = 2; macro KA0302$V_SLOT2_LMMR2_AW = 49792,5,4,0 %; literal KA0302$S_SLOT2_LMMR2_AW = 4; macro KA0302$V_SLOT2_LMMR2_NBANKS = 49792,9,2,0 %; literal KA0302$S_SLOT2_LMMR2_NBANKS = 2; macro KA0302$V_SLOT2_LMMR2_ADDR = 49792,17,15,0 %; literal KA0302$S_SLOT2_LMMR2_ADDR = 15; macro KA0302$b_fill890 = 49796,0,0,0 %; literal KA0302$s_fill890 = 60; macro KA0302$L_SLOT2_LMMR3 = 49856,0,32,0 %; macro KA0302$V_SLOT2_LMMR3_EN = 49856,0,1,0 %; macro KA0302$V_SLOT2_LMMR3_INT = 49856,1,2,0 %; literal KA0302$S_SLOT2_LMMR3_INT = 2; macro KA0302$V_SLOT2_LMMR3_IA = 49856,3,2,0 %; literal KA0302$S_SLOT2_LMMR3_IA = 2; macro KA0302$V_SLOT2_LMMR3_AW = 49856,5,4,0 %; literal KA0302$S_SLOT2_LMMR3_AW = 4; macro KA0302$V_SLOT2_LMMR3_NBANKS = 49856,9,2,0 %; literal KA0302$S_SLOT2_LMMR3_NBANKS = 2; macro KA0302$V_SLOT2_LMMR3_ADDR = 49856,17,15,0 %; literal KA0302$S_SLOT2_LMMR3_ADDR = 15; macro KA0302$b_fill900 = 49860,0,0,0 %; literal KA0302$s_fill900 = 60; macro KA0302$L_SLOT2_LMMR4 = 49920,0,32,0 %; macro KA0302$V_SLOT2_LMMR4_EN = 49920,0,1,0 %; macro KA0302$V_SLOT2_LMMR4_INT = 49920,1,2,0 %; literal KA0302$S_SLOT2_LMMR4_INT = 2; macro KA0302$V_SLOT2_LMMR4_IA = 49920,3,2,0 %; literal KA0302$S_SLOT2_LMMR4_IA = 2; macro KA0302$V_SLOT2_LMMR4_AW = 49920,5,4,0 %; literal KA0302$S_SLOT2_LMMR4_AW = 4; macro KA0302$V_SLOT2_LMMR4_NBANKS = 49920,9,2,0 %; literal KA0302$S_SLOT2_LMMR4_NBANKS = 2; macro KA0302$V_SLOT2_LMMR4_ADDR = 49920,17,15,0 %; literal KA0302$S_SLOT2_LMMR4_ADDR = 15; macro KA0302$b_fill910 = 49924,0,0,0 %; literal KA0302$s_fill910 = 60; macro KA0302$L_SLOT2_LMMR5 = 49984,0,32,0 %; macro KA0302$V_SLOT2_LMMR5_EN = 49984,0,1,0 %; macro KA0302$V_SLOT2_LMMR5_INT = 49984,1,2,0 %; literal KA0302$S_SLOT2_LMMR5_INT = 2; macro KA0302$V_SLOT2_LMMR5_IA = 49984,3,2,0 %; literal KA0302$S_SLOT2_LMMR5_IA = 2; macro KA0302$V_SLOT2_LMMR5_AW = 49984,5,4,0 %; literal KA0302$S_SLOT2_LMMR5_AW = 4; macro KA0302$V_SLOT2_LMMR5_NBANKS = 49984,9,2,0 %; literal KA0302$S_SLOT2_LMMR5_NBANKS = 2; macro KA0302$V_SLOT2_LMMR5_ADDR = 49984,17,15,0 %; literal KA0302$S_SLOT2_LMMR5_ADDR = 15; macro KA0302$b_fill920 = 49988,0,0,0 %; literal KA0302$s_fill920 = 60; macro KA0302$L_SLOT2_LMMR6 = 50048,0,32,0 %; macro KA0302$V_SLOT2_LMMR6_EN = 50048,0,1,0 %; macro KA0302$V_SLOT2_LMMR6_INT = 50048,1,2,0 %; literal KA0302$S_SLOT2_LMMR6_INT = 2; macro KA0302$V_SLOT2_LMMR6_IA = 50048,3,2,0 %; literal KA0302$S_SLOT2_LMMR6_IA = 2; macro KA0302$V_SLOT2_LMMR6_AW = 50048,5,4,0 %; literal KA0302$S_SLOT2_LMMR6_AW = 4; macro KA0302$V_SLOT2_LMMR6_NBANKS = 50048,9,2,0 %; literal KA0302$S_SLOT2_LMMR6_NBANKS = 2; macro KA0302$V_SLOT2_LMMR6_ADDR = 50048,17,15,0 %; literal KA0302$S_SLOT2_LMMR6_ADDR = 15; macro KA0302$b_fill930 = 50052,0,0,0 %; literal KA0302$s_fill930 = 60; macro KA0302$L_SLOT2_LMMR7 = 50112,0,32,0 %; macro KA0302$V_SLOT2_LMMR7_EN = 50112,0,1,0 %; macro KA0302$V_SLOT2_LMMR7_INT = 50112,1,2,0 %; literal KA0302$S_SLOT2_LMMR7_INT = 2; macro KA0302$V_SLOT2_LMMR7_IA = 50112,3,2,0 %; literal KA0302$S_SLOT2_LMMR7_IA = 2; macro KA0302$V_SLOT2_LMMR7_AW = 50112,5,4,0 %; literal KA0302$S_SLOT2_LMMR7_AW = 4; macro KA0302$V_SLOT2_LMMR7_NBANKS = 50112,9,2,0 %; literal KA0302$S_SLOT2_LMMR7_NBANKS = 2; macro KA0302$V_SLOT2_LMMR7_ADDR = 50112,17,15,0 %; literal KA0302$S_SLOT2_LMMR7_ADDR = 15; macro KA0302$b_fill940 = 50116,0,0,0 %; literal KA0302$s_fill940 = 572; macro KA0302$L_SLOT2_LBESR0 = 50688,0,32,0 %; macro KA0302$V_SLOT2_LBESR0_SYNDROME = 50688,0,7,0 %; literal KA0302$S_SLOT2_LBESR0_SYNDROME = 7; macro KA0302$b_fill950 = 50692,0,0,0 %; literal KA0302$s_fill950 = 60; macro KA0302$L_SLOT2_LBESR1 = 50752,0,32,0 %; macro KA0302$V_SLOT2_LBESR1_SYNDROME = 50752,0,7,0 %; literal KA0302$S_SLOT2_LBESR1_SYNDROME = 7; macro KA0302$b_fill960 = 50756,0,0,0 %; literal KA0302$s_fill960 = 60; macro KA0302$L_SLOT2_LBESR2 = 50816,0,32,0 %; macro KA0302$V_SLOT2_LBESR2_SYNDROME = 50816,0,7,0 %; literal KA0302$S_SLOT2_LBESR2_SYNDROME = 7; macro KA0302$b_fill970 = 50820,0,0,0 %; literal KA0302$s_fill970 = 60; macro KA0302$L_SLOT2_LBESR3 = 50880,0,32,0 %; macro KA0302$V_SLOT2_LBESR3_SYNDROME = 50880,0,7,0 %; literal KA0302$S_SLOT2_LBESR3_SYNDROME = 7; macro KA0302$b_fill980 = 50884,0,0,0 %; literal KA0302$s_fill980 = 60; macro KA0302$L_SLOT2_LBECR0 = 50944,0,32,0 %; macro KA0302$L_SLOT2_LBECR0_CA = 50944,0,32,0 %; macro KA0302$b_fill990 = 50948,0,0,0 %; literal KA0302$s_fill990 = 60; macro KA0302$L_SLOT2_LBECR1 = 51008,0,32,0 %; macro KA0302$V_SLOT2_LBECR1_CA = 51008,0,7,0 %; literal KA0302$S_SLOT2_LBECR1_CA = 7; macro KA0302$V_SLOT2_LBECR1_CID = 51008,7,4,0 %; literal KA0302$S_SLOT2_LBECR1_CID = 4; macro KA0302$V_SLOT2_LBECR1_RID = 51008,11,4,0 %; literal KA0302$S_SLOT2_LBECR1_RID = 4; macro KA0302$V_SLOT2_LBECR1_CNF = 51008,15,1,0 %; macro KA0302$V_SLOT2_LBECR1_SHARED = 51008,16,1,0 %; macro KA0302$V_SLOT2_LBECR1_DIRTY = 51008,17,1,0 %; macro KA0302$V_SLOT2_LBECR1_DCYCLE = 51008,18,2,0 %; literal KA0302$S_SLOT2_LBECR1_DCYCLE = 2; macro KA0302$b_fill1000 = 51012,0,0,0 %; literal KA0302$s_fill1000 = 1212; macro KA0302$L_SLOT2_LMODE = 52224,0,32,0 %; macro KA0302$b_fill1010 = 52228,0,0,0 %; literal KA0302$s_fill1010 = 60; macro KA0302$L_SLOT2_LMERR = 52288,0,32,0 %; macro KA0302$b_fill1020 = 52292,0,0,0 %; literal KA0302$s_fill1020 = 60; macro KA0302$L_SLOT2_LLOCK = 52352,0,32,0 %; macro KA0302$b_fill1030 = 52356,0,0,0 %; literal KA0302$s_fill1030 = 60; macro KA0302$L_SLOT2_LEDTO = 52416,0,32,0 %; macro KA0302$b_fill1040 = 52420,0,0,0 %; literal KA0302$s_fill1040 = 60; macro KA0302$L_SLOT2_LDIAG = 52480,0,32,0 %; macro KA0302$b_fill1050 = 52484,0,0,0 %; literal KA0302$s_fill1050 = 60; macro KA0302$L_SLOT2_LTAGA = 52544,0,32,0 %; macro KA0302$b_fill1060 = 52548,0,0,0 %; literal KA0302$s_fill1060 = 60; macro KA0302$L_SLOT2_LTAGW = 52608,0,32,0 %; macro KA0302$b_fill1070 = 52612,0,0,0 %; literal KA0302$s_fill1070 = 124; macro KA0302$L_SLOT2_LCON0 = 52736,0,32,0 %; macro KA0302$b_fill1080 = 52740,0,0,0 %; literal KA0302$s_fill1080 = 60; macro KA0302$L_SLOT2_LCON1 = 52800,0,32,0 %; macro KA0302$b_fill1090 = 52804,0,0,0 %; literal KA0302$s_fill1090 = 188; macro KA0302$L_SLOT2_LPERF = 52992,0,32,0 %; macro KA0302$b_fill1100 = 52996,0,0,0 %; literal KA0302$s_fill1100 = 60; macro KA0302$L_SLOT2_LCNTR0 = 53056,0,32,0 %; macro KA0302$b_fill1110 = 53060,0,0,0 %; literal KA0302$s_fill1110 = 60; macro KA0302$L_SLOT2_LCNTR1 = 53120,0,32,0 %; macro KA0302$b_fill1120 = 53124,0,0,0 %; literal KA0302$s_fill1120 = 60; macro KA0302$L_SLOT2_LMISSADDR = 53184,0,32,0 %; macro KA0302$b_fill1125 = 53188,0,0,0 %; literal KA0302$s_fill1125 = 4156; macro KA0302$L_SLOT2_MCR = 57344,0,32,0 %; macro KA0302$b_fill1130 = 57348,0,0,0 %; literal KA0302$s_fill1130 = 60; macro KA0302$L_SLOT2_AMR = 57408,0,32,0 %; macro KA0302$b_fill1140 = 57412,0,0,0 %; literal KA0302$s_fill1140 = 60; macro KA0302$L_SLOT2_MSTR0 = 57472,0,32,0 %; macro KA0302$b_fill1150 = 57476,0,0,0 %; literal KA0302$s_fill1150 = 60; macro KA0302$L_SLOT2_MSTR1 = 57536,0,32,0 %; macro KA0302$b_fill1160 = 57540,0,0,0 %; literal KA0302$s_fill1160 = 60; macro KA0302$L_SLOT2_FADR = 57600,0,32,0 %; macro KA0302$b_fill1170 = 57604,0,0,0 %; literal KA0302$s_fill1170 = 60; macro KA0302$L_SLOT2_MERA = 57664,0,32,0 %; macro KA0302$b_fill1180 = 57668,0,0,0 %; literal KA0302$s_fill1180 = 60; macro KA0302$L_SLOT2_MSYNDA = 57728,0,32,0 %; macro KA0302$b_fill1190 = 57732,0,0,0 %; literal KA0302$s_fill1190 = 60; macro KA0302$L_SLOT2_MDRA = 57792,0,32,0 %; macro KA0302$b_fill1200 = 57796,0,0,0 %; literal KA0302$s_fill1200 = 60; macro KA0302$L_SLOT2_MCBSA = 57856,0,32,0 %; macro KA0302$b_fill1210 = 57860,0,0,0 %; literal KA0302$s_fill1210 = 7996; macro KA0302$L_SLOT2_MERB = 65856,0,32,0 %; macro KA0302$b_fill1220 = 65860,0,0,0 %; literal KA0302$s_fill1220 = 60; macro KA0302$L_SLOT2_MSYNDB = 65920,0,32,0 %; macro KA0302$b_fill1230 = 65924,0,0,0 %; literal KA0302$s_fill1230 = 60; macro KA0302$L_SLOT2_MDRB = 65984,0,32,0 %; macro KA0302$b_fill1240 = 65988,0,0,0 %; literal KA0302$s_fill1240 = 60; macro KA0302$L_SLOT2_MCBSB = 66048,0,32,0 %; macro KA0302$b_fill1250 = 66052,0,0,0 %; literal KA0302$s_fill1250 = 7676; macro KA0302$L_SLOT3_LDEV = 73728,0,32,0 %; macro KA0302$V_SLOT3_LDEV_DTYPE = 73728,0,16,0 %; literal KA0302$S_SLOT3_LDEV_DTYPE = 16; macro KA0302$V_SLOT3_LDEV_DREV = 73728,16,16,0 %; literal KA0302$S_SLOT3_LDEV_DREV = 16; macro KA0302$b_fill1260 = 73732,0,0,0 %; literal KA0302$s_fill1260 = 60; macro KA0302$L_SLOT3_LBER = 73792,0,32,0 %; macro KA0302$V_SLOT3_LBER_E = 73792,0,1,0 %; macro KA0302$V_SLOT3_LBER_UCE = 73792,1,1,0 %; macro KA0302$V_SLOT3_LBER_UCE2 = 73792,2,1,0 %; macro KA0302$V_SLOT3_LBER_CE = 73792,3,1,0 %; macro KA0302$V_SLOT3_LBER_CE2 = 73792,4,1,0 %; macro KA0302$V_SLOT3_LBER_CPE = 73792,5,1,0 %; macro KA0302$V_SLOT3_LBER_CPE2 = 73792,6,1,0 %; macro KA0302$V_SLOT3_LBER_CDPE = 73792,7,1,0 %; macro KA0302$V_SLOT3_LBER_CDPE2 = 73792,8,1,0 %; macro KA0302$V_SLOT3_LBER_TDE = 73792,9,1,0 %; macro KA0302$V_SLOT3_LBER_STE = 73792,10,1,0 %; macro KA0302$V_SLOT3_LBER_CNFE = 73792,11,1,0 %; macro KA0302$V_SLOT3_LBER_NXAE = 73792,12,1,0 %; macro KA0302$V_SLOT3_LBER_CAE = 73792,13,1,0 %; macro KA0302$V_SLOT3_LBER_SHE = 73792,14,1,0 %; macro KA0302$V_SLOT3_LBER_DIE = 73792,15,1,0 %; macro KA0302$V_SLOT3_LBER_DTCE = 73792,16,1,0 %; macro KA0302$V_SLOT3_LBER_CTCE = 73792,17,1,0 %; macro KA0302$V_SLOT3_LBER_NSES = 73792,18,1,0 %; macro KA0302$b_fill1270 = 73796,0,0,0 %; literal KA0302$s_fill1270 = 60; macro KA0302$L_SLOT3_LCNR = 73856,0,32,0 %; macro KA0302$V_SLOT3_LCNR_CEEN = 73856,0,1,0 %; macro KA0302$V_SLOT3_LCNR_RSTSTAT = 73856,28,1,0 %; macro KA0302$V_SLOT3_LCNR_NHALT = 73856,29,1,0 %; macro KA0302$V_SLOT3_LCNR_NRST = 73856,30,1,0 %; macro KA0302$V_SLOT3_LCNR_STF = 73856,31,1,0 %; macro KA0302$b_fill275 = 73860,0,0,0 %; literal KA0302$s_fill275 = 60; macro KA0302$L_SLOT3_IBR = 73920,0,32,0 %; macro KA0302$V_SLOT3_IBR_RCV_SDAT = 73920,0,1,0 %; macro KA0302$V_SLOT3_IBR_XMT_SDAT = 73920,1,1,0 %; macro KA0302$V_SLOT3_IBR_SCLK = 73920,2,1,0 %; macro KA0302$b_fill1280 = 73924,0,0,0 %; literal KA0302$s_fill1280 = 316; macro KA0302$L_SLOT3_LMMR0 = 74240,0,32,0 %; macro KA0302$V_SLOT3_LMMR0_EN = 74240,0,1,0 %; macro KA0302$V_SLOT3_LMMR0_INT = 74240,1,2,0 %; literal KA0302$S_SLOT3_LMMR0_INT = 2; macro KA0302$V_SLOT3_LMMR0_IA = 74240,3,2,0 %; literal KA0302$S_SLOT3_LMMR0_IA = 2; macro KA0302$V_SLOT3_LMMR0_AW = 74240,5,4,0 %; literal KA0302$S_SLOT3_LMMR0_AW = 4; macro KA0302$V_SLOT3_LMMR0_NBANKS = 74240,9,2,0 %; literal KA0302$S_SLOT3_LMMR0_NBANKS = 2; macro KA0302$V_SLOT3_LMMR0_ADDR = 74240,17,15,0 %; literal KA0302$S_SLOT3_LMMR0_ADDR = 15; macro KA0302$b_fill1290 = 74244,0,0,0 %; literal KA0302$s_fill1290 = 60; macro KA0302$L_SLOT3_LMMR1 = 74304,0,32,0 %; macro KA0302$V_SLOT3_LMMR1_EN = 74304,0,1,0 %; macro KA0302$V_SLOT3_LMMR1_INT = 74304,1,2,0 %; literal KA0302$S_SLOT3_LMMR1_INT = 2; macro KA0302$V_SLOT3_LMMR1_IA = 74304,3,2,0 %; literal KA0302$S_SLOT3_LMMR1_IA = 2; macro KA0302$V_SLOT3_LMMR1_AW = 74304,5,4,0 %; literal KA0302$S_SLOT3_LMMR1_AW = 4; macro KA0302$V_SLOT3_LMMR1_NBANKS = 74304,9,2,0 %; literal KA0302$S_SLOT3_LMMR1_NBANKS = 2; macro KA0302$V_SLOT3_LMMR1_ADDR = 74304,17,15,0 %; literal KA0302$S_SLOT3_LMMR1_ADDR = 15; macro KA0302$b_fill1300 = 74308,0,0,0 %; literal KA0302$s_fill1300 = 60; macro KA0302$L_SLOT3_LMMR2 = 74368,0,32,0 %; macro KA0302$V_SLOT3_LMMR2_EN = 74368,0,1,0 %; macro KA0302$V_SLOT3_LMMR2_INT = 74368,1,2,0 %; literal KA0302$S_SLOT3_LMMR2_INT = 2; macro KA0302$V_SLOT3_LMMR2_IA = 74368,3,2,0 %; literal KA0302$S_SLOT3_LMMR2_IA = 2; macro KA0302$V_SLOT3_LMMR2_AW = 74368,5,4,0 %; literal KA0302$S_SLOT3_LMMR2_AW = 4; macro KA0302$V_SLOT3_LMMR2_NBANKS = 74368,9,2,0 %; literal KA0302$S_SLOT3_LMMR2_NBANKS = 2; macro KA0302$V_SLOT3_LMMR2_ADDR = 74368,17,15,0 %; literal KA0302$S_SLOT3_LMMR2_ADDR = 15; macro KA0302$b_fill1310 = 74372,0,0,0 %; literal KA0302$s_fill1310 = 60; macro KA0302$L_SLOT3_LMMR3 = 74432,0,32,0 %; macro KA0302$V_SLOT3_LMMR3_EN = 74432,0,1,0 %; macro KA0302$V_SLOT3_LMMR3_INT = 74432,1,2,0 %; literal KA0302$S_SLOT3_LMMR3_INT = 2; macro KA0302$V_SLOT3_LMMR3_IA = 74432,3,2,0 %; literal KA0302$S_SLOT3_LMMR3_IA = 2; macro KA0302$V_SLOT3_LMMR3_AW = 74432,5,4,0 %; literal KA0302$S_SLOT3_LMMR3_AW = 4; macro KA0302$V_SLOT3_LMMR3_NBANKS = 74432,9,2,0 %; literal KA0302$S_SLOT3_LMMR3_NBANKS = 2; macro KA0302$V_SLOT3_LMMR3_ADDR = 74432,17,15,0 %; literal KA0302$S_SLOT3_LMMR3_ADDR = 15; macro KA0302$b_fill1320 = 74436,0,0,0 %; literal KA0302$s_fill1320 = 60; macro KA0302$L_SLOT3_LMMR4 = 74496,0,32,0 %; macro KA0302$V_SLOT3_LMMR4_EN = 74496,0,1,0 %; macro KA0302$V_SLOT3_LMMR4_INT = 74496,1,2,0 %; literal KA0302$S_SLOT3_LMMR4_INT = 2; macro KA0302$V_SLOT3_LMMR4_IA = 74496,3,2,0 %; literal KA0302$S_SLOT3_LMMR4_IA = 2; macro KA0302$V_SLOT3_LMMR4_AW = 74496,5,4,0 %; literal KA0302$S_SLOT3_LMMR4_AW = 4; macro KA0302$V_SLOT3_LMMR4_NBANKS = 74496,9,2,0 %; literal KA0302$S_SLOT3_LMMR4_NBANKS = 2; macro KA0302$V_SLOT3_LMMR4_ADDR = 74496,17,15,0 %; literal KA0302$S_SLOT3_LMMR4_ADDR = 15; macro KA0302$b_fill1330 = 74500,0,0,0 %; literal KA0302$s_fill1330 = 60; macro KA0302$L_SLOT3_LMMR5 = 74560,0,32,0 %; macro KA0302$V_SLOT3_LMMR5_EN = 74560,0,1,0 %; macro KA0302$V_SLOT3_LMMR5_INT = 74560,1,2,0 %; literal KA0302$S_SLOT3_LMMR5_INT = 2; macro KA0302$V_SLOT3_LMMR5_IA = 74560,3,2,0 %; literal KA0302$S_SLOT3_LMMR5_IA = 2; macro KA0302$V_SLOT3_LMMR5_AW = 74560,5,4,0 %; literal KA0302$S_SLOT3_LMMR5_AW = 4; macro KA0302$V_SLOT3_LMMR5_NBANKS = 74560,9,2,0 %; literal KA0302$S_SLOT3_LMMR5_NBANKS = 2; macro KA0302$V_SLOT3_LMMR5_ADDR = 74560,17,15,0 %; literal KA0302$S_SLOT3_LMMR5_ADDR = 15; macro KA0302$b_fill1340 = 74564,0,0,0 %; literal KA0302$s_fill1340 = 60; macro KA0302$L_SLOT3_LMMR6 = 74624,0,32,0 %; macro KA0302$V_SLOT3_LMMR6_EN = 74624,0,1,0 %; macro KA0302$V_SLOT3_LMMR6_INT = 74624,1,2,0 %; literal KA0302$S_SLOT3_LMMR6_INT = 2; macro KA0302$V_SLOT3_LMMR6_IA = 74624,3,2,0 %; literal KA0302$S_SLOT3_LMMR6_IA = 2; macro KA0302$V_SLOT3_LMMR6_AW = 74624,5,4,0 %; literal KA0302$S_SLOT3_LMMR6_AW = 4; macro KA0302$V_SLOT3_LMMR6_NBANKS = 74624,9,2,0 %; literal KA0302$S_SLOT3_LMMR6_NBANKS = 2; macro KA0302$V_SLOT3_LMMR6_ADDR = 74624,17,15,0 %; literal KA0302$S_SLOT3_LMMR6_ADDR = 15; macro KA0302$b_fill1350 = 74628,0,0,0 %; literal KA0302$s_fill1350 = 60; macro KA0302$L_SLOT3_LMMR7 = 74688,0,32,0 %; macro KA0302$V_SLOT3_LMMR7_EN = 74688,0,1,0 %; macro KA0302$V_SLOT3_LMMR7_INT = 74688,1,2,0 %; literal KA0302$S_SLOT3_LMMR7_INT = 2; macro KA0302$V_SLOT3_LMMR7_IA = 74688,3,2,0 %; literal KA0302$S_SLOT3_LMMR7_IA = 2; macro KA0302$V_SLOT3_LMMR7_AW = 74688,5,4,0 %; literal KA0302$S_SLOT3_LMMR7_AW = 4; macro KA0302$V_SLOT3_LMMR7_NBANKS = 74688,9,2,0 %; literal KA0302$S_SLOT3_LMMR7_NBANKS = 2; macro KA0302$V_SLOT3_LMMR7_ADDR = 74688,17,15,0 %; literal KA0302$S_SLOT3_LMMR7_ADDR = 15; macro KA0302$b_fill1360 = 74692,0,0,0 %; literal KA0302$s_fill1360 = 572; macro KA0302$L_SLOT3_LBESR0 = 75264,0,32,0 %; macro KA0302$V_SLOT3_LBESR0_SYNDROME = 75264,0,7,0 %; literal KA0302$S_SLOT3_LBESR0_SYNDROME = 7; macro KA0302$b_fill1370 = 75268,0,0,0 %; literal KA0302$s_fill1370 = 60; macro KA0302$L_SLOT3_LBESR1 = 75328,0,32,0 %; macro KA0302$V_SLOT3_LBESR1_SYNDROME = 75328,0,7,0 %; literal KA0302$S_SLOT3_LBESR1_SYNDROME = 7; macro KA0302$b_fill1380 = 75332,0,0,0 %; literal KA0302$s_fill1380 = 60; macro KA0302$L_SLOT3_LBESR2 = 75392,0,32,0 %; macro KA0302$V_SLOT3_LBESR2_SYNDROME = 75392,0,7,0 %; literal KA0302$S_SLOT3_LBESR2_SYNDROME = 7; macro KA0302$b_fill1390 = 75396,0,0,0 %; literal KA0302$s_fill1390 = 60; macro KA0302$L_SLOT3_LBESR3 = 75456,0,32,0 %; macro KA0302$V_SLOT3_LBESR3_SYNDROME = 75456,0,7,0 %; literal KA0302$S_SLOT3_LBESR3_SYNDROME = 7; macro KA0302$b_fill1400 = 75460,0,0,0 %; literal KA0302$s_fill1400 = 60; macro KA0302$L_SLOT3_LBECR0 = 75520,0,32,0 %; macro KA0302$L_SLOT3_LBECR0_CA = 75520,0,32,0 %; macro KA0302$b_fill1410 = 75524,0,0,0 %; literal KA0302$s_fill1410 = 60; macro KA0302$L_SLOT3_LBECR1 = 75584,0,32,0 %; macro KA0302$V_SLOT3_LBECR1_CA = 75584,0,7,0 %; literal KA0302$S_SLOT3_LBECR1_CA = 7; macro KA0302$V_SLOT3_LBECR1_CID = 75584,7,4,0 %; literal KA0302$S_SLOT3_LBECR1_CID = 4; macro KA0302$V_SLOT3_LBECR1_RID = 75584,11,4,0 %; literal KA0302$S_SLOT3_LBECR1_RID = 4; macro KA0302$V_SLOT3_LBECR1_CNF = 75584,15,1,0 %; macro KA0302$V_SLOT3_LBECR1_SHARED = 75584,16,1,0 %; macro KA0302$V_SLOT3_LBECR1_DIRTY = 75584,17,1,0 %; macro KA0302$V_SLOT3_LBECR1_DCYCLE = 75584,18,2,0 %; literal KA0302$S_SLOT3_LBECR1_DCYCLE = 2; macro KA0302$b_fill1420 = 75588,0,0,0 %; literal KA0302$s_fill1420 = 1212; macro KA0302$L_SLOT3_LMODE = 76800,0,32,0 %; macro KA0302$b_fill1430 = 76804,0,0,0 %; literal KA0302$s_fill1430 = 60; macro KA0302$L_SLOT3_LMERR = 76864,0,32,0 %; macro KA0302$b_fill1440 = 76868,0,0,0 %; literal KA0302$s_fill1440 = 60; macro KA0302$L_SLOT3_LLOCK = 76928,0,32,0 %; macro KA0302$b_fill1450 = 76932,0,0,0 %; literal KA0302$s_fill1450 = 60; macro KA0302$L_SLOT3_LEDTO = 76992,0,32,0 %; macro KA0302$b_fill1460 = 76996,0,0,0 %; literal KA0302$s_fill1460 = 60; macro KA0302$L_SLOT3_LDIAG = 77056,0,32,0 %; macro KA0302$b_fill1470 = 77060,0,0,0 %; literal KA0302$s_fill1470 = 60; macro KA0302$L_SLOT3_LTAGA = 77120,0,32,0 %; macro KA0302$b_fill1480 = 77124,0,0,0 %; literal KA0302$s_fill1480 = 60; macro KA0302$L_SLOT3_LTAGW = 77184,0,32,0 %; macro KA0302$b_fill1490 = 77188,0,0,0 %; literal KA0302$s_fill1490 = 124; macro KA0302$L_SLOT3_LCON0 = 77312,0,32,0 %; macro KA0302$b_fill1500 = 77316,0,0,0 %; literal KA0302$s_fill1500 = 60; macro KA0302$L_SLOT3_LCON1 = 77376,0,32,0 %; macro KA0302$b_fill1510 = 77380,0,0,0 %; literal KA0302$s_fill1510 = 188; macro KA0302$L_SLOT3_LPERF = 77568,0,32,0 %; macro KA0302$b_fill1520 = 77572,0,0,0 %; literal KA0302$s_fill1520 = 60; macro KA0302$L_SLOT3_LCNTR0 = 77632,0,32,0 %; macro KA0302$b_fill1530 = 77636,0,0,0 %; literal KA0302$s_fill1530 = 60; macro KA0302$L_SLOT3_LCNTR1 = 77696,0,32,0 %; macro KA0302$b_fill1540 = 77700,0,0,0 %; literal KA0302$s_fill1540 = 60; macro KA0302$L_SLOT3_LMISSADDR = 77760,0,32,0 %; macro KA0302$b_fill1545 = 77764,0,0,0 %; literal KA0302$s_fill1545 = 4156; macro KA0302$L_SLOT3_MCR = 81920,0,32,0 %; macro KA0302$b_fill1550 = 81924,0,0,0 %; literal KA0302$s_fill1550 = 60; macro KA0302$L_SLOT3_AMR = 81984,0,32,0 %; macro KA0302$b_fill1560 = 81988,0,0,0 %; literal KA0302$s_fill1560 = 60; macro KA0302$L_SLOT3_MSTR0 = 82048,0,32,0 %; macro KA0302$b_fill1570 = 82052,0,0,0 %; literal KA0302$s_fill1570 = 60; macro KA0302$L_SLOT3_MSTR1 = 82112,0,32,0 %; macro KA0302$b_fill1580 = 82116,0,0,0 %; literal KA0302$s_fill1580 = 60; macro KA0302$L_SLOT3_FADR = 82176,0,32,0 %; macro KA0302$b_fill1590 = 82180,0,0,0 %; literal KA0302$s_fill1590 = 60; macro KA0302$L_SLOT3_MERA = 82240,0,32,0 %; macro KA0302$b_fill1600 = 82244,0,0,0 %; literal KA0302$s_fill1600 = 60; macro KA0302$L_SLOT3_MSYNDA = 82304,0,32,0 %; macro KA0302$b_fill1610 = 82308,0,0,0 %; literal KA0302$s_fill1610 = 60; macro KA0302$L_SLOT3_MDRA = 82368,0,32,0 %; macro KA0302$b_fill1620 = 82372,0,0,0 %; literal KA0302$s_fill1620 = 60; macro KA0302$L_SLOT3_MCBSA = 82432,0,32,0 %; macro KA0302$b_fill1630 = 82436,0,0,0 %; literal KA0302$s_fill1630 = 7996; macro KA0302$L_SLOT3_MERB = 90432,0,32,0 %; macro KA0302$b_fill1640 = 90436,0,0,0 %; literal KA0302$s_fill1640 = 60; macro KA0302$L_SLOT3_MSYNDB = 90496,0,32,0 %; macro KA0302$b_fill1650 = 90500,0,0,0 %; literal KA0302$s_fill1650 = 60; macro KA0302$L_SLOT3_MDRB = 90560,0,32,0 %; macro KA0302$b_fill1660 = 90564,0,0,0 %; literal KA0302$s_fill1660 = 60; macro KA0302$L_SLOT3_MCBSB = 90624,0,32,0 %; macro KA0302$b_fill1670 = 90628,0,0,0 %; literal KA0302$s_fill1670 = 7676; macro KA0302$L_SLOT4_LDEV = 98304,0,32,0 %; macro KA0302$V_SLOT4_LDEV_DTYPE = 98304,0,16,0 %; literal KA0302$S_SLOT4_LDEV_DTYPE = 16; macro KA0302$V_SLOT4_LDEV_DREV = 98304,16,16,0 %; literal KA0302$S_SLOT4_LDEV_DREV = 16; macro KA0302$b_fill1680 = 98308,0,0,0 %; literal KA0302$s_fill1680 = 60; macro KA0302$L_SLOT4_LBER = 98368,0,32,0 %; macro KA0302$V_SLOT4_LBER_E = 98368,0,1,0 %; macro KA0302$V_SLOT4_LBER_UCE = 98368,1,1,0 %; macro KA0302$V_SLOT4_LBER_UCE2 = 98368,2,1,0 %; macro KA0302$V_SLOT4_LBER_CE = 98368,3,1,0 %; macro KA0302$V_SLOT4_LBER_CE2 = 98368,4,1,0 %; macro KA0302$V_SLOT4_LBER_CPE = 98368,5,1,0 %; macro KA0302$V_SLOT4_LBER_CPE2 = 98368,6,1,0 %; macro KA0302$V_SLOT4_LBER_CDPE = 98368,7,1,0 %; macro KA0302$V_SLOT4_LBER_CDPE2 = 98368,8,1,0 %; macro KA0302$V_SLOT4_LBER_TDE = 98368,9,1,0 %; macro KA0302$V_SLOT4_LBER_STE = 98368,10,1,0 %; macro KA0302$V_SLOT4_LBER_CNFE = 98368,11,1,0 %; macro KA0302$V_SLOT4_LBER_NXAE = 98368,12,1,0 %; macro KA0302$V_SLOT4_LBER_CAE = 98368,13,1,0 %; macro KA0302$V_SLOT4_LBER_SHE = 98368,14,1,0 %; macro KA0302$V_SLOT4_LBER_DIE = 98368,15,1,0 %; macro KA0302$V_SLOT4_LBER_DTCE = 98368,16,1,0 %; macro KA0302$V_SLOT4_LBER_CTCE = 98368,17,1,0 %; macro KA0302$V_SLOT4_LBER_NSES = 98368,18,1,0 %; macro KA0302$b_fill1690 = 98372,0,0,0 %; literal KA0302$s_fill1690 = 60; macro KA0302$L_SLOT4_LCNR = 98432,0,32,0 %; macro KA0302$V_SLOT4_LCNR_CEEN = 98432,0,1,0 %; macro KA0302$V_SLOT4_LCNR_RSTSTAT = 98432,28,1,0 %; macro KA0302$V_SLOT4_LCNR_NHALT = 98432,29,1,0 %; macro KA0302$V_SLOT4_LCNR_NRST = 98432,30,1,0 %; macro KA0302$V_SLOT4_LCNR_STF = 98432,31,1,0 %; macro KA0302$b_fill1695 = 98436,0,0,0 %; literal KA0302$s_fill1695 = 60; macro KA0302$L_SLOT4_IBR = 98496,0,32,0 %; macro KA0302$V_SLOT4_IBR_RCV_SDAT = 98496,0,1,0 %; macro KA0302$V_SLOT4_IBR_XMT_SDAT = 98496,1,1,0 %; macro KA0302$V_SLOT4_IBR_SCLK = 98496,2,1,0 %; macro KA0302$b_fill1700 = 98500,0,0,0 %; literal KA0302$s_fill1700 = 316; macro KA0302$L_SLOT4_LMMR0 = 98816,0,32,0 %; macro KA0302$V_SLOT4_LMMR0_EN = 98816,0,1,0 %; macro KA0302$V_SLOT4_LMMR0_INT = 98816,1,2,0 %; literal KA0302$S_SLOT4_LMMR0_INT = 2; macro KA0302$V_SLOT4_LMMR0_IA = 98816,3,2,0 %; literal KA0302$S_SLOT4_LMMR0_IA = 2; macro KA0302$V_SLOT4_LMMR0_AW = 98816,5,4,0 %; literal KA0302$S_SLOT4_LMMR0_AW = 4; macro KA0302$V_SLOT4_LMMR0_NBANKS = 98816,9,2,0 %; literal KA0302$S_SLOT4_LMMR0_NBANKS = 2; macro KA0302$V_SLOT4_LMMR0_ADDR = 98816,17,15,0 %; literal KA0302$S_SLOT4_LMMR0_ADDR = 15; macro KA0302$b_fill1710 = 98820,0,0,0 %; literal KA0302$s_fill1710 = 60; macro KA0302$L_SLOT4_LMMR1 = 98880,0,32,0 %; macro KA0302$V_SLOT4_LMMR1_EN = 98880,0,1,0 %; macro KA0302$V_SLOT4_LMMR1_INT = 98880,1,2,0 %; literal KA0302$S_SLOT4_LMMR1_INT = 2; macro KA0302$V_SLOT4_LMMR1_IA = 98880,3,2,0 %; literal KA0302$S_SLOT4_LMMR1_IA = 2; macro KA0302$V_SLOT4_LMMR1_AW = 98880,5,4,0 %; literal KA0302$S_SLOT4_LMMR1_AW = 4; macro KA0302$V_SLOT4_LMMR1_NBANKS = 98880,9,2,0 %; literal KA0302$S_SLOT4_LMMR1_NBANKS = 2; macro KA0302$V_SLOT4_LMMR1_ADDR = 98880,17,15,0 %; literal KA0302$S_SLOT4_LMMR1_ADDR = 15; macro KA0302$b_fill1720 = 98884,0,0,0 %; literal KA0302$s_fill1720 = 60; macro KA0302$L_SLOT4_LMMR2 = 98944,0,32,0 %; macro KA0302$V_SLOT4_LMMR2_EN = 98944,0,1,0 %; macro KA0302$V_SLOT4_LMMR2_INT = 98944,1,2,0 %; literal KA0302$S_SLOT4_LMMR2_INT = 2; macro KA0302$V_SLOT4_LMMR2_IA = 98944,3,2,0 %; literal KA0302$S_SLOT4_LMMR2_IA = 2; macro KA0302$V_SLOT4_LMMR2_AW = 98944,5,4,0 %; literal KA0302$S_SLOT4_LMMR2_AW = 4; macro KA0302$V_SLOT4_LMMR2_NBANKS = 98944,9,2,0 %; literal KA0302$S_SLOT4_LMMR2_NBANKS = 2; macro KA0302$V_SLOT4_LMMR2_ADDR = 98944,17,15,0 %; literal KA0302$S_SLOT4_LMMR2_ADDR = 15; macro KA0302$b_fill1730 = 98948,0,0,0 %; literal KA0302$s_fill1730 = 60; macro KA0302$L_SLOT4_LMMR3 = 99008,0,32,0 %; macro KA0302$V_SLOT4_LMMR3_EN = 99008,0,1,0 %; macro KA0302$V_SLOT4_LMMR3_INT = 99008,1,2,0 %; literal KA0302$S_SLOT4_LMMR3_INT = 2; macro KA0302$V_SLOT4_LMMR3_IA = 99008,3,2,0 %; literal KA0302$S_SLOT4_LMMR3_IA = 2; macro KA0302$V_SLOT4_LMMR3_AW = 99008,5,4,0 %; literal KA0302$S_SLOT4_LMMR3_AW = 4; macro KA0302$V_SLOT4_LMMR3_NBANKS = 99008,9,2,0 %; literal KA0302$S_SLOT4_LMMR3_NBANKS = 2; macro KA0302$V_SLOT4_LMMR3_ADDR = 99008,17,15,0 %; literal KA0302$S_SLOT4_LMMR3_ADDR = 15; macro KA0302$b_fill1740 = 99012,0,0,0 %; literal KA0302$s_fill1740 = 60; macro KA0302$L_SLOT4_LMMR4 = 99072,0,32,0 %; macro KA0302$V_SLOT4_LMMR4_EN = 99072,0,1,0 %; macro KA0302$V_SLOT4_LMMR4_INT = 99072,1,2,0 %; literal KA0302$S_SLOT4_LMMR4_INT = 2; macro KA0302$V_SLOT4_LMMR4_IA = 99072,3,2,0 %; literal KA0302$S_SLOT4_LMMR4_IA = 2; macro KA0302$V_SLOT4_LMMR4_AW = 99072,5,4,0 %; literal KA0302$S_SLOT4_LMMR4_AW = 4; macro KA0302$V_SLOT4_LMMR4_NBANKS = 99072,9,2,0 %; literal KA0302$S_SLOT4_LMMR4_NBANKS = 2; macro KA0302$V_SLOT4_LMMR4_ADDR = 99072,17,15,0 %; literal KA0302$S_SLOT4_LMMR4_ADDR = 15; macro KA0302$b_fill1750 = 99076,0,0,0 %; literal KA0302$s_fill1750 = 60; macro KA0302$L_SLOT4_LMMR5 = 99136,0,32,0 %; macro KA0302$V_SLOT4_LMMR5_EN = 99136,0,1,0 %; macro KA0302$V_SLOT4_LMMR5_INT = 99136,1,2,0 %; literal KA0302$S_SLOT4_LMMR5_INT = 2; macro KA0302$V_SLOT4_LMMR5_IA = 99136,3,2,0 %; literal KA0302$S_SLOT4_LMMR5_IA = 2; macro KA0302$V_SLOT4_LMMR5_AW = 99136,5,4,0 %; literal KA0302$S_SLOT4_LMMR5_AW = 4; macro KA0302$V_SLOT4_LMMR5_NBANKS = 99136,9,2,0 %; literal KA0302$S_SLOT4_LMMR5_NBANKS = 2; macro KA0302$V_SLOT4_LMMR5_ADDR = 99136,17,15,0 %; literal KA0302$S_SLOT4_LMMR5_ADDR = 15; macro KA0302$b_fill1760 = 99140,0,0,0 %; literal KA0302$s_fill1760 = 60; macro KA0302$L_SLOT4_LMMR6 = 99200,0,32,0 %; macro KA0302$V_SLOT4_LMMR6_EN = 99200,0,1,0 %; macro KA0302$V_SLOT4_LMMR6_INT = 99200,1,2,0 %; literal KA0302$S_SLOT4_LMMR6_INT = 2; macro KA0302$V_SLOT4_LMMR6_IA = 99200,3,2,0 %; literal KA0302$S_SLOT4_LMMR6_IA = 2; macro KA0302$V_SLOT4_LMMR6_AW = 99200,5,4,0 %; literal KA0302$S_SLOT4_LMMR6_AW = 4; macro KA0302$V_SLOT4_LMMR6_NBANKS = 99200,9,2,0 %; literal KA0302$S_SLOT4_LMMR6_NBANKS = 2; macro KA0302$V_SLOT4_LMMR6_ADDR = 99200,17,15,0 %; literal KA0302$S_SLOT4_LMMR6_ADDR = 15; macro KA0302$b_fill1770 = 99204,0,0,0 %; literal KA0302$s_fill1770 = 60; macro KA0302$L_SLOT4_LMMR7 = 99264,0,32,0 %; macro KA0302$V_SLOT4_LMMR7_EN = 99264,0,1,0 %; macro KA0302$V_SLOT4_LMMR7_INT = 99264,1,2,0 %; literal KA0302$S_SLOT4_LMMR7_INT = 2; macro KA0302$V_SLOT4_LMMR7_IA = 99264,3,2,0 %; literal KA0302$S_SLOT4_LMMR7_IA = 2; macro KA0302$V_SLOT4_LMMR7_AW = 99264,5,4,0 %; literal KA0302$S_SLOT4_LMMR7_AW = 4; macro KA0302$V_SLOT4_LMMR7_NBANKS = 99264,9,2,0 %; literal KA0302$S_SLOT4_LMMR7_NBANKS = 2; macro KA0302$V_SLOT4_LMMR7_ADDR = 99264,17,15,0 %; literal KA0302$S_SLOT4_LMMR7_ADDR = 15; macro KA0302$b_fill1780 = 99268,0,0,0 %; literal KA0302$s_fill1780 = 572; macro KA0302$L_SLOT4_LBESR0 = 99840,0,32,0 %; macro KA0302$V_SLOT4_LBESR0_SYNDROME = 99840,0,7,0 %; literal KA0302$S_SLOT4_LBESR0_SYNDROME = 7; macro KA0302$b_fill1790 = 99844,0,0,0 %; literal KA0302$s_fill1790 = 60; macro KA0302$L_SLOT4_LBESR1 = 99904,0,32,0 %; macro KA0302$V_SLOT4_LBESR1_SYNDROME = 99904,0,7,0 %; literal KA0302$S_SLOT4_LBESR1_SYNDROME = 7; macro KA0302$b_fill1800 = 99908,0,0,0 %; literal KA0302$s_fill1800 = 60; macro KA0302$L_SLOT4_LBESR2 = 99968,0,32,0 %; macro KA0302$V_SLOT4_LBESR2_SYNDROME = 99968,0,7,0 %; literal KA0302$S_SLOT4_LBESR2_SYNDROME = 7; macro KA0302$b_fill1810 = 99972,0,0,0 %; literal KA0302$s_fill1810 = 60; macro KA0302$L_SLOT4_LBESR3 = 100032,0,32,0 %; macro KA0302$V_SLOT4_LBESR3_SYNDROME = 100032,0,7,0 %; literal KA0302$S_SLOT4_LBESR3_SYNDROME = 7; macro KA0302$b_fill1820 = 100036,0,0,0 %; literal KA0302$s_fill1820 = 60; macro KA0302$L_SLOT4_LBECR0 = 100096,0,32,0 %; macro KA0302$L_SLOT4_LBECR0_CA = 100096,0,32,0 %; macro KA0302$b_fill1830 = 100100,0,0,0 %; literal KA0302$s_fill1830 = 60; macro KA0302$L_SLOT4_LBECR1 = 100160,0,32,0 %; macro KA0302$V_SLOT4_LBECR1_CA = 100160,0,7,0 %; literal KA0302$S_SLOT4_LBECR1_CA = 7; macro KA0302$V_SLOT4_LBECR1_CID = 100160,7,4,0 %; literal KA0302$S_SLOT4_LBECR1_CID = 4; macro KA0302$V_SLOT4_LBECR1_RID = 100160,11,4,0 %; literal KA0302$S_SLOT4_LBECR1_RID = 4; macro KA0302$V_SLOT4_LBECR1_CNF = 100160,15,1,0 %; macro KA0302$V_SLOT4_LBECR1_SHARED = 100160,16,1,0 %; macro KA0302$V_SLOT4_LBECR1_DIRTY = 100160,17,1,0 %; macro KA0302$V_SLOT4_LBECR1_DCYCLE = 100160,18,2,0 %; literal KA0302$S_SLOT4_LBECR1_DCYCLE = 2; macro KA0302$b_fill1840 = 100164,0,0,0 %; literal KA0302$s_fill1840 = 1212; macro KA0302$L_SLOT4_LMODE = 101376,0,32,0 %; macro KA0302$b_fill1850 = 101380,0,0,0 %; literal KA0302$s_fill1850 = 60; macro KA0302$L_SLOT4_LMERR = 101440,0,32,0 %; macro KA0302$b_fill1860 = 101444,0,0,0 %; literal KA0302$s_fill1860 = 60; macro KA0302$L_SLOT4_LLOCK = 101504,0,32,0 %; macro KA0302$b_fill1870 = 101508,0,0,0 %; literal KA0302$s_fill1870 = 60; macro KA0302$L_SLOT4_LEDTO = 101568,0,32,0 %; macro KA0302$b_fill1880 = 101572,0,0,0 %; literal KA0302$s_fill1880 = 60; macro KA0302$L_SLOT4_LDIAG = 101632,0,32,0 %; macro KA0302$b_fill1890 = 101636,0,0,0 %; literal KA0302$s_fill1890 = 60; macro KA0302$L_SLOT4_LTAGA = 101696,0,32,0 %; macro KA0302$b_fill1900 = 101700,0,0,0 %; literal KA0302$s_fill1900 = 60; macro KA0302$L_SLOT4_LTAGW = 101760,0,32,0 %; macro KA0302$b_fill1910 = 101764,0,0,0 %; literal KA0302$s_fill1910 = 124; macro KA0302$L_SLOT4_LCON0 = 101888,0,32,0 %; macro KA0302$b_fill1920 = 101892,0,0,0 %; literal KA0302$s_fill1920 = 60; macro KA0302$L_SLOT4_LCON1 = 101952,0,32,0 %; macro KA0302$b_fill1930 = 101956,0,0,0 %; literal KA0302$s_fill1930 = 188; macro KA0302$L_SLOT4_LPERF = 102144,0,32,0 %; macro KA0302$b_fill1940 = 102148,0,0,0 %; literal KA0302$s_fill1940 = 60; macro KA0302$L_SLOT4_LCNTR0 = 102208,0,32,0 %; macro KA0302$b_fill1950 = 102212,0,0,0 %; literal KA0302$s_fill1950 = 60; macro KA0302$L_SLOT4_LCNTR1 = 102272,0,32,0 %; macro KA0302$b_fill1960 = 102276,0,0,0 %; literal KA0302$s_fill1960 = 60; macro KA0302$L_SLOT4_LMISSADDR = 102336,0,32,0 %; macro KA0302$b_fill1965 = 102340,0,0,0 %; literal KA0302$s_fill1965 = 4156; macro KA0302$L_SLOT4_MCR = 106496,0,32,0 %; macro KA0302$b_fill1970 = 106500,0,0,0 %; literal KA0302$s_fill1970 = 60; macro KA0302$L_SLOT4_AMR = 106560,0,32,0 %; macro KA0302$b_fill1980 = 106564,0,0,0 %; literal KA0302$s_fill1980 = 60; macro KA0302$L_SLOT4_MSTR0 = 106624,0,32,0 %; macro KA0302$b_fill1990 = 106628,0,0,0 %; literal KA0302$s_fill1990 = 60; macro KA0302$L_SLOT4_MSTR1 = 106688,0,32,0 %; macro KA0302$b_fill2000 = 106692,0,0,0 %; literal KA0302$s_fill2000 = 60; macro KA0302$L_SLOT4_FADR = 106752,0,32,0 %; macro KA0302$b_fill2010 = 106756,0,0,0 %; literal KA0302$s_fill2010 = 60; macro KA0302$L_SLOT4_MERA = 106816,0,32,0 %; macro KA0302$b_fill2020 = 106820,0,0,0 %; literal KA0302$s_fill2020 = 60; macro KA0302$L_SLOT4_MSYNDA = 106880,0,32,0 %; macro KA0302$b_fill2030 = 106884,0,0,0 %; literal KA0302$s_fill2030 = 60; macro KA0302$L_SLOT4_MDRA = 106944,0,32,0 %; macro KA0302$b_fill2040 = 106948,0,0,0 %; literal KA0302$s_fill2040 = 60; macro KA0302$L_SLOT4_MCBSA = 107008,0,32,0 %; macro KA0302$b_fill2050 = 107012,0,0,0 %; literal KA0302$s_fill2050 = 7996; macro KA0302$L_SLOT4_MERB = 115008,0,32,0 %; macro KA0302$b_fill2060 = 115012,0,0,0 %; literal KA0302$s_fill2060 = 60; macro KA0302$L_SLOT4_MSYNDB = 115072,0,32,0 %; macro KA0302$b_fill2070 = 115076,0,0,0 %; literal KA0302$s_fill2070 = 60; macro KA0302$L_SLOT4_MDRB = 115136,0,32,0 %; macro KA0302$b_fill2080 = 115140,0,0,0 %; literal KA0302$s_fill2080 = 60; macro KA0302$L_SLOT4_MCBSB = 115200,0,32,0 %; macro KA0302$b_fill2090 = 115204,0,0,0 %; literal KA0302$s_fill2090 = 7676; macro KA0302$L_SLOT5_LDEV = 122880,0,32,0 %; macro KA0302$V_SLOT5_LDEV_DTYPE = 122880,0,16,0 %; literal KA0302$S_SLOT5_LDEV_DTYPE = 16; macro KA0302$V_SLOT5_LDEV_DREV = 122880,16,16,0 %; literal KA0302$S_SLOT5_LDEV_DREV = 16; macro KA0302$b_fill2100 = 122884,0,0,0 %; literal KA0302$s_fill2100 = 60; macro KA0302$L_SLOT5_LBER = 122944,0,32,0 %; macro KA0302$V_SLOT5_LBER_E = 122944,0,1,0 %; macro KA0302$V_SLOT5_LBER_UCE = 122944,1,1,0 %; macro KA0302$V_SLOT5_LBER_UCE2 = 122944,2,1,0 %; macro KA0302$V_SLOT5_LBER_CE = 122944,3,1,0 %; macro KA0302$V_SLOT5_LBER_CE2 = 122944,4,1,0 %; macro KA0302$V_SLOT5_LBER_CPE = 122944,5,1,0 %; macro KA0302$V_SLOT5_LBER_CPE2 = 122944,6,1,0 %; macro KA0302$V_SLOT5_LBER_CDPE = 122944,7,1,0 %; macro KA0302$V_SLOT5_LBER_CDPE2 = 122944,8,1,0 %; macro KA0302$V_SLOT5_LBER_TDE = 122944,9,1,0 %; macro KA0302$V_SLOT5_LBER_STE = 122944,10,1,0 %; macro KA0302$V_SLOT5_LBER_CNFE = 122944,11,1,0 %; macro KA0302$V_SLOT5_LBER_NXAE = 122944,12,1,0 %; macro KA0302$V_SLOT5_LBER_CAE = 122944,13,1,0 %; macro KA0302$V_SLOT5_LBER_SHE = 122944,14,1,0 %; macro KA0302$V_SLOT5_LBER_DIE = 122944,15,1,0 %; macro KA0302$V_SLOT5_LBER_DTCE = 122944,16,1,0 %; macro KA0302$V_SLOT5_LBER_CTCE = 122944,17,1,0 %; macro KA0302$V_SLOT5_LBER_NSES = 122944,18,1,0 %; macro KA0302$b_fill2110 = 122948,0,0,0 %; literal KA0302$s_fill2110 = 60; macro KA0302$L_SLOT5_LCNR = 123008,0,32,0 %; macro KA0302$V_SLOT5_LCNR_CEEN = 123008,0,1,0 %; macro KA0302$V_SLOT5_LCNR_RSTSTAT = 123008,28,1,0 %; macro KA0302$V_SLOT5_LCNR_NHALT = 123008,29,1,0 %; macro KA0302$V_SLOT5_LCNR_NRST = 123008,30,1,0 %; macro KA0302$V_SLOT5_LCNR_STF = 123008,31,1,0 %; macro KA0302$b_fill2115 = 123012,0,0,0 %; literal KA0302$s_fill2115 = 60; macro KA0302$L_SLOT5_IBR = 123072,0,32,0 %; macro KA0302$V_SLOT5_IBR_RCV_SDAT = 123072,0,1,0 %; macro KA0302$V_SLOT5_IBR_XMT_SDAT = 123072,1,1,0 %; macro KA0302$V_SLOT5_IBR_SCLK = 123072,2,1,0 %; macro KA0302$b_fill2120 = 123076,0,0,0 %; literal KA0302$s_fill2120 = 316; macro KA0302$L_SLOT5_LMMR0 = 123392,0,32,0 %; macro KA0302$V_SLOT5_LMMR0_EN = 123392,0,1,0 %; macro KA0302$V_SLOT5_LMMR0_INT = 123392,1,2,0 %; literal KA0302$S_SLOT5_LMMR0_INT = 2; macro KA0302$V_SLOT5_LMMR0_IA = 123392,3,2,0 %; literal KA0302$S_SLOT5_LMMR0_IA = 2; macro KA0302$V_SLOT5_LMMR0_AW = 123392,5,4,0 %; literal KA0302$S_SLOT5_LMMR0_AW = 4; macro KA0302$V_SLOT5_LMMR0_NBANKS = 123392,9,2,0 %; literal KA0302$S_SLOT5_LMMR0_NBANKS = 2; macro KA0302$V_SLOT5_LMMR0_ADDR = 123392,17,15,0 %; literal KA0302$S_SLOT5_LMMR0_ADDR = 15; macro KA0302$b_fill2130 = 123396,0,0,0 %; literal KA0302$s_fill2130 = 60; macro KA0302$L_SLOT5_LMMR1 = 123456,0,32,0 %; macro KA0302$V_SLOT5_LMMR1_EN = 123456,0,1,0 %; macro KA0302$V_SLOT5_LMMR1_INT = 123456,1,2,0 %; literal KA0302$S_SLOT5_LMMR1_INT = 2; macro KA0302$V_SLOT5_LMMR1_IA = 123456,3,2,0 %; literal KA0302$S_SLOT5_LMMR1_IA = 2; macro KA0302$V_SLOT5_LMMR1_AW = 123456,5,4,0 %; literal KA0302$S_SLOT5_LMMR1_AW = 4; macro KA0302$V_SLOT5_LMMR1_NBANKS = 123456,9,2,0 %; literal KA0302$S_SLOT5_LMMR1_NBANKS = 2; macro KA0302$V_SLOT5_LMMR1_ADDR = 123456,17,15,0 %; literal KA0302$S_SLOT5_LMMR1_ADDR = 15; macro KA0302$b_fill2140 = 123460,0,0,0 %; literal KA0302$s_fill2140 = 60; macro KA0302$L_SLOT5_LMMR2 = 123520,0,32,0 %; macro KA0302$V_SLOT5_LMMR2_EN = 123520,0,1,0 %; macro KA0302$V_SLOT5_LMMR2_INT = 123520,1,2,0 %; literal KA0302$S_SLOT5_LMMR2_INT = 2; macro KA0302$V_SLOT5_LMMR2_IA = 123520,3,2,0 %; literal KA0302$S_SLOT5_LMMR2_IA = 2; macro KA0302$V_SLOT5_LMMR2_AW = 123520,5,4,0 %; literal KA0302$S_SLOT5_LMMR2_AW = 4; macro KA0302$V_SLOT5_LMMR2_NBANKS = 123520,9,2,0 %; literal KA0302$S_SLOT5_LMMR2_NBANKS = 2; macro KA0302$V_SLOT5_LMMR2_ADDR = 123520,17,15,0 %; literal KA0302$S_SLOT5_LMMR2_ADDR = 15; macro KA0302$b_fill2150 = 123524,0,0,0 %; literal KA0302$s_fill2150 = 60; macro KA0302$L_SLOT5_LMMR3 = 123584,0,32,0 %; macro KA0302$V_SLOT5_LMMR3_EN = 123584,0,1,0 %; macro KA0302$V_SLOT5_LMMR3_INT = 123584,1,2,0 %; literal KA0302$S_SLOT5_LMMR3_INT = 2; macro KA0302$V_SLOT5_LMMR3_IA = 123584,3,2,0 %; literal KA0302$S_SLOT5_LMMR3_IA = 2; macro KA0302$V_SLOT5_LMMR3_AW = 123584,5,4,0 %; literal KA0302$S_SLOT5_LMMR3_AW = 4; macro KA0302$V_SLOT5_LMMR3_NBANKS = 123584,9,2,0 %; literal KA0302$S_SLOT5_LMMR3_NBANKS = 2; macro KA0302$V_SLOT5_LMMR3_ADDR = 123584,17,15,0 %; literal KA0302$S_SLOT5_LMMR3_ADDR = 15; macro KA0302$b_fill2160 = 123588,0,0,0 %; literal KA0302$s_fill2160 = 60; macro KA0302$L_SLOT5_LMMR4 = 123648,0,32,0 %; macro KA0302$V_SLOT5_LMMR4_EN = 123648,0,1,0 %; macro KA0302$V_SLOT5_LMMR4_INT = 123648,1,2,0 %; literal KA0302$S_SLOT5_LMMR4_INT = 2; macro KA0302$V_SLOT5_LMMR4_IA = 123648,3,2,0 %; literal KA0302$S_SLOT5_LMMR4_IA = 2; macro KA0302$V_SLOT5_LMMR4_AW = 123648,5,4,0 %; literal KA0302$S_SLOT5_LMMR4_AW = 4; macro KA0302$V_SLOT5_LMMR4_NBANKS = 123648,9,2,0 %; literal KA0302$S_SLOT5_LMMR4_NBANKS = 2; macro KA0302$V_SLOT5_LMMR4_ADDR = 123648,17,15,0 %; literal KA0302$S_SLOT5_LMMR4_ADDR = 15; macro KA0302$b_fill2170 = 123652,0,0,0 %; literal KA0302$s_fill2170 = 60; macro KA0302$L_SLOT5_LMMR5 = 123712,0,32,0 %; macro KA0302$V_SLOT5_LMMR5_EN = 123712,0,1,0 %; macro KA0302$V_SLOT5_LMMR5_INT = 123712,1,2,0 %; literal KA0302$S_SLOT5_LMMR5_INT = 2; macro KA0302$V_SLOT5_LMMR5_IA = 123712,3,2,0 %; literal KA0302$S_SLOT5_LMMR5_IA = 2; macro KA0302$V_SLOT5_LMMR5_AW = 123712,5,4,0 %; literal KA0302$S_SLOT5_LMMR5_AW = 4; macro KA0302$V_SLOT5_LMMR5_NBANKS = 123712,9,2,0 %; literal KA0302$S_SLOT5_LMMR5_NBANKS = 2; macro KA0302$V_SLOT5_LMMR5_ADDR = 123712,17,15,0 %; literal KA0302$S_SLOT5_LMMR5_ADDR = 15; macro KA0302$b_fill2180 = 123716,0,0,0 %; literal KA0302$s_fill2180 = 60; macro KA0302$L_SLOT5_LMMR6 = 123776,0,32,0 %; macro KA0302$V_SLOT5_LMMR6_EN = 123776,0,1,0 %; macro KA0302$V_SLOT5_LMMR6_INT = 123776,1,2,0 %; literal KA0302$S_SLOT5_LMMR6_INT = 2; macro KA0302$V_SLOT5_LMMR6_IA = 123776,3,2,0 %; literal KA0302$S_SLOT5_LMMR6_IA = 2; macro KA0302$V_SLOT5_LMMR6_AW = 123776,5,4,0 %; literal KA0302$S_SLOT5_LMMR6_AW = 4; macro KA0302$V_SLOT5_LMMR6_NBANKS = 123776,9,2,0 %; literal KA0302$S_SLOT5_LMMR6_NBANKS = 2; macro KA0302$V_SLOT5_LMMR6_ADDR = 123776,17,15,0 %; literal KA0302$S_SLOT5_LMMR6_ADDR = 15; macro KA0302$b_fill2190 = 123780,0,0,0 %; literal KA0302$s_fill2190 = 60; macro KA0302$L_SLOT5_LMMR7 = 123840,0,32,0 %; macro KA0302$V_SLOT5_LMMR7_EN = 123840,0,1,0 %; macro KA0302$V_SLOT5_LMMR7_INT = 123840,1,2,0 %; literal KA0302$S_SLOT5_LMMR7_INT = 2; macro KA0302$V_SLOT5_LMMR7_IA = 123840,3,2,0 %; literal KA0302$S_SLOT5_LMMR7_IA = 2; macro KA0302$V_SLOT5_LMMR7_AW = 123840,5,4,0 %; literal KA0302$S_SLOT5_LMMR7_AW = 4; macro KA0302$V_SLOT5_LMMR7_NBANKS = 123840,9,2,0 %; literal KA0302$S_SLOT5_LMMR7_NBANKS = 2; macro KA0302$V_SLOT5_LMMR7_ADDR = 123840,17,15,0 %; literal KA0302$S_SLOT5_LMMR7_ADDR = 15; macro KA0302$b_fill2200 = 123844,0,0,0 %; literal KA0302$s_fill2200 = 572; macro KA0302$L_SLOT5_LBESR0 = 124416,0,32,0 %; macro KA0302$V_SLOT5_LBESR0_SYNDROME = 124416,0,7,0 %; literal KA0302$S_SLOT5_LBESR0_SYNDROME = 7; macro KA0302$b_fill2210 = 124420,0,0,0 %; literal KA0302$s_fill2210 = 60; macro KA0302$L_SLOT5_LBESR1 = 124480,0,32,0 %; macro KA0302$V_SLOT5_LBESR1_SYNDROME = 124480,0,7,0 %; literal KA0302$S_SLOT5_LBESR1_SYNDROME = 7; macro KA0302$b_fill2220 = 124484,0,0,0 %; literal KA0302$s_fill2220 = 60; macro KA0302$L_SLOT5_LBESR2 = 124544,0,32,0 %; macro KA0302$V_SLOT5_LBESR2_SYNDROME = 124544,0,7,0 %; literal KA0302$S_SLOT5_LBESR2_SYNDROME = 7; macro KA0302$b_fill2230 = 124548,0,0,0 %; literal KA0302$s_fill2230 = 60; macro KA0302$L_SLOT5_LBESR3 = 124608,0,32,0 %; macro KA0302$V_SLOT5_LBESR3_SYNDROME = 124608,0,7,0 %; literal KA0302$S_SLOT5_LBESR3_SYNDROME = 7; macro KA0302$b_fill2240 = 124612,0,0,0 %; literal KA0302$s_fill2240 = 60; macro KA0302$L_SLOT5_LBECR0 = 124672,0,32,0 %; macro KA0302$L_SLOT5_LBECR0_CA = 124672,0,32,0 %; macro KA0302$b_fill2250 = 124676,0,0,0 %; literal KA0302$s_fill2250 = 60; macro KA0302$L_SLOT5_LBECR1 = 124736,0,32,0 %; macro KA0302$V_SLOT5_LBECR1_CA = 124736,0,7,0 %; literal KA0302$S_SLOT5_LBECR1_CA = 7; macro KA0302$V_SLOT5_LBECR1_CID = 124736,7,4,0 %; literal KA0302$S_SLOT5_LBECR1_CID = 4; macro KA0302$V_SLOT5_LBECR1_RID = 124736,11,4,0 %; literal KA0302$S_SLOT5_LBECR1_RID = 4; macro KA0302$V_SLOT5_LBECR1_CNF = 124736,15,1,0 %; macro KA0302$V_SLOT5_LBECR1_SHARED = 124736,16,1,0 %; macro KA0302$V_SLOT5_LBECR1_DIRTY = 124736,17,1,0 %; macro KA0302$V_SLOT5_LBECR1_DCYCLE = 124736,18,2,0 %; literal KA0302$S_SLOT5_LBECR1_DCYCLE = 2; macro KA0302$b_fill2260 = 124740,0,0,0 %; literal KA0302$s_fill2260 = 1212; macro KA0302$L_SLOT5_LMODE = 125952,0,32,0 %; macro KA0302$b_fill2270 = 125956,0,0,0 %; literal KA0302$s_fill2270 = 60; macro KA0302$L_SLOT5_LMERR = 126016,0,32,0 %; macro KA0302$b_fill2280 = 126020,0,0,0 %; literal KA0302$s_fill2280 = 60; macro KA0302$L_SLOT5_LLOCK = 126080,0,32,0 %; macro KA0302$b_fill2290 = 126084,0,0,0 %; literal KA0302$s_fill2290 = 60; macro KA0302$L_SLOT5_LEDTO = 126144,0,32,0 %; macro KA0302$b_fill2300 = 126148,0,0,0 %; literal KA0302$s_fill2300 = 60; macro KA0302$L_SLOT5_LDIAG = 126208,0,32,0 %; macro KA0302$b_fill2310 = 126212,0,0,0 %; literal KA0302$s_fill2310 = 60; macro KA0302$L_SLOT5_LTAGA = 126272,0,32,0 %; macro KA0302$b_fill2320 = 126276,0,0,0 %; literal KA0302$s_fill2320 = 60; macro KA0302$L_SLOT5_LTAGW = 126336,0,32,0 %; macro KA0302$b_fill2330 = 126340,0,0,0 %; literal KA0302$s_fill2330 = 124; macro KA0302$L_SLOT5_LCON0 = 126464,0,32,0 %; macro KA0302$b_fill2340 = 126468,0,0,0 %; literal KA0302$s_fill2340 = 60; macro KA0302$L_SLOT5_LCON1 = 126528,0,32,0 %; macro KA0302$b_fill2350 = 126532,0,0,0 %; literal KA0302$s_fill2350 = 188; macro KA0302$L_SLOT5_LPERF = 126720,0,32,0 %; macro KA0302$b_fill2360 = 126724,0,0,0 %; literal KA0302$s_fill2360 = 60; macro KA0302$L_SLOT5_LCNTR0 = 126784,0,32,0 %; macro KA0302$b_fill2370 = 126788,0,0,0 %; literal KA0302$s_fill2370 = 60; macro KA0302$L_SLOT5_LCNTR1 = 126848,0,32,0 %; macro KA0302$b_fill2380 = 126852,0,0,0 %; literal KA0302$s_fill2380 = 60; macro KA0302$L_SLOT5_LMISSADDR = 126912,0,32,0 %; macro KA0302$b_fill2385 = 126916,0,0,0 %; literal KA0302$s_fill2385 = 4156; macro KA0302$L_SLOT5_MCR = 131072,0,32,0 %; macro KA0302$b_fill2390 = 131076,0,0,0 %; literal KA0302$s_fill2390 = 60; macro KA0302$L_SLOT5_AMR = 131136,0,32,0 %; macro KA0302$b_fill2400 = 131140,0,0,0 %; literal KA0302$s_fill2400 = 60; macro KA0302$L_SLOT5_MSTR0 = 131200,0,32,0 %; macro KA0302$b_fill2410 = 131204,0,0,0 %; literal KA0302$s_fill2410 = 60; macro KA0302$L_SLOT5_MSTR1 = 131264,0,32,0 %; macro KA0302$b_fill2420 = 131268,0,0,0 %; literal KA0302$s_fill2420 = 60; macro KA0302$L_SLOT5_FADR = 131328,0,32,0 %; macro KA0302$b_fill2430 = 131332,0,0,0 %; literal KA0302$s_fill2430 = 60; macro KA0302$L_SLOT5_MERA = 131392,0,32,0 %; macro KA0302$b_fill2440 = 131396,0,0,0 %; literal KA0302$s_fill2440 = 60; macro KA0302$L_SLOT5_MSYNDA = 131456,0,32,0 %; macro KA0302$b_fill2450 = 131460,0,0,0 %; literal KA0302$s_fill2450 = 60; macro KA0302$L_SLOT5_MDRA = 131520,0,32,0 %; macro KA0302$b_fill2460 = 131524,0,0,0 %; literal KA0302$s_fill2460 = 60; macro KA0302$L_SLOT5_MCBSA = 131584,0,32,0 %; macro KA0302$b_fill2470 = 131588,0,0,0 %; literal KA0302$s_fill2470 = 7996; macro KA0302$L_SLOT5_MERB = 139584,0,32,0 %; macro KA0302$b_fill2480 = 139588,0,0,0 %; literal KA0302$s_fill2480 = 60; macro KA0302$L_SLOT5_MSYNDB = 139648,0,32,0 %; macro KA0302$b_fill2490 = 139652,0,0,0 %; literal KA0302$s_fill2490 = 60; macro KA0302$L_SLOT5_MDRB = 139712,0,32,0 %; macro KA0302$b_fill2500 = 139716,0,0,0 %; literal KA0302$s_fill2500 = 60; macro KA0302$L_SLOT5_MCBSB = 139776,0,32,0 %; macro KA0302$b_fill2510 = 139780,0,0,0 %; literal KA0302$s_fill2510 = 7676; macro KA0302$L_SLOT6_LDEV = 147456,0,32,0 %; macro KA0302$V_SLOT6_LDEV_DTYPE = 147456,0,16,0 %; literal KA0302$S_SLOT6_LDEV_DTYPE = 16; macro KA0302$V_SLOT6_LDEV_DREV = 147456,16,16,0 %; literal KA0302$S_SLOT6_LDEV_DREV = 16; macro KA0302$b_fill2520 = 147460,0,0,0 %; literal KA0302$s_fill2520 = 60; macro KA0302$L_SLOT6_LBER = 147520,0,32,0 %; macro KA0302$V_SLOT6_LBER_E = 147520,0,1,0 %; macro KA0302$V_SLOT6_LBER_UCE = 147520,1,1,0 %; macro KA0302$V_SLOT6_LBER_UCE2 = 147520,2,1,0 %; macro KA0302$V_SLOT6_LBER_CE = 147520,3,1,0 %; macro KA0302$V_SLOT6_LBER_CE2 = 147520,4,1,0 %; macro KA0302$V_SLOT6_LBER_CPE = 147520,5,1,0 %; macro KA0302$V_SLOT6_LBER_CPE2 = 147520,6,1,0 %; macro KA0302$V_SLOT6_LBER_CDPE = 147520,7,1,0 %; macro KA0302$V_SLOT6_LBER_CDPE2 = 147520,8,1,0 %; macro KA0302$V_SLOT6_LBER_TDE = 147520,9,1,0 %; macro KA0302$V_SLOT6_LBER_STE = 147520,10,1,0 %; macro KA0302$V_SLOT6_LBER_CNFE = 147520,11,1,0 %; macro KA0302$V_SLOT6_LBER_NXAE = 147520,12,1,0 %; macro KA0302$V_SLOT6_LBER_CAE = 147520,13,1,0 %; macro KA0302$V_SLOT6_LBER_SHE = 147520,14,1,0 %; macro KA0302$V_SLOT6_LBER_DIE = 147520,15,1,0 %; macro KA0302$V_SLOT6_LBER_DTCE = 147520,16,1,0 %; macro KA0302$V_SLOT6_LBER_CTCE = 147520,17,1,0 %; macro KA0302$V_SLOT6_LBER_NSES = 147520,18,1,0 %; macro KA0302$b_fill2530 = 147524,0,0,0 %; literal KA0302$s_fill2530 = 60; macro KA0302$L_SLOT6_LCNR = 147584,0,32,0 %; macro KA0302$V_SLOT6_LCNR_CEEN = 147584,0,1,0 %; macro KA0302$V_SLOT6_LCNR_RSTSTAT = 147584,28,1,0 %; macro KA0302$V_SLOT6_LCNR_NHALT = 147584,29,1,0 %; macro KA0302$V_SLOT6_LCNR_NRST = 147584,30,1,0 %; macro KA0302$V_SLOT6_LCNR_STF = 147584,31,1,0 %; macro KA0302$b_fill2535 = 147588,0,0,0 %; literal KA0302$s_fill2535 = 60; macro KA0302$L_SLOT6_IBR = 147648,0,32,0 %; macro KA0302$V_SLOT6_IBR_RCV_SDAT = 147648,0,1,0 %; macro KA0302$V_SLOT6_IBR_XMT_SDAT = 147648,1,1,0 %; macro KA0302$V_SLOT6_IBR_SCLK = 147648,2,1,0 %; macro KA0302$b_fill2540 = 147652,0,0,0 %; literal KA0302$s_fill2540 = 316; macro KA0302$L_SLOT6_LMMR0 = 147968,0,32,0 %; macro KA0302$V_SLOT6_LMMR0_EN = 147968,0,1,0 %; macro KA0302$V_SLOT6_LMMR0_INT = 147968,1,2,0 %; literal KA0302$S_SLOT6_LMMR0_INT = 2; macro KA0302$V_SLOT6_LMMR0_IA = 147968,3,2,0 %; literal KA0302$S_SLOT6_LMMR0_IA = 2; macro KA0302$V_SLOT6_LMMR0_AW = 147968,5,4,0 %; literal KA0302$S_SLOT6_LMMR0_AW = 4; macro KA0302$V_SLOT6_LMMR0_NBANKS = 147968,9,2,0 %; literal KA0302$S_SLOT6_LMMR0_NBANKS = 2; macro KA0302$V_SLOT6_LMMR0_ADDR = 147968,17,15,0 %; literal KA0302$S_SLOT6_LMMR0_ADDR = 15; macro KA0302$b_fill2550 = 147972,0,0,0 %; literal KA0302$s_fill2550 = 60; macro KA0302$L_SLOT6_LMMR1 = 148032,0,32,0 %; macro KA0302$V_SLOT6_LMMR1_EN = 148032,0,1,0 %; macro KA0302$V_SLOT6_LMMR1_INT = 148032,1,2,0 %; literal KA0302$S_SLOT6_LMMR1_INT = 2; macro KA0302$V_SLOT6_LMMR1_IA = 148032,3,2,0 %; literal KA0302$S_SLOT6_LMMR1_IA = 2; macro KA0302$V_SLOT6_LMMR1_AW = 148032,5,4,0 %; literal KA0302$S_SLOT6_LMMR1_AW = 4; macro KA0302$V_SLOT6_LMMR1_NBANKS = 148032,9,2,0 %; literal KA0302$S_SLOT6_LMMR1_NBANKS = 2; macro KA0302$V_SLOT6_LMMR1_ADDR = 148032,17,15,0 %; literal KA0302$S_SLOT6_LMMR1_ADDR = 15; macro KA0302$b_fill2560 = 148036,0,0,0 %; literal KA0302$s_fill2560 = 60; macro KA0302$L_SLOT6_LMMR2 = 148096,0,32,0 %; macro KA0302$V_SLOT6_LMMR2_EN = 148096,0,1,0 %; macro KA0302$V_SLOT6_LMMR2_INT = 148096,1,2,0 %; literal KA0302$S_SLOT6_LMMR2_INT = 2; macro KA0302$V_SLOT6_LMMR2_IA = 148096,3,2,0 %; literal KA0302$S_SLOT6_LMMR2_IA = 2; macro KA0302$V_SLOT6_LMMR2_AW = 148096,5,4,0 %; literal KA0302$S_SLOT6_LMMR2_AW = 4; macro KA0302$V_SLOT6_LMMR2_NBANKS = 148096,9,2,0 %; literal KA0302$S_SLOT6_LMMR2_NBANKS = 2; macro KA0302$V_SLOT6_LMMR2_ADDR = 148096,17,15,0 %; literal KA0302$S_SLOT6_LMMR2_ADDR = 15; macro KA0302$b_fill2570 = 148100,0,0,0 %; literal KA0302$s_fill2570 = 60; macro KA0302$L_SLOT6_LMMR3 = 148160,0,32,0 %; macro KA0302$V_SLOT6_LMMR3_EN = 148160,0,1,0 %; macro KA0302$V_SLOT6_LMMR3_INT = 148160,1,2,0 %; literal KA0302$S_SLOT6_LMMR3_INT = 2; macro KA0302$V_SLOT6_LMMR3_IA = 148160,3,2,0 %; literal KA0302$S_SLOT6_LMMR3_IA = 2; macro KA0302$V_SLOT6_LMMR3_AW = 148160,5,4,0 %; literal KA0302$S_SLOT6_LMMR3_AW = 4; macro KA0302$V_SLOT6_LMMR3_NBANKS = 148160,9,2,0 %; literal KA0302$S_SLOT6_LMMR3_NBANKS = 2; macro KA0302$V_SLOT6_LMMR3_ADDR = 148160,17,15,0 %; literal KA0302$S_SLOT6_LMMR3_ADDR = 15; macro KA0302$b_fill2580 = 148164,0,0,0 %; literal KA0302$s_fill2580 = 60; macro KA0302$L_SLOT6_LMMR4 = 148224,0,32,0 %; macro KA0302$V_SLOT6_LMMR4_EN = 148224,0,1,0 %; macro KA0302$V_SLOT6_LMMR4_INT = 148224,1,2,0 %; literal KA0302$S_SLOT6_LMMR4_INT = 2; macro KA0302$V_SLOT6_LMMR4_IA = 148224,3,2,0 %; literal KA0302$S_SLOT6_LMMR4_IA = 2; macro KA0302$V_SLOT6_LMMR4_AW = 148224,5,4,0 %; literal KA0302$S_SLOT6_LMMR4_AW = 4; macro KA0302$V_SLOT6_LMMR4_NBANKS = 148224,9,2,0 %; literal KA0302$S_SLOT6_LMMR4_NBANKS = 2; macro KA0302$V_SLOT6_LMMR4_ADDR = 148224,17,15,0 %; literal KA0302$S_SLOT6_LMMR4_ADDR = 15; macro KA0302$b_fill2590 = 148228,0,0,0 %; literal KA0302$s_fill2590 = 60; macro KA0302$L_SLOT6_LMMR5 = 148288,0,32,0 %; macro KA0302$V_SLOT6_LMMR5_EN = 148288,0,1,0 %; macro KA0302$V_SLOT6_LMMR5_INT = 148288,1,2,0 %; literal KA0302$S_SLOT6_LMMR5_INT = 2; macro KA0302$V_SLOT6_LMMR5_IA = 148288,3,2,0 %; literal KA0302$S_SLOT6_LMMR5_IA = 2; macro KA0302$V_SLOT6_LMMR5_AW = 148288,5,4,0 %; literal KA0302$S_SLOT6_LMMR5_AW = 4; macro KA0302$V_SLOT6_LMMR5_NBANKS = 148288,9,2,0 %; literal KA0302$S_SLOT6_LMMR5_NBANKS = 2; macro KA0302$V_SLOT6_LMMR5_ADDR = 148288,17,15,0 %; literal KA0302$S_SLOT6_LMMR5_ADDR = 15; macro KA0302$b_fill2600 = 148292,0,0,0 %; literal KA0302$s_fill2600 = 60; macro KA0302$L_SLOT6_LMMR6 = 148352,0,32,0 %; macro KA0302$V_SLOT6_LMMR6_EN = 148352,0,1,0 %; macro KA0302$V_SLOT6_LMMR6_INT = 148352,1,2,0 %; literal KA0302$S_SLOT6_LMMR6_INT = 2; macro KA0302$V_SLOT6_LMMR6_IA = 148352,3,2,0 %; literal KA0302$S_SLOT6_LMMR6_IA = 2; macro KA0302$V_SLOT6_LMMR6_AW = 148352,5,4,0 %; literal KA0302$S_SLOT6_LMMR6_AW = 4; macro KA0302$V_SLOT6_LMMR6_NBANKS = 148352,9,2,0 %; literal KA0302$S_SLOT6_LMMR6_NBANKS = 2; macro KA0302$V_SLOT6_LMMR6_ADDR = 148352,17,15,0 %; literal KA0302$S_SLOT6_LMMR6_ADDR = 15; macro KA0302$b_fill2610 = 148356,0,0,0 %; literal KA0302$s_fill2610 = 60; macro KA0302$L_SLOT6_LMMR7 = 148416,0,32,0 %; macro KA0302$V_SLOT6_LMMR7_EN = 148416,0,1,0 %; macro KA0302$V_SLOT6_LMMR7_INT = 148416,1,2,0 %; literal KA0302$S_SLOT6_LMMR7_INT = 2; macro KA0302$V_SLOT6_LMMR7_IA = 148416,3,2,0 %; literal KA0302$S_SLOT6_LMMR7_IA = 2; macro KA0302$V_SLOT6_LMMR7_AW = 148416,5,4,0 %; literal KA0302$S_SLOT6_LMMR7_AW = 4; macro KA0302$V_SLOT6_LMMR7_NBANKS = 148416,9,2,0 %; literal KA0302$S_SLOT6_LMMR7_NBANKS = 2; macro KA0302$V_SLOT6_LMMR7_ADDR = 148416,17,15,0 %; literal KA0302$S_SLOT6_LMMR7_ADDR = 15; macro KA0302$b_fill2620 = 148420,0,0,0 %; literal KA0302$s_fill2620 = 572; macro KA0302$L_SLOT6_LBESR0 = 148992,0,32,0 %; macro KA0302$V_SLOT6_LBESR0_SYNDROME = 148992,0,7,0 %; literal KA0302$S_SLOT6_LBESR0_SYNDROME = 7; macro KA0302$b_fill2630 = 148996,0,0,0 %; literal KA0302$s_fill2630 = 60; macro KA0302$L_SLOT6_LBESR1 = 149056,0,32,0 %; macro KA0302$V_SLOT6_LBESR1_SYNDROME = 149056,0,7,0 %; literal KA0302$S_SLOT6_LBESR1_SYNDROME = 7; macro KA0302$b_fill2640 = 149060,0,0,0 %; literal KA0302$s_fill2640 = 60; macro KA0302$L_SLOT6_LBESR2 = 149120,0,32,0 %; macro KA0302$V_SLOT6_LBESR2_SYNDROME = 149120,0,7,0 %; literal KA0302$S_SLOT6_LBESR2_SYNDROME = 7; macro KA0302$b_fill2650 = 149124,0,0,0 %; literal KA0302$s_fill2650 = 60; macro KA0302$L_SLOT6_LBESR3 = 149184,0,32,0 %; macro KA0302$V_SLOT6_LBESR3_SYNDROME = 149184,0,7,0 %; literal KA0302$S_SLOT6_LBESR3_SYNDROME = 7; macro KA0302$b_fill2660 = 149188,0,0,0 %; literal KA0302$s_fill2660 = 60; macro KA0302$L_SLOT6_LBECR0 = 149248,0,32,0 %; macro KA0302$L_SLOT6_LBECR0_CA = 149248,0,32,0 %; macro KA0302$b_fill2670 = 149252,0,0,0 %; literal KA0302$s_fill2670 = 60; macro KA0302$L_SLOT6_LBECR1 = 149312,0,32,0 %; macro KA0302$V_SLOT6_LBECR1_CA = 149312,0,7,0 %; literal KA0302$S_SLOT6_LBECR1_CA = 7; macro KA0302$V_SLOT6_LBECR1_CID = 149312,7,4,0 %; literal KA0302$S_SLOT6_LBECR1_CID = 4; macro KA0302$V_SLOT6_LBECR1_RID = 149312,11,4,0 %; literal KA0302$S_SLOT6_LBECR1_RID = 4; macro KA0302$V_SLOT6_LBECR1_CNF = 149312,15,1,0 %; macro KA0302$V_SLOT6_LBECR1_SHARED = 149312,16,1,0 %; macro KA0302$V_SLOT6_LBECR1_DIRTY = 149312,17,1,0 %; macro KA0302$V_SLOT6_LBECR1_DCYCLE = 149312,18,2,0 %; literal KA0302$S_SLOT6_LBECR1_DCYCLE = 2; macro KA0302$b_fill2680 = 149316,0,0,0 %; literal KA0302$s_fill2680 = 1212; macro KA0302$L_SLOT6_LMODE = 150528,0,32,0 %; macro KA0302$b_fill2690 = 150532,0,0,0 %; literal KA0302$s_fill2690 = 60; macro KA0302$L_SLOT6_LMERR = 150592,0,32,0 %; macro KA0302$b_fill2700 = 150596,0,0,0 %; literal KA0302$s_fill2700 = 60; macro KA0302$L_SLOT6_LLOCK = 150656,0,32,0 %; macro KA0302$b_fill2710 = 150660,0,0,0 %; literal KA0302$s_fill2710 = 60; macro KA0302$L_SLOT6_LEDTO = 150720,0,32,0 %; macro KA0302$b_fill2720 = 150724,0,0,0 %; literal KA0302$s_fill2720 = 60; macro KA0302$L_SLOT6_LDIAG = 150784,0,32,0 %; macro KA0302$b_fill2730 = 150788,0,0,0 %; literal KA0302$s_fill2730 = 60; macro KA0302$L_SLOT6_LTAGA = 150848,0,32,0 %; macro KA0302$b_fill2740 = 150852,0,0,0 %; literal KA0302$s_fill2740 = 60; macro KA0302$L_SLOT6_LTAGW = 150912,0,32,0 %; macro KA0302$b_fill2750 = 150916,0,0,0 %; literal KA0302$s_fill2750 = 124; macro KA0302$L_SLOT6_LCON0 = 151040,0,32,0 %; macro KA0302$b_fill2760 = 151044,0,0,0 %; literal KA0302$s_fill2760 = 60; macro KA0302$L_SLOT6_LCON1 = 151104,0,32,0 %; macro KA0302$b_fill2770 = 151108,0,0,0 %; literal KA0302$s_fill2770 = 188; macro KA0302$L_SLOT6_LPERF = 151296,0,32,0 %; macro KA0302$b_fill2780 = 151300,0,0,0 %; literal KA0302$s_fill2780 = 60; macro KA0302$L_SLOT6_LCNTR0 = 151360,0,32,0 %; macro KA0302$b_fill2790 = 151364,0,0,0 %; literal KA0302$s_fill2790 = 60; macro KA0302$L_SLOT6_LCNTR1 = 151424,0,32,0 %; macro KA0302$b_fill2800 = 151428,0,0,0 %; literal KA0302$s_fill2800 = 60; macro KA0302$L_SLOT6_LMISSADDR = 151488,0,32,0 %; macro KA0302$b_fill2805 = 151492,0,0,0 %; literal KA0302$s_fill2805 = 4156; macro KA0302$L_SLOT6_MCR = 155648,0,32,0 %; macro KA0302$b_fill2810 = 155652,0,0,0 %; literal KA0302$s_fill2810 = 60; macro KA0302$L_SLOT6_AMR = 155712,0,32,0 %; macro KA0302$b_fill2820 = 155716,0,0,0 %; literal KA0302$s_fill2820 = 60; macro KA0302$L_SLOT6_MSTR0 = 155776,0,32,0 %; macro KA0302$b_fill2830 = 155780,0,0,0 %; literal KA0302$s_fill2830 = 60; macro KA0302$L_SLOT6_MSTR1 = 155840,0,32,0 %; macro KA0302$b_fill2840 = 155844,0,0,0 %; literal KA0302$s_fill2840 = 60; macro KA0302$L_SLOT6_FADR = 155904,0,32,0 %; macro KA0302$b_fill2850 = 155908,0,0,0 %; literal KA0302$s_fill2850 = 60; macro KA0302$L_SLOT6_MERA = 155968,0,32,0 %; macro KA0302$b_fill2860 = 155972,0,0,0 %; literal KA0302$s_fill2860 = 60; macro KA0302$L_SLOT6_MSYNDA = 156032,0,32,0 %; macro KA0302$b_fill2870 = 156036,0,0,0 %; literal KA0302$s_fill2870 = 60; macro KA0302$L_SLOT6_MDRA = 156096,0,32,0 %; macro KA0302$b_fill2880 = 156100,0,0,0 %; literal KA0302$s_fill2880 = 60; macro KA0302$L_SLOT6_MCBSA = 156160,0,32,0 %; macro KA0302$b_fill2890 = 156164,0,0,0 %; literal KA0302$s_fill2890 = 7996; macro KA0302$L_SLOT6_MERB = 164160,0,32,0 %; macro KA0302$b_fill2900 = 164164,0,0,0 %; literal KA0302$s_fill2900 = 60; macro KA0302$L_SLOT6_MSYNDB = 164224,0,32,0 %; macro KA0302$b_fill2910 = 164228,0,0,0 %; literal KA0302$s_fill2910 = 60; macro KA0302$L_SLOT6_MDRB = 164288,0,32,0 %; macro KA0302$b_fill2920 = 164292,0,0,0 %; literal KA0302$s_fill2920 = 60; macro KA0302$L_SLOT6_MCBSB = 164352,0,32,0 %; macro KA0302$b_fill2930 = 164356,0,0,0 %; literal KA0302$s_fill2930 = 7676; macro KA0302$L_SLOT7_LDEV = 172032,0,32,0 %; macro KA0302$V_SLOT7_LDEV_DTYPE = 172032,0,16,0 %; literal KA0302$S_SLOT7_LDEV_DTYPE = 16; macro KA0302$V_SLOT7_LDEV_DREV = 172032,16,16,0 %; literal KA0302$S_SLOT7_LDEV_DREV = 16; macro KA0302$b_fill2940 = 172036,0,0,0 %; literal KA0302$s_fill2940 = 60; macro KA0302$L_SLOT7_LBER = 172096,0,32,0 %; macro KA0302$V_SLOT7_LBER_E = 172096,0,1,0 %; macro KA0302$V_SLOT7_LBER_UCE = 172096,1,1,0 %; macro KA0302$V_SLOT7_LBER_UCE2 = 172096,2,1,0 %; macro KA0302$V_SLOT7_LBER_CE = 172096,3,1,0 %; macro KA0302$V_SLOT7_LBER_CE2 = 172096,4,1,0 %; macro KA0302$V_SLOT7_LBER_CPE = 172096,5,1,0 %; macro KA0302$V_SLOT7_LBER_CPE2 = 172096,6,1,0 %; macro KA0302$V_SLOT7_LBER_CDPE = 172096,7,1,0 %; macro KA0302$V_SLOT7_LBER_CDPE2 = 172096,8,1,0 %; macro KA0302$V_SLOT7_LBER_TDE = 172096,9,1,0 %; macro KA0302$V_SLOT7_LBER_STE = 172096,10,1,0 %; macro KA0302$V_SLOT7_LBER_CNFE = 172096,11,1,0 %; macro KA0302$V_SLOT7_LBER_NXAE = 172096,12,1,0 %; macro KA0302$V_SLOT7_LBER_CAE = 172096,13,1,0 %; macro KA0302$V_SLOT7_LBER_SHE = 172096,14,1,0 %; macro KA0302$V_SLOT7_LBER_DIE = 172096,15,1,0 %; macro KA0302$V_SLOT7_LBER_DTCE = 172096,16,1,0 %; macro KA0302$V_SLOT7_LBER_CTCE = 172096,17,1,0 %; macro KA0302$V_SLOT7_LBER_NSES = 172096,18,1,0 %; macro KA0302$b_fill2950 = 172100,0,0,0 %; literal KA0302$s_fill2950 = 60; macro KA0302$L_SLOT7_LCNR = 172160,0,32,0 %; macro KA0302$V_SLOT7_LCNR_CEEN = 172160,0,1,0 %; macro KA0302$V_SLOT7_LCNR_RSTSTAT = 172160,28,1,0 %; macro KA0302$V_SLOT7_LCNR_NHALT = 172160,29,1,0 %; macro KA0302$V_SLOT7_LCNR_NRST = 172160,30,1,0 %; macro KA0302$V_SLOT7_LCNR_STF = 172160,31,1,0 %; macro KA0302$b_fill2955 = 172164,0,0,0 %; literal KA0302$s_fill2955 = 60; macro KA0302$L_SLOT7_IBR = 172224,0,32,0 %; macro KA0302$V_SLOT7_IBR_RCV_SDAT = 172224,0,1,0 %; macro KA0302$V_SLOT7_IBR_XMT_SDAT = 172224,1,1,0 %; macro KA0302$V_SLOT7_IBR_SCLK = 172224,2,1,0 %; macro KA0302$b_fill2960 = 172228,0,0,0 %; literal KA0302$s_fill2960 = 316; macro KA0302$L_SLOT7_LMMR0 = 172544,0,32,0 %; macro KA0302$V_SLOT7_LMMR0_EN = 172544,0,1,0 %; macro KA0302$V_SLOT7_LMMR0_INT = 172544,1,2,0 %; literal KA0302$S_SLOT7_LMMR0_INT = 2; macro KA0302$V_SLOT7_LMMR0_IA = 172544,3,2,0 %; literal KA0302$S_SLOT7_LMMR0_IA = 2; macro KA0302$V_SLOT7_LMMR0_AW = 172544,5,4,0 %; literal KA0302$S_SLOT7_LMMR0_AW = 4; macro KA0302$V_SLOT7_LMMR0_NBANKS = 172544,9,2,0 %; literal KA0302$S_SLOT7_LMMR0_NBANKS = 2; macro KA0302$V_SLOT7_LMMR0_ADDR = 172544,17,15,0 %; literal KA0302$S_SLOT7_LMMR0_ADDR = 15; macro KA0302$b_fill2970 = 172548,0,0,0 %; literal KA0302$s_fill2970 = 60; macro KA0302$L_SLOT7_LMMR1 = 172608,0,32,0 %; macro KA0302$V_SLOT7_LMMR1_EN = 172608,0,1,0 %; macro KA0302$V_SLOT7_LMMR1_INT = 172608,1,2,0 %; literal KA0302$S_SLOT7_LMMR1_INT = 2; macro KA0302$V_SLOT7_LMMR1_IA = 172608,3,2,0 %; literal KA0302$S_SLOT7_LMMR1_IA = 2; macro KA0302$V_SLOT7_LMMR1_AW = 172608,5,4,0 %; literal KA0302$S_SLOT7_LMMR1_AW = 4; macro KA0302$V_SLOT7_LMMR1_NBANKS = 172608,9,2,0 %; literal KA0302$S_SLOT7_LMMR1_NBANKS = 2; macro KA0302$V_SLOT7_LMMR1_ADDR = 172608,17,15,0 %; literal KA0302$S_SLOT7_LMMR1_ADDR = 15; macro KA0302$b_fill2980 = 172612,0,0,0 %; literal KA0302$s_fill2980 = 60; macro KA0302$L_SLOT7_LMMR2 = 172672,0,32,0 %; macro KA0302$V_SLOT7_LMMR2_EN = 172672,0,1,0 %; macro KA0302$V_SLOT7_LMMR2_INT = 172672,1,2,0 %; literal KA0302$S_SLOT7_LMMR2_INT = 2; macro KA0302$V_SLOT7_LMMR2_IA = 172672,3,2,0 %; literal KA0302$S_SLOT7_LMMR2_IA = 2; macro KA0302$V_SLOT7_LMMR2_AW = 172672,5,4,0 %; literal KA0302$S_SLOT7_LMMR2_AW = 4; macro KA0302$V_SLOT7_LMMR2_NBANKS = 172672,9,2,0 %; literal KA0302$S_SLOT7_LMMR2_NBANKS = 2; macro KA0302$V_SLOT7_LMMR2_ADDR = 172672,17,15,0 %; literal KA0302$S_SLOT7_LMMR2_ADDR = 15; macro KA0302$b_fill2990 = 172676,0,0,0 %; literal KA0302$s_fill2990 = 60; macro KA0302$L_SLOT7_LMMR3 = 172736,0,32,0 %; macro KA0302$V_SLOT7_LMMR3_EN = 172736,0,1,0 %; macro KA0302$V_SLOT7_LMMR3_INT = 172736,1,2,0 %; literal KA0302$S_SLOT7_LMMR3_INT = 2; macro KA0302$V_SLOT7_LMMR3_IA = 172736,3,2,0 %; literal KA0302$S_SLOT7_LMMR3_IA = 2; macro KA0302$V_SLOT7_LMMR3_AW = 172736,5,4,0 %; literal KA0302$S_SLOT7_LMMR3_AW = 4; macro KA0302$V_SLOT7_LMMR3_NBANKS = 172736,9,2,0 %; literal KA0302$S_SLOT7_LMMR3_NBANKS = 2; macro KA0302$V_SLOT7_LMMR3_ADDR = 172736,17,15,0 %; literal KA0302$S_SLOT7_LMMR3_ADDR = 15; macro KA0302$b_fill3000 = 172740,0,0,0 %; literal KA0302$s_fill3000 = 60; macro KA0302$L_SLOT7_LMMR4 = 172800,0,32,0 %; macro KA0302$V_SLOT7_LMMR4_EN = 172800,0,1,0 %; macro KA0302$V_SLOT7_LMMR4_INT = 172800,1,2,0 %; literal KA0302$S_SLOT7_LMMR4_INT = 2; macro KA0302$V_SLOT7_LMMR4_IA = 172800,3,2,0 %; literal KA0302$S_SLOT7_LMMR4_IA = 2; macro KA0302$V_SLOT7_LMMR4_AW = 172800,5,4,0 %; literal KA0302$S_SLOT7_LMMR4_AW = 4; macro KA0302$V_SLOT7_LMMR4_NBANKS = 172800,9,2,0 %; literal KA0302$S_SLOT7_LMMR4_NBANKS = 2; macro KA0302$V_SLOT7_LMMR4_ADDR = 172800,17,15,0 %; literal KA0302$S_SLOT7_LMMR4_ADDR = 15; macro KA0302$b_fill3010 = 172804,0,0,0 %; literal KA0302$s_fill3010 = 60; macro KA0302$L_SLOT7_LMMR5 = 172864,0,32,0 %; macro KA0302$V_SLOT7_LMMR5_EN = 172864,0,1,0 %; macro KA0302$V_SLOT7_LMMR5_INT = 172864,1,2,0 %; literal KA0302$S_SLOT7_LMMR5_INT = 2; macro KA0302$V_SLOT7_LMMR5_IA = 172864,3,2,0 %; literal KA0302$S_SLOT7_LMMR5_IA = 2; macro KA0302$V_SLOT7_LMMR5_AW = 172864,5,4,0 %; literal KA0302$S_SLOT7_LMMR5_AW = 4; macro KA0302$V_SLOT7_LMMR5_NBANKS = 172864,9,2,0 %; literal KA0302$S_SLOT7_LMMR5_NBANKS = 2; macro KA0302$V_SLOT7_LMMR5_ADDR = 172864,17,15,0 %; literal KA0302$S_SLOT7_LMMR5_ADDR = 15; macro KA0302$b_fill3020 = 172868,0,0,0 %; literal KA0302$s_fill3020 = 60; macro KA0302$L_SLOT7_LMMR6 = 172928,0,32,0 %; macro KA0302$V_SLOT7_LMMR6_EN = 172928,0,1,0 %; macro KA0302$V_SLOT7_LMMR6_INT = 172928,1,2,0 %; literal KA0302$S_SLOT7_LMMR6_INT = 2; macro KA0302$V_SLOT7_LMMR6_IA = 172928,3,2,0 %; literal KA0302$S_SLOT7_LMMR6_IA = 2; macro KA0302$V_SLOT7_LMMR6_AW = 172928,5,4,0 %; literal KA0302$S_SLOT7_LMMR6_AW = 4; macro KA0302$V_SLOT7_LMMR6_NBANKS = 172928,9,2,0 %; literal KA0302$S_SLOT7_LMMR6_NBANKS = 2; macro KA0302$V_SLOT7_LMMR6_ADDR = 172928,17,15,0 %; literal KA0302$S_SLOT7_LMMR6_ADDR = 15; macro KA0302$b_fill3030 = 172932,0,0,0 %; literal KA0302$s_fill3030 = 60; macro KA0302$L_SLOT7_LMMR7 = 172992,0,32,0 %; macro KA0302$V_SLOT7_LMMR7_EN = 172992,0,1,0 %; macro KA0302$V_SLOT7_LMMR7_INT = 172992,1,2,0 %; literal KA0302$S_SLOT7_LMMR7_INT = 2; macro KA0302$V_SLOT7_LMMR7_IA = 172992,3,2,0 %; literal KA0302$S_SLOT7_LMMR7_IA = 2; macro KA0302$V_SLOT7_LMMR7_AW = 172992,5,4,0 %; literal KA0302$S_SLOT7_LMMR7_AW = 4; macro KA0302$V_SLOT7_LMMR7_NBANKS = 172992,9,2,0 %; literal KA0302$S_SLOT7_LMMR7_NBANKS = 2; macro KA0302$V_SLOT7_LMMR7_ADDR = 172992,17,15,0 %; literal KA0302$S_SLOT7_LMMR7_ADDR = 15; macro KA0302$b_fill3040 = 172996,0,0,0 %; literal KA0302$s_fill3040 = 572; macro KA0302$L_SLOT7_LBESR0 = 173568,0,32,0 %; macro KA0302$V_SLOT7_LBESR0_SYNDROME = 173568,0,7,0 %; literal KA0302$S_SLOT7_LBESR0_SYNDROME = 7; macro KA0302$b_fill3050 = 173572,0,0,0 %; literal KA0302$s_fill3050 = 60; macro KA0302$L_SLOT7_LBESR1 = 173632,0,32,0 %; macro KA0302$V_SLOT7_LBESR1_SYNDROME = 173632,0,7,0 %; literal KA0302$S_SLOT7_LBESR1_SYNDROME = 7; macro KA0302$b_fill3060 = 173636,0,0,0 %; literal KA0302$s_fill3060 = 60; macro KA0302$L_SLOT7_LBESR2 = 173696,0,32,0 %; macro KA0302$V_SLOT7_LBESR2_SYNDROME = 173696,0,7,0 %; literal KA0302$S_SLOT7_LBESR2_SYNDROME = 7; macro KA0302$b_fill3070 = 173700,0,0,0 %; literal KA0302$s_fill3070 = 60; macro KA0302$L_SLOT7_LBESR3 = 173760,0,32,0 %; macro KA0302$V_SLOT7_LBESR3_SYNDROME = 173760,0,7,0 %; literal KA0302$S_SLOT7_LBESR3_SYNDROME = 7; macro KA0302$b_fill3080 = 173764,0,0,0 %; literal KA0302$s_fill3080 = 60; macro KA0302$L_SLOT7_LBECR0 = 173824,0,32,0 %; macro KA0302$L_SLOT7_LBECR0_CA = 173824,0,32,0 %; macro KA0302$b_fill3090 = 173828,0,0,0 %; literal KA0302$s_fill3090 = 60; macro KA0302$L_SLOT7_LBECR1 = 173888,0,32,0 %; macro KA0302$V_SLOT7_LBECR1_CA = 173888,0,7,0 %; literal KA0302$S_SLOT7_LBECR1_CA = 7; macro KA0302$V_SLOT7_LBECR1_CID = 173888,7,4,0 %; literal KA0302$S_SLOT7_LBECR1_CID = 4; macro KA0302$V_SLOT7_LBECR1_RID = 173888,11,4,0 %; literal KA0302$S_SLOT7_LBECR1_RID = 4; macro KA0302$V_SLOT7_LBECR1_CNF = 173888,15,1,0 %; macro KA0302$V_SLOT7_LBECR1_SHARED = 173888,16,1,0 %; macro KA0302$V_SLOT7_LBECR1_DIRTY = 173888,17,1,0 %; macro KA0302$V_SLOT7_LBECR1_DCYCLE = 173888,18,2,0 %; literal KA0302$S_SLOT7_LBECR1_DCYCLE = 2; macro KA0302$b_fill3100 = 173892,0,0,0 %; literal KA0302$s_fill3100 = 1212; macro KA0302$L_SLOT7_LMODE = 175104,0,32,0 %; macro KA0302$b_fill3110 = 175108,0,0,0 %; literal KA0302$s_fill3110 = 60; macro KA0302$L_SLOT7_LMERR = 175168,0,32,0 %; macro KA0302$b_fill3120 = 175172,0,0,0 %; literal KA0302$s_fill3120 = 60; macro KA0302$L_SLOT7_LLOCK = 175232,0,32,0 %; macro KA0302$b_fill3130 = 175236,0,0,0 %; literal KA0302$s_fill3130 = 60; macro KA0302$L_SLOT7_LEDTO = 175296,0,32,0 %; macro KA0302$b_fill3140 = 175300,0,0,0 %; literal KA0302$s_fill3140 = 60; macro KA0302$L_SLOT7_LDIAG = 175360,0,32,0 %; macro KA0302$b_fill3150 = 175364,0,0,0 %; literal KA0302$s_fill3150 = 60; macro KA0302$L_SLOT7_LTAGA = 175424,0,32,0 %; macro KA0302$b_fill3160 = 175428,0,0,0 %; literal KA0302$s_fill3160 = 60; macro KA0302$L_SLOT7_LTAGW = 175488,0,32,0 %; macro KA0302$b_fill3170 = 175492,0,0,0 %; literal KA0302$s_fill3170 = 124; macro KA0302$L_SLOT7_LCON0 = 175616,0,32,0 %; macro KA0302$b_fill3180 = 175620,0,0,0 %; literal KA0302$s_fill3180 = 60; macro KA0302$L_SLOT7_LCON1 = 175680,0,32,0 %; macro KA0302$b_fill3190 = 175684,0,0,0 %; literal KA0302$s_fill3190 = 188; macro KA0302$L_SLOT7_LPERF = 175872,0,32,0 %; macro KA0302$b_fill3200 = 175876,0,0,0 %; literal KA0302$s_fill3200 = 60; macro KA0302$L_SLOT7_LCNTR0 = 175936,0,32,0 %; macro KA0302$b_fill3210 = 175940,0,0,0 %; literal KA0302$s_fill3210 = 60; macro KA0302$L_SLOT7_LCNTR1 = 176000,0,32,0 %; macro KA0302$b_fill3220 = 176004,0,0,0 %; literal KA0302$s_fill3220 = 60; macro KA0302$L_SLOT7_LMISSADDR = 176064,0,32,0 %; macro KA0302$b_fill3225 = 176068,0,0,0 %; literal KA0302$s_fill3225 = 4156; macro KA0302$L_SLOT7_MCR = 180224,0,32,0 %; macro KA0302$b_fill3230 = 180228,0,0,0 %; literal KA0302$s_fill3230 = 60; macro KA0302$L_SLOT7_AMR = 180288,0,32,0 %; macro KA0302$b_fill3240 = 180292,0,0,0 %; literal KA0302$s_fill3240 = 60; macro KA0302$L_SLOT7_MSTR0 = 180352,0,32,0 %; macro KA0302$b_fill3250 = 180356,0,0,0 %; literal KA0302$s_fill3250 = 60; macro KA0302$L_SLOT7_MSTR1 = 180416,0,32,0 %; macro KA0302$b_fill3260 = 180420,0,0,0 %; literal KA0302$s_fill3260 = 60; macro KA0302$L_SLOT7_FADR = 180480,0,32,0 %; macro KA0302$b_fill3270 = 180484,0,0,0 %; literal KA0302$s_fill3270 = 60; macro KA0302$L_SLOT7_MERA = 180544,0,32,0 %; macro KA0302$b_fill3280 = 180548,0,0,0 %; literal KA0302$s_fill3280 = 60; macro KA0302$L_SLOT7_MSYNDA = 180608,0,32,0 %; macro KA0302$b_fill3290 = 180612,0,0,0 %; literal KA0302$s_fill3290 = 60; macro KA0302$L_SLOT7_MDRA = 180672,0,32,0 %; macro KA0302$b_fill3300 = 180676,0,0,0 %; literal KA0302$s_fill3300 = 60; macro KA0302$L_SLOT7_MCBSA = 180736,0,32,0 %; macro KA0302$b_fill3310 = 180740,0,0,0 %; literal KA0302$s_fill3310 = 7996; macro KA0302$L_SLOT7_MERB = 188736,0,32,0 %; macro KA0302$b_fill3320 = 188740,0,0,0 %; literal KA0302$s_fill3320 = 60; macro KA0302$L_SLOT7_MSYNDB = 188800,0,32,0 %; macro KA0302$b_fill3330 = 188804,0,0,0 %; literal KA0302$s_fill3330 = 60; macro KA0302$L_SLOT7_MDRB = 188864,0,32,0 %; macro KA0302$b_fill3340 = 188868,0,0,0 %; literal KA0302$s_fill3340 = 60; macro KA0302$L_SLOT7_MCBSB = 188928,0,32,0 %; macro KA0302$b_fill3350 = 188932,0,0,0 %; literal KA0302$s_fill3350 = 7676; macro KA0302$L_SLOT8_LDEV = 196608,0,32,0 %; macro KA0302$V_SLOT8_LDEV_DTYPE = 196608,0,16,0 %; literal KA0302$S_SLOT8_LDEV_DTYPE = 16; macro KA0302$V_SLOT8_LDEV_DREV = 196608,16,16,0 %; literal KA0302$S_SLOT8_LDEV_DREV = 16; macro KA0302$b_fill3360 = 196612,0,0,0 %; literal KA0302$s_fill3360 = 60; macro KA0302$L_SLOT8_LBER = 196672,0,32,0 %; macro KA0302$V_SLOT8_LBER_E = 196672,0,1,0 %; macro KA0302$V_SLOT8_LBER_UCE = 196672,1,1,0 %; macro KA0302$V_SLOT8_LBER_UCE2 = 196672,2,1,0 %; macro KA0302$V_SLOT8_LBER_CE = 196672,3,1,0 %; macro KA0302$V_SLOT8_LBER_CE2 = 196672,4,1,0 %; macro KA0302$V_SLOT8_LBER_CPE = 196672,5,1,0 %; macro KA0302$V_SLOT8_LBER_CPE2 = 196672,6,1,0 %; macro KA0302$V_SLOT8_LBER_CDPE = 196672,7,1,0 %; macro KA0302$V_SLOT8_LBER_CDPE2 = 196672,8,1,0 %; macro KA0302$V_SLOT8_LBER_TDE = 196672,9,1,0 %; macro KA0302$V_SLOT8_LBER_STE = 196672,10,1,0 %; macro KA0302$V_SLOT8_LBER_CNFE = 196672,11,1,0 %; macro KA0302$V_SLOT8_LBER_NXAE = 196672,12,1,0 %; macro KA0302$V_SLOT8_LBER_CAE = 196672,13,1,0 %; macro KA0302$V_SLOT8_LBER_SHE = 196672,14,1,0 %; macro KA0302$V_SLOT8_LBER_DIE = 196672,15,1,0 %; macro KA0302$V_SLOT8_LBER_DTCE = 196672,16,1,0 %; macro KA0302$V_SLOT8_LBER_CTCE = 196672,17,1,0 %; macro KA0302$V_SLOT8_LBER_NSES = 196672,18,1,0 %; macro KA0302$b_fill3370 = 196676,0,0,0 %; literal KA0302$s_fill3370 = 60; macro KA0302$L_SLOT8_LCNR = 196736,0,32,0 %; macro KA0302$V_SLOT8_LCNR_CEEN = 196736,0,1,0 %; macro KA0302$V_SLOT8_LCNR_RSTSTAT = 196736,28,1,0 %; macro KA0302$V_SLOT8_LCNR_NHALT = 196736,29,1,0 %; macro KA0302$V_SLOT8_LCNR_NRST = 196736,30,1,0 %; macro KA0302$V_SLOT8_LCNR_STF = 196736,31,1,0 %; macro KA0302$b_fill3375 = 196740,0,0,0 %; literal KA0302$s_fill3375 = 60; macro KA0302$L_SLOT8_IBR = 196800,0,32,0 %; macro KA0302$V_SLOT8_IBR_RCV_SDAT = 196800,0,1,0 %; macro KA0302$V_SLOT8_IBR_XMT_SDAT = 196800,1,1,0 %; macro KA0302$V_SLOT8_IBR_SCLK = 196800,2,1,0 %; macro KA0302$b_fill3380 = 196804,0,0,0 %; literal KA0302$s_fill3380 = 316; macro KA0302$L_SLOT8_LMMR0 = 197120,0,32,0 %; macro KA0302$V_SLOT8_LMMR0_EN = 197120,0,1,0 %; macro KA0302$V_SLOT8_LMMR0_INT = 197120,1,2,0 %; literal KA0302$S_SLOT8_LMMR0_INT = 2; macro KA0302$V_SLOT8_LMMR0_IA = 197120,3,2,0 %; literal KA0302$S_SLOT8_LMMR0_IA = 2; macro KA0302$V_SLOT8_LMMR0_AW = 197120,5,4,0 %; literal KA0302$S_SLOT8_LMMR0_AW = 4; macro KA0302$V_SLOT8_LMMR0_NBANKS = 197120,9,2,0 %; literal KA0302$S_SLOT8_LMMR0_NBANKS = 2; macro KA0302$V_SLOT8_LMMR0_ADDR = 197120,17,15,0 %; literal KA0302$S_SLOT8_LMMR0_ADDR = 15; macro KA0302$b_fill3390 = 197124,0,0,0 %; literal KA0302$s_fill3390 = 60; macro KA0302$L_SLOT8_LMMR1 = 197184,0,32,0 %; macro KA0302$V_SLOT8_LMMR1_EN = 197184,0,1,0 %; macro KA0302$V_SLOT8_LMMR1_INT = 197184,1,2,0 %; literal KA0302$S_SLOT8_LMMR1_INT = 2; macro KA0302$V_SLOT8_LMMR1_IA = 197184,3,2,0 %; literal KA0302$S_SLOT8_LMMR1_IA = 2; macro KA0302$V_SLOT8_LMMR1_AW = 197184,5,4,0 %; literal KA0302$S_SLOT8_LMMR1_AW = 4; macro KA0302$V_SLOT8_LMMR1_NBANKS = 197184,9,2,0 %; literal KA0302$S_SLOT8_LMMR1_NBANKS = 2; macro KA0302$V_SLOT8_LMMR1_ADDR = 197184,17,15,0 %; literal KA0302$S_SLOT8_LMMR1_ADDR = 15; macro KA0302$b_fill3400 = 197188,0,0,0 %; literal KA0302$s_fill3400 = 60; macro KA0302$L_SLOT8_LMMR2 = 197248,0,32,0 %; macro KA0302$V_SLOT8_LMMR2_EN = 197248,0,1,0 %; macro KA0302$V_SLOT8_LMMR2_INT = 197248,1,2,0 %; literal KA0302$S_SLOT8_LMMR2_INT = 2; macro KA0302$V_SLOT8_LMMR2_IA = 197248,3,2,0 %; literal KA0302$S_SLOT8_LMMR2_IA = 2; macro KA0302$V_SLOT8_LMMR2_AW = 197248,5,4,0 %; literal KA0302$S_SLOT8_LMMR2_AW = 4; macro KA0302$V_SLOT8_LMMR2_NBANKS = 197248,9,2,0 %; literal KA0302$S_SLOT8_LMMR2_NBANKS = 2; macro KA0302$V_SLOT8_LMMR2_ADDR = 197248,17,15,0 %; literal KA0302$S_SLOT8_LMMR2_ADDR = 15; macro KA0302$b_fill3410 = 197252,0,0,0 %; literal KA0302$s_fill3410 = 60; macro KA0302$L_SLOT8_LMMR3 = 197312,0,32,0 %; macro KA0302$V_SLOT8_LMMR3_EN = 197312,0,1,0 %; macro KA0302$V_SLOT8_LMMR3_INT = 197312,1,2,0 %; literal KA0302$S_SLOT8_LMMR3_INT = 2; macro KA0302$V_SLOT8_LMMR3_IA = 197312,3,2,0 %; literal KA0302$S_SLOT8_LMMR3_IA = 2; macro KA0302$V_SLOT8_LMMR3_AW = 197312,5,4,0 %; literal KA0302$S_SLOT8_LMMR3_AW = 4; macro KA0302$V_SLOT8_LMMR3_NBANKS = 197312,9,2,0 %; literal KA0302$S_SLOT8_LMMR3_NBANKS = 2; macro KA0302$V_SLOT8_LMMR3_ADDR = 197312,17,15,0 %; literal KA0302$S_SLOT8_LMMR3_ADDR = 15; macro KA0302$b_fill3420 = 197316,0,0,0 %; literal KA0302$s_fill3420 = 60; macro KA0302$L_SLOT8_LMMR4 = 197376,0,32,0 %; macro KA0302$V_SLOT8_LMMR4_EN = 197376,0,1,0 %; macro KA0302$V_SLOT8_LMMR4_INT = 197376,1,2,0 %; literal KA0302$S_SLOT8_LMMR4_INT = 2; macro KA0302$V_SLOT8_LMMR4_IA = 197376,3,2,0 %; literal KA0302$S_SLOT8_LMMR4_IA = 2; macro KA0302$V_SLOT8_LMMR4_AW = 197376,5,4,0 %; literal KA0302$S_SLOT8_LMMR4_AW = 4; macro KA0302$V_SLOT8_LMMR4_NBANKS = 197376,9,2,0 %; literal KA0302$S_SLOT8_LMMR4_NBANKS = 2; macro KA0302$V_SLOT8_LMMR4_ADDR = 197376,17,15,0 %; literal KA0302$S_SLOT8_LMMR4_ADDR = 15; macro KA0302$b_fill3430 = 197380,0,0,0 %; literal KA0302$s_fill3430 = 60; macro KA0302$L_SLOT8_LMMR5 = 197440,0,32,0 %; macro KA0302$V_SLOT8_LMMR5_EN = 197440,0,1,0 %; macro KA0302$V_SLOT8_LMMR5_INT = 197440,1,2,0 %; literal KA0302$S_SLOT8_LMMR5_INT = 2; macro KA0302$V_SLOT8_LMMR5_IA = 197440,3,2,0 %; literal KA0302$S_SLOT8_LMMR5_IA = 2; macro KA0302$V_SLOT8_LMMR5_AW = 197440,5,4,0 %; literal KA0302$S_SLOT8_LMMR5_AW = 4; macro KA0302$V_SLOT8_LMMR5_NBANKS = 197440,9,2,0 %; literal KA0302$S_SLOT8_LMMR5_NBANKS = 2; macro KA0302$V_SLOT8_LMMR5_ADDR = 197440,17,15,0 %; literal KA0302$S_SLOT8_LMMR5_ADDR = 15; macro KA0302$b_fill3440 = 197444,0,0,0 %; literal KA0302$s_fill3440 = 60; macro KA0302$L_SLOT8_LMMR6 = 197504,0,32,0 %; macro KA0302$V_SLOT8_LMMR6_EN = 197504,0,1,0 %; macro KA0302$V_SLOT8_LMMR6_INT = 197504,1,2,0 %; literal KA0302$S_SLOT8_LMMR6_INT = 2; macro KA0302$V_SLOT8_LMMR6_IA = 197504,3,2,0 %; literal KA0302$S_SLOT8_LMMR6_IA = 2; macro KA0302$V_SLOT8_LMMR6_AW = 197504,5,4,0 %; literal KA0302$S_SLOT8_LMMR6_AW = 4; macro KA0302$V_SLOT8_LMMR6_NBANKS = 197504,9,2,0 %; literal KA0302$S_SLOT8_LMMR6_NBANKS = 2; macro KA0302$V_SLOT8_LMMR6_ADDR = 197504,17,15,0 %; literal KA0302$S_SLOT8_LMMR6_ADDR = 15; macro KA0302$b_fill3450 = 197508,0,0,0 %; literal KA0302$s_fill3450 = 60; macro KA0302$L_SLOT8_LMMR7 = 197568,0,32,0 %; macro KA0302$V_SLOT8_LMMR7_EN = 197568,0,1,0 %; macro KA0302$V_SLOT8_LMMR7_INT = 197568,1,2,0 %; literal KA0302$S_SLOT8_LMMR7_INT = 2; macro KA0302$V_SLOT8_LMMR7_IA = 197568,3,2,0 %; literal KA0302$S_SLOT8_LMMR7_IA = 2; macro KA0302$V_SLOT8_LMMR7_AW = 197568,5,4,0 %; literal KA0302$S_SLOT8_LMMR7_AW = 4; macro KA0302$V_SLOT8_LMMR7_NBANKS = 197568,9,2,0 %; literal KA0302$S_SLOT8_LMMR7_NBANKS = 2; macro KA0302$V_SLOT8_LMMR7_ADDR = 197568,17,15,0 %; literal KA0302$S_SLOT8_LMMR7_ADDR = 15; macro KA0302$b_fill3460 = 197572,0,0,0 %; literal KA0302$s_fill3460 = 572; macro KA0302$L_SLOT8_LBESR0 = 198144,0,32,0 %; macro KA0302$V_SLOT8_LBESR0_SYNDROME = 198144,0,7,0 %; literal KA0302$S_SLOT8_LBESR0_SYNDROME = 7; macro KA0302$b_fill3470 = 198148,0,0,0 %; literal KA0302$s_fill3470 = 60; macro KA0302$L_SLOT8_LBESR1 = 198208,0,32,0 %; macro KA0302$V_SLOT8_LBESR1_SYNDROME = 198208,0,7,0 %; literal KA0302$S_SLOT8_LBESR1_SYNDROME = 7; macro KA0302$b_fill3480 = 198212,0,0,0 %; literal KA0302$s_fill3480 = 60; macro KA0302$L_SLOT8_LBESR2 = 198272,0,32,0 %; macro KA0302$V_SLOT8_LBESR2_SYNDROME = 198272,0,7,0 %; literal KA0302$S_SLOT8_LBESR2_SYNDROME = 7; macro KA0302$b_fill3490 = 198276,0,0,0 %; literal KA0302$s_fill3490 = 60; macro KA0302$L_SLOT8_LBESR3 = 198336,0,32,0 %; macro KA0302$V_SLOT8_LBESR3_SYNDROME = 198336,0,7,0 %; literal KA0302$S_SLOT8_LBESR3_SYNDROME = 7; macro KA0302$b_fill3500 = 198340,0,0,0 %; literal KA0302$s_fill3500 = 60; macro KA0302$L_SLOT8_LBECR0 = 198400,0,32,0 %; macro KA0302$L_SLOT8_LBECR0_CA = 198400,0,32,0 %; macro KA0302$b_fill3510 = 198404,0,0,0 %; literal KA0302$s_fill3510 = 60; macro KA0302$L_SLOT8_LBECR1 = 198464,0,32,0 %; macro KA0302$V_SLOT8_LBECR1_CA = 198464,0,7,0 %; literal KA0302$S_SLOT8_LBECR1_CA = 7; macro KA0302$V_SLOT8_LBECR1_CID = 198464,7,4,0 %; literal KA0302$S_SLOT8_LBECR1_CID = 4; macro KA0302$V_SLOT8_LBECR1_RID = 198464,11,4,0 %; literal KA0302$S_SLOT8_LBECR1_RID = 4; macro KA0302$V_SLOT8_LBECR1_CNF = 198464,15,1,0 %; macro KA0302$V_SLOT8_LBECR1_SHARED = 198464,16,1,0 %; macro KA0302$V_SLOT8_LBECR1_DIRTY = 198464,17,1,0 %; macro KA0302$V_SLOT8_LBECR1_DCYCLE = 198464,18,2,0 %; literal KA0302$S_SLOT8_LBECR1_DCYCLE = 2; macro KA0302$b_fill3520 = 198468,0,0,0 %; literal KA0302$s_fill3520 = 700; macro KA0302$L_LILID0 = 199168,0,32,0 %; macro KA0302$V_LILID0_IDENT = 199168,0,16,0 %; literal KA0302$S_LILID0_IDENT = 16; macro KA0302$b_fill3530 = 199172,0,0,0 %; literal KA0302$s_fill3530 = 60; macro KA0302$L_LILID1 = 199232,0,32,0 %; macro KA0302$V_LILID1_IDENT = 199232,0,16,0 %; literal KA0302$S_LILID1_IDENT = 16; macro KA0302$b_fill3540 = 199236,0,0,0 %; literal KA0302$s_fill3540 = 60; macro KA0302$L_LILID2 = 199296,0,32,0 %; macro KA0302$V_LILID2_IDENT = 199296,0,16,0 %; literal KA0302$S_LILID2_IDENT = 16; macro KA0302$b_fill3550 = 199300,0,0,0 %; literal KA0302$s_fill3550 = 60; macro KA0302$L_LILID3 = 199360,0,32,0 %; macro KA0302$V_LILID3_IDENT = 199360,0,16,0 %; literal KA0302$S_LILID3_IDENT = 16; macro KA0302$b_fill3560 = 199364,0,0,0 %; literal KA0302$s_fill3560 = 60; macro KA0302$L_LCPUMASK = 199424,0,32,0 %; macro KA0302$V_LCPUMASK_CPU0 = 199424,0,4,0 %; literal KA0302$S_LCPUMASK_CPU0 = 4; macro KA0302$V_LCPUMASK_CPU1 = 199424,4,4,0 %; literal KA0302$S_LCPUMASK_CPU1 = 4; macro KA0302$V_LCPUMASK_CPU2 = 199424,8,4,0 %; literal KA0302$S_LCPUMASK_CPU2 = 4; macro KA0302$V_LCPUMASK_CPU3 = 199424,12,4,0 %; literal KA0302$S_LCPUMASK_CPU3 = 4; macro KA0302$b_fill3570 = 199428,0,0,0 %; literal KA0302$s_fill3570 = 252; macro KA0302$Q_LMBPR = 199680,0,0,1 %; literal KA0302$S_LMBPR = 8; macro KA0302$b_fill3580 = 199688,0,0,0 %; literal KA0302$s_fill3580 = 5112; macro KA0302$L_IPCNSE = 204800,0,32,0 %; macro KA0302$V_IPCNSE_MBX_HOSE0_TIP = 204800,0,1,0 %; macro KA0302$V_IPCNSE_MBX_HOSE1_TIP = 204800,1,1,0 %; macro KA0302$V_IPCNSE_MBX_HOSE2_TIP = 204800,2,1,0 %; macro KA0302$V_IPCNSE_MBX_HOSE3_TIP = 204800,3,1,0 %; macro KA0302$V_IPCNSE_UPHOSE0_OFLO = 204800,4,1,0 %; macro KA0302$V_IPCNSE_UPHOSE1_OFLO = 204800,5,1,0 %; macro KA0302$V_IPCNSE_UPHOSE2_OFLO = 204800,6,1,0 %; macro KA0302$V_IPCNSE_UPHOSE3_OFLO = 204800,7,1,0 %; macro KA0302$V_IPCNSE_UPHOSE0_PKT_ERR = 204800,8,1,0 %; macro KA0302$V_IPCNSE_UPHOSE1_PKT_ERR = 204800,9,1,0 %; macro KA0302$V_IPCNSE_UPHOSE2_PKT_ERR = 204800,10,1,0 %; macro KA0302$V_IPCNSE_UPHOSE3_PKT_ERR = 204800,11,1,0 %; macro KA0302$V_IPCNSE_UPHOSE0_PAR_ERR = 204800,12,1,0 %; macro KA0302$V_IPCNSE_UPHOSE1_PAR_ERR = 204800,13,1,0 %; macro KA0302$V_IPCNSE_UPHOSE2_PAR_ERR = 204800,14,1,0 %; macro KA0302$V_IPCNSE_UPHOSE3_PAR_ERR = 204800,15,1,0 %; macro KA0302$V_IPCNSE_UP_HIC_IE = 204800,16,1,0 %; macro KA0302$V_IPCNSE_IPC_INT_ERR = 204800,17,1,0 %; macro KA0302$V_IPCNSE_UP_VRTX_ERR = 204800,18,1,0 %; macro KA0302$V_IPCNSE_DN_VRTX_ERR = 204800,19,1,0 %; macro KA0302$V_IPCNSE_MULT_INTR_ERR = 204800,20,1,0 %; macro KA0302$V_IPCNSE_INTR_NSES = 204800,31,1,0 %; macro KA0302$b_fill3590 = 204804,0,0,0 %; literal KA0302$s_fill3590 = 60; macro KA0302$L_IPCVR = 204864,0,32,0 %; macro KA0302$V_IPCVR_VECTOR = 204864,0,16,0 %; literal KA0302$S_IPCVR_VECTOR = 16; macro KA0302$b_fill3610 = 204868,0,0,0 %; literal KA0302$s_fill3610 = 60; macro KA0302$L_IPCMSR = 204928,0,32,0 %; macro KA0302$V_IPCMSR_ARB_HIGH = 204928,0,1,0 %; macro KA0302$V_IPCMSR_ARB_CTL = 204928,1,2,0 %; literal KA0302$S_IPCMSR_ARB_CTL = 2; macro KA0302$b_fill3620 = 204932,0,0,0 %; literal KA0302$s_fill3620 = 60; macro KA0302$L_IPCHST = 204992,0,32,0 %; macro KA0302$V_IPCHST_H0_ERROR = 204992,0,1,0 %; macro KA0302$V_IPCHST_H0_PWROK = 204992,1,1,0 %; macro KA0302$V_IPCHST_H0_CBLOK = 204992,2,1,0 %; macro KA0302$V_IPCHST_H0_PWROK_TRANS = 204992,3,1,0 %; macro KA0302$V_IPCHST_H1_ERROR = 204992,4,1,0 %; macro KA0302$V_IPCHST_H1_PWROK = 204992,5,1,0 %; macro KA0302$V_IPCHST_H1_CBLOK = 204992,6,1,0 %; macro KA0302$V_IPCHST_H1_PWROK_TRANS = 204992,7,1,0 %; macro KA0302$V_IPCHST_H2_ERROR = 204992,8,1,0 %; macro KA0302$V_IPCHST_H2_PWROK = 204992,9,1,0 %; macro KA0302$V_IPCHST_H2_CBLOK = 204992,10,1,0 %; macro KA0302$V_IPCHST_H2_PWROK_TRANS = 204992,11,1,0 %; macro KA0302$V_IPCHST_H3_ERROR = 204992,12,1,0 %; macro KA0302$V_IPCHST_H3_PWROK = 204992,13,1,0 %; macro KA0302$V_IPCHST_H3_CBLOK = 204992,14,1,0 %; macro KA0302$V_IPCHST_H3_PWROK_TRANS = 204992,15,1,0 %; macro KA0302$V_IPCHST_HOSE0_RST = 204992,28,1,0 %; macro KA0302$V_IPCHST_HOSE1_RST = 204992,29,1,0 %; macro KA0302$V_IPCHST_HOSE2_RST = 204992,30,1,0 %; macro KA0302$V_IPCHST_HOSE3_RST = 204992,31,1,0 %; macro KA0302$b_fill3630 = 204996,0,0,0 %; literal KA0302$s_fill3630 = 60; macro KA0302$L_IPCDR = 205056,0,32,0 %; macro KA0302$V_IPCDR_FRC_DN_ILL_CMD = 205056,0,1,0 %; macro KA0302$V_IPCDR_FRC_DN_SEQ_ERR = 205056,1,1,0 %; macro KA0302$V_IPCDR_FRC_DN_DPE = 205056,2,2,0 %; literal KA0302$S_IPCDR_FRC_DN_DPE = 2; macro KA0302$V_IPCDR_DIS_LSB_CMD = 205056,10,1,0 %; macro KA0302$V_IPCDR_HIC_LPBCK_EN = 205056,11,1,0 %; macro KA0302$V_IPCDR_FRC_DAT_PE = 205056,12,1,0 %; macro KA0302$V_IPCDR_FRC_CMD_PE = 205056,13,1,0 %; macro KA0302$V_IPCDR_FRC_CNFE = 205056,22,1,0 %; macro KA0302$V_IPCDR_FRC_CAE = 205056,23,1,0 %; macro KA0302$V_IPCDR_DIAG_ECC = 205056,24,7,0 %; literal KA0302$S_IPCDR_DIAG_ECC = 7; macro KA0302$V_IPCDR_DIAG_ECC_EN = 205056,31,1,0 %; macro KA0302$b_fill3650 = 205060,0,0,0 %; literal KA0302$s_fill3650 = 7932; macro KA0302$L_LIOINTR = 212992,0,32,0 %; macro KA0302$V_LIOINTR_CPU0 = 212992,0,4,0 %; literal KA0302$S_LIOINTR_CPU0 = 4; macro KA0302$V_LIOINTR_CPU1 = 212992,4,4,0 %; literal KA0302$S_LIOINTR_CPU1 = 4; macro KA0302$V_LIOINTR_CPU2 = 212992,8,4,0 %; literal KA0302$S_LIOINTR_CPU2 = 4; macro KA0302$V_LIOINTR_CPU3 = 212992,12,4,0 %; literal KA0302$S_LIOINTR_CPU3 = 4; macro KA0302$b_fill3660 = 212996,0,0,0 %; literal KA0302$s_fill3660 = 60; macro KA0302$L_LIPINTR = 213056,0,32,0 %; macro KA0302$V_LIPINTR_CPU0 = 213056,0,4,0 %; literal KA0302$S_LIPINTR_CPU0 = 4; macro KA0302$V_LIPINTR_CPU1 = 213056,4,4,0 %; literal KA0302$S_LIPINTR_CPU1 = 4; macro KA0302$V_LIPINTR_CPU2 = 213056,8,4,0 %; literal KA0302$S_LIPINTR_CPU2 = 4; macro KA0302$V_LIPINTR_CPU3 = 213056,12,4,0 %; literal KA0302$S_LIPINTR_CPU3 = 4; macro KA0302$b_fill3670 = 213060,0,0,0 %; literal KA0302$s_fill3670 = 8124; macro KA0302$L_UART0A_RR0 = 221184,0,32,0 %; macro KA0302$b_fill3680 = 221188,0,0,0 %; literal KA0302$s_fill3680 = 60; macro KA0302$L_UART0A_RR8 = 221248,0,32,0 %; macro KA0302$b_fill3690 = 221252,0,0,0 %; literal KA0302$s_fill3690 = 60; macro KA0302$L_UART0B_RR0 = 221312,0,32,0 %; macro KA0302$b_fill3700 = 221316,0,0,0 %; literal KA0302$s_fill3700 = 60; macro KA0302$L_UART0B_RR8 = 221376,0,32,0 %; macro KA0302$b_fill3710 = 221380,0,0,0 %; literal KA0302$s_fill3710 = 7996; macro KA0302$L_UART1B_RR0 = 229376,0,32,0 %; macro KA0302$L_UART1B_WR0 = 229376,0,32,0 %; macro KA0302$b_fill3740 = 229380,0,0,0 %; literal KA0302$s_fill3740 = 60; macro KA0302$L_UART1B_RR8 = 229440,0,32,0 %; macro KA0302$b_fill3750 = 229444,0,0,0 %; literal KA0302$s_fill3750 = 60; macro KA0302$L_UART1A_RR0 = 229504,0,32,0 %; macro KA0302$b_fill3720 = 229508,0,0,0 %; literal KA0302$s_fill3720 = 60; macro KA0302$L_UART1A_RR8 = 229568,0,32,0 %; macro KA0302$b_fill3730 = 229572,0,0,0 %; literal KA0302$s_fill3730 = 7996; macro KA0302$L_UART2B_RR0 = 237568,0,32,0 %; macro KA0302$b_fill3780 = 237572,0,0,0 %; literal KA0302$s_fill3780 = 60; macro KA0302$L_UART2B_RR8 = 237632,0,32,0 %; macro KA0302$b_fill3790 = 237636,0,0,0 %; literal KA0302$s_fill3790 = 60; macro KA0302$L_UART2A_RR0 = 237696,0,32,0 %; macro KA0302$b_fill3760 = 237700,0,0,0 %; literal KA0302$s_fill3760 = 60; macro KA0302$L_UART2A_RR8 = 237760,0,32,0 %; macro KA0302$b_fill3770 = 237764,0,0,0 %; literal KA0302$s_fill3770 = 7996; macro KA0302$L_WATCH_SECONDS = 245760,0,32,0 %; macro KA0302$b_fill3800 = 245764,0,0,0 %; literal KA0302$s_fill3800 = 124; macro KA0302$L_WATCH_MINUTES = 245888,0,32,0 %; macro KA0302$b_fill3810 = 245892,0,0,0 %; literal KA0302$s_fill3810 = 124; macro KA0302$L_WATCH_HOURS = 246016,0,32,0 %; macro KA0302$b_fill3820 = 246020,0,0,0 %; literal KA0302$s_fill3820 = 188; macro KA0302$L_WATCH_DOM = 246208,0,32,0 %; macro KA0302$b_fill3830 = 246212,0,0,0 %; literal KA0302$s_fill3830 = 60; macro KA0302$L_WATCH_MONTH = 246272,0,32,0 %; macro KA0302$b_fill3840 = 246276,0,0,0 %; literal KA0302$s_fill3840 = 60; macro KA0302$L_WATCH_YEAR = 246336,0,32,0 %; macro KA0302$b_fill3850 = 246340,0,0,0 %; literal KA0302$s_fill3850 = 60; macro KA0302$L_WATCH_CSRA = 246400,0,32,0 %; macro KA0302$V_WATCH_CSRA_RS = 246400,0,4,0 %; literal KA0302$S_WATCH_CSRA_RS = 4; macro KA0302$V_WATCH_CSRA_DV = 246400,4,3,0 %; literal KA0302$S_WATCH_CSRA_DV = 3; macro KA0302$V_WATCH_CSRA_UIP = 246400,7,1,0 %; macro KA0302$b_fill3860 = 246404,0,0,0 %; literal KA0302$s_fill3860 = 60; macro KA0302$L_WATCH_CSRB = 246464,0,32,0 %; macro KA0302$V_WATCH_CSRB_DSE = 246464,0,1,0 %; macro KA0302$V_WATCH_CSRB_24_12 = 246464,1,1,0 %; macro KA0302$V_WATCH_CSRB_DM = 246464,2,1,0 %; macro KA0302$V_WATCH_CSRB_SQWE = 246464,3,1,0 %; macro KA0302$V_WATCH_CSRB_UIE = 246464,4,1,0 %; macro KA0302$V_WATCH_CSRB_AIE = 246464,5,1,0 %; macro KA0302$V_WATCH_CSRB_PIE = 246464,6,1,0 %; macro KA0302$V_WATCH_CSRB_SET = 246464,7,1,0 %; macro KA0302$b_fill3870 = 246468,0,0,0 %; literal KA0302$s_fill3870 = 60; macro KA0302$L_WATCH_CSRC = 246528,0,32,0 %; macro KA0302$V_WATCH_CSRC_UF = 246528,4,1,0 %; macro KA0302$V_WATCH_CSRC_AF = 246528,5,1,0 %; macro KA0302$V_WATCH_CSRC_PF = 246528,6,1,0 %; macro KA0302$V_WATCH_CSRC_IRQF = 246528,7,1,0 %; macro KA0302$b_fill3880 = 246532,0,0,0 %; literal KA0302$s_fill3880 = 60; macro KA0302$L_WATCH_CSRD = 246592,0,32,0 %; macro KA0302$V_WATCH_CSRD_VRT = 246592,7,1,0 %; macro KA0302$b_fill3890 = 246596,0,0,0 %; literal KA0302$s_fill3890 = 60; macro KA0302$L_WATCH_RAM = 246656,0,32,0 %; macro KA0302$b_fill3900 = 246660,0,0,0 %; literal KA0302$s_fill3900 = 7292; macro KA0302$L_GBUS_WHAMI = 253952,0,32,0 %; macro KA0302$V_GBUS_WHAMI_NID = 253952,0,3,0 %; literal KA0302$S_GBUS_WHAMI_NID = 3; macro KA0302$V_GBUS_WHAMI_MFG = 253952,3,1,0 %; macro KA0302$V_GBUS_WHAMI_LSB_BAD = 253952,4,1,0 %; macro KA0302$b_fill3910 = 253956,0,0,0 %; literal KA0302$s_fill3910 = 60; macro KA0302$L_GBUS_LEDS = 254016,0,32,0 %; macro KA0302$V_GBUS_LEDS_STP = 254016,0,1,0 %; macro KA0302$V_GBUS_LEDS_CONW = 254016,1,1,0 %; macro KA0302$V_GBUS_LEDS_RUN = 254016,2,1,0 %; macro KA0302$V_GBUS_LEDS_LED3 = 254016,3,1,0 %; macro KA0302$V_GBUS_LEDS_LED4 = 254016,4,1,0 %; macro KA0302$V_GBUS_LEDS_LED5 = 254016,5,1,0 %; macro KA0302$V_GBUS_LEDS_LED6 = 254016,6,1,0 %; macro KA0302$V_GBUS_LEDS_LED7 = 254016,7,1,0 %; macro KA0302$b_fill3920 = 254020,0,0,0 %; literal KA0302$s_fill3920 = 60; macro KA0302$L_GBUS_PMASK = 254080,0,32,0 %; macro KA0302$V_GBUS_PMASK_HALTEN = 254080,0,1,0 %; macro KA0302$V_GBUS_PMASK_SELTERM = 254080,1,2,0 %; literal KA0302$S_GBUS_PMASK_SELTERM = 2; macro KA0302$b_fill3930 = 254084,0,0,0 %; literal KA0302$s_fill3930 = 60; macro KA0302$L_GBUS_INTR = 254144,0,32,0 %; macro KA0302$V_GBUS_INTR_UARTINT0 = 254144,0,1,0 %; macro KA0302$V_GBUS_INTR_UARTINT1 = 254144,1,1,0 %; macro KA0302$V_GBUS_INTR_LSB0 = 254144,2,1,0 %; macro KA0302$V_GBUS_INTR_LSB2 = 254144,5,1,0 %; macro KA0302$V_GBUS_INTR_IP = 254144,6,1,0 %; macro KA0302$V_GBUS_INTR_INTIM = 254144,7,1,0 %; macro KA0302$b_fill3940 = 254148,0,0,0 %; literal KA0302$s_fill3940 = 60; macro KA0302$L_GBUS_HALT = 254208,0,32,0 %; macro KA0302$V_GBUS_HALT_PHALT = 254208,6,1,0 %; macro KA0302$V_GBUS_HALT_NHALT = 254208,7,1,0 %; macro KA0302$b_fill3950 = 254212,0,0,0 %; literal KA0302$s_fill3950 = 60; macro KA0302$L_GBUS_LSBRST = 254272,0,32,0 %; macro KA0302$b_fill3960 = 254276,0,0,0 %; literal KA0302$s_fill3960 = 60; macro KA0302$L_GBUS_MISC = 254336,0,32,0 %; macro KA0302$V_GBUS_MISC_EXPSEL = 254336,0,2,0 %; literal KA0302$S_GBUS_MISC_EXPSEL = 2; macro KA0302$b_fill3970 = 254340,0,0,0 %; literal KA0302$s_fill3970 = 7804; macro KA0302$L_GBUS_RMODE_ENA = 262144,0,32,0 %; macro KA0302$b_fill3971 = 262148,0,0,0 %; literal KA0302$s_fill3971 = 252; macro KA0302$L_GBUS_LTAGRW = 262400,0,32,0 %; literal FLAG$M_FINT_VECTOR = %X'FFFF'; literal FLAG$M_NID_NODESIDE = %X'1'; literal FLAG$M_NID_GA = %X'3E'; literal FLAG$M_NID_BUS_ADDRESS = %X'FFC0'; literal FLAG$M_STO_VALUE = %X'7F000000'; literal FLAG$M_STO_fill1 = %X'80000000'; literal FLAG$M_ERRORHI_CMD_FIELD = %X'FF'; literal FLAG$M_ERRORHI_STATUS_FIELD = %X'FF00'; literal FLAG$M_ERRORHI_CAP_LINES = %X'70000'; literal FLAG$M_ERRORHI_USE = %X'80000'; literal FLAG$M_ERRORHI_PROTO_ERR = %X'400000'; literal FLAG$M_ERRORHI_DA_PE = %X'800000'; literal FLAG$M_ERRORHI_CMD_PE = %X'1000000'; literal FLAG$M_ERRORHI_NXA = %X'4000000'; literal FLAG$M_ERRORHI_DISC_PHASE = %X'8000000'; literal FLAG$M_ERRORHI_DATA_PHASE = %X'10000000'; literal FLAG$M_ERRORHI_CON_PHASE = %X'20000000'; literal FLAG$M_ERRORHI_MASTER = %X'40000000'; literal FLAG$M_ERRORHI_ERR_SUM = %X'80000000'; literal FLAG$M_ERRORLO_NXTID = %X'1'; literal FLAG$M_TTO_VAL = %X'1E0000'; literal FLAG$M_BZRTRY_BRT = %X'3FF'; literal FLAG$M_BZRTRY_RETDLY = %X'FFF8000'; literal FLAG$M_FCTL_SM = %X'1'; literal FLAG$M_FCTL_SI = %X'2'; literal FLAG$M_FCTL_PRE = %X'4'; literal FLAG$M_FCTL_STF = %X'8'; literal FLAG$M_FCTL_MERR_EN = %X'10'; literal FLAG$M_FCTL_SEL_SLV_ERR_EN = %X'20'; literal FLAG$M_FCTL_SLV_ERR_EN = %X'40'; literal FLAG$M_FCTL_HOSE_ERR_EN = %X'80'; literal FLAG$M_FCTL_FATAL_ERR_ST_EN = %X'100'; literal FLAG$M_FCTL_FBUS_RESET = %X'200'; literal FLAG$M_FCTL_FINTEN_14 = %X'400'; literal FLAG$M_FCTL_FINTEN_15 = %X'800'; literal FLAG$M_FCTL_FINTEN_16 = %X'1000'; literal FLAG$M_FCTL_FINTEN_17 = %X'2000'; literal FLAG$M_FCTL_FINTEN = %X'4000'; literal FLAG$M_FCTL_GF0 = %X'8000'; literal FLAG$M_FCTL_GF1 = %X'10000'; literal FLAG$M_FCTL_MEMDECEN = %X'20000'; literal FLAG$M_FCTL_CSRRBEN = %X'40000'; literal FLAG$M_FCTL_ENUPRST = %X'80000'; literal FLAG$M_DIAG_DNP_HDRERR = %X'1'; literal FLAG$M_DIAG_DNP_DERR = %X'2'; literal FLAG$M_DIAG_DRE = %X'4'; literal FLAG$M_DIAG_FTTO = %X'8'; literal FLAG$M_DIAG_FBI = %X'10'; literal FLAG$M_DIAG_SDL = %X'20'; literal FLAG$M_DIAG_LBD = %X'40'; literal FLAG$M_DIAG_LBEN = %X'80'; literal FLAG$M_DIAG_LBRDY = %X'100'; literal FLAG$M_DIAG_CP = %X'8000'; literal FLAG$M_DIAG_CM = %X'FF0000'; literal FLAG$M_DIAG_BP = %X'FF000000'; literal FLAG$M_FERR_FINTERR = %X'1'; literal FLAG$M_FERR_DHURR = %X'2'; literal FLAG$M_FERR_DHDPE = %X'4'; literal FLAG$M_FERR_TTO = %X'8'; literal FLAG$M_FERR_STO = %X'10'; literal FLAG$M_FERR_BRTO = %X'20'; literal FLAG$M_FERR_DPCU = %X'8000'; literal FLAG$M_FERR_FIFOFULL = %X'10000'; literal FLAG$M_FERR_DNHSE_ICCE = %X'20000'; literal FLAG$M_FERR_DNHSE_PLE = %X'40000'; literal FLAG$M_FERR_DNHSE_IDMALE = %X'80000'; literal FLAG$M_FERR_DNHSE_CMDLE = %X'100000'; literal FLAG$M_FERR_DNHSE_HCPE = %X'200000'; literal FLAG$M_FERR_DNHSE_SEQERR = %X'400000'; literal FLAG$M_FERR_UMBCMD = %X'800000'; literal FLAG$M_FERR_BINT = %X'1000000'; literal FLAG$M_IBR_RCV_SDAT = %X'1'; literal FLAG$M_IBR_XMT_SDAT = %X'2'; literal FLAG$M_IBR_SCLK = %X'4'; literal FLAG$M_DEVICE_ID_FLAG_ID = %X'FFFF'; literal FLAG$M_DEVICE_ID_REV = %X'F0000'; literal FLAG$M_DEVICE_ID_NODESIDE = %X'100000'; literal FLAG$M_DEVICE_ID_GA = %X'3E00000'; literal FLAG$S_FLAGDEF = 60; ! Old size name, synonym for FLAG$S_KA0302FLAG literal FLAG$S_KA0302FLAG = 60; macro FLAG$L_FINT = 0,0,32,0 %; macro FLAG$V_FINT_VECTOR = 0,0,16,0 %; literal FLAG$S_FINT_VECTOR = 16; macro FLAG$L_NID = 4,0,32,0 %; macro FLAG$V_NID_NODESIDE = 4,0,1,0 %; macro FLAG$V_NID_GA = 4,1,5,0 %; literal FLAG$S_NID_GA = 5; macro FLAG$V_NID_BUS_ADDRESS = 4,6,10,0 %; literal FLAG$S_NID_BUS_ADDRESS = 10; macro FLAG$L_STO = 8,0,32,0 %; macro FLAG$V_STO_VALUE = 8,24,7,0 %; literal FLAG$S_STO_VALUE = 7; macro FLAG$V_STO_fill1 = 8,31,1,0 %; macro FLAG$L_ERRORHI = 12,0,32,0 %; macro FLAG$V_ERRORHI_CMD_FIELD = 12,0,8,0 %; literal FLAG$S_ERRORHI_CMD_FIELD = 8; macro FLAG$V_ERRORHI_STATUS_FIELD = 12,8,8,0 %; literal FLAG$S_ERRORHI_STATUS_FIELD = 8; macro FLAG$V_ERRORHI_CAP_LINES = 12,16,3,0 %; literal FLAG$S_ERRORHI_CAP_LINES = 3; macro FLAG$V_ERRORHI_USE = 12,19,1,0 %; macro FLAG$V_ERRORHI_PROTO_ERR = 12,22,1,0 %; macro FLAG$V_ERRORHI_DA_PE = 12,23,1,0 %; macro FLAG$V_ERRORHI_CMD_PE = 12,24,1,0 %; macro FLAG$V_ERRORHI_NXA = 12,26,1,0 %; macro FLAG$V_ERRORHI_DISC_PHASE = 12,27,1,0 %; macro FLAG$V_ERRORHI_DATA_PHASE = 12,28,1,0 %; macro FLAG$V_ERRORHI_CON_PHASE = 12,29,1,0 %; macro FLAG$V_ERRORHI_MASTER = 12,30,1,0 %; macro FLAG$V_ERRORHI_ERR_SUM = 12,31,1,0 %; macro FLAG$L_ERRORLO = 16,0,32,0 %; macro FLAG$V_ERRORLO_NXTID = 16,0,1,0 %; macro FLAG$L_FADRHI = 20,0,32,0 %; macro FLAG$L_FADRLO = 24,0,32,0 %; macro FLAG$L_TTO = 28,0,32,0 %; macro FLAG$V_TTO_VAL = 28,17,4,0 %; literal FLAG$S_TTO_VAL = 4; macro FLAG$L_BZRTRY = 32,0,32,0 %; macro FLAG$V_BZRTRY_BRT = 32,0,10,0 %; literal FLAG$S_BZRTRY_BRT = 10; macro FLAG$V_BZRTRY_RETDLY = 32,15,13,0 %; literal FLAG$S_BZRTRY_RETDLY = 13; macro FLAG$L_FCTL = 36,0,32,0 %; macro FLAG$V_FCTL_SM = 36,0,1,0 %; macro FLAG$V_FCTL_SI = 36,1,1,0 %; macro FLAG$V_FCTL_PRE = 36,2,1,0 %; macro FLAG$V_FCTL_STF = 36,3,1,0 %; macro FLAG$V_FCTL_MERR_EN = 36,4,1,0 %; macro FLAG$V_FCTL_SEL_SLV_ERR_EN = 36,5,1,0 %; macro FLAG$V_FCTL_SLV_ERR_EN = 36,6,1,0 %; macro FLAG$V_FCTL_HOSE_ERR_EN = 36,7,1,0 %; macro FLAG$V_FCTL_FATAL_ERR_ST_EN = 36,8,1,0 %; macro FLAG$V_FCTL_FBUS_RESET = 36,9,1,0 %; macro FLAG$V_FCTL_FINTEN_14 = 36,10,1,0 %; macro FLAG$V_FCTL_FINTEN_15 = 36,11,1,0 %; macro FLAG$V_FCTL_FINTEN_16 = 36,12,1,0 %; macro FLAG$V_FCTL_FINTEN_17 = 36,13,1,0 %; macro FLAG$V_FCTL_FINTEN = 36,14,1,0 %; macro FLAG$V_FCTL_GF0 = 36,15,1,0 %; macro FLAG$V_FCTL_GF1 = 36,16,1,0 %; macro FLAG$V_FCTL_MEMDECEN = 36,17,1,0 %; macro FLAG$V_FCTL_CSRRBEN = 36,18,1,0 %; macro FLAG$V_FCTL_ENUPRST = 36,19,1,0 %; macro FLAG$L_DIAG = 40,0,32,0 %; macro FLAG$V_DIAG_DNP_HDRERR = 40,0,1,0 %; macro FLAG$V_DIAG_DNP_DERR = 40,1,1,0 %; macro FLAG$V_DIAG_DRE = 40,2,1,0 %; macro FLAG$V_DIAG_FTTO = 40,3,1,0 %; macro FLAG$V_DIAG_FBI = 40,4,1,0 %; macro FLAG$V_DIAG_SDL = 40,5,1,0 %; macro FLAG$V_DIAG_LBD = 40,6,1,0 %; macro FLAG$V_DIAG_LBEN = 40,7,1,0 %; macro FLAG$V_DIAG_LBRDY = 40,8,1,0 %; macro FLAG$V_DIAG_CP = 40,15,1,0 %; macro FLAG$V_DIAG_CM = 40,16,8,0 %; literal FLAG$S_DIAG_CM = 8; macro FLAG$V_DIAG_BP = 40,24,8,0 %; literal FLAG$S_DIAG_BP = 8; macro FLAG$L_FGPR = 44,0,32,0 %; macro FLAG$L_FERR = 48,0,32,0 %; macro FLAG$V_FERR_FINTERR = 48,0,1,0 %; macro FLAG$V_FERR_DHURR = 48,1,1,0 %; macro FLAG$V_FERR_DHDPE = 48,2,1,0 %; macro FLAG$V_FERR_TTO = 48,3,1,0 %; macro FLAG$V_FERR_STO = 48,4,1,0 %; macro FLAG$V_FERR_BRTO = 48,5,1,0 %; macro FLAG$V_FERR_DPCU = 48,15,1,0 %; macro FLAG$V_FERR_FIFOFULL = 48,16,1,0 %; macro FLAG$V_FERR_DNHSE_ICCE = 48,17,1,0 %; macro FLAG$V_FERR_DNHSE_PLE = 48,18,1,0 %; macro FLAG$V_FERR_DNHSE_IDMALE = 48,19,1,0 %; macro FLAG$V_FERR_DNHSE_CMDLE = 48,20,1,0 %; macro FLAG$V_FERR_DNHSE_HCPE = 48,21,1,0 %; macro FLAG$V_FERR_DNHSE_SEQERR = 48,22,1,0 %; macro FLAG$V_FERR_UMBCMD = 48,23,1,0 %; macro FLAG$V_FERR_BINT = 48,24,1,0 %; macro FLAG$L_IBR = 52,0,32,0 %; macro FLAG$V_IBR_RCV_SDAT = 52,0,1,0 %; macro FLAG$V_IBR_XMT_SDAT = 52,1,1,0 %; macro FLAG$V_IBR_SCLK = 52,2,1,0 %; macro FLAG$L_DEVICE_ID = 56,0,32,0 %; macro FLAG$V_DEVICE_ID_FLAG_ID = 56,0,16,0 %; literal FLAG$S_DEVICE_ID_FLAG_ID = 16; macro FLAG$V_DEVICE_ID_REV = 56,16,4,0 %; literal FLAG$S_DEVICE_ID_REV = 4; macro FLAG$V_DEVICE_ID_NODESIDE = 56,20,1,0 %; macro FLAG$V_DEVICE_ID_GA = 56,21,5,0 %; literal FLAG$S_DEVICE_ID_GA = 5; literal LAMB$M_LDIAG_F39 = %X'100'; literal LAMB$M_LDIAG_STE = %X'200'; literal LAMB$M_LDIAG_FXA = %X'400'; literal LAMB$M_LDIAG_ASM = %X'1800'; literal LAMB$M_LDIAG_DRNK = %X'4000'; literal LAMB$M_LDIAG_FPE = %X'F0000'; literal LAMB$M_LDIAG_CRE = %X'100000'; literal LAMB$M_LDIAG_FRRM = %X'600000'; literal LAMB$M_LDIAG_LOOP = %X'800000'; literal LAMB$M_LDIAG_LOCK = %X'1000000'; literal LAMB$M_LDIAG_AS = %X'2000000'; literal LAMB$M_LDIAG_DLLF = %X'C000000'; literal LAMB$M_LDIAG_NODE = %X'F0000000'; literal LAMB$M_IMSK_IMBER = %X'10'; literal LAMB$M_IMSK_IRBDPE = %X'20'; literal LAMB$M_IMSK_IDFDPE = %X'40'; literal LAMB$M_IMSK_ITTO = %X'2000'; literal LAMB$M_IMSK_ICNAK = %X'8000'; literal LAMB$M_IMSK_IRER = %X'10000'; literal LAMB$M_IMSK_IRSE = %X'20000'; literal LAMB$M_IMSK_INRR = %X'40000'; literal LAMB$M_IMSK_ICRD = %X'80000'; literal LAMB$M_IMSK_IWDNAK = %X'100000'; literal LAMB$M_IMSK_IRIDNAK = %X'200000'; literal LAMB$M_IMSK_IWSE = %X'400000'; literal LAMB$M_IMSK_IXPE = %X'800000'; literal LAMB$M_IMSK_IIPE = %X'1000000'; literal LAMB$M_IMSK_IWEI = %X'2000000'; literal LAMB$M_IMSK_ICC = %X'8000000'; literal LAMB$M_LEVR_VEC = %X'FFFF'; literal LAMB$M_LERR_FE = %X'8'; literal LAMB$M_LERR_MBOF = %X'10'; literal LAMB$M_LERR_RBDPE = %X'20'; literal LAMB$M_LERR_DFDPE = %X'40'; literal LAMB$M_LERR_MBIA = %X'1000'; literal LAMB$M_LERR_MBIC = %X'2000'; literal LAMB$M_LERR_MBPE = %X'4000'; literal LAMB$M_LERR_IVID = %X'78000'; literal LAMB$M_LERR_DHDPE = %X'10000000'; literal LAMB$M_LERR_XMIPE0 = %X'20000000'; literal LAMB$M_LERR_XMIPE1 = %X'40000000'; literal LAMB$M_LERR_XMIPE2 = %X'80000000'; literal LAMB$M_IPR1_IP1 = %X'F'; literal LAMB$M_IPR1_IP2 = %X'F0'; literal LAMB$M_IPR1_IP3 = %X'F00'; literal LAMB$M_IPR1_IP4 = %X'F000'; literal LAMB$M_IPR1_IP5 = %X'F0000'; literal LAMB$M_IPR1_IP6 = %X'F00000'; literal LAMB$M_IPR1_IP7 = %X'F000000'; literal LAMB$M_IPR1_IP8 = %X'F0000000'; literal LAMB$M_IPR2_IP9 = %X'F'; literal LAMB$M_IPR2_IP10 = %X'F0'; literal LAMB$M_IPR2_IP11 = %X'F00'; literal LAMB$M_IPR2_IP12 = %X'F000'; literal LAMB$M_IPR2_IP13 = %X'F0000'; literal LAMB$M_IPR2_IP14 = %X'F00000'; literal LAMB$M_IPR2_LEIP = %X'80000000'; literal LAMB$M_IIPR_IPL14ID = %X'F'; literal LAMB$M_IIPR_IPL15ID = %X'F0'; literal LAMB$M_IIPR_IPL16ID = %X'F00'; literal LAMB$M_IIPR_IPL17ID = %X'F000'; literal LAMB$M_IIPR_IDENTID = %X'F0000'; literal LAMB$S_LAMBDEF = 96; ! Old size name, synonym for LAMB$S_LAMB literal LAMB$S_LAMB = 96; macro LAMB$L_LDIAG = 64,0,32,0 %; macro LAMB$V_LDIAG_F39 = 64,8,1,0 %; macro LAMB$V_LDIAG_STE = 64,9,1,0 %; macro LAMB$V_LDIAG_FXA = 64,10,1,0 %; macro LAMB$V_LDIAG_ASM = 64,11,2,0 %; literal LAMB$S_LDIAG_ASM = 2; macro LAMB$V_LDIAG_DRNK = 64,14,1,0 %; macro LAMB$V_LDIAG_FPE = 64,16,4,0 %; literal LAMB$S_LDIAG_FPE = 4; macro LAMB$V_LDIAG_CRE = 64,20,1,0 %; macro LAMB$V_LDIAG_FRRM = 64,21,2,0 %; literal LAMB$S_LDIAG_FRRM = 2; macro LAMB$V_LDIAG_LOOP = 64,23,1,0 %; macro LAMB$V_LDIAG_LOCK = 64,24,1,0 %; macro LAMB$V_LDIAG_AS = 64,25,1,0 %; macro LAMB$V_LDIAG_DLLF = 64,26,2,0 %; literal LAMB$S_LDIAG_DLLF = 2; macro LAMB$V_LDIAG_NODE = 64,28,4,0 %; literal LAMB$S_LDIAG_NODE = 4; macro LAMB$L_IMSK = 68,0,32,0 %; macro LAMB$V_IMSK_IMBER = 68,4,1,0 %; macro LAMB$V_IMSK_IRBDPE = 68,5,1,0 %; macro LAMB$V_IMSK_IDFDPE = 68,6,1,0 %; macro LAMB$V_IMSK_ITTO = 68,13,1,0 %; macro LAMB$V_IMSK_ICNAK = 68,15,1,0 %; macro LAMB$V_IMSK_IRER = 68,16,1,0 %; macro LAMB$V_IMSK_IRSE = 68,17,1,0 %; macro LAMB$V_IMSK_INRR = 68,18,1,0 %; macro LAMB$V_IMSK_ICRD = 68,19,1,0 %; macro LAMB$V_IMSK_IWDNAK = 68,20,1,0 %; macro LAMB$V_IMSK_IRIDNAK = 68,21,1,0 %; macro LAMB$V_IMSK_IWSE = 68,22,1,0 %; macro LAMB$V_IMSK_IXPE = 68,23,1,0 %; macro LAMB$V_IMSK_IIPE = 68,24,1,0 %; macro LAMB$V_IMSK_IWEI = 68,25,1,0 %; macro LAMB$V_IMSK_ICC = 68,27,1,0 %; macro LAMB$L_LEVR = 72,0,32,0 %; macro LAMB$V_LEVR_VEC = 72,0,16,0 %; literal LAMB$S_LEVR_VEC = 16; macro LAMB$L_LERR = 76,0,32,0 %; macro LAMB$V_LERR_FE = 76,3,1,0 %; macro LAMB$V_LERR_MBOF = 76,4,1,0 %; macro LAMB$V_LERR_RBDPE = 76,5,1,0 %; macro LAMB$V_LERR_DFDPE = 76,6,1,0 %; macro LAMB$V_LERR_MBIA = 76,12,1,0 %; macro LAMB$V_LERR_MBIC = 76,13,1,0 %; macro LAMB$V_LERR_MBPE = 76,14,1,0 %; macro LAMB$V_LERR_IVID = 76,15,4,0 %; literal LAMB$S_LERR_IVID = 4; macro LAMB$V_LERR_DHDPE = 76,28,1,0 %; macro LAMB$V_LERR_XMIPE0 = 76,29,1,0 %; macro LAMB$V_LERR_XMIPE1 = 76,30,1,0 %; macro LAMB$V_LERR_XMIPE2 = 76,31,1,0 %; macro LAMB$L_LGPR = 80,0,32,0 %; macro LAMB$L_IPR1 = 84,0,32,0 %; macro LAMB$V_IPR1_IP1 = 84,0,4,0 %; literal LAMB$S_IPR1_IP1 = 4; macro LAMB$V_IPR1_IP2 = 84,4,4,0 %; literal LAMB$S_IPR1_IP2 = 4; macro LAMB$V_IPR1_IP3 = 84,8,4,0 %; literal LAMB$S_IPR1_IP3 = 4; macro LAMB$V_IPR1_IP4 = 84,12,4,0 %; literal LAMB$S_IPR1_IP4 = 4; macro LAMB$V_IPR1_IP5 = 84,16,4,0 %; literal LAMB$S_IPR1_IP5 = 4; macro LAMB$V_IPR1_IP6 = 84,20,4,0 %; literal LAMB$S_IPR1_IP6 = 4; macro LAMB$V_IPR1_IP7 = 84,24,4,0 %; literal LAMB$S_IPR1_IP7 = 4; macro LAMB$V_IPR1_IP8 = 84,28,4,0 %; literal LAMB$S_IPR1_IP8 = 4; macro LAMB$L_IPR2 = 88,0,32,0 %; macro LAMB$V_IPR2_IP9 = 88,0,4,0 %; literal LAMB$S_IPR2_IP9 = 4; macro LAMB$V_IPR2_IP10 = 88,4,4,0 %; literal LAMB$S_IPR2_IP10 = 4; macro LAMB$V_IPR2_IP11 = 88,8,4,0 %; literal LAMB$S_IPR2_IP11 = 4; macro LAMB$V_IPR2_IP12 = 88,12,4,0 %; literal LAMB$S_IPR2_IP12 = 4; macro LAMB$V_IPR2_IP13 = 88,16,4,0 %; literal LAMB$S_IPR2_IP13 = 4; macro LAMB$V_IPR2_IP14 = 88,20,4,0 %; literal LAMB$S_IPR2_IP14 = 4; macro LAMB$V_IPR2_LEIP = 88,31,1,0 %; macro LAMB$L_IIPR = 92,0,32,0 %; macro LAMB$V_IIPR_IPL14ID = 92,0,4,0 %; literal LAMB$S_IIPR_IPL14ID = 4; macro LAMB$V_IIPR_IPL15ID = 92,4,4,0 %; literal LAMB$S_IIPR_IPL15ID = 4; macro LAMB$V_IIPR_IPL16ID = 92,8,4,0 %; literal LAMB$S_IIPR_IPL16ID = 4; macro LAMB$V_IIPR_IPL17ID = 92,12,4,0 %; literal LAMB$S_IIPR_IPL17ID = 4; macro LAMB$V_IIPR_IDENTID = 92,16,4,0 %; literal LAMB$S_IIPR_IDENTID = 4; !*** MODULE $MCHECK0302DEF *** literal MCHECK0302$M_GBUS_HALT_PHALT = %X'40'; literal MCHECK0302$M_GBUS_HALT_NHALT = %X'80'; literal MCHECK0302$M_GBUS_INTR_UARTINT0 = %X'10000'; literal MCHECK0302$M_GBUS_INTR_UARTINT1 = %X'20000'; literal MCHECK0302$M_GBUS_INTR_LSB0 = %X'40000'; literal MCHECK0302$M_GBUS_INTR_LSB2 = %X'200000'; literal MCHECK0302$M_GBUS_INTR_IP = %X'400000'; literal MCHECK0302$M_GBUS_INTR_INTIM = %X'800000'; literal MCHECK0302$M_GBUS_PMASK_HALTEN = %X'100000000'; literal MCHECK0302$M_GBUS_PMASK_SELTERM = %X'600000000'; literal MCHECK0302$M_GBUS_WHAMI_NID = %X'7000000000000'; literal MCHECK0302$M_GBUS_WHAMI_MFG = %X'8000000000000'; literal MCHECK0302$M_GBUS_WHAMI_LSB_BAD = %X'10000000000000'; literal MCHECK0302$S_GBUS = 7; macro MCHECK0302$V_GBUS_HALT_PHALT = 0,6,1,0 %; macro MCHECK0302$V_GBUS_HALT_NHALT = 0,7,1,0 %; macro MCHECK0302$V_GBUS_INTR_UARTINT0 = 0,16,1,0 %; macro MCHECK0302$V_GBUS_INTR_UARTINT1 = 0,17,1,0 %; macro MCHECK0302$V_GBUS_INTR_LSB0 = 0,18,1,0 %; macro MCHECK0302$V_GBUS_INTR_LSB2 = 0,21,1,0 %; macro MCHECK0302$V_GBUS_INTR_IP = 0,22,1,0 %; macro MCHECK0302$V_GBUS_INTR_INTIM = 0,23,1,0 %; macro MCHECK0302$V_GBUS_PMASK_HALTEN = 4,0,1,0 %; macro MCHECK0302$V_GBUS_PMASK_SELTERM = 4,1,2,0 %; literal MCHECK0302$S_GBUS_PMASK_SELTERM = 2; macro MCHECK0302$V_GBUS_WHAMI_NID = 4,16,3,0 %; literal MCHECK0302$S_GBUS_WHAMI_NID = 3; macro MCHECK0302$V_GBUS_WHAMI_MFG = 4,19,1,0 %; macro MCHECK0302$V_GBUS_WHAMI_LSB_BAD = 4,20,1,0 %; literal MCHECK0302$S_LMODE = 4; macro MCHECK0302$L_LMODE = 0,0,32,0 %; literal MCHECK0302$S_LMERR = 8; macro MCHECK0302$L_LMERR = 0,0,32,0 %; macro MCHECK0302$v_lmerr_pmap_dlowpe = 0,0,1,0 %; macro MCHECK0302$v_lmerr_pmap_dhipe = 0,1,1,0 %; macro MCHECK0302$v_lmerr_pmap_i0pe = 0,2,1,0 %; macro MCHECK0302$v_lmerr_pmap_i1pe = 0,3,1,0 %; macro MCHECK0302$v_lmerr_btagpe = 0,4,1,0 %; ! BTAG Parity Error macro MCHECK0302$v_lmerr_bstatpe = 0,5,1,0 %; ! BSTATUS Parity Error macro MCHECK0302$v_lmerr_bmappe = 0,6,1,0 %; ! BMAP Parity Error macro MCHECK0302$v_lmerr_bdatasbe = 0,7,1,0 %; ! Bcache Data Single Bit error macro MCHECK0302$v_lmerr_bdatadbe = 0,8,1,0 %; ! Bcache Data Double Bit error macro MCHECK0302$v_lmerr_arbcol = 0,9,1,0 %; ! Arbitration COllision macro MCHECK0302$v_lmerr_arbdrop = 0,10,1,0 %; ! Arbitration Drop macro MCHECK0302$v_lmerr_edalto = 0,11,1,0 %; ! EDAL Timeout. literal MCHECK0302$S_LLOCK = 4; macro MCHECK0302$L_LLOCK = 0,0,32,0 %; literal MCHECK0302$M_LBER_E = %X'1'; literal MCHECK0302$M_LBER_UCE = %X'2'; literal MCHECK0302$M_LBER_UCE2 = %X'4'; literal MCHECK0302$M_LBER_CE = %X'8'; literal MCHECK0302$M_LBER_CE2 = %X'10'; literal MCHECK0302$M_LBER_CPE = %X'20'; literal MCHECK0302$M_LBER_CPE2 = %X'40'; literal MCHECK0302$M_LBER_CDPE = %X'80'; literal MCHECK0302$M_LBER_CDPE2 = %X'100'; literal MCHECK0302$M_LBER_TDE = %X'200'; literal MCHECK0302$M_LBER_STE = %X'400'; literal MCHECK0302$M_LBER_CNFE = %X'800'; literal MCHECK0302$M_LBER_NXAE = %X'1000'; literal MCHECK0302$M_LBER_CAE = %X'2000'; literal MCHECK0302$M_LBER_SHE = %X'4000'; literal MCHECK0302$M_LBER_DIE = %X'8000'; literal MCHECK0302$M_LBER_DTCE = %X'10000'; literal MCHECK0302$M_LBER_CTCE = %X'20000'; literal MCHECK0302$M_LBER_NSES = %X'40000'; literal MCHECK0302$S_LBER = 4; macro MCHECK0302$L_LBER = 0,0,32,0 %; macro MCHECK0302$V_LBER_E = 0,0,1,0 %; macro MCHECK0302$V_LBER_UCE = 0,1,1,0 %; macro MCHECK0302$V_LBER_UCE2 = 0,2,1,0 %; macro MCHECK0302$V_LBER_CE = 0,3,1,0 %; macro MCHECK0302$V_LBER_CE2 = 0,4,1,0 %; macro MCHECK0302$V_LBER_CPE = 0,5,1,0 %; macro MCHECK0302$V_LBER_CPE2 = 0,6,1,0 %; macro MCHECK0302$V_LBER_CDPE = 0,7,1,0 %; macro MCHECK0302$V_LBER_CDPE2 = 0,8,1,0 %; macro MCHECK0302$V_LBER_TDE = 0,9,1,0 %; macro MCHECK0302$V_LBER_STE = 0,10,1,0 %; macro MCHECK0302$V_LBER_CNFE = 0,11,1,0 %; macro MCHECK0302$V_LBER_NXAE = 0,12,1,0 %; macro MCHECK0302$V_LBER_CAE = 0,13,1,0 %; macro MCHECK0302$V_LBER_SHE = 0,14,1,0 %; macro MCHECK0302$V_LBER_DIE = 0,15,1,0 %; macro MCHECK0302$V_LBER_DTCE = 0,16,1,0 %; macro MCHECK0302$V_LBER_CTCE = 0,17,1,0 %; macro MCHECK0302$V_LBER_NSES = 0,18,1,0 %; literal MCHECK0302$M_LCNR_CEEN = %X'1'; literal MCHECK0302$M_LCNR_RSTSTAT = %X'10000000'; literal MCHECK0302$M_LCNR_NHALT = %X'20000000'; literal MCHECK0302$M_LCNR_NRST = %X'40000000'; literal MCHECK0302$M_LCNR_STF = %X'80000000'; literal MCHECK0302$S_LCNR = 4; macro MCHECK0302$L_LCNR = 0,0,32,0 %; macro MCHECK0302$V_LCNR_CEEN = 0,0,1,0 %; macro MCHECK0302$V_LCNR_RSTSTAT = 0,28,1,0 %; macro MCHECK0302$V_LCNR_NHALT = 0,29,1,0 %; macro MCHECK0302$V_LCNR_NRST = 0,30,1,0 %; macro MCHECK0302$V_LCNR_STF = 0,31,1,0 %; literal MCHECK0302$M_LDEV_DTYPE = %X'FFFF'; literal MCHECK0302$M_LDEV_DREV = %X'FFFF0000'; literal MCHECK0302$S_LDEV = 4; macro MCHECK0302$L_LDEV = 0,0,32,0 %; macro MCHECK0302$V_LDEV_DTYPE = 0,0,16,0 %; literal MCHECK0302$S_LDEV_DTYPE = 16; macro MCHECK0302$V_LDEV_DREV = 0,16,16,0 %; literal MCHECK0302$S_LDEV_DREV = 16; literal MCHECK0302$M_LBESR0_SYNDROME = %X'7F'; literal MCHECK0302$S_LBESR0 = 4; macro MCHECK0302$L_LBESR0 = 0,0,32,0 %; macro MCHECK0302$V_LBESR0_SYNDROME = 0,0,7,0 %; literal MCHECK0302$S_LBESR0_SYNDROME = 7; literal MCHECK0302$M_LBESR1_SYNDROME = %X'7F'; literal MCHECK0302$S_LBESR1 = 4; macro MCHECK0302$L_LBESR1 = 0,0,32,0 %; macro MCHECK0302$V_LBESR1_SYNDROME = 0,0,7,0 %; literal MCHECK0302$S_LBESR1_SYNDROME = 7; literal MCHECK0302$M_LBESR2_SYNDROME = %X'7F'; literal MCHECK0302$S_LBESR2 = 4; macro MCHECK0302$L_LBESR2 = 0,0,32,0 %; macro MCHECK0302$V_LBESR2_SYNDROME = 0,0,7,0 %; literal MCHECK0302$S_LBESR2_SYNDROME = 7; literal MCHECK0302$M_LBESR3_SYNDROME = %X'7F'; literal MCHECK0302$S_LBESR3 = 4; macro MCHECK0302$L_LBESR3 = 0,0,32,0 %; macro MCHECK0302$V_LBESR3_SYNDROME = 0,0,7,0 %; literal MCHECK0302$S_LBESR3_SYNDROME = 7; literal MCHECK0302$S_LBECR0 = 4; macro MCHECK0302$L_LBECR0 = 0,0,32,0 %; macro MCHECK0302$L_LBECR0_CA = 0,0,32,0 %; literal MCHECK0302$M_LBECR1_CA = %X'7'; literal MCHECK0302$M_LBECR1_CMD = %X'38'; literal MCHECK0302$M_LBECR1_RSVD = %X'780'; literal MCHECK0302$M_LBECR1_CID = %X'7800'; literal MCHECK0302$M_LBECR1_CNF = %X'8000'; literal MCHECK0302$M_LBECR1_SHARED = %X'10000'; literal MCHECK0302$M_LBECR1_DIRTY = %X'20000'; literal MCHECK0302$M_LBECR1_DCYCLE = %X'C0000'; literal MCHECK0302$S_LBECR1 = 4; macro MCHECK0302$L_LBECR1 = 0,0,32,0 %; macro MCHECK0302$V_LBECR1_CA = 0,0,3,0 %; literal MCHECK0302$S_LBECR1_CA = 3; macro MCHECK0302$V_LBECR1_CMD = 0,3,3,0 %; literal MCHECK0302$S_LBECR1_CMD = 3; macro MCHECK0302$V_LBECR1_PAR = 0,6,1,0 %; macro MCHECK0302$V_LBECR1_RSVD = 0,7,4,0 %; literal MCHECK0302$S_LBECR1_RSVD = 4; macro MCHECK0302$V_LBECR1_CID = 0,11,4,0 %; literal MCHECK0302$S_LBECR1_CID = 4; macro MCHECK0302$V_LBECR1_CNF = 0,15,1,0 %; macro MCHECK0302$V_LBECR1_SHARED = 0,16,1,0 %; macro MCHECK0302$V_LBECR1_DIRTY = 0,17,1,0 %; macro MCHECK0302$V_LBECR1_DCYCLE = 0,18,2,0 %; literal MCHECK0302$S_LBECR1_DCYCLE = 2; literal MCHECK0302$M_MCR_DTYPE = %X'1'; literal MCHECK0302$M_MCR_STRN = %X'C'; literal MCHECK0302$S_MCR = 4; ! Old size name, synonym for MCHECK0302$S_KA0302MCR literal MCHECK0302$S_KA0302MCR = 4; macro MCHECK0302$L_MCR = 0,0,32,0 %; macro MCHECK0302$V_MCR_DTYPE = 0,0,1,0 %; macro MCHECK0302$V_MCR_STRN = 0,2,2,0 %; literal MCHECK0302$S_MCR_STRN = 2; literal MCHECK0302$M_AMR_E = %X'1'; literal MCHECK0302$M_AMR_INTL = %X'6'; literal MCHECK0302$M_AMR_IA = %X'18'; literal MCHECK0302$M_AMR_AW = %X'1E0'; literal MCHECK0302$M_AMR_NBANKS = %X'600'; literal MCHECK0302$M_AMR_MADR = %X'FFFE0000'; literal MCHECK0302$S_AMR = 4; ! Old size name, synonym for MCHECK0302$S_KA0302AMR literal MCHECK0302$S_KA0302AMR = 4; macro MCHECK0302$L_AMR = 0,0,32,0 %; macro MCHECK0302$V_AMR_E = 0,0,1,0 %; macro MCHECK0302$V_AMR_INTL = 0,1,2,0 %; literal MCHECK0302$S_AMR_INTL = 2; macro MCHECK0302$V_AMR_IA = 0,3,2,0 %; literal MCHECK0302$S_AMR_IA = 2; macro MCHECK0302$V_AMR_AW = 0,5,4,0 %; literal MCHECK0302$S_AMR_AW = 4; macro MCHECK0302$V_AMR_NBANKS = 0,9,2,0 %; literal MCHECK0302$S_AMR_NBANKS = 2; macro MCHECK0302$V_AMR_MADR = 0,17,15,0 %; literal MCHECK0302$S_AMR_MADR = 15; literal MCHECK0302$S_MSTR0 = 4; macro MCHECK0302$L_MSTR0 = 0,0,32,0 %; literal MCHECK0302$S_MSTR1 = 4; macro MCHECK0302$L_MSTR1 = 0,0,32,0 %; literal MCHECK0302$S_FADR = 4; macro MCHECK0302$L_FADR = 0,0,32,0 %; literal MCHECK0302$M_MERA_CER = %X'1'; literal MCHECK0302$M_MERA_UCER = %X'2'; literal MCHECK0302$M_MERA_MULE = %X'4'; literal MCHECK0302$M_MERA_APER = %X'8'; literal MCHECK0302$M_MERA_CERA = %X'10'; literal MCHECK0302$M_MERA_CERB = %X'20'; literal MCHECK0302$M_MERA_FSTR = %X'1C0'; literal MCHECK0302$M_MERA_BNKER = %X'200'; literal MCHECK0302$M_MERA_UCERA = %X'400'; literal MCHECK0302$M_MERA_UCERB = %X'800'; literal MCHECK0302$S_MERA = 4; macro MCHECK0302$L_MERA = 0,0,32,0 %; macro MCHECK0302$V_MERA_CER = 0,0,1,0 %; macro MCHECK0302$V_MERA_UCER = 0,1,1,0 %; macro MCHECK0302$V_MERA_MULE = 0,2,1,0 %; macro MCHECK0302$V_MERA_APER = 0,3,1,0 %; macro MCHECK0302$V_MERA_CERA = 0,4,1,0 %; macro MCHECK0302$V_MERA_CERB = 0,5,1,0 %; macro MCHECK0302$V_MERA_FSTR = 0,6,3,0 %; literal MCHECK0302$S_MERA_FSTR = 3; macro MCHECK0302$V_MERA_BNKER = 0,9,1,0 %; macro MCHECK0302$V_MERA_UCERA = 0,10,1,0 %; macro MCHECK0302$V_MERA_UCERB = 0,11,1,0 %; literal MCHECK0302$M_MSYNDA_SYND = %X'FF'; literal MCHECK0302$S_MSYNDA = 4; macro MCHECK0302$L_MSYNDA = 0,0,32,0 %; macro MCHECK0302$V_MSYNDA_SYND = 0,0,8,0 %; literal MCHECK0302$S_MSYNDA_SYND = 8; literal MCHECK0302$M_MDRA_FCBS = %X'1'; literal MCHECK0302$M_MDRA_DRDC = %X'2'; literal MCHECK0302$M_MDRA_DWDC = %X'4'; literal MCHECK0302$M_MDRA_BPAS = %X'8'; literal MCHECK0302$M_MDRA_EXST = %X'10'; literal MCHECK0302$M_MDRA_STPM = %X'20'; literal MCHECK0302$M_MDRA_MODE = %X'40'; literal MCHECK0302$M_MDRA_IGSB = %X'80'; literal MCHECK0302$M_MDRA_FRPE = %X'100'; literal MCHECK0302$M_MDRA_FCPE = %X'200'; literal MCHECK0302$M_MDRA_DCRD = %X'8000000'; literal MCHECK0302$M_MDRA_RFR = %X'30000000'; literal MCHECK0302$M_MDRA_BRFSH = %X'40000000'; literal MCHECK0302$M_MDRA_DRFSH = %X'80000000'; literal MCHECK0302$S_MDRA = 4; macro MCHECK0302$L_MDRA = 0,0,32,0 %; macro MCHECK0302$V_MDRA_FCBS = 0,0,1,0 %; macro MCHECK0302$V_MDRA_DRDC = 0,1,1,0 %; macro MCHECK0302$V_MDRA_DWDC = 0,2,1,0 %; macro MCHECK0302$V_MDRA_BPAS = 0,3,1,0 %; macro MCHECK0302$V_MDRA_EXST = 0,4,1,0 %; macro MCHECK0302$V_MDRA_STPM = 0,5,1,0 %; macro MCHECK0302$V_MDRA_MODE = 0,6,1,0 %; macro MCHECK0302$V_MDRA_IGSB = 0,7,1,0 %; macro MCHECK0302$V_MDRA_FRPE = 0,8,1,0 %; macro MCHECK0302$V_MDRA_FCPE = 0,9,1,0 %; macro MCHECK0302$V_MDRA_DCRD = 0,27,1,0 %; macro MCHECK0302$V_MDRA_RFR = 0,28,2,0 %; literal MCHECK0302$S_MDRA_RFR = 2; macro MCHECK0302$V_MDRA_BRFSH = 0,30,1,0 %; macro MCHECK0302$V_MDRA_DRFSH = 0,31,1,0 %; literal MCHECK0302$M_MCBSA_SCB = %X'FF'; literal MCHECK0302$S_MCBSA = 4; macro MCHECK0302$L_MCBSA = 0,0,32,0 %; macro MCHECK0302$V_MCBSA_SCB = 0,0,8,0 %; literal MCHECK0302$S_MCBSA_SCB = 8; literal MCHECK0302$M_MERB_CER = %X'1'; literal MCHECK0302$M_MERB_UCER = %X'2'; literal MCHECK0302$M_MERB_MULE = %X'4'; literal MCHECK0302$M_MERB_APER = %X'8'; literal MCHECK0302$S_MERB = 4; macro MCHECK0302$L_MERB = 0,0,32,0 %; macro MCHECK0302$V_MERB_CER = 0,0,1,0 %; macro MCHECK0302$V_MERB_UCER = 0,1,1,0 %; macro MCHECK0302$V_MERB_MULE = 0,2,1,0 %; macro MCHECK0302$V_MERB_APER = 0,3,1,0 %; literal MCHECK0302$M_MSYNDB_SYND = %X'FF'; literal MCHECK0302$S_MSYNDB = 4; macro MCHECK0302$L_MSYNDB = 0,0,32,0 %; macro MCHECK0302$V_MSYNDB_SYND = 0,0,8,0 %; literal MCHECK0302$S_MSYNDB_SYND = 8; literal MCHECK0302$M_MDRB_FCBS = %X'1'; literal MCHECK0302$M_MDRB_DRDC = %X'2'; literal MCHECK0302$M_MDRB_DWDC = %X'4'; literal MCHECK0302$M_MDRB_BPAS = %X'8'; literal MCHECK0302$M_MDRB_EXST = %X'10'; literal MCHECK0302$M_MDRB_STPM = %X'20'; literal MCHECK0302$M_MDRB_MODE = %X'40'; literal MCHECK0302$M_MDRB_IGSB = %X'80'; literal MCHECK0302$S_MDRB = 4; macro MCHECK0302$L_MDRB = 0,0,32,0 %; macro MCHECK0302$V_MDRB_FCBS = 0,0,1,0 %; macro MCHECK0302$V_MDRB_DRDC = 0,1,1,0 %; macro MCHECK0302$V_MDRB_DWDC = 0,2,1,0 %; macro MCHECK0302$V_MDRB_BPAS = 0,3,1,0 %; macro MCHECK0302$V_MDRB_EXST = 0,4,1,0 %; macro MCHECK0302$V_MDRB_STPM = 0,5,1,0 %; macro MCHECK0302$V_MDRB_MODE = 0,6,1,0 %; macro MCHECK0302$V_MDRB_IGSB = 0,7,1,0 %; literal MCHECK0302$M_MCBSB_SCB = %X'FF'; literal MCHECK0302$S_MCBSB = 4; macro MCHECK0302$L_MCBSB = 0,0,32,0 %; macro MCHECK0302$V_MCBSB_SCB = 0,0,8,0 %; literal MCHECK0302$S_MCBSB_SCB = 8; literal CPU0302$K_ecc_max_count = 32; ! Note that %xB2D05E00 equals 5 minutes in 100 nanosecond units literal CPU0302$K_ecc_threshold = -1294967296; !*** MODULE $KA0402DEF *** literal KA0402$M_IOSLOT_SLOT0_SG = %X'1'; literal KA0402$M_IOSLOT_SLOT0_BM = %X'2'; literal KA0402$M_IOSLOT_SLOT0_PE = %X'4'; literal KA0402$M_IOSLOT_SLOT1_SG = %X'8'; literal KA0402$M_IOSLOT_SLOT1_BM = %X'10'; literal KA0402$M_IOSLOT_SLOT1_PE = %X'20'; literal KA0402$M_IOSLOT_SLOT2_SG = %X'40'; literal KA0402$M_IOSLOT_SLOT2_BM = %X'80'; literal KA0402$M_IOSLOT_SLOT2_PE = %X'100'; literal KA0402$M_IOSLOT_SLOT3_SG = %X'200'; literal KA0402$M_IOSLOT_SLOT3_BM = %X'400'; literal KA0402$M_IOSLOT_SLOT3_PE = %X'800'; literal KA0402$M_IOSLOT_SLOT4_SG = %X'1000'; literal KA0402$M_IOSLOT_SLOT4_BM = %X'2000'; literal KA0402$M_IOSLOT_SLOT4_PE = %X'4000'; literal KA0402$M_IOSLOT_SLOT5_SG = %X'8000'; literal KA0402$M_IOSLOT_SLOT5_BM = %X'10000'; literal KA0402$M_IOSLOT_SLOT5_PE = %X'20000'; literal KA0402$M_IOSLOT_SLOT6_SG = %X'40000'; literal KA0402$M_IOSLOT_SLOT6_BM = %X'80000'; literal KA0402$M_IOSLOT_SLOT6_PE = %X'100000'; literal KA0402$M_IOSLOT_CORE_SG = %X'200000'; literal KA0402$M_IOSLOT_CORE_BM = %X'400000'; literal KA0402$M_IOSLOT_CORE_PE = %X'800000'; literal KA0402$M_IOSLOT_CXTURBO_SG = %X'1000000'; literal KA0402$M_IOSLOT_CXTURBO_BM = %X'2000000'; literal KA0402$M_IOSLOT_CXTURBO_PE = %X'4000000'; literal KA0402$M_IOSLOT_RM_BYTE0 = %X'8000000'; literal KA0402$M_IOSLOT_RM_BYTE1 = %X'10000000'; literal KA0402$M_IOSLOT_RM_BYTE2 = %X'20000000'; literal KA0402$M_IOSLOT_RM_BYTE3 = %X'40000000'; literal KA0402$M_IOSLOT_RM_VALID = %X'80000000'; literal KA0402$M_TCCONFIG_MAGIC = %X'1F'; literal KA0402$M_TCCONFIG_PAGE_SIZE = %X'100'; literal KA0402$M_TCEREG_SLOT_ID = %X'F'; literal KA0402$M_TCEREG_SG = %X'10'; literal KA0402$M_TCEREG_BM = %X'20'; literal KA0402$M_TCEREG_PE = %X'40'; literal KA0402$M_TCEREG_LOCK = %X'80'; literal KA0402$M_TCEREG_OFFSET = %X'1F00'; literal KA0402$M_TCEREG_SYNDROME = %X'7F0000'; literal KA0402$M_TCEREG_WM_BYTE0 = %X'1000000'; literal KA0402$M_TCEREG_WM_BYTE1 = %X'2000000'; literal KA0402$M_TCEREG_WM_BYTE2 = %X'4000000'; literal KA0402$M_TCEREG_WM_BYTE3 = %X'8000000'; literal KA0402$M_TCEREG_W = %X'40000000'; literal KA0402$M_TCEREG_D = %X'80000000'; literal KA0402$M_IR_TC_INT = %X'1FF'; literal KA0402$M_IR_SEO = %X'80000'; literal KA0402$M_IR_DBF = %X'100000'; literal KA0402$M_IR_X2K = %X'200000'; literal KA0402$M_IR_TCR = %X'400000'; literal KA0402$M_IR_TPE = %X'800000'; literal KA0402$M_IR_TER = %X'1000000'; literal KA0402$M_IR_SBE = %X'2000000'; literal KA0402$M_IR_DBE = %X'4000000'; literal KA0402$M_IR_TO = %X'8000000'; literal KA0402$M_IR_TL = %X'10000000'; literal KA0402$M_IR_IA = %X'20000000'; literal KA0402$M_IR_NV = %X'40000000'; literal KA0402$M_IR_PE = %X'80000000'; literal KA0402$M_IC_TC_INT = %X'1FF'; literal KA0402$M_IC_SEO = %X'80000'; literal KA0402$M_IC_DBF = %X'100000'; literal KA0402$M_IC_X2K = %X'200000'; literal KA0402$M_IC_TCR = %X'400000'; literal KA0402$M_IC_TPE = %X'800000'; literal KA0402$M_IC_TER = %X'1000000'; literal KA0402$M_IC_SBE = %X'2000000'; literal KA0402$M_IC_DBE = %X'4000000'; literal KA0402$M_IC_TO = %X'8000000'; literal KA0402$M_IC_TL = %X'10000000'; literal KA0402$M_IC_IA = %X'20000000'; literal KA0402$M_IC_NV = %X'40000000'; literal KA0402$M_IC_PE = %X'80000000'; literal KA0402$M_LDP_DMA_PA_LO = %X'FFFE0'; literal KA0402$M_LDP_DMA_PA_HI = %X'FFF00000'; literal KA0402$M_SCOMM_TR_DMA_PA = %X'FFFFFFE0'; literal KA0402$M_SCOMM_RC_DMA_PA = %X'FFFFFFE0'; literal KA0402$M_PRINTER_TR_DMA_PA = %X'FFFFFFE0'; literal KA0402$M_PRINTER_RC_DMA_PA = %X'FFFFFFE0'; literal KA0402$M_ISDN_TR_DMA_PA = %X'FFFFFFE0'; literal KA0402$M_ISDN_TR_BUF_DMA_PA = %X'FFFFFFE0'; literal KA0402$M_ISDN_RC_DMA_PA = %X'FFFFFFE0'; literal KA0402$M_ISDN_RC_BUF_DMA_PA = %X'FFFFFFE0'; literal KA0402$M_SSR_LEDS = %X'FF'; literal KA0402$M_SSR_LANCE_RESET = %X'100'; literal KA0402$M_SSR_RTC_RESET = %X'400'; literal KA0402$M_SSR_SSC_RESET = %X'800'; literal KA0402$M_SSR_ISDN_RESET = %X'1000'; literal KA0402$M_SSR_10BASET_SEL = %X'2000'; literal KA0402$M_SSR_NI_LOOPBACK = %X'4000'; literal KA0402$M_SSR_TXDIS = %X'8000'; literal KA0402$M_SSR_LANCE_DMA_EN = %X'10000'; literal KA0402$M_SSR_ISDN_RC_DMA_EN = %X'80000'; literal KA0402$M_SSR_ISDN_TR_DMA_EN = %X'100000'; literal KA0402$M_SSR_PRINTER_RC_DMA_EN = %X'10000000'; literal KA0402$M_SSR_PRINTER_TR_DMA_EN = %X'20000000'; literal KA0402$M_SSR_COMM_RC_DMA_EN = %X'40000000'; literal KA0402$M_SSR_COMM_TR_DMA_EN = %X'80000000'; literal KA0402$M_SIR_HALT0 = %X'1'; literal KA0402$M_SIR_HALT1 = %X'2'; literal KA0402$M_SIR_ALT_CONSOLE = %X'8'; literal KA0402$M_SIR_SCC0_SI = %X'40'; literal KA0402$M_SIR_SCC1_SI = %X'80'; literal KA0402$M_SIR_NI_INTR = %X'100'; literal KA0402$M_SIR_ISDN_INTR = %X'2000'; literal KA0402$M_SIR_LANCE_DMA_RE = %X'10000'; literal KA0402$M_SIR_ISDN_DMA_MRE = %X'100000'; literal KA0402$M_SIR_ISDN_DMA_RC_INTR = %X'200000'; literal KA0402$M_SIR_ISDN_DMA_TR_INTR = %X'400000'; literal KA0402$M_SIR_PP_RC_DMA_OVR = %X'1000000'; literal KA0402$M_SIR_PP_RC_HP_INTR = %X'2000000'; literal KA0402$M_SIR_PP_TR_DMA_MRE = %X'4000000'; literal KA0402$M_SIR_PP_TR_PE_INTR = %X'8000000'; literal KA0402$M_SIR_COMM_RC_DMA_OVR = %X'10000000'; literal KA0402$M_SIR_COMM_RC_HP_INTR = %X'20000000'; literal KA0402$M_SIR_COMM_TR_DMA_MRE = %X'40000000'; literal KA0402$M_SIR_COMM_TR_PE_INTR = %X'80000000'; literal KA0402$M_SIMR_HALT0 = %X'1'; literal KA0402$M_SIMR_HALT1 = %X'2'; literal KA0402$M_SIMR_ALT_CONSOLE = %X'8'; literal KA0402$M_SIMR_SCC0_SI = %X'40'; literal KA0402$M_SIMR_SCC1_SI = %X'80'; literal KA0402$M_SIMR_NI_INTR = %X'100'; literal KA0402$M_SIMR_ISDN_INTR = %X'2000'; literal KA0402$M_SIMR_LANCE_DMA_RE = %X'10000'; literal KA0402$M_SIMR_ISDN_DMA_MRE = %X'100000'; literal KA0402$M_SIMR_ISDN_DMA_RC_INTR = %X'200000'; literal KA0402$M_SIMR_ISDN_DMA_TR_INTR = %X'400000'; literal KA0402$M_SIMR_PP_RC_DMA_OVR = %X'1000000'; literal KA0402$M_SIMR_PP_RC_HP_INTR = %X'2000000'; literal KA0402$M_SIMR_PP_TR_DMA_MRE = %X'4000000'; literal KA0402$M_SIMR_PP_TR_PE_INTR = %X'8000000'; literal KA0402$M_SIMR_COMM_RC_DMA_OVR = %X'10000000'; literal KA0402$M_SIMR_COMM_RC_HP_INTR = %X'20000000'; literal KA0402$M_SIMR_COMM_TR_DMA_MRE = %X'40000000'; literal KA0402$M_SIMR_COMM_TR_PE_INTR = %X'80000000'; literal KA0402$M_SADR_TC_ADDR = %X'1FFFFE0'; literal KA0402$M_ISDN_DATA_TR_DATA = %X'FFFFFF'; literal KA0402$M_ISDN_DATA_RC_DATA = %X'FFFFFF'; literal KA0402$M_LANCE_SLOT_CS = %X'F'; literal KA0402$M_LANCE_SLOT_HW_ADDR = %X'3F0'; literal KA0402$M_SCC0_SLOT_CS = %X'F'; literal KA0402$M_SCC0_SLOT_HW_ADDR = %X'3F0'; literal KA0402$M_SCC1_SLOT_CS = %X'F'; literal KA0402$M_SCC1_SLOT_HW_ADDR = %X'3F0'; literal KA0402$S_KA0402DEF = 434176; ! Old KA0402 size for compatibility literal KA0402$S_KA0402 = 434176; macro KA0402$L_IOSLOT = 0,0,32,1 %; ! Slot mode register macro KA0402$V_IOSLOT_SLOT0_SG = 0,0,1,0 %; macro KA0402$V_IOSLOT_SLOT0_BM = 0,1,1,0 %; macro KA0402$V_IOSLOT_SLOT0_PE = 0,2,1,0 %; macro KA0402$V_IOSLOT_SLOT1_SG = 0,3,1,0 %; macro KA0402$V_IOSLOT_SLOT1_BM = 0,4,1,0 %; macro KA0402$V_IOSLOT_SLOT1_PE = 0,5,1,0 %; macro KA0402$V_IOSLOT_SLOT2_SG = 0,6,1,0 %; macro KA0402$V_IOSLOT_SLOT2_BM = 0,7,1,0 %; macro KA0402$V_IOSLOT_SLOT2_PE = 0,8,1,0 %; macro KA0402$V_IOSLOT_SLOT3_SG = 0,9,1,0 %; macro KA0402$V_IOSLOT_SLOT3_BM = 0,10,1,0 %; macro KA0402$V_IOSLOT_SLOT3_PE = 0,11,1,0 %; macro KA0402$V_IOSLOT_SLOT4_SG = 0,12,1,0 %; macro KA0402$V_IOSLOT_SLOT4_BM = 0,13,1,0 %; macro KA0402$V_IOSLOT_SLOT4_PE = 0,14,1,0 %; macro KA0402$V_IOSLOT_SLOT5_SG = 0,15,1,0 %; macro KA0402$V_IOSLOT_SLOT5_BM = 0,16,1,0 %; macro KA0402$V_IOSLOT_SLOT5_PE = 0,17,1,0 %; macro KA0402$V_IOSLOT_SLOT6_SG = 0,18,1,0 %; macro KA0402$V_IOSLOT_SLOT6_BM = 0,19,1,0 %; macro KA0402$V_IOSLOT_SLOT6_PE = 0,20,1,0 %; macro KA0402$V_IOSLOT_CORE_SG = 0,21,1,0 %; macro KA0402$V_IOSLOT_CORE_BM = 0,22,1,0 %; macro KA0402$V_IOSLOT_CORE_PE = 0,23,1,0 %; macro KA0402$V_IOSLOT_CXTURBO_SG = 0,24,1,0 %; macro KA0402$V_IOSLOT_CXTURBO_BM = 0,25,1,0 %; macro KA0402$V_IOSLOT_CXTURBO_PE = 0,26,1,0 %; macro KA0402$V_IOSLOT_RM_BYTE0 = 0,27,1,0 %; macro KA0402$V_IOSLOT_RM_BYTE1 = 0,28,1,0 %; macro KA0402$V_IOSLOT_RM_BYTE2 = 0,29,1,0 %; macro KA0402$V_IOSLOT_RM_BYTE3 = 0,30,1,0 %; macro KA0402$V_IOSLOT_RM_VALID = 0,31,1,0 %; macro KA0402$L_TCCONFIG = 16,0,32,1 %; ! TC Configuration register macro KA0402$V_TCCONFIG_MAGIC = 16,0,5,0 %; literal KA0402$S_TCCONFIG_MAGIC = 5; macro KA0402$V_TCCONFIG_PAGE_SIZE = 16,8,1,0 %; macro KA0402$L_FADR = 32,0,32,1 %; ! Failing Address register macro KA0402$L_TCEREG = 48,0,32,1 %; ! Error register macro KA0402$V_TCEREG_SLOT_ID = 48,0,4,0 %; literal KA0402$S_TCEREG_SLOT_ID = 4; macro KA0402$V_TCEREG_SG = 48,4,1,0 %; macro KA0402$V_TCEREG_BM = 48,5,1,0 %; macro KA0402$V_TCEREG_PE = 48,6,1,0 %; macro KA0402$V_TCEREG_LOCK = 48,7,1,0 %; macro KA0402$V_TCEREG_OFFSET = 48,8,5,0 %; literal KA0402$S_TCEREG_OFFSET = 5; macro KA0402$V_TCEREG_SYNDROME = 48,16,7,0 %; literal KA0402$S_TCEREG_SYNDROME = 7; macro KA0402$V_TCEREG_WM_BYTE0 = 48,24,1,0 %; macro KA0402$V_TCEREG_WM_BYTE1 = 48,25,1,0 %; macro KA0402$V_TCEREG_WM_BYTE2 = 48,26,1,0 %; macro KA0402$V_TCEREG_WM_BYTE3 = 48,27,1,0 %; macro KA0402$V_TCEREG_W = 48,30,1,0 %; macro KA0402$V_TCEREG_D = 48,31,1,0 %; macro KA0402$L_MCR0 = 8192,0,32,1 %; ! Memory configuration 0 macro KA0402$L_MCR1 = 16384,0,32,1 %; ! Memory configuration 1 macro KA0402$L_MCR2 = 24576,0,32,1 %; ! Memory configuration 2 macro KA0402$L_MCR3 = 32768,0,32,1 %; ! Memory configuration 3 macro KA0402$L_MCR4 = 40960,0,32,1 %; ! Memory configuration 4 macro KA0402$L_MCR5 = 49152,0,32,1 %; ! Memory configuration 5 macro KA0402$L_MCR6 = 57344,0,32,1 %; ! Memory configuration 6 macro KA0402$L_MCR7 = 65536,0,32,1 %; ! Memory configuration 7 macro KA0402$L_IR = 73728,0,32,1 %; ! Interrupt register macro KA0402$V_IR_TC_INT = 73728,0,9,0 %; literal KA0402$S_IR_TC_INT = 9; macro KA0402$V_IR_SEO = 73728,19,1,0 %; macro KA0402$V_IR_DBF = 73728,20,1,0 %; macro KA0402$V_IR_X2K = 73728,21,1,0 %; macro KA0402$V_IR_TCR = 73728,22,1,0 %; macro KA0402$V_IR_TPE = 73728,23,1,0 %; macro KA0402$V_IR_TER = 73728,24,1,0 %; macro KA0402$V_IR_SBE = 73728,25,1,0 %; macro KA0402$V_IR_DBE = 73728,26,1,0 %; macro KA0402$V_IR_TO = 73728,27,1,0 %; macro KA0402$V_IR_TL = 73728,28,1,0 %; macro KA0402$V_IR_IA = 73728,29,1,0 %; macro KA0402$V_IR_NV = 73728,30,1,0 %; macro KA0402$V_IR_PE = 73728,31,1,0 %; macro KA0402$L_IC = 81920,0,32,1 %; ! Interrupt Cause register macro KA0402$V_IC_TC_INT = 81920,0,9,0 %; literal KA0402$S_IC_TC_INT = 9; macro KA0402$V_IC_SEO = 81920,19,1,0 %; macro KA0402$V_IC_DBF = 81920,20,1,0 %; macro KA0402$V_IC_X2K = 81920,21,1,0 %; macro KA0402$V_IC_TCR = 81920,22,1,0 %; macro KA0402$V_IC_TPE = 81920,23,1,0 %; macro KA0402$V_IC_TER = 81920,24,1,0 %; macro KA0402$V_IC_SBE = 81920,25,1,0 %; macro KA0402$V_IC_DBE = 81920,26,1,0 %; macro KA0402$V_IC_TO = 81920,27,1,0 %; macro KA0402$V_IC_TL = 81920,28,1,0 %; macro KA0402$V_IC_IA = 81920,29,1,0 %; macro KA0402$V_IC_NV = 81920,30,1,0 %; macro KA0402$V_IC_PE = 81920,31,1,0 %; macro KA0402$L_SG_MAP = 90112,0,32,1 %; ! Scatter/gather map (32 pages) macro KA0402$L_TCRESET = 352256,0,32,1 %; ! TC reset register macro KA0402$L_IOCTL_CSR = 360448,0,32,1 %; ! Core I/O base CSR address macro KA0402$L_LDP = 360512,0,32,1 %; ! Ethernet Lance DMA pointer macro KA0402$V_LDP_DMA_PA_LO = 360512,5,15,0 %; literal KA0402$S_LDP_DMA_PA_LO = 15; macro KA0402$V_LDP_DMA_PA_HI = 360512,20,12,0 %; literal KA0402$S_LDP_DMA_PA_HI = 12; macro KA0402$L_SCOMM_TR = 360544,0,32,1 %; ! Serial comm transmit port 1 DMA pointer macro KA0402$V_SCOMM_TR_DMA_PA = 360544,5,27,0 %; literal KA0402$S_SCOMM_TR_DMA_PA = 27; macro KA0402$L_SCOMM_RC = 360576,0,32,1 %; ! Serial comm receive port 1 DMA pointer macro KA0402$V_SCOMM_RC_DMA_PA = 360576,5,27,0 %; literal KA0402$S_SCOMM_RC_DMA_PA = 27; macro KA0402$L_PRINTER_TR = 360608,0,32,1 %; ! Printer transmit port DMA pointer macro KA0402$V_PRINTER_TR_DMA_PA = 360608,5,27,0 %; literal KA0402$S_PRINTER_TR_DMA_PA = 27; macro KA0402$L_PRINTER_RC = 360640,0,32,1 %; ! Printer receive port DMA pointer macro KA0402$V_PRINTER_RC_DMA_PA = 360640,5,27,0 %; literal KA0402$S_PRINTER_RC_DMA_PA = 27; macro KA0402$L_ISDN_TR = 360704,0,32,1 %; ! ISDN transmit DMA pointer macro KA0402$V_ISDN_TR_DMA_PA = 360704,5,27,0 %; literal KA0402$S_ISDN_TR_DMA_PA = 27; macro KA0402$L_ISDN_TR_BUF = 360736,0,32,1 %; ! ISDN transmit DMA buffer pointer macro KA0402$V_ISDN_TR_BUF_DMA_PA = 360736,5,27,0 %; literal KA0402$S_ISDN_TR_BUF_DMA_PA = 27; macro KA0402$L_ISDN_RC = 360768,0,32,1 %; ! ISDN receive DMA pointer macro KA0402$V_ISDN_RC_DMA_PA = 360768,5,27,0 %; literal KA0402$S_ISDN_RC_DMA_PA = 27; macro KA0402$L_ISDN_RC_BUF = 360800,0,32,1 %; ! ISDN receive DMA buffer pointer macro KA0402$V_ISDN_RC_BUF_DMA_PA = 360800,5,27,0 %; literal KA0402$S_ISDN_RC_BUF_DMA_PA = 27; macro KA0402$L_DATA0 = 360832,0,32,1 %; ! System Data Buffer 0 macro KA0402$L_DATA1 = 360864,0,32,1 %; ! System Data Buffer 1 macro KA0402$L_DATA2 = 360896,0,32,1 %; ! System Data Buffer 2 macro KA0402$L_DATA3 = 360928,0,32,1 %; ! System Data Buffer 3 macro KA0402$L_SSR = 360960,0,32,1 %; ! System support register macro KA0402$V_SSR_LEDS = 360960,0,8,0 %; literal KA0402$S_SSR_LEDS = 8; macro KA0402$V_SSR_LANCE_RESET = 360960,8,1,0 %; macro KA0402$V_SSR_RTC_RESET = 360960,10,1,0 %; macro KA0402$V_SSR_SSC_RESET = 360960,11,1,0 %; macro KA0402$V_SSR_ISDN_RESET = 360960,12,1,0 %; macro KA0402$V_SSR_10BASET_SEL = 360960,13,1,0 %; macro KA0402$V_SSR_NI_LOOPBACK = 360960,14,1,0 %; macro KA0402$V_SSR_TXDIS = 360960,15,1,0 %; macro KA0402$V_SSR_LANCE_DMA_EN = 360960,16,1,0 %; macro KA0402$V_SSR_ISDN_RC_DMA_EN = 360960,19,1,0 %; macro KA0402$V_SSR_ISDN_TR_DMA_EN = 360960,20,1,0 %; macro KA0402$V_SSR_PRINTER_RC_DMA_EN = 360960,28,1,0 %; macro KA0402$V_SSR_PRINTER_TR_DMA_EN = 360960,29,1,0 %; macro KA0402$V_SSR_COMM_RC_DMA_EN = 360960,30,1,0 %; macro KA0402$V_SSR_COMM_TR_DMA_EN = 360960,31,1,0 %; macro KA0402$L_SIR = 360992,0,32,1 %; ! System interrupt register macro KA0402$V_SIR_HALT0 = 360992,0,1,0 %; macro KA0402$V_SIR_HALT1 = 360992,1,1,0 %; macro KA0402$V_SIR_ALT_CONSOLE = 360992,3,1,0 %; macro KA0402$V_SIR_SCC0_SI = 360992,6,1,0 %; macro KA0402$V_SIR_SCC1_SI = 360992,7,1,0 %; macro KA0402$V_SIR_NI_INTR = 360992,8,1,0 %; macro KA0402$V_SIR_ISDN_INTR = 360992,13,1,0 %; macro KA0402$V_SIR_LANCE_DMA_RE = 360992,16,1,0 %; macro KA0402$V_SIR_ISDN_DMA_MRE = 360992,20,1,0 %; macro KA0402$V_SIR_ISDN_DMA_RC_INTR = 360992,21,1,0 %; macro KA0402$V_SIR_ISDN_DMA_TR_INTR = 360992,22,1,0 %; macro KA0402$V_SIR_PP_RC_DMA_OVR = 360992,24,1,0 %; macro KA0402$V_SIR_PP_RC_HP_INTR = 360992,25,1,0 %; macro KA0402$V_SIR_PP_TR_DMA_MRE = 360992,26,1,0 %; macro KA0402$V_SIR_PP_TR_PE_INTR = 360992,27,1,0 %; macro KA0402$V_SIR_COMM_RC_DMA_OVR = 360992,28,1,0 %; macro KA0402$V_SIR_COMM_RC_HP_INTR = 360992,29,1,0 %; macro KA0402$V_SIR_COMM_TR_DMA_MRE = 360992,30,1,0 %; macro KA0402$V_SIR_COMM_TR_PE_INTR = 360992,31,1,0 %; macro KA0402$L_SIMR = 361024,0,32,1 %; ! System interrupt mask register macro KA0402$V_SIMR_HALT0 = 361024,0,1,0 %; macro KA0402$V_SIMR_HALT1 = 361024,1,1,0 %; macro KA0402$V_SIMR_ALT_CONSOLE = 361024,3,1,0 %; macro KA0402$V_SIMR_SCC0_SI = 361024,6,1,0 %; macro KA0402$V_SIMR_SCC1_SI = 361024,7,1,0 %; macro KA0402$V_SIMR_NI_INTR = 361024,8,1,0 %; macro KA0402$V_SIMR_ISDN_INTR = 361024,13,1,0 %; macro KA0402$V_SIMR_LANCE_DMA_RE = 361024,16,1,0 %; macro KA0402$V_SIMR_ISDN_DMA_MRE = 361024,20,1,0 %; macro KA0402$V_SIMR_ISDN_DMA_RC_INTR = 361024,21,1,0 %; macro KA0402$V_SIMR_ISDN_DMA_TR_INTR = 361024,22,1,0 %; macro KA0402$V_SIMR_PP_RC_DMA_OVR = 361024,24,1,0 %; macro KA0402$V_SIMR_PP_RC_HP_INTR = 361024,25,1,0 %; macro KA0402$V_SIMR_PP_TR_DMA_MRE = 361024,26,1,0 %; macro KA0402$V_SIMR_PP_TR_PE_INTR = 361024,27,1,0 %; macro KA0402$V_SIMR_COMM_RC_DMA_OVR = 361024,28,1,0 %; macro KA0402$V_SIMR_COMM_RC_HP_INTR = 361024,29,1,0 %; macro KA0402$V_SIMR_COMM_TR_DMA_MRE = 361024,30,1,0 %; macro KA0402$V_SIMR_COMM_TR_PE_INTR = 361024,31,1,0 %; macro KA0402$L_SADR = 361056,0,32,1 %; ! System address register macro KA0402$V_SADR_TC_ADDR = 361056,5,20,0 %; literal KA0402$S_SADR_TC_ADDR = 20; macro KA0402$L_ISDN_DATA_TR = 361088,0,32,1 %; ! ISDN Data Transmit macro KA0402$V_ISDN_DATA_TR_DATA = 361088,0,24,0 %; literal KA0402$S_ISDN_DATA_TR_DATA = 24; macro KA0402$L_ISDN_DATA_RC = 361120,0,32,1 %; ! ISDN Data Receive macro KA0402$V_ISDN_DATA_RC_DATA = 361120,0,24,0 %; literal KA0402$S_ISDN_DATA_RC_DATA = 24; macro KA0402$L_LANCE_SLOT = 361152,0,32,1 %; ! Lance slot register macro KA0402$V_LANCE_SLOT_CS = 361152,0,4,0 %; literal KA0402$S_LANCE_SLOT_CS = 4; macro KA0402$V_LANCE_SLOT_HW_ADDR = 361152,4,6,0 %; literal KA0402$S_LANCE_SLOT_HW_ADDR = 6; macro KA0402$L_SCC0_SLOT = 361216,0,32,1 %; ! SCC0 slot register macro KA0402$V_SCC0_SLOT_CS = 361216,0,4,0 %; literal KA0402$S_SCC0_SLOT_CS = 4; macro KA0402$V_SCC0_SLOT_HW_ADDR = 361216,4,6,0 %; literal KA0402$S_SCC0_SLOT_HW_ADDR = 6; macro KA0402$L_SCC1_SLOT = 361248,0,32,1 %; ! SCC1 slot register macro KA0402$V_SCC1_SLOT_CS = 361248,0,4,0 %; literal KA0402$S_SCC1_SLOT_CS = 4; macro KA0402$V_SCC1_SLOT_HW_ADDR = 361248,4,6,0 %; literal KA0402$S_SCC1_SLOT_HW_ADDR = 6; macro KA0402$L_NI_ADR_ROM = 368640,0,32,1 %; ! Ethernet address ROM macro KA0402$L_LANCE_RDP = 376832,0,32,1 %; ! Lance ethernet CSR macro KA0402$L_LANCE_RAP = 376840,0,32,1 %; ! Lance ethernet CSR macro KA0402$L_SCC0B_COMM_RAP = 385024,0,32,1 %; ! Comm Port 1 RAP macro KA0402$L_SCC0B_COMM_DATA = 385032,0,32,1 %; ! Comm Port 1 data macro KA0402$L_SCC0A_MOUSE_RAP = 385040,0,32,1 %; ! Mouse RAP macro KA0402$L_SCC0A_MOUSE_DATA = 385048,0,32,1 %; ! Mouse port data register macro KA0402$L_SCC1B_PRINT_RAP = 393216,0,32,1 %; ! Printer Port 2 RAP macro KA0402$L_SCC1B_PRINT_DATA = 393224,0,32,1 %; ! Printer Port 2 data macro KA0402$L_SCC1A_KEY_RAP = 393232,0,32,1 %; ! Keyboard RAP macro KA0402$L_SCC1A_KEY_DATA = 393240,0,32,1 %; ! Keyboard port data register macro KA0402$L_RTC_SEC = 401408,0,32,1 %; ! TOY clock CSR--seconds macro KA0402$L_RTC_ALMS = 401416,0,32,1 %; ! TOY clock CSR--seconds alarm macro KA0402$L_RTC_MIN = 401424,0,32,1 %; ! TOY clock CSR--minutes macro KA0402$L_RTC_ALMN = 401432,0,32,1 %; ! TOY clock CSR--minutes alarm macro KA0402$L_RTC_HOUR = 401440,0,32,1 %; ! TOY clock CSR--hours macro KA0402$L_RTC_ALMH = 401448,0,32,1 %; ! TOY clock CSR--hours alarm macro KA0402$L_RTC_DOW = 401456,0,32,1 %; ! TOY clock CSR--day of week macro KA0402$L_RTC_DAY = 401464,0,32,1 %; ! TOY clock CSR--date of month macro KA0402$L_RTC_MON = 401472,0,32,1 %; ! TOY clock CSR--month macro KA0402$L_RTC_YEAR = 401480,0,32,1 %; ! TOY clock CSR--year macro KA0402$L_RTC_REGA = 401488,0,32,1 %; ! TOY clock CSR--register A macro KA0402$L_RTC_REGB = 401496,0,32,1 %; ! TOY clock CSR--register B macro KA0402$L_RTC_REGC = 401504,0,32,1 %; ! TOY clock CSR--register C macro KA0402$L_RTC_REGD = 401512,0,32,1 %; ! TOY clock CSR--register D macro KA0402$L_RTC_RAM = 401520,0,32,1 %; ! TOY clock CSR--base of BBU RAM macro KA0402$L_SCSI_HOST_ID = 401784,0,32,0 %; ! SCSI Host id for use by PKCDRIVER. macro KA0402$L_ISDN_AUDIO = 409600,0,32,1 %; ! ISDN audio chip CSR macro KA0402$L_IMASK_READ = 417792,0,32,0 %; ! Interrupt mask, read macro KA0402$L_IMASK_WRITE = 434172,0,32,0 %; ! Interrupt mask, write literal KA0402$M_SG_MAP_PPN = %X'1FFFFF'; literal KA0402$M_SG_MAP_P = %X'200000'; literal KA0402$M_SG_MAP_F = %X'400000'; literal KA0402$M_SG_MAP_V = %X'800000'; literal KA0402$S_SG_MAP_ENTRY_BITS = 3; macro KA0402$V_SG_MAP_PPN = 0,0,21,0 %; literal KA0402$S_SG_MAP_PPN = 21; macro KA0402$V_SG_MAP_P = 0,21,1,0 %; macro KA0402$V_SG_MAP_F = 0,22,1,0 %; macro KA0402$V_SG_MAP_V = 0,23,1,0 %; literal KA0402$M_SG_MAP_VA_LW_IN_PAGE = %X'1FFF'; literal KA0402$M_SG_MAP_VA_PAGE = %X'FFFE000'; literal KA0402$S_SG_MAP_VA_BITS = 4; macro KA0402$V_SG_MAP_VA_LW_IN_PAGE = 0,0,13,0 %; literal KA0402$S_SG_MAP_VA_LW_IN_PAGE = 13; macro KA0402$V_SG_MAP_VA_PAGE = 0,13,15,0 %; literal KA0402$S_SG_MAP_VA_PAGE = 15; literal KA0402$K_IO_SCB_VEC = 2048; literal KA0402$K_CORE_IO_TC_SLOT = 7; literal KA0402$K_CXTURBO_TC_SLOT = 8; literal KA0402$K_TC_SLOT0_VEC = 0; literal KA0402$K_TC_SLOT1_VEC = 1; literal KA0402$K_TC_SLOT2_VEC = 2; literal KA0402$K_TC_SLOT3_VEC = 3; literal KA0402$K_TC_SLOT4_VEC = 4; literal KA0402$K_TC_SLOT5_VEC = 5; literal KA0402$K_TC_SLOT6_VEC = 6; literal KA0402$K_ETHERNET_VEC = 7; literal KA0402$K_ISDN_VEC = 8; literal KA0402$K_CXTURBO_VEC = 9; literal KA0402$K_SCC_VEC = 10; literal KA0402$K_OPDRVR_XMIT = 11; literal KA0402$K_OPDRVR_RCV = 12; literal KA0402$K_TOTAL_VECTORS = 13; literal KA0402$M_MASK0 = %X'1'; literal KA0402$M_MASK1 = %X'2'; literal KA0402$M_MASK2 = %X'4'; literal KA0402$M_MASK3 = %X'8'; literal KA0402$S_BYTE_MASK_BITS = 1; macro KA0402$V_MASK0 = 0,0,1,0 %; macro KA0402$V_MASK1 = 0,1,1,0 %; macro KA0402$V_MASK2 = 0,2,1,0 %; macro KA0402$V_MASK3 = 0,3,1,0 %; ! The following definition defines an entry of a Saved Error Register Table. ! This table is pointed to by a cell in the Turbo ADP. The table is divided up ! into an entry for each slot. Each entry contains saved copies of IR, TCEREG, ! and FADR. The entries are written by the machine check handler on an error, and ! read by a driver (at some appropriate time) to determine if a TC error ! occurred. ! Define Saved Register Table Entry literal KA0402$M_SAVED_IR_TC_INT = %X'1FF'; literal KA0402$M_SAVED_IR_SEO = %X'80000'; literal KA0402$M_SAVED_IR_DBF = %X'100000'; literal KA0402$M_SAVED_IR_X2K = %X'200000'; literal KA0402$M_SAVED_IR_TCR = %X'400000'; literal KA0402$M_SAVED_IR_TPE = %X'800000'; literal KA0402$M_SAVED_IR_TER = %X'1000000'; literal KA0402$M_SAVED_IR_SBE = %X'2000000'; literal KA0402$M_SAVED_IR_DBE = %X'4000000'; literal KA0402$M_SAVED_IR_TO = %X'8000000'; literal KA0402$M_SAVED_IR_TL = %X'10000000'; literal KA0402$M_SAVED_IR_IA = %X'20000000'; literal KA0402$M_SAVED_IR_NV = %X'40000000'; literal KA0402$M_SAVED_IR_PE = %X'80000000'; literal KA0402$M_SAVED_TCEREG_SLOT_ID = %X'F'; literal KA0402$M_SAVED_TCEREG_SG = %X'10'; literal KA0402$M_SAVED_TCEREG_BM = %X'20'; literal KA0402$M_SAVED_TCEREG_PE = %X'40'; literal KA0402$M_SAVED_TCEREG_LOCK = %X'80'; literal KA0402$M_SAVED_TCEREG_OFFSET = %X'1F00'; literal KA0402$M_SAVED_TCEREG_SYNDROME = %X'7F0000'; literal KA0402$M_SAVED_TCEREG_WM_BYTE0 = %X'1000000'; literal KA0402$M_SAVED_TCEREG_WM_BYTE1 = %X'2000000'; literal KA0402$M_SAVED_TCEREG_WM_BYTE2 = %X'4000000'; literal KA0402$M_SAVED_TCEREG_WM_BYTE3 = %X'8000000'; literal KA0402$M_SAVED_TCEREG_W = %X'40000000'; literal KA0402$M_SAVED_TCEREG_D = %X'80000000'; literal KA0402$K_SAVED_REG_ENTRY_SIZE = 16; literal KA0402$S_SAVED_REG_ENTRY = 16; macro KA0402$L_SAVED_IR = 0,0,32,0 %; ! Interrupt reason macro KA0402$V_SAVED_IR_TC_INT = 0,0,9,0 %; literal KA0402$S_SAVED_IR_TC_INT = 9; macro KA0402$V_SAVED_IR_SEO = 0,19,1,0 %; macro KA0402$V_SAVED_IR_DBF = 0,20,1,0 %; macro KA0402$V_SAVED_IR_X2K = 0,21,1,0 %; macro KA0402$V_SAVED_IR_TCR = 0,22,1,0 %; macro KA0402$V_SAVED_IR_TPE = 0,23,1,0 %; macro KA0402$V_SAVED_IR_TER = 0,24,1,0 %; macro KA0402$V_SAVED_IR_SBE = 0,25,1,0 %; macro KA0402$V_SAVED_IR_DBE = 0,26,1,0 %; macro KA0402$V_SAVED_IR_TO = 0,27,1,0 %; macro KA0402$V_SAVED_IR_TL = 0,28,1,0 %; macro KA0402$V_SAVED_IR_IA = 0,29,1,0 %; macro KA0402$V_SAVED_IR_NV = 0,30,1,0 %; macro KA0402$V_SAVED_IR_PE = 0,31,1,0 %; macro KA0402$L_SAVED_TCEREG = 4,0,32,0 %; ! Error register macro KA0402$V_SAVED_TCEREG_SLOT_ID = 4,0,4,0 %; literal KA0402$S_SAVED_TCEREG_SLOT_ID = 4; macro KA0402$V_SAVED_TCEREG_SG = 4,4,1,0 %; macro KA0402$V_SAVED_TCEREG_BM = 4,5,1,0 %; macro KA0402$V_SAVED_TCEREG_PE = 4,6,1,0 %; macro KA0402$V_SAVED_TCEREG_LOCK = 4,7,1,0 %; macro KA0402$V_SAVED_TCEREG_OFFSET = 4,8,5,0 %; literal KA0402$S_SAVED_TCEREG_OFFSET = 5; macro KA0402$V_SAVED_TCEREG_SYNDROME = 4,16,7,0 %; literal KA0402$S_SAVED_TCEREG_SYNDROME = 7; macro KA0402$V_SAVED_TCEREG_WM_BYTE0 = 4,24,1,0 %; macro KA0402$V_SAVED_TCEREG_WM_BYTE1 = 4,25,1,0 %; macro KA0402$V_SAVED_TCEREG_WM_BYTE2 = 4,26,1,0 %; macro KA0402$V_SAVED_TCEREG_WM_BYTE3 = 4,27,1,0 %; macro KA0402$V_SAVED_TCEREG_W = 4,30,1,0 %; macro KA0402$V_SAVED_TCEREG_D = 4,31,1,0 %; macro KA0402$L_SAVED_FADR = 8,0,32,1 %; ! Failing Address ! Define indexes into error table. Indexes are 0 thru 10. ! The count of the number of entries is 11. literal KA0402$K_SLOT0_INDEX = 0; literal KA0402$K_SLOT1_INDEX = 1; literal KA0402$K_SLOT2_INDEX = 2; literal KA0402$K_SLOT3_INDEX = 3; literal KA0402$K_SLOT4_INDEX = 4; literal KA0402$K_SLOT5_INDEX = 5; literal KA0402$K_SCSI_INDEX = 6; literal KA0402$K_CORE_NI_INDEX = 7; literal KA0402$K_CORE_SLU_INDEX = 8; literal KA0402$K_CORE_ISDN_INDEX = 9; literal KA0402$K_CXTURBO_INDEX = 10; literal KA0402$K_SAVED_REG_ENTRY_COUNT = 11; !*** MODULE $KA0602DEF *** literal KA0602$M_COMBO_TOY_RTCA_RS0 = %X'1'; literal KA0602$M_COMBO_TOY_RTCA_RS1 = %X'2'; literal KA0602$M_COMBO_TOY_RTCA_RS2 = %X'4'; literal KA0602$M_COMBO_TOY_RTCA_RS3 = %X'8'; literal KA0602$M_COMBO_TOY_RTCA_DV0 = %X'10'; literal KA0602$M_COMBO_TOY_RTCA_DV1 = %X'20'; literal KA0602$M_COMBO_TOY_RTCA_DV2 = %X'40'; literal KA0602$M_COMBO_TOY_RTCA_UIP = %X'80'; literal KA0602$M_COMBO_TOY_RTCB_DSE = %X'1'; literal KA0602$M_COMBO_TOY_RTCB_2412 = %X'2'; literal KA0602$M_COMBO_TOY_RTCB_DM = %X'4'; literal KA0602$M_COMBO_TOY_RTCB_UIE = %X'10'; literal KA0602$M_COMBO_TOY_RTCB_AIE = %X'20'; literal KA0602$M_COMBO_TOY_RTCB_PIE = %X'40'; literal KA0602$M_COMBO_TOY_RTCB_SET = %X'80'; literal KA0602$M_COMBO_TOY_RTCC_UF = %X'10'; literal KA0602$M_COMBO_TOY_RTCC_AF = %X'20'; literal KA0602$M_COMBO_TOY_RTCC_PF = %X'40'; literal KA0602$M_COMBO_TOY_RTCC_IRQF = %X'80'; literal KA0602$M_COMBO_TOY_RTCD_VRT = %X'80'; literal KA0602$M_HAE_EISA_ADDR = %X'7F'; literal KA0602$M_SYSCTL_LEDS = %X'F'; literal KA0602$M_SYSCTL_IOR = %X'10'; literal KA0602$M_SYSCTL_ERRENB = %X'20'; literal KA0602$M_SYSCTL_MCNFG = %X'C0'; literal KA0602$M_INT1_OCW2_IRQ = %X'7'; literal KA0602$M_INT1_OCW2_SEL = %X'18'; literal KA0602$M_INT1_OCW2_EOI = %X'20'; literal KA0602$M_INT1_OCW2_SL = %X'40'; literal KA0602$M_INT1_OCW2_ROT = %X'80'; literal KA0602$M_INT1_OCW3_RIS = %X'1'; literal KA0602$M_INT1_OCW3_RR = %X'2'; literal KA0602$M_INT1_OCW3_P = %X'4'; literal KA0602$M_INT1_OCW3_SEL = %X'18'; literal KA0602$M_INT1_OCW3_SMM = %X'20'; literal KA0602$M_INT1_OCW3_ESMM = %X'40'; literal KA0602$M_INT1_OCW1_M0 = %X'1'; literal KA0602$M_INT1_OCW1_M1 = %X'2'; literal KA0602$M_INT1_OCW1_M2 = %X'4'; literal KA0602$M_INT1_OCW1_M3 = %X'8'; literal KA0602$M_INT1_OCW1_M4 = %X'10'; literal KA0602$M_INT1_OCW1_M5 = %X'20'; literal KA0602$M_INT1_OCW1_M6 = %X'40'; literal KA0602$M_INT1_OCW1_M7 = %X'80'; literal KA0602$M_INT2_OCW2_IRQ = %X'7'; literal KA0602$M_INT2_OCW2_SEL = %X'18'; literal KA0602$M_INT2_OCW2_EOI = %X'20'; literal KA0602$M_INT2_OCW2_SL = %X'40'; literal KA0602$M_INT2_OCW2_ROT = %X'80'; literal KA0602$M_INT2_OCW3_RIS = %X'1'; literal KA0602$M_INT2_OCW3_RR = %X'2'; literal KA0602$M_INT2_OCW3_P = %X'4'; literal KA0602$M_INT2_OCW3_SEL = %X'18'; literal KA0602$M_INT2_OCW3_SMM = %X'20'; literal KA0602$M_INT2_OCW3_ESMM = %X'40'; literal KA0602$M_INT2_OCW1_M0 = %X'1'; literal KA0602$M_INT2_OCW1_M1 = %X'2'; literal KA0602$M_INT2_OCW1_M2 = %X'4'; literal KA0602$M_INT2_OCW1_M3 = %X'8'; literal KA0602$M_INT2_OCW1_M4 = %X'10'; literal KA0602$M_INT2_OCW1_M5 = %X'20'; literal KA0602$M_INT2_OCW1_M6 = %X'40'; literal KA0602$M_INT2_OCW1_M7 = %X'80'; literal KA0602$S_KA0602DEF = 548865; ! Old size name, synonym for KA0602$S_KA0602 literal KA0602$S_KA0602 = 548865; macro KA0602$L_PORT_INDEX = 0,0,32,0 %; macro KA0602$b_fill0001 = 4,0,0,1 %; literal KA0602$s_fill0001 = 508; macro KA0602$L_PORT_DATA = 512,0,32,0 %; macro KA0602$b_fill0002 = 516,0,0,1 %; literal KA0602$s_fill0002 = 508; macro KA0602$L_COMBO_TOY_MINS = 1024,0,32,0 %; macro KA0602$b_fill0003 = 1028,0,0,1 %; literal KA0602$s_fill0003 = 508; macro KA0602$L_COMBO_TOY_AMINS = 1536,0,32,0 %; macro KA0602$b_fill0004 = 1540,0,0,1 %; literal KA0602$s_fill0004 = 508; macro KA0602$L_COMBO_TOY_HRS = 2048,0,32,0 %; macro KA0602$b_fill0005 = 2052,0,0,1 %; literal KA0602$s_fill0005 = 508; macro KA0602$L_COMBO_TOY_AHRS = 2560,0,32,0 %; macro KA0602$b_fill0006 = 2564,0,0,1 %; literal KA0602$s_fill0006 = 508; macro KA0602$L_COMBO_TOY_DAY = 3072,0,32,0 %; macro KA0602$b_fill0007 = 3076,0,0,1 %; literal KA0602$s_fill0007 = 508; macro KA0602$L_COMBO_TOY_MNTH = 3584,0,32,0 %; macro KA0602$b_fill0008 = 3588,0,0,1 %; literal KA0602$s_fill0008 = 508; macro KA0602$L_COMBO_TOY_YEAR = 4096,0,32,0 %; macro KA0602$b_fill0009 = 4100,0,0,1 %; literal KA0602$s_fill0009 = 508; macro KA0602$L_COMBO_TOY_RTCA = 4608,0,32,0 %; macro KA0602$V_COMBO_TOY_RTCA_RS0 = 4608,0,1,0 %; macro KA0602$V_COMBO_TOY_RTCA_RS1 = 4608,1,1,0 %; macro KA0602$V_COMBO_TOY_RTCA_RS2 = 4608,2,1,0 %; macro KA0602$V_COMBO_TOY_RTCA_RS3 = 4608,3,1,0 %; macro KA0602$V_COMBO_TOY_RTCA_DV0 = 4608,4,1,0 %; macro KA0602$V_COMBO_TOY_RTCA_DV1 = 4608,5,1,0 %; macro KA0602$V_COMBO_TOY_RTCA_DV2 = 4608,6,1,0 %; macro KA0602$V_COMBO_TOY_RTCA_UIP = 4608,7,1,0 %; macro KA0602$b_fill0010 = 4612,0,0,1 %; literal KA0602$s_fill0010 = 508; macro KA0602$L_COMBO_TOY_RTCB = 5120,0,32,0 %; macro KA0602$V_COMBO_TOY_RTCB_DSE = 5120,0,1,0 %; macro KA0602$V_COMBO_TOY_RTCB_2412 = 5120,1,1,0 %; macro KA0602$V_COMBO_TOY_RTCB_DM = 5120,2,1,0 %; macro KA0602$V_COMBO_TOY_RTCB_UIE = 5120,4,1,0 %; macro KA0602$V_COMBO_TOY_RTCB_AIE = 5120,5,1,0 %; macro KA0602$V_COMBO_TOY_RTCB_PIE = 5120,6,1,0 %; macro KA0602$V_COMBO_TOY_RTCB_SET = 5120,7,1,0 %; macro KA0602$b_fill0011 = 5124,0,0,1 %; literal KA0602$s_fill0011 = 508; macro KA0602$L_COMBO_TOY_RTCC = 5632,0,32,0 %; macro KA0602$V_COMBO_TOY_RTCC_UF = 5632,4,1,0 %; macro KA0602$V_COMBO_TOY_RTCC_AF = 5632,5,1,0 %; macro KA0602$V_COMBO_TOY_RTCC_PF = 5632,6,1,0 %; macro KA0602$V_COMBO_TOY_RTCC_IRQF = 5632,7,1,0 %; macro KA0602$b_fill0012 = 5636,0,0,1 %; literal KA0602$s_fill0012 = 508; macro KA0602$L_COMBO_TOY_RTCD = 6144,0,32,0 %; macro KA0602$V_COMBO_TOY_RTCD_VRT = 6144,7,1,0 %; macro KA0602$b_fill0013 = 6148,0,0,1 %; literal KA0602$s_fill0013 = 2044; macro KA0602$L_HAE = 8192,0,32,0 %; macro KA0602$V_HAE_EISA_ADDR = 8192,0,7,0 %; literal KA0602$S_HAE_EISA_ADDR = 7; macro KA0602$b_fill2aa = 8196,0,0,1 %; literal KA0602$s_fill2aa = 8188; macro KA0602$L_SYSCTL = 16384,0,32,0 %; macro KA0602$V_SYSCTL_LEDS = 16384,0,4,0 %; literal KA0602$S_SYSCTL_LEDS = 4; macro KA0602$V_SYSCTL_IOR = 16384,4,1,0 %; macro KA0602$V_SYSCTL_ERRENB = 16384,5,1,0 %; macro KA0602$V_SYSCTL_MCNFG = 16384,6,2,0 %; literal KA0602$S_SYSCTL_MCNFG = 2; macro KA0602$b_fill3 = 16388,0,0,1 %; literal KA0602$s_fill3 = 8188; macro KA0602$B_DMA1_CH0_CA = 24576,0,8,0 %; macro KA0602$b_fill4 = 24577,0,0,1 %; literal KA0602$s_fill4 = 4095; macro KA0602$B_INT1_OCW2 = 28672,0,8,0 %; macro KA0602$V_INT1_OCW2_IRQ = 28672,0,3,0 %; literal KA0602$S_INT1_OCW2_IRQ = 3; macro KA0602$V_INT1_OCW2_SEL = 28672,3,2,0 %; literal KA0602$S_INT1_OCW2_SEL = 2; macro KA0602$V_INT1_OCW2_EOI = 28672,5,1,0 %; macro KA0602$V_INT1_OCW2_SL = 28672,6,1,0 %; macro KA0602$V_INT1_OCW2_ROT = 28672,7,1,0 %; macro KA0602$V_INT1_OCW3_RIS = 28672,0,1,0 %; macro KA0602$V_INT1_OCW3_RR = 28672,1,1,0 %; macro KA0602$V_INT1_OCW3_P = 28672,2,1,0 %; macro KA0602$V_INT1_OCW3_SEL = 28672,3,2,0 %; literal KA0602$S_INT1_OCW3_SEL = 2; macro KA0602$V_INT1_OCW3_SMM = 28672,5,1,0 %; macro KA0602$V_INT1_OCW3_ESMM = 28672,6,1,0 %; macro KA0602$b_fill5 = 28673,0,0,1 %; literal KA0602$s_fill5 = 127; macro KA0602$B_INT1_OCW1 = 28800,0,8,0 %; macro KA0602$V_INT1_OCW1_M0 = 28800,0,1,0 %; macro KA0602$V_INT1_OCW1_M1 = 28800,1,1,0 %; macro KA0602$V_INT1_OCW1_M2 = 28800,2,1,0 %; macro KA0602$V_INT1_OCW1_M3 = 28800,3,1,0 %; macro KA0602$V_INT1_OCW1_M4 = 28800,4,1,0 %; macro KA0602$V_INT1_OCW1_M5 = 28800,5,1,0 %; macro KA0602$V_INT1_OCW1_M6 = 28800,6,1,0 %; macro KA0602$V_INT1_OCW1_M7 = 28800,7,1,0 %; macro KA0602$b_fill6 = 28801,0,0,1 %; literal KA0602$s_fill6 = 16255; macro KA0602$B_INT2_OCW2 = 45056,0,8,0 %; macro KA0602$V_INT2_OCW2_IRQ = 45056,0,3,0 %; literal KA0602$S_INT2_OCW2_IRQ = 3; macro KA0602$V_INT2_OCW2_SEL = 45056,3,2,0 %; literal KA0602$S_INT2_OCW2_SEL = 2; macro KA0602$V_INT2_OCW2_EOI = 45056,5,1,0 %; macro KA0602$V_INT2_OCW2_SL = 45056,6,1,0 %; macro KA0602$V_INT2_OCW2_ROT = 45056,7,1,0 %; macro KA0602$V_INT2_OCW3_RIS = 45056,0,1,0 %; macro KA0602$V_INT2_OCW3_RR = 45056,1,1,0 %; macro KA0602$V_INT2_OCW3_P = 45056,2,1,0 %; macro KA0602$V_INT2_OCW3_SEL = 45056,3,2,0 %; literal KA0602$S_INT2_OCW3_SEL = 2; macro KA0602$V_INT2_OCW3_SMM = 45056,5,1,0 %; macro KA0602$V_INT2_OCW3_ESMM = 45056,6,1,0 %; macro KA0602$b_fill7 = 45057,0,0,1 %; literal KA0602$s_fill7 = 127; macro KA0602$B_INT2_OCW1 = 45184,0,8,0 %; macro KA0602$V_INT2_OCW1_M0 = 45184,0,1,0 %; macro KA0602$V_INT2_OCW1_M1 = 45184,1,1,0 %; macro KA0602$V_INT2_OCW1_M2 = 45184,2,1,0 %; macro KA0602$V_INT2_OCW1_M3 = 45184,3,1,0 %; macro KA0602$V_INT2_OCW1_M4 = 45184,4,1,0 %; macro KA0602$V_INT2_OCW1_M5 = 45184,5,1,0 %; macro KA0602$V_INT2_OCW1_M6 = 45184,6,1,0 %; macro KA0602$V_INT2_OCW1_M7 = 45184,7,1,0 %; macro KA0602$b_fill8 = 45185,0,0,1 %; literal KA0602$s_fill8 = 503680; !*** MODULE $KA0702DEF *** literal KA0702$M_IR_SFB_INT = %X'4'; literal KA0702$M_IR_SCSI_INT = %X'8'; literal KA0702$M_IR_COREIO_INT = %X'10'; literal KA0702$M_IR_BC_TPE = %X'8000000'; literal KA0702$M_IR_TC_ORE = %X'10000000'; literal KA0702$M_IR_TC_TOE = %X'20000000'; literal KA0702$M_IR_BPE = %X'40000000'; literal KA0702$M_IR_MPE = %X'80000000'; literal KA0702$M_TCSR_AP0 = %X'1'; literal KA0702$M_TCSR_AP1 = %X'2'; literal KA0702$M_TCSR_AP2 = %X'4'; literal KA0702$M_TCSR_AP3 = %X'8'; literal KA0702$M_TCSR_AP4 = %X'10'; literal KA0702$M_MCR_SP0_SIZE = %X'1'; literal KA0702$M_MCR_SP1_SIZE = %X'2'; literal KA0702$M_MCR_SP2_SIZE = %X'4'; literal KA0702$M_MCR_SP3_SIZE = %X'8'; literal KA0702$M_LDP_DMA_PA_LO = %X'FFFE0'; literal KA0702$M_LDP_DMA_PA_HI = %X'FFF00000'; literal KA0702$M_SCOMM_TR_DMA_PA = %X'FFFFFFE0'; literal KA0702$M_SCOMM_RC_DMA_PA = %X'FFFFFFE0'; literal KA0702$M_PRINTER_TR_DMA_PA = %X'FFFFFFE0'; literal KA0702$M_PRINTER_RC_DMA_PA = %X'FFFFFFE0'; literal KA0702$M_ISDN_TR_DMA_PA = %X'FFFFFFE0'; literal KA0702$M_ISDN_TR_BUF_DMA_PA = %X'FFFFFFE0'; literal KA0702$M_ISDN_RC_DMA_PA = %X'FFFFFFE0'; literal KA0702$M_ISDN_RC_BUF_DMA_PA = %X'FFFFFFE0'; literal KA0702$M_SSR_IO_MASK = %X'F'; literal KA0702$M_SSR_IO_MASK_EN = %X'10'; literal KA0702$M_SSR_FPE = %X'80'; literal KA0702$M_SSR_LANCE_RESET = %X'100'; literal KA0702$M_SSR_RTC_RESET = %X'400'; literal KA0702$M_SSR_SCC_RESET = %X'800'; literal KA0702$M_SSR_ISDN_RESET = %X'1000'; literal KA0702$M_SSR_TXDIS = %X'8000'; literal KA0702$M_SSR_LANCE_DMA_EN = %X'10000'; literal KA0702$M_SSR_ISDN_RCV_EN = %X'80000'; literal KA0702$M_SSR_ISDN_TR_EN = %X'100000'; literal KA0702$M_SSR_SMR0 = %X'1000000'; literal KA0702$M_SSR_SMR1 = %X'2000000'; literal KA0702$M_SSR_SMRA = %X'4000000'; literal KA0702$M_SSR_FAST_MODE = %X'8000000'; literal KA0702$M_SSR_KBD_RC_DMA_EN = %X'10000000'; literal KA0702$M_SSR_KBD_TR_DMA_EN = %X'20000000'; literal KA0702$M_SSR_COMM_RC_DMA_EN = %X'40000000'; literal KA0702$M_SSR_COMM_TR_DMA_EN = %X'80000000'; literal KA0702$M_SIR_HALT0 = %X'1'; literal KA0702$M_SIR_HALT1 = %X'2'; literal KA0702$M_SIR_TC_SLOT0 = %X'4'; literal KA0702$M_SIR_TC_SLOT1 = %X'8'; literal KA0702$M_SIR_SCC0_INT = %X'40'; literal KA0702$M_SIR_SCC1_INT = %X'80'; literal KA0702$M_SIR_LANCE_INT = %X'100'; literal KA0702$M_SIR_ISDN_INT = %X'2000'; literal KA0702$M_SIR_CONS_SEL = %X'8000'; literal KA0702$M_SIR_LANCE_DMA_ER = %X'10000'; literal KA0702$M_SIR_ISDN_DMA_MRE = %X'100000'; literal KA0702$M_SIR_ISDN_DMA_RC_INTR = %X'200000'; literal KA0702$M_SIR_ISDN_DMA_TR_INTR = %X'400000'; literal KA0702$M_SIR_SCC1_DMA_OV = %X'1000000'; literal KA0702$M_SIR_SCC1_RCV_INT = %X'2000000'; literal KA0702$M_SIR_SCC1_TR_DMA_ME = %X'4000000'; literal KA0702$M_SIR_SCC1_TR_INT = %X'8000000'; literal KA0702$M_SIR_SCC0_DMA_OV = %X'10000000'; literal KA0702$M_SIR_SCC0_RCV_INT = %X'20000000'; literal KA0702$M_SIR_SCC0_TR_DMA_ME = %X'40000000'; literal KA0702$M_SIR_SCC0_TR_INT = %X'80000000'; literal KA0702$M_SIMR_HALT0 = %X'1'; literal KA0702$M_SIMR_HALT1 = %X'2'; literal KA0702$M_SIMR_TC_SLOT0 = %X'4'; literal KA0702$M_SIMR_TC_SLOT1 = %X'8'; literal KA0702$M_SIMR_SCC0_INT = %X'40'; literal KA0702$M_SIMR_SCC1_INT = %X'80'; literal KA0702$M_SIMR_LANCE_INT = %X'100'; literal KA0702$M_SIMR_ISDN_INT = %X'2000'; literal KA0702$M_SIMR_CONS_SEL = %X'8000'; literal KA0702$M_SIMR_LANCE_DMA_ER = %X'10000'; literal KA0702$M_SIMR_ISDN_DMA_MRE = %X'100000'; literal KA0702$M_SIMR_ISDN_DMA_RC_INTR = %X'200000'; literal KA0702$M_SIMR_ISDN_DMA_TR_INTR = %X'400000'; literal KA0702$M_SIMR_SCC1_DMA_OV = %X'1000000'; literal KA0702$M_SIMR_SCC1_RCV_INT = %X'2000000'; literal KA0702$M_SIMR_SCC1_TR_DMA_ME = %X'4000000'; literal KA0702$M_SIMR_SCC1_TR_INT = %X'8000000'; literal KA0702$M_SIMR_SCC0_DMA_OV = %X'10000000'; literal KA0702$M_SIMR_SCC0_RCV_INT = %X'20000000'; literal KA0702$M_SIMR_SCC0_TR_DMA_ME = %X'40000000'; literal KA0702$M_SIMR_SCC0_TR_INT = %X'80000000'; literal KA0702$M_SADR_TC_ADDR = %X'1FFFFE0'; literal KA0702$M_ISDN_DATA_TR_DATA = %X'FFFFFF'; literal KA0702$M_ISDN_DATA_RC_DATA = %X'FFFFFF'; literal KA0702$M_LANCE_SLOT_CS = %X'F'; literal KA0702$M_LANCE_SLOT_HW_ADDR = %X'3F0'; literal KA0702$M_SCC0_SLOT_CS = %X'F'; literal KA0702$M_SCC0_SLOT_HW_ADDR = %X'3F0'; literal KA0702$M_SCC1_SLOT_CS = %X'F'; literal KA0702$M_SCC1_SLOT_HW_ADDR = %X'3F0'; literal KA0702$M_MODE_FIELD = %X'7'; literal KA0702$M_BOOLOP_OP = %X'F'; literal KA0702$M_PIXELSHIFT_COUNT = %X'F'; literal KA0702$M_ADDR_REG_VALUE = %X'FFFFFF'; literal KA0702$M_BRES1_EI1 = %X'FFFF'; literal KA0702$M_BRES1_AI1 = %X'FFFF0000'; literal KA0702$M_BRES2_EI2 = %X'FFFF'; literal KA0702$M_BRES2_AI2 = %X'FFFF0000'; literal KA0702$M_BRES3_LL = %X'F'; literal KA0702$M_BRES3_IEV = %X'FFFF8000'; literal KA0702$M_DEEP_PLANE = %X'3'; literal KA0702$M_V_REF_COUNT_VC = %X'3FF'; literal KA0702$M_V_HOR_PIXELS = %X'1FF'; literal KA0702$M_V_HOR_FP = %X'3E00'; literal KA0702$M_V_HOR_SYNCH = %X'1FC000'; literal KA0702$M_V_HOR_BP = %X'FE00000'; literal KA0702$M_V_VER_SL = %X'7FF'; literal KA0702$M_V_VER_FP = %X'F800'; literal KA0702$M_V_VER_SYNCH = %X'3F0000'; literal KA0702$M_V_VER_BP = %X'FC00000'; literal KA0702$M_V_BASE_ADDR_ROW = %X'1FF'; literal KA0702$M_RAMDAC_ADDR_LO_BYTE0 = %X'FF'; literal KA0702$M_RAMDAC_ADDR_HI_BYTE0 = %X'FF'; literal KA0702$M_RAMDAC_REG_ADDR_BYTE0 = %X'FF'; literal KA0702$M_RAMDAC_MAP_LOC_BYTE0 = %X'FF'; literal KA0702$S_KA0702DEF = 2179072; ! Old size name, synonym for KA0702$S_KA0702 literal KA0702$S_KA0702 = 2179072; macro KA0702$L_IR = 0,0,32,0 %; ! Interrupt register macro KA0702$V_IR_SFB_INT = 0,2,1,0 %; macro KA0702$V_IR_SCSI_INT = 0,3,1,0 %; macro KA0702$V_IR_COREIO_INT = 0,4,1,0 %; macro KA0702$V_IR_BC_TPE = 0,27,1,0 %; macro KA0702$V_IR_TC_ORE = 0,28,1,0 %; macro KA0702$V_IR_TC_TOE = 0,29,1,0 %; macro KA0702$V_IR_BPE = 0,30,1,0 %; macro KA0702$V_IR_MPE = 0,31,1,0 %; macro KA0702$L_TCSR = 16,0,32,0 %; ! TC status and control register macro KA0702$V_TCSR_AP0 = 16,0,1,0 %; macro KA0702$V_TCSR_AP1 = 16,1,1,0 %; macro KA0702$V_TCSR_AP2 = 16,2,1,0 %; macro KA0702$V_TCSR_AP3 = 16,3,1,0 %; macro KA0702$V_TCSR_AP4 = 16,4,1,0 %; macro KA0702$L_MCR = 32,0,32,0 %; ! Memory Configuration Register macro KA0702$V_MCR_SP0_SIZE = 32,0,1,0 %; ! SIMM PAIR0 Size macro KA0702$V_MCR_SP1_SIZE = 32,1,1,0 %; ! SIMM PAIR1 Size macro KA0702$V_MCR_SP2_SIZE = 32,2,1,0 %; ! SIMM PAIR2 Size macro KA0702$V_MCR_SP3_SIZE = 32,3,1,0 %; ! SIMM PAIR3 Size macro KA0702$L_IOCTL_CSR = 8192,0,32,0 %; ! Core I/O base CSR address macro KA0702$L_LDP = 8256,0,32,0 %; ! Ethernet Lance DMA pointer macro KA0702$V_LDP_DMA_PA_LO = 8256,5,15,0 %; literal KA0702$S_LDP_DMA_PA_LO = 15; macro KA0702$V_LDP_DMA_PA_HI = 8256,20,12,0 %; literal KA0702$S_LDP_DMA_PA_HI = 12; macro KA0702$L_SCOMM_TR = 8288,0,32,0 %; ! Serial comm transmit port 1 DMA pointer macro KA0702$V_SCOMM_TR_DMA_PA = 8288,5,27,0 %; literal KA0702$S_SCOMM_TR_DMA_PA = 27; macro KA0702$L_SCOMM_RC = 8320,0,32,0 %; ! Serial comm receive port 1 DMA pointer macro KA0702$V_SCOMM_RC_DMA_PA = 8320,5,27,0 %; literal KA0702$S_SCOMM_RC_DMA_PA = 27; macro KA0702$L_PRINTER_TR = 8352,0,32,0 %; ! Printer transmit port DMA pointer macro KA0702$V_PRINTER_TR_DMA_PA = 8352,5,27,0 %; literal KA0702$S_PRINTER_TR_DMA_PA = 27; macro KA0702$L_PRINTER_RC = 8384,0,32,0 %; ! Printer receive port DMA pointer macro KA0702$V_PRINTER_RC_DMA_PA = 8384,5,27,0 %; literal KA0702$S_PRINTER_RC_DMA_PA = 27; macro KA0702$L_ISDN_TR = 8448,0,32,0 %; ! ISDN transmit DMA pointer macro KA0702$V_ISDN_TR_DMA_PA = 8448,5,27,0 %; literal KA0702$S_ISDN_TR_DMA_PA = 27; macro KA0702$L_ISDN_TR_BUF = 8480,0,32,0 %; ! ISDN transmit DMA buffer pointer macro KA0702$V_ISDN_TR_BUF_DMA_PA = 8480,5,27,0 %; literal KA0702$S_ISDN_TR_BUF_DMA_PA = 27; macro KA0702$L_ISDN_RC = 8512,0,32,0 %; ! ISDN receive DMA pointer macro KA0702$V_ISDN_RC_DMA_PA = 8512,5,27,0 %; literal KA0702$S_ISDN_RC_DMA_PA = 27; macro KA0702$L_ISDN_RC_BUF = 8544,0,32,0 %; ! ISDN receive DMA buffer pointer macro KA0702$V_ISDN_RC_BUF_DMA_PA = 8544,5,27,0 %; literal KA0702$S_ISDN_RC_BUF_DMA_PA = 27; macro KA0702$L_DATA0 = 8576,0,32,0 %; ! System Data Buffer 0 macro KA0702$L_DATA1 = 8608,0,32,0 %; ! System Data Buffer 1 macro KA0702$L_DATA2 = 8640,0,32,0 %; ! System Data Buffer 2 macro KA0702$L_DATA3 = 8672,0,32,0 %; ! System Data Buffer 3 macro KA0702$L_SSR = 8704,0,32,0 %; ! System support register macro KA0702$V_SSR_IO_MASK = 8704,0,4,0 %; literal KA0702$S_SSR_IO_MASK = 4; macro KA0702$V_SSR_IO_MASK_EN = 8704,4,1,0 %; macro KA0702$V_SSR_FPE = 8704,7,1,0 %; macro KA0702$V_SSR_LANCE_RESET = 8704,8,1,0 %; macro KA0702$V_SSR_RTC_RESET = 8704,10,1,0 %; macro KA0702$V_SSR_SCC_RESET = 8704,11,1,0 %; macro KA0702$V_SSR_ISDN_RESET = 8704,12,1,0 %; macro KA0702$V_SSR_TXDIS = 8704,15,1,0 %; macro KA0702$V_SSR_LANCE_DMA_EN = 8704,16,1,0 %; macro KA0702$V_SSR_ISDN_RCV_EN = 8704,19,1,0 %; macro KA0702$V_SSR_ISDN_TR_EN = 8704,20,1,0 %; macro KA0702$V_SSR_SMR0 = 8704,24,1,0 %; macro KA0702$V_SSR_SMR1 = 8704,25,1,0 %; macro KA0702$V_SSR_SMRA = 8704,26,1,0 %; macro KA0702$V_SSR_FAST_MODE = 8704,27,1,0 %; macro KA0702$V_SSR_KBD_RC_DMA_EN = 8704,28,1,0 %; macro KA0702$V_SSR_KBD_TR_DMA_EN = 8704,29,1,0 %; macro KA0702$V_SSR_COMM_RC_DMA_EN = 8704,30,1,0 %; macro KA0702$V_SSR_COMM_TR_DMA_EN = 8704,31,1,0 %; macro KA0702$L_SIR = 8736,0,32,0 %; ! System interrupt register macro KA0702$V_SIR_HALT0 = 8736,0,1,0 %; macro KA0702$V_SIR_HALT1 = 8736,1,1,0 %; macro KA0702$V_SIR_TC_SLOT0 = 8736,2,1,0 %; macro KA0702$V_SIR_TC_SLOT1 = 8736,3,1,0 %; macro KA0702$V_SIR_SCC0_INT = 8736,6,1,0 %; macro KA0702$V_SIR_SCC1_INT = 8736,7,1,0 %; macro KA0702$V_SIR_LANCE_INT = 8736,8,1,0 %; macro KA0702$V_SIR_ISDN_INT = 8736,13,1,0 %; macro KA0702$V_SIR_CONS_SEL = 8736,15,1,0 %; macro KA0702$V_SIR_LANCE_DMA_ER = 8736,16,1,0 %; macro KA0702$V_SIR_ISDN_DMA_MRE = 8736,20,1,0 %; macro KA0702$V_SIR_ISDN_DMA_RC_INTR = 8736,21,1,0 %; macro KA0702$V_SIR_ISDN_DMA_TR_INTR = 8736,22,1,0 %; macro KA0702$V_SIR_SCC1_DMA_OV = 8736,24,1,0 %; macro KA0702$V_SIR_SCC1_RCV_INT = 8736,25,1,0 %; macro KA0702$V_SIR_SCC1_TR_DMA_ME = 8736,26,1,0 %; macro KA0702$V_SIR_SCC1_TR_INT = 8736,27,1,0 %; macro KA0702$V_SIR_SCC0_DMA_OV = 8736,28,1,0 %; macro KA0702$V_SIR_SCC0_RCV_INT = 8736,29,1,0 %; macro KA0702$V_SIR_SCC0_TR_DMA_ME = 8736,30,1,0 %; macro KA0702$V_SIR_SCC0_TR_INT = 8736,31,1,0 %; macro KA0702$L_SIMR = 8768,0,32,0 %; ! System interrupt mask register macro KA0702$V_SIMR_HALT0 = 8768,0,1,0 %; macro KA0702$V_SIMR_HALT1 = 8768,1,1,0 %; macro KA0702$V_SIMR_TC_SLOT0 = 8768,2,1,0 %; macro KA0702$V_SIMR_TC_SLOT1 = 8768,3,1,0 %; macro KA0702$V_SIMR_SCC0_INT = 8768,6,1,0 %; macro KA0702$V_SIMR_SCC1_INT = 8768,7,1,0 %; macro KA0702$V_SIMR_LANCE_INT = 8768,8,1,0 %; macro KA0702$V_SIMR_ISDN_INT = 8768,13,1,0 %; macro KA0702$V_SIMR_CONS_SEL = 8768,15,1,0 %; macro KA0702$V_SIMR_LANCE_DMA_ER = 8768,16,1,0 %; macro KA0702$V_SIMR_ISDN_DMA_MRE = 8768,20,1,0 %; macro KA0702$V_SIMR_ISDN_DMA_RC_INTR = 8768,21,1,0 %; macro KA0702$V_SIMR_ISDN_DMA_TR_INTR = 8768,22,1,0 %; macro KA0702$V_SIMR_SCC1_DMA_OV = 8768,24,1,0 %; macro KA0702$V_SIMR_SCC1_RCV_INT = 8768,25,1,0 %; macro KA0702$V_SIMR_SCC1_TR_DMA_ME = 8768,26,1,0 %; macro KA0702$V_SIMR_SCC1_TR_INT = 8768,27,1,0 %; macro KA0702$V_SIMR_SCC0_DMA_OV = 8768,28,1,0 %; macro KA0702$V_SIMR_SCC0_RCV_INT = 8768,29,1,0 %; macro KA0702$V_SIMR_SCC0_TR_DMA_ME = 8768,30,1,0 %; macro KA0702$V_SIMR_SCC0_TR_INT = 8768,31,1,0 %; macro KA0702$L_SADR = 8800,0,32,0 %; ! System address register macro KA0702$V_SADR_TC_ADDR = 8800,5,20,0 %; literal KA0702$S_SADR_TC_ADDR = 20; macro KA0702$L_ISDN_DATA_TR = 8832,0,32,0 %; ! ISDN Data Transmit macro KA0702$V_ISDN_DATA_TR_DATA = 8832,0,24,0 %; literal KA0702$S_ISDN_DATA_TR_DATA = 24; macro KA0702$L_ISDN_DATA_RC = 8864,0,32,0 %; ! ISDN Data Receive macro KA0702$V_ISDN_DATA_RC_DATA = 8864,0,24,0 %; literal KA0702$S_ISDN_DATA_RC_DATA = 24; macro KA0702$L_LANCE_SLOT = 8896,0,32,0 %; ! Lance slot register macro KA0702$V_LANCE_SLOT_CS = 8896,0,4,0 %; literal KA0702$S_LANCE_SLOT_CS = 4; macro KA0702$V_LANCE_SLOT_HW_ADDR = 8896,4,6,0 %; literal KA0702$S_LANCE_SLOT_HW_ADDR = 6; macro KA0702$L_SCC0_SLOT = 8960,0,32,0 %; ! SCC0 slot register macro KA0702$V_SCC0_SLOT_CS = 8960,0,4,0 %; literal KA0702$S_SCC0_SLOT_CS = 4; macro KA0702$V_SCC0_SLOT_HW_ADDR = 8960,4,6,0 %; literal KA0702$S_SCC0_SLOT_HW_ADDR = 6; macro KA0702$L_SCC1_SLOT = 8992,0,32,0 %; ! SCC1 slot register macro KA0702$V_SCC1_SLOT_CS = 8992,0,4,0 %; literal KA0702$S_SCC1_SLOT_CS = 4; macro KA0702$V_SCC1_SLOT_HW_ADDR = 8992,4,6,0 %; literal KA0702$S_SCC1_SLOT_HW_ADDR = 6; macro KA0702$L_NI_ADR_ROM = 16384,0,32,0 %; ! Ethernet address ROM macro KA0702$L_LANCE_RDP = 24576,0,32,0 %; ! Lance ethernet CSR macro KA0702$L_LANCE_RAP = 24584,0,32,0 %; ! Lance ethernet CSR macro KA0702$L_SCC0B_COMM_RAP = 32768,0,32,0 %; ! Comm Port 1 RAP macro KA0702$L_SCC0B_COMM_DATA = 32776,0,32,0 %; ! Comm Port 1 data macro KA0702$L_SCC0A_MOUSE_RAP = 32784,0,32,0 %; ! Mouse RAP macro KA0702$L_SCC0A_MOUSE_DATA = 32792,0,32,0 %; ! Mouse port data register macro KA0702$L_SCC1B_PRINT_RAP = 40960,0,32,0 %; ! Printer Port 2 RAP macro KA0702$L_SCC1B_PRINT_DATA = 40968,0,32,0 %; ! Printer Port 2 data macro KA0702$L_SCC1A_KEY_RAP = 40976,0,32,0 %; ! Keyboard RAP macro KA0702$L_SCC1A_KEY_DATA = 40984,0,32,0 %; ! Keyboard port data register macro KA0702$L_RTC_SEC = 49152,0,32,0 %; ! TOY clock CSR--seconds macro KA0702$L_RTC_ALMS = 49160,0,32,0 %; ! TOY clock CSR--seconds alarm macro KA0702$L_RTC_MIN = 49168,0,32,0 %; ! TOY clock CSR--minutes macro KA0702$L_RTC_ALMN = 49176,0,32,0 %; ! TOY clock CSR--minutes alarm macro KA0702$L_RTC_HOUR = 49184,0,32,0 %; ! TOY clock CSR--hours macro KA0702$L_RTC_ALMH = 49192,0,32,0 %; ! TOY clock CSR--hours alarm macro KA0702$L_RTC_DOW = 49200,0,32,0 %; ! TOY clock CSR--day of week macro KA0702$L_RTC_DAY = 49208,0,32,0 %; ! TOY clock CSR--date of month macro KA0702$L_RTC_MON = 49216,0,32,0 %; ! TOY clock CSR--month macro KA0702$L_RTC_YEAR = 49224,0,32,0 %; ! TOY clock CSR--year macro KA0702$L_RTC_REGA = 49232,0,32,0 %; ! TOY clock CSR--register A macro KA0702$L_RTC_REGB = 49240,0,32,0 %; ! TOY clock CSR--register B macro KA0702$L_RTC_REGC = 49248,0,32,0 %; ! TOY clock CSR--register C macro KA0702$L_RTC_REGD = 49256,0,32,0 %; ! TOY clock CSR--register D macro KA0702$L_RTC_RAM = 49264,0,32,0 %; ! TOY clock CSR--base of BBU RAM macro KA0702$L_SCSI_HOST_ID = 49528,0,32,0 %; ! SCSI Host ID macro KA0702$L_ISDN_AUDIO = 57344,0,32,0 %; ! ISDN audio chip CSR macro KA0702$L_CPYBUF0 = 65536,0,32,0 %; ! Copy Buffer register macro KA0702$L_CPYBUF1 = 65544,0,32,0 %; ! Copy Buffer register macro KA0702$L_CPYBUF2 = 65552,0,32,0 %; ! Copy Buffer register macro KA0702$L_CPYBUF3 = 65560,0,32,0 %; ! Copy Buffer register macro KA0702$L_CPYBUF4 = 65568,0,32,0 %; ! Copy Buffer register macro KA0702$L_CPYBUF5 = 65576,0,32,0 %; ! Copy Buffer register macro KA0702$L_CPYBUF6 = 65584,0,32,0 %; ! Copy Buffer register macro KA0702$L_CPYBUF7 = 65592,0,32,0 %; ! Copy Buffer register macro KA0702$L_FG = 65600,0,32,0 %; ! Foreground macro KA0702$L_BG = 65608,0,32,0 %; ! Background macro KA0702$L_PLANEMASK = 65616,0,32,0 %; ! Planemask macro KA0702$L_PIXELMASK = 65624,0,32,0 %; ! Pixel Mask register macro KA0702$L_MODE = 65632,0,32,0 %; ! Mode register macro KA0702$V_MODE_FIELD = 65632,0,3,0 %; literal KA0702$S_MODE_FIELD = 3; macro KA0702$L_BOOLOP = 65640,0,32,0 %; ! Boolean Op register macro KA0702$V_BOOLOP_OP = 65640,0,4,0 %; literal KA0702$S_BOOLOP_OP = 4; macro KA0702$L_PIXELSHIFT = 65648,0,32,0 %; ! Pixel Shift register macro KA0702$V_PIXELSHIFT_COUNT = 65648,0,4,0 %; literal KA0702$S_PIXELSHIFT_COUNT = 4; macro KA0702$L_ADDR_REG = 65656,0,32,0 %; ! Address register macro KA0702$V_ADDR_REG_VALUE = 65656,0,24,0 %; literal KA0702$S_ADDR_REG_VALUE = 24; macro KA0702$L_BRES1 = 65664,0,32,0 %; ! Bresenham register 1 macro KA0702$V_BRES1_EI1 = 65664,0,16,0 %; literal KA0702$S_BRES1_EI1 = 16; macro KA0702$V_BRES1_AI1 = 65664,16,16,0 %; literal KA0702$S_BRES1_AI1 = 16; macro KA0702$L_BRES2 = 65672,0,32,0 %; ! Bresenham register 2 macro KA0702$V_BRES2_EI2 = 65672,0,16,0 %; literal KA0702$S_BRES2_EI2 = 16; macro KA0702$V_BRES2_AI2 = 65672,16,16,0 %; literal KA0702$S_BRES2_AI2 = 16; macro KA0702$L_BRES3 = 65680,0,32,0 %; ! Bresenham register 3 macro KA0702$V_BRES3_LL = 65680,0,4,0 %; literal KA0702$S_BRES3_LL = 4; macro KA0702$V_BRES3_IEV = 65680,15,17,0 %; literal KA0702$S_BRES3_IEV = 17; macro KA0702$L_BCONT = 65688,0,32,0 %; ! Bresenham continue macro KA0702$L_DEEP = 65696,0,32,0 %; ! Deep register macro KA0702$V_DEEP_PLANE = 65696,0,2,0 %; literal KA0702$S_DEEP_PLANE = 2; macro KA0702$L_START = 65704,0,32,0 %; ! Start register macro KA0702$L_CI = 65712,0,32,0 %; ! Clear interrupt macro KA0702$L_V_REF_COUNT = 65728,0,32,0 %; ! Video refresh count macro KA0702$V_V_REF_COUNT_VC = 65728,0,10,0 %; literal KA0702$S_V_REF_COUNT_VC = 10; macro KA0702$L_V_HOR = 65736,0,32,0 %; ! Video horizontal setup macro KA0702$V_V_HOR_PIXELS = 65736,0,9,0 %; literal KA0702$S_V_HOR_PIXELS = 9; macro KA0702$V_V_HOR_FP = 65736,9,5,0 %; literal KA0702$S_V_HOR_FP = 5; macro KA0702$V_V_HOR_SYNCH = 65736,14,7,0 %; literal KA0702$S_V_HOR_SYNCH = 7; macro KA0702$V_V_HOR_BP = 65736,21,7,0 %; literal KA0702$S_V_HOR_BP = 7; macro KA0702$L_V_VER = 65744,0,32,0 %; ! Video vertical setup macro KA0702$V_V_VER_SL = 65744,0,11,0 %; literal KA0702$S_V_VER_SL = 11; macro KA0702$V_V_VER_FP = 65744,11,5,0 %; literal KA0702$S_V_VER_FP = 5; macro KA0702$V_V_VER_SYNCH = 65744,16,6,0 %; literal KA0702$S_V_VER_SYNCH = 6; macro KA0702$V_V_VER_BP = 65744,22,6,0 %; literal KA0702$S_V_VER_BP = 6; macro KA0702$L_V_BASE_ADDR = 65752,0,32,0 %; ! Video Base Address macro KA0702$V_V_BASE_ADDR_ROW = 65752,0,9,0 %; literal KA0702$S_V_BASE_ADDR_ROW = 9; macro KA0702$L_VV = 65760,0,32,0 %; ! Video valid macro KA0702$L_EI = 65768,0,32,0 %; ! Enable interrupts macro KA0702$L_TCCLK_COUNT = 65776,0,32,0 %; ! TC clk count macro KA0702$L_VIDCLK_COUNT = 65784,0,32,0 %; ! TC clk count macro KA0702$L_RAMDAC_ADDR_LO = 73728,0,32,0 %; ! RAMDAC color map and registers macro KA0702$V_RAMDAC_ADDR_LO_BYTE0 = 73728,0,8,0 %; literal KA0702$S_RAMDAC_ADDR_LO_BYTE0 = 8; macro KA0702$L_RAMDAC_ADDR_HI = 73736,0,32,0 %; ! RAMDAC color map and registers macro KA0702$V_RAMDAC_ADDR_HI_BYTE0 = 73736,0,8,0 %; literal KA0702$S_RAMDAC_ADDR_HI_BYTE0 = 8; macro KA0702$L_RAMDAC_REG_ADDR = 73744,0,32,0 %; ! RAMDAC color map and registers macro KA0702$V_RAMDAC_REG_ADDR_BYTE0 = 73744,0,8,0 %; literal KA0702$S_RAMDAC_REG_ADDR_BYTE0 = 8; macro KA0702$L_RAMDAC_MAP_LOC = 73752,0,32,0 %; ! RAMDAC color map and registers macro KA0702$V_RAMDAC_MAP_LOC_BYTE0 = 73752,0,8,0 %; literal KA0702$S_RAMDAC_MAP_LOC_BYTE0 = 8; macro KA0702$L_FB = 81920,0,32,0 %; ! Video RAM (2 MB dense) literal KA0702$K_IO_SCB_VEC = 2048; literal KA0702$K_SCSI_TC_SLOT = 3; literal KA0702$K_CORE_IO_TC_SLOT = 4; literal KA0702$K_CXTURBO_TC_SLOT = 2; literal KA0702$K_TC_SLOT0_VEC = 0; literal KA0702$K_TC_SLOT1_VEC = 1; literal KA0702$K_TC_EMPTY2_VEC = 2; literal KA0702$K_TC_EMPTY3_VEC = 3; literal KA0702$K_TC_SLOT4_VEC = 4; literal KA0702$K_COREIO_VEC = 5; literal KA0702$K_SFB_VEC = 6; literal KA0702$K_ETHERNET_VEC = 7; literal KA0702$K_SCC_VEC = 8; literal KA0702$K_OPDRVR_XMIT = 9; literal KA0702$K_OPDRVR_RCV = 10; literal KA0702$K_ISDN_VEC = 11; literal KA0702$K_TOTAL_VECTORS = 12; literal KA0702$M_MASK0 = %X'1'; literal KA0702$M_MASK1 = %X'2'; literal KA0702$M_MASK2 = %X'4'; literal KA0702$M_MASK3 = %X'8'; literal KA0702$S_KA0702_MASK_BITS = 1; macro KA0702$V_MASK0 = 0,0,1,0 %; macro KA0702$V_MASK1 = 0,1,1,0 %; macro KA0702$V_MASK2 = 0,2,1,0 %; macro KA0702$V_MASK3 = 0,3,1,0 %; ! The following definition defines an entry of a Saved Error Register Table. ! This table is pointed to by a cell in the Turbo ADP. The table is divided up ! into an entry for each slot. Each entry contains saved copies of IR, TCEREG, ! and FADR. The entries are written by the machine check handler on an error, and ! read by a driver (at some appropriate time) to determine if a TC error ! occurred. ! Define Saved Register Table Entry literal KA0702$M_SAVED_IR_SFB_INT = %X'4'; literal KA0702$M_SAVED_IR_SCSI_INT = %X'8'; literal KA0702$M_SAVED_IR_COREIO_INT = %X'10'; literal KA0702$M_SAVED_IR_BC_TPE = %X'8000000'; literal KA0702$M_SAVED_IR_TC_ORE = %X'10000000'; literal KA0702$M_SAVED_IR_TC_TOE = %X'20000000'; literal KA0702$M_SAVED_IR_BPE = %X'40000000'; literal KA0702$M_SAVED_IR_MPE = %X'80000000'; literal KA0702$K_SAVED_REG_ENTRY_SIZE = 8; literal KA0702$S_KA0702_SAVED_REG = 8; macro KA0702$L_SAVED_IR = 0,0,32,0 %; ! Interrupt reason macro KA0702$V_SAVED_IR_SFB_INT = 0,2,1,0 %; macro KA0702$V_SAVED_IR_SCSI_INT = 0,3,1,0 %; macro KA0702$V_SAVED_IR_COREIO_INT = 0,4,1,0 %; macro KA0702$V_SAVED_IR_BC_TPE = 0,27,1,0 %; macro KA0702$V_SAVED_IR_TC_ORE = 0,28,1,0 %; macro KA0702$V_SAVED_IR_TC_TOE = 0,29,1,0 %; macro KA0702$V_SAVED_IR_BPE = 0,30,1,0 %; macro KA0702$V_SAVED_IR_MPE = 0,31,1,0 %; ! Define indexes into error table. Indexes are 0 thru 10. ! The count of the number of entries is 11. literal KA0702$K_SLOT0_INDEX = 0; literal KA0702$K_SLOT1_INDEX = 1; literal KA0702$K_SLOT2_INDEX = 2; literal KA0702$K_SLOT3_INDEX = 3; literal KA0702$K_SCSI_INDEX = 4; literal KA0702$K_COREIO_INDEX = 5; literal KA0702$K_CXTURBO_INDEX = 6; literal KA0702$K_SAVED_REG_ENTRY_COUNT = 7; !*** MODULE $KA0802DEF *** literal KA0802$M_APC_HAE = %X'1F'; literal KA0802$M_APC_INTERVAL_TIMER = %X'FFFF'; literal KA0802$M_APC_BUFFER_STATUS_E = %X'1'; literal KA0802$M_APC_BUFFER_STATUS_O = %X'2'; literal KA0802$M_APC_BUFFER_STATUS_M = %X'4'; literal KA0802$M_APC_BUFFER_STATUS_H = %X'8'; literal KA0802$M_APC_ERROR_STATUS = %X'FFFF'; literal KA0802$M_APC_ERROR_MASK = %X'FFFF'; literal KA0802$M_APC_LAST_PREFIX_LEN = %X'60'; literal KA0802$M_APC_LAST_PREFIX_OFF = %X'180'; literal KA0802$M_APC_LAST_PREFIX_CYCLE = %X'E00'; literal KA0802$M_APC_LAST_PREFIX_fill1 = %X'1000'; literal KA0802$M_APC_LAST_PREFIX_A = %X'2000'; literal KA0802$M_APC_LAST_PREFIX_E = %X'4000'; literal KA0802$M_APC_LAST_PREFIX_RW = %X'8000'; literal KA0802$M_APC_LAST_PREFIX_V = %X'10000'; literal KA0802$M_APC_LAST_PREFIX_fill2 = %X'FFFE0000'; literal KA0802$M_APC_LOCK_ADDRESS_L = %X'1'; literal KA0802$M_APC_LOCK_ADDRESS = %X'FFFFFFE0'; literal KA0802$M_APC_PREFIX_LEN = %X'18'; literal KA0802$M_APC_PREFIX_OFF = %X'60'; literal KA0802$M_APC_PREFIX_SUB_FOR_10 = %X'180'; literal KA0802$M_APC_PREFIX_CYCLE = %X'E00'; literal KA0802$M_APC_PREFIX_SUB_87_EN = %X'1000'; literal KA0802$M_APC_PREFIX_SUB_11_9_EN = %X'2000'; literal KA0802$S_KA0802DEF = 32768; ! Old KA0802 size for compatibility literal KA0802$S_KA0802 = 32768; macro KA0802$L_APC_HAE = 0,0,32,1 %; macro KA0802$V_APC_HAE = 0,0,5,0 %; literal KA0802$S_APC_HAE = 5; macro KA0802$L_APC_INTERVAL_TIMER = 128,0,32,1 %; macro KA0802$V_APC_INTERVAL_TIMER = 128,0,16,0 %; literal KA0802$S_APC_INTERVAL_TIMER = 16; macro KA0802$L_APC_BUFFER_STATUS = 192,0,32,1 %; macro KA0802$V_APC_BUFFER_STATUS_E = 192,0,1,0 %; macro KA0802$V_APC_BUFFER_STATUS_O = 192,1,1,0 %; macro KA0802$V_APC_BUFFER_STATUS_M = 192,2,1,0 %; macro KA0802$V_APC_BUFFER_STATUS_H = 192,3,1,0 %; macro KA0802$L_APC_ERROR_STATUS = 256,0,32,1 %; macro KA0802$V_APC_ERROR_STATUS = 256,0,16,0 %; literal KA0802$S_APC_ERROR_STATUS = 16; macro KA0802$L_APC_ERROR_MASK = 320,0,32,1 %; macro KA0802$V_APC_ERROR_MASK = 320,0,16,0 %; literal KA0802$S_APC_ERROR_MASK = 16; macro KA0802$L_APC_LAST_PREFIX = 384,0,32,1 %; macro KA0802$V_APC_LAST_PREFIX_LEN = 384,5,2,0 %; literal KA0802$S_APC_LAST_PREFIX_LEN = 2; macro KA0802$V_APC_LAST_PREFIX_OFF = 384,7,2,0 %; literal KA0802$S_APC_LAST_PREFIX_OFF = 2; macro KA0802$V_APC_LAST_PREFIX_CYCLE = 384,9,3,0 %; literal KA0802$S_APC_LAST_PREFIX_CYCLE = 3; macro KA0802$V_APC_LAST_PREFIX_fill1 = 384,12,1,0 %; macro KA0802$V_APC_LAST_PREFIX_A = 384,13,1,0 %; macro KA0802$V_APC_LAST_PREFIX_E = 384,14,1,0 %; macro KA0802$V_APC_LAST_PREFIX_RW = 384,15,1,0 %; macro KA0802$V_APC_LAST_PREFIX_V = 384,16,1,0 %; macro KA0802$V_APC_LAST_PREFIX_fill2 = 384,17,15,0 %; literal KA0802$S_APC_LAST_PREFIX_fill2 = 15; macro KA0802$L_APC_LOCK_ADDRESS = 448,0,32,1 %; macro KA0802$V_APC_LOCK_ADDRESS_L = 448,0,1,0 %; macro KA0802$V_APC_LOCK_ADDRESS = 448,5,27,0 %; literal KA0802$S_APC_LOCK_ADDRESS = 27; macro KA0802$L_APC_LOCAL_DEVICE_PORT = 512,0,32,1 %; macro KA0802$L_APC_MISC_DATA0 = 640,0,32,1 %; macro KA0802$L_APC_MISC_DATA1 = 704,0,32,1 %; macro KA0802$L_APC_PREFIX = 8192,0,32,1 %; macro KA0802$V_APC_PREFIX_LEN = 8192,3,2,0 %; literal KA0802$S_APC_PREFIX_LEN = 2; macro KA0802$V_APC_PREFIX_OFF = 8192,5,2,0 %; literal KA0802$S_APC_PREFIX_OFF = 2; macro KA0802$V_APC_PREFIX_SUB_FOR_10 = 8192,7,2,0 %; literal KA0802$S_APC_PREFIX_SUB_FOR_10 = 2; macro KA0802$V_APC_PREFIX_CYCLE = 8192,9,3,0 %; literal KA0802$S_APC_PREFIX_CYCLE = 3; macro KA0802$V_APC_PREFIX_SUB_87_EN = 8192,12,1,0 %; macro KA0802$V_APC_PREFIX_SUB_11_9_EN = 8192,13,1,0 %; macro KA0802$L_APC_CACHE_CONTROL = 24576,0,32,1 %; macro KA0802$L_APC_PCI_CONFIG = 24704,0,32,1 %; macro KA0802$L_APC_PCI_STATUS = 24768,0,32,1 %; macro KA0802$L_APC_MEM_BANK_01 = 24832,0,32,1 %; macro KA0802$L_APC_MEM_BANK_23 = 24864,0,32,1 %; macro KA0802$L_APC_MEM_BANK_45 = 24896,0,32,1 %; macro KA0802$L_APC_MEM_BANK_67 = 24928,0,32,1 %; macro KA0802$L_APC_MEM_CONTROL = 24960,0,32,1 %; macro KA0802$L_APC_EXT_PC_HOLE = 25024,0,32,1 %; macro KA0802$L_APC_EXT_PROG_HOLE = 25056,0,32,1 %; macro KA0802$L_APC_DIAG_CONTROL = 25088,0,32,1 %; macro KA0802$L_APC_DIAG_DATA0 = 25216,0,32,1 %; macro KA0802$L_APC_DIAG_DATA1 = 25280,0,32,1 %; macro KA0802$L_APC_REV_LEVEL = 25344,0,32,1 %; macro KA0802$L_APC_PARITY_CONTROL = 25408,0,32,1 %; macro KA0802$L_APC_SM_ADDRESS = 25600,0,32,1 %; macro KA0802$L_APC_SM_DATA = 25664,0,32,1 %; !*** MODULE $KA0902DEF *** literal KA0902$K_MAX_CPU_MODULES = 4; literal KA0902$K_MAX_MEMORY_MODULES = 4; literal KA0902$K_OPDRIVER_RCV_ISR = 6; literal KA0902$K_OPDRIVER_XMT_ISR = 15; literal KA0902_IIO$M_IOCSR_EN_LDEN = %X'1'; literal KA0902_IIO$M_IOCSR_EL = %X'2'; literal KA0902_IIO$M_IOCSR_ESMV = %X'4'; literal KA0902_IIO$M_IOCSR_PDBP = %X'8'; literal KA0902_IIO$M_IOCSR_PCIPRST0 = %X'10'; literal KA0902_IIO$M_IOCSR_PCIPRST1 = %X'20'; literal KA0902_IIO$M_IOCSR_INT = %X'40'; literal KA0902_IIO$M_IOCSR_TLBEE = %X'80'; literal KA0902_IIO$M_IOCSR_CXACK = %X'100'; literal KA0902_IIO$M_IOCSR_FILL2 = %X'200'; literal KA0902_IIO$M_IOCSR_EXEX = %X'400'; literal KA0902_IIO$M_IOCSR_FILL3 = %X'800'; literal KA0902_IIO$M_IOCSR_CAWWP0 = %X'1000'; literal KA0902_IIO$M_IOCSR_CAWWP2 = %X'2000'; literal KA0902_IIO$M_IOCSR_DWWPE = %X'4000'; literal KA0902_IIO$M_IOCSR_MBA5 = %X'8000'; literal KA0902_IIO$M_IOCSR_MBA6 = %X'10000'; literal KA0902_IIO$M_IOCSR_MBA7 = %X'20000'; literal KA0902_IIO$M_IOCSR_PCIPRST3 = %X'40000'; literal KA0902_IIO$M_IOCSR_PCIPRST4 = %X'80000'; literal KA0902_IIO$M_IOCSR_PDWWP1 = %X'100000'; literal KA0902_IIO$M_IOCSR_PDWWP0 = %X'200000'; literal KA0902_IIO$M_IOCSR_PBR = %X'400000'; literal KA0902_IIO$M_IOCSR_PIR = %X'800000'; literal KA0902_IIO$M_IOCSR_ENCOI = %X'1000000'; literal KA0902_IIO$M_IOCSR_EPMS = %X'2000000'; literal KA0902_IIO$M_IOCSR_ETLB = %X'4000000'; literal KA0902_IIO$M_IOCSR_EACC = %X'8000000'; literal KA0902_IIO$M_IOCSR_FTLB = %X'10000000'; literal KA0902_IIO$M_IOCSR_ECPC = %X'20000000'; literal KA0902_IIO$M_IOCSR_CIR = %X'40000000'; literal KA0902_IIO$M_IOCSR_EPL = %X'80000000'; literal KA0902_IIO$M_IOCSR_CBBCE = %X'1'; literal KA0902_IIO$M_IOCSR_TRN = %X'E'; literal KA0902_IIO$M_IOCSR_SMVL = %X'70'; literal KA0902_IIO$M_IOCSR_MBA4 = %X'80'; literal KA0902_IIO$M_IOCSR_EPR = %X'100'; literal KA0902_IIO$M_IOCSR_RDPE64 = %X'200'; literal KA0902_IIO$M_IOCSR_ADPE64 = %X'400'; literal KA0902_IIO$M_IOCSR_WDPE64 = %X'800'; literal KA0902_IIO$M_IOCSR_CAWWP1 = %X'1000'; literal KA0902_IIO$M_IOCSR_CAWWP3 = %X'2000'; literal KA0902_IIO$M_IOCSR_DWWPO = %X'4000'; literal KA0902_IIO$M_IOCSR_T24ST = %X'8000'; literal KA0902_IIO$M_IOCSR_PPC1 = %X'10000'; literal KA0902_IIO$M_IOCSR_PPC2 = %X'20000'; literal KA0902_IIO$M_IOCSR_STALL = %X'40000'; literal KA0902_IIO$M_IOCSR_FILL4 = %X'80000'; literal KA0902_IIO$M_IOCSR_PRM = %X'100000'; literal KA0902_IIO$M_IOCSR_PWM = %X'200000'; literal KA0902_IIO$M_IOCSR_FPRDPED = %X'400000'; literal KA0902_IIO$M_IOCSR_FPADPED = %X'800000'; literal KA0902_IIO$M_IOCSR_FPWDPED = %X'1000000'; literal KA0902_IIO$M_IOCSR_EPNMI = %X'2000000'; literal KA0902_IIO$M_IOCSR_EPDTI = %X'4000000'; literal KA0902_IIO$M_IOCSR_EPSEI = %X'8000000'; literal KA0902_IIO$M_IOCSR_EPPEI = %X'10000000'; literal KA0902_IIO$M_IOCSR_ERDPC = %X'20000000'; literal KA0902_IIO$M_IOCSR_EPADPC = %X'40000000'; literal KA0902_IIO$M_IOCSR_EWDPC = %X'80000000'; literal KA0902_IIO$M_CERR1_URE = %X'1'; literal KA0902_IIO$M_CERR1_NAE = %X'2'; literal KA0902_IIO$M_CERR1_CAPE = %X'4'; literal KA0902_IIO$M_CERR1_MCAPE = %X'8'; literal KA0902_IIO$M_CERR1_RWDPE = %X'10'; literal KA0902_IIO$M_CERR1_MWRPE = %X'20'; literal KA0902_IIO$M_CERR1_RDPE = %X'40'; literal KA0902_IIO$M_CERR1_MRDPE = %X'80'; literal KA0902_IIO$M_CERR1_CAPE0 = %X'100'; literal KA0902_IIO$M_CERR1_CAPE2 = %X'200'; literal KA0902_IIO$M_CERR1_DPE0 = %X'400'; literal KA0902_IIO$M_CERR1_DPE2 = %X'800'; literal KA0902_IIO$M_CERR1_DPE4 = %X'1000'; literal KA0902_IIO$M_CERR1_DPE6 = %X'2000'; literal KA0902_IIO$M_CERR1_CWDP = %X'10000'; literal KA0902_IIO$M_CERR1_BSE = %X'20000'; literal KA0902_IIO$M_CERR1_IPFNE = %X'40000'; literal KA0902_IIO$M_CERR1_CAPE1 = %X'100'; literal KA0902_IIO$M_CERR1_CAPE3 = %X'200'; literal KA0902_IIO$M_CERR1_DPE1 = %X'400'; literal KA0902_IIO$M_CERR1_DPE3 = %X'800'; literal KA0902_IIO$M_CERR1_DPE5 = %X'1000'; literal KA0902_IIO$M_CERR1_DPE7 = %X'2000'; literal KA0902_IIO$M_CERR3_L = %X'FFFFFFFF'; literal KA0902_IIO$M_CERR3_H = %X'FFFFFFFF00000000'; literal KA0902_IIO$M_PERR1_PWDPE = %X'1'; literal KA0902_IIO$M_PERR1_PAPE = %X'2'; literal KA0902_IIO$M_PERR1_PRDPE = %X'4'; literal KA0902_IIO$M_PERR1_PPE = %X'8'; literal KA0902_IIO$M_PERR1_PSE = %X'10'; literal KA0902_IIO$M_PERR1_PDTE = %X'20'; literal KA0902_IIO$M_PERR1_NMI = %X'40'; literal KA0902_IIO$M_PERR1_PPCSE = %X'80'; literal KA0902_IIO$M_PERR1_WDPE64 = %X'100'; literal KA0902_IIO$M_PERR1_ADPE64 = %X'200'; literal KA0902_IIO$M_PERR1_RDPE64 = %X'400'; literal KA0902_IIO$M_PERR1_TA = %X'800'; literal KA0902_IIO$M_PERR1_PRDPE64 = %X'10000'; literal KA0902_IIO$M_PERR1_PADPE64 = %X'20000'; literal KA0902_IIO$M_PERR1_PWDPE64 = %X'40000'; literal KA0902_IIO$M_PERR1_PTA = %X'80000'; literal KA0902_IIO$M_PSCM_L = %X'FFFFFFFF'; literal KA0902_IIO$M_PSCM_H = %X'FFFFFFFF00000000'; literal KA0902_IIO$M_HAE1_PUA_BIT26 = %X'20'; literal KA0902_IIO$M_HBASE_PHE1 = %X'2000'; literal KA0902_IIO$M_HBASE_PHE2 = %X'4000'; literal KA0902_IIO$M_HBASE_R0_ENA = %X'1000000'; literal KA0902_IIO$M_HBASE_R1_ENA = %X'2000000'; literal KA0902_IIO$M_HBASE_R2_ENA = %X'4000000'; literal KA0902_IIO$M_HBASE_R3_ENA = %X'8000000'; literal KA0902_IIO$M_HBASE_R4_ENA = %X'10000000'; literal KA0902_IIO$M_HBASE_R5_ENA = %X'20000000'; literal KA0902_IIO$M_HBASE_R6_ENA = %X'40000000'; literal KA0902_IIO$M_HBASE_R7_ENA = %X'80000000'; literal KA0902_IIO$M_HBASE_R8_ENA = %X'1'; literal KA0902_IIO$M_HBASE_R9_ENA = %X'2'; literal KA0902_IIO$M_HBASE_R10_ENA = %X'4'; literal KA0902_IIO$M_HBASE_R11_ENA = %X'8'; literal KA0902_IIO$M_HBASE_R12_ENA = %X'10'; literal KA0902_IIO$M_HBASE_R13_ENA = %X'20'; literal KA0902_IIO$M_HBASE_R14_ENA = %X'40'; literal KA0902_IIO$M_WBASE1_PPE = %X'20000'; literal KA0902_IIO$M_WBASE1_SGE = %X'40000'; literal KA0902_IIO$M_WBASE1_PWE = %X'80000'; literal KA0902_IIO$M_WBASE2_PPE = %X'20000'; literal KA0902_IIO$M_WBASE2_SGE = %X'40000'; literal KA0902_IIO$M_WBASE2_PWE = %X'80000'; literal KA0902_IIO$M_TLBBR_TLBBV = %X'1'; literal KA0902_IIO$M_TLBBR_TLBBD = %X'7FFFE'; literal KA0902_IIO$M_IVRPR_PRVECT = %X'FF'; literal KA0902_IIO$M_IVRPR_IA = %X'3FFFF'; literal KA0902_IIO$M_HAE3_CFG_TYPE = %X'C0000000'; literal KA0902_IIO$M_WBASE3_PPE = %X'1000'; literal KA0902_IIO$M_WBASE3_SGE = %X'40000'; literal KA0902_IIO$M_WBASE3_PWE = %X'80000'; literal KA0902_IIO$M_TDR0_TLBTD0 = %X'3FFFF'; literal KA0902_IIO$M_TDR0_TLBTD1 = %X'3FFC0000'; literal KA0902_IIO$M_TDR0_TLBV0 = %X'1'; literal KA0902_IIO$M_TDR0_TLBPFN = %X'7FFFE'; literal KA0902_IIO$M_TDR1_TLBTD0 = %X'3FFFF'; literal KA0902_IIO$M_TDR1_TLBTD1 = %X'3FFC0000'; literal KA0902_IIO$M_TDR1_TLBV1 = %X'1'; literal KA0902_IIO$M_TDR1_TLBPFN = %X'7FFFE'; literal KA0902_IIO$M_TDR2_TLBTD0 = %X'3FFFF'; literal KA0902_IIO$M_TDR2_TLBTD1 = %X'3FFC0000'; literal KA0902_IIO$M_TDR2_TLBV2 = %X'1'; literal KA0902_IIO$M_TDR2_TLBPFN = %X'7FFFE'; literal KA0902_IIO$M_TDR3_TLBTD0 = %X'3FFFF'; literal KA0902_IIO$M_TDR3_TLBTD1 = %X'3FFC0000'; literal KA0902_IIO$M_TDR3_TLBV3 = %X'1'; literal KA0902_IIO$M_TDR3_TLBPFN = %X'7FFFE'; literal KA0902_IIO$M_TDR4_TLBTD0 = %X'3FFFF'; literal KA0902_IIO$M_TDR4_TLBTD1 = %X'3FFC0000'; literal KA0902_IIO$M_TDR4_TLBV4 = %X'1'; literal KA0902_IIO$M_TDR4_TLBPFN = %X'7FFFE'; literal KA0902_IIO$M_TDR5_TLBTD0 = %X'3FFFF'; literal KA0902_IIO$M_TDR5_TLBTD1 = %X'3FFC0000'; literal KA0902_IIO$M_TDR5_TLBV5 = %X'1'; literal KA0902_IIO$M_TDR5_TLBPFN = %X'7FFFE'; literal KA0902_IIO$M_TDR6_TLBTD0 = %X'3FFFF'; literal KA0902_IIO$M_TDR6_TLBTD1 = %X'3FFC0000'; literal KA0902_IIO$M_TDR6_TLBV6 = %X'1'; literal KA0902_IIO$M_TDR6_TLBPFN = %X'7FFFE'; literal KA0902_IIO$M_TDR7_TLBTD0 = %X'3FFFF'; literal KA0902_IIO$M_TDR7_TLBTD1 = %X'3FFC0000'; literal KA0902_IIO$M_TDR7_TLBV7 = %X'1'; literal KA0902_IIO$M_TDR7_TLBPFN = %X'7FFFE'; literal KA0902_IIO$M_WBASE4_PPE = %X'1000'; literal KA0902_IIO$M_WBASE4_SGE = %X'40000'; literal KA0902_IIO$M_WBASE4_PWE = %X'80000'; literal KA0902_IIO$S_KA0902_IIO = 1248; ! I/O control/status register macro KA0902_IIO$Q_IOCSR = 0,0,0,1 %; literal KA0902_IIO$S_IOCSR = 8; macro KA0902_IIO$L_IOCSR_L = 0,0,32,0 %; macro KA0902_IIO$V_IOCSR_EN_LDEN = 0,0,1,0 %; ! dense hole enable macro KA0902_IIO$V_IOCSR_EL = 0,1,1,0 %; ! Enable loopback macro KA0902_IIO$V_IOCSR_ESMV = 0,2,1,0 %; ! State Machine Visibility macro KA0902_IIO$V_IOCSR_PDBP = 0,3,1,0 %; ! Drive PCI bad parity macro KA0902_IIO$V_IOCSR_PCIPRST0 = 0,4,1,0 %; ! PCI slot 0 present macro KA0902_IIO$V_IOCSR_PCIPRST1 = 0,5,1,0 %; ! PCI slot 1 present macro KA0902_IIO$V_IOCSR_INT = 0,6,1,0 %; ! external interrupt pin sts macro KA0902_IIO$V_IOCSR_TLBEE = 0,7,1,0 %; ! TLB error enable macro KA0902_IIO$V_IOCSR_CXACK = 0,8,1,0 %; ! log cxack errors macro KA0902_IIO$V_IOCSR_FILL2 = 0,9,1,0 %; ! macro KA0902_IIO$V_IOCSR_EXEX = 0,10,1,0 %; ! Exclusive Exchange cmd macro KA0902_IIO$V_IOCSR_FILL3 = 0,11,1,0 %; ! macro KA0902_IIO$V_IOCSR_CAWWP0 = 0,12,1,0 %; ! Write CBUS C/A bad parity macro KA0902_IIO$V_IOCSR_CAWWP2 = 0,13,1,0 %; ! Write CBUS C/A bad parity macro KA0902_IIO$V_IOCSR_DWWPE = 0,14,1,0 %; ! Write CBUS even bad parity macro KA0902_IIO$V_IOCSR_MBA5 = 0,15,1,0 %; ! external MBA5 status macro KA0902_IIO$V_IOCSR_MBA6 = 0,16,1,0 %; ! external MBA6 status macro KA0902_IIO$V_IOCSR_MBA7 = 0,17,1,0 %; ! external MBA7 status macro KA0902_IIO$V_IOCSR_PCIPRST3 = 0,18,1,0 %; ! slot 4 present1 macro KA0902_IIO$V_IOCSR_PCIPRST4 = 0,19,1,0 %; ! slot 4 present2 macro KA0902_IIO$V_IOCSR_PDWWP1 = 0,20,1,0 %; ! Write CBUS DMA bad parity macro KA0902_IIO$V_IOCSR_PDWWP0 = 0,21,1,0 %; ! Write CBUS DMA bad parity macro KA0902_IIO$V_IOCSR_PBR = 0,22,1,0 %; ! PCI bus reset macro KA0902_IIO$V_IOCSR_PIR = 0,23,1,0 %; ! PCI interface reset macro KA0902_IIO$V_IOCSR_ENCOI = 0,24,1,0 %; ! Enable NOACK,CUCERR,SYNC macro KA0902_IIO$V_IOCSR_EPMS = 0,25,1,0 %; ! Enable PCI memory space macro KA0902_IIO$V_IOCSR_ETLB = 0,26,1,0 %; ! Enable Translation buffer macro KA0902_IIO$V_IOCSR_EACC = 0,27,1,0 %; ! Enable atomic CBUS cycles macro KA0902_IIO$V_IOCSR_FTLB = 0,28,1,0 %; ! Flush Translation buffer macro KA0902_IIO$V_IOCSR_ECPC = 0,29,1,0 %; ! Enable CBUS parity check macro KA0902_IIO$V_IOCSR_CIR = 0,30,1,0 %; ! CBUS interface reset macro KA0902_IIO$V_IOCSR_EPL = 0,31,1,0 %; ! Enable PCI lock macro KA0902_IIO$L_IOCSR_H = 4,0,32,0 %; macro KA0902_IIO$V_IOCSR_CBBCE = 4,0,1,0 %; ! Enable CBUS back-to-back macro KA0902_IIO$V_IOCSR_TRN = 4,1,3,0 %; literal KA0902_IIO$S_IOCSR_TRN = 3; ! T2 revision number macro KA0902_IIO$V_IOCSR_SMVL = 4,4,3,0 %; literal KA0902_IIO$S_IOCSR_SMVL = 3; ! State machine select macro KA0902_IIO$V_IOCSR_MBA4 = 4,7,1,0 %; ! external MBA4 status macro KA0902_IIO$V_IOCSR_EPR = 4,8,1,0 %; ! Enable passive release macro KA0902_IIO$V_IOCSR_RDPE64 = 4,9,1,0 %; ! T4 parity: master read macro KA0902_IIO$V_IOCSR_ADPE64 = 4,10,1,0 %; ! T4 parity: target rcv macro KA0902_IIO$V_IOCSR_WDPE64 = 4,11,1,0 %; ! T4 parity: target write macro KA0902_IIO$V_IOCSR_CAWWP1 = 4,12,1,0 %; ! CBUS C/A bad parity 1 macro KA0902_IIO$V_IOCSR_CAWWP3 = 4,13,1,0 %; ! CBUS C/A bad parity 3 macro KA0902_IIO$V_IOCSR_DWWPO = 4,14,1,0 %; ! CBUS data parity odd macro KA0902_IIO$V_IOCSR_T24ST = 4,15,1,0 %; ! clear: T2 compatability mode macro KA0902_IIO$V_IOCSR_PPC1 = 4,16,1,0 %; ! 2nd PIO buf is PPC buf macro KA0902_IIO$V_IOCSR_PPC2 = 4,17,1,0 %; ! 3rd PIO buf is PPC buf macro KA0902_IIO$V_IOCSR_STALL = 4,18,1,0 %; ! enable DMA stall mode macro KA0902_IIO$V_IOCSR_FILL4 = 4,19,1,0 %; macro KA0902_IIO$V_IOCSR_PRM = 4,20,1,0 %; ! PCI read multiple macro KA0902_IIO$V_IOCSR_PWM = 4,21,1,0 %; ! PCI write multiple macro KA0902_IIO$V_IOCSR_FPRDPED = 4,22,1,0 %; ! PCI Force RDPE detect macro KA0902_IIO$V_IOCSR_FPADPED = 4,23,1,0 %; ! PCI Force APE detect macro KA0902_IIO$V_IOCSR_FPWDPED = 4,24,1,0 %; ! PCI Force RWPE detect macro KA0902_IIO$V_IOCSR_EPNMI = 4,25,1,0 %; ! PCI enable NMI macro KA0902_IIO$V_IOCSR_EPDTI = 4,26,1,0 %; ! PCI enable DTI macro KA0902_IIO$V_IOCSR_EPSEI = 4,27,1,0 %; ! PCI enable SERR interrupt macro KA0902_IIO$V_IOCSR_EPPEI = 4,28,1,0 %; ! PCI enable PERR interrupt macro KA0902_IIO$V_IOCSR_ERDPC = 4,29,1,0 %; ! PCI enable RDPE interrupt macro KA0902_IIO$V_IOCSR_EPADPC = 4,30,1,0 %; ! PCI enable addr parity int. macro KA0902_IIO$V_IOCSR_EWDPC = 4,31,1,0 %; ! PCI enable WD parity int. ! Cbus error register 1 macro KA0902_IIO$Q_CERR1 = 32,0,0,1 %; literal KA0902_IIO$S_CERR1 = 8; macro KA0902_IIO$L_CERR1_L = 32,0,32,0 %; macro KA0902_IIO$V_CERR1_URE = 32,0,1,0 %; ! Uncorrectable read error macro KA0902_IIO$V_CERR1_NAE = 32,1,1,0 %; ! No acknowledge error macro KA0902_IIO$V_CERR1_CAPE = 32,2,1,0 %; ! Command address parity error even macro KA0902_IIO$V_CERR1_MCAPE = 32,3,1,0 %; ! Missed command address parity error even macro KA0902_IIO$V_CERR1_RWDPE = 32,4,1,0 %; ! Write data parity error even macro KA0902_IIO$V_CERR1_MWRPE = 32,5,1,0 %; ! Missed write data parity error even macro KA0902_IIO$V_CERR1_RDPE = 32,6,1,0 %; ! Read data parity error even macro KA0902_IIO$V_CERR1_MRDPE = 32,7,1,0 %; ! Missed read data parity error even macro KA0902_IIO$V_CERR1_CAPE0 = 32,8,1,0 %; ! C/A parity error longword 0 macro KA0902_IIO$V_CERR1_CAPE2 = 32,9,1,0 %; ! C/A parity error longword 2 macro KA0902_IIO$V_CERR1_DPE0 = 32,10,1,0 %; ! Data parity error longword 0 macro KA0902_IIO$V_CERR1_DPE2 = 32,11,1,0 %; ! Data parity error longword 2 macro KA0902_IIO$V_CERR1_DPE4 = 32,12,1,0 %; ! Data parity error longword 4 macro KA0902_IIO$V_CERR1_DPE6 = 32,13,1,0 %; ! Data parity error longword 6 macro KA0902_IIO$V_CERR1_CWDP = 32,16,1,0 %; ! Command WDPE macro KA0902_IIO$V_CERR1_BSE = 32,17,1,0 %; ! Bus sync error macro KA0902_IIO$V_CERR1_IPFNE = 32,18,1,0 %; ! Invalid PFN macro KA0902_IIO$L_CERR1_H = 36,0,32,0 %; macro KA0902_IIO$V_CERR1_CAPE1 = 36,8,1,0 %; ! C/A parity error LW1 macro KA0902_IIO$V_CERR1_CAPE3 = 36,9,1,0 %; ! C/A parity error LW3 macro KA0902_IIO$V_CERR1_DPE1 = 36,10,1,0 %; ! Data parity error LW1 macro KA0902_IIO$V_CERR1_DPE3 = 36,11,1,0 %; ! Data parity error LW3 macro KA0902_IIO$V_CERR1_DPE5 = 36,12,1,0 %; ! Data parity error LW5 macro KA0902_IIO$V_CERR1_DPE7 = 36,13,1,0 %; ! Data parity error LW7 ! Cbus error register 2 macro KA0902_IIO$Q_CERR2 = 64,0,0,0 %; literal KA0902_IIO$S_CERR2 = 8; macro KA0902_IIO$L_CERR2_L = 64,0,32,0 %; macro KA0902_IIO$L_CERR2_H = 68,0,32,0 %; ! Cbus error register 3 macro KA0902_IIO$Q_CERR3 = 96,0,0,0 %; literal KA0902_IIO$S_CERR3 = 8; macro KA0902_IIO$V_CERR3_L = 96,0,32,0 %; literal KA0902_IIO$S_CERR3_L = 32; macro KA0902_IIO$V_CERR3_H = 100,0,32,0 %; literal KA0902_IIO$S_CERR3_H = 32; ! PCI error register 1 macro KA0902_IIO$Q_PERR1 = 128,0,0,1 %; literal KA0902_IIO$S_PERR1 = 8; macro KA0902_IIO$L_PERR1_L = 128,0,32,0 %; macro KA0902_IIO$V_PERR1_PWDPE = 128,0,1,0 %; ! PCI write data parity error macro KA0902_IIO$V_PERR1_PAPE = 128,1,1,0 %; ! PCI address parity error macro KA0902_IIO$V_PERR1_PRDPE = 128,2,1,0 %; ! PCI read data parity error macro KA0902_IIO$V_PERR1_PPE = 128,3,1,0 %; ! PCI parity error macro KA0902_IIO$V_PERR1_PSE = 128,4,1,0 %; ! PCI system error macro KA0902_IIO$V_PERR1_PDTE = 128,5,1,0 %; ! PCI device timeout error macro KA0902_IIO$V_PERR1_NMI = 128,6,1,0 %; ! Non-maskable interrupt macro KA0902_IIO$V_PERR1_PPCSE = 128,7,1,0 %; ! Bad size on PPC xfer macro KA0902_IIO$V_PERR1_WDPE64 = 128,8,1,0 %; ! Parity: write data,T4 target macro KA0902_IIO$V_PERR1_ADPE64 = 128,9,1,0 %; ! Parity: address, T4 target macro KA0902_IIO$V_PERR1_RDPE64 = 128,10,1,0 %; ! Parity: read data, T4 master macro KA0902_IIO$V_PERR1_TA = 128,11,1,0 %; ! Target abort macro KA0902_IIO$V_PERR1_PRDPE64 = 128,16,1,0 %; ! enable logging rdpe macro KA0902_IIO$V_PERR1_PADPE64 = 128,17,1,0 %; ! enable logging adpe macro KA0902_IIO$V_PERR1_PWDPE64 = 128,18,1,0 %; ! enable logging wdpe macro KA0902_IIO$V_PERR1_PTA = 128,19,1,0 %; ! enable loggine TA macro KA0902_IIO$L_PERR1_H = 132,0,32,0 %; ! PCI error register 2 macro KA0902_IIO$Q_PERR2 = 160,0,0,1 %; literal KA0902_IIO$S_PERR2 = 8; macro KA0902_IIO$L_PERR2_L = 160,0,32,0 %; macro KA0902_IIO$V_PERR2_PEA = 160,0,32,0 %; literal KA0902_IIO$S_PERR2_PEA = 32; ! PCI error address macro KA0902_IIO$L_PERR2_H = 164,0,32,0 %; macro KA0902_IIO$V_PERR2_PEC = 164,0,5,0 %; literal KA0902_IIO$S_PERR2_PEC = 5; ! PCI error command ! PCI special cycle register macro KA0902_IIO$Q_PSCM = 192,0,0,0 %; literal KA0902_IIO$S_PSCM = 8; macro KA0902_IIO$V_PSCM_L = 192,0,32,0 %; literal KA0902_IIO$S_PSCM_L = 32; macro KA0902_IIO$V_PSCM_H = 196,0,32,0 %; literal KA0902_IIO$S_PSCM_H = 32; ! High Address Extension register 1 ! Note extra bit for T4 ! macro KA0902_IIO$Q_HAE1 = 224,0,0,1 %; literal KA0902_IIO$S_HAE1 = 8; macro KA0902_IIO$L_HAE1_L = 224,0,32,0 %; macro KA0902_IIO$V_HAE1_PUA1 = 224,0,5,0 %; literal KA0902_IIO$S_HAE1_PUA1 = 5; ! PCI upper address (T2) macro KA0902_IIO$V_HAE1_PUA_BIT26 = 224,5,1,0 %; ! extra addr bit for T4 only macro KA0902_IIO$L_HAE1_H = 228,0,32,0 %; ! High Address Extension register 2 ! Note 1 less bit for T4 macro KA0902_IIO$Q_HAE2 = 256,0,0,1 %; literal KA0902_IIO$S_HAE2 = 8; macro KA0902_IIO$L_HAE2_L = 256,0,32,0 %; macro KA0902_IIO$V_HAE2_PUA2 = 256,0,8,0 %; literal KA0902_IIO$S_HAE2_PUA2 = 8; ! PCI upper address macro KA0902_IIO$V_HAE2_PUA1 = 256,8,1,0 %; ! and 1 more for T2 macro KA0902_IIO$L_HAE2_H = 260,0,32,0 %; ! PCI Hole base register macro KA0902_IIO$Q_HBASE = 288,0,0,1 %; literal KA0902_IIO$S_HBASE = 8; macro KA0902_IIO$L_HBASE_L = 288,0,32,0 %; macro KA0902_IIO$V_HBASE_PHEA = 288,0,9,0 %; literal KA0902_IIO$S_HBASE_PHEA = 9; ! PCI hole end address macro KA0902_IIO$V_HBASE_PHE1 = 288,13,1,0 %; ! PCI fixed hole enable 1 ! Note that although at first glance this seems ! incompatible with T2, the sense is the same - T4 ! merely allows subsets of 512-1mb macro KA0902_IIO$V_HBASE_PHE2 = 288,14,1,0 %; ! PCI programmable hole enable macro KA0902_IIO$V_HBASE_PHSA = 288,15,9,0 %; literal KA0902_IIO$S_HBASE_PHSA = 9; ! PCI hole start address macro KA0902_IIO$V_HBASE_R0_ENA = 288,24,1,0 %; ! enable region 0 macro KA0902_IIO$V_HBASE_R1_ENA = 288,25,1,0 %; ! enable region 1 macro KA0902_IIO$V_HBASE_R2_ENA = 288,26,1,0 %; ! enable region 2 macro KA0902_IIO$V_HBASE_R3_ENA = 288,27,1,0 %; ! enable region 3 macro KA0902_IIO$V_HBASE_R4_ENA = 288,28,1,0 %; ! enable region 4 macro KA0902_IIO$V_HBASE_R5_ENA = 288,29,1,0 %; ! enable region 5 macro KA0902_IIO$V_HBASE_R6_ENA = 288,30,1,0 %; ! enable region 6 macro KA0902_IIO$V_HBASE_R7_ENA = 288,31,1,0 %; ! enable region 7 macro KA0902_IIO$L_HBASE_H = 292,0,32,0 %; macro KA0902_IIO$V_HBASE_R8_ENA = 292,0,1,0 %; ! enable region 8 macro KA0902_IIO$V_HBASE_R9_ENA = 292,1,1,0 %; ! enable region 9 macro KA0902_IIO$V_HBASE_R10_ENA = 292,2,1,0 %; ! enable region 10 macro KA0902_IIO$V_HBASE_R11_ENA = 292,3,1,0 %; ! enable region 11 macro KA0902_IIO$V_HBASE_R12_ENA = 292,4,1,0 %; ! enable region 12 macro KA0902_IIO$V_HBASE_R13_ENA = 292,5,1,0 %; ! enable region 13 macro KA0902_IIO$V_HBASE_R14_ENA = 292,6,1,0 %; ! enable region 14 ! PCI Window base register 1 macro KA0902_IIO$Q_WBASE1 = 320,0,0,1 %; literal KA0902_IIO$S_WBASE1 = 8; macro KA0902_IIO$L_WBASE1_L = 320,0,32,0 %; macro KA0902_IIO$V_WBASE1_PWEA = 320,0,12,0 %; literal KA0902_IIO$S_WBASE1_PWEA = 12; ! PCI window end address macro KA0902_IIO$V_WBASE1_PPE = 320,17,1,0 %; ! PCI peer-to-peer enabled macro KA0902_IIO$V_WBASE1_SGE = 320,18,1,0 %; ! PCI Scatter-Gather enabled macro KA0902_IIO$V_WBASE1_PWE = 320,19,1,0 %; ! PCI window enable macro KA0902_IIO$V_WBASE1_PWSA = 320,20,12,0 %; literal KA0902_IIO$S_WBASE1_PWSA = 12; ! PCI window start address macro KA0902_IIO$L_WBASE1_H = 324,0,32,0 %; ! PCI Window mask register 1 macro KA0902_IIO$Q_WMASK1 = 352,0,0,1 %; literal KA0902_IIO$S_WMASK1 = 8; macro KA0902_IIO$L_WMASK1_L = 352,0,32,0 %; macro KA0902_IIO$V_WMASK1_PWM = 352,20,11,0 %; literal KA0902_IIO$S_WMASK1_PWM = 11; ! PCI window mask macro KA0902_IIO$L_WMASK1_H = 356,0,32,0 %; ! PCI Translated Base register 1 macro KA0902_IIO$Q_TBASE1 = 384,0,0,1 %; literal KA0902_IIO$S_TBASE1 = 8; macro KA0902_IIO$L_TBASE1_L = 384,0,32,0 %; macro KA0902_IIO$V_TBASE1_TBA = 384,9,22,0 %; literal KA0902_IIO$S_TBASE1_TBA = 22; ! PCI Translated Base macro KA0902_IIO$L_TBASE1_H = 388,0,32,0 %; ! PCI Window base register 2 macro KA0902_IIO$Q_WBASE2 = 416,0,0,1 %; literal KA0902_IIO$S_WBASE2 = 8; macro KA0902_IIO$L_WBASE2_L = 416,0,32,0 %; macro KA0902_IIO$V_WBASE2_PWEA = 416,0,12,0 %; literal KA0902_IIO$S_WBASE2_PWEA = 12; ! PCI window end address macro KA0902_IIO$V_WBASE2_PPE = 416,17,1,0 %; ! PCI peer-to-peer enabled macro KA0902_IIO$V_WBASE2_SGE = 416,18,1,0 %; ! PCI Scatter-Gather enabled macro KA0902_IIO$V_WBASE2_PWE = 416,19,1,0 %; ! PCI window enable macro KA0902_IIO$V_WBASE2_PWSA = 416,20,12,0 %; literal KA0902_IIO$S_WBASE2_PWSA = 12; ! PCI window start address macro KA0902_IIO$L_WBASE2_H = 420,0,32,0 %; ! PCI Window mask register 2 macro KA0902_IIO$Q_WMASK2 = 448,0,0,1 %; literal KA0902_IIO$S_WMASK2 = 8; macro KA0902_IIO$L_WMASK2_L = 448,0,32,0 %; macro KA0902_IIO$V_WMASK2_PWM = 448,20,11,0 %; literal KA0902_IIO$S_WMASK2_PWM = 11; ! PCI window mask macro KA0902_IIO$L_WMASK2_H = 452,0,32,0 %; ! PCI Translated Base register 2 macro KA0902_IIO$Q_TBASE2 = 480,0,0,1 %; literal KA0902_IIO$S_TBASE2 = 8; macro KA0902_IIO$L_TBASE2_L = 480,0,32,0 %; macro KA0902_IIO$V_TBASE2_TBA = 480,9,22,0 %; literal KA0902_IIO$S_TBASE2_TBA = 22; ! PCI Translated Base macro KA0902_IIO$L_TBASE2_H = 484,0,32,0 %; ! PCI TLB by-pass register macro KA0902_IIO$Q_TLBBR = 512,0,0,1 %; literal KA0902_IIO$S_TLBBR = 8; macro KA0902_IIO$L_TLBBR_L = 512,0,32,0 %; macro KA0902_IIO$V_TLBBR_TLBBV = 512,0,1,0 %; ! TLB by-pass valid macro KA0902_IIO$V_TLBBR_TLBBD = 512,1,18,0 %; literal KA0902_IIO$S_TLBBR_TLBBD = 18; ! TLB by-pass data macro KA0902_IIO$L_TLBBR_H = 516,0,32,0 %; ! PCI Invalid Passive Release register ! for late T2 and T4, contains both IVR and passive release vector fields macro KA0902_IIO$Q_IVRPR = 544,0,0,1 %; literal KA0902_IIO$S_IVRPR = 8; macro KA0902_IIO$L_IVRPR_L = 544,0,32,0 %; macro KA0902_IIO$V_IVRPR_PRVECT = 544,0,8,0 %; literal KA0902_IIO$S_IVRPR_PRVECT = 8; ! Passive release vec macro KA0902_IIO$L_IVRPR_H = 548,0,32,0 %; macro KA0902_IIO$V_IVRPR_IA = 548,0,18,0 %; literal KA0902_IIO$S_IVRPR_IA = 18; ! Interrupt address ! High Address Extension register 3 macro KA0902_IIO$Q_HAE3 = 576,0,0,1 %; literal KA0902_IIO$S_HAE3 = 8; macro KA0902_IIO$L_HAE3_L = 576,0,32,0 %; macro KA0902_IIO$V_HAE3_CFG_TYPE = 576,30,2,0 %; literal KA0902_IIO$S_HAE3_CFG_TYPE = 2; macro KA0902_IIO$L_HAE3_H = 580,0,32,0 %; ! High Address Extension register 4 macro KA0902_IIO$Q_HAE4 = 608,0,0,1 %; literal KA0902_IIO$S_HAE4 = 8; macro KA0902_IIO$L_HAE4_L = 608,0,32,0 %; macro KA0902_IIO$V_HAE4_PUA = 608,0,2,0 %; literal KA0902_IIO$S_HAE4_PUA = 2; ! PCI upper address macro KA0902_IIO$L_HAE4_H = 612,0,32,0 %; ! PCI Window base register 3 ! added for T4 macro KA0902_IIO$Q_WBASE3 = 640,0,0,1 %; literal KA0902_IIO$S_WBASE3 = 8; macro KA0902_IIO$L_WBASE3_L = 640,0,32,0 %; macro KA0902_IIO$V_WBASE3_PWEA = 640,0,12,0 %; literal KA0902_IIO$S_WBASE3_PWEA = 12; ! PCI window end address macro KA0902_IIO$V_WBASE3_PPE = 640,12,1,0 %; ! PCI peer-to-peer enable macro KA0902_IIO$V_WBASE3_SGE = 640,18,1,0 %; ! PCI Scatter-Gather enabled macro KA0902_IIO$V_WBASE3_PWE = 640,19,1,0 %; ! PCI window enable macro KA0902_IIO$V_WBASE3_PWSA = 640,20,12,0 %; literal KA0902_IIO$S_WBASE3_PWSA = 12; ! PCI window start address macro KA0902_IIO$L_WBASE3_H = 644,0,32,0 %; ! PCI Window mask register 3 ! added for T4 macro KA0902_IIO$Q_WMASK3 = 672,0,0,1 %; literal KA0902_IIO$S_WMASK3 = 8; macro KA0902_IIO$L_WMASK3_L = 672,0,32,0 %; macro KA0902_IIO$V_WMASK3_PWM = 672,20,11,0 %; literal KA0902_IIO$S_WMASK3_PWM = 11; ! PCI window mask macro KA0902_IIO$L_WMASK3_H = 676,0,32,0 %; ! PCI Translated Base register 3 ! added for T4 macro KA0902_IIO$Q_TBASE3 = 704,0,0,1 %; literal KA0902_IIO$S_TBASE3 = 8; macro KA0902_IIO$L_TBASE3_L = 704,0,32,0 %; macro KA0902_IIO$V_TBASE3_TBA = 704,9,22,0 %; literal KA0902_IIO$S_TBASE3_TBA = 22; ! PCI Translated Base macro KA0902_IIO$L_TBASE3_H = 708,0,32,0 %; ! TLB data register 0 macro KA0902_IIO$Q_TDR0 = 768,0,0,1 %; literal KA0902_IIO$S_TDR0 = 8; macro KA0902_IIO$L_TDR0_L = 768,0,32,0 %; macro KA0902_IIO$V_TDR0_TLBTD0 = 768,0,18,0 %; literal KA0902_IIO$S_TDR0_TLBTD0 = 18; ! Tag for TLB entry 0 macro KA0902_IIO$V_TDR0_TLBTD1 = 768,18,12,0 %; literal KA0902_IIO$S_TDR0_TLBTD1 = 12; ! Extended for T4 macro KA0902_IIO$L_TDR0_H = 772,0,32,0 %; macro KA0902_IIO$V_TDR0_TLBV0 = 772,0,1,0 %; ! Valid tag for TLB 0 macro KA0902_IIO$V_TDR0_TLBPFN = 772,1,18,0 %; literal KA0902_IIO$S_TDR0_TLBPFN = 18; ! PFN for TLB 0 ! TLB data register 1 macro KA0902_IIO$Q_TDR1 = 800,0,0,1 %; literal KA0902_IIO$S_TDR1 = 8; macro KA0902_IIO$L_TDR1_L = 800,0,32,0 %; macro KA0902_IIO$V_TDR1_TLBTD0 = 800,0,18,0 %; literal KA0902_IIO$S_TDR1_TLBTD0 = 18; ! Tag for TLB entry 0 macro KA0902_IIO$V_TDR1_TLBTD1 = 800,18,12,0 %; literal KA0902_IIO$S_TDR1_TLBTD1 = 12; ! Extended for T4 macro KA0902_IIO$L_TDR1_H = 804,0,32,0 %; macro KA0902_IIO$V_TDR1_TLBV1 = 804,0,1,0 %; ! Valid tag for TLB 1 macro KA0902_IIO$V_TDR1_TLBPFN = 804,1,18,0 %; literal KA0902_IIO$S_TDR1_TLBPFN = 18; ! PFN for TLB 1 ! TLB data register 2 macro KA0902_IIO$Q_TDR2 = 832,0,0,1 %; literal KA0902_IIO$S_TDR2 = 8; macro KA0902_IIO$L_TDR2_L = 832,0,32,0 %; macro KA0902_IIO$V_TDR2_TLBTD0 = 832,0,18,0 %; literal KA0902_IIO$S_TDR2_TLBTD0 = 18; ! Tag for TLB entry 0 macro KA0902_IIO$V_TDR2_TLBTD1 = 832,18,12,0 %; literal KA0902_IIO$S_TDR2_TLBTD1 = 12; ! Extended for T4 macro KA0902_IIO$L_TDR2_H = 836,0,32,0 %; macro KA0902_IIO$V_TDR2_TLBV2 = 836,0,1,0 %; ! Valid tag for TLB 2 macro KA0902_IIO$V_TDR2_TLBPFN = 836,1,18,0 %; literal KA0902_IIO$S_TDR2_TLBPFN = 18; ! PFN for TLB 2 ! TLB data register 3 macro KA0902_IIO$Q_TDR3 = 864,0,0,1 %; literal KA0902_IIO$S_TDR3 = 8; macro KA0902_IIO$L_TDR3_L = 864,0,32,0 %; macro KA0902_IIO$V_TDR3_TLBTD0 = 864,0,18,0 %; literal KA0902_IIO$S_TDR3_TLBTD0 = 18; ! Tag for TLB entry 0 macro KA0902_IIO$V_TDR3_TLBTD1 = 864,18,12,0 %; literal KA0902_IIO$S_TDR3_TLBTD1 = 12; ! Extended for T4 macro KA0902_IIO$L_TDR3_H = 868,0,32,0 %; macro KA0902_IIO$V_TDR3_TLBV3 = 868,0,1,0 %; ! Valid tag for TLB 3 macro KA0902_IIO$V_TDR3_TLBPFN = 868,1,18,0 %; literal KA0902_IIO$S_TDR3_TLBPFN = 18; ! PFN for TLB 3 ! TLB data register 4 macro KA0902_IIO$Q_TDR4 = 896,0,0,1 %; literal KA0902_IIO$S_TDR4 = 8; macro KA0902_IIO$L_TDR4_L = 896,0,32,0 %; macro KA0902_IIO$V_TDR4_TLBTD0 = 896,0,18,0 %; literal KA0902_IIO$S_TDR4_TLBTD0 = 18; ! Tag for TLB entry 0 macro KA0902_IIO$V_TDR4_TLBTD1 = 896,18,12,0 %; literal KA0902_IIO$S_TDR4_TLBTD1 = 12; ! Extended for T4 macro KA0902_IIO$L_TDR4_H = 900,0,32,0 %; macro KA0902_IIO$V_TDR4_TLBV4 = 900,0,1,0 %; ! Valid tag for TLB 4 macro KA0902_IIO$V_TDR4_TLBPFN = 900,1,18,0 %; literal KA0902_IIO$S_TDR4_TLBPFN = 18; ! PFN for TLB 4 ! TLB data register 5 macro KA0902_IIO$Q_TDR5 = 928,0,0,1 %; literal KA0902_IIO$S_TDR5 = 8; macro KA0902_IIO$L_TDR5_L = 928,0,32,0 %; macro KA0902_IIO$V_TDR5_TLBTD0 = 928,0,18,0 %; literal KA0902_IIO$S_TDR5_TLBTD0 = 18; ! Tag for TLB entry 0 macro KA0902_IIO$V_TDR5_TLBTD1 = 928,18,12,0 %; literal KA0902_IIO$S_TDR5_TLBTD1 = 12; ! Extended for T4 macro KA0902_IIO$L_TDR5_H = 932,0,32,0 %; macro KA0902_IIO$V_TDR5_TLBV5 = 932,0,1,0 %; ! Valid tag for TLB 5 macro KA0902_IIO$V_TDR5_TLBPFN = 932,1,18,0 %; literal KA0902_IIO$S_TDR5_TLBPFN = 18; ! PFN for TLB 5 ! TLB data register 6 macro KA0902_IIO$Q_TDR6 = 960,0,0,1 %; literal KA0902_IIO$S_TDR6 = 8; macro KA0902_IIO$L_TDR6_L = 960,0,32,0 %; macro KA0902_IIO$V_TDR6_TLBTD0 = 960,0,18,0 %; literal KA0902_IIO$S_TDR6_TLBTD0 = 18; ! Tag for TLB entry 0 macro KA0902_IIO$V_TDR6_TLBTD1 = 960,18,12,0 %; literal KA0902_IIO$S_TDR6_TLBTD1 = 12; ! Extended for T4 macro KA0902_IIO$L_TDR6_H = 964,0,32,0 %; macro KA0902_IIO$V_TDR6_TLBV6 = 964,0,1,0 %; ! Valid tag for TLB 6 macro KA0902_IIO$V_TDR6_TLBPFN = 964,1,18,0 %; literal KA0902_IIO$S_TDR6_TLBPFN = 18; ! PFN for TLB 6 ! TLB data register 7 macro KA0902_IIO$Q_TDR7 = 992,0,0,1 %; literal KA0902_IIO$S_TDR7 = 8; macro KA0902_IIO$L_TDR7_L = 992,0,32,0 %; macro KA0902_IIO$V_TDR7_TLBTD0 = 992,0,18,0 %; literal KA0902_IIO$S_TDR7_TLBTD0 = 18; ! Tag for TLB entry 0 macro KA0902_IIO$V_TDR7_TLBTD1 = 992,18,12,0 %; literal KA0902_IIO$S_TDR7_TLBTD1 = 12; ! Extended for T4 macro KA0902_IIO$L_TDR7_H = 996,0,32,0 %; macro KA0902_IIO$V_TDR7_TLBV7 = 996,0,1,0 %; ! Valid tag for TLB 7 macro KA0902_IIO$V_TDR7_TLBPFN = 996,1,18,0 %; literal KA0902_IIO$S_TDR7_TLBPFN = 18; ! PFN for TLB 7 ! PCI Window base register 4 ! added for T4 macro KA0902_IIO$Q_WBASE4 = 1024,0,0,1 %; literal KA0902_IIO$S_WBASE4 = 8; macro KA0902_IIO$L_WBASE4_L = 1024,0,32,0 %; macro KA0902_IIO$V_WBASE4_PWEA = 1024,0,12,0 %; literal KA0902_IIO$S_WBASE4_PWEA = 12; ! PCI window end address macro KA0902_IIO$V_WBASE4_PPE = 1024,12,1,0 %; ! PCI peer-to-peer enable macro KA0902_IIO$V_WBASE4_SGE = 1024,18,1,0 %; ! PCI Scatter-Gather enabled macro KA0902_IIO$V_WBASE4_PWE = 1024,19,1,0 %; ! PCI window enable macro KA0902_IIO$V_WBASE4_PWSA = 1024,20,12,0 %; literal KA0902_IIO$S_WBASE4_PWSA = 12; ! PCI window start address macro KA0902_IIO$L_WBASE4_H = 1028,0,32,0 %; ! PCI Window mask register 4 ! added for T4 macro KA0902_IIO$Q_WMASK4 = 1056,0,0,1 %; literal KA0902_IIO$S_WMASK4 = 8; macro KA0902_IIO$L_WMASK4_L = 1056,0,32,0 %; macro KA0902_IIO$V_WMASK4_PWM = 1056,20,11,0 %; literal KA0902_IIO$S_WMASK4_PWM = 11; ! PCI window mask macro KA0902_IIO$L_WMASK4_H = 1060,0,32,0 %; ! PCI Translated Base register 4 ! added for T4 macro KA0902_IIO$Q_TBASE4 = 1088,0,0,1 %; literal KA0902_IIO$S_TBASE4 = 8; macro KA0902_IIO$L_TBASE4_L = 1088,0,32,0 %; macro KA0902_IIO$V_TBASE4_TBA = 1088,9,22,0 %; literal KA0902_IIO$S_TBASE4_TBA = 22; ! PCI Translated Base macro KA0902_IIO$L_TBASE4_H = 1092,0,32,0 %; ! PCI IC Interrupt Controller Address Indirection Register ! Load with offset of desired configuration register ! See ICIC spec for definition macro KA0902_IIO$Q_AIR = 1120,0,0,1 %; literal KA0902_IIO$S_AIR = 8; macro KA0902_IIO$L_AIR_L = 1120,0,32,0 %; macro KA0902_IIO$L_AIR_H = 1124,0,32,0 %; ! PCI IC Interrupt Controller Vector Register ! Read to obtain the 8-bit interrupt vector. ! Write to cause an SEOI to the vector indicated by the low 6 bits. macro KA0902_IIO$Q_VECTOR = 1152,0,0,1 %; literal KA0902_IIO$S_VECTOR = 8; macro KA0902_IIO$L_VECTOR_L = 1152,0,32,0 %; macro KA0902_IIO$L_VECTOR_H = 1156,0,32,0 %; ! PCI IC Interrupt Controller Data Indirection Register ! Read or write DIR to access configuration register ! identified by AIR. See ICIC spec for details. macro KA0902_IIO$Q_DIR = 1184,0,0,1 %; literal KA0902_IIO$S_DIR = 8; macro KA0902_IIO$L_DIR_L = 1184,0,32,0 %; macro KA0902_IIO$L_DIR_H = 1188,0,32,0 %; ! PCI IC Interrupt Controller setup register ! added for T3 and T4 ! See ICIC spec for definition macro KA0902_IIO$Q_ICIC = 1216,0,0,1 %; literal KA0902_IIO$S_ICIC = 8; macro KA0902_IIO$L_ICIC_L = 1216,0,32,0 %; macro KA0902_IIO$V_ICIC_FLUSH_ADDR = 1216,0,24,0 %; literal KA0902_IIO$S_ICIC_FLUSH_ADDR = 24; ! EISA flush address macro KA0902_IIO$V_ICIC_ENABLE = 1216,24,1,0 %; ! Enable ICIC macro KA0902_IIO$V_ICIC_CLOCK = 1216,25,1,0 %; ! Fast/slow clock macro KA0902_IIO$L_ICIC_H = 1220,0,32,0 %; literal KA0902_IIO$K_LENGTH = 1248; ! New for T4 and Lynx (T3), the IC Interrupt Controller. ! ICIC register definitions. To access these registers, write the offset ! into the AIR register, then read the DIR register or write your data ! to the DIR register. ! literal KA0902_ICIC$K_MASK = 64; ! ICIC interrupt mask register literal KA0902_ICIC$K_ELCR = 80; ! ICIC edge level register literal KA0902_ICIC$K_EISA = 96; ! ICIC device is behind EISA bridge literal KA0902_ICIC$K_MODE = 112; ! Bit 0: priority or round robin ! ! Sable CPU register definitions ! literal KA0902_CPU$M_BCC_ENB_ALLOC_L = %X'1'; literal KA0902_CPU$M_BCC_FRC_FILL_SH_L = %X'2'; literal KA0902_CPU$M_BCC_ENB_TPC_L = %X'4'; literal KA0902_CPU$M_BCC_FILL_WTP_L = %X'8'; literal KA0902_CPU$M_BCC_FILL_WCP_L = %X'10'; literal KA0902_CPU$M_BCC_FILL_WDTP_L = %X'20'; literal KA0902_CPU$M_BCC_ENB_CEI_L = %X'40'; literal KA0902_CPU$M_BCC_ENB_EDCC_L = %X'80'; literal KA0902_CPU$M_BCC_ENB_EDC_CHK_L = %X'100'; literal KA0902_CPU$M_BCC_ENB_BC_CIO_L = %X'200'; literal KA0902_CPU$M_BCC_DIS_BLK_W_L = %X'400'; literal KA0902_CPU$M_BCC_ENB_BC_INIT_L = %X'800'; literal KA0902_CPU$M_BCC_FOR_EDCC_L = %X'1000'; literal KA0902_CPU$M_BCC_SH_D_V_L = %X'E000'; literal KA0902_CPU$M_BCC_EDC_L = %X'3FFF0000'; literal KA0902_CPU$M_BCC_CACHE_SIZE_L = %X'C0000000'; literal KA0902_CPU$M_BCC_ENB_ALLOC_H = %X'1'; literal KA0902_CPU$M_BCC_FRC_FILL_SH_H = %X'2'; literal KA0902_CPU$M_BCC_ENB_TPC_H = %X'4'; literal KA0902_CPU$M_BCC_FILL_WTP_H = %X'8'; literal KA0902_CPU$M_BCC_FILL_WCP_H = %X'10'; literal KA0902_CPU$M_BCC_FILL_WDTP_H = %X'20'; literal KA0902_CPU$M_BCC_ENB_CEI_H = %X'40'; literal KA0902_CPU$M_BCC_ENB_EDCC_H = %X'80'; literal KA0902_CPU$M_BCC_ENB_EDC_CHK_H = %X'100'; literal KA0902_CPU$M_BCC_ENB_BC_CIO_H = %X'200'; literal KA0902_CPU$M_BCC_DIS_BLK_W_H = %X'400'; literal KA0902_CPU$M_BCC_ENB_BC_INIT_H = %X'800'; literal KA0902_CPU$M_BCC_FOR_EDCC_H = %X'1000'; literal KA0902_CPU$M_BCC_SH_D_V_H = %X'E000'; literal KA0902_CPU$M_BCC_EDC_L_H = %X'3FFF0000'; literal KA0902_CPU$M_BCC_CACHE_SIZE_H = %X'C0000000'; literal KA0902_BCC$K_RESERVED = 0; ! Reserved literal KA0902_BCC$K_CACHE_SIZE_1MB = 1; ! Cache size is 1Mb literal KA0902_BCC$K_CACHE_SIZE_4MB = 2; ! Cache size is 4Mb literal KA0902_CPU$M_BCCE_MCE_L = %X'4'; literal KA0902_CPU$M_BCCE_CE_L = %X'8'; literal KA0902_CPU$M_BCCE_CNTRL_PAR_L = %X'100'; literal KA0902_CPU$M_BCCE_SH_L = %X'200'; literal KA0902_CPU$M_BCCE_DIRTY_L = %X'400'; literal KA0902_CPU$M_BCCE_VALID_L = %X'800'; literal KA0902_CPU$M_BCCE_BC_EDC_L = %X'20000'; literal KA0902_CPU$M_BCCE_EDC_SYND_0 = %X'1FC0000'; literal KA0902_CPU$M_BCCE_EDC_SYND_2 = %X'FE000000'; literal KA0902_CPU$M_BCCE_MCE_H = %X'4'; literal KA0902_CPU$M_BCCE_CE_H = %X'8'; literal KA0902_CPU$M_BCCE_READ_ONLY = %X'1FFF0'; literal KA0902_CPU$M_BCCE_BC_EDC_H = %X'20000'; literal KA0902_CPU$M_BCCE_EDC_SYND_1 = %X'1FC0000'; literal KA0902_CPU$M_BCCE_EDC_SYND_3 = %X'FE000000'; literal KA0902_CPU$M_BCCEA_BCMAP_OFF_L = %X'1FFFF'; literal KA0902_CPU$M_BCCEA_TAG_PAR_L = %X'40000'; literal KA0902_CPU$M_BCCEA_TAG_VALUE_L = %X'7FF80000'; literal KA0902_CPU$M_BCCEA_BCMAP_OFF_H = %X'1FFFF'; literal KA0902_CPU$M_BCCEA_TAG_PAR_H = %X'40000'; literal KA0902_CPU$M_BCCEA_TAG_VALUE_H = %X'7FF80000'; literal KA0902_CPU$M_BCUE_MPE_L = %X'1'; literal KA0902_CPU$M_BCUE_PE_L = %X'2'; literal KA0902_CPU$M_BCUE_MUNCE_L = %X'4'; literal KA0902_CPU$M_BCUE_UNCE_L = %X'8'; literal KA0902_CPU$M_BCUE_CTRL_PAR_L = %X'100'; literal KA0902_CPU$M_BCUE_SH_L = %X'200'; literal KA0902_CPU$M_BCUE_DIRTY_L = %X'400'; literal KA0902_CPU$M_BCUE_VALID_L = %X'800'; literal KA0902_CPU$M_BCUE_BC_EDC_L = %X'20000'; literal KA0902_CPU$M_BCUE_EDC_SYND_0 = %X'1FC0000'; literal KA0902_CPU$M_BCUE_EDC_SYND_2 = %X'FE000000'; literal KA0902_CPU$M_BCUE_MPE_H = %X'1'; literal KA0902_CPU$M_BCUE_PE_H = %X'2'; literal KA0902_CPU$M_BCUE_MUNCE_H = %X'4'; literal KA0902_CPU$M_BCUE_UNCE_H = %X'8'; literal KA0902_CPU$M_BCUE_BC_EDC_H = %X'20000'; literal KA0902_CPU$M_BCUE_EDC_SYND_1 = %X'1FC0000'; literal KA0902_CPU$M_BCUE_EDC_SYND_3 = %X'FE000000'; literal KA0902_CPU$M_BCUEA_BCMAP_OFF_L = %X'1FFFF'; literal KA0902_CPU$M_BCUEA_PTP_L = %X'20000'; literal KA0902_CPU$M_BCUEA_TP_L = %X'40000'; literal KA0902_CPU$M_BCUEA_TV_L = %X'7FF80000'; literal KA0902_CPU$M_BCUEA_FILL1_L = %X'80000000'; literal KA0902_CPU$M_BCUEA_BCMAP_OFF_H = %X'1FFFF'; literal KA0902_CPU$M_BCUEA_PTP_H = %X'20000'; literal KA0902_CPU$M_BCUEA_TP_H = %X'40000'; literal KA0902_CPU$M_BCUEA_TV_H = %X'7FF80000'; literal KA0902_CPU$M_BCUEA_FILL1_H = %X'80000000'; literal KA0902_CPU$M_DTER_MDTER_L = %X'1'; literal KA0902_CPU$M_DTER_DTER_L = %X'2'; literal KA0902_CPU$M_DTER_TOFF_L = %X'3FC'; literal KA0902_CPU$M_DTER_BANK0_TAG_L = %X'7FC00'; literal KA0902_CPU$M_DTER_BANK0_PAR_L = %X'80000'; literal KA0902_CPU$M_DTER_BANK1_TAG_L = %X'1FF00000'; literal KA0902_CPU$M_DTER_BANK1_PAR_L = %X'20000000'; literal KA0902_CPU$M_DTER_MDTER_H = %X'1'; literal KA0902_CPU$M_DTER_DTER_H = %X'2'; literal KA0902_CPU$M_DTER_TOFF_H = %X'3FC'; literal KA0902_CPU$M_DTER_BANK0_TAG_H = %X'7FC00'; literal KA0902_CPU$M_DTER_BANK0_PAR_H = %X'80000'; literal KA0902_CPU$M_DTER_BANK1_TAG_H = %X'1FF00000'; literal KA0902_CPU$M_DTER_BANK1_PAR_H = %X'20000000'; literal KA0902_CPU$M_CBCTL_DWP_L = %X'1'; literal KA0902_CPU$M_CBCTL_CAWP_L = %X'6'; literal KA0902_CPU$M_CBCTL_EPC_L = %X'8'; literal KA0902_CPU$M_CBCTL_FRC_SH_L = %X'10'; literal KA0902_CPU$M_CBCTL_CMDER_ID_L = %X'E0'; literal KA0902_CPU$M_CBCTL_ACM_L = %X'700'; literal KA0902_CPU$M_CBCTL_ENB_CI_L = %X'800'; literal KA0902_CPU$M_CBCTL_RD_L = %X'1000'; literal KA0902_CPU$M_CBCTL_QW_2_SEL_L = %X'2000'; literal KA0902_CPU$M_CBCTL_SEL_DRACK_L = %X'4000'; literal KA0902_CPU$M_CBCTL_DWP_H = %X'1'; literal KA0902_CPU$M_CBCTL_CAWP_H = %X'6'; literal KA0902_CPU$M_CBCTL_EPC_H = %X'8'; literal KA0902_CPU$M_CBCTL_FRC_SH_H = %X'10'; literal KA0902_CPU$M_CBCTL_CMDER_ID_H = %X'E0'; literal KA0902_CPU$M_CBCTL_ACM_H = %X'700'; literal KA0902_CPU$M_CBCTL_ENB_CI_H = %X'800'; literal KA0902_CPU$M_CBCTL_RD_H = %X'1000'; literal KA0902_CPU$M_CBCTL_QW_2_SEL_H = %X'2000'; literal KA0902_CPU$M_CBCTL_SEL_DRACK_H = %X'4000'; literal KA0902_CPU$M_CBE_DIAG_L = %X'2'; literal KA0902_CPU$M_CBE_CAP_L = %X'4'; literal KA0902_CPU$M_CBE_MCAP_L = %X'8'; literal KA0902_CPU$M_CBE_PE_WRD_L = %X'10'; literal KA0902_CPU$M_CBE_MPE_WRD_L = %X'20'; literal KA0902_CPU$M_CBE_PE_RD_L = %X'40'; literal KA0902_CPU$M_CBE_MPE_RD_L = %X'80'; literal KA0902_CPU$M_CBE_CA_PE_LW0 = %X'100'; literal KA0902_CPU$M_CBE_CA_PE_LW2 = %X'200'; literal KA0902_CPU$M_CBE_D_PE_LW0 = %X'400'; literal KA0902_CPU$M_CBE_D_PE_LW2 = %X'800'; literal KA0902_CPU$M_CBE_D_PE_LW4 = %X'1000'; literal KA0902_CPU$M_CBE_D_PE_LW6 = %X'2000'; literal KA0902_CPU$M_CBE_CA_NACK_L = %X'4000'; literal KA0902_CPU$M_CBE_WR_DATA_NACK_L = %X'8000'; literal KA0902_CPU$M_CBE_MCOUNT_L = %X'3F000000'; literal KA0902_CPU$M_CBE_MADR_VALID_L = %X'40000000'; literal KA0902_CPU$M_CBE_DIAG_H = %X'2'; literal KA0902_CPU$M_CBE_CAP_H = %X'4'; literal KA0902_CPU$M_CBE_MCAP_H = %X'8'; literal KA0902_CPU$M_CBE_PE_WRD_H = %X'10'; literal KA0902_CPU$M_CBE_MPE_WRD_H = %X'20'; literal KA0902_CPU$M_CBE_PE_RD_H = %X'40'; literal KA0902_CPU$M_CBE_MPE_RD_H = %X'80'; literal KA0902_CPU$M_CBE_CA_PE_LW1 = %X'100'; literal KA0902_CPU$M_CBE_CA_PE_LW3 = %X'200'; literal KA0902_CPU$M_CBE_D_PE_LW1 = %X'400'; literal KA0902_CPU$M_CBE_D_PE_LW3 = %X'800'; literal KA0902_CPU$M_CBE_D_PE_LW5 = %X'1000'; literal KA0902_CPU$M_CBE_D_PE_LW7 = %X'2000'; literal KA0902_CPU$M_CBE_UNDEFINED = %X'4000'; literal KA0902_CPU$M_CBE_UNDEFINED2 = %X'8000'; literal KA0902_CPU$M_CBE_MCOUNT_H = %X'3F000000'; literal KA0902_CPU$M_CBE_MADR_VALID_H = %X'40000000'; literal KA0902_CPU$M_CBEAL_SBO_L = %X'3'; literal KA0902_CPU$M_CBEAL_ADDR_CAD_L = %X'FFFFFFFC'; literal KA0902_CPU$M_CBEAL_SBO_H = %X'3'; literal KA0902_CPU$M_CBEAL_ADDR_CAD_H = %X'FFFFFFFC'; literal KA0902_CPU$M_CBEAH_SB0_L = %X'3'; literal KA0902_CPU$M_CBEAH_EA_L = %X'3FFFC'; literal KA0902_CPU$M_CBEAH_T_TYPE_L = %X'1C0000'; literal KA0902_CPU$M_CBEAH_CMDR_ID_L = %X'E00000'; literal KA0902_CPU$M_CBEAH_SB1_L = %X'FF000000'; literal KA0902_CPU$M_CBEAH_SB0_H = %X'3'; literal KA0902_CPU$M_CBEAH_EA_H = %X'3FFFC'; literal KA0902_CPU$M_CBEAH_T_TYPE_H = %X'1C0000'; literal KA0902_CPU$M_CBEAH_CMDR_ID_H = %X'E00000'; literal KA0902_CPU$M_CBEAH_SB1_H = %X'FF000000'; literal KA0902_CPU$M_PMBX_FILL1_L = %X'FFFFFFFF'; literal KA0902_CPU$M_PMBX_FILL1_H = %X'FFFFFFFF'; literal KA0902_CPU$M_IPIR_UNDEFINED = %X'1'; literal KA0902_CPU$M_IPIR_REQ_INT_CPU = %X'1'; literal KA0902_CPU$M_IPIR_REQ_NODE_HALT = %X'8'; literal KA0902_CPU$M_SIC_UNDEFINED0 = %X'1'; literal KA0902_CPU$M_SIC_UNDEFINED1 = %X'2'; literal KA0902_CPU$M_SIC_EIC = %X'4'; literal KA0902_CPU$M_SIC_UNDEFINED2 = %X'8'; literal KA0902_CPU$M_SIC_IT_ICLEAR = %X'1'; literal KA0902_CPU$M_SIC_SYS_EVT_CLR = %X'2'; literal KA0902_CPU$M_SIC_UNDEFINED3 = %X'4'; literal KA0902_CPU$M_SIC_NODE_HALT_CLR = %X'8'; literal KA0902_CPU$M_ADLK_LA_V_L = %X'1'; literal KA0902_CPU$M_ADLK_LA_L = %X'FFFFFFF8'; literal KA0902_CPU$M_ADLK_LA_V_H = %X'1'; literal KA0902_CPU$M_ADLK_LA_H = %X'FFFFFFF8'; literal KA0902_CPU$M_MADRL_VALID_L = %X'1'; literal KA0902_CPU$M_MADRL_T_TYPE_L = %X'2'; literal KA0902_CPU$M_MADRL_ADDRESS_L = %X'FFFFFFFC'; literal KA0902_CPU$M_MADRL_VALID_H = %X'1'; literal KA0902_CPU$M_MADRL_T_TYPE_H = %X'2'; literal KA0902_CPU$M_MADRL_ADDRESS_H = %X'FFFFFFFC'; literal KA0902_CPU$M_CRREVS_REV_L = %X'F'; literal KA0902_CPU$M_CRREVS_CPU_MODE_L = %X'10'; literal KA0902_CPU$M_CRREVS_C3_SPEED_L = %X'FE0'; literal KA0902_CPU$M_CRREVS_SB0_L = %X'1000'; literal KA0902_CPU$M_CRREVS_FILL1_L = %X'2000'; literal KA0902_CPU$M_CRREVS_IO_RETRY_L = %X'4000'; literal KA0902_CPU$M_CRREVS_PCH_INV_L = %X'200000'; literal KA0902_CPU$M_CRREVS_REV_H = %X'F'; literal KA0902_CPU$M_CRREVS_CPU_MODE_H = %X'10'; literal KA0902_CPU$M_CRREVS_C3_SPEED_H = %X'FE0'; literal KA0902_CPU$M_CRREVS_SB0_H = %X'1000'; literal KA0902_CPU$M_CRREVS_FILL1_H = %X'2000'; literal KA0902_CPU$M_CRREVS_IO_RETRY_H = %X'4000'; literal KA0902_CPU$M_CRREVS_PCH_INV_H = %X'200000'; literal KA0902_CPU$S_KA0902_CPU = 488; ! B-Cache Control Register 0 macro KA0902_CPU$Q_BCC = 0,0,0,1 %; literal KA0902_CPU$S_BCC = 8; macro KA0902_CPU$L_BCC_L = 0,0,32,0 %; macro KA0902_CPU$V_BCC_ENB_ALLOC_L = 0,0,1,0 %; macro KA0902_CPU$V_BCC_FRC_FILL_SH_L = 0,1,1,0 %; macro KA0902_CPU$V_BCC_ENB_TPC_L = 0,2,1,0 %; macro KA0902_CPU$V_BCC_FILL_WTP_L = 0,3,1,0 %; macro KA0902_CPU$V_BCC_FILL_WCP_L = 0,4,1,0 %; macro KA0902_CPU$V_BCC_FILL_WDTP_L = 0,5,1,0 %; macro KA0902_CPU$V_BCC_ENB_CEI_L = 0,6,1,0 %; macro KA0902_CPU$V_BCC_ENB_EDCC_L = 0,7,1,0 %; macro KA0902_CPU$V_BCC_ENB_EDC_CHK_L = 0,8,1,0 %; macro KA0902_CPU$V_BCC_ENB_BC_CIO_L = 0,9,1,0 %; macro KA0902_CPU$V_BCC_DIS_BLK_W_L = 0,10,1,0 %; macro KA0902_CPU$V_BCC_ENB_BC_INIT_L = 0,11,1,0 %; macro KA0902_CPU$V_BCC_FOR_EDCC_L = 0,12,1,0 %; macro KA0902_CPU$V_BCC_SH_D_V_L = 0,13,3,0 %; literal KA0902_CPU$S_BCC_SH_D_V_L = 3; macro KA0902_CPU$V_BCC_EDC_L = 0,16,14,0 %; literal KA0902_CPU$S_BCC_EDC_L = 14; macro KA0902_CPU$V_BCC_CACHE_SIZE_L = 0,30,2,0 %; literal KA0902_CPU$S_BCC_CACHE_SIZE_L = 2; macro KA0902_CPU$L_BCC_H = 4,0,32,0 %; macro KA0902_CPU$V_BCC_ENB_ALLOC_H = 4,0,1,0 %; macro KA0902_CPU$V_BCC_FRC_FILL_SH_H = 4,1,1,0 %; macro KA0902_CPU$V_BCC_ENB_TPC_H = 4,2,1,0 %; macro KA0902_CPU$V_BCC_FILL_WTP_H = 4,3,1,0 %; macro KA0902_CPU$V_BCC_FILL_WCP_H = 4,4,1,0 %; macro KA0902_CPU$V_BCC_FILL_WDTP_H = 4,5,1,0 %; macro KA0902_CPU$V_BCC_ENB_CEI_H = 4,6,1,0 %; macro KA0902_CPU$V_BCC_ENB_EDCC_H = 4,7,1,0 %; macro KA0902_CPU$V_BCC_ENB_EDC_CHK_H = 4,8,1,0 %; macro KA0902_CPU$V_BCC_ENB_BC_CIO_H = 4,9,1,0 %; macro KA0902_CPU$V_BCC_DIS_BLK_W_H = 4,10,1,0 %; macro KA0902_CPU$V_BCC_ENB_BC_INIT_H = 4,11,1,0 %; macro KA0902_CPU$V_BCC_FOR_EDCC_H = 4,12,1,0 %; macro KA0902_CPU$V_BCC_SH_D_V_H = 4,13,3,0 %; literal KA0902_CPU$S_BCC_SH_D_V_H = 3; macro KA0902_CPU$V_BCC_EDC_L_H = 4,16,14,0 %; literal KA0902_CPU$S_BCC_EDC_L_H = 14; macro KA0902_CPU$V_BCC_CACHE_SIZE_H = 4,30,2,0 %; literal KA0902_CPU$S_BCC_CACHE_SIZE_H = 2; ! B-Cache Correctable Error Register, BCCE macro KA0902_CPU$Q_BCCE = 32,0,0,1 %; literal KA0902_CPU$S_BCCE = 8; macro KA0902_CPU$L_BCCE_L = 32,0,32,0 %; macro KA0902_CPU$V_BCCE_MCE_L = 32,2,1,0 %; macro KA0902_CPU$V_BCCE_CE_L = 32,3,1,0 %; macro KA0902_CPU$V_BCCE_CNTRL_PAR_L = 32,8,1,0 %; macro KA0902_CPU$V_BCCE_SH_L = 32,9,1,0 %; macro KA0902_CPU$V_BCCE_DIRTY_L = 32,10,1,0 %; macro KA0902_CPU$V_BCCE_VALID_L = 32,11,1,0 %; macro KA0902_CPU$V_BCCE_BC_EDC_L = 32,17,1,0 %; macro KA0902_CPU$V_BCCE_EDC_SYND_0 = 32,18,7,0 %; literal KA0902_CPU$S_BCCE_EDC_SYND_0 = 7; macro KA0902_CPU$V_BCCE_EDC_SYND_2 = 32,25,7,0 %; literal KA0902_CPU$S_BCCE_EDC_SYND_2 = 7; macro KA0902_CPU$L_BCCE_H = 36,0,32,0 %; macro KA0902_CPU$V_BCCE_MCE_H = 36,2,1,0 %; macro KA0902_CPU$V_BCCE_CE_H = 36,3,1,0 %; macro KA0902_CPU$V_BCCE_READ_ONLY = 36,4,13,0 %; literal KA0902_CPU$S_BCCE_READ_ONLY = 13; macro KA0902_CPU$V_BCCE_BC_EDC_H = 36,17,1,0 %; macro KA0902_CPU$V_BCCE_EDC_SYND_1 = 36,18,7,0 %; literal KA0902_CPU$S_BCCE_EDC_SYND_1 = 7; macro KA0902_CPU$V_BCCE_EDC_SYND_3 = 36,25,7,0 %; literal KA0902_CPU$S_BCCE_EDC_SYND_3 = 7; ! B-Cache Correctable Error Register, BCCEA macro KA0902_CPU$Q_BCCEA = 64,0,0,1 %; literal KA0902_CPU$S_BCCEA = 8; macro KA0902_CPU$L_BCCEA_L = 64,0,32,0 %; macro KA0902_CPU$V_BCCEA_BCMAP_OFF_L = 64,0,17,0 %; literal KA0902_CPU$S_BCCEA_BCMAP_OFF_L = 17; macro KA0902_CPU$V_BCCEA_TAG_PAR_L = 64,18,1,0 %; macro KA0902_CPU$V_BCCEA_TAG_VALUE_L = 64,19,12,0 %; literal KA0902_CPU$S_BCCEA_TAG_VALUE_L = 12; macro KA0902_CPU$L_BCCEA_H = 68,0,32,0 %; macro KA0902_CPU$V_BCCEA_BCMAP_OFF_H = 68,0,17,0 %; literal KA0902_CPU$S_BCCEA_BCMAP_OFF_H = 17; macro KA0902_CPU$V_BCCEA_TAG_PAR_H = 68,18,1,0 %; macro KA0902_CPU$V_BCCEA_TAG_VALUE_H = 68,19,12,0 %; literal KA0902_CPU$S_BCCEA_TAG_VALUE_H = 12; ! B-Cache UNCRectable Error Register, BCUE macro KA0902_CPU$Q_BCUE = 96,0,0,1 %; literal KA0902_CPU$S_BCUE = 8; macro KA0902_CPU$L_BCUE_L = 96,0,32,0 %; macro KA0902_CPU$V_BCUE_MPE_L = 96,0,1,0 %; macro KA0902_CPU$V_BCUE_PE_L = 96,1,1,0 %; macro KA0902_CPU$V_BCUE_MUNCE_L = 96,2,1,0 %; macro KA0902_CPU$V_BCUE_UNCE_L = 96,3,1,0 %; macro KA0902_CPU$V_BCUE_CTRL_PAR_L = 96,8,1,0 %; macro KA0902_CPU$V_BCUE_SH_L = 96,9,1,0 %; macro KA0902_CPU$V_BCUE_DIRTY_L = 96,10,1,0 %; macro KA0902_CPU$V_BCUE_VALID_L = 96,11,1,0 %; macro KA0902_CPU$V_BCUE_BC_EDC_L = 96,17,1,0 %; macro KA0902_CPU$V_BCUE_EDC_SYND_0 = 96,18,7,0 %; literal KA0902_CPU$S_BCUE_EDC_SYND_0 = 7; macro KA0902_CPU$V_BCUE_EDC_SYND_2 = 96,25,7,0 %; literal KA0902_CPU$S_BCUE_EDC_SYND_2 = 7; macro KA0902_CPU$L_BCUE_H = 100,0,32,0 %; macro KA0902_CPU$V_BCUE_MPE_H = 100,0,1,0 %; macro KA0902_CPU$V_BCUE_PE_H = 100,1,1,0 %; macro KA0902_CPU$V_BCUE_MUNCE_H = 100,2,1,0 %; macro KA0902_CPU$V_BCUE_UNCE_H = 100,3,1,0 %; macro KA0902_CPU$V_BCUE_BC_EDC_H = 100,17,1,0 %; macro KA0902_CPU$V_BCUE_EDC_SYND_1 = 100,18,7,0 %; literal KA0902_CPU$S_BCUE_EDC_SYND_1 = 7; macro KA0902_CPU$V_BCUE_EDC_SYND_3 = 100,25,7,0 %; literal KA0902_CPU$S_BCUE_EDC_SYND_3 = 7; ! B-Cache UNCRectable Error Address Register, BCUEA macro KA0902_CPU$Q_BCUEA = 128,0,0,1 %; literal KA0902_CPU$S_BCUEA = 8; macro KA0902_CPU$L_BCUEA_L = 128,0,32,0 %; macro KA0902_CPU$V_BCUEA_BCMAP_OFF_L = 128,0,17,0 %; literal KA0902_CPU$S_BCUEA_BCMAP_OFF_L = 17; macro KA0902_CPU$V_BCUEA_PTP_L = 128,17,1,0 %; macro KA0902_CPU$V_BCUEA_TP_L = 128,18,1,0 %; macro KA0902_CPU$V_BCUEA_TV_L = 128,19,12,0 %; literal KA0902_CPU$S_BCUEA_TV_L = 12; macro KA0902_CPU$V_BCUEA_FILL1_L = 128,31,1,0 %; macro KA0902_CPU$L_BCUEA_H = 132,0,32,0 %; macro KA0902_CPU$V_BCUEA_BCMAP_OFF_H = 132,0,17,0 %; literal KA0902_CPU$S_BCUEA_BCMAP_OFF_H = 17; macro KA0902_CPU$V_BCUEA_PTP_H = 132,17,1,0 %; macro KA0902_CPU$V_BCUEA_TP_H = 132,18,1,0 %; macro KA0902_CPU$V_BCUEA_TV_H = 132,19,12,0 %; literal KA0902_CPU$S_BCUEA_TV_H = 12; macro KA0902_CPU$V_BCUEA_FILL1_H = 132,31,1,0 %; ! Duplicate Tag Error Register DTER macro KA0902_CPU$Q_DTER = 160,0,0,1 %; literal KA0902_CPU$S_DTER = 8; macro KA0902_CPU$L_DTER_L = 160,0,32,0 %; macro KA0902_CPU$V_DTER_MDTER_L = 160,0,1,0 %; macro KA0902_CPU$V_DTER_DTER_L = 160,1,1,0 %; macro KA0902_CPU$V_DTER_TOFF_L = 160,2,8,0 %; literal KA0902_CPU$S_DTER_TOFF_L = 8; macro KA0902_CPU$V_DTER_BANK0_TAG_L = 160,10,9,0 %; literal KA0902_CPU$S_DTER_BANK0_TAG_L = 9; macro KA0902_CPU$V_DTER_BANK0_PAR_L = 160,19,1,0 %; macro KA0902_CPU$V_DTER_BANK1_TAG_L = 160,20,9,0 %; literal KA0902_CPU$S_DTER_BANK1_TAG_L = 9; macro KA0902_CPU$V_DTER_BANK1_PAR_L = 160,29,1,0 %; macro KA0902_CPU$L_DTER_H = 164,0,32,0 %; macro KA0902_CPU$V_DTER_MDTER_H = 164,0,1,0 %; macro KA0902_CPU$V_DTER_DTER_H = 164,1,1,0 %; macro KA0902_CPU$V_DTER_TOFF_H = 164,2,8,0 %; literal KA0902_CPU$S_DTER_TOFF_H = 8; macro KA0902_CPU$V_DTER_BANK0_TAG_H = 164,10,9,0 %; literal KA0902_CPU$S_DTER_BANK0_TAG_H = 9; macro KA0902_CPU$V_DTER_BANK0_PAR_H = 164,19,1,0 %; macro KA0902_CPU$V_DTER_BANK1_TAG_H = 164,20,9,0 %; literal KA0902_CPU$S_DTER_BANK1_TAG_H = 9; macro KA0902_CPU$V_DTER_BANK1_PAR_H = 164,29,1,0 %; ! Cobra bus Control Register - CBCTL macro KA0902_CPU$Q_CBCTL = 192,0,0,1 %; literal KA0902_CPU$S_CBCTL = 8; macro KA0902_CPU$L_CBCTL_L = 192,0,32,0 %; macro KA0902_CPU$V_CBCTL_DWP_L = 192,0,1,0 %; macro KA0902_CPU$V_CBCTL_CAWP_L = 192,1,2,0 %; literal KA0902_CPU$S_CBCTL_CAWP_L = 2; macro KA0902_CPU$V_CBCTL_EPC_L = 192,3,1,0 %; macro KA0902_CPU$V_CBCTL_FRC_SH_L = 192,4,1,0 %; macro KA0902_CPU$V_CBCTL_CMDER_ID_L = 192,5,3,0 %; literal KA0902_CPU$S_CBCTL_CMDER_ID_L = 3; macro KA0902_CPU$V_CBCTL_ACM_L = 192,8,3,0 %; literal KA0902_CPU$S_CBCTL_ACM_L = 3; macro KA0902_CPU$V_CBCTL_ENB_CI_L = 192,11,1,0 %; macro KA0902_CPU$V_CBCTL_RD_L = 192,12,1,0 %; macro KA0902_CPU$V_CBCTL_QW_2_SEL_L = 192,13,1,0 %; macro KA0902_CPU$V_CBCTL_SEL_DRACK_L = 192,14,1,0 %; macro KA0902_CPU$L_CBCTL_H = 196,0,32,0 %; macro KA0902_CPU$V_CBCTL_DWP_H = 196,0,1,0 %; macro KA0902_CPU$V_CBCTL_CAWP_H = 196,1,2,0 %; literal KA0902_CPU$S_CBCTL_CAWP_H = 2; macro KA0902_CPU$V_CBCTL_EPC_H = 196,3,1,0 %; macro KA0902_CPU$V_CBCTL_FRC_SH_H = 196,4,1,0 %; macro KA0902_CPU$V_CBCTL_CMDER_ID_H = 196,5,3,0 %; literal KA0902_CPU$S_CBCTL_CMDER_ID_H = 3; macro KA0902_CPU$V_CBCTL_ACM_H = 196,8,3,0 %; literal KA0902_CPU$S_CBCTL_ACM_H = 3; macro KA0902_CPU$V_CBCTL_ENB_CI_H = 196,11,1,0 %; macro KA0902_CPU$V_CBCTL_RD_H = 196,12,1,0 %; macro KA0902_CPU$V_CBCTL_QW_2_SEL_H = 196,13,1,0 %; macro KA0902_CPU$V_CBCTL_SEL_DRACK_H = 196,14,1,0 %; ! Cobra bus Error Register - CBE macro KA0902_CPU$Q_CBE = 224,0,0,1 %; literal KA0902_CPU$S_CBE = 8; macro KA0902_CPU$L_CBE_L = 224,0,32,0 %; macro KA0902_CPU$V_CBE_DIAG_L = 224,1,1,0 %; macro KA0902_CPU$V_CBE_CAP_L = 224,2,1,0 %; macro KA0902_CPU$V_CBE_MCAP_L = 224,3,1,0 %; macro KA0902_CPU$V_CBE_PE_WRD_L = 224,4,1,0 %; macro KA0902_CPU$V_CBE_MPE_WRD_L = 224,5,1,0 %; macro KA0902_CPU$V_CBE_PE_RD_L = 224,6,1,0 %; macro KA0902_CPU$V_CBE_MPE_RD_L = 224,7,1,0 %; macro KA0902_CPU$V_CBE_CA_PE_LW0 = 224,8,1,0 %; macro KA0902_CPU$V_CBE_CA_PE_LW2 = 224,9,1,0 %; macro KA0902_CPU$V_CBE_D_PE_LW0 = 224,10,1,0 %; macro KA0902_CPU$V_CBE_D_PE_LW2 = 224,11,1,0 %; macro KA0902_CPU$V_CBE_D_PE_LW4 = 224,12,1,0 %; macro KA0902_CPU$V_CBE_D_PE_LW6 = 224,13,1,0 %; macro KA0902_CPU$V_CBE_CA_NACK_L = 224,14,1,0 %; macro KA0902_CPU$V_CBE_WR_DATA_NACK_L = 224,15,1,0 %; macro KA0902_CPU$V_CBE_MCOUNT_L = 224,24,6,0 %; literal KA0902_CPU$S_CBE_MCOUNT_L = 6; macro KA0902_CPU$V_CBE_MADR_VALID_L = 224,30,1,0 %; macro KA0902_CPU$L_CBE_H = 228,0,32,0 %; macro KA0902_CPU$V_CBE_DIAG_H = 228,1,1,0 %; macro KA0902_CPU$V_CBE_CAP_H = 228,2,1,0 %; macro KA0902_CPU$V_CBE_MCAP_H = 228,3,1,0 %; macro KA0902_CPU$V_CBE_PE_WRD_H = 228,4,1,0 %; macro KA0902_CPU$V_CBE_MPE_WRD_H = 228,5,1,0 %; macro KA0902_CPU$V_CBE_PE_RD_H = 228,6,1,0 %; macro KA0902_CPU$V_CBE_MPE_RD_H = 228,7,1,0 %; macro KA0902_CPU$V_CBE_CA_PE_LW1 = 228,8,1,0 %; macro KA0902_CPU$V_CBE_CA_PE_LW3 = 228,9,1,0 %; macro KA0902_CPU$V_CBE_D_PE_LW1 = 228,10,1,0 %; macro KA0902_CPU$V_CBE_D_PE_LW3 = 228,11,1,0 %; macro KA0902_CPU$V_CBE_D_PE_LW5 = 228,12,1,0 %; macro KA0902_CPU$V_CBE_D_PE_LW7 = 228,13,1,0 %; macro KA0902_CPU$V_CBE_UNDEFINED = 228,14,1,0 %; macro KA0902_CPU$V_CBE_UNDEFINED2 = 228,15,1,0 %; macro KA0902_CPU$V_CBE_MCOUNT_H = 228,24,6,0 %; literal KA0902_CPU$S_CBE_MCOUNT_H = 6; macro KA0902_CPU$V_CBE_MADR_VALID_H = 228,30,1,0 %; ! Cobra bus Error Address Low Register - CBEAL macro KA0902_CPU$Q_CBEAL = 256,0,0,1 %; literal KA0902_CPU$S_CBEAL = 8; macro KA0902_CPU$L_CBEAL_L = 256,0,32,0 %; macro KA0902_CPU$V_CBEAL_SBO_L = 256,0,2,0 %; literal KA0902_CPU$S_CBEAL_SBO_L = 2; macro KA0902_CPU$V_CBEAL_ADDR_CAD_L = 256,2,30,0 %; literal KA0902_CPU$S_CBEAL_ADDR_CAD_L = 30; macro KA0902_CPU$L_CBEAL_H = 260,0,32,0 %; macro KA0902_CPU$V_CBEAL_SBO_H = 260,0,2,0 %; literal KA0902_CPU$S_CBEAL_SBO_H = 2; macro KA0902_CPU$V_CBEAL_ADDR_CAD_H = 260,2,30,0 %; literal KA0902_CPU$S_CBEAL_ADDR_CAD_H = 30; ! Cobra bus Error Address High Register - CBEAH macro KA0902_CPU$Q_CBEAH = 288,0,0,1 %; literal KA0902_CPU$S_CBEAH = 8; macro KA0902_CPU$L_CBEAH_L = 288,0,32,0 %; macro KA0902_CPU$V_CBEAH_SB0_L = 288,0,2,0 %; literal KA0902_CPU$S_CBEAH_SB0_L = 2; macro KA0902_CPU$V_CBEAH_EA_L = 288,2,16,0 %; literal KA0902_CPU$S_CBEAH_EA_L = 16; macro KA0902_CPU$V_CBEAH_T_TYPE_L = 288,18,3,0 %; literal KA0902_CPU$S_CBEAH_T_TYPE_L = 3; macro KA0902_CPU$V_CBEAH_CMDR_ID_L = 288,21,3,0 %; literal KA0902_CPU$S_CBEAH_CMDR_ID_L = 3; macro KA0902_CPU$V_CBEAH_SB1_L = 288,24,8,0 %; literal KA0902_CPU$S_CBEAH_SB1_L = 8; macro KA0902_CPU$L_CBEAH_H = 292,0,32,0 %; macro KA0902_CPU$V_CBEAH_SB0_H = 292,0,2,0 %; literal KA0902_CPU$S_CBEAH_SB0_H = 2; macro KA0902_CPU$V_CBEAH_EA_H = 292,2,16,0 %; literal KA0902_CPU$S_CBEAH_EA_H = 16; macro KA0902_CPU$V_CBEAH_T_TYPE_H = 292,18,3,0 %; literal KA0902_CPU$S_CBEAH_T_TYPE_H = 3; macro KA0902_CPU$V_CBEAH_CMDR_ID_H = 292,21,3,0 %; literal KA0902_CPU$S_CBEAH_CMDR_ID_H = 3; macro KA0902_CPU$V_CBEAH_SB1_H = 292,24,8,0 %; literal KA0902_CPU$S_CBEAH_SB1_H = 8; ! Processor Mailbox Register - PMBX macro KA0902_CPU$Q_PMBX = 320,0,0,1 %; literal KA0902_CPU$S_PMBX = 8; macro KA0902_CPU$L_PMBX_L = 320,0,32,0 %; macro KA0902_CPU$V_PMBX_FILL1_L = 320,0,32,0 %; literal KA0902_CPU$S_PMBX_FILL1_L = 32; macro KA0902_CPU$L_PMBX_H = 324,0,32,0 %; macro KA0902_CPU$V_PMBX_FILL1_H = 324,0,32,0 %; literal KA0902_CPU$S_PMBX_FILL1_H = 32; ! Interprocessor Interrupt Request Register - IPIR macro KA0902_CPU$Q_IPIR = 352,0,0,1 %; literal KA0902_CPU$S_IPIR = 8; macro KA0902_CPU$L_IPIR_L = 352,0,32,0 %; macro KA0902_CPU$V_IPIR_UNDEFINED = 352,0,1,0 %; macro KA0902_CPU$L_IPIR_H = 356,0,32,0 %; macro KA0902_CPU$V_IPIR_REQ_INT_CPU = 356,0,1,0 %; macro KA0902_CPU$V_IPIR_REQ_NODE_HALT = 356,3,1,0 %; ! System Interrupt Clear Register - SIC macro KA0902_CPU$Q_SIC = 384,0,0,1 %; literal KA0902_CPU$S_SIC = 8; macro KA0902_CPU$L_SIC_L = 384,0,32,0 %; macro KA0902_CPU$V_SIC_UNDEFINED0 = 384,0,1,0 %; macro KA0902_CPU$V_SIC_UNDEFINED1 = 384,1,1,0 %; macro KA0902_CPU$V_SIC_EIC = 384,2,1,0 %; macro KA0902_CPU$V_SIC_UNDEFINED2 = 384,3,1,0 %; macro KA0902_CPU$L_SIC_H = 388,0,32,0 %; macro KA0902_CPU$V_SIC_IT_ICLEAR = 388,0,1,0 %; macro KA0902_CPU$V_SIC_SYS_EVT_CLR = 388,1,1,0 %; macro KA0902_CPU$V_SIC_UNDEFINED3 = 388,2,1,0 %; macro KA0902_CPU$V_SIC_NODE_HALT_CLR = 388,3,1,0 %; ! Address Lock Register - ADLK macro KA0902_CPU$Q_ADLK = 416,0,0,1 %; literal KA0902_CPU$S_ADLK = 8; macro KA0902_CPU$L_ADLK_L = 416,0,32,0 %; macro KA0902_CPU$V_ADLK_LA_V_L = 416,0,1,0 %; macro KA0902_CPU$V_ADLK_LA_L = 416,3,29,0 %; literal KA0902_CPU$S_ADLK_LA_L = 29; macro KA0902_CPU$L_ADLK_H = 420,0,32,0 %; macro KA0902_CPU$V_ADLK_LA_V_H = 420,0,1,0 %; macro KA0902_CPU$V_ADLK_LA_H = 420,3,29,0 %; literal KA0902_CPU$S_ADLK_LA_H = 29; ! Miss Address Register - MADRL macro KA0902_CPU$Q_MADRL = 448,0,0,1 %; literal KA0902_CPU$S_MADRL = 8; macro KA0902_CPU$L_MADRL_L = 448,0,32,0 %; macro KA0902_CPU$V_MADRL_VALID_L = 448,0,1,0 %; macro KA0902_CPU$V_MADRL_T_TYPE_L = 448,1,1,0 %; macro KA0902_CPU$V_MADRL_ADDRESS_L = 448,2,30,0 %; literal KA0902_CPU$S_MADRL_ADDRESS_L = 30; macro KA0902_CPU$L_MADRL_H = 452,0,32,0 %; macro KA0902_CPU$V_MADRL_VALID_H = 452,0,1,0 %; macro KA0902_CPU$V_MADRL_T_TYPE_H = 452,1,1,0 %; macro KA0902_CPU$V_MADRL_ADDRESS_H = 452,2,30,0 %; literal KA0902_CPU$S_MADRL_ADDRESS_H = 30; ! C3 revision Register - CRREVS macro KA0902_CPU$Q_CRREVS = 480,0,0,1 %; literal KA0902_CPU$S_CRREVS = 8; macro KA0902_CPU$L_CRREVS_L = 480,0,32,0 %; macro KA0902_CPU$V_CRREVS_REV_L = 480,0,4,0 %; literal KA0902_CPU$S_CRREVS_REV_L = 4; macro KA0902_CPU$V_CRREVS_CPU_MODE_L = 480,4,1,0 %; macro KA0902_CPU$V_CRREVS_C3_SPEED_L = 480,5,7,0 %; literal KA0902_CPU$S_CRREVS_C3_SPEED_L = 7; macro KA0902_CPU$V_CRREVS_SB0_L = 480,12,1,0 %; macro KA0902_CPU$V_CRREVS_IO_RETRY_L = 480,14,1,0 %; macro KA0902_CPU$V_CRREVS_PCH_INV_L = 480,21,1,0 %; macro KA0902_CPU$L_CRREVS_H = 484,0,32,0 %; macro KA0902_CPU$V_CRREVS_REV_H = 484,0,4,0 %; literal KA0902_CPU$S_CRREVS_REV_H = 4; macro KA0902_CPU$V_CRREVS_CPU_MODE_H = 484,4,1,0 %; macro KA0902_CPU$V_CRREVS_C3_SPEED_H = 484,5,7,0 %; literal KA0902_CPU$S_CRREVS_C3_SPEED_H = 7; macro KA0902_CPU$V_CRREVS_SB0_H = 484,12,1,0 %; macro KA0902_CPU$V_CRREVS_IO_RETRY_H = 484,14,1,0 %; macro KA0902_CPU$V_CRREVS_PCH_INV_H = 484,21,1,0 %; literal KA0902_CPU$K_LENGTH = 488; ! ! Sable Memory Module register definitions ! literal KA0902_SMM$M_CME_ES_L = %X'1'; literal KA0902_SMM$M_CME_SE_L = %X'2'; literal KA0902_SMM$M_CME_CA_PE_L = %X'4'; literal KA0902_SMM$M_CME_MCA_PE_L = %X'8'; literal KA0902_SMM$M_CME_WD_PE_L = %X'10'; literal KA0902_SMM$M_CME_MWD_PE_L = %X'20'; literal KA0902_SMM$M_CME_CA_PE_LW0 = %X'100'; literal KA0902_SMM$M_CME_CA_PE_LW2 = %X'200'; literal KA0902_SMM$M_CME_D_PE_LW0 = %X'400'; literal KA0902_SMM$M_CME_D_PE_LW2 = %X'800'; literal KA0902_SMM$M_CME_D_PE_LW4 = %X'1000'; literal KA0902_SMM$M_CME_D_PE_LW6 = %X'2000'; literal KA0902_SMM$M_CME_EUE_L = %X'10000'; literal KA0902_SMM$M_CME_MEUE_L = %X'20000'; literal KA0902_SMM$M_CME_ECE_L = %X'40000'; literal KA0902_SMM$M_CME_MECE_L = %X'80000'; literal KA0902_SMM$M_CME_ES_H = %X'1'; literal KA0902_SMM$M_CME_SE_H = %X'2'; literal KA0902_SMM$M_CME_CA_PE_H = %X'4'; literal KA0902_SMM$M_CME_MCA_PE_H = %X'8'; literal KA0902_SMM$M_CME_WD_PE_H = %X'10'; literal KA0902_SMM$M_CME_MWD_PE_H = %X'20'; literal KA0902_SMM$M_CME_CA_PE_LW1 = %X'100'; literal KA0902_SMM$M_CME_CA_PE_LW3 = %X'200'; literal KA0902_SMM$M_CME_D_PE_LW1 = %X'400'; literal KA0902_SMM$M_CME_D_PE_LW3 = %X'800'; literal KA0902_SMM$M_CME_D_PE_LW5 = %X'1000'; literal KA0902_SMM$M_CME_D_PE_LW7 = %X'2000'; literal KA0902_SMM$M_CME_EUE_H = %X'10000'; literal KA0902_SMM$M_CME_MEUE_H = %X'20000'; literal KA0902_SMM$M_CME_ECE_H = %X'40000'; literal KA0902_SMM$M_CME_MECE_H = %X'80000'; literal KA0902_SMM$M_CNFG_MID_L = %X'3'; literal KA0902_SMM$M_CNFG_DRAM_ACC_L = %X'8'; literal KA0902_SMM$M_CNFG_MSIZE_L = %X'F0'; literal KA0902_SMM$M_CNFG_DIAG_L = %X'100'; literal KA0902_SMM$M_CNFG_CSIC_REV_L = %X'F000'; literal KA0902_SMM$M_CNFG_ALT_CSR_L = %X'10000'; literal KA0902_SMM$M_CNFG_ILVM_L = %X'C0000'; literal KA0902_SMM$M_CNFG_ILVU_L = %X'300000'; literal KA0902_SMM$M_CNFG_BASE_ADR_L = %X'7F800000'; literal KA0902_SMM$M_CNFG_MEM_ENA_L = %X'80000000'; literal KA0902_SMM$M_CNFG_MID_H = %X'3'; literal KA0902_SMM$M_CNFG_DRAM_ACC_H = %X'8'; literal KA0902_SMM$M_CNFG_MSIZE_H = %X'F0'; literal KA0902_SMM$M_CNFG_DIAG_H = %X'100'; literal KA0902_SMM$M_CNFG_CSIC_REV_H = %X'F000'; literal KA0902_SMM$M_CNFG_ALT_CSR_H = %X'10000'; literal KA0902_SMM$M_CNFG_ILVM_H = %X'C0000'; literal KA0902_SMM$M_CNFG_ILVU_H = %X'300000'; literal KA0902_SMM$M_CNFG_BASE_ADR_H = %X'7F800000'; literal KA0902_SMM$M_CNFG_MEM_ENA_H = %X'80000000'; literal KA0902_SMM$M_EDC1_READ_CBITS_L = %X'FFF'; literal KA0902_SMM$M_EDC1_WR_CBITS_L = %X'FFF0000'; literal KA0902_SMM$M_EDC1_READ_CBITS_H = %X'FFF'; literal KA0902_SMM$M_EDC1_WR_CBITS_H = %X'FFF0000'; literal KA0902_SMM$M_EDC2_SYNDROME_L = %X'FFF'; literal KA0902_SMM$M_EDC2_SYNDROME_H = %X'FFF'; literal KA0902_SMM$M_EDCTL_SRB_L = %X'FFF'; literal KA0902_SMM$M_EDCTL_USCB_L = %X'1000'; literal KA0902_SMM$M_EDCTL_USWCB_L = %X'2000'; literal KA0902_SMM$M_EDCTL_DIPC_L = %X'4000'; literal KA0902_SMM$M_EDCTL_ENB_ES_L = %X'8000'; literal KA0902_SMM$M_EDCTL_SWCB_L = %X'FFF0000'; literal KA0902_SMM$M_EDCTL_CRDP_L = %X'10000000'; literal KA0902_SMM$M_EDCTL_ENB_CRDR_L = %X'20000000'; literal KA0902_SMM$M_EDCTL_DEDCCORR_L = %X'40000000'; literal KA0902_SMM$M_EDCTL_DEDCREPORT_L = %X'80000000'; literal KA0902_SMM$M_EDCTL_SRB_H = %X'FFF'; literal KA0902_SMM$M_EDCTL_USCB_H = %X'1000'; literal KA0902_SMM$M_EDCTL_USWCB_H = %X'2000'; literal KA0902_SMM$M_EDCTL_DIPC_H = %X'4000'; literal KA0902_SMM$M_EDCTL_ENB_ES_H = %X'8000'; literal KA0902_SMM$M_EDCTL_SWCB_H = %X'FFF0000'; literal KA0902_SMM$M_EDCTL_CRDP_H = %X'10000000'; literal KA0902_SMM$M_EDCTL_ENB_CRDR_H = %X'20000000'; literal KA0902_SMM$M_EDCTL_DEDCCORR_H = %X'40000000'; literal KA0902_SMM$M_EDCTL_DEDCREPORT_H = %X'80000000'; literal KA0902_SMM$M_SBCTRL_DSD_L = %X'1'; literal KA0902_SMM$M_SBCTRL_DSH_L = %X'2'; literal KA0902_SMM$M_SBCTRL_DSF_L = %X'4'; literal KA0902_SMM$M_SBCTRL_DSI_L = %X'8'; literal KA0902_SMM$M_SBCTRL_ERWD_L = %X'10'; literal KA0902_SMM$M_SBCTRL_FHB_L = %X'20'; literal KA0902_SMM$M_SBCTRL_FILL1_L = %X'C0'; literal KA0902_SMM$M_SBCTRL_HBSM_L = %X'100'; literal KA0902_SMM$M_SBCTRL_HBHF_L = %X'200'; literal KA0902_SMM$M_SBCTRL_FL_L = %X'400'; literal KA0902_SMM$M_SBCTRL_DSD_H = %X'1'; literal KA0902_SMM$M_SBCTRL_DSH_H = %X'2'; literal KA0902_SMM$M_SBCTRL_DSF_H = %X'4'; literal KA0902_SMM$M_SBCTRL_DSI_H = %X'8'; literal KA0902_SMM$M_SBCTRL_ERWD_H = %X'10'; literal KA0902_SMM$M_SBCTRL_FHB_H = %X'20'; literal KA0902_SMM$M_SBCTRL_FILL1_H = %X'C0'; literal KA0902_SMM$M_SBCTRL_HBSM_H = %X'100'; literal KA0902_SMM$M_SBCTRL_HBHF_H = %X'200'; literal KA0902_SMM$M_SBCTRL_FL_H = %X'400'; literal KA0902_SMM$M_RCTRL_RC_L = %X'FF'; literal KA0902_SMM$M_RCTRL_REF_ENB_L = %X'100'; literal KA0902_SMM$M_RCTRL_NUT_L = %X'1000'; literal KA0902_SMM$M_RCTRL_HIT_L = %X'2000'; literal KA0902_SMM$M_RCTRL_RC_H = %X'FF'; literal KA0902_SMM$M_RCTRL_REF_ENB_H = %X'100'; literal KA0902_SMM$M_RCTRL_NUT_H = %X'1000'; literal KA0902_SMM$M_RCTRL_HIT_H = %X'2000'; literal KA0902_SMM$M_CRDCTL_SM_L = %X'FFF'; literal KA0902_SMM$M_CRDCTL_BS_L = %X'3000'; literal KA0902_SMM$M_CRDCTL_CFE_L = %X'4000'; literal KA0902_SMM$M_CRDCTL_SM_H = %X'FFF'; literal KA0902_SMM$M_CRDCTL_BS_H = %X'3000'; literal KA0902_SMM$M_CRDCTL_CFE_H = %X'4000'; literal KA0902_SMM$S_KA0902_SMM = 296; ! Sable Memory Module CSR0 Error Register macro KA0902_SMM$Q_CME = 0,0,0,1 %; literal KA0902_SMM$S_CME = 8; macro KA0902_SMM$L_CME_L = 0,0,32,0 %; macro KA0902_SMM$V_CME_ES_L = 0,0,1,0 %; macro KA0902_SMM$V_CME_SE_L = 0,1,1,0 %; macro KA0902_SMM$V_CME_CA_PE_L = 0,2,1,0 %; macro KA0902_SMM$V_CME_MCA_PE_L = 0,3,1,0 %; macro KA0902_SMM$V_CME_WD_PE_L = 0,4,1,0 %; macro KA0902_SMM$V_CME_MWD_PE_L = 0,5,1,0 %; macro KA0902_SMM$V_CME_CA_PE_LW0 = 0,8,1,0 %; macro KA0902_SMM$V_CME_CA_PE_LW2 = 0,9,1,0 %; macro KA0902_SMM$V_CME_D_PE_LW0 = 0,10,1,0 %; macro KA0902_SMM$V_CME_D_PE_LW2 = 0,11,1,0 %; macro KA0902_SMM$V_CME_D_PE_LW4 = 0,12,1,0 %; macro KA0902_SMM$V_CME_D_PE_LW6 = 0,13,1,0 %; macro KA0902_SMM$V_CME_EUE_L = 0,16,1,0 %; macro KA0902_SMM$V_CME_MEUE_L = 0,17,1,0 %; macro KA0902_SMM$V_CME_ECE_L = 0,18,1,0 %; macro KA0902_SMM$V_CME_MECE_L = 0,19,1,0 %; macro KA0902_SMM$L_CME_H = 4,0,32,0 %; macro KA0902_SMM$V_CME_ES_H = 4,0,1,0 %; macro KA0902_SMM$V_CME_SE_H = 4,1,1,0 %; macro KA0902_SMM$V_CME_CA_PE_H = 4,2,1,0 %; macro KA0902_SMM$V_CME_MCA_PE_H = 4,3,1,0 %; macro KA0902_SMM$V_CME_WD_PE_H = 4,4,1,0 %; macro KA0902_SMM$V_CME_MWD_PE_H = 4,5,1,0 %; macro KA0902_SMM$V_CME_CA_PE_LW1 = 4,8,1,0 %; macro KA0902_SMM$V_CME_CA_PE_LW3 = 4,9,1,0 %; macro KA0902_SMM$V_CME_D_PE_LW1 = 4,10,1,0 %; macro KA0902_SMM$V_CME_D_PE_LW3 = 4,11,1,0 %; macro KA0902_SMM$V_CME_D_PE_LW5 = 4,12,1,0 %; macro KA0902_SMM$V_CME_D_PE_LW7 = 4,13,1,0 %; macro KA0902_SMM$V_CME_EUE_H = 4,16,1,0 %; macro KA0902_SMM$V_CME_MEUE_H = 4,17,1,0 %; macro KA0902_SMM$V_CME_ECE_H = 4,18,1,0 %; macro KA0902_SMM$V_CME_MECE_H = 4,19,1,0 %; ! Sable Memory Module CSR1 Command Trap 1 macro KA0902_SMM$Q_TRAP1 = 32,0,0,1 %; literal KA0902_SMM$S_TRAP1 = 8; macro KA0902_SMM$L_TRAP1_L = 32,0,32,0 %; macro KA0902_SMM$L_TRAP1_H = 36,0,32,0 %; ! Sable Memory Module CSR2 Command Trap 2 macro KA0902_SMM$Q_TRAP2 = 64,0,0,1 %; literal KA0902_SMM$S_TRAP2 = 8; macro KA0902_SMM$L_TRAP2_L = 64,0,32,0 %; macro KA0902_SMM$L_TRAP2_H = 68,0,32,0 %; ! Sable Memory Module CSR3 Configuration macro KA0902_SMM$Q_CNFG = 96,0,0,1 %; literal KA0902_SMM$S_CNFG = 8; macro KA0902_SMM$L_CNFG_L = 96,0,32,0 %; macro KA0902_SMM$V_CNFG_MID_L = 96,0,2,0 %; literal KA0902_SMM$S_CNFG_MID_L = 2; macro KA0902_SMM$V_CNFG_DRAM_ACC_L = 96,3,1,0 %; macro KA0902_SMM$V_CNFG_MSIZE_L = 96,4,4,0 %; literal KA0902_SMM$S_CNFG_MSIZE_L = 4; macro KA0902_SMM$V_CNFG_DIAG_L = 96,8,1,0 %; macro KA0902_SMM$V_CNFG_CSIC_REV_L = 96,12,4,0 %; literal KA0902_SMM$S_CNFG_CSIC_REV_L = 4; macro KA0902_SMM$V_CNFG_ALT_CSR_L = 96,16,1,0 %; macro KA0902_SMM$V_CNFG_ILVM_L = 96,18,2,0 %; literal KA0902_SMM$S_CNFG_ILVM_L = 2; macro KA0902_SMM$V_CNFG_ILVU_L = 96,20,2,0 %; literal KA0902_SMM$S_CNFG_ILVU_L = 2; macro KA0902_SMM$V_CNFG_BASE_ADR_L = 96,23,8,0 %; literal KA0902_SMM$S_CNFG_BASE_ADR_L = 8; macro KA0902_SMM$V_CNFG_MEM_ENA_L = 96,31,1,0 %; macro KA0902_SMM$L_CNFG_H = 100,0,32,0 %; macro KA0902_SMM$V_CNFG_MID_H = 100,0,2,0 %; literal KA0902_SMM$S_CNFG_MID_H = 2; macro KA0902_SMM$V_CNFG_DRAM_ACC_H = 100,3,1,0 %; macro KA0902_SMM$V_CNFG_MSIZE_H = 100,4,4,0 %; literal KA0902_SMM$S_CNFG_MSIZE_H = 4; macro KA0902_SMM$V_CNFG_DIAG_H = 100,8,1,0 %; macro KA0902_SMM$V_CNFG_CSIC_REV_H = 100,12,4,0 %; literal KA0902_SMM$S_CNFG_CSIC_REV_H = 4; macro KA0902_SMM$V_CNFG_ALT_CSR_H = 100,16,1,0 %; macro KA0902_SMM$V_CNFG_ILVM_H = 100,18,2,0 %; literal KA0902_SMM$S_CNFG_ILVM_H = 2; macro KA0902_SMM$V_CNFG_ILVU_H = 100,20,2,0 %; literal KA0902_SMM$S_CNFG_ILVU_H = 2; macro KA0902_SMM$V_CNFG_BASE_ADR_H = 100,23,8,0 %; literal KA0902_SMM$S_CNFG_BASE_ADR_H = 8; macro KA0902_SMM$V_CNFG_MEM_ENA_H = 100,31,1,0 %; ! Sable Memory Module CSR4 EDC Status 1 macro KA0902_SMM$Q_EDC1 = 128,0,0,1 %; literal KA0902_SMM$S_EDC1 = 8; macro KA0902_SMM$L_EDC1_L = 128,0,32,0 %; macro KA0902_SMM$V_EDC1_READ_CBITS_L = 128,0,12,0 %; literal KA0902_SMM$S_EDC1_READ_CBITS_L = 12; macro KA0902_SMM$V_EDC1_WR_CBITS_L = 128,16,12,0 %; literal KA0902_SMM$S_EDC1_WR_CBITS_L = 12; macro KA0902_SMM$L_EDC1_H = 132,0,32,0 %; macro KA0902_SMM$V_EDC1_READ_CBITS_H = 132,0,12,0 %; literal KA0902_SMM$S_EDC1_READ_CBITS_H = 12; macro KA0902_SMM$V_EDC1_WR_CBITS_H = 132,16,12,0 %; literal KA0902_SMM$S_EDC1_WR_CBITS_H = 12; ! Sable Memory Module CSR5 EDC Status 2 macro KA0902_SMM$Q_EDC2 = 160,0,0,1 %; literal KA0902_SMM$S_EDC2 = 8; macro KA0902_SMM$L_EDC2_L = 160,0,32,0 %; macro KA0902_SMM$V_EDC2_SYNDROME_L = 160,0,12,0 %; literal KA0902_SMM$S_EDC2_SYNDROME_L = 12; macro KA0902_SMM$L_EDC2_H = 164,0,32,0 %; macro KA0902_SMM$V_EDC2_SYNDROME_H = 164,0,12,0 %; literal KA0902_SMM$S_EDC2_SYNDROME_H = 12; ! Sable Memory Module CSR6 EDC Control macro KA0902_SMM$Q_EDCTL = 192,0,0,1 %; literal KA0902_SMM$S_EDCTL = 8; macro KA0902_SMM$L_EDCTL_L = 192,0,32,0 %; macro KA0902_SMM$V_EDCTL_SRB_L = 192,0,12,0 %; literal KA0902_SMM$S_EDCTL_SRB_L = 12; macro KA0902_SMM$V_EDCTL_USCB_L = 192,12,1,0 %; macro KA0902_SMM$V_EDCTL_USWCB_L = 192,13,1,0 %; macro KA0902_SMM$V_EDCTL_DIPC_L = 192,14,1,0 %; macro KA0902_SMM$V_EDCTL_ENB_ES_L = 192,15,1,0 %; macro KA0902_SMM$V_EDCTL_SWCB_L = 192,16,12,0 %; literal KA0902_SMM$S_EDCTL_SWCB_L = 12; macro KA0902_SMM$V_EDCTL_CRDP_L = 192,28,1,0 %; macro KA0902_SMM$V_EDCTL_ENB_CRDR_L = 192,29,1,0 %; macro KA0902_SMM$V_EDCTL_DEDCCORR_L = 192,30,1,0 %; macro KA0902_SMM$V_EDCTL_DEDCREPORT_L = 192,31,1,0 %; macro KA0902_SMM$L_EDCTL_H = 196,0,32,0 %; macro KA0902_SMM$V_EDCTL_SRB_H = 196,0,12,0 %; literal KA0902_SMM$S_EDCTL_SRB_H = 12; macro KA0902_SMM$V_EDCTL_USCB_H = 196,12,1,0 %; macro KA0902_SMM$V_EDCTL_USWCB_H = 196,13,1,0 %; macro KA0902_SMM$V_EDCTL_DIPC_H = 196,14,1,0 %; macro KA0902_SMM$V_EDCTL_ENB_ES_H = 196,15,1,0 %; macro KA0902_SMM$V_EDCTL_SWCB_H = 196,16,12,0 %; literal KA0902_SMM$S_EDCTL_SWCB_H = 12; macro KA0902_SMM$V_EDCTL_CRDP_H = 196,28,1,0 %; macro KA0902_SMM$V_EDCTL_ENB_CRDR_H = 196,29,1,0 %; macro KA0902_SMM$V_EDCTL_DEDCCORR_H = 196,30,1,0 %; macro KA0902_SMM$V_EDCTL_DEDCREPORT_H = 196,31,1,0 %; ! Sable Memory Module CSR7 Stream Buffer Control macro KA0902_SMM$Q_SBCTRL = 224,0,0,1 %; literal KA0902_SMM$S_SBCTRL = 8; macro KA0902_SMM$L_SBCTRL_L = 224,0,32,0 %; macro KA0902_SMM$V_SBCTRL_DSD_L = 224,0,1,0 %; macro KA0902_SMM$V_SBCTRL_DSH_L = 224,1,1,0 %; macro KA0902_SMM$V_SBCTRL_DSF_L = 224,2,1,0 %; macro KA0902_SMM$V_SBCTRL_DSI_L = 224,3,1,0 %; macro KA0902_SMM$V_SBCTRL_ERWD_L = 224,4,1,0 %; macro KA0902_SMM$V_SBCTRL_FHB_L = 224,5,1,0 %; macro KA0902_SMM$V_SBCTRL_FILL1_L = 224,6,2,0 %; literal KA0902_SMM$S_SBCTRL_FILL1_L = 2; macro KA0902_SMM$V_SBCTRL_HBSM_L = 224,8,1,0 %; macro KA0902_SMM$V_SBCTRL_HBHF_L = 224,9,1,0 %; macro KA0902_SMM$V_SBCTRL_FL_L = 224,10,1,0 %; macro KA0902_SMM$L_SBCTRL_H = 228,0,32,0 %; macro KA0902_SMM$V_SBCTRL_DSD_H = 228,0,1,0 %; macro KA0902_SMM$V_SBCTRL_DSH_H = 228,1,1,0 %; macro KA0902_SMM$V_SBCTRL_DSF_H = 228,2,1,0 %; macro KA0902_SMM$V_SBCTRL_DSI_H = 228,3,1,0 %; macro KA0902_SMM$V_SBCTRL_ERWD_H = 228,4,1,0 %; macro KA0902_SMM$V_SBCTRL_FHB_H = 228,5,1,0 %; macro KA0902_SMM$V_SBCTRL_FILL1_H = 228,6,2,0 %; literal KA0902_SMM$S_SBCTRL_FILL1_H = 2; macro KA0902_SMM$V_SBCTRL_HBSM_H = 228,8,1,0 %; macro KA0902_SMM$V_SBCTRL_HBHF_H = 228,9,1,0 %; macro KA0902_SMM$V_SBCTRL_FL_H = 228,10,1,0 %; ! Sable Memory Module CSR8 Refresh control macro KA0902_SMM$Q_RCTRL = 256,0,0,1 %; literal KA0902_SMM$S_RCTRL = 8; macro KA0902_SMM$L_RCTRL_L = 256,0,32,0 %; macro KA0902_SMM$V_RCTRL_RC_L = 256,0,8,0 %; literal KA0902_SMM$S_RCTRL_RC_L = 8; macro KA0902_SMM$V_RCTRL_REF_ENB_L = 256,8,1,0 %; macro KA0902_SMM$V_RCTRL_NUT_L = 256,12,1,0 %; macro KA0902_SMM$V_RCTRL_HIT_L = 256,13,1,0 %; macro KA0902_SMM$L_RCTRL_H = 260,0,32,0 %; macro KA0902_SMM$V_RCTRL_RC_H = 260,0,8,0 %; literal KA0902_SMM$S_RCTRL_RC_H = 8; macro KA0902_SMM$V_RCTRL_REF_ENB_H = 260,8,1,0 %; macro KA0902_SMM$V_RCTRL_NUT_H = 260,12,1,0 %; macro KA0902_SMM$V_RCTRL_HIT_H = 260,13,1,0 %; ! Sable Memory Module CSR9 CRD Filter control macro KA0902_SMM$Q_CRDCTL = 288,0,0,1 %; literal KA0902_SMM$S_CRDCTL = 8; macro KA0902_SMM$L_CRDCTL_L = 288,0,32,0 %; macro KA0902_SMM$V_CRDCTL_SM_L = 288,0,12,0 %; literal KA0902_SMM$S_CRDCTL_SM_L = 12; macro KA0902_SMM$V_CRDCTL_BS_L = 288,12,2,0 %; literal KA0902_SMM$S_CRDCTL_BS_L = 2; macro KA0902_SMM$V_CRDCTL_CFE_L = 288,14,1,0 %; macro KA0902_SMM$L_CRDCTL_H = 292,0,32,0 %; macro KA0902_SMM$V_CRDCTL_SM_H = 292,0,12,0 %; literal KA0902_SMM$S_CRDCTL_SM_H = 12; macro KA0902_SMM$V_CRDCTL_BS_H = 292,12,2,0 %; literal KA0902_SMM$S_CRDCTL_BS_H = 2; macro KA0902_SMM$V_CRDCTL_CFE_H = 292,14,1,0 %; literal KA0902_SMM$K_LENGTH = 296; ! ! DS1287A register definitions ! literal KA0902_DS1287A$S_KA0902_DS1287A = 3624; macro KA0902_DS1287A$L_PORT_INDEX = 3584,0,32,0 %; macro KA0902_DS1287A$L_PORT_DATA = 3616,0,32,0 %; ! ! IIC register definitions ! literal KA0902_IIC$M_DATA_READ_DIR = %X'1'; literal KA0902_IIC$M_STATUS_BB = %X'1'; literal KA0902_IIC$M_STATUS_LAB = %X'2'; literal KA0902_IIC$M_STATUS_AAS = %X'4'; literal KA0902_IIC$M_STATUS_ADO = %X'8'; literal KA0902_IIC$M_STATUS_BER = %X'10'; literal KA0902_IIC$M_STATUS_STS = %X'20'; literal KA0902_IIC$M_STATUS_RES = %X'40'; literal KA0902_IIC$M_STATUS_PIN = %X'80'; literal KA0902_IIC$M_IIC_STATUS_FILL2 = %X'FFFFFF00'; literal KA0902_IIC$M_CMD_ACKB = %X'1'; literal KA0902_IIC$M_CMD_STO = %X'2'; literal KA0902_IIC$M_CMD_STA = %X'4'; literal KA0902_IIC$M_CMD_ENI = %X'8'; literal KA0902_IIC$M_CMD_S3 = %X'10'; literal KA0902_IIC$M_CMD_S2 = %X'20'; literal KA0902_IIC$M_CMD_ESO = %X'40'; literal KA0902_IIC$M_CMD_PIN = %X'80'; literal KA0902_IIC$M_IIC_CMD_FILL3 = %X'FFFFFF00'; literal KA0902_IIC$K_CPU0_EEPROM_SLAVE = 168; ! Slave address of CPU0 EEPROM literal KA0902_IIC$K_CPU1_EEPROM_SLAVE = 170; ! Slave address of CPU0 EEPROM literal KA0902_IIC$K_CPU2_EEPROM_SLAVE = 174; ! Slave address of CPU0 EEPROM literal KA0902_IIC$K_CPU3_EEPROM_SLAVE = 162; ! Slave address of CPU0 EEPROM literal KA0902_IIC$K_MEM0_EEPROM_SLAVE = 160; ! Slave address of MEM0 EEPROM literal KA0902_IIC$K_MEM1_EEPROM_SLAVE = 162; ! Slave address of MEM1 EEPROM literal KA0902_IIC$K_MEM2_EEPROM_SLAVE = 164; ! Slave address of MEM2 EEPROM literal KA0902_IIC$K_MEM3_EEPROM_SLAVE = 166; ! Slave address of MEM3 EEPROM literal KA0902_IIC$K_IO_EEPROM_SLAVE = 172; ! Slave address of I/O EEPROM literal KA0902_IIC$K_EXTIO_EEPROM_SLAVE = 174; ! Slave addr. of Ext.I/O EEPROM literal KA0902_IIC$K_MASTER_SLAVE = 182; ! Slave address of master literal KA0902_IIC$K_IIC_CLOCK = 28; ! Clock speed 90khz + 12Mhz literal KA0902_IIC$K_IIC_RETRY_MAX = 10; ! Maximum number of retrys literal KA0902_IIC$S_KA0902_IIC = 42536; macro KA0902_IIC$L_IIC_DATA = 42496,0,32,0 %; macro KA0902_IIC$V_DATA_READ_DIR = 42496,0,1,0 %; ! Write the data macro KA0902_IIC$L_IIC_STATUS = 42528,0,32,0 %; macro KA0902_IIC$V_STATUS_BB = 42528,0,1,0 %; ! Bus Busy NOT macro KA0902_IIC$V_STATUS_LAB = 42528,1,1,0 %; ! Lost Arbitration macro KA0902_IIC$V_STATUS_AAS = 42528,2,1,0 %; ! Addressed as Slave macro KA0902_IIC$V_STATUS_ADO = 42528,3,1,0 %; ! Address 0/Last recieved bit macro KA0902_IIC$V_STATUS_BER = 42528,4,1,0 %; ! Bus Error macro KA0902_IIC$V_STATUS_STS = 42528,5,1,0 %; ! External Stop signal macro KA0902_IIC$V_STATUS_RES = 42528,6,1,0 %; ! Reserved must be 0 macro KA0902_IIC$V_STATUS_PIN = 42528,7,1,0 %; ! Pending Interrupt NOT macro KA0902_IIC$V_CMD_ACKB = 42528,0,1,0 %; ! Acknowledge after each byte macro KA0902_IIC$V_CMD_STO = 42528,1,1,0 %; ! Send Stop condition macro KA0902_IIC$V_CMD_STA = 42528,2,1,0 %; ! Send Start condition macro KA0902_IIC$V_CMD_ENI = 42528,3,1,0 %; ! External Interrupt Enable macro KA0902_IIC$V_CMD_S3 = 42528,4,1,0 %; ! Interrupt Vector Register macro KA0902_IIC$V_CMD_S2 = 42528,5,1,0 %; ! Clock Register macro KA0902_IIC$V_CMD_ESO = 42528,6,1,0 %; ! Enable serial output macro KA0902_IIC$V_CMD_PIN = 42528,7,1,0 %; ! Pending Interrupt Not ! ! EISA register definitions ! literal KA0902_ESC$K_RID = 8; ! Revision ID register literal KA0902_ESC$K_MS = 64; ! Mode Select register literal KA0902_ESC$K_ESCID = 2; ! EISA Config space enable literal KA0902_ESC$K_SGRBA = 87; ! Scatter Gather Base Address register literal KA0902_ESC$K_PIRQ0 = 64; ! PCI IRQ 0 register literal KA0902_ESC$K_PIRQ1 = 65; ! PCI IRQ 0 register literal KA0902_ESC$K_PIRQ2 = 66; ! PCI IRQ 0 register literal KA0902_ESC$K_PIRQ3 = 67; ! PCI IRQ 0 register literal KA0902_ESC$K_EISAID0 = 80; ! EISA ID register 0 literal KA0902_ESC$K_EISAID1 = 81; ! EISA ID register 1 literal KA0902_ESC$K_EISAID2 = 82; ! EISA ID register 2 literal KA0902_ESC$K_EISAID3 = 83; ! EISA ID register 3 literal KA0902_ESC$K_CFG_ENABLE = 15; ! Value of ESCID to enable config space literal KA0902_ESC$S_KA0902_ESC = 35984; macro KA0902_ESC$L_CFGAI = 1088,0,32,0 %; ! Configuration Address Index register macro KA0902_ESC$L_CFGDI = 1120,0,32,0 %; ! Configuration Data Index register macro KA0902_ESC$L_NMISC = 3112,0,32,0 %; ! NMI Status and Control register macro KA0902_ESC$L_NMIESC = 35880,0,32,0 %; ! NMI Extended Status and Control macro KA0902_ESC$L_LEBMG = 35976,0,32,0 %; ! Last EISA Bus Master Granted ! Define index of... !*** MODULE $KA0905DEF *** literal KA0905$K_MAX_CPU_MODULES = 4; literal KA0905$K_MAX_MEMORY_MODULES = 4; ! ! Gamma CPU register definitions ! literal KA0905_CPU$M_CREG_RN_0 = %X'F'; literal KA0905_CPU$M_CREG_FILL_01 = %X'FF0'; literal KA0905_CPU$M_CREG_EBSS_0 = %X'1000'; literal KA0905_CPU$M_CREG_FILL_02 = %X'FE000'; literal KA0905_CPU$M_CREG_EEDLY_0 = %X'100000'; literal KA0905_CPU$M_CREG_FILL_03 = %X'600000'; literal KA0905_CPU$M_CREG_EFF_0 = %X'800000'; literal KA0905_CPU$M_CREG_DIC_0 = %X'1000000'; literal KA0905_CPU$M_CREG_E4_0 = %X'2000000'; literal KA0905_CPU$M_CREG_AMB_0 = %X'4000000'; literal KA0905_CPU$M_CREG_ASD_0 = %X'8000000'; literal KA0905_CPU$M_CREG_CS_0 = %X'70000000'; literal KA0905_CPU$M_CREG_FILL_04 = %X'80000000'; literal KA0905_CPU$M_CREG_RN_1 = %X'F'; literal KA0905_CPU$M_CREG_ESI = %X'F0'; literal KA0905_CPU$M_CREG_EIOI = %X'300'; literal KA0905_CPU$M_CREG_EAIOI = %X'C00'; literal KA0905_CPU$M_CREG_EBSS_1 = %X'1000'; literal KA0905_CPU$M_CREG_FILL_05 = %X'FE000'; literal KA0905_CPU$M_CREG_EE_DLY_1 = %X'100000'; literal KA0905_CPU$M_CREG_FILL_06 = %X'600000'; literal KA0905_CPU$M_CREG_EFF_1 = %X'800000'; literal KA0905_CPU$M_CREG_DIC_1 = %X'1000000'; literal KA0905_CPU$M_CREG_E4_1 = %X'2000000'; literal KA0905_CPU$M_CREG_AMB_1 = %X'4000000'; literal KA0905_CPU$M_CREG_ASD_1 = %X'8000000'; literal KA0905_CPU$M_CREG_CS_1 = %X'70000000'; literal KA0905_CPU$M_CREG_FILL_07 = %X'80000000'; literal KA0905_CREG$K_RESERVED = 0; ! Reserved literal KA0905_CREG$K_CACHE_SIZE_1MB = 1; ! Cache size is 1Mb literal KA0905_CREG$K_CACHE_SIZE_2MB = 2; ! Cache size is 2Mb literal KA0905_CREG$K_CACHE_SIZE_4MB = 3; ! Cache size is 4Mb literal KA0905_CREG$K_CACHE_SIZE_8MB = 4; ! Cache size is 8Mb literal KA0905_CREG$K_CACHE_SIZE_16MB = 5; ! Cache size is 16Mb literal KA0905_CPU$M_ESREG_EVBCEF_0 = %X'7'; literal KA0905_CPU$M_ESREG_FILL_01 = %X'8'; literal KA0905_CPU$M_ESREG_EVB_FEF_0 = %X'F0'; literal KA0905_CPU$M_ESREG_DTS_0 = %X'400'; literal KA0905_CPU$M_ESREG_FILL_02 = %X'800'; literal KA0905_CPU$M_ESREG_IBPE_0 = %X'1000'; literal KA0905_CPU$M_ESREG_IBEI_0 = %X'6000'; literal KA0905_CPU$M_ESREG_IBS_0 = %X'8000'; literal KA0905_CPU$M_ESREG_CBEF_0 = %X'FF0000'; literal KA0905_CPU$M_ESREG_CBS_0 = %X'1000000'; literal KA0905_CPU$M_ESREG_CBC_0 = %X'2000000'; literal KA0905_CPU$M_ESREG_FILL_03 = %X'C000000'; literal KA0905_CPU$M_ESREG_EVNR_0 = %X'10000000'; literal KA0905_CPU$M_ESREG_FILL_04 = %X'E0000000'; literal KA0905_CPU$M_ESREG_EVBCEF_1 = %X'7'; literal KA0905_CPU$M_ESREG_EVBCEI_1 = %X'8'; literal KA0905_CPU$M_ESREG_EVBFEF_1 = %X'F0'; literal KA0905_CPU$M_ESREG_DTS_1 = %X'400'; literal KA0905_CPU$M_ESREG_FILL_05 = %X'800'; literal KA0905_CPU$M_ESREG_IBPE_1 = %X'1000'; literal KA0905_CPU$M_ESREG_IBEI_1 = %X'6000'; literal KA0905_CPU$M_ESREG_IBS_1 = %X'8000'; literal KA0905_CPU$M_ESREG_CBEF_1 = %X'F0000'; literal KA0905_CPU$M_ESREG_FILL_06 = %X'F00000'; literal KA0905_CPU$M_ESREG_CBS_1 = %X'1000000'; literal KA0905_CPU$M_ESREG_CBC_1 = %X'2000000'; literal KA0905_CPU$M_ESREG_FILL_07 = %X'C000000'; literal KA0905_CPU$M_ESREG_EVNR_1 = %X'10000000'; literal KA0905_CPU$M_ESREG_EVSF_1 = %X'20000000'; literal KA0905_CPU$M_ESREG_FILL_08 = %X'C0000000'; literal KA0905_CPU$M_EVBCR_EACBPC_0 = %X'1'; literal KA0905_CPU$M_EVBCR_FILL_01 = %X'E'; literal KA0905_CPU$M_EVBCR_ECEI_0 = %X'10'; literal KA0905_CPU$M_EVBCR_EEC_0 = %X'20'; literal KA0905_CPU$M_EVBCR_EREC_0 = %X'40'; literal KA0905_CPU$M_EVBCR_FILL_02 = %X'7FFFF80'; literal KA0905_CPU$M_EVBCR_FFS = %X'8000000'; literal KA0905_CPU$M_EVBCR_RSFS = %X'10000000'; literal KA0905_CPU$M_EVBCR_FILL_03 = %X'E0000000'; literal KA0905_CPU$M_EVBCR_EACBPC_1 = %X'1'; literal KA0905_CPU$M_EVBCR_FILL_04 = %X'E'; literal KA0905_CPU$M_EVBCR_ECEI_1 = %X'10'; literal KA0905_CPU$M_EVBCR_EEC_1 = %X'20'; literal KA0905_CPU$M_EVBCR_EREC_1 = %X'40'; literal KA0905_CPU$M_EVBCR_DEEC_1 = %X'80'; literal KA0905_CPU$M_EVBCR_FILL_05 = %X'FFFFFF00'; literal KA0905_CPU$M_EVBVEAR_VEA_0 = %X'3FFFFFFF'; literal KA0905_CPU$M_EVBVEAR_FILL_01 = %X'C0000000'; literal KA0905_CPU$M_EVBVEAR_VEA_1 = %X'3FFFFFFF'; literal KA0905_CPU$M_EVBVEAR_FILL_02 = %X'C0000000'; literal KA0905_CPU$M_EVBCER_CE_0 = %X'3'; literal KA0905_CPU$M_EVBCER_RD_0 = %X'4'; literal KA0905_CPU$M_EVBCER_MCE_0 = %X'8'; literal KA0905_CPU$M_EVBCER_FILL_01 = %X'F0'; literal KA0905_CPU$M_EVBCER_ES_0 = %X'FF00'; literal KA0905_CPU$M_EVBCER_ES_2 = %X'FF0000'; literal KA0905_CPU$M_EVBCER_FILL_02 = %X'FF000000'; literal KA0905_CPU$M_EVBCER_CE_1 = %X'3'; literal KA0905_CPU$M_EVBCER_RD_1 = %X'4'; literal KA0905_CPU$M_EVBCER_MCE_1 = %X'8'; literal KA0905_CPU$M_EVBCER_FILL_03 = %X'F0'; literal KA0905_CPU$M_EVBCER_ES_1 = %X'FF00'; literal KA0905_CPU$M_EVBCER_ES_3 = %X'FF0000'; literal KA0905_CPU$M_EVBCER_FILL_04 = %X'FF000000'; literal KA0905_CPU$M_EVBCEAR_CEA_0 = %X'FFFFFFFF'; literal KA0905_CPU$M_EVBCEAR_CEA_1 = %X'FFFFFFFF'; literal KA0905_CPU$M_EVBUER_UE_0 = %X'3'; literal KA0905_CPU$M_EVBUER_RD_0 = %X'4'; literal KA0905_CPU$M_EVBUER_FILL_01 = %X'8'; literal KA0905_CPU$M_EVBUER_PEACB_0 = %X'10'; literal KA0905_CPU$M_EVBUER_PEVA_0 = %X'20'; literal KA0905_CPU$M_EVBUER_FILL_02 = %X'C0'; literal KA0905_CPU$M_EVBUER_ES_0 = %X'FF00'; literal KA0905_CPU$M_EVBUER_ES_2 = %X'FF0000'; literal KA0905_CPU$M_EVBUER_FILL_03 = %X'F000000'; literal KA0905_CPU$M_EVBUER_EVBCB_0 = %X'F0000000'; literal KA0905_CPU$M_EVBUER_UE_1 = %X'3'; literal KA0905_CPU$M_EVBUER_RD_1 = %X'4'; literal KA0905_CPU$M_EVBUER_FILL_04 = %X'8'; literal KA0905_CPU$M_EVBUER_PEACB_1 = %X'10'; literal KA0905_CPU$M_EVBUER_PEVA_1 = %X'20'; literal KA0905_CPU$M_EVBUER_FILL_05 = %X'C0'; literal KA0905_CPU$M_EVBUER_ES_1 = %X'FF00'; literal KA0905_CPU$M_EVBUER_ES_3 = %X'FF0000'; literal KA0905_CPU$M_EVBUER_FILL_06 = %X'F000000'; literal KA0905_CPU$M_EVBUER_EVBCB_1 = %X'F0000000'; literal KA0905_CPU$M_EVBUEAR_UEA_0 = %X'FFFFFFFF'; literal KA0905_CPU$M_EVBUEAR_UEA_1 = %X'FFFFFFFF'; literal KA0905_CPU$M_EVBRESV_FILL_01 = %X'FFFFFFFF'; literal KA0905_CPU$M_EVBRESV_FILL_02 = %X'FFFFFFFF'; literal KA0905_CPU$M_DTCTR_DTE_0 = %X'1'; literal KA0905_CPU$M_DTCTR_FILL_01 = %X'E'; literal KA0905_CPU$M_DTCTR_ECPC_0 = %X'10'; literal KA0905_CPU$M_DTCTR_FBCP = %X'20'; literal KA0905_CPU$M_DTCTR_FILL_02 = %X'C0'; literal KA0905_CPU$M_DTCTR_ETPC_0 = %X'100'; literal KA0905_CPU$M_DTCTR_FBTP = %X'200'; literal KA0905_CPU$M_DTCTR_FILL_03 = %X'C00'; literal KA0905_CPU$M_DTCTR_DTDM_0 = %X'1000'; literal KA0905_CPU$M_DTCTR_FILL_04 = %X'FFFFE000'; literal KA0905_CPU$M_DTCTR_DTE_1 = %X'1'; literal KA0905_CPU$M_DTCTR_FILL_05 = %X'E'; literal KA0905_CPU$M_DTCTR_ECPC_1 = %X'10'; literal KA0905_CPU$M_DTCTR_FILL_06 = %X'E0'; literal KA0905_CPU$M_DTCTR_ETPC_1 = %X'100'; literal KA0905_CPU$M_DTCTR_FILL_07 = %X'E00'; literal KA0905_CPU$M_DTCTR_DTDM_1 = %X'1000'; literal KA0905_CPU$M_DTCTR_FILL_08 = %X'FFFFE000'; literal KA0905_CPU$M_DTER_FILL_01 = %X'1F'; literal KA0905_CPU$M_DTER_DTEA = %X'FFFFE0'; literal KA0905_CPU$M_DTER_FILL_02 = %X'F000000'; literal KA0905_CPU$M_DTER_TCPE_0 = %X'10000000'; literal KA0905_CPU$M_DTER_FILL_03 = %X'60000000'; literal KA0905_CPU$M_DTER_TPE_0 = %X'80000000'; literal KA0905_CPU$M_DTER_FILL_04 = %X'FFFFFFF'; literal KA0905_CPU$M_DTER_TCPE_1 = %X'10000000'; literal KA0905_CPU$M_DTER_FILL_05 = %X'60000000'; literal KA0905_CPU$M_DTER_TPE_1 = %X'80000000'; literal KA0905_CPU$M_DTTCR_TCF = %X'7'; literal KA0905_CPU$M_DTTCR_TCPF = %X'8'; literal KA0905_CPU$M_DTTCR_FILL_01 = %X'10'; literal KA0905_CPU$M_DTTCR_AF = %X'FFFE0'; literal KA0905_CPU$M_DTTCR_MTAF = %X'F00000'; literal KA0905_CPU$M_DTTCR_PTF = %X'7F000000'; literal KA0905_CPU$M_DTTCR_TPF = %X'80000000'; literal KA0905_CPU$M_DTTCR_FILL_02 = %X'FFFFFFFF'; literal KA0905_CPU$M_DTTR_TC_0 = %X'7'; literal KA0905_CPU$M_DTTR_TCP_0 = %X'8'; literal KA0905_CPU$M_DTTR_FILL_01 = %X'FFFF0'; literal KA0905_CPU$M_DTTR_TD_0 = %X'7FF00000'; literal KA0905_CPU$M_DTTR_TP_0 = %X'80000000'; literal KA0905_CPU$M_DTTR_TC_1 = %X'7'; literal KA0905_CPU$M_DTTR_TCP_1 = %X'8'; literal KA0905_CPU$M_DTTR_FILL_02 = %X'FFFF0'; literal KA0905_CPU$M_DTTR_TD_1 = %X'7FF00000'; literal KA0905_CPU$M_DTTR_TP_1 = %X'80000000'; literal KA0905_CPU$M_DTRESV_FILL_01 = %X'FFFFFFFF'; literal KA0905_CPU$M_DTRESV_FILL_02 = %X'FFFFFFFF'; literal KA0905_CPU$M_IBCSR_FILL_01 = %X'F'; literal KA0905_CPU$M_IBCSR_IBPE_0 = %X'10'; literal KA0905_CPU$M_IBCSR_SCDIPE_0 = %X'20'; literal KA0905_CPU$M_IBCSR_CCDIPE_0 = %X'40'; literal KA0905_CPU$M_IBCSR_FILL_02 = %X'F80'; literal KA0905_CPU$M_IBCSR_EIPC_0 = %X'1000'; literal KA0905_CPU$M_IBCSR_DBIP_0 = %X'2000'; literal KA0905_CPU$M_IBCSR_FILL_03 = %X'FFFFC000'; literal KA0905_CPU$M_IBCSR_FILL_04 = %X'F'; literal KA0905_CPU$M_IBCSR_IBPE_1 = %X'10'; literal KA0905_CPU$M_IBCSR_SCDIPE_1 = %X'20'; literal KA0905_CPU$M_IBCSR_CCDIPE_1 = %X'40'; literal KA0905_CPU$M_IBCSR_FILL_05 = %X'F80'; literal KA0905_CPU$M_IBCSR_EIPC_1 = %X'1000'; literal KA0905_CPU$M_IBCSR_FILL_06 = %X'FFFFE000'; literal KA0905_CPU$M_IBEAR_CBCAC_0 = %X'FFFFFFFF'; literal KA0905_CPU$M_IBEAR_CBCAC_1 = %X'FFFFFFFF'; literal KA0905_CPU$M_ACR_CBE_0 = %X'1'; literal KA0905_CPU$M_ACR_FILL_01 = %X'E'; literal KA0905_CPU$M_ACR_BME_0 = %X'10'; literal KA0905_CPU$M_ACR_DME_0 = %X'20'; literal KA0905_CPU$M_ACR_FILL_02 = %X'C0'; literal KA0905_CPU$M_ACR_PME_0 = %X'100'; literal KA0905_CPU$M_ACR_BCRE_0 = %X'200'; literal KA0905_CPU$M_ACR_FILL_03 = %X'C00'; literal KA0905_CPU$M_ACR_DCBR_0 = %X'1000'; literal KA0905_CPU$M_ACR_FILL_04 = %X'FFFFE000'; literal KA0905_CPU$M_ACR_CBE_1 = %X'1'; literal KA0905_CPU$M_ACR_FILL_05 = %X'E'; literal KA0905_CPU$M_ACR_BME_1 = %X'10'; literal KA0905_CPU$M_ACR_DME_1 = %X'20'; literal KA0905_CPU$M_ACR_FILL_06 = %X'C0'; literal KA0905_CPU$M_ACR_PME_1 = %X'100'; literal KA0905_CPU$M_ACR_BCRE_1 = %X'200'; literal KA0905_CPU$M_ACR_FILL_07 = %X'C00'; literal KA0905_CPU$M_ACR_DCBR_1 = %X'1000'; literal KA0905_CPU$M_ACR_FILL_08 = %X'FFFFE000'; literal KA0905_CPU$M_CBCR_EPC_0 = %X'1'; literal KA0905_CPU$M_CBCR_DWP_0 = %X'2'; literal KA0905_CPU$M_CBCR_CAWP_0 = %X'4'; literal KA0905_CPU$M_CBCR_FILL_01 = %X'8'; literal KA0905_CPU$M_CBCR_FS = %X'10'; literal KA0905_CPU$M_CBCR_FILL_02 = %X'FE0'; literal KA0905_CPU$M_CBCR_ECBEI_0 = %X'1000'; literal KA0905_CPU$M_CBCR_FILL_03 = %X'E000'; literal KA0905_CPU$M_CBCR_DSRC = %X'10000'; literal KA0905_CPU$M_CBCR_FILL_04 = %X'FFFE0000'; literal KA0905_CPU$M_CBCR_EPC_1 = %X'1'; literal KA0905_CPU$M_CBCR_DWP_1 = %X'2'; literal KA0905_CPU$M_CBCR_CAWP_1 = %X'4'; literal KA0905_CPU$M_CBCR_FILL_05 = %X'F8'; literal KA0905_CPU$M_CBCR_CID = %X'700'; literal KA0905_CPU$M_CBCR_FILL_06 = %X'800'; literal KA0905_CPU$M_CBCR_ECBEI_1 = %X'1000'; literal KA0905_CPU$M_CBCR_FILL_07 = %X'FFFFE000'; literal KA0905_CPU$M_CBER_URE_0 = %X'1'; literal KA0905_CPU$M_CBER_FILL_01 = %X'E'; literal KA0905_CPU$M_CBER_CALLPE_0 = %X'10'; literal KA0905_CPU$M_CBER_CAHLPE_0 = %X'20'; literal KA0905_CPU$M_CBER_FILL_02 = %X'C0'; literal KA0905_CPU$M_CBER_PELW0WD = %X'100'; literal KA0905_CPU$M_CBER_PELW1WD = %X'200'; literal KA0905_CPU$M_CBER_PELW4WD = %X'400'; literal KA0905_CPU$M_CBER_PELW5WD = %X'800'; literal KA0905_CPU$M_CBER_FILL_03 = %X'F000'; literal KA0905_CPU$M_CBER_PELW0RD = %X'10000'; literal KA0905_CPU$M_CBER_PELW1RD = %X'20000'; literal KA0905_CPU$M_CBER_PELW4RD = %X'40000'; literal KA0905_CPU$M_CBER_PELW5RD = %X'80000'; literal KA0905_CPU$M_CBER_USR = %X'100000'; literal KA0905_CPU$M_CBER_FILL_04 = %X'E00000'; literal KA0905_CPU$M_CBER_CANA = %X'1000000'; literal KA0905_CPU$M_CBER_FILL_05 = %X'E000000'; literal KA0905_CPU$M_CBER_D0NA = %X'10000000'; literal KA0905_CPU$M_CBER_D1NA = %X'20000000'; literal KA0905_CPU$M_CBER_FILL_06 = %X'C0000000'; literal KA0905_CPU$M_CBER_UCR_1 = %X'1'; literal KA0905_CPU$M_CBER_FILL_07 = %X'E'; literal KA0905_CPU$M_CBER_CALLPE_1 = %X'10'; literal KA0905_CPU$M_CBER_CAHLPE_1 = %X'20'; literal KA0905_CPU$M_CBER_FILL_08 = %X'C0'; literal KA0905_CPU$M_CBER_PELW2WD = %X'100'; literal KA0905_CPU$M_CBER_PELW3WD = %X'200'; literal KA0905_CPU$M_CBER_PELW6WD = %X'400'; literal KA0905_CPU$M_CBER_PELW7WD = %X'800'; literal KA0905_CPU$M_CBER_FILL_09 = %X'F000'; literal KA0905_CPU$M_CBER_PELW2RD = %X'10000'; literal KA0905_CPU$M_CBER_PELW3RD = %X'20000'; literal KA0905_CPU$M_CBER_PELW6RD = %X'40000'; literal KA0905_CPU$M_CBER_PELW7RD = %X'80000'; literal KA0905_CPU$M_CBER_FILL_10 = %X'FFF00000'; literal KA0905_CPU$M_CBEALR_CBLA_0 = %X'FFFFFFFF'; literal KA0905_CPU$M_CBEALR_CBLA_1 = %X'FFFFFFFF'; literal KA0905_CPU$M_CBEAHR_CBHA_0 = %X'FFFFFFFF'; literal KA0905_CPU$M_CBEAHR_CBHA_1 = %X'FFFFFFFF'; literal KA0905_CPU$M_CBRESV_FILL_01 = %X'FFFFFFFF'; literal KA0905_CPU$M_CBRESV_FILL_02 = %X'FFFFFFFF'; literal KA0905_CPU$M_ALR_LAV_0 = %X'1'; literal KA0905_CPU$M_ALR_FILL_01 = %X'1E'; literal KA0905_CPU$M_ALR_LA_0 = %X'FFFFFFE0'; literal KA0905_CPU$M_ALR_LAV_1 = %X'1'; literal KA0905_CPU$M_ALR_FILL_02 = %X'1E'; literal KA0905_CPU$M_ALR_LA_1 = %X'FFFFFFE0'; literal KA0905_CPU$M_PMBR_DATA_0 = %X'FFFFFFFF'; literal KA0905_CPU$M_PMBR_DATA_1 = %X'FFFFFFFF'; literal KA0905_CPU$M_IIRR_FILL_0 = %X'FFFFFFFF'; literal KA0905_CPU$M_IIRR_FILL_02 = %X'FFF'; literal KA0905_CPU$M_IIRR_RHI = %X'1000'; literal KA0905_CPU$M_IIRR_FILL_03 = %X'E000'; literal KA0905_CPU$M_IIRR_II = %X'10000'; literal KA0905_CPU$M_IIRR_FILL_04 = %X'FFFE0000'; literal KA0905_CPU$M_SICR_CBEIC_0 = %X'1'; literal KA0905_CPU$M_SICR_FILL_01 = %X'FFFFFFFE'; literal KA0905_CPU$M_SICR_CBEIC_1 = %X'1'; literal KA0905_CPU$M_SICR_FILL_02 = %X'E'; literal KA0905_CPU$M_SICR_ITI = %X'10'; literal KA0905_CPU$M_SICR_FILL_03 = %X'E0'; literal KA0905_CPU$M_SICR_SEC = %X'100'; literal KA0905_CPU$M_SICR_FILL_04 = %X'E00'; literal KA0905_CPU$M_SICR_NHIC = %X'1000'; literal KA0905_CPU$M_SICR_FILL_05 = %X'E000'; literal KA0905_CPU$M_SICR_IIC = %X'10000'; literal KA0905_CPU$M_SICR_FILL_06 = %X'E0000'; literal KA0905_CPU$M_SICR_IOII = %X'300000'; literal KA0905_CPU$M_SICR_FILL_07 = %X'FFC00000'; literal KA0905_CPU$M_PMCR_SS_0 = %X'1'; literal KA0905_CPU$M_PMCR_FILL_01 = %X'E'; literal KA0905_CPU$M_PMCR_AM_0 = %X'30'; literal KA0905_CPU$M_PMCR_FILL_02 = %X'FC0'; literal KA0905_CPU$M_PMCR_SPMR10 = %X'F000'; literal KA0905_CPU$M_PMCR_SPMR9 = %X'F0000'; literal KA0905_CPU$M_PMCR_SPMR8 = %X'F00000'; literal KA0905_CPU$M_PMCR_SPMR7 = %X'F000000'; literal KA0905_CPU$M_PMCR_SPMR6 = %X'F0000000'; literal KA0905_CPU$M_PMCR_SS_1 = %X'1'; literal KA0905_CPU$M_PMCR_EPMO = %X'6'; literal KA0905_CPU$M_PMCR_FILL_03 = %X'8'; literal KA0905_CPU$M_PMCR_AM_1 = %X'30'; literal KA0905_CPU$M_PMCR_CIDMASK = %X'1C0'; literal KA0905_CPU$M_PMCR_CIDMATCH = %X'E00'; literal KA0905_CPU$M_PMCR_SPMR5 = %X'F000'; literal KA0905_CPU$M_PMCR_SPMR4 = %X'F0000'; literal KA0905_CPU$M_PMCR_SPMR3 = %X'F00000'; literal KA0905_CPU$M_PMCR_SPMR2 = %X'F000000'; literal KA0905_CPU$M_PMCR_SPMR1 = %X'F0000000'; literal KA0905_CPU$M_PMR1_C6 = %X'7FFFFFFF'; literal KA0905_CPU$M_PMR1_OF6 = %X'80000000'; literal KA0905_CPU$M_PMR1_C1 = %X'7FFFFFFF'; literal KA0905_CPU$M_PMR1_OF1 = %X'80000000'; literal KA0905_CPU$M_PMR2_C7 = %X'7FFFFFFF'; literal KA0905_CPU$M_PMR2_OF7 = %X'80000000'; literal KA0905_CPU$M_PMR2_C2 = %X'7FFFFFFF'; literal KA0905_CPU$M_PMR2_OF2 = %X'80000000'; literal KA0905_CPU$M_PMR3_C8 = %X'7FFFFFFF'; literal KA0905_CPU$M_PMR3_OF8 = %X'80000000'; literal KA0905_CPU$M_PMR3_C3 = %X'7FFFFFFF'; literal KA0905_CPU$M_PMR3_OF3 = %X'80000000'; literal KA0905_CPU$M_PMR4_C9 = %X'7FFFFFFF'; literal KA0905_CPU$M_PMR4_OF9 = %X'80000000'; literal KA0905_CPU$M_PMR4_C4 = %X'7FFFFFFF'; literal KA0905_CPU$M_PMR4_OF4 = %X'80000000'; literal KA0905_CPU$M_PMR5_C10 = %X'7FFFFFFF'; literal KA0905_CPU$M_PMR5_OF10 = %X'80000000'; literal KA0905_CPU$M_PMR5_C5 = %X'7FFFFFFF'; literal KA0905_CPU$M_PMR5_OF5 = %X'80000000'; literal KA0905_CPU$S_KA0905_CPU = 1000; ! Configuration Register, CREG macro KA0905_CPU$Q_CREG = 0,0,0,1 %; literal KA0905_CPU$S_CREG = 8; macro KA0905_CPU$L_CREG_L = 0,0,32,0 %; macro KA0905_CPU$V_CREG_RN_0 = 0,0,4,0 %; literal KA0905_CPU$S_CREG_RN_0 = 4; ! Revision Number 0 macro KA0905_CPU$V_CREG_FILL_01 = 0,4,8,0 %; literal KA0905_CPU$S_CREG_FILL_01 = 8; macro KA0905_CPU$V_CREG_EBSS_0 = 0,12,1,0 %; ! Enable Bus sizing Support 0 macro KA0905_CPU$V_CREG_FILL_02 = 0,13,7,0 %; literal KA0905_CPU$S_CREG_FILL_02 = 7; macro KA0905_CPU$V_CREG_EEDLY_0 = 0,20,1,0 %; ! Enable EXCH DYL 0 macro KA0905_CPU$V_CREG_FILL_03 = 0,21,2,0 %; literal KA0905_CPU$S_CREG_FILL_03 = 2; macro KA0905_CPU$V_CREG_EFF_0 = 0,23,1,0 %; ! Enable Fast Fill 0 macro KA0905_CPU$V_CREG_DIC_0 = 0,24,1,0 %; ! Disable IDELBC-CSTALL 0 macro KA0905_CPU$V_CREG_E4_0 = 0,25,1,0 %; ! Enable 4IDLEBC 0 macro KA0905_CPU$V_CREG_AMB_0 = 0,26,1,0 %; ! Ack MB 0 macro KA0905_CPU$V_CREG_ASD_0 = 0,27,1,0 %; ! Ack Set Dirty 0 macro KA0905_CPU$V_CREG_CS_0 = 0,28,3,0 %; literal KA0905_CPU$S_CREG_CS_0 = 3; ! Cache Size 0 macro KA0905_CPU$V_CREG_FILL_04 = 0,31,1,0 %; macro KA0905_CPU$L_CREG_H = 4,0,32,0 %; macro KA0905_CPU$V_CREG_RN_1 = 4,0,4,0 %; literal KA0905_CPU$S_CREG_RN_1 = 4; ! Revision Number 1 macro KA0905_CPU$V_CREG_ESI = 4,4,4,0 %; literal KA0905_CPU$S_CREG_ESI = 4; ! Enable System Interrupts macro KA0905_CPU$V_CREG_EIOI = 4,8,2,0 %; literal KA0905_CPU$S_CREG_EIOI = 2; ! Enable I/O Interrupts macro KA0905_CPU$V_CREG_EAIOI = 4,10,2,0 %; literal KA0905_CPU$S_CREG_EAIOI = 2; ! Enable Alt I/O Interrupts macro KA0905_CPU$V_CREG_EBSS_1 = 4,12,1,0 %; ! Enable Bus sizing Support 1 macro KA0905_CPU$V_CREG_FILL_05 = 4,13,7,0 %; literal KA0905_CPU$S_CREG_FILL_05 = 7; macro KA0905_CPU$V_CREG_EE_DLY_1 = 4,20,1,0 %; ! Enable EXCH DYL 1 macro KA0905_CPU$V_CREG_FILL_06 = 4,21,2,0 %; literal KA0905_CPU$S_CREG_FILL_06 = 2; macro KA0905_CPU$V_CREG_EFF_1 = 4,23,1,0 %; ! Enable Fast Fill 1 macro KA0905_CPU$V_CREG_DIC_1 = 4,24,1,0 %; ! Disable IDELBC-STALL 1 macro KA0905_CPU$V_CREG_E4_1 = 4,25,1,0 %; ! Enable 4IDLEBC 1 macro KA0905_CPU$V_CREG_AMB_1 = 4,26,1,0 %; ! Ack MB 1 macro KA0905_CPU$V_CREG_ASD_1 = 4,27,1,0 %; ! Ack Set Dirty 1 macro KA0905_CPU$V_CREG_CS_1 = 4,28,3,0 %; literal KA0905_CPU$S_CREG_CS_1 = 3; ! Cache Size 1 macro KA0905_CPU$V_CREG_FILL_07 = 4,31,1,0 %; ! Error Summary Register, ESREG macro KA0905_CPU$Q_ESREG = 32,0,0,1 %; literal KA0905_CPU$S_ESREG = 8; macro KA0905_CPU$L_ESREG_L = 32,0,32,0 %; macro KA0905_CPU$V_ESREG_EVBCEF_0 = 32,0,3,0 %; literal KA0905_CPU$S_ESREG_EVBCEF_0 = 3; ! EVB Correctable Error Field 0 macro KA0905_CPU$V_ESREG_FILL_01 = 32,3,1,0 %; macro KA0905_CPU$V_ESREG_EVB_FEF_0 = 32,4,4,0 %; literal KA0905_CPU$S_ESREG_EVB_FEF_0 = 4; ! EVB Fatal Error Field 0 macro KA0905_CPU$V_ESREG_DTS_0 = 32,10,1,0 %; ! DT Summary 0 macro KA0905_CPU$V_ESREG_FILL_02 = 32,11,1,0 %; macro KA0905_CPU$V_ESREG_IBPE_0 = 32,12,1,0 %; ! IB Parity Error 0 macro KA0905_CPU$V_ESREG_IBEI_0 = 32,13,2,0 %; literal KA0905_CPU$S_ESREG_IBEI_0 = 2; ! IB Error Info 0 macro KA0905_CPU$V_ESREG_IBS_0 = 32,15,1,0 %; ! IB Summary 0 macro KA0905_CPU$V_ESREG_CBEF_0 = 32,16,8,0 %; literal KA0905_CPU$S_ESREG_CBEF_0 = 8; ! CB Error Field 0 macro KA0905_CPU$V_ESREG_CBS_0 = 32,24,1,0 %; ! CB Summary 0 macro KA0905_CPU$V_ESREG_CBC_0 = 32,25,1,0 %; ! CB CMDR 0 macro KA0905_CPU$V_ESREG_FILL_03 = 32,26,2,0 %; literal KA0905_CPU$S_ESREG_FILL_03 = 2; macro KA0905_CPU$V_ESREG_EVNR_0 = 32,28,1,0 %; ! EV Noresponse 0 macro KA0905_CPU$V_ESREG_FILL_04 = 32,29,3,0 %; literal KA0905_CPU$S_ESREG_FILL_04 = 3; macro KA0905_CPU$L_ESREG_H = 36,0,32,0 %; macro KA0905_CPU$V_ESREG_EVBCEF_1 = 36,0,3,0 %; literal KA0905_CPU$S_ESREG_EVBCEF_1 = 3; ! EVB Correctable Error Field 1 macro KA0905_CPU$V_ESREG_EVBCEI_1 = 36,3,1,0 %; ! EVB Correctable Error Int 1 macro KA0905_CPU$V_ESREG_EVBFEF_1 = 36,4,4,0 %; literal KA0905_CPU$S_ESREG_EVBFEF_1 = 4; ! EVB Fatal Error Field 1 macro KA0905_CPU$V_ESREG_DTS_1 = 36,10,1,0 %; ! DT Summary 1 macro KA0905_CPU$V_ESREG_FILL_05 = 36,11,1,0 %; macro KA0905_CPU$V_ESREG_IBPE_1 = 36,12,1,0 %; ! IB Parity Error 1 macro KA0905_CPU$V_ESREG_IBEI_1 = 36,13,2,0 %; literal KA0905_CPU$S_ESREG_IBEI_1 = 2; ! IB Error Info 1 macro KA0905_CPU$V_ESREG_IBS_1 = 36,15,1,0 %; ! IB Summary 1 macro KA0905_CPU$V_ESREG_CBEF_1 = 36,16,4,0 %; literal KA0905_CPU$S_ESREG_CBEF_1 = 4; ! CB Error Field 1 macro KA0905_CPU$V_ESREG_FILL_06 = 36,20,4,0 %; literal KA0905_CPU$S_ESREG_FILL_06 = 4; macro KA0905_CPU$V_ESREG_CBS_1 = 36,24,1,0 %; ! CB Summary 1 macro KA0905_CPU$V_ESREG_CBC_1 = 36,25,1,0 %; ! CB CMDR 1 macro KA0905_CPU$V_ESREG_FILL_07 = 36,26,2,0 %; literal KA0905_CPU$S_ESREG_FILL_07 = 2; macro KA0905_CPU$V_ESREG_EVNR_1 = 36,28,1,0 %; ! EV Noresponse 1 macro KA0905_CPU$V_ESREG_EVSF_1 = 36,29,1,0 %; ! EX Sysfail 1 macro KA0905_CPU$V_ESREG_FILL_08 = 36,30,2,0 %; literal KA0905_CPU$S_ESREG_FILL_08 = 2; ! EVBCR Control Register, EVBCR macro KA0905_CPU$Q_EVBCR = 64,0,0,1 %; literal KA0905_CPU$S_EVBCR = 8; macro KA0905_CPU$L_EVBCR_L = 64,0,32,0 %; macro KA0905_CPU$V_EVBCR_EACBPC_0 = 64,0,1,0 %; ! Enable Addr-CMD Bus Parity 0 macro KA0905_CPU$V_EVBCR_FILL_01 = 64,1,3,0 %; literal KA0905_CPU$S_EVBCR_FILL_01 = 3; macro KA0905_CPU$V_EVBCR_ECEI_0 = 64,4,1,0 %; ! Enable Corr Error Int 0 macro KA0905_CPU$V_EVBCR_EEC_0 = 64,5,1,0 %; ! Enable ECC Correction 0 macro KA0905_CPU$V_EVBCR_EREC_0 = 64,6,1,0 %; ! Enable Rattler ECC Checking 0 macro KA0905_CPU$V_EVBCR_FILL_02 = 64,7,20,0 %; literal KA0905_CPU$S_EVBCR_FILL_02 = 20; macro KA0905_CPU$V_EVBCR_FFS = 64,27,1,0 %; ! Force Filled Shared macro KA0905_CPU$V_EVBCR_RSFS = 64,28,1,0 %; ! RMM STXC Filled Shared macro KA0905_CPU$V_EVBCR_FILL_03 = 64,29,3,0 %; literal KA0905_CPU$S_EVBCR_FILL_03 = 3; macro KA0905_CPU$L_EVBCR_H = 68,0,32,0 %; macro KA0905_CPU$V_EVBCR_EACBPC_1 = 68,0,1,0 %; ! Enable Addr-CMD Bus Parity 1 macro KA0905_CPU$V_EVBCR_FILL_04 = 68,1,3,0 %; literal KA0905_CPU$S_EVBCR_FILL_04 = 3; macro KA0905_CPU$V_EVBCR_ECEI_1 = 68,4,1,0 %; ! Enable Corr Error Int 1 macro KA0905_CPU$V_EVBCR_EEC_1 = 68,5,1,0 %; ! Enable ECC Correction 1 macro KA0905_CPU$V_EVBCR_EREC_1 = 68,6,1,0 %; ! Enable Rattler ECC Checking 1 macro KA0905_CPU$V_EVBCR_DEEC_1 = 68,7,1,0 %; ! Disable EV5 ECC Checking 1 macro KA0905_CPU$V_EVBCR_FILL_05 = 68,8,24,0 %; literal KA0905_CPU$S_EVBCR_FILL_05 = 24; ! EVB Victim Error Address Register, EVBVEAR macro KA0905_CPU$Q_EVBVEAR = 96,0,0,1 %; literal KA0905_CPU$S_EVBVEAR = 8; macro KA0905_CPU$L_EVBVEAR_L = 96,0,32,0 %; macro KA0905_CPU$V_EVBVEAR_VEA_0 = 96,0,30,0 %; literal KA0905_CPU$S_EVBVEAR_VEA_0 = 30; ! Victim Err Address 0 macro KA0905_CPU$V_EVBVEAR_FILL_01 = 96,30,2,0 %; literal KA0905_CPU$S_EVBVEAR_FILL_01 = 2; macro KA0905_CPU$L_EVBVEAR_H = 100,0,32,0 %; macro KA0905_CPU$V_EVBVEAR_VEA_1 = 100,0,30,0 %; literal KA0905_CPU$S_EVBVEAR_VEA_1 = 30; ! Victim Err Address 1 macro KA0905_CPU$V_EVBVEAR_FILL_02 = 100,30,2,0 %; literal KA0905_CPU$S_EVBVEAR_FILL_02 = 2; ! EVB Correctable Error Register, EVBCER macro KA0905_CPU$Q_EVBCER = 128,0,0,1 %; literal KA0905_CPU$S_EVBCER = 8; macro KA0905_CPU$L_EVBCER_L = 128,0,32,0 %; macro KA0905_CPU$V_EVBCER_CE_0 = 128,0,2,0 %; literal KA0905_CPU$S_EVBCER_CE_0 = 2; ! Correctable Error 0 macro KA0905_CPU$V_EVBCER_RD_0 = 128,2,1,0 %; ! Read Dirty 0 macro KA0905_CPU$V_EVBCER_MCE_0 = 128,3,1,0 %; ! Missed correctable Error 0 macro KA0905_CPU$V_EVBCER_FILL_01 = 128,4,4,0 %; literal KA0905_CPU$S_EVBCER_FILL_01 = 4; macro KA0905_CPU$V_EVBCER_ES_0 = 128,8,8,0 %; literal KA0905_CPU$S_EVBCER_ES_0 = 8; ! ECC Syndrome 0 macro KA0905_CPU$V_EVBCER_ES_2 = 128,16,8,0 %; literal KA0905_CPU$S_EVBCER_ES_2 = 8; ! ECC Syndrome 2 macro KA0905_CPU$V_EVBCER_FILL_02 = 128,24,8,0 %; literal KA0905_CPU$S_EVBCER_FILL_02 = 8; macro KA0905_CPU$L_EVBCER_H = 132,0,32,0 %; macro KA0905_CPU$V_EVBCER_CE_1 = 132,0,2,0 %; literal KA0905_CPU$S_EVBCER_CE_1 = 2; ! Correctable Error 1 macro KA0905_CPU$V_EVBCER_RD_1 = 132,2,1,0 %; ! Read Dirty 1 macro KA0905_CPU$V_EVBCER_MCE_1 = 132,3,1,0 %; ! Missed correctable Error 1 macro KA0905_CPU$V_EVBCER_FILL_03 = 132,4,4,0 %; literal KA0905_CPU$S_EVBCER_FILL_03 = 4; macro KA0905_CPU$V_EVBCER_ES_1 = 132,8,8,0 %; literal KA0905_CPU$S_EVBCER_ES_1 = 8; ! ECC Syndrome 1 macro KA0905_CPU$V_EVBCER_ES_3 = 132,16,8,0 %; literal KA0905_CPU$S_EVBCER_ES_3 = 8; ! ECC Syndrome 3 macro KA0905_CPU$V_EVBCER_FILL_04 = 132,24,8,0 %; literal KA0905_CPU$S_EVBCER_FILL_04 = 8; ! EVB Correctable Error Address Register, EVBCEAR macro KA0905_CPU$Q_EVBCEAR = 160,0,0,1 %; literal KA0905_CPU$S_EVBCEAR = 8; macro KA0905_CPU$L_EVBCEAR_L = 160,0,32,0 %; macro KA0905_CPU$V_EVBCEAR_CEA_0 = 160,0,32,0 %; literal KA0905_CPU$S_EVBCEAR_CEA_0 = 32; ! Corr Err Addr 0 macro KA0905_CPU$L_EVBCEAR_H = 164,0,32,0 %; macro KA0905_CPU$V_EVBCEAR_CEA_1 = 164,0,32,0 %; literal KA0905_CPU$S_EVBCEAR_CEA_1 = 32; ! Corr Err Addr 1 ! EVB Uncorrectable Error Register, EVBUER macro KA0905_CPU$Q_EVBUER = 192,0,0,1 %; literal KA0905_CPU$S_EVBUER = 8; macro KA0905_CPU$L_EVBUER_L = 192,0,32,0 %; macro KA0905_CPU$V_EVBUER_UE_0 = 192,0,2,0 %; literal KA0905_CPU$S_EVBUER_UE_0 = 2; ! Uncorrectable Error 0 macro KA0905_CPU$V_EVBUER_RD_0 = 192,2,1,0 %; ! Read Dirty 0 macro KA0905_CPU$V_EVBUER_FILL_01 = 192,3,1,0 %; macro KA0905_CPU$V_EVBUER_PEACB_0 = 192,4,1,0 %; ! Parity Err on Addr-CMD Bus 0 macro KA0905_CPU$V_EVBUER_PEVA_0 = 192,5,1,0 %; ! Parity Err on Victim Addr 0 macro KA0905_CPU$V_EVBUER_FILL_02 = 192,6,2,0 %; literal KA0905_CPU$S_EVBUER_FILL_02 = 2; macro KA0905_CPU$V_EVBUER_ES_0 = 192,8,8,0 %; literal KA0905_CPU$S_EVBUER_ES_0 = 8; ! ECC Syndrome 0 macro KA0905_CPU$V_EVBUER_ES_2 = 192,16,8,0 %; literal KA0905_CPU$S_EVBUER_ES_2 = 8; ! ECC Syndrome 2 macro KA0905_CPU$V_EVBUER_FILL_03 = 192,24,4,0 %; literal KA0905_CPU$S_EVBUER_FILL_03 = 4; macro KA0905_CPU$V_EVBUER_EVBCB_0 = 192,28,4,0 %; literal KA0905_CPU$S_EVBUER_EVBCB_0 = 4; ! EVB CMD-Bus 0 macro KA0905_CPU$L_EVBUER_H = 196,0,32,0 %; macro KA0905_CPU$V_EVBUER_UE_1 = 196,0,2,0 %; literal KA0905_CPU$S_EVBUER_UE_1 = 2; ! Uncorrectable Error 1 macro KA0905_CPU$V_EVBUER_RD_1 = 196,2,1,0 %; ! Read Dirty 1 macro KA0905_CPU$V_EVBUER_FILL_04 = 196,3,1,0 %; macro KA0905_CPU$V_EVBUER_PEACB_1 = 196,4,1,0 %; ! Parity Err on Addr-CMD Bus 1 macro KA0905_CPU$V_EVBUER_PEVA_1 = 196,5,1,0 %; ! Parity Err on Victim Addr 1 macro KA0905_CPU$V_EVBUER_FILL_05 = 196,6,2,0 %; literal KA0905_CPU$S_EVBUER_FILL_05 = 2; macro KA0905_CPU$V_EVBUER_ES_1 = 196,8,8,0 %; literal KA0905_CPU$S_EVBUER_ES_1 = 8; ! ECC Syndrome 1 macro KA0905_CPU$V_EVBUER_ES_3 = 196,16,8,0 %; literal KA0905_CPU$S_EVBUER_ES_3 = 8; ! ECC Syndrome 3 macro KA0905_CPU$V_EVBUER_FILL_06 = 196,24,4,0 %; literal KA0905_CPU$S_EVBUER_FILL_06 = 4; macro KA0905_CPU$V_EVBUER_EVBCB_1 = 196,28,4,0 %; literal KA0905_CPU$S_EVBUER_EVBCB_1 = 4; ! EVB CMD-Bus 1 ! EVB Uncorrectable Error Address Register, EVBUEAR macro KA0905_CPU$Q_EVBUEAR = 224,0,0,1 %; literal KA0905_CPU$S_EVBUEAR = 8; macro KA0905_CPU$L_EVBUEAR_L = 224,0,32,0 %; macro KA0905_CPU$V_EVBUEAR_UEA_0 = 224,0,32,0 %; literal KA0905_CPU$S_EVBUEAR_UEA_0 = 32; ! Uncorr Err Address 0 macro KA0905_CPU$L_EVBUEAR_H = 228,0,32,0 %; macro KA0905_CPU$V_EVBUEAR_UEA_1 = 228,0,32,0 %; literal KA0905_CPU$S_EVBUEAR_UEA_1 = 32; ! Uncorr Err Address 1 ! EVB Reserver Register, EVBRESV macro KA0905_CPU$Q_EVBRESV = 256,0,0,1 %; literal KA0905_CPU$S_EVBRESV = 8; macro KA0905_CPU$L_EVBRESV_L = 256,0,32,0 %; macro KA0905_CPU$V_EVBRESV_FILL_01 = 256,0,32,0 %; literal KA0905_CPU$S_EVBRESV_FILL_01 = 32; macro KA0905_CPU$L_EVBRESV_H = 260,0,32,0 %; macro KA0905_CPU$V_EVBRESV_FILL_02 = 260,0,32,0 %; literal KA0905_CPU$S_EVBRESV_FILL_02 = 32; ! Duplicate tag Control Register, DTCTR macro KA0905_CPU$Q_DTCTR = 288,0,0,1 %; literal KA0905_CPU$S_DTCTR = 8; macro KA0905_CPU$L_DTCTR_L = 288,0,32,0 %; macro KA0905_CPU$V_DTCTR_DTE_0 = 288,0,1,0 %; ! Duplicate Tag Enable 0 macro KA0905_CPU$V_DTCTR_FILL_01 = 288,1,3,0 %; literal KA0905_CPU$S_DTCTR_FILL_01 = 3; macro KA0905_CPU$V_DTCTR_ECPC_0 = 288,4,1,0 %; ! Ena ctrl Parity Checking 0 macro KA0905_CPU$V_DTCTR_FBCP = 288,5,1,0 %; ! Fill Bad Control Parity macro KA0905_CPU$V_DTCTR_FILL_02 = 288,6,2,0 %; literal KA0905_CPU$S_DTCTR_FILL_02 = 2; macro KA0905_CPU$V_DTCTR_ETPC_0 = 288,8,1,0 %; ! Enable Tag Parity Checking 0 macro KA0905_CPU$V_DTCTR_FBTP = 288,9,1,0 %; ! Fill Bad Tag Parity macro KA0905_CPU$V_DTCTR_FILL_03 = 288,10,2,0 %; literal KA0905_CPU$S_DTCTR_FILL_03 = 2; macro KA0905_CPU$V_DTCTR_DTDM_0 = 288,12,1,0 %; ! Duplicate Tag Diag Mode 0 macro KA0905_CPU$V_DTCTR_FILL_04 = 288,13,19,0 %; literal KA0905_CPU$S_DTCTR_FILL_04 = 19; macro KA0905_CPU$L_DTCTR_H = 292,0,32,0 %; macro KA0905_CPU$V_DTCTR_DTE_1 = 292,0,1,0 %; ! Duplicate Tag Enable 1 macro KA0905_CPU$V_DTCTR_FILL_05 = 292,1,3,0 %; literal KA0905_CPU$S_DTCTR_FILL_05 = 3; macro KA0905_CPU$V_DTCTR_ECPC_1 = 292,4,1,0 %; ! Ena ctrl Parity Checking 1 macro KA0905_CPU$V_DTCTR_FILL_06 = 292,5,3,0 %; literal KA0905_CPU$S_DTCTR_FILL_06 = 3; macro KA0905_CPU$V_DTCTR_ETPC_1 = 292,8,1,0 %; ! Enable Tag Parity Checking 1 macro KA0905_CPU$V_DTCTR_FILL_07 = 292,9,3,0 %; literal KA0905_CPU$S_DTCTR_FILL_07 = 3; macro KA0905_CPU$V_DTCTR_DTDM_1 = 292,12,1,0 %; ! Duplicate Tag Diag Mode 1 macro KA0905_CPU$V_DTCTR_FILL_08 = 292,13,19,0 %; literal KA0905_CPU$S_DTCTR_FILL_08 = 19; ! Duplicate Tag Error Register, DTER macro KA0905_CPU$Q_DTER = 320,0,0,1 %; literal KA0905_CPU$S_DTER = 8; macro KA0905_CPU$L_DTER_L = 320,0,32,0 %; macro KA0905_CPU$V_DTER_FILL_01 = 320,0,5,0 %; literal KA0905_CPU$S_DTER_FILL_01 = 5; macro KA0905_CPU$V_DTER_DTEA = 320,5,19,0 %; literal KA0905_CPU$S_DTER_DTEA = 19; ! DTER Error Address macro KA0905_CPU$V_DTER_FILL_02 = 320,24,4,0 %; literal KA0905_CPU$S_DTER_FILL_02 = 4; macro KA0905_CPU$V_DTER_TCPE_0 = 320,28,1,0 %; ! Tag Con Par Error 0 macro KA0905_CPU$V_DTER_FILL_03 = 320,29,2,0 %; literal KA0905_CPU$S_DTER_FILL_03 = 2; macro KA0905_CPU$V_DTER_TPE_0 = 320,31,1,0 %; ! Tag Parity Error 0 macro KA0905_CPU$L_DTER_H = 324,0,32,0 %; macro KA0905_CPU$V_DTER_FILL_04 = 324,0,28,0 %; literal KA0905_CPU$S_DTER_FILL_04 = 28; macro KA0905_CPU$V_DTER_TCPE_1 = 324,28,1,0 %; ! Tag Con Par Error 1 macro KA0905_CPU$V_DTER_FILL_05 = 324,29,2,0 %; literal KA0905_CPU$S_DTER_FILL_05 = 2; macro KA0905_CPU$V_DTER_TPE_1 = 324,31,1,0 %; ! Tag Parity Error 1 ! Duplicate_Tag Test Control Register, DTTCR macro KA0905_CPU$Q_DTTCR = 352,0,0,1 %; literal KA0905_CPU$S_DTTCR = 8; macro KA0905_CPU$L_DTTCR_L = 352,0,32,0 %; macro KA0905_CPU$V_DTTCR_TCF = 352,0,3,0 %; literal KA0905_CPU$S_DTTCR_TCF = 3; ! Tag Control Field macro KA0905_CPU$V_DTTCR_TCPF = 352,3,1,0 %; ! Tag Control Parity Field macro KA0905_CPU$V_DTTCR_FILL_01 = 352,4,1,0 %; macro KA0905_CPU$V_DTTCR_AF = 352,5,15,0 %; literal KA0905_CPU$S_DTTCR_AF = 15; ! Address Field macro KA0905_CPU$V_DTTCR_MTAF = 352,20,4,0 %; literal KA0905_CPU$S_DTTCR_MTAF = 4; ! Mux Tag Address Field macro KA0905_CPU$V_DTTCR_PTF = 352,24,7,0 %; literal KA0905_CPU$S_DTTCR_PTF = 7; ! Partial Tag Field macro KA0905_CPU$V_DTTCR_TPF = 352,31,1,0 %; ! Tag Parity field macro KA0905_CPU$L_DTTCR_H = 356,0,32,0 %; macro KA0905_CPU$V_DTTCR_FILL_02 = 356,0,32,0 %; literal KA0905_CPU$S_DTTCR_FILL_02 = 32; ! Duplicate Tag Test Register, DTTR macro KA0905_CPU$Q_DTTR = 384,0,0,1 %; literal KA0905_CPU$S_DTTR = 8; macro KA0905_CPU$L_DTTR_L = 384,0,32,0 %; macro KA0905_CPU$V_DTTR_TC_0 = 384,0,3,0 %; literal KA0905_CPU$S_DTTR_TC_0 = 3; ! Tag Control 0 macro KA0905_CPU$V_DTTR_TCP_0 = 384,3,1,0 %; ! Tag Control Parity 0 macro KA0905_CPU$V_DTTR_FILL_01 = 384,4,16,0 %; literal KA0905_CPU$S_DTTR_FILL_01 = 16; macro KA0905_CPU$V_DTTR_TD_0 = 384,20,11,0 %; literal KA0905_CPU$S_DTTR_TD_0 = 11; ! Tag Data 0 macro KA0905_CPU$V_DTTR_TP_0 = 384,31,1,0 %; ! Tag Parity 0 macro KA0905_CPU$L_DTTR_H = 388,0,32,0 %; macro KA0905_CPU$V_DTTR_TC_1 = 388,0,3,0 %; literal KA0905_CPU$S_DTTR_TC_1 = 3; ! Tag Control 1 macro KA0905_CPU$V_DTTR_TCP_1 = 388,3,1,0 %; ! Tag Control Parity 1 macro KA0905_CPU$V_DTTR_FILL_02 = 388,4,16,0 %; literal KA0905_CPU$S_DTTR_FILL_02 = 16; macro KA0905_CPU$V_DTTR_TD_1 = 388,20,11,0 %; literal KA0905_CPU$S_DTTR_TD_1 = 11; ! Tag Data 1 macro KA0905_CPU$V_DTTR_TP_1 = 388,31,1,0 %; ! Tag Parity 1 ! Duplicate Tag Reserve Register, DTRESV macro KA0905_CPU$Q_DTRESV = 416,0,0,1 %; literal KA0905_CPU$S_DTRESV = 8; macro KA0905_CPU$L_DTRESV_L = 416,0,32,0 %; macro KA0905_CPU$V_DTRESV_FILL_01 = 416,0,32,0 %; literal KA0905_CPU$S_DTRESV_FILL_01 = 32; macro KA0905_CPU$L_DTRESV_H = 420,0,32,0 %; macro KA0905_CPU$V_DTRESV_FILL_02 = 420,0,32,0 %; literal KA0905_CPU$S_DTRESV_FILL_02 = 32; ! I-Bus Control and Status Register, IBCSR macro KA0905_CPU$Q_IBCSR = 448,0,0,1 %; literal KA0905_CPU$S_IBCSR = 8; macro KA0905_CPU$L_IBCSR_L = 448,0,32,0 %; macro KA0905_CPU$V_IBCSR_FILL_01 = 448,0,4,0 %; literal KA0905_CPU$S_IBCSR_FILL_01 = 4; macro KA0905_CPU$V_IBCSR_IBPE_0 = 448,4,1,0 %; ! I-bus Parity Error 0 macro KA0905_CPU$V_IBCSR_SCDIPE_0 = 448,5,1,0 %; ! Snoop Cyc During I-bus Par Error 0 macro KA0905_CPU$V_IBCSR_CCDIPE_0 = 448,6,1,0 %; ! CMDR Cyc During I-bus Par Error 0 macro KA0905_CPU$V_IBCSR_FILL_02 = 448,7,5,0 %; literal KA0905_CPU$S_IBCSR_FILL_02 = 5; macro KA0905_CPU$V_IBCSR_EIPC_0 = 448,12,1,0 %; ! Enable I-bus Par Checking 0 macro KA0905_CPU$V_IBCSR_DBIP_0 = 448,13,1,0 %; ! Drive Bad I-bus Parity 0 macro KA0905_CPU$V_IBCSR_FILL_03 = 448,14,18,0 %; literal KA0905_CPU$S_IBCSR_FILL_03 = 18; macro KA0905_CPU$L_IBCSR_H = 452,0,32,0 %; macro KA0905_CPU$V_IBCSR_FILL_04 = 452,0,4,0 %; literal KA0905_CPU$S_IBCSR_FILL_04 = 4; macro KA0905_CPU$V_IBCSR_IBPE_1 = 452,4,1,0 %; ! I-bus Parity Error 1 macro KA0905_CPU$V_IBCSR_SCDIPE_1 = 452,5,1,0 %; ! Snoop Cyc During I-bus Par Error 1 macro KA0905_CPU$V_IBCSR_CCDIPE_1 = 452,6,1,0 %; ! CMDR Cyc During I-bus Par Error 1 macro KA0905_CPU$V_IBCSR_FILL_05 = 452,7,5,0 %; literal KA0905_CPU$S_IBCSR_FILL_05 = 5; macro KA0905_CPU$V_IBCSR_EIPC_1 = 452,12,1,0 %; ! Enable I-bus Par Checking 1 macro KA0905_CPU$V_IBCSR_FILL_06 = 452,13,19,0 %; literal KA0905_CPU$S_IBCSR_FILL_06 = 19; ! I-Bus Error Address Register, IBEAR macro KA0905_CPU$Q_IBEAR = 480,0,0,1 %; literal KA0905_CPU$S_IBEAR = 8; macro KA0905_CPU$L_IBEAR_L = 480,0,32,0 %; macro KA0905_CPU$V_IBEAR_CBCAC_0 = 480,0,32,0 %; literal KA0905_CPU$S_IBEAR_CBCAC_0 = 32; ! C-bus2 CA cycle 0 macro KA0905_CPU$L_IBEAR_H = 484,0,32,0 %; macro KA0905_CPU$V_IBEAR_CBCAC_1 = 484,0,32,0 %; literal KA0905_CPU$S_IBEAR_CBCAC_1 = 32; ! C-bus2 CA cycle 1 ! Arbitrarion Control Register, ACR macro KA0905_CPU$Q_ACR = 512,0,0,1 %; literal KA0905_CPU$S_ACR = 8; macro KA0905_CPU$L_ACR_L = 512,0,32,0 %; macro KA0905_CPU$V_ACR_CBE_0 = 512,0,1,0 %; ! CBUS2 Equalizer 0 macro KA0905_CPU$V_ACR_FILL_01 = 512,1,3,0 %; literal KA0905_CPU$S_ACR_FILL_01 = 3; macro KA0905_CPU$V_ACR_BME_0 = 512,4,1,0 %; ! Bad Mode Enable 0 macro KA0905_CPU$V_ACR_DME_0 = 512,5,1,0 %; ! Donate Mode Enable 0 macro KA0905_CPU$V_ACR_FILL_02 = 512,6,2,0 %; literal KA0905_CPU$S_ACR_FILL_02 = 2; macro KA0905_CPU$V_ACR_PME_0 = 512,8,1,0 %; ! Pawn Mode Enable 0 macro KA0905_CPU$V_ACR_BCRE_0 = 512,9,1,0 %; ! BCREQ Enable 0 macro KA0905_CPU$V_ACR_FILL_03 = 512,10,2,0 %; literal KA0905_CPU$S_ACR_FILL_03 = 2; macro KA0905_CPU$V_ACR_DCBR_0 = 512,12,1,0 %; ! Disable CBUS2 Request 0 macro KA0905_CPU$V_ACR_FILL_04 = 512,13,19,0 %; literal KA0905_CPU$S_ACR_FILL_04 = 19; macro KA0905_CPU$L_ACR_H = 516,0,32,0 %; macro KA0905_CPU$V_ACR_CBE_1 = 516,0,1,0 %; ! CBUS2 Equalizer 1 macro KA0905_CPU$V_ACR_FILL_05 = 516,1,3,0 %; literal KA0905_CPU$S_ACR_FILL_05 = 3; macro KA0905_CPU$V_ACR_BME_1 = 516,4,1,0 %; ! Bad Mode Enable 1 macro KA0905_CPU$V_ACR_DME_1 = 516,5,1,0 %; ! Donate Mode Enable 1 macro KA0905_CPU$V_ACR_FILL_06 = 516,6,2,0 %; literal KA0905_CPU$S_ACR_FILL_06 = 2; macro KA0905_CPU$V_ACR_PME_1 = 516,8,1,0 %; ! Pawn Mode Enable 1 macro KA0905_CPU$V_ACR_BCRE_1 = 516,9,1,0 %; ! BCREQ Enable 1 macro KA0905_CPU$V_ACR_FILL_07 = 516,10,2,0 %; literal KA0905_CPU$S_ACR_FILL_07 = 2; macro KA0905_CPU$V_ACR_DCBR_1 = 516,12,1,0 %; ! Disable CBUS2 Request 1 macro KA0905_CPU$V_ACR_FILL_08 = 516,13,19,0 %; literal KA0905_CPU$S_ACR_FILL_08 = 19; ! Cobra-bus2 Control Register, CBCR macro KA0905_CPU$Q_CBCR = 544,0,0,1 %; literal KA0905_CPU$S_CBCR = 8; macro KA0905_CPU$L_CBCR_L = 544,0,32,0 %; macro KA0905_CPU$V_CBCR_EPC_0 = 544,0,1,0 %; ! Enable Parity Checking 0 macro KA0905_CPU$V_CBCR_DWP_0 = 544,1,1,0 %; ! Data Wrong Parity 0 macro KA0905_CPU$V_CBCR_CAWP_0 = 544,2,1,0 %; ! C/A Wrong Parity 0 macro KA0905_CPU$V_CBCR_FILL_01 = 544,3,1,0 %; macro KA0905_CPU$V_CBCR_FS = 544,4,1,0 %; ! Force Shared macro KA0905_CPU$V_CBCR_FILL_02 = 544,5,7,0 %; literal KA0905_CPU$S_CBCR_FILL_02 = 7; macro KA0905_CPU$V_CBCR_ECBEI_0 = 544,12,1,0 %; ! Enable CBUS Err Interrupt 0 macro KA0905_CPU$V_CBCR_FILL_03 = 544,13,3,0 %; literal KA0905_CPU$S_CBCR_FILL_03 = 3; macro KA0905_CPU$V_CBCR_DSRC = 544,16,1,0 %; ! Dis Shared Response checking macro KA0905_CPU$V_CBCR_FILL_04 = 544,17,15,0 %; literal KA0905_CPU$S_CBCR_FILL_04 = 15; macro KA0905_CPU$L_CBCR_H = 548,0,32,0 %; macro KA0905_CPU$V_CBCR_EPC_1 = 548,0,1,0 %; ! Enable Parity Checking 1 macro KA0905_CPU$V_CBCR_DWP_1 = 548,1,1,0 %; ! Date Wrong Parity 1 macro KA0905_CPU$V_CBCR_CAWP_1 = 548,2,1,0 %; ! C/A Wrong Parity 1 macro KA0905_CPU$V_CBCR_FILL_05 = 548,3,5,0 %; literal KA0905_CPU$S_CBCR_FILL_05 = 5; macro KA0905_CPU$V_CBCR_CID = 548,8,3,0 %; literal KA0905_CPU$S_CBCR_CID = 3; ! Commander ID macro KA0905_CPU$V_CBCR_FILL_06 = 548,11,1,0 %; macro KA0905_CPU$V_CBCR_ECBEI_1 = 548,12,1,0 %; ! Enable CBUS Err Interrupt 0 macro KA0905_CPU$V_CBCR_FILL_07 = 548,13,19,0 %; literal KA0905_CPU$S_CBCR_FILL_07 = 19; ! Cobra-bus2 Error Register, CBER macro KA0905_CPU$Q_CBER = 576,0,0,1 %; literal KA0905_CPU$S_CBER = 8; macro KA0905_CPU$L_CBER_L = 576,0,32,0 %; macro KA0905_CPU$V_CBER_URE_0 = 576,0,1,0 %; ! Uncorrectable Read Error 0 macro KA0905_CPU$V_CBER_FILL_01 = 576,1,3,0 %; literal KA0905_CPU$S_CBER_FILL_01 = 3; macro KA0905_CPU$V_CBER_CALLPE_0 = 576,4,1,0 %; ! C/A Low LW Parity Err 0 macro KA0905_CPU$V_CBER_CAHLPE_0 = 576,5,1,0 %; ! C/A Hign LW Parity Err 0 macro KA0905_CPU$V_CBER_FILL_02 = 576,6,2,0 %; literal KA0905_CPU$S_CBER_FILL_02 = 2; macro KA0905_CPU$V_CBER_PELW0WD = 576,8,1,0 %; ! Parity Err LW0 Write Data macro KA0905_CPU$V_CBER_PELW1WD = 576,9,1,0 %; ! Parity Err LW1 Write Data macro KA0905_CPU$V_CBER_PELW4WD = 576,10,1,0 %; ! Parity Err LW4 Write Data macro KA0905_CPU$V_CBER_PELW5WD = 576,11,1,0 %; ! Parity Err LW5 Write Data macro KA0905_CPU$V_CBER_FILL_03 = 576,12,4,0 %; literal KA0905_CPU$S_CBER_FILL_03 = 4; macro KA0905_CPU$V_CBER_PELW0RD = 576,16,1,0 %; ! Parity Err LW0 Read Data macro KA0905_CPU$V_CBER_PELW1RD = 576,17,1,0 %; ! Parity Err LW1 Read Data macro KA0905_CPU$V_CBER_PELW4RD = 576,18,1,0 %; ! Parity Err LW4 Read Data macro KA0905_CPU$V_CBER_PELW5RD = 576,19,1,0 %; ! Parity Err LW5 Read Data macro KA0905_CPU$V_CBER_USR = 576,20,1,0 %; ! Unexpected Shared Response macro KA0905_CPU$V_CBER_FILL_04 = 576,21,3,0 %; literal KA0905_CPU$S_CBER_FILL_04 = 3; macro KA0905_CPU$V_CBER_CANA = 576,24,1,0 %; ! C/A Not Acked macro KA0905_CPU$V_CBER_FILL_05 = 576,25,3,0 %; literal KA0905_CPU$S_CBER_FILL_05 = 3; macro KA0905_CPU$V_CBER_D0NA = 576,28,1,0 %; ! Data 0 Not Acked macro KA0905_CPU$V_CBER_D1NA = 576,29,1,0 %; ! Data 1 Not Acked macro KA0905_CPU$V_CBER_FILL_06 = 576,30,2,0 %; literal KA0905_CPU$S_CBER_FILL_06 = 2; macro KA0905_CPU$L_CBER_H = 580,0,32,0 %; macro KA0905_CPU$V_CBER_UCR_1 = 580,0,1,0 %; ! Uncorrectable Read Error 1 macro KA0905_CPU$V_CBER_FILL_07 = 580,1,3,0 %; literal KA0905_CPU$S_CBER_FILL_07 = 3; macro KA0905_CPU$V_CBER_CALLPE_1 = 580,4,1,0 %; ! C/A Low LW Parity Err 1 macro KA0905_CPU$V_CBER_CAHLPE_1 = 580,5,1,0 %; ! C/A High LW Parity Err 1 macro KA0905_CPU$V_CBER_FILL_08 = 580,6,2,0 %; literal KA0905_CPU$S_CBER_FILL_08 = 2; macro KA0905_CPU$V_CBER_PELW2WD = 580,8,1,0 %; ! Parity Err LW2 Write Data macro KA0905_CPU$V_CBER_PELW3WD = 580,9,1,0 %; ! Parity Err LW3 Write Data macro KA0905_CPU$V_CBER_PELW6WD = 580,10,1,0 %; ! Parity Err LW6 Write Data macro KA0905_CPU$V_CBER_PELW7WD = 580,11,1,0 %; ! Parity Err LW7 Write Data macro KA0905_CPU$V_CBER_FILL_09 = 580,12,4,0 %; literal KA0905_CPU$S_CBER_FILL_09 = 4; macro KA0905_CPU$V_CBER_PELW2RD = 580,16,1,0 %; ! Parity Err LW2 Read Data macro KA0905_CPU$V_CBER_PELW3RD = 580,17,1,0 %; ! Parity Err LW3 Read Data macro KA0905_CPU$V_CBER_PELW6RD = 580,18,1,0 %; ! Parity Err LW6 Read Data macro KA0905_CPU$V_CBER_PELW7RD = 580,19,1,0 %; ! Parity Err LW7 Read Data macro KA0905_CPU$V_CBER_FILL_10 = 580,20,12,0 %; literal KA0905_CPU$S_CBER_FILL_10 = 12; ! Cobra-bus2 Error Address Low Register, CBEALR macro KA0905_CPU$Q_CBEALR = 608,0,0,1 %; literal KA0905_CPU$S_CBEALR = 8; macro KA0905_CPU$L_CBEALR_L = 608,0,32,0 %; macro KA0905_CPU$V_CBEALR_CBLA_0 = 608,0,32,0 %; literal KA0905_CPU$S_CBEALR_CBLA_0 = 32; ! CBus 2 Low Address 0 macro KA0905_CPU$L_CBEALR_H = 612,0,32,0 %; macro KA0905_CPU$V_CBEALR_CBLA_1 = 612,0,32,0 %; literal KA0905_CPU$S_CBEALR_CBLA_1 = 32; ! CBus 2 Low Address 1 ! Cobra-bus2 Error Address High Register, CBEAHR macro KA0905_CPU$Q_CBEAHR = 640,0,0,1 %; literal KA0905_CPU$S_CBEAHR = 8; macro KA0905_CPU$L_CBEAHR_L = 640,0,32,0 %; macro KA0905_CPU$V_CBEAHR_CBHA_0 = 640,0,32,0 %; literal KA0905_CPU$S_CBEAHR_CBHA_0 = 32; ! CBus 2 High Addr 0 macro KA0905_CPU$L_CBEAHR_H = 644,0,32,0 %; macro KA0905_CPU$V_CBEAHR_CBHA_1 = 644,0,32,0 %; literal KA0905_CPU$S_CBEAHR_CBHA_1 = 32; ! CBus 2 High Addr 1 ! Cobra-bus2 Reserve Register, CBRESV macro KA0905_CPU$Q_CBRESV = 672,0,0,1 %; literal KA0905_CPU$S_CBRESV = 8; macro KA0905_CPU$L_CBRESV_L = 672,0,32,0 %; macro KA0905_CPU$V_CBRESV_FILL_01 = 672,0,32,0 %; literal KA0905_CPU$S_CBRESV_FILL_01 = 32; macro KA0905_CPU$L_CBRESV_H = 676,0,32,0 %; macro KA0905_CPU$V_CBRESV_FILL_02 = 676,0,32,0 %; literal KA0905_CPU$S_CBRESV_FILL_02 = 32; ! Address Lock Register, ALR macro KA0905_CPU$Q_ALR = 704,0,0,1 %; literal KA0905_CPU$S_ALR = 8; macro KA0905_CPU$L_ALR_L = 704,0,32,0 %; macro KA0905_CPU$V_ALR_LAV_0 = 704,0,1,0 %; ! Lock Address Valid 0 macro KA0905_CPU$V_ALR_FILL_01 = 704,1,4,0 %; literal KA0905_CPU$S_ALR_FILL_01 = 4; macro KA0905_CPU$V_ALR_LA_0 = 704,5,27,0 %; literal KA0905_CPU$S_ALR_LA_0 = 27; ! Lock Address 0 macro KA0905_CPU$L_ALR_H = 708,0,32,0 %; macro KA0905_CPU$V_ALR_LAV_1 = 708,0,1,0 %; ! Lock Address Valid 1 macro KA0905_CPU$V_ALR_FILL_02 = 708,1,4,0 %; literal KA0905_CPU$S_ALR_FILL_02 = 4; macro KA0905_CPU$V_ALR_LA_1 = 708,5,27,0 %; literal KA0905_CPU$S_ALR_LA_1 = 27; ! Lock Address 1 ! Processor Mailbox Register, PMBR macro KA0905_CPU$Q_PMBR = 736,0,0,1 %; literal KA0905_CPU$S_PMBR = 8; macro KA0905_CPU$L_PMBR_L = 736,0,32,0 %; macro KA0905_CPU$V_PMBR_DATA_0 = 736,0,32,0 %; literal KA0905_CPU$S_PMBR_DATA_0 = 32; ! Data 0 macro KA0905_CPU$L_PMBR_H = 740,0,32,0 %; macro KA0905_CPU$V_PMBR_DATA_1 = 740,0,32,0 %; literal KA0905_CPU$S_PMBR_DATA_1 = 32; ! Data 1 ! Inter-processor Interrupt Request Register, IIRR macro KA0905_CPU$Q_IIRR = 768,0,0,1 %; literal KA0905_CPU$S_IIRR = 8; macro KA0905_CPU$L_IIRR_L = 768,0,32,0 %; macro KA0905_CPU$V_IIRR_FILL_0 = 768,0,32,0 %; literal KA0905_CPU$S_IIRR_FILL_0 = 32; macro KA0905_CPU$L_IIRR_H = 772,0,32,0 %; macro KA0905_CPU$V_IIRR_FILL_02 = 772,0,12,0 %; literal KA0905_CPU$S_IIRR_FILL_02 = 12; macro KA0905_CPU$V_IIRR_RHI = 772,12,1,0 %; ! Requiest Halt Interrupt macro KA0905_CPU$V_IIRR_FILL_03 = 772,13,3,0 %; literal KA0905_CPU$S_IIRR_FILL_03 = 3; macro KA0905_CPU$V_IIRR_II = 772,16,1,0 %; ! Interprocessor Interrupt macro KA0905_CPU$V_IIRR_FILL_04 = 772,17,15,0 %; literal KA0905_CPU$S_IIRR_FILL_04 = 15; ! System Interrupt Clear Register, SICR macro KA0905_CPU$Q_SICR = 800,0,0,1 %; literal KA0905_CPU$S_SICR = 8; macro KA0905_CPU$L_SICR_L = 800,0,32,0 %; macro KA0905_CPU$V_SICR_CBEIC_0 = 800,0,1,0 %; ! CBus2 Err Interrupt Clear 0 macro KA0905_CPU$V_SICR_FILL_01 = 800,1,31,0 %; literal KA0905_CPU$S_SICR_FILL_01 = 31; macro KA0905_CPU$L_SICR_H = 804,0,32,0 %; macro KA0905_CPU$V_SICR_CBEIC_1 = 804,0,1,0 %; ! CBus2 Err Interrupt Clear 1 macro KA0905_CPU$V_SICR_FILL_02 = 804,1,3,0 %; literal KA0905_CPU$S_SICR_FILL_02 = 3; macro KA0905_CPU$V_SICR_ITI = 804,4,1,0 %; ! Interval Timer Interrupt macro KA0905_CPU$V_SICR_FILL_03 = 804,5,3,0 %; literal KA0905_CPU$S_SICR_FILL_03 = 3; macro KA0905_CPU$V_SICR_SEC = 804,8,1,0 %; ! System Event Clear macro KA0905_CPU$V_SICR_FILL_04 = 804,9,3,0 %; literal KA0905_CPU$S_SICR_FILL_04 = 3; macro KA0905_CPU$V_SICR_NHIC = 804,12,1,0 %; ! Node Halt-Interrupt Clear macro KA0905_CPU$V_SICR_FILL_05 = 804,13,3,0 %; literal KA0905_CPU$S_SICR_FILL_05 = 3; macro KA0905_CPU$V_SICR_IIC = 804,16,1,0 %; ! Interprocessor Int Clear macro KA0905_CPU$V_SICR_FILL_06 = 804,17,3,0 %; literal KA0905_CPU$S_SICR_FILL_06 = 3; macro KA0905_CPU$V_SICR_IOII = 804,20,2,0 %; literal KA0905_CPU$S_SICR_IOII = 2; ! I/O Interrupt IRQ macro KA0905_CPU$V_SICR_FILL_07 = 804,22,10,0 %; literal KA0905_CPU$S_SICR_FILL_07 = 10; ! Performance Monitor Control Register, PMCR macro KA0905_CPU$Q_PMCR = 832,0,0,1 %; literal KA0905_CPU$S_PMCR = 8; macro KA0905_CPU$L_PMCR_L = 832,0,32,0 %; macro KA0905_CPU$V_PMCR_SS_0 = 832,0,1,0 %; ! Start Stop 0 macro KA0905_CPU$V_PMCR_FILL_01 = 832,1,3,0 %; literal KA0905_CPU$S_PMCR_FILL_01 = 3; macro KA0905_CPU$V_PMCR_AM_0 = 832,4,2,0 %; literal KA0905_CPU$S_PMCR_AM_0 = 2; ! Address Match 0 macro KA0905_CPU$V_PMCR_FILL_02 = 832,6,6,0 %; literal KA0905_CPU$S_PMCR_FILL_02 = 6; macro KA0905_CPU$V_PMCR_SPMR10 = 832,12,4,0 %; literal KA0905_CPU$S_PMCR_SPMR10 = 4; ! Select PMR10 macro KA0905_CPU$V_PMCR_SPMR9 = 832,16,4,0 %; literal KA0905_CPU$S_PMCR_SPMR9 = 4; ! Select PMR9 macro KA0905_CPU$V_PMCR_SPMR8 = 832,20,4,0 %; literal KA0905_CPU$S_PMCR_SPMR8 = 4; ! Select PMR8 macro KA0905_CPU$V_PMCR_SPMR7 = 832,24,4,0 %; literal KA0905_CPU$S_PMCR_SPMR7 = 4; ! Select PMR7 macro KA0905_CPU$V_PMCR_SPMR6 = 832,28,4,0 %; literal KA0905_CPU$S_PMCR_SPMR6 = 4; ! Select PMR6 macro KA0905_CPU$L_PMCR_H = 836,0,32,0 %; macro KA0905_CPU$V_PMCR_SS_1 = 836,0,1,0 %; ! Start Stop 1 macro KA0905_CPU$V_PMCR_EPMO = 836,1,2,0 %; literal KA0905_CPU$S_PMCR_EPMO = 2; ! Enable Perf Mon Output macro KA0905_CPU$V_PMCR_FILL_03 = 836,3,1,0 %; macro KA0905_CPU$V_PMCR_AM_1 = 836,4,2,0 %; literal KA0905_CPU$S_PMCR_AM_1 = 2; ! Address Match 1 macro KA0905_CPU$V_PMCR_CIDMASK = 836,6,3,0 %; literal KA0905_CPU$S_PMCR_CIDMASK = 3; ! CID Mask macro KA0905_CPU$V_PMCR_CIDMATCH = 836,9,3,0 %; literal KA0905_CPU$S_PMCR_CIDMATCH = 3; ! CIT Match macro KA0905_CPU$V_PMCR_SPMR5 = 836,12,4,0 %; literal KA0905_CPU$S_PMCR_SPMR5 = 4; ! Select PMR5 macro KA0905_CPU$V_PMCR_SPMR4 = 836,16,4,0 %; literal KA0905_CPU$S_PMCR_SPMR4 = 4; ! Select PMR4 macro KA0905_CPU$V_PMCR_SPMR3 = 836,20,4,0 %; literal KA0905_CPU$S_PMCR_SPMR3 = 4; ! Select PMR3 macro KA0905_CPU$V_PMCR_SPMR2 = 836,24,4,0 %; literal KA0905_CPU$S_PMCR_SPMR2 = 4; ! Select PMR2 macro KA0905_CPU$V_PMCR_SPMR1 = 836,28,4,0 %; literal KA0905_CPU$S_PMCR_SPMR1 = 4; ! Select PMR1 ! Performance Monitor Register 1, PMR1 macro KA0905_CPU$Q_PMR1 = 864,0,0,1 %; literal KA0905_CPU$S_PMR1 = 8; macro KA0905_CPU$L_PMR1_L = 864,0,32,0 %; macro KA0905_CPU$V_PMR1_C6 = 864,0,31,0 %; literal KA0905_CPU$S_PMR1_C6 = 31; ! Counter 6 macro KA0905_CPU$V_PMR1_OF6 = 864,31,1,0 %; ! Overflow 6 macro KA0905_CPU$L_PMR1_H = 868,0,32,0 %; macro KA0905_CPU$V_PMR1_C1 = 868,0,31,0 %; literal KA0905_CPU$S_PMR1_C1 = 31; ! Counter 1 macro KA0905_CPU$V_PMR1_OF1 = 868,31,1,0 %; ! Overflow 1 ! Performance Monitor Register 2, PMR2 macro KA0905_CPU$Q_PMR2 = 896,0,0,1 %; literal KA0905_CPU$S_PMR2 = 8; macro KA0905_CPU$L_PMR2_L = 896,0,32,0 %; macro KA0905_CPU$V_PMR2_C7 = 896,0,31,0 %; literal KA0905_CPU$S_PMR2_C7 = 31; ! Counter 7 macro KA0905_CPU$V_PMR2_OF7 = 896,31,1,0 %; ! Overflow 7 macro KA0905_CPU$L_PMR2_H = 900,0,32,0 %; macro KA0905_CPU$V_PMR2_C2 = 900,0,31,0 %; literal KA0905_CPU$S_PMR2_C2 = 31; ! Counter 2 macro KA0905_CPU$V_PMR2_OF2 = 900,31,1,0 %; ! Overflow 2 ! Performance Monitor Register 3, PMR3 macro KA0905_CPU$Q_PMR3 = 928,0,0,1 %; literal KA0905_CPU$S_PMR3 = 8; macro KA0905_CPU$L_PMR3_L = 928,0,32,0 %; macro KA0905_CPU$V_PMR3_C8 = 928,0,31,0 %; literal KA0905_CPU$S_PMR3_C8 = 31; ! Counter 8 macro KA0905_CPU$V_PMR3_OF8 = 928,31,1,0 %; ! Overflow 8 macro KA0905_CPU$L_PMR3_H = 932,0,32,0 %; macro KA0905_CPU$V_PMR3_C3 = 932,0,31,0 %; literal KA0905_CPU$S_PMR3_C3 = 31; ! Counter 3 macro KA0905_CPU$V_PMR3_OF3 = 932,31,1,0 %; ! Overflow 3 ! Performance Monitor Register 4, PMR4 macro KA0905_CPU$Q_PMR4 = 960,0,0,1 %; literal KA0905_CPU$S_PMR4 = 8; macro KA0905_CPU$L_PMR4_L = 960,0,32,0 %; macro KA0905_CPU$V_PMR4_C9 = 960,0,31,0 %; literal KA0905_CPU$S_PMR4_C9 = 31; ! Counter 9 macro KA0905_CPU$V_PMR4_OF9 = 960,31,1,0 %; ! Overflow 9 macro KA0905_CPU$L_PMR4_H = 964,0,32,0 %; macro KA0905_CPU$V_PMR4_C4 = 964,0,31,0 %; literal KA0905_CPU$S_PMR4_C4 = 31; ! Counter 4 macro KA0905_CPU$V_PMR4_OF4 = 964,31,1,0 %; ! Overflow 4 ! Performance Monitor Register 5, PMR5 macro KA0905_CPU$Q_PMR5 = 992,0,0,1 %; literal KA0905_CPU$S_PMR5 = 8; macro KA0905_CPU$L_PMR5_L = 992,0,32,0 %; macro KA0905_CPU$V_PMR5_C10 = 992,0,31,0 %; literal KA0905_CPU$S_PMR5_C10 = 31; ! Counter 10 macro KA0905_CPU$V_PMR5_OF10 = 992,31,1,0 %; ! Overflow 10 macro KA0905_CPU$L_PMR5_H = 996,0,32,0 %; macro KA0905_CPU$V_PMR5_C5 = 996,0,31,0 %; literal KA0905_CPU$S_PMR5_C5 = 31; ! Counter 5 macro KA0905_CPU$V_PMR5_OF5 = 996,31,1,0 %; ! Overflow 5 literal KA0905_CPU$K_LENGTH = 1000; !*** MODULE $KA0C05DEF *** literal KA0C05_BSB$M_TLIPINT_MASK = %X'FFFF'; literal KA0C05_BSB$M_TLIOINT4_MASK = %X'FFFF'; literal KA0C05_BSB$M_TLIOINT4_IPL14 = %X'10000'; literal KA0C05_BSB$M_TLIOINT4_IPL15 = %X'20000'; literal KA0C05_BSB$M_TLIOINT4_IPL16 = %X'40000'; literal KA0C05_BSB$M_TLIOINT4_IPL17 = %X'80000'; literal KA0C05_BSB$M_TLIOINT5_MASK = %X'FFFF'; literal KA0C05_BSB$M_TLIOINT5_IPL14 = %X'10000'; literal KA0C05_BSB$M_TLIOINT5_IPL15 = %X'20000'; literal KA0C05_BSB$M_TLIOINT5_IPL16 = %X'40000'; literal KA0C05_BSB$M_TLIOINT5_IPL17 = %X'80000'; literal KA0C05_BSB$M_TLIOINT6_MASK = %X'FFFF'; literal KA0C05_BSB$M_TLIOINT6_IPL14 = %X'10000'; literal KA0C05_BSB$M_TLIOINT6_IPL15 = %X'20000'; literal KA0C05_BSB$M_TLIOINT6_IPL16 = %X'40000'; literal KA0C05_BSB$M_TLIOINT6_IPL17 = %X'80000'; literal KA0C05_BSB$M_TLIOINT7_MASK = %X'FFFF'; literal KA0C05_BSB$M_TLIOINT7_IPL14 = %X'10000'; literal KA0C05_BSB$M_TLIOINT7_IPL15 = %X'20000'; literal KA0C05_BSB$M_TLIOINT7_IPL16 = %X'40000'; literal KA0C05_BSB$M_TLIOINT7_IPL17 = %X'80000'; literal KA0C05_BSB$M_TLIOINT8_MASK = %X'FFFF'; literal KA0C05_BSB$M_TLIOINT8_IPL14 = %X'10000'; literal KA0C05_BSB$M_TLIOINT8_IPL15 = %X'20000'; literal KA0C05_BSB$M_TLIOINT8_IPL16 = %X'40000'; literal KA0C05_BSB$M_TLIOINT8_IPL17 = %X'80000'; literal KA0C05_BSB$S_KA0C05_BSB = 8200; macro KA0C05_BSB$L_TLPRIVATE = 0,0,32,0 %; macro KA0C05_BSB$b_f10 = 4,0,0,0 %; literal KA0C05_BSB$s_f10 = 60; macro KA0C05_BSB$L_TLIPINT = 64,0,32,0 %; macro KA0C05_BSB$V_TLIPINT_MASK = 64,0,16,0 %; literal KA0C05_BSB$S_TLIPINT_MASK = 16; macro KA0C05_BSB$b_f20 = 68,0,0,0 %; literal KA0C05_BSB$s_f20 = 188; macro KA0C05_BSB$L_TLIOINT4 = 256,0,32,0 %; macro KA0C05_BSB$V_TLIOINT4_MASK = 256,0,16,0 %; literal KA0C05_BSB$S_TLIOINT4_MASK = 16; macro KA0C05_BSB$V_TLIOINT4_IPL14 = 256,16,1,0 %; macro KA0C05_BSB$V_TLIOINT4_IPL15 = 256,17,1,0 %; macro KA0C05_BSB$V_TLIOINT4_IPL16 = 256,18,1,0 %; macro KA0C05_BSB$V_TLIOINT4_IPL17 = 256,19,1,0 %; macro KA0C05_BSB$b_fill30 = 260,0,0,0 %; literal KA0C05_BSB$s_fill30 = 60; macro KA0C05_BSB$L_TLIOINT5 = 320,0,32,0 %; macro KA0C05_BSB$V_TLIOINT5_MASK = 320,0,16,0 %; literal KA0C05_BSB$S_TLIOINT5_MASK = 16; macro KA0C05_BSB$V_TLIOINT5_IPL14 = 320,16,1,0 %; macro KA0C05_BSB$V_TLIOINT5_IPL15 = 320,17,1,0 %; macro KA0C05_BSB$V_TLIOINT5_IPL16 = 320,18,1,0 %; macro KA0C05_BSB$V_TLIOINT5_IPL17 = 320,19,1,0 %; macro KA0C05_BSB$b_fill40 = 324,0,0,0 %; literal KA0C05_BSB$s_fill40 = 60; macro KA0C05_BSB$L_TLIOINT6 = 384,0,32,0 %; macro KA0C05_BSB$V_TLIOINT6_MASK = 384,0,16,0 %; literal KA0C05_BSB$S_TLIOINT6_MASK = 16; macro KA0C05_BSB$V_TLIOINT6_IPL14 = 384,16,1,0 %; macro KA0C05_BSB$V_TLIOINT6_IPL15 = 384,17,1,0 %; macro KA0C05_BSB$V_TLIOINT6_IPL16 = 384,18,1,0 %; macro KA0C05_BSB$V_TLIOINT6_IPL17 = 384,19,1,0 %; macro KA0C05_BSB$b_fill50 = 388,0,0,0 %; literal KA0C05_BSB$s_fill50 = 60; macro KA0C05_BSB$L_TLIOINT7 = 448,0,32,0 %; macro KA0C05_BSB$V_TLIOINT7_MASK = 448,0,16,0 %; literal KA0C05_BSB$S_TLIOINT7_MASK = 16; macro KA0C05_BSB$V_TLIOINT7_IPL14 = 448,16,1,0 %; macro KA0C05_BSB$V_TLIOINT7_IPL15 = 448,17,1,0 %; macro KA0C05_BSB$V_TLIOINT7_IPL16 = 448,18,1,0 %; macro KA0C05_BSB$V_TLIOINT7_IPL17 = 448,19,1,0 %; macro KA0C05_BSB$b_fill60 = 452,0,0,0 %; literal KA0C05_BSB$s_fill60 = 60; macro KA0C05_BSB$L_TLIOINT8 = 512,0,32,0 %; macro KA0C05_BSB$V_TLIOINT8_MASK = 512,0,16,0 %; literal KA0C05_BSB$S_TLIOINT8_MASK = 16; macro KA0C05_BSB$V_TLIOINT8_IPL14 = 512,16,1,0 %; macro KA0C05_BSB$V_TLIOINT8_IPL15 = 512,17,1,0 %; macro KA0C05_BSB$V_TLIOINT8_IPL16 = 512,18,1,0 %; macro KA0C05_BSB$V_TLIOINT8_IPL17 = 512,19,1,0 %; macro KA0C05_BSB$b_fill70 = 516,0,0,0 %; literal KA0C05_BSB$s_fill70 = 508; macro KA0C05_BSB$L_TLWSDQR4 = 1024,0,32,0 %; macro KA0C05_BSB$b_fill80 = 1028,0,0,0 %; literal KA0C05_BSB$s_fill80 = 60; macro KA0C05_BSB$L_TLWSDQR5 = 1088,0,32,0 %; macro KA0C05_BSB$b_fill90 = 1092,0,0,0 %; literal KA0C05_BSB$s_fill90 = 60; macro KA0C05_BSB$L_TLWSDQR6 = 1152,0,32,0 %; macro KA0C05_BSB$b_f100 = 1156,0,0,0 %; literal KA0C05_BSB$s_f100 = 60; macro KA0C05_BSB$L_TLWSDQR7 = 1216,0,32,0 %; macro KA0C05_BSB$b_f110 = 1220,0,0,0 %; literal KA0C05_BSB$s_f110 = 60; macro KA0C05_BSB$L_TLWSDQR8 = 1280,0,32,0 %; macro KA0C05_BSB$b_f120 = 1284,0,0,0 %; literal KA0C05_BSB$s_f120 = 252; macro KA0C05_BSB$L_TLRMDQRX = 1536,0,32,0 %; macro KA0C05_BSB$b_f130 = 1540,0,0,0 %; literal KA0C05_BSB$s_f130 = 60; macro KA0C05_BSB$L_TLRMDQR8 = 1600,0,32,0 %; macro KA0C05_BSB$b_f140 = 1604,0,0,0 %; literal KA0C05_BSB$s_f140 = 444; macro KA0C05_BSB$Q_TLRDRD = 2048,0,0,1 %; literal KA0C05_BSB$S_TLRDRD = 8; macro KA0C05_BSB$b_f150 = 2056,0,0,0 %; literal KA0C05_BSB$s_f150 = 60; macro KA0C05_BSB$L_TLRDRE = 2116,0,32,0 %; macro KA0C05_BSB$b_f160 = 2120,0,0,0 %; literal KA0C05_BSB$s_f160 = 4156; macro KA0C05_BSB$L_TLMCR = 6276,0,32,0 %; macro KA0C05_BSB$b_f170 = 6280,0,0,0 %; literal KA0C05_BSB$s_f170 = 1916; literal KA0C05_TLEP$M_TLDEV_DTYPE = %X'FFFF'; literal KA0C05_TLEP$M_TLDEV_SWREV = %X'FF0000'; literal KA0C05_TLEP$M_TLDEV_HWREV = %X'FF000000'; literal KA0C05_TLEP$M_TLBER_ATCE = %X'1'; literal KA0C05_TLEP$M_TLBER_APE = %X'2'; literal KA0C05_TLEP$M_TLBER_BBE = %X'4'; literal KA0C05_TLEP$M_TLBER_LKTO = %X'8'; literal KA0C05_TLEP$M_TLBER_NAE = %X'10'; literal KA0C05_TLEP$M_TLBER_RTCE = %X'20'; literal KA0C05_TLEP$M_TLBER_ACKTCE = %X'40'; literal KA0C05_TLEP$M_TLBER_MMRE = %X'80'; literal KA0C05_TLEP$M_TLBER_FNAE = %X'100'; literal KA0C05_TLEP$M_TLBER_REQDE = %X'200'; literal KA0C05_TLEP$M_TLBER_ATDE = %X'400'; literal KA0C05_TLEP$M_TLBER_UDE = %X'10000'; literal KA0C05_TLEP$M_TLBER_CWDE = %X'20000'; literal KA0C05_TLEP$M_TLBER_CRDE = %X'40000'; literal KA0C05_TLEP$M_TLBER_DS0 = %X'100000'; literal KA0C05_TLEP$M_TLBER_DS1 = %X'200000'; literal KA0C05_TLEP$M_TLBER_DS2 = %X'400000'; literal KA0C05_TLEP$M_TLBER_DS3 = %X'800000'; literal KA0C05_TLEP$M_TLBER_DTDE = %X'1000000'; literal KA0C05_TLEP$M_TLBER_FDTCE = %X'2000000'; literal KA0C05_TLEP$M_TLBER_UACKE = %X'4000000'; literal KA0C05_TLEP$M_TLBER_ABTCE = %X'8000000'; literal KA0C05_TLEP$M_TLBER_DCTCE = %X'10000000'; literal KA0C05_TLEP$M_TLBER_SEQE = %X'20000000'; literal KA0C05_TLEP$M_TLBER_DSE = %X'40000000'; literal KA0C05_TLEP$M_TLBER_DTO = %X'80000000'; literal KA0C05_TLEP$M_TLCNR_CWDD = %X'1'; literal KA0C05_TLEP$M_TLCNR_CRDD = %X'2'; literal KA0C05_TLEP$M_TLCNR_DTOD = %X'8'; literal KA0C05_TLEP$M_TLCNR_NODE_ID = %X'F0'; literal KA0C05_TLEP$M_TLCNR_VCNT = %X'F00'; literal KA0C05_TLEP$M_TLCNR_STF_A = %X'1000'; literal KA0C05_TLEP$M_TLCNR_STF_B = %X'2000'; literal KA0C05_TLEP$M_TLCNR_HALT_A = %X'100000'; literal KA0C05_TLEP$M_TLCNR_HALT_B = %X'200000'; literal KA0C05_TLEP$M_TLCNR_NRST = %X'40000000'; literal KA0C05_TLEP$M_TLCNR_LOFE = %X'80000000'; literal KA0C05_TLEP$M_VID_A = %X'F'; literal KA0C05_TLEP$M_VID_B = %X'F0'; literal KA0C05_TLEP$M_TLMMR0_INTMASK = %X'3'; literal KA0C05_TLEP$M_TLMMR0_ADRMASK = %X'F0'; literal KA0C05_TLEP$M_TLMMR0_INTLV = %X'700'; literal KA0C05_TLEP$M_TLMMR0_SBANK = %X'800'; literal KA0C05_TLEP$M_TLMMR0_ADDRESS = %X'3FFF000'; literal KA0C05_TLEP$M_TLMMR0_VALID = %X'80000000'; literal KA0C05_TLEP$M_TLMMR1_INTMASK = %X'3'; literal KA0C05_TLEP$M_TLMMR1_ADRMASK = %X'F0'; literal KA0C05_TLEP$M_TLMMR1_INTLV = %X'700'; literal KA0C05_TLEP$M_TLMMR1_SBANK = %X'800'; literal KA0C05_TLEP$M_TLMMR1_ADDRESS = %X'3FFF000'; literal KA0C05_TLEP$M_TLMMR1_VALID = %X'80000000'; literal KA0C05_TLEP$M_TLMMR2_INTMASK = %X'3'; literal KA0C05_TLEP$M_TLMMR2_ADRMASK = %X'F0'; literal KA0C05_TLEP$M_TLMMR2_INTLV = %X'700'; literal KA0C05_TLEP$M_TLMMR2_SBANK = %X'800'; literal KA0C05_TLEP$M_TLMMR2_ADDRESS = %X'3FFF000'; literal KA0C05_TLEP$M_TLMMR2_VALID = %X'80000000'; literal KA0C05_TLEP$M_TLMMR3_INTMASK = %X'3'; literal KA0C05_TLEP$M_TLMMR3_ADRMASK = %X'F0'; literal KA0C05_TLEP$M_TLMMR3_INTLV = %X'700'; literal KA0C05_TLEP$M_TLMMR3_SBANK = %X'800'; literal KA0C05_TLEP$M_TLMMR3_ADDRESS = %X'3FFF000'; literal KA0C05_TLEP$M_TLMMR3_VALID = %X'80000000'; literal KA0C05_TLEP$M_TLMMR4_INTMASK = %X'3'; literal KA0C05_TLEP$M_TLMMR4_ADRMASK = %X'F0'; literal KA0C05_TLEP$M_TLMMR4_INTLV = %X'700'; literal KA0C05_TLEP$M_TLMMR4_SBANK = %X'800'; literal KA0C05_TLEP$M_TLMMR4_ADDRESS = %X'3FFF000'; literal KA0C05_TLEP$M_TLMMR4_VALID = %X'80000000'; literal KA0C05_TLEP$M_TLMMR5_INTMASK = %X'3'; literal KA0C05_TLEP$M_TLMMR5_ADRMASK = %X'F0'; literal KA0C05_TLEP$M_TLMMR5_INTLV = %X'700'; literal KA0C05_TLEP$M_TLMMR5_SBANK = %X'800'; literal KA0C05_TLEP$M_TLMMR5_ADDRESS = %X'3FFF000'; literal KA0C05_TLEP$M_TLMMR5_VALID = %X'80000000'; literal KA0C05_TLEP$M_TLMMR6_INTMASK = %X'3'; literal KA0C05_TLEP$M_TLMMR6_ADRMASK = %X'F0'; literal KA0C05_TLEP$M_TLMMR6_INTLV = %X'700'; literal KA0C05_TLEP$M_TLMMR6_SBANK = %X'800'; literal KA0C05_TLEP$M_TLMMR6_ADDRESS = %X'3FFF000'; literal KA0C05_TLEP$M_TLMMR6_VALID = %X'80000000'; literal KA0C05_TLEP$M_TLMMR7_INTMASK = %X'3'; literal KA0C05_TLEP$M_TLMMR7_ADRMASK = %X'F0'; literal KA0C05_TLEP$M_TLMMR7_INTLV = %X'700'; literal KA0C05_TLEP$M_TLMMR7_SBANK = %X'800'; literal KA0C05_TLEP$M_TLMMR7_ADDRESS = %X'3FFF000'; literal KA0C05_TLEP$M_TLMMR7_VALID = %X'80000000'; literal KA0C05_TLEP$M_TLESR0_SYND0 = %X'FF'; literal KA0C05_TLEP$M_TLESR0_SYND1 = %X'FF00'; literal KA0C05_TLEP$M_TLESR0_TDE = %X'10000'; literal KA0C05_TLEP$M_TLESR0_TCE = %X'20000'; literal KA0C05_TLEP$M_TLESR0_DVTCE = %X'40000'; literal KA0C05_TLEP$M_TLESR0_UECC = %X'80000'; literal KA0C05_TLEP$M_TLESR0_CWECC = %X'100000'; literal KA0C05_TLEP$M_TLESR0_CRECC = %X'200000'; literal KA0C05_TLEP$M_TLESR0_CPU0 = %X'400000'; literal KA0C05_TLEP$M_TLESR0_CPU1 = %X'800000'; literal KA0C05_TLEP$M_TLESR0_LOFSYN = %X'80000000'; literal KA0C05_TLEP$M_TLESR1_SYND0 = %X'FF'; literal KA0C05_TLEP$M_TLESR1_SYND1 = %X'FF00'; literal KA0C05_TLEP$M_TLESR1_TDE = %X'10000'; literal KA0C05_TLEP$M_TLESR1_TCE = %X'20000'; literal KA0C05_TLEP$M_TLESR1_DVTCE = %X'40000'; literal KA0C05_TLEP$M_TLESR1_UECC = %X'80000'; literal KA0C05_TLEP$M_TLESR1_CWECC = %X'100000'; literal KA0C05_TLEP$M_TLESR1_CRECC = %X'200000'; literal KA0C05_TLEP$M_TLESR1_CPU0 = %X'400000'; literal KA0C05_TLEP$M_TLESR1_CPU1 = %X'800000'; literal KA0C05_TLEP$M_TLESR1_LOFSYN = %X'80000000'; literal KA0C05_TLEP$M_TLESR2_SYND0 = %X'FF'; literal KA0C05_TLEP$M_TLESR2_SYND1 = %X'FF00'; literal KA0C05_TLEP$M_TLESR2_TDE = %X'10000'; literal KA0C05_TLEP$M_TLESR2_TCE = %X'20000'; literal KA0C05_TLEP$M_TLESR2_DVTCE = %X'40000'; literal KA0C05_TLEP$M_TLESR2_UECC = %X'80000'; literal KA0C05_TLEP$M_TLESR2_CWECC = %X'100000'; literal KA0C05_TLEP$M_TLESR2_CRECC = %X'200000'; literal KA0C05_TLEP$M_TLESR2_CPU0 = %X'400000'; literal KA0C05_TLEP$M_TLESR2_CPU1 = %X'800000'; literal KA0C05_TLEP$M_TLESR2_LOFSYN = %X'80000000'; literal KA0C05_TLEP$M_TLESR3_SYND0 = %X'FF'; literal KA0C05_TLEP$M_TLESR3_SYND1 = %X'FF00'; literal KA0C05_TLEP$M_TLESR3_TDE = %X'10000'; literal KA0C05_TLEP$M_TLESR3_TCE = %X'20000'; literal KA0C05_TLEP$M_TLESR3_DVTCE = %X'40000'; literal KA0C05_TLEP$M_TLESR3_UECC = %X'80000'; literal KA0C05_TLEP$M_TLESR3_CWECC = %X'100000'; literal KA0C05_TLEP$M_TLESR3_CRECC = %X'200000'; literal KA0C05_TLEP$M_TLESR3_CPU0 = %X'400000'; literal KA0C05_TLEP$M_TLESR3_CPU1 = %X'800000'; literal KA0C05_TLEP$M_TLESR3_LOFSYN = %X'80000000'; literal KA0C05_TLEP$M_TLDIAG_FRIGN = %X'1'; literal KA0C05_TLEP$M_TLDIAG_DTWR = %X'2'; literal KA0C05_TLEP$M_TLDIAG_DTRD = %X'4'; literal KA0C05_TLEP$M_TLDIAG_DTCP = %X'8'; literal KA0C05_TLEP$M_TLDIAG_FVW = %X'10'; literal KA0C05_TLEP$M_TLDIAG_FAE = %X'20'; literal KA0C05_TLEP$M_TLDIAG_FCBE = %X'40'; literal KA0C05_TLEP$M_TLDIAG_FDBE = %X'80'; literal KA0C05_TLEP$M_TLDIAG_FDE = %X'F00'; literal KA0C05_TLEP$M_TLDIAG_FTW = %X'1000'; literal KA0C05_TLEP$M_TLDIAG_ASRT_FLT = %X'2000'; literal KA0C05_TLEP$M_TLDIAG_QWVAL_EN = %X'4000'; literal KA0C05_TLEP$M_TLDIAG_GSLOW = %X'8000'; literal KA0C05_TLEP$M_TLDTAGD_DTAG_PAR = %X'1'; literal KA0C05_TLEP$M_TLDTAGD_DTAG_DATA = %X'FFFFE'; literal KA0C05_TLEP$M_TLDTAGS_STATPAR = %X'1'; literal KA0C05_TLEP$M_TLDTAGS_STATD = %X'2'; literal KA0C05_TLEP$M_TLDTAGS_STATS = %X'4'; literal KA0C05_TLEP$M_TLDTAGS_STATV = %X'8'; literal KA0C05_TLEP$M_TLMCFG_CPU0DSBL = %X'1'; literal KA0C05_TLEP$M_TLMCFG_CPU1DSBL = %X'2'; literal KA0C05_TLEP$M_TLMCFG_BC_SIZE = %X'C'; literal KA0C05_TLEP$M_TLMCFG_LO_EN = %X'10'; literal KA0C05_TLEP$M_TLMCFG_RM_SIZE = %X'20'; literal KA0C05_TLEP$M_TLMCFG_BCIDLE = %X'3C0'; literal KA0C05_TLEP$M_TLMCFG_CQ_ENTRY = %X'1C00'; literal KA0C05_TLEP$M_TLMCFG_BQ_ENTRY = %X'E000'; literal KA0C05_TLEP$M_TLMCFG_SYS_DSBL = %X'10000'; literal KA0C05_TLEP$M_TLMCFG_EV5_DSBL = %X'20000'; literal KA0C05_TLEP$M_TLMCFG_FLT_DSBL = %X'40000'; literal KA0C05_TLEP$M_TLIMASK0_DUART0EN = %X'1'; literal KA0C05_TLEP$M_TLIMASK0_IPL14_EN = %X'2'; literal KA0C05_TLEP$M_TLIMASK0_IPL15_EN = %X'4'; literal KA0C05_TLEP$M_TLIMASK0_IPL16_EN = %X'8'; literal KA0C05_TLEP$M_TLIMASK0_IPL17_EN = %X'10'; literal KA0C05_TLEP$M_TLIMASK0_IP_EN = %X'20'; literal KA0C05_TLEP$M_TLIMASK0_INTIM_EN = %X'40'; literal KA0C05_TLEP$M_TLIMASK0_HALT_EN = %X'80'; literal KA0C05_TLEP$M_TLIMASK0_CP_EN = %X'100'; literal KA0C05_TLEP$M_TLIMASK1_DUART0EN = %X'1'; literal KA0C05_TLEP$M_TLIMASK1_IPL14_EN = %X'2'; literal KA0C05_TLEP$M_TLIMASK1_IPL15_EN = %X'4'; literal KA0C05_TLEP$M_TLIMASK1_IPL16_EN = %X'8'; literal KA0C05_TLEP$M_TLIMASK1_IPL17_EN = %X'10'; literal KA0C05_TLEP$M_TLIMASK1_IP_EN = %X'20'; literal KA0C05_TLEP$M_TLIMASK1_INTIM_EN = %X'40'; literal KA0C05_TLEP$M_TLIMASK1_HALT_EN = %X'80'; literal KA0C05_TLEP$M_TLIMASK1_CP_EN = %X'100'; literal KA0C05_TLEP$M_TLISUM0_DUART0INT = %X'1'; literal KA0C05_TLEP$M_TLISUM0_IPL14_INT = %X'2'; literal KA0C05_TLEP$M_TLISUM0_IPL15_INT = %X'4'; literal KA0C05_TLEP$M_TLISUM0_IPL16_INT = %X'8'; literal KA0C05_TLEP$M_TLISUM0_IPL17_INT = %X'10'; literal KA0C05_TLEP$M_TLISUM0_IP_INT = %X'20'; literal KA0C05_TLEP$M_TLISUM0_INTIM_INT = %X'40'; literal KA0C05_TLEP$M_TLISUM0_IPL14 = %X'F80'; literal KA0C05_TLEP$M_TLISUM0_IPL15 = %X'1F000'; literal KA0C05_TLEP$M_TLISUM0_IPL16 = %X'3E0000'; literal KA0C05_TLEP$M_TLISUM0_IPL17 = %X'7C00000'; literal KA0C05_TLEP$M_TLISUM0_CP_HALT = %X'8000000'; literal KA0C05_TLEP$M_TLISUM0_HALT = %X'10000000'; literal KA0C05_TLEP$M_TLISUM1_DUART0INT = %X'1'; literal KA0C05_TLEP$M_TLISUM1_IPL14_INT = %X'2'; literal KA0C05_TLEP$M_TLISUM1_IPL15_INT = %X'4'; literal KA0C05_TLEP$M_TLISUM1_IPL16_INT = %X'8'; literal KA0C05_TLEP$M_TLISUM1_IPL17_INT = %X'10'; literal KA0C05_TLEP$M_TLISUM1_IP_INT = %X'20'; literal KA0C05_TLEP$M_TLISUM1_INTIM_INT = %X'40'; literal KA0C05_TLEP$M_TLISUM1_IPL14 = %X'F80'; literal KA0C05_TLEP$M_TLISUM1_IPL15 = %X'1F000'; literal KA0C05_TLEP$M_TLISUM1_IPL16 = %X'3E0000'; literal KA0C05_TLEP$M_TLISUM1_IPL17 = %X'7C00000'; literal KA0C05_TLEP$M_TLISUM1_CP_HALT = %X'8000000'; literal KA0C05_TLEP$M_TLISUM1_HALT = %X'10000000'; literal KA0C05_TLEP$M_TLEPAERR_E2MAPE0 = %X'1'; literal KA0C05_TLEP$M_TLEPAERR_E2MAPE1 = %X'2'; literal KA0C05_TLEP$M_TLEPAERR_M2AAPE0 = %X'4'; literal KA0C05_TLEP$M_TLEPAERR_M2AAPE1 = %X'8'; literal KA0C05_TLEP$M_TLEPAERR_DTDPE = %X'10'; literal KA0C05_TLEP$M_TLEPAERR_DTSPE = %X'20'; literal KA0C05_TLEP$M_TLEPAERR_D2ACPE = %X'40'; literal KA0C05_TLEP$M_TLEPAERR_SYSDERR = %X'80'; literal KA0C05_TLEP$M_TLEPAERR_SYSFLT = %X'100'; literal KA0C05_TLEP$M_TLEPAERR_RD_ERR = %X'600'; literal KA0C05_TLEP$M_TLEPAERR_IBOXTO = %X'1800'; literal KA0C05_TLEP$M_TLEPAERR_RD_PEND = %X'6000'; literal KA0C05_TLEP$M_TLEPAERR_NXM = %X'8000'; literal KA0C05_TLEP$M_TLEPAERR_NO_ACK = %X'30000'; literal KA0C05_TLEP$M_TLEPDERR_A2DCPE = %X'1'; literal KA0C05_TLEP$M_TLEPDERR_D2DCPE0 = %X'2'; literal KA0C05_TLEP$M_TLEPDERR_GBTO = %X'4'; literal KA0C05_TLEP$M_TLEPMERR_A2MAPE0 = %X'1'; literal KA0C05_TLEP$M_TLEPMERR_A2MAPE1 = %X'2'; literal KA0C05_TLEP$M_TLEPMERR_D2MCPE = %X'4'; literal KA0C05_TLEP$M_TLEPMERR_D2DCPE1 = %X'8'; literal KA0C05_TLEP$M_TLEPMERR_D2DCPE2 = %X'10'; literal KA0C05_TLEP$M_TLEPMERR_D2DCPE3 = %X'20'; literal KA0C05_TLEP$M_TLEPMERR_RSTSTAT = %X'40'; literal KA0C05_TLEP$M_TLEP_VMG_5P = %X'1'; literal KA0C05_TLEP$M_TLEP_VMG_5M = %X'2'; literal KA0C05_TLEP$M_TLEP_VMG_3P = %X'4'; literal KA0C05_TLEP$M_TLEP_VMG_3M = %X'8'; literal KA0C05_TLEP$M_TLDMCMD_SIZE_512 = %X'1'; literal KA0C05_TLEP$M_TLDMCMD_SIZE_1K = %X'2'; literal KA0C05_TLEP$M_TLDMCMD_SIZE_2K = %X'4'; literal KA0C05_TLEP$M_TLDMCMD_SIZE_4K = %X'8'; literal KA0C05_TLEP$M_TLDMCMD_SIZE_8K = %X'10'; literal KA0C05_TLEP$M_TLDMCMD_CMD = %X'300'; literal KA0C05_TLEP$M_TLDMCMD_VALID = %X'800'; literal KA0C05_TLEP$M_TLDMCMD_RM_3 = %X'1000'; literal KA0C05_TLEP$M_TLDMCMD_RM_4 = %X'2000'; literal KA0C05_TLEP$M_TLDMCMD_RM_INLV = %X'4000'; literal KA0C05_TLEP$M_TLDMCMD_CPU_ID = %X'10000'; literal KA0C05_TLEP$M_TLDMCMD_IN_PROG = %X'100000'; literal KA0C05_TLEP$M_TLDMCMD_DONE = %X'200000'; literal KA0C05_TLEP$M_TLDMADRA_ADDR = %X'3FFFFFFF'; literal KA0C05_TLEP$M_TLDMADRB_ADDR = %X'3FFFFFFF'; literal KA0C05_TLEP$M_TLPM_CMD_CPUNUM = %X'1'; literal KA0C05_TLEP$M_TLPM_CMD_SET_SEL = %X'6'; literal KA0C05_TLEP$M_TLPM_CMD_VALID = %X'8'; literal KA0C05_TLEP$M_TLPM_CMD_READ_SET = %X'10'; literal KA0C05_TLEP$M_TLPM_CMD_OVRF_EN = %X'800'; literal KA0C05_TLEP$M_TLPM_CMD_TOT_CYC = %X'1000'; literal KA0C05_TLEP$M_TLPM_CMD_EV5_LAT = %X'2000'; literal KA0C05_TLEP$M_TLPM_CMD_RD_LAT = %X'4000'; literal KA0C05_TLEP$M_TLPM_CMD_SYS_OWN = %X'8000'; literal KA0C05_TLEP$M_TLPM_CMD_f2 = %X'10000'; literal KA0C05_TLEP$M_TLPM_CMD_LOCK = %X'20000'; literal KA0C05_TLEP$M_TLPM_CMD_MB = %X'40000'; literal KA0C05_TLEP$M_TLPM_CMD_SD_TOT = %X'80000'; literal KA0C05_TLEP$M_TLPM_CMD_SD_ACK = %X'100000'; literal KA0C05_TLEP$M_TLPM_CMD_RD_CSR = %X'200000'; literal KA0C05_TLEP$M_TLPM_CMD_RD = %X'400000'; literal KA0C05_TLEP$M_TLPM_CMD_RD_MOD = %X'800000'; literal KA0C05_TLEP$M_TLPM_CMD_RD_STC = %X'1000000'; literal KA0C05_TLEP$M_TLPM_CMD_VIC = %X'2000000'; literal KA0C05_TLEP$M_TLPM_CMD_WR_CSR = %X'4000000'; literal KA0C05_TLEP$M_TLPM_CMD_WR = %X'8000000'; literal KA0C05_TLEP$M_TLPM_CMD_WR_LOCK = %X'10000000'; literal KA0C05_TLEP$M_TLPM_CMD_INVAL = %X'20000000'; literal KA0C05_TLEP$M_TLPM_CMD_SET_SHR = %X'40000000'; literal KA0C05_TLEP$M_TLPM_CMD_RD_DIRT = %X'80000000'; literal KA0C05_TLEP$M_RM_REG0A_AEXT = %X'F'; literal KA0C05_TLEP$M_RM_REG0A_BADDR = %X'FFFFF00'; literal KA0C05_TLEP$M_RM_REG0A_VALID = %X'80000000'; literal KA0C05_TLEP$M_RM_REG0B_AEXT = %X'F'; literal KA0C05_TLEP$M_RM_REG0B_BADDR = %X'FFFFF00'; literal KA0C05_TLEP$M_RM_REG0B_VALID = %X'80000000'; literal KA0C05_TLEP$M_RM_REG1A_AEXT = %X'F'; literal KA0C05_TLEP$M_RM_REG1A_BADDR = %X'FFFFF00'; literal KA0C05_TLEP$M_RM_REG1A_VALID = %X'80000000'; literal KA0C05_TLEP$M_RM_REG1B_AEXT = %X'F'; literal KA0C05_TLEP$M_RM_REG1B_BADDR = %X'FFFFF00'; literal KA0C05_TLEP$M_RM_REG1B_VALID = %X'80000000'; literal KA0C05_TLEP$S_KA0C05_TLEP = 8064; macro KA0C05_TLEP$L_TLDEV = 0,0,32,0 %; macro KA0C05_TLEP$V_TLDEV_DTYPE = 0,0,16,0 %; literal KA0C05_TLEP$S_TLDEV_DTYPE = 16; macro KA0C05_TLEP$V_TLDEV_SWREV = 0,16,8,0 %; literal KA0C05_TLEP$S_TLDEV_SWREV = 8; macro KA0C05_TLEP$V_TLDEV_HWREV = 0,24,8,0 %; literal KA0C05_TLEP$S_TLDEV_HWREV = 8; macro KA0C05_TLEP$b_f200 = 4,0,0,0 %; literal KA0C05_TLEP$s_f200 = 60; macro KA0C05_TLEP$L_TLBER = 64,0,32,0 %; macro KA0C05_TLEP$V_TLBER_ATCE = 64,0,1,0 %; macro KA0C05_TLEP$V_TLBER_APE = 64,1,1,0 %; macro KA0C05_TLEP$V_TLBER_BBE = 64,2,1,0 %; macro KA0C05_TLEP$V_TLBER_LKTO = 64,3,1,0 %; macro KA0C05_TLEP$V_TLBER_NAE = 64,4,1,0 %; macro KA0C05_TLEP$V_TLBER_RTCE = 64,5,1,0 %; macro KA0C05_TLEP$V_TLBER_ACKTCE = 64,6,1,0 %; macro KA0C05_TLEP$V_TLBER_MMRE = 64,7,1,0 %; macro KA0C05_TLEP$V_TLBER_FNAE = 64,8,1,0 %; macro KA0C05_TLEP$V_TLBER_REQDE = 64,9,1,0 %; macro KA0C05_TLEP$V_TLBER_ATDE = 64,10,1,0 %; macro KA0C05_TLEP$V_TLBER_UDE = 64,16,1,0 %; macro KA0C05_TLEP$V_TLBER_CWDE = 64,17,1,0 %; macro KA0C05_TLEP$V_TLBER_CRDE = 64,18,1,0 %; macro KA0C05_TLEP$V_TLBER_DS0 = 64,20,1,0 %; macro KA0C05_TLEP$V_TLBER_DS1 = 64,21,1,0 %; macro KA0C05_TLEP$V_TLBER_DS2 = 64,22,1,0 %; macro KA0C05_TLEP$V_TLBER_DS3 = 64,23,1,0 %; macro KA0C05_TLEP$V_TLBER_DTDE = 64,24,1,0 %; macro KA0C05_TLEP$V_TLBER_FDTCE = 64,25,1,0 %; macro KA0C05_TLEP$V_TLBER_UACKE = 64,26,1,0 %; macro KA0C05_TLEP$V_TLBER_ABTCE = 64,27,1,0 %; macro KA0C05_TLEP$V_TLBER_DCTCE = 64,28,1,0 %; macro KA0C05_TLEP$V_TLBER_SEQE = 64,29,1,0 %; macro KA0C05_TLEP$V_TLBER_DSE = 64,30,1,0 %; macro KA0C05_TLEP$V_TLBER_DTO = 64,31,1,0 %; macro KA0C05_TLEP$b_f210 = 68,0,0,0 %; literal KA0C05_TLEP$s_f210 = 60; macro KA0C05_TLEP$L_TLCNR = 128,0,32,0 %; macro KA0C05_TLEP$V_TLCNR_CWDD = 128,0,1,0 %; macro KA0C05_TLEP$V_TLCNR_CRDD = 128,1,1,0 %; macro KA0C05_TLEP$V_TLCNR_DTOD = 128,3,1,0 %; macro KA0C05_TLEP$V_TLCNR_NODE_ID = 128,4,4,0 %; literal KA0C05_TLEP$S_TLCNR_NODE_ID = 4; macro KA0C05_TLEP$V_TLCNR_VCNT = 128,8,4,0 %; literal KA0C05_TLEP$S_TLCNR_VCNT = 4; macro KA0C05_TLEP$V_TLCNR_STF_A = 128,12,1,0 %; macro KA0C05_TLEP$V_TLCNR_STF_B = 128,13,1,0 %; macro KA0C05_TLEP$V_TLCNR_HALT_A = 128,20,1,0 %; macro KA0C05_TLEP$V_TLCNR_HALT_B = 128,21,1,0 %; macro KA0C05_TLEP$V_TLCNR_NRST = 128,30,1,0 %; macro KA0C05_TLEP$V_TLCNR_LOFE = 128,31,1,0 %; macro KA0C05_TLEP$b_f220 = 132,0,0,0 %; literal KA0C05_TLEP$s_f220 = 60; macro KA0C05_TLEP$L_TLVID = 192,0,32,0 %; macro KA0C05_TLEP$V_VID_A = 192,0,4,0 %; literal KA0C05_TLEP$S_VID_A = 4; macro KA0C05_TLEP$V_VID_B = 192,4,4,0 %; literal KA0C05_TLEP$S_VID_B = 4; macro KA0C05_TLEP$b_f230 = 196,0,0,0 %; literal KA0C05_TLEP$s_f230 = 316; macro KA0C05_TLEP$L_TLMMR0 = 512,0,32,0 %; macro KA0C05_TLEP$V_TLMMR0_INTMASK = 512,0,2,0 %; literal KA0C05_TLEP$S_TLMMR0_INTMASK = 2; macro KA0C05_TLEP$V_TLMMR0_ADRMASK = 512,4,4,0 %; literal KA0C05_TLEP$S_TLMMR0_ADRMASK = 4; macro KA0C05_TLEP$V_TLMMR0_INTLV = 512,8,3,0 %; literal KA0C05_TLEP$S_TLMMR0_INTLV = 3; macro KA0C05_TLEP$V_TLMMR0_SBANK = 512,11,1,0 %; macro KA0C05_TLEP$V_TLMMR0_ADDRESS = 512,12,14,0 %; literal KA0C05_TLEP$S_TLMMR0_ADDRESS = 14; macro KA0C05_TLEP$V_TLMMR0_VALID = 512,31,1,0 %; macro KA0C05_TLEP$b_f240 = 516,0,0,0 %; literal KA0C05_TLEP$s_f240 = 60; macro KA0C05_TLEP$L_TLMMR1 = 576,0,32,0 %; macro KA0C05_TLEP$V_TLMMR1_INTMASK = 576,0,2,0 %; literal KA0C05_TLEP$S_TLMMR1_INTMASK = 2; macro KA0C05_TLEP$V_TLMMR1_ADRMASK = 576,4,4,0 %; literal KA0C05_TLEP$S_TLMMR1_ADRMASK = 4; macro KA0C05_TLEP$V_TLMMR1_INTLV = 576,8,3,0 %; literal KA0C05_TLEP$S_TLMMR1_INTLV = 3; macro KA0C05_TLEP$V_TLMMR1_SBANK = 576,11,1,0 %; macro KA0C05_TLEP$V_TLMMR1_ADDRESS = 576,12,14,0 %; literal KA0C05_TLEP$S_TLMMR1_ADDRESS = 14; macro KA0C05_TLEP$V_TLMMR1_VALID = 576,31,1,0 %; macro KA0C05_TLEP$b_f250 = 580,0,0,0 %; literal KA0C05_TLEP$s_f250 = 60; macro KA0C05_TLEP$L_TLMMR2 = 640,0,32,0 %; macro KA0C05_TLEP$V_TLMMR2_INTMASK = 640,0,2,0 %; literal KA0C05_TLEP$S_TLMMR2_INTMASK = 2; macro KA0C05_TLEP$V_TLMMR2_ADRMASK = 640,4,4,0 %; literal KA0C05_TLEP$S_TLMMR2_ADRMASK = 4; macro KA0C05_TLEP$V_TLMMR2_INTLV = 640,8,3,0 %; literal KA0C05_TLEP$S_TLMMR2_INTLV = 3; macro KA0C05_TLEP$V_TLMMR2_SBANK = 640,11,1,0 %; macro KA0C05_TLEP$V_TLMMR2_ADDRESS = 640,12,14,0 %; literal KA0C05_TLEP$S_TLMMR2_ADDRESS = 14; macro KA0C05_TLEP$V_TLMMR2_VALID = 640,31,1,0 %; macro KA0C05_TLEP$b_f260 = 644,0,0,0 %; literal KA0C05_TLEP$s_f260 = 60; macro KA0C05_TLEP$L_TLMMR3 = 704,0,32,0 %; macro KA0C05_TLEP$V_TLMMR3_INTMASK = 704,0,2,0 %; literal KA0C05_TLEP$S_TLMMR3_INTMASK = 2; macro KA0C05_TLEP$V_TLMMR3_ADRMASK = 704,4,4,0 %; literal KA0C05_TLEP$S_TLMMR3_ADRMASK = 4; macro KA0C05_TLEP$V_TLMMR3_INTLV = 704,8,3,0 %; literal KA0C05_TLEP$S_TLMMR3_INTLV = 3; macro KA0C05_TLEP$V_TLMMR3_SBANK = 704,11,1,0 %; macro KA0C05_TLEP$V_TLMMR3_ADDRESS = 704,12,14,0 %; literal KA0C05_TLEP$S_TLMMR3_ADDRESS = 14; macro KA0C05_TLEP$V_TLMMR3_VALID = 704,31,1,0 %; macro KA0C05_TLEP$b_f270 = 708,0,0,0 %; literal KA0C05_TLEP$s_f270 = 60; macro KA0C05_TLEP$L_TLMMR4 = 768,0,32,0 %; macro KA0C05_TLEP$V_TLMMR4_INTMASK = 768,0,2,0 %; literal KA0C05_TLEP$S_TLMMR4_INTMASK = 2; macro KA0C05_TLEP$V_TLMMR4_ADRMASK = 768,4,4,0 %; literal KA0C05_TLEP$S_TLMMR4_ADRMASK = 4; macro KA0C05_TLEP$V_TLMMR4_INTLV = 768,8,3,0 %; literal KA0C05_TLEP$S_TLMMR4_INTLV = 3; macro KA0C05_TLEP$V_TLMMR4_SBANK = 768,11,1,0 %; macro KA0C05_TLEP$V_TLMMR4_ADDRESS = 768,12,14,0 %; literal KA0C05_TLEP$S_TLMMR4_ADDRESS = 14; macro KA0C05_TLEP$V_TLMMR4_VALID = 768,31,1,0 %; macro KA0C05_TLEP$b_f280 = 772,0,0,0 %; literal KA0C05_TLEP$s_f280 = 60; macro KA0C05_TLEP$L_TLMMR5 = 832,0,32,0 %; macro KA0C05_TLEP$V_TLMMR5_INTMASK = 832,0,2,0 %; literal KA0C05_TLEP$S_TLMMR5_INTMASK = 2; macro KA0C05_TLEP$V_TLMMR5_ADRMASK = 832,4,4,0 %; literal KA0C05_TLEP$S_TLMMR5_ADRMASK = 4; macro KA0C05_TLEP$V_TLMMR5_INTLV = 832,8,3,0 %; literal KA0C05_TLEP$S_TLMMR5_INTLV = 3; macro KA0C05_TLEP$V_TLMMR5_SBANK = 832,11,1,0 %; macro KA0C05_TLEP$V_TLMMR5_ADDRESS = 832,12,14,0 %; literal KA0C05_TLEP$S_TLMMR5_ADDRESS = 14; macro KA0C05_TLEP$V_TLMMR5_VALID = 832,31,1,0 %; macro KA0C05_TLEP$b_f290 = 836,0,0,0 %; literal KA0C05_TLEP$s_f290 = 60; macro KA0C05_TLEP$L_TLMMR6 = 896,0,32,0 %; macro KA0C05_TLEP$V_TLMMR6_INTMASK = 896,0,2,0 %; literal KA0C05_TLEP$S_TLMMR6_INTMASK = 2; macro KA0C05_TLEP$V_TLMMR6_ADRMASK = 896,4,4,0 %; literal KA0C05_TLEP$S_TLMMR6_ADRMASK = 4; macro KA0C05_TLEP$V_TLMMR6_INTLV = 896,8,3,0 %; literal KA0C05_TLEP$S_TLMMR6_INTLV = 3; macro KA0C05_TLEP$V_TLMMR6_SBANK = 896,11,1,0 %; macro KA0C05_TLEP$V_TLMMR6_ADDRESS = 896,12,14,0 %; literal KA0C05_TLEP$S_TLMMR6_ADDRESS = 14; macro KA0C05_TLEP$V_TLMMR6_VALID = 896,31,1,0 %; macro KA0C05_TLEP$b_fill300 = 900,0,0,0 %; literal KA0C05_TLEP$s_fill300 = 60; macro KA0C05_TLEP$L_TLMMR7 = 960,0,32,0 %; macro KA0C05_TLEP$V_TLMMR7_INTMASK = 960,0,2,0 %; literal KA0C05_TLEP$S_TLMMR7_INTMASK = 2; macro KA0C05_TLEP$V_TLMMR7_ADRMASK = 960,4,4,0 %; literal KA0C05_TLEP$S_TLMMR7_ADRMASK = 4; macro KA0C05_TLEP$V_TLMMR7_INTLV = 960,8,3,0 %; literal KA0C05_TLEP$S_TLMMR7_INTLV = 3; macro KA0C05_TLEP$V_TLMMR7_SBANK = 960,11,1,0 %; macro KA0C05_TLEP$V_TLMMR7_ADDRESS = 960,12,14,0 %; literal KA0C05_TLEP$S_TLMMR7_ADDRESS = 14; macro KA0C05_TLEP$V_TLMMR7_VALID = 960,31,1,0 %; macro KA0C05_TLEP$b_fill310 = 964,0,0,0 %; literal KA0C05_TLEP$s_fill310 = 700; macro KA0C05_TLEP$L_TLESR0 = 1664,0,32,0 %; macro KA0C05_TLEP$V_TLESR0_SYND0 = 1664,0,8,0 %; literal KA0C05_TLEP$S_TLESR0_SYND0 = 8; macro KA0C05_TLEP$V_TLESR0_SYND1 = 1664,8,8,0 %; literal KA0C05_TLEP$S_TLESR0_SYND1 = 8; macro KA0C05_TLEP$V_TLESR0_TDE = 1664,16,1,0 %; macro KA0C05_TLEP$V_TLESR0_TCE = 1664,17,1,0 %; macro KA0C05_TLEP$V_TLESR0_DVTCE = 1664,18,1,0 %; macro KA0C05_TLEP$V_TLESR0_UECC = 1664,19,1,0 %; macro KA0C05_TLEP$V_TLESR0_CWECC = 1664,20,1,0 %; macro KA0C05_TLEP$V_TLESR0_CRECC = 1664,21,1,0 %; macro KA0C05_TLEP$V_TLESR0_CPU0 = 1664,22,1,0 %; macro KA0C05_TLEP$V_TLESR0_CPU1 = 1664,23,1,0 %; macro KA0C05_TLEP$V_TLESR0_LOFSYN = 1664,31,1,0 %; macro KA0C05_TLEP$b_fill320 = 1668,0,0,0 %; literal KA0C05_TLEP$s_fill320 = 60; macro KA0C05_TLEP$L_TLESR1 = 1728,0,32,0 %; macro KA0C05_TLEP$V_TLESR1_SYND0 = 1728,0,8,0 %; literal KA0C05_TLEP$S_TLESR1_SYND0 = 8; macro KA0C05_TLEP$V_TLESR1_SYND1 = 1728,8,8,0 %; literal KA0C05_TLEP$S_TLESR1_SYND1 = 8; macro KA0C05_TLEP$V_TLESR1_TDE = 1728,16,1,0 %; macro KA0C05_TLEP$V_TLESR1_TCE = 1728,17,1,0 %; macro KA0C05_TLEP$V_TLESR1_DVTCE = 1728,18,1,0 %; macro KA0C05_TLEP$V_TLESR1_UECC = 1728,19,1,0 %; macro KA0C05_TLEP$V_TLESR1_CWECC = 1728,20,1,0 %; macro KA0C05_TLEP$V_TLESR1_CRECC = 1728,21,1,0 %; macro KA0C05_TLEP$V_TLESR1_CPU0 = 1728,22,1,0 %; macro KA0C05_TLEP$V_TLESR1_CPU1 = 1728,23,1,0 %; macro KA0C05_TLEP$V_TLESR1_LOFSYN = 1728,31,1,0 %; macro KA0C05_TLEP$b_fill330 = 1732,0,0,0 %; literal KA0C05_TLEP$s_fill330 = 60; macro KA0C05_TLEP$L_TLESR2 = 1792,0,32,0 %; macro KA0C05_TLEP$V_TLESR2_SYND0 = 1792,0,8,0 %; literal KA0C05_TLEP$S_TLESR2_SYND0 = 8; macro KA0C05_TLEP$V_TLESR2_SYND1 = 1792,8,8,0 %; literal KA0C05_TLEP$S_TLESR2_SYND1 = 8; macro KA0C05_TLEP$V_TLESR2_TDE = 1792,16,1,0 %; macro KA0C05_TLEP$V_TLESR2_TCE = 1792,17,1,0 %; macro KA0C05_TLEP$V_TLESR2_DVTCE = 1792,18,1,0 %; macro KA0C05_TLEP$V_TLESR2_UECC = 1792,19,1,0 %; macro KA0C05_TLEP$V_TLESR2_CWECC = 1792,20,1,0 %; macro KA0C05_TLEP$V_TLESR2_CRECC = 1792,21,1,0 %; macro KA0C05_TLEP$V_TLESR2_CPU0 = 1792,22,1,0 %; macro KA0C05_TLEP$V_TLESR2_CPU1 = 1792,23,1,0 %; macro KA0C05_TLEP$V_TLESR2_LOFSYN = 1792,31,1,0 %; macro KA0C05_TLEP$b_fill340 = 1796,0,0,0 %; literal KA0C05_TLEP$s_fill340 = 60; macro KA0C05_TLEP$L_TLESR3 = 1856,0,32,0 %; macro KA0C05_TLEP$V_TLESR3_SYND0 = 1856,0,8,0 %; literal KA0C05_TLEP$S_TLESR3_SYND0 = 8; macro KA0C05_TLEP$V_TLESR3_SYND1 = 1856,8,8,0 %; literal KA0C05_TLEP$S_TLESR3_SYND1 = 8; macro KA0C05_TLEP$V_TLESR3_TDE = 1856,16,1,0 %; macro KA0C05_TLEP$V_TLESR3_TCE = 1856,17,1,0 %; macro KA0C05_TLEP$V_TLESR3_DVTCE = 1856,18,1,0 %; macro KA0C05_TLEP$V_TLESR3_UECC = 1856,19,1,0 %; macro KA0C05_TLEP$V_TLESR3_CWECC = 1856,20,1,0 %; macro KA0C05_TLEP$V_TLESR3_CRECC = 1856,21,1,0 %; macro KA0C05_TLEP$V_TLESR3_CPU0 = 1856,22,1,0 %; macro KA0C05_TLEP$V_TLESR3_CPU1 = 1856,23,1,0 %; macro KA0C05_TLEP$V_TLESR3_LOFSYN = 1856,31,1,0 %; macro KA0C05_TLEP$b_fill350 = 1860,0,0,0 %; literal KA0C05_TLEP$s_fill350 = 2236; macro KA0C05_TLEP$L_TLDIAG = 4096,0,32,0 %; macro KA0C05_TLEP$V_TLDIAG_FRIGN = 4096,0,1,0 %; macro KA0C05_TLEP$V_TLDIAG_DTWR = 4096,1,1,0 %; macro KA0C05_TLEP$V_TLDIAG_DTRD = 4096,2,1,0 %; macro KA0C05_TLEP$V_TLDIAG_DTCP = 4096,3,1,0 %; macro KA0C05_TLEP$V_TLDIAG_FVW = 4096,4,1,0 %; macro KA0C05_TLEP$V_TLDIAG_FAE = 4096,5,1,0 %; macro KA0C05_TLEP$V_TLDIAG_FCBE = 4096,6,1,0 %; macro KA0C05_TLEP$V_TLDIAG_FDBE = 4096,7,1,0 %; macro KA0C05_TLEP$V_TLDIAG_FDE = 4096,8,4,0 %; literal KA0C05_TLEP$S_TLDIAG_FDE = 4; macro KA0C05_TLEP$V_TLDIAG_FTW = 4096,12,1,0 %; macro KA0C05_TLEP$V_TLDIAG_ASRT_FLT = 4096,13,1,0 %; macro KA0C05_TLEP$V_TLDIAG_QWVAL_EN = 4096,14,1,0 %; macro KA0C05_TLEP$V_TLDIAG_GSLOW = 4096,15,1,0 %; macro KA0C05_TLEP$b_fill360 = 4100,0,0,0 %; literal KA0C05_TLEP$s_fill360 = 60; macro KA0C05_TLEP$L_TLDTAGD = 4160,0,32,0 %; macro KA0C05_TLEP$V_TLDTAGD_DTAG_PAR = 4160,0,1,0 %; macro KA0C05_TLEP$V_TLDTAGD_DTAG_DATA = 4160,1,19,0 %; literal KA0C05_TLEP$S_TLDTAGD_DTAG_DATA = 19; macro KA0C05_TLEP$b_fill370 = 4164,0,0,0 %; literal KA0C05_TLEP$s_fill370 = 60; macro KA0C05_TLEP$L_TLDTAGS = 4224,0,32,0 %; macro KA0C05_TLEP$V_TLDTAGS_STATPAR = 4224,0,1,0 %; macro KA0C05_TLEP$V_TLDTAGS_STATD = 4224,1,1,0 %; macro KA0C05_TLEP$V_TLDTAGS_STATS = 4224,2,1,0 %; macro KA0C05_TLEP$V_TLDTAGS_STATV = 4224,3,1,0 %; macro KA0C05_TLEP$b_fill380 = 4228,0,0,0 %; literal KA0C05_TLEP$s_fill380 = 60; macro KA0C05_TLEP$L_TLMCFG = 4288,0,32,0 %; macro KA0C05_TLEP$V_TLMCFG_CPU0DSBL = 4288,0,1,0 %; macro KA0C05_TLEP$V_TLMCFG_CPU1DSBL = 4288,1,1,0 %; macro KA0C05_TLEP$V_TLMCFG_BC_SIZE = 4288,2,2,0 %; literal KA0C05_TLEP$S_TLMCFG_BC_SIZE = 2; macro KA0C05_TLEP$V_TLMCFG_LO_EN = 4288,4,1,0 %; macro KA0C05_TLEP$V_TLMCFG_RM_SIZE = 4288,5,1,0 %; macro KA0C05_TLEP$V_TLMCFG_BCIDLE = 4288,6,4,0 %; literal KA0C05_TLEP$S_TLMCFG_BCIDLE = 4; macro KA0C05_TLEP$V_TLMCFG_CQ_ENTRY = 4288,10,3,0 %; literal KA0C05_TLEP$S_TLMCFG_CQ_ENTRY = 3; macro KA0C05_TLEP$V_TLMCFG_BQ_ENTRY = 4288,13,3,0 %; literal KA0C05_TLEP$S_TLMCFG_BQ_ENTRY = 3; macro KA0C05_TLEP$V_TLMCFG_SYS_DSBL = 4288,16,1,0 %; macro KA0C05_TLEP$V_TLMCFG_EV5_DSBL = 4288,17,1,0 %; macro KA0C05_TLEP$V_TLMCFG_FLT_DSBL = 4288,18,1,0 %; macro KA0C05_TLEP$b_fill390 = 4292,0,0,0 %; literal KA0C05_TLEP$s_fill390 = 60; macro KA0C05_TLEP$L_TLIMASK0 = 4352,0,32,0 %; macro KA0C05_TLEP$V_TLIMASK0_DUART0EN = 4352,0,1,0 %; macro KA0C05_TLEP$V_TLIMASK0_IPL14_EN = 4352,1,1,0 %; macro KA0C05_TLEP$V_TLIMASK0_IPL15_EN = 4352,2,1,0 %; macro KA0C05_TLEP$V_TLIMASK0_IPL16_EN = 4352,3,1,0 %; macro KA0C05_TLEP$V_TLIMASK0_IPL17_EN = 4352,4,1,0 %; macro KA0C05_TLEP$V_TLIMASK0_IP_EN = 4352,5,1,0 %; macro KA0C05_TLEP$V_TLIMASK0_INTIM_EN = 4352,6,1,0 %; macro KA0C05_TLEP$V_TLIMASK0_HALT_EN = 4352,7,1,0 %; macro KA0C05_TLEP$V_TLIMASK0_CP_EN = 4352,8,1,0 %; macro KA0C05_TLEP$b_fill400 = 4356,0,0,0 %; literal KA0C05_TLEP$s_fill400 = 60; macro KA0C05_TLEP$L_TLIMASK1 = 4416,0,32,0 %; macro KA0C05_TLEP$V_TLIMASK1_DUART0EN = 4416,0,1,0 %; macro KA0C05_TLEP$V_TLIMASK1_IPL14_EN = 4416,1,1,0 %; macro KA0C05_TLEP$V_TLIMASK1_IPL15_EN = 4416,2,1,0 %; macro KA0C05_TLEP$V_TLIMASK1_IPL16_EN = 4416,3,1,0 %; macro KA0C05_TLEP$V_TLIMASK1_IPL17_EN = 4416,4,1,0 %; macro KA0C05_TLEP$V_TLIMASK1_IP_EN = 4416,5,1,0 %; macro KA0C05_TLEP$V_TLIMASK1_INTIM_EN = 4416,6,1,0 %; macro KA0C05_TLEP$V_TLIMASK1_HALT_EN = 4416,7,1,0 %; macro KA0C05_TLEP$V_TLIMASK1_CP_EN = 4416,8,1,0 %; macro KA0C05_TLEP$b_fill410 = 4420,0,0,0 %; literal KA0C05_TLEP$s_fill410 = 60; macro KA0C05_TLEP$L_TLISUM0 = 4480,0,32,0 %; macro KA0C05_TLEP$V_TLISUM0_DUART0INT = 4480,0,1,0 %; macro KA0C05_TLEP$V_TLISUM0_IPL14_INT = 4480,1,1,0 %; macro KA0C05_TLEP$V_TLISUM0_IPL15_INT = 4480,2,1,0 %; macro KA0C05_TLEP$V_TLISUM0_IPL16_INT = 4480,3,1,0 %; macro KA0C05_TLEP$V_TLISUM0_IPL17_INT = 4480,4,1,0 %; macro KA0C05_TLEP$V_TLISUM0_IP_INT = 4480,5,1,0 %; macro KA0C05_TLEP$V_TLISUM0_INTIM_INT = 4480,6,1,0 %; macro KA0C05_TLEP$V_TLISUM0_IPL14 = 4480,7,5,0 %; literal KA0C05_TLEP$S_TLISUM0_IPL14 = 5; macro KA0C05_TLEP$V_TLISUM0_IPL15 = 4480,12,5,0 %; literal KA0C05_TLEP$S_TLISUM0_IPL15 = 5; macro KA0C05_TLEP$V_TLISUM0_IPL16 = 4480,17,5,0 %; literal KA0C05_TLEP$S_TLISUM0_IPL16 = 5; macro KA0C05_TLEP$V_TLISUM0_IPL17 = 4480,22,5,0 %; literal KA0C05_TLEP$S_TLISUM0_IPL17 = 5; macro KA0C05_TLEP$V_TLISUM0_CP_HALT = 4480,27,1,0 %; macro KA0C05_TLEP$V_TLISUM0_HALT = 4480,28,1,0 %; macro KA0C05_TLEP$b_fill420 = 4484,0,0,0 %; literal KA0C05_TLEP$s_fill420 = 60; macro KA0C05_TLEP$L_TLISUM1 = 4544,0,32,0 %; macro KA0C05_TLEP$V_TLISUM1_DUART0INT = 4544,0,1,0 %; macro KA0C05_TLEP$V_TLISUM1_IPL14_INT = 4544,1,1,0 %; macro KA0C05_TLEP$V_TLISUM1_IPL15_INT = 4544,2,1,0 %; macro KA0C05_TLEP$V_TLISUM1_IPL16_INT = 4544,3,1,0 %; macro KA0C05_TLEP$V_TLISUM1_IPL17_INT = 4544,4,1,0 %; macro KA0C05_TLEP$V_TLISUM1_IP_INT = 4544,5,1,0 %; macro KA0C05_TLEP$V_TLISUM1_INTIM_INT = 4544,6,1,0 %; macro KA0C05_TLEP$V_TLISUM1_IPL14 = 4544,7,5,0 %; literal KA0C05_TLEP$S_TLISUM1_IPL14 = 5; macro KA0C05_TLEP$V_TLISUM1_IPL15 = 4544,12,5,0 %; literal KA0C05_TLEP$S_TLISUM1_IPL15 = 5; macro KA0C05_TLEP$V_TLISUM1_IPL16 = 4544,17,5,0 %; literal KA0C05_TLEP$S_TLISUM1_IPL16 = 5; macro KA0C05_TLEP$V_TLISUM1_IPL17 = 4544,22,5,0 %; literal KA0C05_TLEP$S_TLISUM1_IPL17 = 5; macro KA0C05_TLEP$V_TLISUM1_CP_HALT = 4544,27,1,0 %; macro KA0C05_TLEP$V_TLISUM1_HALT = 4544,28,1,0 %; macro KA0C05_TLEP$b_fill430 = 4548,0,0,0 %; literal KA0C05_TLEP$s_fill430 = 60; macro KA0C05_TLEP$L_TLCON00 = 4608,0,32,0 %; macro KA0C05_TLEP$b_fill440 = 4612,0,0,0 %; literal KA0C05_TLEP$s_fill440 = 60; macro KA0C05_TLEP$L_TLCON00A = 4672,0,32,0 %; macro KA0C05_TLEP$b_fill450 = 4676,0,0,0 %; literal KA0C05_TLEP$s_fill450 = 60; macro KA0C05_TLEP$L_TLCON00B = 4736,0,32,0 %; macro KA0C05_TLEP$b_fill460 = 4740,0,0,0 %; literal KA0C05_TLEP$s_fill460 = 60; macro KA0C05_TLEP$L_TLCON00C = 4800,0,32,0 %; macro KA0C05_TLEP$b_fill470 = 4804,0,0,0 %; literal KA0C05_TLEP$s_fill470 = 60; macro KA0C05_TLEP$L_TLCON10 = 4864,0,32,0 %; macro KA0C05_TLEP$b_fill480 = 4868,0,0,0 %; literal KA0C05_TLEP$s_fill480 = 60; macro KA0C05_TLEP$L_TLCON10A = 4928,0,32,0 %; macro KA0C05_TLEP$b_fill490 = 4932,0,0,0 %; literal KA0C05_TLEP$s_fill490 = 60; macro KA0C05_TLEP$L_TLCON10B = 4992,0,32,0 %; macro KA0C05_TLEP$b_fill500 = 4996,0,0,0 %; literal KA0C05_TLEP$s_fill500 = 60; macro KA0C05_TLEP$L_TLCON10C = 5056,0,32,0 %; macro KA0C05_TLEP$b_fill510 = 5060,0,0,0 %; literal KA0C05_TLEP$s_fill510 = 60; macro KA0C05_TLEP$L_TLCON01 = 5120,0,32,0 %; macro KA0C05_TLEP$b_fill520 = 5124,0,0,0 %; literal KA0C05_TLEP$s_fill520 = 60; macro KA0C05_TLEP$L_TLCON11 = 5184,0,32,0 %; macro KA0C05_TLEP$b_fill530 = 5188,0,0,0 %; literal KA0C05_TLEP$s_fill530 = 188; macro KA0C05_TLEP$L_TLEPAERR = 5376,0,32,0 %; macro KA0C05_TLEP$V_TLEPAERR_E2MAPE0 = 5376,0,1,0 %; macro KA0C05_TLEP$V_TLEPAERR_E2MAPE1 = 5376,1,1,0 %; macro KA0C05_TLEP$V_TLEPAERR_M2AAPE0 = 5376,2,1,0 %; macro KA0C05_TLEP$V_TLEPAERR_M2AAPE1 = 5376,3,1,0 %; macro KA0C05_TLEP$V_TLEPAERR_DTDPE = 5376,4,1,0 %; macro KA0C05_TLEP$V_TLEPAERR_DTSPE = 5376,5,1,0 %; macro KA0C05_TLEP$V_TLEPAERR_D2ACPE = 5376,6,1,0 %; macro KA0C05_TLEP$V_TLEPAERR_SYSDERR = 5376,7,1,0 %; macro KA0C05_TLEP$V_TLEPAERR_SYSFLT = 5376,8,1,0 %; macro KA0C05_TLEP$V_TLEPAERR_RD_ERR = 5376,9,2,0 %; literal KA0C05_TLEP$S_TLEPAERR_RD_ERR = 2; macro KA0C05_TLEP$V_TLEPAERR_IBOXTO = 5376,11,2,0 %; literal KA0C05_TLEP$S_TLEPAERR_IBOXTO = 2; macro KA0C05_TLEP$V_TLEPAERR_RD_PEND = 5376,13,2,0 %; literal KA0C05_TLEP$S_TLEPAERR_RD_PEND = 2; macro KA0C05_TLEP$V_TLEPAERR_NXM = 5376,15,1,0 %; macro KA0C05_TLEP$V_TLEPAERR_NO_ACK = 5376,16,2,0 %; literal KA0C05_TLEP$S_TLEPAERR_NO_ACK = 2; macro KA0C05_TLEP$b_fill540 = 5380,0,0,0 %; literal KA0C05_TLEP$s_fill540 = 60; macro KA0C05_TLEP$L_TLEPDERR = 5440,0,32,0 %; macro KA0C05_TLEP$V_TLEPDERR_A2DCPE = 5440,0,1,0 %; macro KA0C05_TLEP$V_TLEPDERR_D2DCPE0 = 5440,1,1,0 %; macro KA0C05_TLEP$V_TLEPDERR_GBTO = 5440,2,1,0 %; macro KA0C05_TLEP$b_fill550 = 5444,0,0,0 %; literal KA0C05_TLEP$s_fill550 = 60; macro KA0C05_TLEP$L_TLEPMERR = 5504,0,32,0 %; macro KA0C05_TLEP$V_TLEPMERR_A2MAPE0 = 5504,0,1,0 %; macro KA0C05_TLEP$V_TLEPMERR_A2MAPE1 = 5504,1,1,0 %; macro KA0C05_TLEP$V_TLEPMERR_D2MCPE = 5504,2,1,0 %; macro KA0C05_TLEP$V_TLEPMERR_D2DCPE1 = 5504,3,1,0 %; macro KA0C05_TLEP$V_TLEPMERR_D2DCPE2 = 5504,4,1,0 %; macro KA0C05_TLEP$V_TLEPMERR_D2DCPE3 = 5504,5,1,0 %; macro KA0C05_TLEP$V_TLEPMERR_RSTSTAT = 5504,6,1,0 %; macro KA0C05_TLEP$b_fill560 = 5508,0,0,0 %; literal KA0C05_TLEP$s_fill560 = 60; macro KA0C05_TLEP$L_TLEP_VMG = 5568,0,32,0 %; macro KA0C05_TLEP$V_TLEP_VMG_5P = 5568,0,1,0 %; macro KA0C05_TLEP$V_TLEP_VMG_5M = 5568,1,1,0 %; macro KA0C05_TLEP$V_TLEP_VMG_3P = 5568,2,1,0 %; macro KA0C05_TLEP$V_TLEP_VMG_3M = 5568,3,1,0 %; macro KA0C05_TLEP$b_fill570 = 5572,0,0,0 %; literal KA0C05_TLEP$s_fill570 = 60; macro KA0C05_TLEP$L_TLDMCMD = 5632,0,32,0 %; macro KA0C05_TLEP$V_TLDMCMD_SIZE_512 = 5632,0,1,0 %; macro KA0C05_TLEP$V_TLDMCMD_SIZE_1K = 5632,1,1,0 %; macro KA0C05_TLEP$V_TLDMCMD_SIZE_2K = 5632,2,1,0 %; macro KA0C05_TLEP$V_TLDMCMD_SIZE_4K = 5632,3,1,0 %; macro KA0C05_TLEP$V_TLDMCMD_SIZE_8K = 5632,4,1,0 %; macro KA0C05_TLEP$V_TLDMCMD_CMD = 5632,8,2,0 %; literal KA0C05_TLEP$S_TLDMCMD_CMD = 2; macro KA0C05_TLEP$V_TLDMCMD_VALID = 5632,11,1,0 %; macro KA0C05_TLEP$V_TLDMCMD_RM_3 = 5632,12,1,0 %; macro KA0C05_TLEP$V_TLDMCMD_RM_4 = 5632,13,1,0 %; macro KA0C05_TLEP$V_TLDMCMD_RM_INLV = 5632,14,1,0 %; macro KA0C05_TLEP$V_TLDMCMD_CPU_ID = 5632,16,1,0 %; macro KA0C05_TLEP$V_TLDMCMD_IN_PROG = 5632,20,1,0 %; macro KA0C05_TLEP$V_TLDMCMD_DONE = 5632,21,1,0 %; macro KA0C05_TLEP$b_fill580 = 5636,0,0,0 %; literal KA0C05_TLEP$s_fill580 = 124; macro KA0C05_TLEP$L_TLDMADRA = 5760,0,32,0 %; macro KA0C05_TLEP$V_TLDMADRA_ADDR = 5760,0,30,0 %; literal KA0C05_TLEP$S_TLDMADRA_ADDR = 30; macro KA0C05_TLEP$b_fill590 = 5764,0,0,0 %; literal KA0C05_TLEP$s_fill590 = 60; macro KA0C05_TLEP$L_TLDMADRB = 5824,0,32,0 %; macro KA0C05_TLEP$V_TLDMADRB_ADDR = 5824,0,30,0 %; literal KA0C05_TLEP$S_TLDMADRB_ADDR = 30; macro KA0C05_TLEP$b_fill600 = 5828,0,0,0 %; literal KA0C05_TLEP$s_fill600 = 316; macro KA0C05_TLEP$L_TLPM_CMD = 6144,0,32,0 %; macro KA0C05_TLEP$V_TLPM_CMD_CPUNUM = 6144,0,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_SET_SEL = 6144,1,2,0 %; literal KA0C05_TLEP$S_TLPM_CMD_SET_SEL = 2; macro KA0C05_TLEP$V_TLPM_CMD_VALID = 6144,3,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_READ_SET = 6144,4,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_OVRF_EN = 6144,11,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_TOT_CYC = 6144,12,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_EV5_LAT = 6144,13,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_RD_LAT = 6144,14,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_SYS_OWN = 6144,15,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_f2 = 6144,16,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_LOCK = 6144,17,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_MB = 6144,18,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_SD_TOT = 6144,19,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_SD_ACK = 6144,20,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_RD_CSR = 6144,21,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_RD = 6144,22,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_RD_MOD = 6144,23,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_RD_STC = 6144,24,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_VIC = 6144,25,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_WR_CSR = 6144,26,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_WR = 6144,27,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_WR_LOCK = 6144,28,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_INVAL = 6144,29,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_SET_SHR = 6144,30,1,0 %; macro KA0C05_TLEP$V_TLPM_CMD_RD_DIRT = 6144,31,1,0 %; macro KA0C05_TLEP$b_fill610 = 6148,0,0,0 %; literal KA0C05_TLEP$s_fill610 = 60; macro KA0C05_TLEP$L_TLPM_TOT_CYCLES = 6208,0,32,0 %; macro KA0C05_TLEP$b_fill620 = 6212,0,0,0 %; literal KA0C05_TLEP$s_fill620 = 60; macro KA0C05_TLEP$L_TLPM_EV5_LAT = 6272,0,32,0 %; macro KA0C05_TLEP$b_fill630 = 6276,0,0,0 %; literal KA0C05_TLEP$s_fill630 = 60; macro KA0C05_TLEP$L_TLPM_READ_LAT = 6336,0,32,0 %; macro KA0C05_TLEP$b_fill640 = 6340,0,0,0 %; literal KA0C05_TLEP$s_fill640 = 60; macro KA0C05_TLEP$L_TLPM_OWNER = 6400,0,32,0 %; macro KA0C05_TLEP$b_fill650 = 6404,0,0,0 %; literal KA0C05_TLEP$s_fill650 = 60; macro KA0C05_TLEP$L_TLPM_SILO = 6464,0,32,0 %; macro KA0C05_TLEP$b_fill660 = 6468,0,0,0 %; literal KA0C05_TLEP$s_fill660 = 60; macro KA0C05_TLEP$L_TLPM_LOCK = 6528,0,32,0 %; macro KA0C05_TLEP$b_fill670 = 6532,0,0,0 %; literal KA0C05_TLEP$s_fill670 = 60; macro KA0C05_TLEP$L_TLPM_MB = 6592,0,32,0 %; macro KA0C05_TLEP$b_fill680 = 6596,0,0,0 %; literal KA0C05_TLEP$s_fill680 = 60; macro KA0C05_TLEP$L_TLPM_SD = 6656,0,32,0 %; macro KA0C05_TLEP$b_fill690 = 6660,0,0,0 %; literal KA0C05_TLEP$s_fill690 = 60; macro KA0C05_TLEP$L_TLPM_SD_ACK = 6720,0,32,0 %; macro KA0C05_TLEP$b_fill700 = 6724,0,0,0 %; literal KA0C05_TLEP$s_fill700 = 60; macro KA0C05_TLEP$L_TLPM_RD_CSR = 6784,0,32,0 %; macro KA0C05_TLEP$b_fill710 = 6788,0,0,0 %; literal KA0C05_TLEP$s_fill710 = 60; macro KA0C05_TLEP$L_TLPM_RD_MISS = 6848,0,32,0 %; macro KA0C05_TLEP$b_fill720 = 6852,0,0,0 %; literal KA0C05_TLEP$s_fill720 = 60; macro KA0C05_TLEP$L_TLPM_RD_MOD = 6912,0,32,0 %; macro KA0C05_TLEP$b_fill730 = 6916,0,0,0 %; literal KA0C05_TLEP$s_fill730 = 60; macro KA0C05_TLEP$L_TLPM_RD_STC = 6976,0,32,0 %; macro KA0C05_TLEP$b_fill740 = 6980,0,0,0 %; literal KA0C05_TLEP$s_fill740 = 60; macro KA0C05_TLEP$L_TLPM_VICTIM = 7040,0,32,0 %; macro KA0C05_TLEP$b_fill750 = 7044,0,0,0 %; literal KA0C05_TLEP$s_fill750 = 60; macro KA0C05_TLEP$L_TLPM_WR_CSR = 7104,0,32,0 %; macro KA0C05_TLEP$b_fill760 = 7108,0,0,0 %; literal KA0C05_TLEP$s_fill760 = 60; macro KA0C05_TLEP$L_TLPM_WR = 7168,0,32,0 %; macro KA0C05_TLEP$b_fill770 = 7172,0,0,0 %; literal KA0C05_TLEP$s_fill770 = 60; macro KA0C05_TLEP$L_TLPM_WR_LOCK = 7232,0,32,0 %; macro KA0C05_TLEP$b_fill780 = 7236,0,0,0 %; literal KA0C05_TLEP$s_fill780 = 60; macro KA0C05_TLEP$L_TLPM_INVAL = 7296,0,32,0 %; macro KA0C05_TLEP$b_fill790 = 7300,0,0,0 %; literal KA0C05_TLEP$s_fill790 = 60; macro KA0C05_TLEP$L_TLPM_S_SHRD = 7360,0,32,0 %; macro KA0C05_TLEP$b_fill800 = 7364,0,0,0 %; literal KA0C05_TLEP$s_fill800 = 60; macro KA0C05_TLEP$L_TLPM_RD = 7424,0,32,0 %; macro KA0C05_TLEP$b_fill810 = 7428,0,0,0 %; literal KA0C05_TLEP$s_fill810 = 60; macro KA0C05_TLEP$L_TLPM_ASILO = 7488,0,32,0 %; macro KA0C05_TLEP$b_fill820 = 7492,0,0,0 %; literal KA0C05_TLEP$s_fill820 = 60; macro KA0C05_TLEP$L_RM_REG0A = 7552,0,32,0 %; macro KA0C05_TLEP$V_RM_REG0A_AEXT = 7552,0,4,0 %; literal KA0C05_TLEP$S_RM_REG0A_AEXT = 4; macro KA0C05_TLEP$V_RM_REG0A_BADDR = 7552,8,20,0 %; literal KA0C05_TLEP$S_RM_REG0A_BADDR = 20; macro KA0C05_TLEP$V_RM_REG0A_VALID = 7552,31,1,0 %; macro KA0C05_TLEP$b_fill830 = 7556,0,0,0 %; literal KA0C05_TLEP$s_fill830 = 60; macro KA0C05_TLEP$L_RM_REG0B = 7616,0,32,0 %; macro KA0C05_TLEP$V_RM_REG0B_AEXT = 7616,0,4,0 %; literal KA0C05_TLEP$S_RM_REG0B_AEXT = 4; macro KA0C05_TLEP$V_RM_REG0B_BADDR = 7616,8,20,0 %; literal KA0C05_TLEP$S_RM_REG0B_BADDR = 20; macro KA0C05_TLEP$V_RM_REG0B_VALID = 7616,31,1,0 %; macro KA0C05_TLEP$b_fill840 = 7620,0,0,0 %; literal KA0C05_TLEP$s_fill840 = 60; macro KA0C05_TLEP$L_RM_REG1A = 7680,0,32,0 %; macro KA0C05_TLEP$V_RM_REG1A_AEXT = 7680,0,4,0 %; literal KA0C05_TLEP$S_RM_REG1A_AEXT = 4; macro KA0C05_TLEP$V_RM_REG1A_BADDR = 7680,8,20,0 %; literal KA0C05_TLEP$S_RM_REG1A_BADDR = 20; macro KA0C05_TLEP$V_RM_REG1A_VALID = 7680,31,1,0 %; macro KA0C05_TLEP$b_fill850 = 7684,0,0,0 %; literal KA0C05_TLEP$s_fill850 = 60; macro KA0C05_TLEP$L_RM_REG1B = 7744,0,32,0 %; macro KA0C05_TLEP$V_RM_REG1B_AEXT = 7744,0,4,0 %; literal KA0C05_TLEP$S_RM_REG1B_AEXT = 4; macro KA0C05_TLEP$V_RM_REG1B_BADDR = 7744,8,20,0 %; literal KA0C05_TLEP$S_RM_REG1B_BADDR = 20; macro KA0C05_TLEP$V_RM_REG1B_VALID = 7744,31,1,0 %; macro KA0C05_TLEP$b_fill860 = 7748,0,0,0 %; literal KA0C05_TLEP$s_fill860 = 316; literal KA0C08_TLEP$M_TLDEV_DTYPE = %X'FFFF'; literal KA0C08_TLEP$M_TLDEV_SWREV = %X'FF0000'; literal KA0C08_TLEP$M_TLDEV_HWREV = %X'FF000000'; literal KA0C08_TLEP$M_TLBER_ATCE = %X'1'; literal KA0C08_TLEP$M_TLBER_APE = %X'2'; literal KA0C08_TLEP$M_TLBER_BBE = %X'4'; literal KA0C08_TLEP$M_TLBER_LKTO = %X'8'; literal KA0C08_TLEP$M_TLBER_NAE = %X'10'; literal KA0C08_TLEP$M_TLBER_RTCE = %X'20'; literal KA0C08_TLEP$M_TLBER_ACKTCE = %X'40'; literal KA0C08_TLEP$M_TLBER_MMRE = %X'80'; literal KA0C08_TLEP$M_TLBER_FNAE = %X'100'; literal KA0C08_TLEP$M_TLBER_REQDE = %X'200'; literal KA0C08_TLEP$M_TLBER_ATDE = %X'400'; literal KA0C08_TLEP$M_TLBER_UDE = %X'10000'; literal KA0C08_TLEP$M_TLBER_CWDE = %X'20000'; literal KA0C08_TLEP$M_TLBER_CRDE = %X'40000'; literal KA0C08_TLEP$M_TLBER_DS0 = %X'100000'; literal KA0C08_TLEP$M_TLBER_DS1 = %X'200000'; literal KA0C08_TLEP$M_TLBER_DS2 = %X'400000'; literal KA0C08_TLEP$M_TLBER_DS3 = %X'800000'; literal KA0C08_TLEP$M_TLBER_DTDE = %X'1000000'; literal KA0C08_TLEP$M_TLBER_FDTCE = %X'2000000'; literal KA0C08_TLEP$M_TLBER_UACKE = %X'4000000'; literal KA0C08_TLEP$M_TLBER_ABTCE = %X'8000000'; literal KA0C08_TLEP$M_TLBER_DCTCE = %X'10000000'; literal KA0C08_TLEP$M_TLBER_SEQE = %X'20000000'; literal KA0C08_TLEP$M_TLBER_DSE = %X'40000000'; literal KA0C08_TLEP$M_TLBER_DTO = %X'80000000'; literal KA0C08_TLEP$M_TLCNR_CWDD = %X'1'; literal KA0C08_TLEP$M_TLCNR_CRDD = %X'2'; literal KA0C08_TLEP$M_TLCNR_DTOD = %X'8'; literal KA0C08_TLEP$M_TLCNR_NODE_ID = %X'F0'; literal KA0C08_TLEP$M_TLCNR_VCNT = %X'F00'; literal KA0C08_TLEP$M_TLCNR_STF_A = %X'1000'; literal KA0C08_TLEP$M_TLCNR_STF_B = %X'2000'; literal KA0C08_TLEP$M_TLCNR_HALT_A = %X'100000'; literal KA0C08_TLEP$M_TLCNR_HALT_B = %X'200000'; literal KA0C08_TLEP$M_TLCNR_NRST = %X'40000000'; literal KA0C08_TLEP$M_TLCNR_LOFE = %X'80000000'; literal KA0C08_TLEP$M_VID_A = %X'F'; literal KA0C08_TLEP$M_VID_B = %X'F0'; literal KA0C08_TLEP$M_TLMMR0_INTMASK = %X'3'; literal KA0C08_TLEP$M_TLMMR0_ADRMASK = %X'F0'; literal KA0C08_TLEP$M_TLMMR0_INTLV = %X'700'; literal KA0C08_TLEP$M_TLMMR0_SBANK = %X'800'; literal KA0C08_TLEP$M_TLMMR0_ADDRESS = %X'3FFF000'; literal KA0C08_TLEP$M_TLMMR0_VALID = %X'80000000'; literal KA0C08_TLEP$M_TLMMR1_INTMASK = %X'3'; literal KA0C08_TLEP$M_TLMMR1_ADRMASK = %X'F0'; literal KA0C08_TLEP$M_TLMMR1_INTLV = %X'700'; literal KA0C08_TLEP$M_TLMMR1_SBANK = %X'800'; literal KA0C08_TLEP$M_TLMMR1_ADDRESS = %X'3FFF000'; literal KA0C08_TLEP$M_TLMMR1_VALID = %X'80000000'; literal KA0C08_TLEP$M_TLMMR2_INTMASK = %X'3'; literal KA0C08_TLEP$M_TLMMR2_ADRMASK = %X'F0'; literal KA0C08_TLEP$M_TLMMR2_INTLV = %X'700'; literal KA0C08_TLEP$M_TLMMR2_SBANK = %X'800'; literal KA0C08_TLEP$M_TLMMR2_ADDRESS = %X'3FFF000'; literal KA0C08_TLEP$M_TLMMR2_VALID = %X'80000000'; literal KA0C08_TLEP$M_TLMMR3_INTMASK = %X'3'; literal KA0C08_TLEP$M_TLMMR3_ADRMASK = %X'F0'; literal KA0C08_TLEP$M_TLMMR3_INTLV = %X'700'; literal KA0C08_TLEP$M_TLMMR3_SBANK = %X'800'; literal KA0C08_TLEP$M_TLMMR3_ADDRESS = %X'3FFF000'; literal KA0C08_TLEP$M_TLMMR3_VALID = %X'80000000'; literal KA0C08_TLEP$M_TLMMR4_INTMASK = %X'3'; literal KA0C08_TLEP$M_TLMMR4_ADRMASK = %X'F0'; literal KA0C08_TLEP$M_TLMMR4_INTLV = %X'700'; literal KA0C08_TLEP$M_TLMMR4_SBANK = %X'800'; literal KA0C08_TLEP$M_TLMMR4_ADDRESS = %X'3FFF000'; literal KA0C08_TLEP$M_TLMMR4_VALID = %X'80000000'; literal KA0C08_TLEP$M_TLMMR5_INTMASK = %X'3'; literal KA0C08_TLEP$M_TLMMR5_ADRMASK = %X'F0'; literal KA0C08_TLEP$M_TLMMR5_INTLV = %X'700'; literal KA0C08_TLEP$M_TLMMR5_SBANK = %X'800'; literal KA0C08_TLEP$M_TLMMR5_ADDRESS = %X'3FFF000'; literal KA0C08_TLEP$M_TLMMR5_VALID = %X'80000000'; literal KA0C08_TLEP$M_TLMMR6_INTMASK = %X'3'; literal KA0C08_TLEP$M_TLMMR6_ADRMASK = %X'F0'; literal KA0C08_TLEP$M_TLMMR6_INTLV = %X'700'; literal KA0C08_TLEP$M_TLMMR6_SBANK = %X'800'; literal KA0C08_TLEP$M_TLMMR6_ADDRESS = %X'3FFF000'; literal KA0C08_TLEP$M_TLMMR6_VALID = %X'80000000'; literal KA0C08_TLEP$M_TLMMR7_INTMASK = %X'3'; literal KA0C08_TLEP$M_TLMMR7_ADRMASK = %X'F0'; literal KA0C08_TLEP$M_TLMMR7_INTLV = %X'700'; literal KA0C08_TLEP$M_TLMMR7_SBANK = %X'800'; literal KA0C08_TLEP$M_TLMMR7_ADDRESS = %X'3FFF000'; literal KA0C08_TLEP$M_TLMMR7_VALID = %X'80000000'; literal KA0C08_TLEP$M_TLESR0_SYND0 = %X'FF'; literal KA0C08_TLEP$M_TLESR0_SYND1 = %X'FF00'; literal KA0C08_TLEP$M_TLESR0_TDE = %X'10000'; literal KA0C08_TLEP$M_TLESR0_TCE = %X'20000'; literal KA0C08_TLEP$M_TLESR0_DVTCE = %X'40000'; literal KA0C08_TLEP$M_TLESR0_UECC = %X'80000'; literal KA0C08_TLEP$M_TLESR0_CWECC = %X'100000'; literal KA0C08_TLEP$M_TLESR0_CRECC = %X'200000'; literal KA0C08_TLEP$M_TLESR0_CPU0 = %X'400000'; literal KA0C08_TLEP$M_TLESR0_CPU1 = %X'800000'; literal KA0C08_TLEP$M_TLESR0_LOFSYN = %X'80000000'; literal KA0C08_TLEP$M_TLESR1_SYND0 = %X'FF'; literal KA0C08_TLEP$M_TLESR1_SYND1 = %X'FF00'; literal KA0C08_TLEP$M_TLESR1_TDE = %X'10000'; literal KA0C08_TLEP$M_TLESR1_TCE = %X'20000'; literal KA0C08_TLEP$M_TLESR1_DVTCE = %X'40000'; literal KA0C08_TLEP$M_TLESR1_UECC = %X'80000'; literal KA0C08_TLEP$M_TLESR1_CWECC = %X'100000'; literal KA0C08_TLEP$M_TLESR1_CRECC = %X'200000'; literal KA0C08_TLEP$M_TLESR1_CPU0 = %X'400000'; literal KA0C08_TLEP$M_TLESR1_CPU1 = %X'800000'; literal KA0C08_TLEP$M_TLESR1_LOFSYN = %X'80000000'; literal KA0C08_TLEP$M_TLESR2_SYND0 = %X'FF'; literal KA0C08_TLEP$M_TLESR2_SYND1 = %X'FF00'; literal KA0C08_TLEP$M_TLESR2_TDE = %X'10000'; literal KA0C08_TLEP$M_TLESR2_TCE = %X'20000'; literal KA0C08_TLEP$M_TLESR2_DVTCE = %X'40000'; literal KA0C08_TLEP$M_TLESR2_UECC = %X'80000'; literal KA0C08_TLEP$M_TLESR2_CWECC = %X'100000'; literal KA0C08_TLEP$M_TLESR2_CRECC = %X'200000'; literal KA0C08_TLEP$M_TLESR2_CPU0 = %X'400000'; literal KA0C08_TLEP$M_TLESR2_CPU1 = %X'800000'; literal KA0C08_TLEP$M_TLESR2_LOFSYN = %X'80000000'; literal KA0C08_TLEP$M_TLESR3_SYND0 = %X'FF'; literal KA0C08_TLEP$M_TLESR3_SYND1 = %X'FF00'; literal KA0C08_TLEP$M_TLESR3_TDE = %X'10000'; literal KA0C08_TLEP$M_TLESR3_TCE = %X'20000'; literal KA0C08_TLEP$M_TLESR3_DVTCE = %X'40000'; literal KA0C08_TLEP$M_TLESR3_UECC = %X'80000'; literal KA0C08_TLEP$M_TLESR3_CWECC = %X'100000'; literal KA0C08_TLEP$M_TLESR3_CRECC = %X'200000'; literal KA0C08_TLEP$M_TLESR3_CPU0 = %X'400000'; literal KA0C08_TLEP$M_TLESR3_CPU1 = %X'800000'; literal KA0C08_TLEP$M_TLESR3_LOFSYN = %X'80000000'; literal KA0C08_TLEP$M_TLMODCFG0_FRIGN = %X'1'; literal KA0C08_TLEP$M_TLMODCFG0_FDE0 = %X'2'; literal KA0C08_TLEP$M_TLMODCFG0_FDE1 = %X'4'; literal KA0C08_TLEP$M_TLMODCFG0_P1_UDE = %X'8'; literal KA0C08_TLEP$M_TLMODCFG0_P1_CRDE = %X'10'; literal KA0C08_TLEP$M_TLMODCFG0_DLY_IN = %X'20'; literal KA0C08_TLEP$M_TLMODCFG0_DLY_OUT = %X'40'; literal KA0C08_TLEP$M_TLMODCFG0_DPQ_MAX = %X'380'; literal KA0C08_TLEP$M_TLMODCFG0_MMRE_DS = %X'400'; literal KA0C08_TLEP$M_TLMODCFG0_FASTFLS = %X'800'; literal KA0C08_TLEP$M_TLMODCFG0_DELAY_A = %X'1000'; literal KA0C08_TLEP$M_TLMODCFG0_ILGLCSR = %X'2000'; literal KA0C08_TLEP$M_TLMODCFG0_E_SLOWR = %X'4000'; literal KA0C08_TLEP$M_TLMODCFG0_ASRT_FT = %X'8000'; literal KA0C08_TLEP$M_TLMODCFG0_DTAG_PE = %X'10000'; literal KA0C08_TLEP$M_TLMODCFG0_DTAG0_D = %X'20000'; literal KA0C08_TLEP$M_TLMODCFG0_DTAG1_D = %X'40000'; literal KA0C08_TLEP$M_TLMODCFG0_D_WRAP = %X'80000'; literal KA0C08_TLEP$M_TLMODCFG0_BQ_MAX = %X'700000'; literal KA0C08_TLEP$M_TLMODCFG0_BC_SIZE = %X'1800000'; literal KA0C08_TLEP$M_TLMODCFG0_FDE_CMD = %X'1E000000'; literal KA0C08_TLEP$M_TLMODCFG0_FSBE = %X'20000000'; literal KA0C08_TLEP$M_TLMODCFG0_FDE2 = %X'40000000'; literal KA0C08_TLEP$M_TLMODCFG0_FDE3 = %X'80000000'; literal KA0C08_TLEP$M_TLDTAGDATA_PAR = %X'1'; literal KA0C08_TLEP$M_TLDTAGDATA_DATA = %X'3FFFE'; literal KA0C08_TLEP$M_TLDTAGADDR_ADDR = %X'3FFFF'; literal KA0C08_TLEP$M_TLDTAGADDR_CPU_SL = %X'1000000'; literal KA0C08_TLEP$M_TLMODCFG1_OVRTK_E = %X'1'; literal KA0C08_TLEP$M_TLMODCFG1_P0_RID = %X'E'; literal KA0C08_TLEP$M_TLMODCFG1_P1_RID = %X'70'; literal KA0C08_TLEP$M_TLMODCFG1_MBPR_RY = %X'180'; literal KA0C08_TLEP$M_TLMODCFG1_FAULT_D = %X'200'; literal KA0C08_TLEP$M_TLMODCFG1_FSTRQ_D = %X'400'; literal KA0C08_TLEP$M_TLMODCFG1_P0_RQ_D = %X'800'; literal KA0C08_TLEP$M_TLMODCFG1_P1_RQ_D = %X'1000'; literal KA0C08_TLEP$M_TLMODCFG1_D_PROBE = %X'6000'; literal KA0C08_TLEP$M_TLMODCFG1_FSTPTH = %X'8000'; literal KA0C08_TLEP$M_TLMODCFG1_DLSB_PR = %X'10000'; literal KA0C08_TLEP$M_TLMODCFG1_VIC_SKP = %X'20000'; literal KA0C08_TLEP$M_TLMODCFG1_FRCE_SQ = %X'40000'; literal KA0C08_TLEP$M_TLMODCFG1_DB_BUB = %X'80000'; literal KA0C08_TLEP$M_TLMODCFG1_FST_VQ = %X'100000'; literal KA0C08_TLEP$M_TLMODCFG1_FST_PRQ = %X'200000'; literal KA0C08_TLEP$M_TLMODCFG1_BUSWRTE = %X'400000'; literal KA0C08_TLEP$M_TLMODCFG1_FST_WRT = %X'800000'; literal KA0C08_TLEP$M_TLMODCFG1_FRC_SHR = %X'1000000'; literal KA0C08_TLEP$M_TLMODCFG1_VQRBCTL = %X'2000000'; literal KA0C08_TLEP$M_TLMODCFG1_CSR_SIZ = %X'4000000'; literal KA0C08_TLEP$M_TLIMASK0_DUART0EN = %X'1'; literal KA0C08_TLEP$M_TLIMASK0_IPL14_EN = %X'2'; literal KA0C08_TLEP$M_TLIMASK0_IPL15_EN = %X'4'; literal KA0C08_TLEP$M_TLIMASK0_IPL16_EN = %X'8'; literal KA0C08_TLEP$M_TLIMASK0_IPL17_EN = %X'10'; literal KA0C08_TLEP$M_TLIMASK0_IP_EN = %X'20'; literal KA0C08_TLEP$M_TLIMASK0_INTIM_EN = %X'40'; literal KA0C08_TLEP$M_TLIMASK0_HALT_EN = %X'80'; literal KA0C08_TLEP$M_TLIMASK0_CP_EN = %X'100'; literal KA0C08_TLEP$M_TLIMASK1_DUART0EN = %X'1'; literal KA0C08_TLEP$M_TLIMASK1_IPL14_EN = %X'2'; literal KA0C08_TLEP$M_TLIMASK1_IPL15_EN = %X'4'; literal KA0C08_TLEP$M_TLIMASK1_IPL16_EN = %X'8'; literal KA0C08_TLEP$M_TLIMASK1_IPL17_EN = %X'10'; literal KA0C08_TLEP$M_TLIMASK1_IP_EN = %X'20'; literal KA0C08_TLEP$M_TLIMASK1_INTIM_EN = %X'40'; literal KA0C08_TLEP$M_TLIMASK1_HALT_EN = %X'80'; literal KA0C08_TLEP$M_TLIMASK1_CP_EN = %X'100'; literal KA0C08_TLEP$M_TLISUM0_DUART0INT = %X'1'; literal KA0C08_TLEP$M_TLISUM0_IPL14_INT = %X'2'; literal KA0C08_TLEP$M_TLISUM0_IPL15_INT = %X'4'; literal KA0C08_TLEP$M_TLISUM0_IPL16_INT = %X'8'; literal KA0C08_TLEP$M_TLISUM0_IPL17_INT = %X'10'; literal KA0C08_TLEP$M_TLISUM0_IP_INT = %X'20'; literal KA0C08_TLEP$M_TLISUM0_INTIM_INT = %X'40'; literal KA0C08_TLEP$M_TLISUM0_IPL14 = %X'F80'; literal KA0C08_TLEP$M_TLISUM0_IPL15 = %X'1F000'; literal KA0C08_TLEP$M_TLISUM0_IPL16 = %X'3E0000'; literal KA0C08_TLEP$M_TLISUM0_IPL17 = %X'7C00000'; literal KA0C08_TLEP$M_TLISUM0_CP_HALT = %X'8000000'; literal KA0C08_TLEP$M_TLISUM0_HALT = %X'10000000'; literal KA0C08_TLEP$M_TLISUM1_DUART0INT = %X'1'; literal KA0C08_TLEP$M_TLISUM1_IPL14_INT = %X'2'; literal KA0C08_TLEP$M_TLISUM1_IPL15_INT = %X'4'; literal KA0C08_TLEP$M_TLISUM1_IPL16_INT = %X'8'; literal KA0C08_TLEP$M_TLISUM1_IPL17_INT = %X'10'; literal KA0C08_TLEP$M_TLISUM1_IP_INT = %X'20'; literal KA0C08_TLEP$M_TLISUM1_INTIM_INT = %X'40'; literal KA0C08_TLEP$M_TLISUM1_IPL14 = %X'F80'; literal KA0C08_TLEP$M_TLISUM1_IPL15 = %X'1F000'; literal KA0C08_TLEP$M_TLISUM1_IPL16 = %X'3E0000'; literal KA0C08_TLEP$M_TLISUM1_IPL17 = %X'7C00000'; literal KA0C08_TLEP$M_TLISUM1_CP_HALT = %X'8000000'; literal KA0C08_TLEP$M_TLISUM1_HALT = %X'10000000'; literal KA0C08_TLEP$M_TCCERR_P0_MBPR_TO = %X'1'; literal KA0C08_TLEP$M_TCCERR_P1_MBPR_TO = %X'2'; literal KA0C08_TLEP$M_TCCERR_DTPE0 = %X'4'; literal KA0C08_TLEP$M_TCCERR_DTPE1 = %X'8'; literal KA0C08_TLEP$M_TCCERR_SYSDERR = %X'10'; literal KA0C08_TLEP$M_TCCERR_WSPC_RD_ER = %X'20'; literal KA0C08_TLEP$M_TCCERR_SYSFAULT = %X'C0'; literal KA0C08_TLEP$M_TCCERR_FAULT_ASRT = %X'100'; literal KA0C08_TLEP$M_TCCERR_P0_FTLMMRE = %X'200'; literal KA0C08_TLEP$M_TCCERR_P1_FTLMMRE = %X'400'; literal KA0C08_TLEP$M_TCCERR_P0_MMRE = %X'800'; literal KA0C08_TLEP$M_TCCERR_P1_MMRE = %X'1000'; literal KA0C08_TLEP$M_TCCERR_CSR_WR_NXM = %X'2000'; literal KA0C08_TLEP$M_TCCERR_CSR_XACTN = %X'4000'; literal KA0C08_TLEP$M_TCCERR_TCC_REV = %X'F0000'; literal KA0C08_TLEP$M_TCCERR_P0_ILGLCSR = %X'100000'; literal KA0C08_TLEP$M_TCCERR_P1_ILGLCSR = %X'200000'; literal KA0C08_TLEP$M_TDIERR_GBTO = %X'4'; literal KA0C08_TLEP$M_TL6_VMG_5P = %X'1'; literal KA0C08_TLEP$M_TL6_VMG_5M = %X'2'; literal KA0C08_TLEP$M_TL6_VMG_3P = %X'4'; literal KA0C08_TLEP$M_TL6_VMG_3M = %X'8'; literal KA0C08_TLEP$M_TL6WERR_SELECT = %X'3'; literal KA0C08_TLEP$M_TL6WERR_R0_RD_PND = %X'1'; literal KA0C08_TLEP$M_TL6WERR_R0_ADDR = %X'FFFF8'; literal KA0C08_TLEP$M_TL6WERR_R1_ADDR = %X'7FFFF'; literal KA0C08_TLEP$M_TL6WERR_R2_RD_PND = %X'1'; literal KA0C08_TLEP$M_TL6WERR_R2_ADDR = %X'FFFF8'; literal KA0C08_TLEP$M_TL6WERR_R3_ADDR = %X'7FFFF'; literal KA0C08_TLEP$M_TLDTAGEX_f1 = %X'FFFFFFFF'; literal KA0C08_TLEP$S_KA0C08_TLEP = 6272; macro KA0C08_TLEP$L_TLDEV = 0,0,32,0 %; macro KA0C08_TLEP$V_TLDEV_DTYPE = 0,0,16,0 %; literal KA0C08_TLEP$S_TLDEV_DTYPE = 16; macro KA0C08_TLEP$V_TLDEV_SWREV = 0,16,8,0 %; literal KA0C08_TLEP$S_TLDEV_SWREV = 8; macro KA0C08_TLEP$V_TLDEV_HWREV = 0,24,8,0 %; literal KA0C08_TLEP$S_TLDEV_HWREV = 8; macro KA0C08_TLEP$b_f200 = 4,0,0,0 %; literal KA0C08_TLEP$s_f200 = 60; macro KA0C08_TLEP$L_TLBER = 64,0,32,0 %; macro KA0C08_TLEP$V_TLBER_ATCE = 64,0,1,0 %; macro KA0C08_TLEP$V_TLBER_APE = 64,1,1,0 %; macro KA0C08_TLEP$V_TLBER_BBE = 64,2,1,0 %; macro KA0C08_TLEP$V_TLBER_LKTO = 64,3,1,0 %; macro KA0C08_TLEP$V_TLBER_NAE = 64,4,1,0 %; macro KA0C08_TLEP$V_TLBER_RTCE = 64,5,1,0 %; macro KA0C08_TLEP$V_TLBER_ACKTCE = 64,6,1,0 %; macro KA0C08_TLEP$V_TLBER_MMRE = 64,7,1,0 %; macro KA0C08_TLEP$V_TLBER_FNAE = 64,8,1,0 %; macro KA0C08_TLEP$V_TLBER_REQDE = 64,9,1,0 %; macro KA0C08_TLEP$V_TLBER_ATDE = 64,10,1,0 %; macro KA0C08_TLEP$V_TLBER_UDE = 64,16,1,0 %; macro KA0C08_TLEP$V_TLBER_CWDE = 64,17,1,0 %; macro KA0C08_TLEP$V_TLBER_CRDE = 64,18,1,0 %; macro KA0C08_TLEP$V_TLBER_DS0 = 64,20,1,0 %; macro KA0C08_TLEP$V_TLBER_DS1 = 64,21,1,0 %; macro KA0C08_TLEP$V_TLBER_DS2 = 64,22,1,0 %; macro KA0C08_TLEP$V_TLBER_DS3 = 64,23,1,0 %; macro KA0C08_TLEP$V_TLBER_DTDE = 64,24,1,0 %; macro KA0C08_TLEP$V_TLBER_FDTCE = 64,25,1,0 %; macro KA0C08_TLEP$V_TLBER_UACKE = 64,26,1,0 %; macro KA0C08_TLEP$V_TLBER_ABTCE = 64,27,1,0 %; macro KA0C08_TLEP$V_TLBER_DCTCE = 64,28,1,0 %; macro KA0C08_TLEP$V_TLBER_SEQE = 64,29,1,0 %; macro KA0C08_TLEP$V_TLBER_DSE = 64,30,1,0 %; macro KA0C08_TLEP$V_TLBER_DTO = 64,31,1,0 %; macro KA0C08_TLEP$b_f210 = 68,0,0,0 %; literal KA0C08_TLEP$s_f210 = 60; macro KA0C08_TLEP$L_TLCNR = 128,0,32,0 %; macro KA0C08_TLEP$V_TLCNR_CWDD = 128,0,1,0 %; macro KA0C08_TLEP$V_TLCNR_CRDD = 128,1,1,0 %; macro KA0C08_TLEP$V_TLCNR_DTOD = 128,3,1,0 %; macro KA0C08_TLEP$V_TLCNR_NODE_ID = 128,4,4,0 %; literal KA0C08_TLEP$S_TLCNR_NODE_ID = 4; macro KA0C08_TLEP$V_TLCNR_VCNT = 128,8,4,0 %; literal KA0C08_TLEP$S_TLCNR_VCNT = 4; macro KA0C08_TLEP$V_TLCNR_STF_A = 128,12,1,0 %; macro KA0C08_TLEP$V_TLCNR_STF_B = 128,13,1,0 %; macro KA0C08_TLEP$V_TLCNR_HALT_A = 128,20,1,0 %; macro KA0C08_TLEP$V_TLCNR_HALT_B = 128,21,1,0 %; macro KA0C08_TLEP$V_TLCNR_NRST = 128,30,1,0 %; macro KA0C08_TLEP$V_TLCNR_LOFE = 128,31,1,0 %; macro KA0C08_TLEP$b_f220 = 132,0,0,0 %; literal KA0C08_TLEP$s_f220 = 60; macro KA0C08_TLEP$L_TLVID = 192,0,32,0 %; macro KA0C08_TLEP$V_VID_A = 192,0,4,0 %; literal KA0C08_TLEP$S_VID_A = 4; macro KA0C08_TLEP$V_VID_B = 192,4,4,0 %; literal KA0C08_TLEP$S_VID_B = 4; macro KA0C08_TLEP$b_f230 = 196,0,0,0 %; literal KA0C08_TLEP$s_f230 = 316; macro KA0C08_TLEP$L_TLMMR0 = 512,0,32,0 %; macro KA0C08_TLEP$V_TLMMR0_INTMASK = 512,0,2,0 %; literal KA0C08_TLEP$S_TLMMR0_INTMASK = 2; macro KA0C08_TLEP$V_TLMMR0_ADRMASK = 512,4,4,0 %; literal KA0C08_TLEP$S_TLMMR0_ADRMASK = 4; macro KA0C08_TLEP$V_TLMMR0_INTLV = 512,8,3,0 %; literal KA0C08_TLEP$S_TLMMR0_INTLV = 3; macro KA0C08_TLEP$V_TLMMR0_SBANK = 512,11,1,0 %; macro KA0C08_TLEP$V_TLMMR0_ADDRESS = 512,12,14,0 %; literal KA0C08_TLEP$S_TLMMR0_ADDRESS = 14; macro KA0C08_TLEP$V_TLMMR0_VALID = 512,31,1,0 %; macro KA0C08_TLEP$b_f240 = 516,0,0,0 %; literal KA0C08_TLEP$s_f240 = 60; macro KA0C08_TLEP$L_TLMMR1 = 576,0,32,0 %; macro KA0C08_TLEP$V_TLMMR1_INTMASK = 576,0,2,0 %; literal KA0C08_TLEP$S_TLMMR1_INTMASK = 2; macro KA0C08_TLEP$V_TLMMR1_ADRMASK = 576,4,4,0 %; literal KA0C08_TLEP$S_TLMMR1_ADRMASK = 4; macro KA0C08_TLEP$V_TLMMR1_INTLV = 576,8,3,0 %; literal KA0C08_TLEP$S_TLMMR1_INTLV = 3; macro KA0C08_TLEP$V_TLMMR1_SBANK = 576,11,1,0 %; macro KA0C08_TLEP$V_TLMMR1_ADDRESS = 576,12,14,0 %; literal KA0C08_TLEP$S_TLMMR1_ADDRESS = 14; macro KA0C08_TLEP$V_TLMMR1_VALID = 576,31,1,0 %; macro KA0C08_TLEP$b_f250 = 580,0,0,0 %; literal KA0C08_TLEP$s_f250 = 60; macro KA0C08_TLEP$L_TLMMR2 = 640,0,32,0 %; macro KA0C08_TLEP$V_TLMMR2_INTMASK = 640,0,2,0 %; literal KA0C08_TLEP$S_TLMMR2_INTMASK = 2; macro KA0C08_TLEP$V_TLMMR2_ADRMASK = 640,4,4,0 %; literal KA0C08_TLEP$S_TLMMR2_ADRMASK = 4; macro KA0C08_TLEP$V_TLMMR2_INTLV = 640,8,3,0 %; literal KA0C08_TLEP$S_TLMMR2_INTLV = 3; macro KA0C08_TLEP$V_TLMMR2_SBANK = 640,11,1,0 %; macro KA0C08_TLEP$V_TLMMR2_ADDRESS = 640,12,14,0 %; literal KA0C08_TLEP$S_TLMMR2_ADDRESS = 14; macro KA0C08_TLEP$V_TLMMR2_VALID = 640,31,1,0 %; macro KA0C08_TLEP$b_f260 = 644,0,0,0 %; literal KA0C08_TLEP$s_f260 = 60; macro KA0C08_TLEP$L_TLMMR3 = 704,0,32,0 %; macro KA0C08_TLEP$V_TLMMR3_INTMASK = 704,0,2,0 %; literal KA0C08_TLEP$S_TLMMR3_INTMASK = 2; macro KA0C08_TLEP$V_TLMMR3_ADRMASK = 704,4,4,0 %; literal KA0C08_TLEP$S_TLMMR3_ADRMASK = 4; macro KA0C08_TLEP$V_TLMMR3_INTLV = 704,8,3,0 %; literal KA0C08_TLEP$S_TLMMR3_INTLV = 3; macro KA0C08_TLEP$V_TLMMR3_SBANK = 704,11,1,0 %; macro KA0C08_TLEP$V_TLMMR3_ADDRESS = 704,12,14,0 %; literal KA0C08_TLEP$S_TLMMR3_ADDRESS = 14; macro KA0C08_TLEP$V_TLMMR3_VALID = 704,31,1,0 %; macro KA0C08_TLEP$b_f270 = 708,0,0,0 %; literal KA0C08_TLEP$s_f270 = 60; macro KA0C08_TLEP$L_TLMMR4 = 768,0,32,0 %; macro KA0C08_TLEP$V_TLMMR4_INTMASK = 768,0,2,0 %; literal KA0C08_TLEP$S_TLMMR4_INTMASK = 2; macro KA0C08_TLEP$V_TLMMR4_ADRMASK = 768,4,4,0 %; literal KA0C08_TLEP$S_TLMMR4_ADRMASK = 4; macro KA0C08_TLEP$V_TLMMR4_INTLV = 768,8,3,0 %; literal KA0C08_TLEP$S_TLMMR4_INTLV = 3; macro KA0C08_TLEP$V_TLMMR4_SBANK = 768,11,1,0 %; macro KA0C08_TLEP$V_TLMMR4_ADDRESS = 768,12,14,0 %; literal KA0C08_TLEP$S_TLMMR4_ADDRESS = 14; macro KA0C08_TLEP$V_TLMMR4_VALID = 768,31,1,0 %; macro KA0C08_TLEP$b_f280 = 772,0,0,0 %; literal KA0C08_TLEP$s_f280 = 60; macro KA0C08_TLEP$L_TLMMR5 = 832,0,32,0 %; macro KA0C08_TLEP$V_TLMMR5_INTMASK = 832,0,2,0 %; literal KA0C08_TLEP$S_TLMMR5_INTMASK = 2; macro KA0C08_TLEP$V_TLMMR5_ADRMASK = 832,4,4,0 %; literal KA0C08_TLEP$S_TLMMR5_ADRMASK = 4; macro KA0C08_TLEP$V_TLMMR5_INTLV = 832,8,3,0 %; literal KA0C08_TLEP$S_TLMMR5_INTLV = 3; macro KA0C08_TLEP$V_TLMMR5_SBANK = 832,11,1,0 %; macro KA0C08_TLEP$V_TLMMR5_ADDRESS = 832,12,14,0 %; literal KA0C08_TLEP$S_TLMMR5_ADDRESS = 14; macro KA0C08_TLEP$V_TLMMR5_VALID = 832,31,1,0 %; macro KA0C08_TLEP$b_f290 = 836,0,0,0 %; literal KA0C08_TLEP$s_f290 = 60; macro KA0C08_TLEP$L_TLMMR6 = 896,0,32,0 %; macro KA0C08_TLEP$V_TLMMR6_INTMASK = 896,0,2,0 %; literal KA0C08_TLEP$S_TLMMR6_INTMASK = 2; macro KA0C08_TLEP$V_TLMMR6_ADRMASK = 896,4,4,0 %; literal KA0C08_TLEP$S_TLMMR6_ADRMASK = 4; macro KA0C08_TLEP$V_TLMMR6_INTLV = 896,8,3,0 %; literal KA0C08_TLEP$S_TLMMR6_INTLV = 3; macro KA0C08_TLEP$V_TLMMR6_SBANK = 896,11,1,0 %; macro KA0C08_TLEP$V_TLMMR6_ADDRESS = 896,12,14,0 %; literal KA0C08_TLEP$S_TLMMR6_ADDRESS = 14; macro KA0C08_TLEP$V_TLMMR6_VALID = 896,31,1,0 %; macro KA0C08_TLEP$b_fill300 = 900,0,0,0 %; literal KA0C08_TLEP$s_fill300 = 60; macro KA0C08_TLEP$L_TLMMR7 = 960,0,32,0 %; macro KA0C08_TLEP$V_TLMMR7_INTMASK = 960,0,2,0 %; literal KA0C08_TLEP$S_TLMMR7_INTMASK = 2; macro KA0C08_TLEP$V_TLMMR7_ADRMASK = 960,4,4,0 %; literal KA0C08_TLEP$S_TLMMR7_ADRMASK = 4; macro KA0C08_TLEP$V_TLMMR7_INTLV = 960,8,3,0 %; literal KA0C08_TLEP$S_TLMMR7_INTLV = 3; macro KA0C08_TLEP$V_TLMMR7_SBANK = 960,11,1,0 %; macro KA0C08_TLEP$V_TLMMR7_ADDRESS = 960,12,14,0 %; literal KA0C08_TLEP$S_TLMMR7_ADDRESS = 14; macro KA0C08_TLEP$V_TLMMR7_VALID = 960,31,1,0 %; macro KA0C08_TLEP$b_fill310 = 964,0,0,0 %; literal KA0C08_TLEP$s_fill310 = 700; macro KA0C08_TLEP$L_TLESR0 = 1664,0,32,0 %; macro KA0C08_TLEP$V_TLESR0_SYND0 = 1664,0,8,0 %; literal KA0C08_TLEP$S_TLESR0_SYND0 = 8; macro KA0C08_TLEP$V_TLESR0_SYND1 = 1664,8,8,0 %; literal KA0C08_TLEP$S_TLESR0_SYND1 = 8; macro KA0C08_TLEP$V_TLESR0_TDE = 1664,16,1,0 %; macro KA0C08_TLEP$V_TLESR0_TCE = 1664,17,1,0 %; macro KA0C08_TLEP$V_TLESR0_DVTCE = 1664,18,1,0 %; macro KA0C08_TLEP$V_TLESR0_UECC = 1664,19,1,0 %; macro KA0C08_TLEP$V_TLESR0_CWECC = 1664,20,1,0 %; macro KA0C08_TLEP$V_TLESR0_CRECC = 1664,21,1,0 %; macro KA0C08_TLEP$V_TLESR0_CPU0 = 1664,22,1,0 %; macro KA0C08_TLEP$V_TLESR0_CPU1 = 1664,23,1,0 %; macro KA0C08_TLEP$V_TLESR0_LOFSYN = 1664,31,1,0 %; macro KA0C08_TLEP$b_fill320 = 1668,0,0,0 %; literal KA0C08_TLEP$s_fill320 = 60; macro KA0C08_TLEP$L_TLESR1 = 1728,0,32,0 %; macro KA0C08_TLEP$V_TLESR1_SYND0 = 1728,0,8,0 %; literal KA0C08_TLEP$S_TLESR1_SYND0 = 8; macro KA0C08_TLEP$V_TLESR1_SYND1 = 1728,8,8,0 %; literal KA0C08_TLEP$S_TLESR1_SYND1 = 8; macro KA0C08_TLEP$V_TLESR1_TDE = 1728,16,1,0 %; macro KA0C08_TLEP$V_TLESR1_TCE = 1728,17,1,0 %; macro KA0C08_TLEP$V_TLESR1_DVTCE = 1728,18,1,0 %; macro KA0C08_TLEP$V_TLESR1_UECC = 1728,19,1,0 %; macro KA0C08_TLEP$V_TLESR1_CWECC = 1728,20,1,0 %; macro KA0C08_TLEP$V_TLESR1_CRECC = 1728,21,1,0 %; macro KA0C08_TLEP$V_TLESR1_CPU0 = 1728,22,1,0 %; macro KA0C08_TLEP$V_TLESR1_CPU1 = 1728,23,1,0 %; macro KA0C08_TLEP$V_TLESR1_LOFSYN = 1728,31,1,0 %; macro KA0C08_TLEP$b_fill330 = 1732,0,0,0 %; literal KA0C08_TLEP$s_fill330 = 60; macro KA0C08_TLEP$L_TLESR2 = 1792,0,32,0 %; macro KA0C08_TLEP$V_TLESR2_SYND0 = 1792,0,8,0 %; literal KA0C08_TLEP$S_TLESR2_SYND0 = 8; macro KA0C08_TLEP$V_TLESR2_SYND1 = 1792,8,8,0 %; literal KA0C08_TLEP$S_TLESR2_SYND1 = 8; macro KA0C08_TLEP$V_TLESR2_TDE = 1792,16,1,0 %; macro KA0C08_TLEP$V_TLESR2_TCE = 1792,17,1,0 %; macro KA0C08_TLEP$V_TLESR2_DVTCE = 1792,18,1,0 %; macro KA0C08_TLEP$V_TLESR2_UECC = 1792,19,1,0 %; macro KA0C08_TLEP$V_TLESR2_CWECC = 1792,20,1,0 %; macro KA0C08_TLEP$V_TLESR2_CRECC = 1792,21,1,0 %; macro KA0C08_TLEP$V_TLESR2_CPU0 = 1792,22,1,0 %; macro KA0C08_TLEP$V_TLESR2_CPU1 = 1792,23,1,0 %; macro KA0C08_TLEP$V_TLESR2_LOFSYN = 1792,31,1,0 %; macro KA0C08_TLEP$b_fill340 = 1796,0,0,0 %; literal KA0C08_TLEP$s_fill340 = 60; macro KA0C08_TLEP$L_TLESR3 = 1856,0,32,0 %; macro KA0C08_TLEP$V_TLESR3_SYND0 = 1856,0,8,0 %; literal KA0C08_TLEP$S_TLESR3_SYND0 = 8; macro KA0C08_TLEP$V_TLESR3_SYND1 = 1856,8,8,0 %; literal KA0C08_TLEP$S_TLESR3_SYND1 = 8; macro KA0C08_TLEP$V_TLESR3_TDE = 1856,16,1,0 %; macro KA0C08_TLEP$V_TLESR3_TCE = 1856,17,1,0 %; macro KA0C08_TLEP$V_TLESR3_DVTCE = 1856,18,1,0 %; macro KA0C08_TLEP$V_TLESR3_UECC = 1856,19,1,0 %; macro KA0C08_TLEP$V_TLESR3_CWECC = 1856,20,1,0 %; macro KA0C08_TLEP$V_TLESR3_CRECC = 1856,21,1,0 %; macro KA0C08_TLEP$V_TLESR3_CPU0 = 1856,22,1,0 %; macro KA0C08_TLEP$V_TLESR3_CPU1 = 1856,23,1,0 %; macro KA0C08_TLEP$V_TLESR3_LOFSYN = 1856,31,1,0 %; macro KA0C08_TLEP$b_fill350 = 1860,0,0,0 %; literal KA0C08_TLEP$s_fill350 = 2236; macro KA0C08_TLEP$L_TLMODCFG0 = 4096,0,32,0 %; macro KA0C08_TLEP$V_TLMODCFG0_FRIGN = 4096,0,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_FDE0 = 4096,1,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_FDE1 = 4096,2,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_P1_UDE = 4096,3,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_P1_CRDE = 4096,4,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_DLY_IN = 4096,5,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_DLY_OUT = 4096,6,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_DPQ_MAX = 4096,7,3,0 %; literal KA0C08_TLEP$S_TLMODCFG0_DPQ_MAX = 3; macro KA0C08_TLEP$V_TLMODCFG0_MMRE_DS = 4096,10,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_FASTFLS = 4096,11,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_DELAY_A = 4096,12,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_ILGLCSR = 4096,13,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_E_SLOWR = 4096,14,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_ASRT_FT = 4096,15,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_DTAG_PE = 4096,16,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_DTAG0_D = 4096,17,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_DTAG1_D = 4096,18,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_D_WRAP = 4096,19,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_BQ_MAX = 4096,20,3,0 %; literal KA0C08_TLEP$S_TLMODCFG0_BQ_MAX = 3; macro KA0C08_TLEP$V_TLMODCFG0_BC_SIZE = 4096,23,2,0 %; literal KA0C08_TLEP$S_TLMODCFG0_BC_SIZE = 2; macro KA0C08_TLEP$V_TLMODCFG0_FDE_CMD = 4096,25,4,0 %; literal KA0C08_TLEP$S_TLMODCFG0_FDE_CMD = 4; macro KA0C08_TLEP$V_TLMODCFG0_FSBE = 4096,29,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_FDE2 = 4096,30,1,0 %; macro KA0C08_TLEP$V_TLMODCFG0_FDE3 = 4096,31,1,0 %; macro KA0C08_TLEP$b_fill360 = 4100,0,0,0 %; literal KA0C08_TLEP$s_fill360 = 60; macro KA0C08_TLEP$L_TLDTAGDATA = 4160,0,32,0 %; macro KA0C08_TLEP$V_TLDTAGDATA_PAR = 4160,0,1,0 %; macro KA0C08_TLEP$V_TLDTAGDATA_DATA = 4160,1,17,0 %; literal KA0C08_TLEP$S_TLDTAGDATA_DATA = 17; macro KA0C08_TLEP$b_fill370 = 4164,0,0,0 %; literal KA0C08_TLEP$s_fill370 = 60; macro KA0C08_TLEP$L_TLDTAGADDR = 4224,0,32,0 %; macro KA0C08_TLEP$V_TLDTAGADDR_ADDR = 4224,0,18,0 %; literal KA0C08_TLEP$S_TLDTAGADDR_ADDR = 18; macro KA0C08_TLEP$V_TLDTAGADDR_CPU_SL = 4224,24,1,0 %; macro KA0C08_TLEP$b_fill380 = 4228,0,0,0 %; literal KA0C08_TLEP$s_fill380 = 60; macro KA0C08_TLEP$L_TLMODCFG1 = 4288,0,32,0 %; macro KA0C08_TLEP$V_TLMODCFG1_OVRTK_E = 4288,0,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_P0_RID = 4288,1,3,0 %; literal KA0C08_TLEP$S_TLMODCFG1_P0_RID = 3; macro KA0C08_TLEP$V_TLMODCFG1_P1_RID = 4288,4,3,0 %; literal KA0C08_TLEP$S_TLMODCFG1_P1_RID = 3; macro KA0C08_TLEP$V_TLMODCFG1_MBPR_RY = 4288,7,2,0 %; literal KA0C08_TLEP$S_TLMODCFG1_MBPR_RY = 2; macro KA0C08_TLEP$V_TLMODCFG1_FAULT_D = 4288,9,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_FSTRQ_D = 4288,10,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_P0_RQ_D = 4288,11,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_P1_RQ_D = 4288,12,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_D_PROBE = 4288,13,2,0 %; literal KA0C08_TLEP$S_TLMODCFG1_D_PROBE = 2; macro KA0C08_TLEP$V_TLMODCFG1_FSTPTH = 4288,15,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_DLSB_PR = 4288,16,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_VIC_SKP = 4288,17,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_FRCE_SQ = 4288,18,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_DB_BUB = 4288,19,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_FST_VQ = 4288,20,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_FST_PRQ = 4288,21,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_BUSWRTE = 4288,22,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_FST_WRT = 4288,23,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_FRC_SHR = 4288,24,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_VQRBCTL = 4288,25,1,0 %; macro KA0C08_TLEP$V_TLMODCFG1_CSR_SIZ = 4288,26,1,0 %; macro KA0C08_TLEP$b_fill390 = 4292,0,0,0 %; literal KA0C08_TLEP$s_fill390 = 60; macro KA0C08_TLEP$L_TLIMASK0 = 4352,0,32,0 %; macro KA0C08_TLEP$V_TLIMASK0_DUART0EN = 4352,0,1,0 %; macro KA0C08_TLEP$V_TLIMASK0_IPL14_EN = 4352,1,1,0 %; macro KA0C08_TLEP$V_TLIMASK0_IPL15_EN = 4352,2,1,0 %; macro KA0C08_TLEP$V_TLIMASK0_IPL16_EN = 4352,3,1,0 %; macro KA0C08_TLEP$V_TLIMASK0_IPL17_EN = 4352,4,1,0 %; macro KA0C08_TLEP$V_TLIMASK0_IP_EN = 4352,5,1,0 %; macro KA0C08_TLEP$V_TLIMASK0_INTIM_EN = 4352,6,1,0 %; macro KA0C08_TLEP$V_TLIMASK0_HALT_EN = 4352,7,1,0 %; macro KA0C08_TLEP$V_TLIMASK0_CP_EN = 4352,8,1,0 %; macro KA0C08_TLEP$b_fill400 = 4356,0,0,0 %; literal KA0C08_TLEP$s_fill400 = 60; macro KA0C08_TLEP$L_TLIMASK1 = 4416,0,32,0 %; macro KA0C08_TLEP$V_TLIMASK1_DUART0EN = 4416,0,1,0 %; macro KA0C08_TLEP$V_TLIMASK1_IPL14_EN = 4416,1,1,0 %; macro KA0C08_TLEP$V_TLIMASK1_IPL15_EN = 4416,2,1,0 %; macro KA0C08_TLEP$V_TLIMASK1_IPL16_EN = 4416,3,1,0 %; macro KA0C08_TLEP$V_TLIMASK1_IPL17_EN = 4416,4,1,0 %; macro KA0C08_TLEP$V_TLIMASK1_IP_EN = 4416,5,1,0 %; macro KA0C08_TLEP$V_TLIMASK1_INTIM_EN = 4416,6,1,0 %; macro KA0C08_TLEP$V_TLIMASK1_HALT_EN = 4416,7,1,0 %; macro KA0C08_TLEP$V_TLIMASK1_CP_EN = 4416,8,1,0 %; macro KA0C08_TLEP$b_fill410 = 4420,0,0,0 %; literal KA0C08_TLEP$s_fill410 = 60; macro KA0C08_TLEP$L_TLISUM0 = 4480,0,32,0 %; macro KA0C08_TLEP$V_TLISUM0_DUART0INT = 4480,0,1,0 %; macro KA0C08_TLEP$V_TLISUM0_IPL14_INT = 4480,1,1,0 %; macro KA0C08_TLEP$V_TLISUM0_IPL15_INT = 4480,2,1,0 %; macro KA0C08_TLEP$V_TLISUM0_IPL16_INT = 4480,3,1,0 %; macro KA0C08_TLEP$V_TLISUM0_IPL17_INT = 4480,4,1,0 %; macro KA0C08_TLEP$V_TLISUM0_IP_INT = 4480,5,1,0 %; macro KA0C08_TLEP$V_TLISUM0_INTIM_INT = 4480,6,1,0 %; macro KA0C08_TLEP$V_TLISUM0_IPL14 = 4480,7,5,0 %; literal KA0C08_TLEP$S_TLISUM0_IPL14 = 5; macro KA0C08_TLEP$V_TLISUM0_IPL15 = 4480,12,5,0 %; literal KA0C08_TLEP$S_TLISUM0_IPL15 = 5; macro KA0C08_TLEP$V_TLISUM0_IPL16 = 4480,17,5,0 %; literal KA0C08_TLEP$S_TLISUM0_IPL16 = 5; macro KA0C08_TLEP$V_TLISUM0_IPL17 = 4480,22,5,0 %; literal KA0C08_TLEP$S_TLISUM0_IPL17 = 5; macro KA0C08_TLEP$V_TLISUM0_CP_HALT = 4480,27,1,0 %; macro KA0C08_TLEP$V_TLISUM0_HALT = 4480,28,1,0 %; macro KA0C08_TLEP$b_fill420 = 4484,0,0,0 %; literal KA0C08_TLEP$s_fill420 = 60; macro KA0C08_TLEP$L_TLISUM1 = 4544,0,32,0 %; macro KA0C08_TLEP$V_TLISUM1_DUART0INT = 4544,0,1,0 %; macro KA0C08_TLEP$V_TLISUM1_IPL14_INT = 4544,1,1,0 %; macro KA0C08_TLEP$V_TLISUM1_IPL15_INT = 4544,2,1,0 %; macro KA0C08_TLEP$V_TLISUM1_IPL16_INT = 4544,3,1,0 %; macro KA0C08_TLEP$V_TLISUM1_IPL17_INT = 4544,4,1,0 %; macro KA0C08_TLEP$V_TLISUM1_IP_INT = 4544,5,1,0 %; macro KA0C08_TLEP$V_TLISUM1_INTIM_INT = 4544,6,1,0 %; macro KA0C08_TLEP$V_TLISUM1_IPL14 = 4544,7,5,0 %; literal KA0C08_TLEP$S_TLISUM1_IPL14 = 5; macro KA0C08_TLEP$V_TLISUM1_IPL15 = 4544,12,5,0 %; literal KA0C08_TLEP$S_TLISUM1_IPL15 = 5; macro KA0C08_TLEP$V_TLISUM1_IPL16 = 4544,17,5,0 %; literal KA0C08_TLEP$S_TLISUM1_IPL16 = 5; macro KA0C08_TLEP$V_TLISUM1_IPL17 = 4544,22,5,0 %; literal KA0C08_TLEP$S_TLISUM1_IPL17 = 5; macro KA0C08_TLEP$V_TLISUM1_CP_HALT = 4544,27,1,0 %; macro KA0C08_TLEP$V_TLISUM1_HALT = 4544,28,1,0 %; macro KA0C08_TLEP$b_fill430 = 4548,0,0,0 %; literal KA0C08_TLEP$s_fill430 = 60; macro KA0C08_TLEP$L_TLCON00 = 4608,0,32,0 %; macro KA0C08_TLEP$b_fill440 = 4612,0,0,0 %; literal KA0C08_TLEP$s_fill440 = 60; macro KA0C08_TLEP$L_TLCON00A = 4672,0,32,0 %; macro KA0C08_TLEP$b_fill450 = 4676,0,0,0 %; literal KA0C08_TLEP$s_fill450 = 60; macro KA0C08_TLEP$L_TLCON00B = 4736,0,32,0 %; macro KA0C08_TLEP$b_fill460 = 4740,0,0,0 %; literal KA0C08_TLEP$s_fill460 = 60; macro KA0C08_TLEP$L_TLCON00C = 4800,0,32,0 %; macro KA0C08_TLEP$b_fill470 = 4804,0,0,0 %; literal KA0C08_TLEP$s_fill470 = 60; macro KA0C08_TLEP$L_TLCON10 = 4864,0,32,0 %; macro KA0C08_TLEP$b_fill480 = 4868,0,0,0 %; literal KA0C08_TLEP$s_fill480 = 60; macro KA0C08_TLEP$L_TLCON10A = 4928,0,32,0 %; macro KA0C08_TLEP$b_fill490 = 4932,0,0,0 %; literal KA0C08_TLEP$s_fill490 = 60; macro KA0C08_TLEP$L_TLCON10B = 4992,0,32,0 %; macro KA0C08_TLEP$b_fill500 = 4996,0,0,0 %; literal KA0C08_TLEP$s_fill500 = 60; macro KA0C08_TLEP$L_TLCON10C = 5056,0,32,0 %; macro KA0C08_TLEP$b_fill510 = 5060,0,0,0 %; literal KA0C08_TLEP$s_fill510 = 60; macro KA0C08_TLEP$L_TLCON01 = 5120,0,32,0 %; macro KA0C08_TLEP$b_fill520 = 5124,0,0,0 %; literal KA0C08_TLEP$s_fill520 = 60; macro KA0C08_TLEP$L_TLCON11 = 5184,0,32,0 %; macro KA0C08_TLEP$b_fill530 = 5188,0,0,0 %; literal KA0C08_TLEP$s_fill530 = 188; macro KA0C08_TLEP$L_TCCERR = 5376,0,32,0 %; macro KA0C08_TLEP$V_TCCERR_P0_MBPR_TO = 5376,0,1,0 %; macro KA0C08_TLEP$V_TCCERR_P1_MBPR_TO = 5376,1,1,0 %; macro KA0C08_TLEP$V_TCCERR_DTPE0 = 5376,2,1,0 %; macro KA0C08_TLEP$V_TCCERR_DTPE1 = 5376,3,1,0 %; macro KA0C08_TLEP$V_TCCERR_SYSDERR = 5376,4,1,0 %; macro KA0C08_TLEP$V_TCCERR_WSPC_RD_ER = 5376,5,1,0 %; macro KA0C08_TLEP$V_TCCERR_SYSFAULT = 5376,6,2,0 %; literal KA0C08_TLEP$S_TCCERR_SYSFAULT = 2; macro KA0C08_TLEP$V_TCCERR_FAULT_ASRT = 5376,8,1,0 %; macro KA0C08_TLEP$V_TCCERR_P0_FTLMMRE = 5376,9,1,0 %; macro KA0C08_TLEP$V_TCCERR_P1_FTLMMRE = 5376,10,1,0 %; macro KA0C08_TLEP$V_TCCERR_P0_MMRE = 5376,11,1,0 %; macro KA0C08_TLEP$V_TCCERR_P1_MMRE = 5376,12,1,0 %; macro KA0C08_TLEP$V_TCCERR_CSR_WR_NXM = 5376,13,1,0 %; macro KA0C08_TLEP$V_TCCERR_CSR_XACTN = 5376,14,1,0 %; macro KA0C08_TLEP$V_TCCERR_TCC_REV = 5376,16,4,0 %; literal KA0C08_TLEP$S_TCCERR_TCC_REV = 4; macro KA0C08_TLEP$V_TCCERR_P0_ILGLCSR = 5376,20,1,0 %; macro KA0C08_TLEP$V_TCCERR_P1_ILGLCSR = 5376,21,1,0 %; macro KA0C08_TLEP$b_fill540 = 5380,0,0,0 %; literal KA0C08_TLEP$s_fill540 = 60; macro KA0C08_TLEP$L_TDIERR = 5440,0,32,0 %; macro KA0C08_TLEP$V_TDIERR_GBTO = 5440,2,1,0 %; macro KA0C08_TLEP$b_fill550 = 5444,0,0,0 %; literal KA0C08_TLEP$s_fill550 = 124; macro KA0C08_TLEP$L_TL6_VMG = 5568,0,32,0 %; macro KA0C08_TLEP$V_TL6_VMG_5P = 5568,0,1,0 %; macro KA0C08_TLEP$V_TL6_VMG_5M = 5568,1,1,0 %; macro KA0C08_TLEP$V_TL6_VMG_3P = 5568,2,1,0 %; macro KA0C08_TLEP$V_TL6_VMG_3M = 5568,3,1,0 %; macro KA0C08_TLEP$b_fill570 = 5572,0,0,0 %; literal KA0C08_TLEP$s_fill570 = 60; macro KA0C08_TLEP$L_TL6WERR = 5632,0,32,0 %; macro KA0C08_TLEP$V_TL6WERR_SELECT = 5632,0,2,0 %; literal KA0C08_TLEP$S_TL6WERR_SELECT = 2; macro KA0C08_TLEP$V_TL6WERR_R0_RD_PND = 5632,0,1,0 %; macro KA0C08_TLEP$V_TL6WERR_R0_ADDR = 5632,3,17,0 %; literal KA0C08_TLEP$S_TL6WERR_R0_ADDR = 17; macro KA0C08_TLEP$V_TL6WERR_R1_ADDR = 5632,0,19,0 %; literal KA0C08_TLEP$S_TL6WERR_R1_ADDR = 19; macro KA0C08_TLEP$V_TL6WERR_R2_RD_PND = 5632,0,1,0 %; macro KA0C08_TLEP$V_TL6WERR_R2_ADDR = 5632,3,17,0 %; literal KA0C08_TLEP$S_TL6WERR_R2_ADDR = 17; macro KA0C08_TLEP$V_TL6WERR_R3_ADDR = 5632,0,19,0 %; literal KA0C08_TLEP$S_TL6WERR_R3_ADDR = 19; macro KA0C08_TLEP$b_fill580 = 5636,0,0,0 %; literal KA0C08_TLEP$s_fill580 = 508; macro KA0C08_TLEP$L_TLDTAGEX = 6144,0,32,0 %; macro KA0C08_TLEP$V_TLDTAGEX_f1 = 6144,0,32,0 %; literal KA0C08_TLEP$S_TLDTAGEX_f1 = 32; macro KA0C08_TLEP$b_fill610 = 6148,0,0,0 %; literal KA0C08_TLEP$s_fill610 = 60; macro KA0C08_TLEP$L_TLLOOPBCK = 6208,0,32,0 %; macro KA0C08_TLEP$b_fill620 = 6212,0,0,0 %; literal KA0C08_TLEP$s_fill620 = 60; literal KA0C05_TLMEM$M_TLDEV_DTYPE = %X'FFFF'; literal KA0C05_TLMEM$M_TLDEV_SWREV = %X'FF0000'; literal KA0C05_TLMEM$M_TLDEV_HWREV = %X'FF000000'; literal KA0C05_TLMEM$M_TLBER_ATCE = %X'1'; literal KA0C05_TLMEM$M_TLBER_APE = %X'2'; literal KA0C05_TLMEM$M_TLBER_BBE = %X'4'; literal KA0C05_TLMEM$M_TLBER_LKTO = %X'8'; literal KA0C05_TLMEM$M_TLBER_NAE = %X'10'; literal KA0C05_TLMEM$M_TLBER_RTCE = %X'20'; literal KA0C05_TLMEM$M_TLBER_ACKTCE = %X'40'; literal KA0C05_TLMEM$M_TLBER_MMRE = %X'80'; literal KA0C05_TLMEM$M_TLBER_FNAE = %X'100'; literal KA0C05_TLMEM$M_TLBER_REQDE = %X'200'; literal KA0C05_TLMEM$M_TLBER_ATDE = %X'400'; literal KA0C05_TLMEM$M_TLBER_UDE = %X'10000'; literal KA0C05_TLMEM$M_TLBER_CWDE = %X'20000'; literal KA0C05_TLMEM$M_TLBER_CRDE = %X'40000'; literal KA0C05_TLMEM$M_TLBER_DS0 = %X'100000'; literal KA0C05_TLMEM$M_TLBER_DS1 = %X'200000'; literal KA0C05_TLMEM$M_TLBER_DS2 = %X'400000'; literal KA0C05_TLMEM$M_TLBER_DS3 = %X'800000'; literal KA0C05_TLMEM$M_TLBER_DTDE = %X'1000000'; literal KA0C05_TLMEM$M_TLBER_FDTCE = %X'2000000'; literal KA0C05_TLMEM$M_TLBER_UACKE = %X'4000000'; literal KA0C05_TLMEM$M_TLBER_ABTCE = %X'8000000'; literal KA0C05_TLMEM$M_TLBER_DCTCE = %X'10000000'; literal KA0C05_TLMEM$M_TLBER_SEQE = %X'20000000'; literal KA0C05_TLMEM$M_TLBER_DSE = %X'40000000'; literal KA0C05_TLMEM$M_TLBER_DTO = %X'80000000'; literal KA0C05_TLMEM$M_TLCNR_CWDD = %X'1'; literal KA0C05_TLMEM$M_TLCNR_CRDD = %X'2'; literal KA0C05_TLMEM$M_TLCNR_LKTOD = %X'4'; literal KA0C05_TLMEM$M_TLCNR_DTOD = %X'8'; literal KA0C05_TLMEM$M_TLCNR_NODE_ID = %X'F0'; literal KA0C05_TLMEM$M_TLCNR_VCNT = %X'F00'; literal KA0C05_TLMEM$M_TLCNR_STF_A = %X'1000'; literal KA0C05_TLMEM$M_TLCNR_STF_B = %X'2000'; literal KA0C05_TLMEM$M_TLCNR_STF_C = %X'4000'; literal KA0C05_TLMEM$M_TLCNR_STF_D = %X'8000'; literal KA0C05_TLMEM$M_TLCNR_STF_E = %X'10000'; literal KA0C05_TLMEM$M_TLCNR_STF_F = %X'20000'; literal KA0C05_TLMEM$M_TLCNR_STF_G = %X'40000'; literal KA0C05_TLMEM$M_TLCNR_STF_H = %X'80000'; literal KA0C05_TLMEM$M_TLCNR_HALT_A = %X'100000'; literal KA0C05_TLMEM$M_TLCNR_HALT_B = %X'200000'; literal KA0C05_TLMEM$M_TLCNR_HALT_C = %X'400000'; literal KA0C05_TLMEM$M_TLCNR_HALT_D = %X'800000'; literal KA0C05_TLMEM$M_TLCNR_HALT_E = %X'1000000'; literal KA0C05_TLMEM$M_TLCNR_HALT_F = %X'2000000'; literal KA0C05_TLMEM$M_TLCNR_HALT_G = %X'4000000'; literal KA0C05_TLMEM$M_TLCNR_HALT_H = %X'8000000'; literal KA0C05_TLMEM$M_TLCNR_RSTSTAT = %X'10000000'; literal KA0C05_TLMEM$M_TLCNR_NRST = %X'40000000'; literal KA0C05_TLMEM$M_TLCNR_LOFE = %X'80000000'; literal KA0C05_TLMEM$M_VID_A = %X'F'; literal KA0C05_TLMEM$M_VID_B = %X'F0'; literal KA0C05_TLMEM$M_VID_C = %X'F00'; literal KA0C05_TLMEM$M_VID_D = %X'F000'; literal KA0C05_TLMEM$M_VID_E = %X'F0000'; literal KA0C05_TLMEM$M_VID_F = %X'F00000'; literal KA0C05_TLMEM$M_VID_G = %X'F000000'; literal KA0C05_TLMEM$M_VID_H = %X'F0000000'; literal KA0C05_TLMEM$M_TLFADR0_FADR = %X'FFFFFFF8'; literal KA0C05_TLMEM$M_TLFADR1_FADR = %X'FF'; literal KA0C05_TLMEM$M_TLFADR1_FCMD = %X'70000'; literal KA0C05_TLMEM$M_TLFADR1_FBANK = %X'F00000'; literal KA0C05_TLMEM$M_TLFADR1_ADRV = %X'1000000'; literal KA0C05_TLMEM$M_TLFADR1_CMDV = %X'2000000'; literal KA0C05_TLMEM$M_TLFADR1_BANKV = %X'4000000'; literal KA0C05_TLMEM$K_VICTIM = 65536; literal KA0C05_TLMEM$K_BUS_READ = 131072; literal KA0C05_TLMEM$K_BUS_WRITE = 196608; literal KA0C05_TLMEM$K_READ_BANK_LOCK = 262144; literal KA0C05_TLMEM$K_WRITE_BANK_UNLCK = 327680; literal KA0C05_TLMEM$K_CSR_READ = 393216; literal KA0C05_TLMEM$K_CSR_WRITE = 458752; literal KA0C05_TLMEM$M_TLESR0_SYND0 = %X'FF'; literal KA0C05_TLMEM$M_TLESR0_SYND1 = %X'FF00'; literal KA0C05_TLMEM$M_TLESR0_TDE = %X'10000'; literal KA0C05_TLMEM$M_TLESR0_TCE = %X'20000'; literal KA0C05_TLMEM$M_TLESR0_DVTCE = %X'40000'; literal KA0C05_TLMEM$M_TLESR0_UECC = %X'80000'; literal KA0C05_TLMEM$M_TLESR0_CWECC = %X'100000'; literal KA0C05_TLMEM$M_TLESR0_CRECC = %X'200000'; literal KA0C05_TLMEM$M_TLESR0_LOFSYN = %X'80000000'; literal KA0C05_TLMEM$M_TLESR1_SYND0 = %X'FF'; literal KA0C05_TLMEM$M_TLESR1_SYND1 = %X'FF00'; literal KA0C05_TLMEM$M_TLESR1_TDE = %X'10000'; literal KA0C05_TLMEM$M_TLESR1_TCE = %X'20000'; literal KA0C05_TLMEM$M_TLESR1_DVTCE = %X'40000'; literal KA0C05_TLMEM$M_TLESR1_UECC = %X'80000'; literal KA0C05_TLMEM$M_TLESR1_CWECC = %X'100000'; literal KA0C05_TLMEM$M_TLESR1_CRECC = %X'200000'; literal KA0C05_TLMEM$M_TLESR1_LOFSYN = %X'80000000'; literal KA0C05_TLMEM$M_TLESR2_SYND0 = %X'FF'; literal KA0C05_TLMEM$M_TLESR2_SYND1 = %X'FF00'; literal KA0C05_TLMEM$M_TLESR2_TDE = %X'10000'; literal KA0C05_TLMEM$M_TLESR2_TCE = %X'20000'; literal KA0C05_TLMEM$M_TLESR2_DVTCE = %X'40000'; literal KA0C05_TLMEM$M_TLESR2_UECC = %X'80000'; literal KA0C05_TLMEM$M_TLESR2_CWECC = %X'100000'; literal KA0C05_TLMEM$M_TLESR2_CRECC = %X'200000'; literal KA0C05_TLMEM$M_TLESR2_LOFSYN = %X'80000000'; literal KA0C05_TLMEM$M_TLESR3_SYND0 = %X'FF'; literal KA0C05_TLMEM$M_TLESR3_SYND1 = %X'FF00'; literal KA0C05_TLMEM$M_TLESR3_TDE = %X'10000'; literal KA0C05_TLMEM$M_TLESR3_TCE = %X'20000'; literal KA0C05_TLMEM$M_TLESR3_DVTCE = %X'40000'; literal KA0C05_TLMEM$M_TLESR3_UECC = %X'80000'; literal KA0C05_TLMEM$M_TLESR3_CWECC = %X'100000'; literal KA0C05_TLMEM$M_TLESR3_CRECC = %X'200000'; literal KA0C05_TLMEM$M_TLESR3_LOFSYN = %X'80000000'; literal KA0C05_TLMEM$M_TLSECR_RCV_SDAT = %X'1'; literal KA0C05_TLMEM$M_TLSECR_XMT_SDAT = %X'2'; literal KA0C05_TLMEM$M_TLSECR_SCLK = %X'4'; literal KA0C05_TLMEM$M_TLMIR_INT = %X'7'; literal KA0C05_TLMEM$M_TLMIR_V = %X'80000000'; literal KA0C05_TLMEM$M_TLMCR_DTYP = %X'1'; literal KA0C05_TLMEM$M_TLMCR_STRN = %X'C'; literal KA0C05_TLMEM$M_TLMCR_DTR = %X'30'; literal KA0C05_TLMEM$M_TLMCR_DEFLT = %X'40'; literal KA0C05_TLMEM$M_TLMCR_SHRD = %X'100'; literal KA0C05_TLMEM$M_TLMCR_OPTION = %X'200'; literal KA0C05_TLMEM$M_TLMCR_BDC = %X'10000000'; literal KA0C05_TLMEM$M_TLMCR_BREN = %X'20000000'; literal KA0C05_TLMEM$M_TLMCR_BDIS = %X'40000000'; literal KA0C05_TLMEM$M_TLMCR_BAT = %X'80000000'; literal KA0C05_TLMEM$M_TLSTER_FSTR = %X'7'; literal KA0C05_TLMEM$M_TLSTER_STE0 = %X'10'; literal KA0C05_TLMEM$M_TLSTER_STE1 = %X'20'; literal KA0C05_TLMEM$M_TLSTER_STE2 = %X'40'; literal KA0C05_TLMEM$M_TLSTER_STE3 = %X'80'; literal KA0C05_TLMEM$M_TLMER_FSTR = %X'7'; literal KA0C05_TLMEM$M_TLMDRA_AMEN = %X'1'; literal KA0C05_TLMEM$M_TLMDRA_FRAPE = %X'2'; literal KA0C05_TLMEM$M_TLMDRA_FCAPE = %X'4'; literal KA0C05_TLMEM$M_TLMDRA_MMPS = %X'8'; literal KA0C05_TLMEM$M_TLMDRA_EXST = %X'10'; literal KA0C05_TLMEM$M_TLMDRA_FRUN = %X'20'; literal KA0C05_TLMEM$M_TLMDRA_POEM = %X'40'; literal KA0C05_TLMEM$M_TLMDRA_POEMC = %X'80'; literal KA0C05_TLMEM$M_TLMDRA_DEDA = %X'100'; literal KA0C05_TLMEM$M_TLMDRA_RFR = %X'30000000'; literal KA0C05_TLMEM$M_TLMDRA_BRFSH = %X'40000000'; literal KA0C05_TLMEM$M_TLMDRA_DRFSH = %X'80000000'; literal KA0C05_TLMEM$M_TLMDRB_MADR = %X'FFFFFFFF'; literal KA0C05_TLMEM$M_TLSTDERE_0_STE = %X'FFFF'; literal KA0C05_TLMEM$M_TLSTDERE_0_VRC = %X'70000'; literal KA0C05_TLMEM$M_TLDDR0_LOE = %X'1'; literal KA0C05_TLMEM$M_TLDDR0_CDER = %X'2'; literal KA0C05_TLMEM$M_TLDDR0_ICFR = %X'4'; literal KA0C05_TLMEM$M_TLDDR0_PAT = %X'8'; literal KA0C05_TLMEM$M_TLDDR0_CFLP = %X'70'; literal KA0C05_TLMEM$M_TLDDR0_DFLP = %X'3F00'; literal KA0C05_TLMEM$M_TLDDR0_EFLPC = %X'4000'; literal KA0C05_TLMEM$M_TLDDR0_EFLPD = %X'8000'; literal KA0C05_TLMEM$M_TLDDR0_MARG = %X'80000000'; literal KA0C05_TLMEM$M_TLSTDERE_1_STE = %X'FFFF'; literal KA0C05_TLMEM$M_TLSTDERE_1_VRC = %X'70000'; literal KA0C05_TLMEM$M_TLDDR1_LOE = %X'1'; literal KA0C05_TLMEM$M_TLDDR1_CDER = %X'2'; literal KA0C05_TLMEM$M_TLDDR1_ICFR = %X'4'; literal KA0C05_TLMEM$M_TLDDR1_PAT = %X'8'; literal KA0C05_TLMEM$M_TLDDR1_CFLP = %X'70'; literal KA0C05_TLMEM$M_TLDDR1_DFLP = %X'3F00'; literal KA0C05_TLMEM$M_TLDDR1_EFLPC = %X'4000'; literal KA0C05_TLMEM$M_TLDDR1_EFLPD = %X'8000'; literal KA0C05_TLMEM$M_TLDDR1_MARG = %X'80000000'; literal KA0C05_TLMEM$M_TLSTDERE_2_STE = %X'FFFF'; literal KA0C05_TLMEM$M_TLSTDERE_2_VRC = %X'70000'; literal KA0C05_TLMEM$M_TLDDR2_LOE = %X'1'; literal KA0C05_TLMEM$M_TLDDR2_CDER = %X'2'; literal KA0C05_TLMEM$M_TLDDR2_ICFR = %X'4'; literal KA0C05_TLMEM$M_TLDDR2_PAT = %X'8'; literal KA0C05_TLMEM$M_TLDDR2_CFLP = %X'70'; literal KA0C05_TLMEM$M_TLDDR2_DFLP = %X'3F00'; literal KA0C05_TLMEM$M_TLDDR2_EFLPC = %X'4000'; literal KA0C05_TLMEM$M_TLDDR2_EFLPD = %X'8000'; literal KA0C05_TLMEM$M_TLDDR2_MARG = %X'80000000'; literal KA0C05_TLMEM$M_TLSTDERE_3_STE = %X'FFFF'; literal KA0C05_TLMEM$M_TLSTDERE_3_VRC = %X'70000'; literal KA0C05_TLMEM$M_TLDDR3_LOE = %X'1'; literal KA0C05_TLMEM$M_TLDDR3_CDER = %X'2'; literal KA0C05_TLMEM$M_TLDDR3_ICFR = %X'4'; literal KA0C05_TLMEM$M_TLDDR3_PAT = %X'8'; literal KA0C05_TLMEM$M_TLDDR3_CFLP = %X'70'; literal KA0C05_TLMEM$M_TLDDR3_DFLP = %X'3F00'; literal KA0C05_TLMEM$M_TLDDR3_EFLPC = %X'4000'; literal KA0C05_TLMEM$M_TLDDR3_EFLPD = %X'8000'; literal KA0C05_TLMEM$M_TLDDR3_MARG = %X'80000000'; literal KA0C05_TLMEM$S_KA0C05_TLMEM = 40960; macro KA0C05_TLMEM$L_TLDEV = 0,0,32,0 %; macro KA0C05_TLMEM$V_TLDEV_DTYPE = 0,0,16,0 %; literal KA0C05_TLMEM$S_TLDEV_DTYPE = 16; macro KA0C05_TLMEM$V_TLDEV_SWREV = 0,16,8,0 %; literal KA0C05_TLMEM$S_TLDEV_SWREV = 8; macro KA0C05_TLMEM$V_TLDEV_HWREV = 0,24,8,0 %; literal KA0C05_TLMEM$S_TLDEV_HWREV = 8; macro KA0C05_TLMEM$b_fill900 = 4,0,0,0 %; literal KA0C05_TLMEM$s_fill900 = 60; macro KA0C05_TLMEM$L_TLBER = 64,0,32,0 %; macro KA0C05_TLMEM$V_TLBER_ATCE = 64,0,1,0 %; macro KA0C05_TLMEM$V_TLBER_APE = 64,1,1,0 %; macro KA0C05_TLMEM$V_TLBER_BBE = 64,2,1,0 %; macro KA0C05_TLMEM$V_TLBER_LKTO = 64,3,1,0 %; macro KA0C05_TLMEM$V_TLBER_NAE = 64,4,1,0 %; macro KA0C05_TLMEM$V_TLBER_RTCE = 64,5,1,0 %; macro KA0C05_TLMEM$V_TLBER_ACKTCE = 64,6,1,0 %; macro KA0C05_TLMEM$V_TLBER_MMRE = 64,7,1,0 %; macro KA0C05_TLMEM$V_TLBER_FNAE = 64,8,1,0 %; macro KA0C05_TLMEM$V_TLBER_REQDE = 64,9,1,0 %; macro KA0C05_TLMEM$V_TLBER_ATDE = 64,10,1,0 %; macro KA0C05_TLMEM$V_TLBER_UDE = 64,16,1,0 %; macro KA0C05_TLMEM$V_TLBER_CWDE = 64,17,1,0 %; macro KA0C05_TLMEM$V_TLBER_CRDE = 64,18,1,0 %; macro KA0C05_TLMEM$V_TLBER_DS0 = 64,20,1,0 %; macro KA0C05_TLMEM$V_TLBER_DS1 = 64,21,1,0 %; macro KA0C05_TLMEM$V_TLBER_DS2 = 64,22,1,0 %; macro KA0C05_TLMEM$V_TLBER_DS3 = 64,23,1,0 %; macro KA0C05_TLMEM$V_TLBER_DTDE = 64,24,1,0 %; macro KA0C05_TLMEM$V_TLBER_FDTCE = 64,25,1,0 %; macro KA0C05_TLMEM$V_TLBER_UACKE = 64,26,1,0 %; macro KA0C05_TLMEM$V_TLBER_ABTCE = 64,27,1,0 %; macro KA0C05_TLMEM$V_TLBER_DCTCE = 64,28,1,0 %; macro KA0C05_TLMEM$V_TLBER_SEQE = 64,29,1,0 %; macro KA0C05_TLMEM$V_TLBER_DSE = 64,30,1,0 %; macro KA0C05_TLMEM$V_TLBER_DTO = 64,31,1,0 %; macro KA0C05_TLMEM$b_fill910 = 68,0,0,0 %; literal KA0C05_TLMEM$s_fill910 = 60; macro KA0C05_TLMEM$L_TLCNR = 128,0,32,0 %; macro KA0C05_TLMEM$V_TLCNR_CWDD = 128,0,1,0 %; macro KA0C05_TLMEM$V_TLCNR_CRDD = 128,1,1,0 %; macro KA0C05_TLMEM$V_TLCNR_LKTOD = 128,2,1,0 %; macro KA0C05_TLMEM$V_TLCNR_DTOD = 128,3,1,0 %; macro KA0C05_TLMEM$V_TLCNR_NODE_ID = 128,4,4,0 %; literal KA0C05_TLMEM$S_TLCNR_NODE_ID = 4; macro KA0C05_TLMEM$V_TLCNR_VCNT = 128,8,4,0 %; literal KA0C05_TLMEM$S_TLCNR_VCNT = 4; macro KA0C05_TLMEM$V_TLCNR_STF_A = 128,12,1,0 %; macro KA0C05_TLMEM$V_TLCNR_STF_B = 128,13,1,0 %; macro KA0C05_TLMEM$V_TLCNR_STF_C = 128,14,1,0 %; macro KA0C05_TLMEM$V_TLCNR_STF_D = 128,15,1,0 %; macro KA0C05_TLMEM$V_TLCNR_STF_E = 128,16,1,0 %; macro KA0C05_TLMEM$V_TLCNR_STF_F = 128,17,1,0 %; macro KA0C05_TLMEM$V_TLCNR_STF_G = 128,18,1,0 %; macro KA0C05_TLMEM$V_TLCNR_STF_H = 128,19,1,0 %; macro KA0C05_TLMEM$V_TLCNR_HALT_A = 128,20,1,0 %; macro KA0C05_TLMEM$V_TLCNR_HALT_B = 128,21,1,0 %; macro KA0C05_TLMEM$V_TLCNR_HALT_C = 128,22,1,0 %; macro KA0C05_TLMEM$V_TLCNR_HALT_D = 128,23,1,0 %; macro KA0C05_TLMEM$V_TLCNR_HALT_E = 128,24,1,0 %; macro KA0C05_TLMEM$V_TLCNR_HALT_F = 128,25,1,0 %; macro KA0C05_TLMEM$V_TLCNR_HALT_G = 128,26,1,0 %; macro KA0C05_TLMEM$V_TLCNR_HALT_H = 128,27,1,0 %; macro KA0C05_TLMEM$V_TLCNR_RSTSTAT = 128,28,1,0 %; macro KA0C05_TLMEM$V_TLCNR_NRST = 128,30,1,0 %; macro KA0C05_TLMEM$V_TLCNR_LOFE = 128,31,1,0 %; macro KA0C05_TLMEM$b_fill920 = 132,0,0,0 %; literal KA0C05_TLMEM$s_fill920 = 60; macro KA0C05_TLMEM$L_TLVID = 192,0,32,0 %; macro KA0C05_TLMEM$V_VID_A = 192,0,4,0 %; literal KA0C05_TLMEM$S_VID_A = 4; macro KA0C05_TLMEM$V_VID_B = 192,4,4,0 %; literal KA0C05_TLMEM$S_VID_B = 4; macro KA0C05_TLMEM$V_VID_C = 192,8,4,0 %; literal KA0C05_TLMEM$S_VID_C = 4; macro KA0C05_TLMEM$V_VID_D = 192,12,4,0 %; literal KA0C05_TLMEM$S_VID_D = 4; macro KA0C05_TLMEM$V_VID_E = 192,16,4,0 %; literal KA0C05_TLMEM$S_VID_E = 4; macro KA0C05_TLMEM$V_VID_F = 192,20,4,0 %; literal KA0C05_TLMEM$S_VID_F = 4; macro KA0C05_TLMEM$V_VID_G = 192,24,4,0 %; literal KA0C05_TLMEM$S_VID_G = 4; macro KA0C05_TLMEM$V_VID_H = 192,28,4,0 %; literal KA0C05_TLMEM$S_VID_H = 4; macro KA0C05_TLMEM$b_fill930 = 196,0,0,0 %; literal KA0C05_TLMEM$s_fill930 = 1340; macro KA0C05_TLMEM$L_TLFADR0 = 1536,0,32,0 %; macro KA0C05_TLMEM$V_TLFADR0_FADR = 1536,3,29,0 %; literal KA0C05_TLMEM$S_TLFADR0_FADR = 29; macro KA0C05_TLMEM$b_fill940 = 1540,0,0,0 %; literal KA0C05_TLMEM$s_fill940 = 60; macro KA0C05_TLMEM$L_TLFADR1 = 1600,0,32,0 %; macro KA0C05_TLMEM$V_TLFADR1_FADR = 1600,0,8,0 %; literal KA0C05_TLMEM$S_TLFADR1_FADR = 8; macro KA0C05_TLMEM$V_TLFADR1_FCMD = 1600,16,3,0 %; literal KA0C05_TLMEM$S_TLFADR1_FCMD = 3; macro KA0C05_TLMEM$V_TLFADR1_FBANK = 1600,20,4,0 %; literal KA0C05_TLMEM$S_TLFADR1_FBANK = 4; macro KA0C05_TLMEM$V_TLFADR1_ADRV = 1600,24,1,0 %; macro KA0C05_TLMEM$V_TLFADR1_CMDV = 1600,25,1,0 %; macro KA0C05_TLMEM$V_TLFADR1_BANKV = 1600,26,1,0 %; macro KA0C05_TLMEM$b_fill950 = 1604,0,0,0 %; literal KA0C05_TLMEM$s_fill950 = 60; macro KA0C05_TLMEM$L_TLESR0 = 1664,0,32,0 %; macro KA0C05_TLMEM$V_TLESR0_SYND0 = 1664,0,8,0 %; literal KA0C05_TLMEM$S_TLESR0_SYND0 = 8; macro KA0C05_TLMEM$V_TLESR0_SYND1 = 1664,8,8,0 %; literal KA0C05_TLMEM$S_TLESR0_SYND1 = 8; macro KA0C05_TLMEM$V_TLESR0_TDE = 1664,16,1,0 %; macro KA0C05_TLMEM$V_TLESR0_TCE = 1664,17,1,0 %; macro KA0C05_TLMEM$V_TLESR0_DVTCE = 1664,18,1,0 %; macro KA0C05_TLMEM$V_TLESR0_UECC = 1664,19,1,0 %; macro KA0C05_TLMEM$V_TLESR0_CWECC = 1664,20,1,0 %; macro KA0C05_TLMEM$V_TLESR0_CRECC = 1664,21,1,0 %; macro KA0C05_TLMEM$V_TLESR0_LOFSYN = 1664,31,1,0 %; macro KA0C05_TLMEM$b_fill960 = 1668,0,0,0 %; literal KA0C05_TLMEM$s_fill960 = 60; macro KA0C05_TLMEM$L_TLESR1 = 1728,0,32,0 %; macro KA0C05_TLMEM$V_TLESR1_SYND0 = 1728,0,8,0 %; literal KA0C05_TLMEM$S_TLESR1_SYND0 = 8; macro KA0C05_TLMEM$V_TLESR1_SYND1 = 1728,8,8,0 %; literal KA0C05_TLMEM$S_TLESR1_SYND1 = 8; macro KA0C05_TLMEM$V_TLESR1_TDE = 1728,16,1,0 %; macro KA0C05_TLMEM$V_TLESR1_TCE = 1728,17,1,0 %; macro KA0C05_TLMEM$V_TLESR1_DVTCE = 1728,18,1,0 %; macro KA0C05_TLMEM$V_TLESR1_UECC = 1728,19,1,0 %; macro KA0C05_TLMEM$V_TLESR1_CWECC = 1728,20,1,0 %; macro KA0C05_TLMEM$V_TLESR1_CRECC = 1728,21,1,0 %; macro KA0C05_TLMEM$V_TLESR1_LOFSYN = 1728,31,1,0 %; macro KA0C05_TLMEM$b_fill970 = 1732,0,0,0 %; literal KA0C05_TLMEM$s_fill970 = 60; macro KA0C05_TLMEM$L_TLESR2 = 1792,0,32,0 %; macro KA0C05_TLMEM$V_TLESR2_SYND0 = 1792,0,8,0 %; literal KA0C05_TLMEM$S_TLESR2_SYND0 = 8; macro KA0C05_TLMEM$V_TLESR2_SYND1 = 1792,8,8,0 %; literal KA0C05_TLMEM$S_TLESR2_SYND1 = 8; macro KA0C05_TLMEM$V_TLESR2_TDE = 1792,16,1,0 %; macro KA0C05_TLMEM$V_TLESR2_TCE = 1792,17,1,0 %; macro KA0C05_TLMEM$V_TLESR2_DVTCE = 1792,18,1,0 %; macro KA0C05_TLMEM$V_TLESR2_UECC = 1792,19,1,0 %; macro KA0C05_TLMEM$V_TLESR2_CWECC = 1792,20,1,0 %; macro KA0C05_TLMEM$V_TLESR2_CRECC = 1792,21,1,0 %; macro KA0C05_TLMEM$V_TLESR2_LOFSYN = 1792,31,1,0 %; macro KA0C05_TLMEM$b_fill980 = 1796,0,0,0 %; literal KA0C05_TLMEM$s_fill980 = 60; macro KA0C05_TLMEM$L_TLESR3 = 1856,0,32,0 %; macro KA0C05_TLMEM$V_TLESR3_SYND0 = 1856,0,8,0 %; literal KA0C05_TLMEM$S_TLESR3_SYND0 = 8; macro KA0C05_TLMEM$V_TLESR3_SYND1 = 1856,8,8,0 %; literal KA0C05_TLMEM$S_TLESR3_SYND1 = 8; macro KA0C05_TLMEM$V_TLESR3_TDE = 1856,16,1,0 %; macro KA0C05_TLMEM$V_TLESR3_TCE = 1856,17,1,0 %; macro KA0C05_TLMEM$V_TLESR3_DVTCE = 1856,18,1,0 %; macro KA0C05_TLMEM$V_TLESR3_UECC = 1856,19,1,0 %; macro KA0C05_TLMEM$V_TLESR3_CWECC = 1856,20,1,0 %; macro KA0C05_TLMEM$V_TLESR3_CRECC = 1856,21,1,0 %; macro KA0C05_TLMEM$V_TLESR3_LOFSYN = 1856,31,1,0 %; macro KA0C05_TLMEM$b_fill990 = 1860,0,0,0 %; literal KA0C05_TLMEM$s_fill990 = 4284; macro KA0C05_TLMEM$L_TLSECR = 6144,0,32,0 %; macro KA0C05_TLMEM$V_TLSECR_RCV_SDAT = 6144,0,1,0 %; macro KA0C05_TLMEM$V_TLSECR_XMT_SDAT = 6144,1,1,0 %; macro KA0C05_TLMEM$V_TLSECR_SCLK = 6144,2,1,0 %; macro KA0C05_TLMEM$b_f1000 = 6148,0,0,0 %; literal KA0C05_TLMEM$s_f1000 = 60; macro KA0C05_TLMEM$L_TLMIR = 6208,0,32,0 %; macro KA0C05_TLMEM$V_TLMIR_INT = 6208,0,3,0 %; literal KA0C05_TLMEM$S_TLMIR_INT = 3; macro KA0C05_TLMEM$V_TLMIR_V = 6208,31,1,0 %; macro KA0C05_TLMEM$b_f1010 = 6212,0,0,0 %; literal KA0C05_TLMEM$s_f1010 = 60; macro KA0C05_TLMEM$L_TLMCR = 6272,0,32,0 %; macro KA0C05_TLMEM$V_TLMCR_DTYP = 6272,0,1,0 %; macro KA0C05_TLMEM$V_TLMCR_STRN = 6272,2,2,0 %; literal KA0C05_TLMEM$S_TLMCR_STRN = 2; macro KA0C05_TLMEM$V_TLMCR_DTR = 6272,4,2,0 %; literal KA0C05_TLMEM$S_TLMCR_DTR = 2; macro KA0C05_TLMEM$V_TLMCR_DEFLT = 6272,6,1,0 %; macro KA0C05_TLMEM$V_TLMCR_SHRD = 6272,8,1,0 %; macro KA0C05_TLMEM$V_TLMCR_OPTION = 6272,9,1,0 %; macro KA0C05_TLMEM$V_TLMCR_BDC = 6272,28,1,0 %; macro KA0C05_TLMEM$V_TLMCR_BREN = 6272,29,1,0 %; macro KA0C05_TLMEM$V_TLMCR_BDIS = 6272,30,1,0 %; macro KA0C05_TLMEM$V_TLMCR_BAT = 6272,31,1,0 %; macro KA0C05_TLMEM$b_f1020 = 6276,0,0,0 %; literal KA0C05_TLMEM$s_f1020 = 60; macro KA0C05_TLMEM$L_TLSTAIR = 6336,0,32,0 %; macro KA0C05_TLMEM$b_f1030 = 6340,0,0,0 %; literal KA0C05_TLMEM$s_f1030 = 60; macro KA0C05_TLMEM$L_TLSTER = 6400,0,32,0 %; macro KA0C05_TLMEM$V_TLSTER_FSTR = 6400,0,3,0 %; literal KA0C05_TLMEM$S_TLSTER_FSTR = 3; macro KA0C05_TLMEM$V_TLSTER_STE0 = 6400,4,1,0 %; macro KA0C05_TLMEM$V_TLSTER_STE1 = 6400,5,1,0 %; macro KA0C05_TLMEM$V_TLSTER_STE2 = 6400,6,1,0 %; macro KA0C05_TLMEM$V_TLSTER_STE3 = 6400,7,1,0 %; macro KA0C05_TLMEM$b_f1040 = 6404,0,0,0 %; literal KA0C05_TLMEM$s_f1040 = 60; macro KA0C05_TLMEM$L_TLMER = 6464,0,32,0 %; macro KA0C05_TLMEM$V_TLMER_FSTR = 6464,0,3,0 %; literal KA0C05_TLMEM$S_TLMER_FSTR = 3; macro KA0C05_TLMEM$b_f1050 = 6468,0,0,0 %; literal KA0C05_TLMEM$s_f1050 = 60; macro KA0C05_TLMEM$L_TLMDRA = 6528,0,32,0 %; macro KA0C05_TLMEM$V_TLMDRA_AMEN = 6528,0,1,0 %; macro KA0C05_TLMEM$V_TLMDRA_FRAPE = 6528,1,1,0 %; macro KA0C05_TLMEM$V_TLMDRA_FCAPE = 6528,2,1,0 %; macro KA0C05_TLMEM$V_TLMDRA_MMPS = 6528,3,1,0 %; macro KA0C05_TLMEM$V_TLMDRA_EXST = 6528,4,1,0 %; macro KA0C05_TLMEM$V_TLMDRA_FRUN = 6528,5,1,0 %; macro KA0C05_TLMEM$V_TLMDRA_POEM = 6528,6,1,0 %; macro KA0C05_TLMEM$V_TLMDRA_POEMC = 6528,7,1,0 %; macro KA0C05_TLMEM$V_TLMDRA_DEDA = 6528,8,1,0 %; macro KA0C05_TLMEM$V_TLMDRA_RFR = 6528,28,2,0 %; literal KA0C05_TLMEM$S_TLMDRA_RFR = 2; macro KA0C05_TLMEM$V_TLMDRA_BRFSH = 6528,30,1,0 %; macro KA0C05_TLMEM$V_TLMDRA_DRFSH = 6528,31,1,0 %; macro KA0C05_TLMEM$b_f1060 = 6532,0,0,0 %; literal KA0C05_TLMEM$s_f1060 = 60; macro KA0C05_TLMEM$L_TLMDRB = 6592,0,32,0 %; macro KA0C05_TLMEM$V_TLMDRB_MADR = 6592,0,32,0 %; literal KA0C05_TLMEM$S_TLMDRB_MADR = 32; macro KA0C05_TLMEM$b_f1070 = 6596,0,0,0 %; literal KA0C05_TLMEM$s_f1070 = 1596; macro KA0C05_TLMEM$L_TLSTDERA_0 = 8192,0,32,0 %; macro KA0C05_TLMEM$b_f1080 = 8196,0,0,0 %; literal KA0C05_TLMEM$s_f1080 = 60; macro KA0C05_TLMEM$L_TLSTDERB_0 = 8256,0,32,0 %; macro KA0C05_TLMEM$b_f1090 = 8260,0,0,0 %; literal KA0C05_TLMEM$s_f1090 = 60; macro KA0C05_TLMEM$L_TLSTDERC_0 = 8320,0,32,0 %; macro KA0C05_TLMEM$b_f1100 = 8324,0,0,0 %; literal KA0C05_TLMEM$s_f1100 = 60; macro KA0C05_TLMEM$L_TLSTDERD_0 = 8384,0,32,0 %; macro KA0C05_TLMEM$b_f1110 = 8388,0,0,0 %; literal KA0C05_TLMEM$s_f1110 = 60; macro KA0C05_TLMEM$L_TLSTDERE_0 = 8448,0,32,0 %; macro KA0C05_TLMEM$V_TLSTDERE_0_STE = 8448,0,16,0 %; literal KA0C05_TLMEM$S_TLSTDERE_0_STE = 16; macro KA0C05_TLMEM$V_TLSTDERE_0_VRC = 8448,16,3,0 %; literal KA0C05_TLMEM$S_TLSTDERE_0_VRC = 3; macro KA0C05_TLMEM$b_f1120 = 8452,0,0,0 %; literal KA0C05_TLMEM$s_f1120 = 60; macro KA0C05_TLMEM$L_TLDDR0 = 8512,0,32,0 %; macro KA0C05_TLMEM$V_TLDDR0_LOE = 8512,0,1,0 %; macro KA0C05_TLMEM$V_TLDDR0_CDER = 8512,1,1,0 %; macro KA0C05_TLMEM$V_TLDDR0_ICFR = 8512,2,1,0 %; macro KA0C05_TLMEM$V_TLDDR0_PAT = 8512,3,1,0 %; macro KA0C05_TLMEM$V_TLDDR0_CFLP = 8512,4,3,0 %; literal KA0C05_TLMEM$S_TLDDR0_CFLP = 3; macro KA0C05_TLMEM$V_TLDDR0_DFLP = 8512,8,6,0 %; literal KA0C05_TLMEM$S_TLDDR0_DFLP = 6; macro KA0C05_TLMEM$V_TLDDR0_EFLPC = 8512,14,1,0 %; macro KA0C05_TLMEM$V_TLDDR0_EFLPD = 8512,15,1,0 %; macro KA0C05_TLMEM$V_TLDDR0_MARG = 8512,31,1,0 %; macro KA0C05_TLMEM$b_f1130 = 8516,0,0,0 %; literal KA0C05_TLMEM$s_f1130 = 7868; macro KA0C05_TLMEM$L_TLSTDERA_1 = 16384,0,32,0 %; macro KA0C05_TLMEM$b_f1140 = 16388,0,0,0 %; literal KA0C05_TLMEM$s_f1140 = 60; macro KA0C05_TLMEM$L_TLSTDERB_1 = 16448,0,32,0 %; macro KA0C05_TLMEM$b_f1150 = 16452,0,0,0 %; literal KA0C05_TLMEM$s_f1150 = 60; macro KA0C05_TLMEM$L_TLSTDERC_1 = 16512,0,32,0 %; macro KA0C05_TLMEM$b_f1160 = 16516,0,0,0 %; literal KA0C05_TLMEM$s_f1160 = 60; macro KA0C05_TLMEM$L_TLSTDERD_1 = 16576,0,32,0 %; macro KA0C05_TLMEM$b_f1170 = 16580,0,0,0 %; literal KA0C05_TLMEM$s_f1170 = 60; macro KA0C05_TLMEM$L_TLSTDERE_1 = 16640,0,32,0 %; macro KA0C05_TLMEM$V_TLSTDERE_1_STE = 16640,0,16,0 %; literal KA0C05_TLMEM$S_TLSTDERE_1_STE = 16; macro KA0C05_TLMEM$V_TLSTDERE_1_VRC = 16640,16,3,0 %; literal KA0C05_TLMEM$S_TLSTDERE_1_VRC = 3; macro KA0C05_TLMEM$b_f1180 = 16644,0,0,0 %; literal KA0C05_TLMEM$s_f1180 = 60; macro KA0C05_TLMEM$L_TLDDR1 = 16704,0,32,0 %; macro KA0C05_TLMEM$V_TLDDR1_LOE = 16704,0,1,0 %; macro KA0C05_TLMEM$V_TLDDR1_CDER = 16704,1,1,0 %; macro KA0C05_TLMEM$V_TLDDR1_ICFR = 16704,2,1,0 %; macro KA0C05_TLMEM$V_TLDDR1_PAT = 16704,3,1,0 %; macro KA0C05_TLMEM$V_TLDDR1_CFLP = 16704,4,3,0 %; literal KA0C05_TLMEM$S_TLDDR1_CFLP = 3; macro KA0C05_TLMEM$V_TLDDR1_DFLP = 16704,8,6,0 %; literal KA0C05_TLMEM$S_TLDDR1_DFLP = 6; macro KA0C05_TLMEM$V_TLDDR1_EFLPC = 16704,14,1,0 %; macro KA0C05_TLMEM$V_TLDDR1_EFLPD = 16704,15,1,0 %; macro KA0C05_TLMEM$V_TLDDR1_MARG = 16704,31,1,0 %; macro KA0C05_TLMEM$b_f1190 = 16708,0,0,0 %; literal KA0C05_TLMEM$s_f1190 = 7868; macro KA0C05_TLMEM$L_TLSTDERA_2 = 24576,0,32,0 %; macro KA0C05_TLMEM$b_f1200 = 24580,0,0,0 %; literal KA0C05_TLMEM$s_f1200 = 60; macro KA0C05_TLMEM$L_TLSTDERB_2 = 24640,0,32,0 %; macro KA0C05_TLMEM$b_f1210 = 24644,0,0,0 %; literal KA0C05_TLMEM$s_f1210 = 60; macro KA0C05_TLMEM$L_TLSTDERC_2 = 24704,0,32,0 %; macro KA0C05_TLMEM$b_f1220 = 24708,0,0,0 %; literal KA0C05_TLMEM$s_f1220 = 60; macro KA0C05_TLMEM$L_TLSTDERD_2 = 24768,0,32,0 %; macro KA0C05_TLMEM$b_f1230 = 24772,0,0,0 %; literal KA0C05_TLMEM$s_f1230 = 60; macro KA0C05_TLMEM$L_TLSTDERE_2 = 24832,0,32,0 %; macro KA0C05_TLMEM$V_TLSTDERE_2_STE = 24832,0,16,0 %; literal KA0C05_TLMEM$S_TLSTDERE_2_STE = 16; macro KA0C05_TLMEM$V_TLSTDERE_2_VRC = 24832,16,3,0 %; literal KA0C05_TLMEM$S_TLSTDERE_2_VRC = 3; macro KA0C05_TLMEM$b_f1240 = 24836,0,0,0 %; literal KA0C05_TLMEM$s_f1240 = 60; macro KA0C05_TLMEM$L_TLDDR2 = 24896,0,32,0 %; macro KA0C05_TLMEM$V_TLDDR2_LOE = 24896,0,1,0 %; macro KA0C05_TLMEM$V_TLDDR2_CDER = 24896,1,1,0 %; macro KA0C05_TLMEM$V_TLDDR2_ICFR = 24896,2,1,0 %; macro KA0C05_TLMEM$V_TLDDR2_PAT = 24896,3,1,0 %; macro KA0C05_TLMEM$V_TLDDR2_CFLP = 24896,4,3,0 %; literal KA0C05_TLMEM$S_TLDDR2_CFLP = 3; macro KA0C05_TLMEM$V_TLDDR2_DFLP = 24896,8,6,0 %; literal KA0C05_TLMEM$S_TLDDR2_DFLP = 6; macro KA0C05_TLMEM$V_TLDDR2_EFLPC = 24896,14,1,0 %; macro KA0C05_TLMEM$V_TLDDR2_EFLPD = 24896,15,1,0 %; macro KA0C05_TLMEM$V_TLDDR2_MARG = 24896,31,1,0 %; macro KA0C05_TLMEM$b_f1250 = 24900,0,0,0 %; literal KA0C05_TLMEM$s_f1250 = 7868; macro KA0C05_TLMEM$L_TLSTDERA_3 = 32768,0,32,0 %; macro KA0C05_TLMEM$b_f1260 = 32772,0,0,0 %; literal KA0C05_TLMEM$s_f1260 = 60; macro KA0C05_TLMEM$L_TLSTDERB_3 = 32832,0,32,0 %; macro KA0C05_TLMEM$b_f1270 = 32836,0,0,0 %; literal KA0C05_TLMEM$s_f1270 = 60; macro KA0C05_TLMEM$L_TLSTDERC_3 = 32896,0,32,0 %; macro KA0C05_TLMEM$b_f1280 = 32900,0,0,0 %; literal KA0C05_TLMEM$s_f1280 = 60; macro KA0C05_TLMEM$L_TLSTDERD_3 = 32960,0,32,0 %; macro KA0C05_TLMEM$b_f1290 = 32964,0,0,0 %; literal KA0C05_TLMEM$s_f1290 = 60; macro KA0C05_TLMEM$L_TLSTDERE_3 = 33024,0,32,0 %; macro KA0C05_TLMEM$V_TLSTDERE_3_STE = 33024,0,16,0 %; literal KA0C05_TLMEM$S_TLSTDERE_3_STE = 16; macro KA0C05_TLMEM$V_TLSTDERE_3_VRC = 33024,16,3,0 %; literal KA0C05_TLMEM$S_TLSTDERE_3_VRC = 3; macro KA0C05_TLMEM$b_f1300 = 33028,0,0,0 %; literal KA0C05_TLMEM$s_f1300 = 60; macro KA0C05_TLMEM$L_TLDDR3 = 33088,0,32,0 %; macro KA0C05_TLMEM$V_TLDDR3_LOE = 33088,0,1,0 %; macro KA0C05_TLMEM$V_TLDDR3_CDER = 33088,1,1,0 %; macro KA0C05_TLMEM$V_TLDDR3_ICFR = 33088,2,1,0 %; macro KA0C05_TLMEM$V_TLDDR3_PAT = 33088,3,1,0 %; macro KA0C05_TLMEM$V_TLDDR3_CFLP = 33088,4,3,0 %; literal KA0C05_TLMEM$S_TLDDR3_CFLP = 3; macro KA0C05_TLMEM$V_TLDDR3_DFLP = 33088,8,6,0 %; literal KA0C05_TLMEM$S_TLDDR3_DFLP = 6; macro KA0C05_TLMEM$V_TLDDR3_EFLPC = 33088,14,1,0 %; macro KA0C05_TLMEM$V_TLDDR3_EFLPD = 33088,15,1,0 %; macro KA0C05_TLMEM$V_TLDDR3_MARG = 33088,31,1,0 %; macro KA0C05_TLMEM$b_f1310 = 33092,0,0,0 %; literal KA0C05_TLMEM$s_f1310 = 7868; literal KA0C05_CMD$K_NOP = 0; literal KA0C05_CMD$K_VICTIM = 1; literal KA0C05_CMD$K_BUS_READ = 2; literal KA0C05_CMD$K_BUS_WRITE = 3; literal KA0C05_CMD$K_READ_BANK_LOCK = 4; literal KA0C05_CMD$K_WRITE_BANK_UNLOCK = 5; literal KA0C05_CMD$K_CSR_READ = 6; literal KA0C05_CMD$K_CSR_WRITE = 7; literal KA0C05_TIOP$M_TLDEV_DTYPE = %X'FFFF'; literal KA0C05_TIOP$M_TLDEV_SWREV = %X'FF0000'; literal KA0C05_TIOP$M_TLDEV_HWREV = %X'FF000000'; literal KA0C05_TIOP$M_TLBER_ATCE = %X'1'; literal KA0C05_TIOP$M_TLBER_APE = %X'2'; literal KA0C05_TIOP$M_TLBER_BBE = %X'4'; literal KA0C05_TIOP$M_TLBER_LKTO = %X'8'; literal KA0C05_TIOP$M_TLBER_NAE = %X'10'; literal KA0C05_TIOP$M_TLBER_RTCE = %X'20'; literal KA0C05_TIOP$M_TLBER_ACKTCE = %X'40'; literal KA0C05_TIOP$M_TLBER_MMRE = %X'80'; literal KA0C05_TIOP$M_TLBER_FNAE = %X'100'; literal KA0C05_TIOP$M_TLBER_REQDE = %X'200'; literal KA0C05_TIOP$M_TLBER_ATDE = %X'400'; literal KA0C05_TIOP$M_TLBER_UDE = %X'10000'; literal KA0C05_TIOP$M_TLBER_CWDE = %X'20000'; literal KA0C05_TIOP$M_TLBER_CRDE = %X'40000'; literal KA0C05_TIOP$M_TLBER_DS0 = %X'100000'; literal KA0C05_TIOP$M_TLBER_DS1 = %X'200000'; literal KA0C05_TIOP$M_TLBER_DS2 = %X'400000'; literal KA0C05_TIOP$M_TLBER_DS3 = %X'800000'; literal KA0C05_TIOP$M_TLBER_DTDE = %X'1000000'; literal KA0C05_TIOP$M_TLBER_FDTCE = %X'2000000'; literal KA0C05_TIOP$M_TLBER_UACKE = %X'4000000'; literal KA0C05_TIOP$M_TLBER_ABTCE = %X'8000000'; literal KA0C05_TIOP$M_TLBER_DCTCE = %X'10000000'; literal KA0C05_TIOP$M_TLBER_SEQE = %X'20000000'; literal KA0C05_TIOP$M_TLBER_DSE = %X'40000000'; literal KA0C05_TIOP$M_TLBER_DTO = %X'80000000'; literal KA0C05_TIOP$M_TLCNR_CWDD = %X'1'; literal KA0C05_TIOP$M_TLCNR_CRDD = %X'2'; literal KA0C05_TIOP$M_TLCNR_LKTOD = %X'4'; literal KA0C05_TIOP$M_TLCNR_DTOD = %X'8'; literal KA0C05_TIOP$M_TLCNR_NODE_ID = %X'F0'; literal KA0C05_TIOP$M_TLCNR_VCNT = %X'F00'; literal KA0C05_TIOP$M_TLCNR_STF_A = %X'1000'; literal KA0C05_TIOP$M_TLCNR_STF_B = %X'2000'; literal KA0C05_TIOP$M_TLCNR_STF_C = %X'4000'; literal KA0C05_TIOP$M_TLCNR_STF_D = %X'8000'; literal KA0C05_TIOP$M_TLCNR_STF_E = %X'10000'; literal KA0C05_TIOP$M_TLCNR_STF_F = %X'20000'; literal KA0C05_TIOP$M_TLCNR_STF_G = %X'40000'; literal KA0C05_TIOP$M_TLCNR_STF_H = %X'80000'; literal KA0C05_TIOP$M_TLCNR_HALT_A = %X'100000'; literal KA0C05_TIOP$M_TLCNR_HALT_B = %X'200000'; literal KA0C05_TIOP$M_TLCNR_HALT_C = %X'400000'; literal KA0C05_TIOP$M_TLCNR_HALT_D = %X'800000'; literal KA0C05_TIOP$M_TLCNR_HALT_E = %X'1000000'; literal KA0C05_TIOP$M_TLCNR_HALT_F = %X'2000000'; literal KA0C05_TIOP$M_TLCNR_HALT_G = %X'4000000'; literal KA0C05_TIOP$M_TLCNR_HALT_H = %X'8000000'; literal KA0C05_TIOP$M_TLCNR_RSTSTAT = %X'10000000'; literal KA0C05_TIOP$M_TLCNR_NRST = %X'40000000'; literal KA0C05_TIOP$M_TLCNR_LOFE = %X'80000000'; literal KA0C05_TIOP$M_TLMMR0_INTMASK = %X'3'; literal KA0C05_TIOP$M_TLMMR0_ADRMASK = %X'F0'; literal KA0C05_TIOP$M_TLMMR0_INTLV = %X'700'; literal KA0C05_TIOP$M_TLMMR0_SBANK = %X'800'; literal KA0C05_TIOP$M_TLMMR0_ADDRESS = %X'3FFF000'; literal KA0C05_TIOP$M_TLMMR0_VALID = %X'80000000'; literal KA0C05_TIOP$M_TLMMR1_INTMASK = %X'3'; literal KA0C05_TIOP$M_TLMMR1_ADRMASK = %X'F0'; literal KA0C05_TIOP$M_TLMMR1_INTLV = %X'700'; literal KA0C05_TIOP$M_TLMMR1_SBANK = %X'800'; literal KA0C05_TIOP$M_TLMMR1_ADDRESS = %X'3FFF000'; literal KA0C05_TIOP$M_TLMMR1_VALID = %X'80000000'; literal KA0C05_TIOP$M_TLMMR2_INTMASK = %X'3'; literal KA0C05_TIOP$M_TLMMR2_ADRMASK = %X'F0'; literal KA0C05_TIOP$M_TLMMR2_INTLV = %X'700'; literal KA0C05_TIOP$M_TLMMR2_SBANK = %X'800'; literal KA0C05_TIOP$M_TLMMR2_ADDRESS = %X'3FFF000'; literal KA0C05_TIOP$M_TLMMR2_VALID = %X'80000000'; literal KA0C05_TIOP$M_TLMMR3_INTMASK = %X'3'; literal KA0C05_TIOP$M_TLMMR3_ADRMASK = %X'F0'; literal KA0C05_TIOP$M_TLMMR3_INTLV = %X'700'; literal KA0C05_TIOP$M_TLMMR3_SBANK = %X'800'; literal KA0C05_TIOP$M_TLMMR3_ADDRESS = %X'3FFF000'; literal KA0C05_TIOP$M_TLMMR3_VALID = %X'80000000'; literal KA0C05_TIOP$M_TLMMR4_INTMASK = %X'3'; literal KA0C05_TIOP$M_TLMMR4_ADRMASK = %X'F0'; literal KA0C05_TIOP$M_TLMMR4_INTLV = %X'700'; literal KA0C05_TIOP$M_TLMMR4_SBANK = %X'800'; literal KA0C05_TIOP$M_TLMMR4_ADDRESS = %X'3FFF000'; literal KA0C05_TIOP$M_TLMMR4_VALID = %X'80000000'; literal KA0C05_TIOP$M_TLMMR5_INTMASK = %X'3'; literal KA0C05_TIOP$M_TLMMR5_ADRMASK = %X'F0'; literal KA0C05_TIOP$M_TLMMR5_INTLV = %X'700'; literal KA0C05_TIOP$M_TLMMR5_SBANK = %X'800'; literal KA0C05_TIOP$M_TLMMR5_ADDRESS = %X'3FFF000'; literal KA0C05_TIOP$M_TLMMR5_VALID = %X'80000000'; literal KA0C05_TIOP$M_TLMMR6_INTMASK = %X'3'; literal KA0C05_TIOP$M_TLMMR6_ADRMASK = %X'F0'; literal KA0C05_TIOP$M_TLMMR6_INTLV = %X'700'; literal KA0C05_TIOP$M_TLMMR6_SBANK = %X'800'; literal KA0C05_TIOP$M_TLMMR6_ADDRESS = %X'3FFF000'; literal KA0C05_TIOP$M_TLMMR6_VALID = %X'80000000'; literal KA0C05_TIOP$M_TLMMR7_INTMASK = %X'3'; literal KA0C05_TIOP$M_TLMMR7_ADRMASK = %X'F0'; literal KA0C05_TIOP$M_TLMMR7_INTLV = %X'700'; literal KA0C05_TIOP$M_TLMMR7_SBANK = %X'800'; literal KA0C05_TIOP$M_TLMMR7_ADDRESS = %X'3FFF000'; literal KA0C05_TIOP$M_TLMMR7_VALID = %X'80000000'; literal KA0C05_TIOP$M_TLFADR0_FADR = %X'FFFFFFF8'; literal KA0C05_TIOP$M_TLFADR1_FADR = %X'FF'; literal KA0C05_TIOP$M_TLFADR1_FCMD = %X'70000'; literal KA0C05_TIOP$M_TLFADR1_FBANK = %X'F00000'; literal KA0C05_TIOP$M_TLFADR1_ADRV = %X'1000000'; literal KA0C05_TIOP$M_TLFADR1_CMDV = %X'2000000'; literal KA0C05_TIOP$M_TLFADR1_BANKV = %X'4000000'; literal KA0C05_TIOP$M_TLESR0_SYND0 = %X'FF'; literal KA0C05_TIOP$M_TLESR0_SYND1 = %X'FF00'; literal KA0C05_TIOP$M_TLESR0_TDE = %X'10000'; literal KA0C05_TIOP$M_TLESR0_TCE = %X'20000'; literal KA0C05_TIOP$M_TLESR0_DVTCE = %X'40000'; literal KA0C05_TIOP$M_TLESR0_UECC = %X'80000'; literal KA0C05_TIOP$M_TLESR0_CWECC = %X'100000'; literal KA0C05_TIOP$M_TLESR0_CRECC = %X'200000'; literal KA0C05_TIOP$M_TLESR0_LOFSYN = %X'80000000'; literal KA0C05_TIOP$M_TLESR1_SYND0 = %X'FF'; literal KA0C05_TIOP$M_TLESR1_SYND1 = %X'FF00'; literal KA0C05_TIOP$M_TLESR1_TDE = %X'10000'; literal KA0C05_TIOP$M_TLESR1_TCE = %X'20000'; literal KA0C05_TIOP$M_TLESR1_DVTCE = %X'40000'; literal KA0C05_TIOP$M_TLESR1_UECC = %X'80000'; literal KA0C05_TIOP$M_TLESR1_CWECC = %X'100000'; literal KA0C05_TIOP$M_TLESR1_CRECC = %X'200000'; literal KA0C05_TIOP$M_TLESR1_LOFSYN = %X'80000000'; literal KA0C05_TIOP$M_TLESR2_SYND0 = %X'FF'; literal KA0C05_TIOP$M_TLESR2_SYND1 = %X'FF00'; literal KA0C05_TIOP$M_TLESR2_TDE = %X'10000'; literal KA0C05_TIOP$M_TLESR2_TCE = %X'20000'; literal KA0C05_TIOP$M_TLESR2_DVTCE = %X'40000'; literal KA0C05_TIOP$M_TLESR2_UECC = %X'80000'; literal KA0C05_TIOP$M_TLESR2_CWECC = %X'100000'; literal KA0C05_TIOP$M_TLESR2_CRECC = %X'200000'; literal KA0C05_TIOP$M_TLESR2_LOFSYN = %X'80000000'; literal KA0C05_TIOP$M_TLESR3_SYND0 = %X'FF'; literal KA0C05_TIOP$M_TLESR3_SYND1 = %X'FF00'; literal KA0C05_TIOP$M_TLESR3_TDE = %X'10000'; literal KA0C05_TIOP$M_TLESR3_TCE = %X'20000'; literal KA0C05_TIOP$M_TLESR3_DVTCE = %X'40000'; literal KA0C05_TIOP$M_TLESR3_UECC = %X'80000'; literal KA0C05_TIOP$M_TLESR3_CWECC = %X'100000'; literal KA0C05_TIOP$M_TLESR3_CRECC = %X'200000'; literal KA0C05_TIOP$M_TLESR3_LOFSYN = %X'80000000'; literal KA0C05_TIOP$M_TLILID0_IDENT = %X'FFFF'; literal KA0C05_TIOP$M_TLILID1_IDENT = %X'FFFF'; literal KA0C05_TIOP$M_TLILID2_IDENT = %X'FFFF'; literal KA0C05_TIOP$M_TLILID3_IDENT = %X'FFFF'; literal KA0C05_TIOP$M_TLCPUMASK_MASK = %X'FFFF'; literal KA0C05_TIOP$M_TLRMR0A_MASK = %X'F'; literal KA0C05_TIOP$M_TLRMR0A_ILV_EN = %X'10'; literal KA0C05_TIOP$M_TLRMR0A_BADR = %X'FFFFF00'; literal KA0C05_TIOP$M_TLRMR0A_NVRAM = %X'40000000'; literal KA0C05_TIOP$M_TLRMR0A_VALID = %X'80000000'; literal KA0C05_TIOP$M_TLRMR0B_MASK = %X'F'; literal KA0C05_TIOP$M_TLRMR0B_ILV_EN = %X'10'; literal KA0C05_TIOP$M_TLRMR0B_BADR = %X'FFFFF00'; literal KA0C05_TIOP$M_TLRMR0B_NVRAM = %X'40000000'; literal KA0C05_TIOP$M_TLRMR0B_VALID = %X'80000000'; literal KA0C05_TIOP$M_TLRMR1A_MASK = %X'F'; literal KA0C05_TIOP$M_TLRMR1A_ILV_EN = %X'10'; literal KA0C05_TIOP$M_TLRMR1A_BADR = %X'FFFFF00'; literal KA0C05_TIOP$M_TLRMR1A_NVRAM = %X'40000000'; literal KA0C05_TIOP$M_TLRMR1A_VALID = %X'80000000'; literal KA0C05_TIOP$M_TLRMR1B_MASK = %X'F'; literal KA0C05_TIOP$M_TLRMR1B_ILV_EN = %X'10'; literal KA0C05_TIOP$M_TLRMR1B_BADR = %X'FFFFF00'; literal KA0C05_TIOP$M_TLRMR1B_NVRAM = %X'40000000'; literal KA0C05_TIOP$M_TLRMR1B_VALID = %X'80000000'; literal KA0C05_TIOP$M_TLICMSR_ARB_CTL = %X'3'; literal KA0C05_TIOP$M_TLICMSR_SUP_CTL = %X'C'; literal KA0C05_TIOP$M_TLICMSR_FORCE_ACK = %X'10'; literal KA0C05_TIOP$M_TLICMSR_RMNXM = %X'20'; literal KA0C05_TIOP$M_TLICMSR_ACK_DSBL = %X'40'; literal KA0C05_TIOP$M_TLICNSE_ACK_DROP = %X'4'; literal KA0C05_TIOP$M_TLICNSE_RMNXM = %X'8'; literal KA0C05_TIOP$M_TLICNSE_MBX_STAT = %X'F0'; literal KA0C05_TIOP$M_TLICNSE_OFLO = %X'F00'; literal KA0C05_TIOP$M_TLICNSE_PKT_E = %X'F000'; literal KA0C05_TIOP$M_TLICNSE_PAR_E = %X'F0000'; literal KA0C05_TIOP$M_TLICNSE_UP_HDP_IE = %X'300000'; literal KA0C05_TIOP$M_TLICNSE_INT_E = %X'400000'; literal KA0C05_TIOP$M_TLICNSE_DN_VRTX_E = %X'1800000'; literal KA0C05_TIOP$M_TLICNSE_UP_VRTX_E = %X'6000000'; literal KA0C05_TIOP$M_TLICNSE_IE = %X'8000000'; literal KA0C05_TIOP$M_TLICNSE_BUS_PE = %X'10000000'; literal KA0C05_TIOP$M_TLICNSE_WND_OFLO = %X'20000000'; literal KA0C05_TIOP$M_TLICNSE_RM_OFLO = %X'40000000'; literal KA0C05_TIOP$M_TLICNSE_INT_NSES = %X'80000000'; literal KA0C05_TIOP$M_TLICDR_IDP_PE = %X'1'; literal KA0C05_TIOP$M_TLICDR_DSE = %X'2'; literal KA0C05_TIOP$M_TLICDR_DTO = %X'4'; literal KA0C05_TIOP$M_TLICDR_DIS_CMD = %X'8'; literal KA0C05_TIOP$M_TLICDR_DIS_FLT = %X'10'; literal KA0C05_TIOP$M_TLICDR_CMD_PE = %X'20'; literal KA0C05_TIOP$M_TLICDR_BNK_BSY = %X'40'; literal KA0C05_TIOP$M_TLICDR_IDP_CMD_PE = %X'100'; literal KA0C05_TIOP$M_TLICDR_EN_HID = %X'80000000'; literal KA0C05_TIOP$M_TLICMTR_MBX_TIP = %X'F'; literal KA0C05_TIOP$M_TLICWRT_WIP = %X'F'; literal KA0C05_TIOP$M_TLIDPNSE_ERR = %X'1'; literal KA0C05_TIOP$M_TLIDPNSE_POK = %X'2'; literal KA0C05_TIOP$M_TLIDPNSE_CBLOK = %X'4'; literal KA0C05_TIOP$M_TLIDPNSE_POK_TRAN = %X'8'; literal KA0C05_TIOP$M_TLIDPNSE_SOFT_ERR = %X'10'; literal KA0C05_TIOP$M_TLIDPNSE_RM_M_ERR = %X'C00000'; literal KA0C05_TIOP$M_TLIDPNSE_CPE = %X'1000000'; literal KA0C05_TIOP$M_TLIDPNSE_UP_V_ERR = %X'6000000'; literal KA0C05_TIOP$M_TLIDPNSE_IE = %X'8000000'; literal KA0C05_TIOP$M_TLIDPNSE_PE = %X'10000000'; literal KA0C05_TIOP$M_TLIDPNSE_RESET = %X'80000000'; literal KA0C05_TIOP$M_TLIPMASK_CPU = %X'FFFF'; literal KA0C05_TIOP$M_TLIDPVR_VECTOR = %X'FFFF'; literal KA0C05_TIOP$M_TLIBR_RCV_SDAT = %X'1'; literal KA0C05_TIOP$M_TLIBR_XMT_SDAT = %X'2'; literal KA0C05_TIOP$M_TLIBR_SCLK = %X'4'; literal KA0C05_TIOP$S_KA0C05_TIOP = 16384; macro KA0C05_TIOP$L_TLDEV = 0,0,32,0 %; macro KA0C05_TIOP$V_TLDEV_DTYPE = 0,0,16,0 %; literal KA0C05_TIOP$S_TLDEV_DTYPE = 16; macro KA0C05_TIOP$V_TLDEV_SWREV = 0,16,8,0 %; literal KA0C05_TIOP$S_TLDEV_SWREV = 8; macro KA0C05_TIOP$V_TLDEV_HWREV = 0,24,8,0 %; literal KA0C05_TIOP$S_TLDEV_HWREV = 8; macro KA0C05_TIOP$b_f1400 = 4,0,0,0 %; literal KA0C05_TIOP$s_f1400 = 60; macro KA0C05_TIOP$L_TLBER = 64,0,32,0 %; macro KA0C05_TIOP$V_TLBER_ATCE = 64,0,1,0 %; macro KA0C05_TIOP$V_TLBER_APE = 64,1,1,0 %; macro KA0C05_TIOP$V_TLBER_BBE = 64,2,1,0 %; macro KA0C05_TIOP$V_TLBER_LKTO = 64,3,1,0 %; macro KA0C05_TIOP$V_TLBER_NAE = 64,4,1,0 %; macro KA0C05_TIOP$V_TLBER_RTCE = 64,5,1,0 %; macro KA0C05_TIOP$V_TLBER_ACKTCE = 64,6,1,0 %; macro KA0C05_TIOP$V_TLBER_MMRE = 64,7,1,0 %; macro KA0C05_TIOP$V_TLBER_FNAE = 64,8,1,0 %; macro KA0C05_TIOP$V_TLBER_REQDE = 64,9,1,0 %; macro KA0C05_TIOP$V_TLBER_ATDE = 64,10,1,0 %; macro KA0C05_TIOP$V_TLBER_UDE = 64,16,1,0 %; macro KA0C05_TIOP$V_TLBER_CWDE = 64,17,1,0 %; macro KA0C05_TIOP$V_TLBER_CRDE = 64,18,1,0 %; macro KA0C05_TIOP$V_TLBER_DS0 = 64,20,1,0 %; macro KA0C05_TIOP$V_TLBER_DS1 = 64,21,1,0 %; macro KA0C05_TIOP$V_TLBER_DS2 = 64,22,1,0 %; macro KA0C05_TIOP$V_TLBER_DS3 = 64,23,1,0 %; macro KA0C05_TIOP$V_TLBER_DTDE = 64,24,1,0 %; macro KA0C05_TIOP$V_TLBER_FDTCE = 64,25,1,0 %; macro KA0C05_TIOP$V_TLBER_UACKE = 64,26,1,0 %; macro KA0C05_TIOP$V_TLBER_ABTCE = 64,27,1,0 %; macro KA0C05_TIOP$V_TLBER_DCTCE = 64,28,1,0 %; macro KA0C05_TIOP$V_TLBER_SEQE = 64,29,1,0 %; macro KA0C05_TIOP$V_TLBER_DSE = 64,30,1,0 %; macro KA0C05_TIOP$V_TLBER_DTO = 64,31,1,0 %; macro KA0C05_TIOP$b_f1410 = 68,0,0,0 %; literal KA0C05_TIOP$s_f1410 = 60; macro KA0C05_TIOP$L_TLCNR = 128,0,32,0 %; macro KA0C05_TIOP$V_TLCNR_CWDD = 128,0,1,0 %; macro KA0C05_TIOP$V_TLCNR_CRDD = 128,1,1,0 %; macro KA0C05_TIOP$V_TLCNR_LKTOD = 128,2,1,0 %; macro KA0C05_TIOP$V_TLCNR_DTOD = 128,3,1,0 %; macro KA0C05_TIOP$V_TLCNR_NODE_ID = 128,4,4,0 %; literal KA0C05_TIOP$S_TLCNR_NODE_ID = 4; macro KA0C05_TIOP$V_TLCNR_VCNT = 128,8,4,0 %; literal KA0C05_TIOP$S_TLCNR_VCNT = 4; macro KA0C05_TIOP$V_TLCNR_STF_A = 128,12,1,0 %; macro KA0C05_TIOP$V_TLCNR_STF_B = 128,13,1,0 %; macro KA0C05_TIOP$V_TLCNR_STF_C = 128,14,1,0 %; macro KA0C05_TIOP$V_TLCNR_STF_D = 128,15,1,0 %; macro KA0C05_TIOP$V_TLCNR_STF_E = 128,16,1,0 %; macro KA0C05_TIOP$V_TLCNR_STF_F = 128,17,1,0 %; macro KA0C05_TIOP$V_TLCNR_STF_G = 128,18,1,0 %; macro KA0C05_TIOP$V_TLCNR_STF_H = 128,19,1,0 %; macro KA0C05_TIOP$V_TLCNR_HALT_A = 128,20,1,0 %; macro KA0C05_TIOP$V_TLCNR_HALT_B = 128,21,1,0 %; macro KA0C05_TIOP$V_TLCNR_HALT_C = 128,22,1,0 %; macro KA0C05_TIOP$V_TLCNR_HALT_D = 128,23,1,0 %; macro KA0C05_TIOP$V_TLCNR_HALT_E = 128,24,1,0 %; macro KA0C05_TIOP$V_TLCNR_HALT_F = 128,25,1,0 %; macro KA0C05_TIOP$V_TLCNR_HALT_G = 128,26,1,0 %; macro KA0C05_TIOP$V_TLCNR_HALT_H = 128,27,1,0 %; macro KA0C05_TIOP$V_TLCNR_RSTSTAT = 128,28,1,0 %; macro KA0C05_TIOP$V_TLCNR_NRST = 128,30,1,0 %; macro KA0C05_TIOP$V_TLCNR_LOFE = 128,31,1,0 %; macro KA0C05_TIOP$b_f1420 = 132,0,0,0 %; literal KA0C05_TIOP$s_f1420 = 380; macro KA0C05_TIOP$L_TLMMR0 = 512,0,32,0 %; macro KA0C05_TIOP$V_TLMMR0_INTMASK = 512,0,2,0 %; literal KA0C05_TIOP$S_TLMMR0_INTMASK = 2; macro KA0C05_TIOP$V_TLMMR0_ADRMASK = 512,4,4,0 %; literal KA0C05_TIOP$S_TLMMR0_ADRMASK = 4; macro KA0C05_TIOP$V_TLMMR0_INTLV = 512,8,3,0 %; literal KA0C05_TIOP$S_TLMMR0_INTLV = 3; macro KA0C05_TIOP$V_TLMMR0_SBANK = 512,11,1,0 %; macro KA0C05_TIOP$V_TLMMR0_ADDRESS = 512,12,14,0 %; literal KA0C05_TIOP$S_TLMMR0_ADDRESS = 14; macro KA0C05_TIOP$V_TLMMR0_VALID = 512,31,1,0 %; macro KA0C05_TIOP$b_f1440 = 516,0,0,0 %; literal KA0C05_TIOP$s_f1440 = 60; macro KA0C05_TIOP$L_TLMMR1 = 576,0,32,0 %; macro KA0C05_TIOP$V_TLMMR1_INTMASK = 576,0,2,0 %; literal KA0C05_TIOP$S_TLMMR1_INTMASK = 2; macro KA0C05_TIOP$V_TLMMR1_ADRMASK = 576,4,4,0 %; literal KA0C05_TIOP$S_TLMMR1_ADRMASK = 4; macro KA0C05_TIOP$V_TLMMR1_INTLV = 576,8,3,0 %; literal KA0C05_TIOP$S_TLMMR1_INTLV = 3; macro KA0C05_TIOP$V_TLMMR1_SBANK = 576,11,1,0 %; macro KA0C05_TIOP$V_TLMMR1_ADDRESS = 576,12,14,0 %; literal KA0C05_TIOP$S_TLMMR1_ADDRESS = 14; macro KA0C05_TIOP$V_TLMMR1_VALID = 576,31,1,0 %; macro KA0C05_TIOP$b_f1450 = 580,0,0,0 %; literal KA0C05_TIOP$s_f1450 = 60; macro KA0C05_TIOP$L_TLMMR2 = 640,0,32,0 %; macro KA0C05_TIOP$V_TLMMR2_INTMASK = 640,0,2,0 %; literal KA0C05_TIOP$S_TLMMR2_INTMASK = 2; macro KA0C05_TIOP$V_TLMMR2_ADRMASK = 640,4,4,0 %; literal KA0C05_TIOP$S_TLMMR2_ADRMASK = 4; macro KA0C05_TIOP$V_TLMMR2_INTLV = 640,8,3,0 %; literal KA0C05_TIOP$S_TLMMR2_INTLV = 3; macro KA0C05_TIOP$V_TLMMR2_SBANK = 640,11,1,0 %; macro KA0C05_TIOP$V_TLMMR2_ADDRESS = 640,12,14,0 %; literal KA0C05_TIOP$S_TLMMR2_ADDRESS = 14; macro KA0C05_TIOP$V_TLMMR2_VALID = 640,31,1,0 %; macro KA0C05_TIOP$b_f1460 = 644,0,0,0 %; literal KA0C05_TIOP$s_f1460 = 60; macro KA0C05_TIOP$L_TLMMR3 = 704,0,32,0 %; macro KA0C05_TIOP$V_TLMMR3_INTMASK = 704,0,2,0 %; literal KA0C05_TIOP$S_TLMMR3_INTMASK = 2; macro KA0C05_TIOP$V_TLMMR3_ADRMASK = 704,4,4,0 %; literal KA0C05_TIOP$S_TLMMR3_ADRMASK = 4; macro KA0C05_TIOP$V_TLMMR3_INTLV = 704,8,3,0 %; literal KA0C05_TIOP$S_TLMMR3_INTLV = 3; macro KA0C05_TIOP$V_TLMMR3_SBANK = 704,11,1,0 %; macro KA0C05_TIOP$V_TLMMR3_ADDRESS = 704,12,14,0 %; literal KA0C05_TIOP$S_TLMMR3_ADDRESS = 14; macro KA0C05_TIOP$V_TLMMR3_VALID = 704,31,1,0 %; macro KA0C05_TIOP$b_f1470 = 708,0,0,0 %; literal KA0C05_TIOP$s_f1470 = 60; macro KA0C05_TIOP$L_TLMMR4 = 768,0,32,0 %; macro KA0C05_TIOP$V_TLMMR4_INTMASK = 768,0,2,0 %; literal KA0C05_TIOP$S_TLMMR4_INTMASK = 2; macro KA0C05_TIOP$V_TLMMR4_ADRMASK = 768,4,4,0 %; literal KA0C05_TIOP$S_TLMMR4_ADRMASK = 4; macro KA0C05_TIOP$V_TLMMR4_INTLV = 768,8,3,0 %; literal KA0C05_TIOP$S_TLMMR4_INTLV = 3; macro KA0C05_TIOP$V_TLMMR4_SBANK = 768,11,1,0 %; macro KA0C05_TIOP$V_TLMMR4_ADDRESS = 768,12,14,0 %; literal KA0C05_TIOP$S_TLMMR4_ADDRESS = 14; macro KA0C05_TIOP$V_TLMMR4_VALID = 768,31,1,0 %; macro KA0C05_TIOP$b_f1480 = 772,0,0,0 %; literal KA0C05_TIOP$s_f1480 = 60; macro KA0C05_TIOP$L_TLMMR5 = 832,0,32,0 %; macro KA0C05_TIOP$V_TLMMR5_INTMASK = 832,0,2,0 %; literal KA0C05_TIOP$S_TLMMR5_INTMASK = 2; macro KA0C05_TIOP$V_TLMMR5_ADRMASK = 832,4,4,0 %; literal KA0C05_TIOP$S_TLMMR5_ADRMASK = 4; macro KA0C05_TIOP$V_TLMMR5_INTLV = 832,8,3,0 %; literal KA0C05_TIOP$S_TLMMR5_INTLV = 3; macro KA0C05_TIOP$V_TLMMR5_SBANK = 832,11,1,0 %; macro KA0C05_TIOP$V_TLMMR5_ADDRESS = 832,12,14,0 %; literal KA0C05_TIOP$S_TLMMR5_ADDRESS = 14; macro KA0C05_TIOP$V_TLMMR5_VALID = 832,31,1,0 %; macro KA0C05_TIOP$b_f1490 = 836,0,0,0 %; literal KA0C05_TIOP$s_f1490 = 60; macro KA0C05_TIOP$L_TLMMR6 = 896,0,32,0 %; macro KA0C05_TIOP$V_TLMMR6_INTMASK = 896,0,2,0 %; literal KA0C05_TIOP$S_TLMMR6_INTMASK = 2; macro KA0C05_TIOP$V_TLMMR6_ADRMASK = 896,4,4,0 %; literal KA0C05_TIOP$S_TLMMR6_ADRMASK = 4; macro KA0C05_TIOP$V_TLMMR6_INTLV = 896,8,3,0 %; literal KA0C05_TIOP$S_TLMMR6_INTLV = 3; macro KA0C05_TIOP$V_TLMMR6_SBANK = 896,11,1,0 %; macro KA0C05_TIOP$V_TLMMR6_ADDRESS = 896,12,14,0 %; literal KA0C05_TIOP$S_TLMMR6_ADDRESS = 14; macro KA0C05_TIOP$V_TLMMR6_VALID = 896,31,1,0 %; macro KA0C05_TIOP$b_f1500 = 900,0,0,0 %; literal KA0C05_TIOP$s_f1500 = 60; macro KA0C05_TIOP$L_TLMMR7 = 960,0,32,0 %; macro KA0C05_TIOP$V_TLMMR7_INTMASK = 960,0,2,0 %; literal KA0C05_TIOP$S_TLMMR7_INTMASK = 2; macro KA0C05_TIOP$V_TLMMR7_ADRMASK = 960,4,4,0 %; literal KA0C05_TIOP$S_TLMMR7_ADRMASK = 4; macro KA0C05_TIOP$V_TLMMR7_INTLV = 960,8,3,0 %; literal KA0C05_TIOP$S_TLMMR7_INTLV = 3; macro KA0C05_TIOP$V_TLMMR7_SBANK = 960,11,1,0 %; macro KA0C05_TIOP$V_TLMMR7_ADDRESS = 960,12,14,0 %; literal KA0C05_TIOP$S_TLMMR7_ADDRESS = 14; macro KA0C05_TIOP$V_TLMMR7_VALID = 960,31,1,0 %; macro KA0C05_TIOP$b_f1510 = 964,0,0,0 %; literal KA0C05_TIOP$s_f1510 = 572; macro KA0C05_TIOP$L_TLFADR0 = 1536,0,32,0 %; macro KA0C05_TIOP$V_TLFADR0_FADR = 1536,3,29,0 %; literal KA0C05_TIOP$S_TLFADR0_FADR = 29; macro KA0C05_TIOP$b_f1520 = 1540,0,0,0 %; literal KA0C05_TIOP$s_f1520 = 60; macro KA0C05_TIOP$L_TLFADR1 = 1600,0,32,0 %; macro KA0C05_TIOP$V_TLFADR1_FADR = 1600,0,8,0 %; literal KA0C05_TIOP$S_TLFADR1_FADR = 8; macro KA0C05_TIOP$V_TLFADR1_FCMD = 1600,16,3,0 %; literal KA0C05_TIOP$S_TLFADR1_FCMD = 3; macro KA0C05_TIOP$V_TLFADR1_FBANK = 1600,20,4,0 %; literal KA0C05_TIOP$S_TLFADR1_FBANK = 4; macro KA0C05_TIOP$V_TLFADR1_ADRV = 1600,24,1,0 %; macro KA0C05_TIOP$V_TLFADR1_CMDV = 1600,25,1,0 %; macro KA0C05_TIOP$V_TLFADR1_BANKV = 1600,26,1,0 %; macro KA0C05_TIOP$b_f1530 = 1604,0,0,0 %; literal KA0C05_TIOP$s_f1530 = 60; macro KA0C05_TIOP$L_TLESR0 = 1664,0,32,0 %; macro KA0C05_TIOP$V_TLESR0_SYND0 = 1664,0,8,0 %; literal KA0C05_TIOP$S_TLESR0_SYND0 = 8; macro KA0C05_TIOP$V_TLESR0_SYND1 = 1664,8,8,0 %; literal KA0C05_TIOP$S_TLESR0_SYND1 = 8; macro KA0C05_TIOP$V_TLESR0_TDE = 1664,16,1,0 %; macro KA0C05_TIOP$V_TLESR0_TCE = 1664,17,1,0 %; macro KA0C05_TIOP$V_TLESR0_DVTCE = 1664,18,1,0 %; macro KA0C05_TIOP$V_TLESR0_UECC = 1664,19,1,0 %; macro KA0C05_TIOP$V_TLESR0_CWECC = 1664,20,1,0 %; macro KA0C05_TIOP$V_TLESR0_CRECC = 1664,21,1,0 %; macro KA0C05_TIOP$V_TLESR0_LOFSYN = 1664,31,1,0 %; macro KA0C05_TIOP$b_f1540 = 1668,0,0,0 %; literal KA0C05_TIOP$s_f1540 = 60; macro KA0C05_TIOP$L_TLESR1 = 1728,0,32,0 %; macro KA0C05_TIOP$V_TLESR1_SYND0 = 1728,0,8,0 %; literal KA0C05_TIOP$S_TLESR1_SYND0 = 8; macro KA0C05_TIOP$V_TLESR1_SYND1 = 1728,8,8,0 %; literal KA0C05_TIOP$S_TLESR1_SYND1 = 8; macro KA0C05_TIOP$V_TLESR1_TDE = 1728,16,1,0 %; macro KA0C05_TIOP$V_TLESR1_TCE = 1728,17,1,0 %; macro KA0C05_TIOP$V_TLESR1_DVTCE = 1728,18,1,0 %; macro KA0C05_TIOP$V_TLESR1_UECC = 1728,19,1,0 %; macro KA0C05_TIOP$V_TLESR1_CWECC = 1728,20,1,0 %; macro KA0C05_TIOP$V_TLESR1_CRECC = 1728,21,1,0 %; macro KA0C05_TIOP$V_TLESR1_LOFSYN = 1728,31,1,0 %; macro KA0C05_TIOP$b_f1550 = 1732,0,0,0 %; literal KA0C05_TIOP$s_f1550 = 60; macro KA0C05_TIOP$L_TLESR2 = 1792,0,32,0 %; macro KA0C05_TIOP$V_TLESR2_SYND0 = 1792,0,8,0 %; literal KA0C05_TIOP$S_TLESR2_SYND0 = 8; macro KA0C05_TIOP$V_TLESR2_SYND1 = 1792,8,8,0 %; literal KA0C05_TIOP$S_TLESR2_SYND1 = 8; macro KA0C05_TIOP$V_TLESR2_TDE = 1792,16,1,0 %; macro KA0C05_TIOP$V_TLESR2_TCE = 1792,17,1,0 %; macro KA0C05_TIOP$V_TLESR2_DVTCE = 1792,18,1,0 %; macro KA0C05_TIOP$V_TLESR2_UECC = 1792,19,1,0 %; macro KA0C05_TIOP$V_TLESR2_CWECC = 1792,20,1,0 %; macro KA0C05_TIOP$V_TLESR2_CRECC = 1792,21,1,0 %; macro KA0C05_TIOP$V_TLESR2_LOFSYN = 1792,31,1,0 %; macro KA0C05_TIOP$b_f1560 = 1796,0,0,0 %; literal KA0C05_TIOP$s_f1560 = 60; macro KA0C05_TIOP$L_TLESR3 = 1856,0,32,0 %; macro KA0C05_TIOP$V_TLESR3_SYND0 = 1856,0,8,0 %; literal KA0C05_TIOP$S_TLESR3_SYND0 = 8; macro KA0C05_TIOP$V_TLESR3_SYND1 = 1856,8,8,0 %; literal KA0C05_TIOP$S_TLESR3_SYND1 = 8; macro KA0C05_TIOP$V_TLESR3_TDE = 1856,16,1,0 %; macro KA0C05_TIOP$V_TLESR3_TCE = 1856,17,1,0 %; macro KA0C05_TIOP$V_TLESR3_DVTCE = 1856,18,1,0 %; macro KA0C05_TIOP$V_TLESR3_UECC = 1856,19,1,0 %; macro KA0C05_TIOP$V_TLESR3_CWECC = 1856,20,1,0 %; macro KA0C05_TIOP$V_TLESR3_CRECC = 1856,21,1,0 %; macro KA0C05_TIOP$V_TLESR3_LOFSYN = 1856,31,1,0 %; macro KA0C05_TIOP$b_f1570 = 1860,0,0,0 %; literal KA0C05_TIOP$s_f1570 = 700; macro KA0C05_TIOP$L_TLILID0 = 2560,0,32,0 %; macro KA0C05_TIOP$V_TLILID0_IDENT = 2560,0,16,0 %; literal KA0C05_TIOP$S_TLILID0_IDENT = 16; macro KA0C05_TIOP$b_f1580 = 2564,0,0,0 %; literal KA0C05_TIOP$s_f1580 = 60; macro KA0C05_TIOP$L_TLILID1 = 2624,0,32,0 %; macro KA0C05_TIOP$V_TLILID1_IDENT = 2624,0,16,0 %; literal KA0C05_TIOP$S_TLILID1_IDENT = 16; macro KA0C05_TIOP$b_f1590 = 2628,0,0,0 %; literal KA0C05_TIOP$s_f1590 = 60; macro KA0C05_TIOP$L_TLILID2 = 2688,0,32,0 %; macro KA0C05_TIOP$V_TLILID2_IDENT = 2688,0,16,0 %; literal KA0C05_TIOP$S_TLILID2_IDENT = 16; macro KA0C05_TIOP$b_f1600 = 2692,0,0,0 %; literal KA0C05_TIOP$s_f1600 = 60; macro KA0C05_TIOP$L_TLILID3 = 2752,0,32,0 %; macro KA0C05_TIOP$V_TLILID3_IDENT = 2752,0,16,0 %; literal KA0C05_TIOP$S_TLILID3_IDENT = 16; macro KA0C05_TIOP$b_f1610 = 2756,0,0,0 %; literal KA0C05_TIOP$s_f1610 = 60; macro KA0C05_TIOP$L_TLCPUMASK = 2816,0,32,0 %; macro KA0C05_TIOP$V_TLCPUMASK_MASK = 2816,0,16,0 %; literal KA0C05_TIOP$S_TLCPUMASK_MASK = 16; macro KA0C05_TIOP$b_f1620 = 2820,0,0,0 %; literal KA0C05_TIOP$s_f1620 = 252; macro KA0C05_TIOP$Q_TLMBPR = 3072,0,0,1 %; literal KA0C05_TIOP$S_TLMBPR = 8; macro KA0C05_TIOP$b_f1630 = 3080,0,0,0 %; literal KA0C05_TIOP$s_f1630 = 4600; macro KA0C05_TIOP$L_TLRMR0A = 7680,0,32,0 %; macro KA0C05_TIOP$V_TLRMR0A_MASK = 7680,0,4,0 %; literal KA0C05_TIOP$S_TLRMR0A_MASK = 4; macro KA0C05_TIOP$V_TLRMR0A_ILV_EN = 7680,4,1,0 %; macro KA0C05_TIOP$V_TLRMR0A_BADR = 7680,8,20,0 %; literal KA0C05_TIOP$S_TLRMR0A_BADR = 20; macro KA0C05_TIOP$V_TLRMR0A_NVRAM = 7680,30,1,0 %; macro KA0C05_TIOP$V_TLRMR0A_VALID = 7680,31,1,0 %; macro KA0C05_TIOP$b_f1640 = 7684,0,0,0 %; literal KA0C05_TIOP$s_f1640 = 60; macro KA0C05_TIOP$L_TLRMR0B = 7744,0,32,0 %; macro KA0C05_TIOP$V_TLRMR0B_MASK = 7744,0,4,0 %; literal KA0C05_TIOP$S_TLRMR0B_MASK = 4; macro KA0C05_TIOP$V_TLRMR0B_ILV_EN = 7744,4,1,0 %; macro KA0C05_TIOP$V_TLRMR0B_BADR = 7744,8,20,0 %; literal KA0C05_TIOP$S_TLRMR0B_BADR = 20; macro KA0C05_TIOP$V_TLRMR0B_NVRAM = 7744,30,1,0 %; macro KA0C05_TIOP$V_TLRMR0B_VALID = 7744,31,1,0 %; macro KA0C05_TIOP$b_f1650 = 7748,0,0,0 %; literal KA0C05_TIOP$s_f1650 = 60; macro KA0C05_TIOP$L_TLRMR1A = 7808,0,32,0 %; macro KA0C05_TIOP$V_TLRMR1A_MASK = 7808,0,4,0 %; literal KA0C05_TIOP$S_TLRMR1A_MASK = 4; macro KA0C05_TIOP$V_TLRMR1A_ILV_EN = 7808,4,1,0 %; macro KA0C05_TIOP$V_TLRMR1A_BADR = 7808,8,20,0 %; literal KA0C05_TIOP$S_TLRMR1A_BADR = 20; macro KA0C05_TIOP$V_TLRMR1A_NVRAM = 7808,30,1,0 %; macro KA0C05_TIOP$V_TLRMR1A_VALID = 7808,31,1,0 %; macro KA0C05_TIOP$b_f1660 = 7812,0,0,0 %; literal KA0C05_TIOP$s_f1660 = 60; macro KA0C05_TIOP$L_TLRMR1B = 7872,0,32,0 %; macro KA0C05_TIOP$V_TLRMR1B_MASK = 7872,0,4,0 %; literal KA0C05_TIOP$S_TLRMR1B_MASK = 4; macro KA0C05_TIOP$V_TLRMR1B_ILV_EN = 7872,4,1,0 %; macro KA0C05_TIOP$V_TLRMR1B_BADR = 7872,8,20,0 %; literal KA0C05_TIOP$S_TLRMR1B_BADR = 20; macro KA0C05_TIOP$V_TLRMR1B_NVRAM = 7872,30,1,0 %; macro KA0C05_TIOP$V_TLRMR1B_VALID = 7872,31,1,0 %; macro KA0C05_TIOP$b_f1670 = 7876,0,0,0 %; literal KA0C05_TIOP$s_f1670 = 316; macro KA0C05_TIOP$L_TLICMSR = 8192,0,32,0 %; macro KA0C05_TIOP$V_TLICMSR_ARB_CTL = 8192,0,2,0 %; literal KA0C05_TIOP$S_TLICMSR_ARB_CTL = 2; macro KA0C05_TIOP$V_TLICMSR_SUP_CTL = 8192,2,2,0 %; literal KA0C05_TIOP$S_TLICMSR_SUP_CTL = 2; macro KA0C05_TIOP$V_TLICMSR_FORCE_ACK = 8192,4,1,0 %; macro KA0C05_TIOP$V_TLICMSR_RMNXM = 8192,5,1,0 %; macro KA0C05_TIOP$V_TLICMSR_ACK_DSBL = 8192,6,1,0 %; macro KA0C05_TIOP$b_f1700 = 8196,0,0,0 %; literal KA0C05_TIOP$s_f1700 = 60; macro KA0C05_TIOP$L_TLICNSE = 8256,0,32,0 %; macro KA0C05_TIOP$V_TLICNSE_ACK_DROP = 8256,2,1,0 %; macro KA0C05_TIOP$V_TLICNSE_RMNXM = 8256,3,1,0 %; macro KA0C05_TIOP$V_TLICNSE_MBX_STAT = 8256,4,4,0 %; literal KA0C05_TIOP$S_TLICNSE_MBX_STAT = 4; macro KA0C05_TIOP$V_TLICNSE_OFLO = 8256,8,4,0 %; literal KA0C05_TIOP$S_TLICNSE_OFLO = 4; macro KA0C05_TIOP$V_TLICNSE_PKT_E = 8256,12,4,0 %; literal KA0C05_TIOP$S_TLICNSE_PKT_E = 4; macro KA0C05_TIOP$V_TLICNSE_PAR_E = 8256,16,4,0 %; literal KA0C05_TIOP$S_TLICNSE_PAR_E = 4; macro KA0C05_TIOP$V_TLICNSE_UP_HDP_IE = 8256,20,2,0 %; literal KA0C05_TIOP$S_TLICNSE_UP_HDP_IE = 2; macro KA0C05_TIOP$V_TLICNSE_INT_E = 8256,22,1,0 %; macro KA0C05_TIOP$V_TLICNSE_DN_VRTX_E = 8256,23,2,0 %; literal KA0C05_TIOP$S_TLICNSE_DN_VRTX_E = 2; macro KA0C05_TIOP$V_TLICNSE_UP_VRTX_E = 8256,25,2,0 %; literal KA0C05_TIOP$S_TLICNSE_UP_VRTX_E = 2; macro KA0C05_TIOP$V_TLICNSE_IE = 8256,27,1,0 %; macro KA0C05_TIOP$V_TLICNSE_BUS_PE = 8256,28,1,0 %; macro KA0C05_TIOP$V_TLICNSE_WND_OFLO = 8256,29,1,0 %; macro KA0C05_TIOP$V_TLICNSE_RM_OFLO = 8256,30,1,0 %; macro KA0C05_TIOP$V_TLICNSE_INT_NSES = 8256,31,1,0 %; macro KA0C05_TIOP$b_f1710 = 8260,0,0,0 %; literal KA0C05_TIOP$s_f1710 = 60; macro KA0C05_TIOP$L_TLICDR = 8320,0,32,0 %; macro KA0C05_TIOP$V_TLICDR_IDP_PE = 8320,0,1,0 %; macro KA0C05_TIOP$V_TLICDR_DSE = 8320,1,1,0 %; macro KA0C05_TIOP$V_TLICDR_DTO = 8320,2,1,0 %; macro KA0C05_TIOP$V_TLICDR_DIS_CMD = 8320,3,1,0 %; macro KA0C05_TIOP$V_TLICDR_DIS_FLT = 8320,4,1,0 %; macro KA0C05_TIOP$V_TLICDR_CMD_PE = 8320,5,1,0 %; macro KA0C05_TIOP$V_TLICDR_BNK_BSY = 8320,6,1,0 %; macro KA0C05_TIOP$V_TLICDR_IDP_CMD_PE = 8320,8,1,0 %; macro KA0C05_TIOP$V_TLICDR_EN_HID = 8320,31,1,0 %; macro KA0C05_TIOP$b_f1720 = 8324,0,0,0 %; literal KA0C05_TIOP$s_f1720 = 60; macro KA0C05_TIOP$L_TLICMTR = 8384,0,32,0 %; macro KA0C05_TIOP$V_TLICMTR_MBX_TIP = 8384,0,4,0 %; literal KA0C05_TIOP$S_TLICMTR_MBX_TIP = 4; macro KA0C05_TIOP$b_f1730 = 8388,0,0,0 %; literal KA0C05_TIOP$s_f1730 = 60; macro KA0C05_TIOP$L_TLICWRT = 8448,0,32,0 %; macro KA0C05_TIOP$V_TLICWRT_WIP = 8448,0,4,0 %; literal KA0C05_TIOP$S_TLICWRT_WIP = 4; macro KA0C05_TIOP$b_f1740 = 8452,0,0,0 %; literal KA0C05_TIOP$s_f1740 = 60; macro KA0C05_TIOP$L_TLIDPNSE1 = 8512,0,32,0 %; macro KA0C05_TIOP$V_TLIDPNSE_ERR = 8512,0,1,0 %; macro KA0C05_TIOP$V_TLIDPNSE_POK = 8512,1,1,0 %; macro KA0C05_TIOP$V_TLIDPNSE_CBLOK = 8512,2,1,0 %; macro KA0C05_TIOP$V_TLIDPNSE_POK_TRAN = 8512,3,1,0 %; macro KA0C05_TIOP$V_TLIDPNSE_SOFT_ERR = 8512,4,1,0 %; macro KA0C05_TIOP$V_TLIDPNSE_RM_M_ERR = 8512,22,2,0 %; literal KA0C05_TIOP$S_TLIDPNSE_RM_M_ERR = 2; macro KA0C05_TIOP$V_TLIDPNSE_CPE = 8512,24,1,0 %; macro KA0C05_TIOP$V_TLIDPNSE_UP_V_ERR = 8512,25,2,0 %; literal KA0C05_TIOP$S_TLIDPNSE_UP_V_ERR = 2; macro KA0C05_TIOP$V_TLIDPNSE_IE = 8512,27,1,0 %; macro KA0C05_TIOP$V_TLIDPNSE_PE = 8512,28,1,0 %; macro KA0C05_TIOP$V_TLIDPNSE_RESET = 8512,31,1,0 %; macro KA0C05_TIOP$b_f1750 = 8516,0,0,0 %; literal KA0C05_TIOP$s_f1750 = 60; macro KA0C05_TIOP$L_TLIDPDR1 = 8576,0,32,0 %; macro KA0C05_TIOP$b_f1760 = 8580,0,0,0 %; literal KA0C05_TIOP$s_f1760 = 188; macro KA0C05_TIOP$L_TLIDPNSE2 = 8768,0,32,0 %; macro KA0C05_TIOP$b_f1770 = 8772,0,0,0 %; literal KA0C05_TIOP$s_f1770 = 60; macro KA0C05_TIOP$L_TLIDPDR2 = 8832,0,32,0 %; macro KA0C05_TIOP$b_f1780 = 8836,0,0,0 %; literal KA0C05_TIOP$s_f1780 = 188; macro KA0C05_TIOP$L_TLIDPNSE3 = 9024,0,32,0 %; macro KA0C05_TIOP$b_f1790 = 9028,0,0,0 %; literal KA0C05_TIOP$s_f1790 = 60; macro KA0C05_TIOP$L_TLIDPDR3 = 9088,0,32,0 %; macro KA0C05_TIOP$b_f1800 = 9092,0,0,0 %; literal KA0C05_TIOP$s_f1800 = 1724; macro KA0C05_TIOP$L_TLIDPNSE0 = 10816,0,32,0 %; macro KA0C05_TIOP$b_f1810 = 10820,0,0,0 %; literal KA0C05_TIOP$s_f1810 = 60; macro KA0C05_TIOP$L_TLIDPDR0 = 10880,0,32,0 %; macro KA0C05_TIOP$b_f1820 = 10884,0,0,0 %; literal KA0C05_TIOP$s_f1820 = 60; macro KA0C05_TIOP$L_TLIPMASK = 10944,0,32,0 %; macro KA0C05_TIOP$V_TLIPMASK_CPU = 10944,0,16,0 %; literal KA0C05_TIOP$S_TLIPMASK_CPU = 16; macro KA0C05_TIOP$b_fill830 = 10948,0,0,0 %; literal KA0C05_TIOP$s_fill830 = 124; macro KA0C05_TIOP$L_TLIDPVR = 11072,0,32,0 %; macro KA0C05_TIOP$V_TLIDPVR_VECTOR = 11072,0,16,0 %; literal KA0C05_TIOP$S_TLIDPVR_VECTOR = 16; macro KA0C05_TIOP$b_f1840 = 11076,0,0,0 %; literal KA0C05_TIOP$s_f1840 = 60; macro KA0C05_TIOP$L_TLIDPMSR = 11136,0,32,0 %; macro KA0C05_TIOP$b_f1850 = 11140,0,0,0 %; literal KA0C05_TIOP$s_f1850 = 60; macro KA0C05_TIOP$L_TLIBR = 11200,0,32,0 %; macro KA0C05_TIOP$V_TLIBR_RCV_SDAT = 11200,0,1,0 %; macro KA0C05_TIOP$V_TLIBR_XMT_SDAT = 11200,1,1,0 %; macro KA0C05_TIOP$V_TLIBR_SCLK = 11200,2,1,0 %; macro KA0C05_TIOP$b_f1860 = 11204,0,0,0 %; literal KA0C05_TIOP$s_f1860 = 5180; literal KA0C05_UART0B$S_KA0C05_UART0B = 8192; macro KA0C05_UART0B$L_UART0B_RR0 = 0,0,32,0 %; macro KA0C05_UART0B$b_f2000 = 4,0,0,0 %; literal KA0C05_UART0B$s_f2000 = 60; macro KA0C05_UART0B$L_UART0B_RR8 = 64,0,32,0 %; macro KA0C05_UART0B$b_f2010 = 68,0,0,0 %; literal KA0C05_UART0B$s_f2010 = 60; macro KA0C05_UART0B$L_UART0A_RR0 = 128,0,32,0 %; macro KA0C05_UART0B$b_f2020 = 132,0,0,0 %; literal KA0C05_UART0B$s_f2020 = 60; macro KA0C05_UART0B$L_UART0A_RR8 = 192,0,32,0 %; macro KA0C05_UART0B$b_f2030 = 196,0,0,0 %; literal KA0C05_UART0B$s_f2030 = 7996; literal KA0C05_UART1B$S_KA0C05_UART1B = 8192; macro KA0C05_UART1B$L_UART1B_RR0 = 0,0,32,0 %; macro KA0C05_UART1B$L_UART1B_WR0 = 0,0,32,0 %; macro KA0C05_UART1B$b_f2040 = 4,0,0,0 %; literal KA0C05_UART1B$s_f2040 = 60; macro KA0C05_UART1B$L_UART1B_RR8 = 64,0,32,0 %; macro KA0C05_UART1B$b_f2050 = 68,0,0,0 %; literal KA0C05_UART1B$s_f2050 = 60; macro KA0C05_UART1B$L_UART1A_RR0 = 128,0,32,0 %; macro KA0C05_UART1B$b_f2060 = 132,0,0,0 %; literal KA0C05_UART1B$s_f2060 = 60; macro KA0C05_UART1B$L_UART1A_RR8 = 192,0,32,0 %; macro KA0C05_UART1B$b_f2070 = 196,0,0,0 %; literal KA0C05_UART1B$s_f2070 = 7996; literal KA0C05_WATCH$M_WATCH_CSRA_RS = %X'F'; literal KA0C05_WATCH$M_WATCH_CSRA_DV = %X'70'; literal KA0C05_WATCH$M_WATCH_CSRA_UIP = %X'80'; literal KA0C05_WATCH$M_WATCH_CSRB_DSE = %X'1'; literal KA0C05_WATCH$M_WATCH_CSRB_24_12 = %X'2'; literal KA0C05_WATCH$M_WATCH_CSRB_DM = %X'4'; literal KA0C05_WATCH$M_WATCH_CSRB_SQWE = %X'8'; literal KA0C05_WATCH$M_WATCH_CSRB_UIE = %X'10'; literal KA0C05_WATCH$M_WATCH_CSRB_AIE = %X'20'; literal KA0C05_WATCH$M_WATCH_CSRB_PIE = %X'40'; literal KA0C05_WATCH$M_WATCH_CSRB_SET = %X'80'; literal KA0C05_WATCH$M_WATCH_CSRC_UF = %X'10'; literal KA0C05_WATCH$M_WATCH_CSRC_AF = %X'20'; literal KA0C05_WATCH$M_WATCH_CSRC_PF = %X'40'; literal KA0C05_WATCH$M_WATCH_CSRC_IRQF = %X'80'; literal KA0C05_WATCH$M_WATCH_CSRD_VRT = %X'80'; literal KA0C05_WATCH$S_KA0C05_WATCH = 8192; macro KA0C05_WATCH$L_WATCH_SECONDS = 0,0,32,0 %; macro KA0C05_WATCH$b_fill3000 = 4,0,0,0 %; literal KA0C05_WATCH$s_fill3000 = 124; macro KA0C05_WATCH$L_WATCH_MINUTES = 128,0,32,0 %; macro KA0C05_WATCH$b_fill3010 = 132,0,0,0 %; literal KA0C05_WATCH$s_fill3010 = 124; macro KA0C05_WATCH$L_WATCH_HOURS = 256,0,32,0 %; macro KA0C05_WATCH$b_fill3020 = 260,0,0,0 %; literal KA0C05_WATCH$s_fill3020 = 188; macro KA0C05_WATCH$L_WATCH_DOM = 448,0,32,0 %; macro KA0C05_WATCH$b_fill3030 = 452,0,0,0 %; literal KA0C05_WATCH$s_fill3030 = 60; macro KA0C05_WATCH$L_WATCH_MONTH = 512,0,32,0 %; macro KA0C05_WATCH$b_fill3040 = 516,0,0,0 %; literal KA0C05_WATCH$s_fill3040 = 60; macro KA0C05_WATCH$L_WATCH_YEAR = 576,0,32,0 %; macro KA0C05_WATCH$b_fill3050 = 580,0,0,0 %; literal KA0C05_WATCH$s_fill3050 = 60; macro KA0C05_WATCH$L_WATCH_CSRA = 640,0,32,0 %; macro KA0C05_WATCH$V_WATCH_CSRA_RS = 640,0,4,0 %; literal KA0C05_WATCH$S_WATCH_CSRA_RS = 4; macro KA0C05_WATCH$V_WATCH_CSRA_DV = 640,4,3,0 %; literal KA0C05_WATCH$S_WATCH_CSRA_DV = 3; macro KA0C05_WATCH$V_WATCH_CSRA_UIP = 640,7,1,0 %; macro KA0C05_WATCH$b_fill3060 = 644,0,0,0 %; literal KA0C05_WATCH$s_fill3060 = 60; macro KA0C05_WATCH$L_WATCH_CSRB = 704,0,32,0 %; macro KA0C05_WATCH$V_WATCH_CSRB_DSE = 704,0,1,0 %; macro KA0C05_WATCH$V_WATCH_CSRB_24_12 = 704,1,1,0 %; macro KA0C05_WATCH$V_WATCH_CSRB_DM = 704,2,1,0 %; macro KA0C05_WATCH$V_WATCH_CSRB_SQWE = 704,3,1,0 %; macro KA0C05_WATCH$V_WATCH_CSRB_UIE = 704,4,1,0 %; macro KA0C05_WATCH$V_WATCH_CSRB_AIE = 704,5,1,0 %; macro KA0C05_WATCH$V_WATCH_CSRB_PIE = 704,6,1,0 %; macro KA0C05_WATCH$V_WATCH_CSRB_SET = 704,7,1,0 %; macro KA0C05_WATCH$b_fill3070 = 708,0,0,0 %; literal KA0C05_WATCH$s_fill3070 = 60; macro KA0C05_WATCH$L_WATCH_CSRC = 768,0,32,0 %; macro KA0C05_WATCH$V_WATCH_CSRC_UF = 768,4,1,0 %; macro KA0C05_WATCH$V_WATCH_CSRC_AF = 768,5,1,0 %; macro KA0C05_WATCH$V_WATCH_CSRC_PF = 768,6,1,0 %; macro KA0C05_WATCH$V_WATCH_CSRC_IRQF = 768,7,1,0 %; macro KA0C05_WATCH$b_fill3080 = 772,0,0,0 %; literal KA0C05_WATCH$s_fill3080 = 60; macro KA0C05_WATCH$L_WATCH_CSRD = 832,0,32,0 %; macro KA0C05_WATCH$V_WATCH_CSRD_VRT = 832,7,1,0 %; macro KA0C05_WATCH$b_fill3090 = 836,0,0,0 %; literal KA0C05_WATCH$s_fill3090 = 60; macro KA0C05_WATCH$L_WATCH_RAM = 896,0,32,0 %; macro KA0C05_WATCH$b_fill3100 = 900,0,0,0 %; literal KA0C05_WATCH$s_fill3100 = 7292; literal KA0C05_GBUS$M_GWHAMI_CPU = %X'1'; literal KA0C05_GBUS$M_GWHAMI_NID = %X'E'; literal KA0C05_GBUS$M_GWHAMI_BAD = %X'10'; literal KA0C05_GBUS$M_GWHAMI_CONWIN = %X'20'; literal KA0C05_GBUS$M_GWHAMI_MFG_MODE = %X'40'; literal KA0C05_GBUS$M_GMISCR_CACSIZ = %X'3'; literal KA0C05_GBUS$M_GMISCR_PROCCNT = %X'4'; literal KA0C05_GBUS$M_GMISCR_SECURE = %X'8'; literal KA0C05_GBUS$M_GMISCR_RUN = %X'10'; literal KA0C05_GBUS$M_GMISCR_CONWIN0 = %X'40'; literal KA0C05_GBUS$M_GMISCR_CONWIN1 = %X'80'; literal KA0C05_GBUS$M_GMISCW_DRIVE_BAD = %X'4'; literal KA0C05_GBUS$M_GMISCW_FPROM_WE = %X'8'; literal KA0C05_GBUS$M_GMISCW_DRIVE_RUN = %X'10'; literal KA0C05_GBUS$M_GMISCW_DRV_CONWIN = %X'20'; literal KA0C05_GBUS$M_GMISCW_CONWIN0 = %X'40'; literal KA0C05_GBUS$M_GMISCW_CONWIN1 = %X'80'; literal KA0C05_GBUS$M_GSERNUM_CLK = %X'1'; literal KA0C05_GBUS$M_GSERNUM_RCV_DATA = %X'2'; literal KA0C05_GBUS$M_GSERNUM_XMT_DATA = %X'4'; literal KA0C05_GBUS$M_GSERNUM_EXPSEL = %X'18'; literal KA0C05_GBUS$M_GSERNUM_PIUB = %X'20'; literal KA0C05_GBUS$M_GSERNUM_PIUA = %X'40'; literal KA0C05_GBUS$M_GSERNUM_STP = %X'80'; literal KA0C05_GBUS$S_KA0C05_GBUS = 73728; macro KA0C05_GBUS$L_GWHAMI = 0,0,32,0 %; macro KA0C05_GBUS$V_GWHAMI_CPU = 0,0,1,0 %; macro KA0C05_GBUS$V_GWHAMI_NID = 0,1,3,0 %; literal KA0C05_GBUS$S_GWHAMI_NID = 3; macro KA0C05_GBUS$V_GWHAMI_BAD = 0,4,1,0 %; macro KA0C05_GBUS$V_GWHAMI_CONWIN = 0,5,1,0 %; macro KA0C05_GBUS$V_GWHAMI_MFG_MODE = 0,6,1,0 %; macro KA0C05_GBUS$b_fill3110 = 4,0,0,0 %; literal KA0C05_GBUS$s_fill3110 = 8188; macro KA0C05_GBUS$L_GBUS_LED0 = 8192,0,32,0 %; macro KA0C05_GBUS$b_fill3120 = 8196,0,0,0 %; literal KA0C05_GBUS$s_fill3120 = 8188; macro KA0C05_GBUS$L_GBUS_LED1 = 16384,0,32,0 %; macro KA0C05_GBUS$b_fill3130 = 16388,0,0,0 %; literal KA0C05_GBUS$s_fill3130 = 8188; macro KA0C05_GBUS$L_GBUS_LED2 = 24576,0,32,0 %; macro KA0C05_GBUS$b_fill3140 = 24580,0,0,0 %; literal KA0C05_GBUS$s_fill3140 = 8188; macro KA0C05_GBUS$L_GMISCR = 32768,0,32,0 %; macro KA0C05_GBUS$V_GMISCR_CACSIZ = 32768,0,2,0 %; literal KA0C05_GBUS$S_GMISCR_CACSIZ = 2; macro KA0C05_GBUS$V_GMISCR_PROCCNT = 32768,2,1,0 %; macro KA0C05_GBUS$V_GMISCR_SECURE = 32768,3,1,0 %; macro KA0C05_GBUS$V_GMISCR_RUN = 32768,4,1,0 %; macro KA0C05_GBUS$V_GMISCR_CONWIN0 = 32768,6,1,0 %; macro KA0C05_GBUS$V_GMISCR_CONWIN1 = 32768,7,1,0 %; macro KA0C05_GBUS$b_fill3150 = 32772,0,0,0 %; literal KA0C05_GBUS$s_fill3150 = 8188; macro KA0C05_GBUS$L_GMISCW = 40960,0,32,0 %; macro KA0C05_GBUS$V_GMISCW_DRIVE_BAD = 40960,2,1,0 %; macro KA0C05_GBUS$V_GMISCW_FPROM_WE = 40960,3,1,0 %; macro KA0C05_GBUS$V_GMISCW_DRIVE_RUN = 40960,4,1,0 %; macro KA0C05_GBUS$V_GMISCW_DRV_CONWIN = 40960,5,1,0 %; macro KA0C05_GBUS$V_GMISCW_CONWIN0 = 40960,6,1,0 %; macro KA0C05_GBUS$V_GMISCW_CONWIN1 = 40960,7,1,0 %; macro KA0C05_GBUS$b_fill3160 = 40964,0,0,0 %; literal KA0C05_GBUS$s_fill3160 = 8188; macro KA0C05_GBUS$L_GBUS_TLSBRST = 49152,0,32,0 %; macro KA0C05_GBUS$b_fill3170 = 49156,0,0,0 %; literal KA0C05_GBUS$s_fill3170 = 8188; macro KA0C05_GBUS$L_GSERNUM = 57344,0,32,0 %; macro KA0C05_GBUS$V_GSERNUM_CLK = 57344,0,1,0 %; macro KA0C05_GBUS$V_GSERNUM_RCV_DATA = 57344,1,1,0 %; macro KA0C05_GBUS$V_GSERNUM_XMT_DATA = 57344,2,1,0 %; macro KA0C05_GBUS$V_GSERNUM_EXPSEL = 57344,3,2,0 %; literal KA0C05_GBUS$S_GSERNUM_EXPSEL = 2; macro KA0C05_GBUS$V_GSERNUM_PIUB = 57344,5,1,0 %; macro KA0C05_GBUS$V_GSERNUM_PIUA = 57344,6,1,0 %; macro KA0C05_GBUS$V_GSERNUM_STP = 57344,7,1,0 %; macro KA0C05_GBUS$b_fill3180 = 57348,0,0,0 %; literal KA0C05_GBUS$s_fill3180 = 8188; macro KA0C05_GBUS$L_GBUS_TEST = 65536,0,32,0 %; macro KA0C05_GBUS$b_fill3190 = 65540,0,0,0 %; literal KA0C05_GBUS$s_fill3190 = 8188; literal S_KA0C05DEF = 73728; ! Old size name, synonym for KA0C05$S_KA0C05 !*** MODULE $KA0E04DEF *** literal KA0E04$M_IOC_PCI_CFG_CYC = %X'3'; literal KA0E04$M_IOC_CERR = %X'10'; literal KA0E04$M_IOC_CLOST = %X'20'; literal KA0E04$M_IOC_PCI_SOFT_RST = %X'40'; literal KA0E04$M_IOC_TLB_EN = %X'80'; literal KA0E04$M_IOC_HAE = %X'F8000000'; literal KA0E04$M_STAT0_CMD = %X'F'; literal KA0E04$M_STAT0_ERR = %X'10'; literal KA0E04$M_STAT0_LOST = %X'20'; literal KA0E04$M_STAT0_T_HIT = %X'40'; literal KA0E04$M_STAT0_T_REF = %X'80'; literal KA0E04$M_STAT0_CODE = %X'700'; literal KA0E04$M_STAT0_P_NBR = %X'FFFFE000'; literal KA0E04$M_WBASE0_WBASE = %X'FFF00000'; literal KA0E04$M_WBASE0_SG = %X'100000000'; literal KA0E04$M_WBASE0_WEN = %X'200000000'; literal KA0E04$M_WBASE1_WBASE = %X'FFF00000'; literal KA0E04$M_WBASE1_SG = %X'100000000'; literal KA0E04$M_WBASE1_WEN = %X'200000000'; literal KA0E04$M_WMASK0_WMASK = %X'FFF00000'; literal KA0E04$M_WMASK1_WMASK = %X'FFF00000'; literal KA0E04$M_TBASE0_TBASE = %X'FFF00000'; literal KA0E04$M_TBASE1_TBASE = %X'FFFFFC00'; literal KA0E04$S_KA0E04 = 424; macro KA0E04$Q_IOC = 0,0,0,0 %; literal KA0E04$S_IOC = 8; macro KA0E04$V_IOC_PCI_CFG_CYC = 0,0,2,0 %; literal KA0E04$S_IOC_PCI_CFG_CYC = 2; macro KA0E04$V_IOC_CERR = 0,4,1,0 %; macro KA0E04$V_IOC_CLOST = 0,5,1,0 %; macro KA0E04$V_IOC_PCI_SOFT_RST = 0,6,1,0 %; macro KA0E04$V_IOC_TLB_EN = 0,7,1,0 %; macro KA0E04$V_IOC_HAE = 0,27,5,0 %; literal KA0E04$S_IOC_HAE = 5; macro KA0E04$b_fill1 = 8,0,0,1 %; literal KA0E04$s_fill1 = 56; ! this should pad from PA 180000008 to 180000040 macro KA0E04$Q_IOC_STAT0 = 64,0,0,0 %; literal KA0E04$S_IOC_STAT0 = 8; macro KA0E04$V_STAT0_CMD = 64,0,4,0 %; literal KA0E04$S_STAT0_CMD = 4; macro KA0E04$V_STAT0_ERR = 64,4,1,0 %; macro KA0E04$V_STAT0_LOST = 64,5,1,0 %; macro KA0E04$V_STAT0_T_HIT = 64,6,1,0 %; macro KA0E04$V_STAT0_T_REF = 64,7,1,0 %; macro KA0E04$V_STAT0_CODE = 64,8,3,0 %; literal KA0E04$S_STAT0_CODE = 3; macro KA0E04$V_STAT0_P_NBR = 64,13,19,0 %; literal KA0E04$S_STAT0_P_NBR = 19; macro KA0E04$b_fill2 = 72,0,0,1 %; literal KA0E04$s_fill2 = 24; ! pad from PA 1.8000.0048 to 1.8000.0060 macro KA0E04$Q_IOC_STAT1 = 96,0,0,0 %; literal KA0E04$S_IOC_STAT1 = 8; macro KA0E04$b_fill3 = 104,0,0,1 %; literal KA0E04$s_fill3 = 24; ! pad from PA 1.8000.0068 to 1.8000.0080 macro KA0E04$Q_IOC_TBIA = 128,0,0,0 %; literal KA0E04$S_IOC_TBIA = 8; macro KA0E04$b_fill4 = 136,0,0,1 %; literal KA0E04$s_fill4 = 120; ! pad from PA 1.8000.0088 to 1.8000.0100 macro KA0E04$Q_IOC_WBASE0 = 256,0,0,0 %; literal KA0E04$S_IOC_WBASE0 = 8; macro KA0E04$V_WBASE0_WBASE = 256,20,12,0 %; literal KA0E04$S_WBASE0_WBASE = 12; macro KA0E04$V_WBASE0_SG = 260,0,1,0 %; macro KA0E04$V_WBASE0_WEN = 260,1,1,0 %; macro KA0E04$b_fill5 = 264,0,0,1 %; literal KA0E04$s_fill5 = 24; ! pad from PA 1.8000.0108 to 1.8000.0120 macro KA0E04$Q_IOC_WBASE1 = 288,0,0,0 %; literal KA0E04$S_IOC_WBASE1 = 8; macro KA0E04$V_WBASE1_WBASE = 288,20,12,0 %; literal KA0E04$S_WBASE1_WBASE = 12; macro KA0E04$V_WBASE1_SG = 292,0,1,0 %; macro KA0E04$V_WBASE1_WEN = 292,1,1,0 %; macro KA0E04$b_fill6 = 296,0,0,1 %; literal KA0E04$s_fill6 = 24; ! pad from PA 1.8000.0128 to 1.8000.0140 macro KA0E04$Q_IOC_WMASK0 = 320,0,0,0 %; literal KA0E04$S_IOC_WMASK0 = 8; macro KA0E04$V_WMASK0_WMASK = 320,20,12,0 %; literal KA0E04$S_WMASK0_WMASK = 12; macro KA0E04$b_fill7 = 328,0,0,1 %; literal KA0E04$s_fill7 = 24; ! pad from PA 1.8000.0148 to 1.8000.0160 macro KA0E04$Q_IOC_WMASK1 = 352,0,0,0 %; literal KA0E04$S_IOC_WMASK1 = 8; macro KA0E04$V_WMASK1_WMASK = 352,20,12,0 %; literal KA0E04$S_WMASK1_WMASK = 12; macro KA0E04$b_fill8 = 360,0,0,1 %; literal KA0E04$s_fill8 = 24; ! pad from PA 1.8000.0168 to 1.8000.0180 macro KA0E04$Q_IOC_TBASE0 = 384,0,0,0 %; literal KA0E04$S_IOC_TBASE0 = 8; macro KA0E04$V_TBASE0_TBASE = 384,20,12,0 %; literal KA0E04$S_TBASE0_TBASE = 12; macro KA0E04$b_fill9 = 392,0,0,1 %; literal KA0E04$s_fill9 = 24; ! pad from PA 1.8000.0188 to 1.8000.01A0 macro KA0E04$Q_IOC_TBASE1 = 416,0,0,0 %; literal KA0E04$S_IOC_TBASE1 = 8; macro KA0E04$V_TBASE1_TBASE = 416,10,22,0 %; literal KA0E04$S_TBASE1_TBASE = 22; literal KA0E04$K_OPDRIVER_XMT_ISR = 1; literal KA0E04$K_OPDRIVER_RCV_ISR = 12; !*** MODULE $KA0F05DEF IDENT X-5 *** ! ! GRU space ! literal GRU$M_INT_CLR = %X'1'; literal GRU$M_CNFG_CLK_DIV = %X'F0'; literal GRU$M_CNFG_CACHE_SP = %X'1800'; literal GRU$M_CNFG_CACHE_SZ = %X'E000'; literal GRU$M_CNFG_MMB0_CFG = %X'F0000'; literal GRU$M_CNFG_MMB1_CFG = %X'F000000'; literal GRU$M_CNFG_SS7_MMB0 = %X'3'; literal GRU$M_CNFG_SS6_MMB0 = %X'C'; literal GRU$M_CNFG_SS5_MMB0 = %X'30'; literal GRU$M_CNFG_SS4_MMB0 = %X'C0'; literal GRU$M_CNFG_SS3_MMB0 = %X'300'; literal GRU$M_CNFG_SS2_MMB0 = %X'C00'; literal GRU$M_CNFG_SS1_MMB0 = %X'3000'; literal GRU$M_CNFG_SS0_MMB0 = %X'C000'; literal GRU$M_CNFG_SS7_MMB1 = %X'30000'; literal GRU$M_CNFG_SS6_MMB1 = %X'C0000'; literal GRU$M_CNFG_SS5_MMB1 = %X'300000'; literal GRU$M_CNFG_SS4_MMB1 = %X'C00000'; literal GRU$M_CNFG_SS3_MMB1 = %X'3000000'; literal GRU$M_CNFG_SS2_MMB1 = %X'C000000'; literal GRU$M_CNFG_SS1_MMB1 = %X'30000000'; literal GRU$M_CNFG_SS0_MMB1 = %X'C0000000'; literal GRU$S_GRU = 59904; ! ! The following element is the displacement in the virtual io table from ! the cia structure to the gru structure (see map_local_io_0f05() in ! io_support_0f05.c). ! ! ! GRU Interrupt request register - 0x8780000000 ! macro GRU$L_INT_REQ = 57344,0,32,1 %; ! ! GRU Interrupt mask register - 0x8780000040 ! macro GRU$L_INT_MASK = 57408,0,32,1 %; ! ! GRU Interrupt Level/edge select register - 0x8780000080 ! macro GRU$L_INT_EDGE = 57472,0,32,1 %; ! ! GRU Interrupt High/Low select register - 0x87800000C0 ! macro GRU$L_INT_HILO = 57536,0,32,1 %; ! ! GRU Interrupt clear register - 0x8780000100 ! macro GRU$L_INT_CLEAR = 57600,0,32,1 %; macro GRU$V_INT_CLR = 57600,0,1,0 %; ! macro GRU$V_ICLR_FILL = 57600,1,31,0 %; literal GRU$S_ICLR_FILL = 31; ! ! GRU Cache and Memory Config register - 0x8780000200 ! macro GRU$L_CACHE_CONFIG = 57856,0,32,1 %; macro GRU$V_CNFG_CLK_DIV = 57856,4,4,0 %; literal GRU$S_CNFG_CLK_DIV = 4; ! macro GRU$V_CNFG_CACHE_SP = 57856,11,2,0 %; literal GRU$S_CNFG_CACHE_SP = 2; ! macro GRU$V_CNFG_CACHE_SZ = 57856,13,3,0 %; literal GRU$S_CNFG_CACHE_SZ = 3; ! macro GRU$V_CNFG_MMB0_CFG = 57856,16,4,0 %; literal GRU$S_CNFG_MMB0_CFG = 4; ! macro GRU$V_CNFG_MMB1_CFG = 57856,24,4,0 %; literal GRU$S_CNFG_MMB1_CFG = 4; ! ! ! GRU SET Memory Config register - 0x8780000300 ! macro GRU$L_SET_CONFIG = 58112,0,32,1 %; macro GRU$V_CNFG_SS7_MMB0 = 58112,0,2,0 %; literal GRU$S_CNFG_SS7_MMB0 = 2; ! macro GRU$V_CNFG_SS6_MMB0 = 58112,2,2,0 %; literal GRU$S_CNFG_SS6_MMB0 = 2; ! macro GRU$V_CNFG_SS5_MMB0 = 58112,4,2,0 %; literal GRU$S_CNFG_SS5_MMB0 = 2; ! macro GRU$V_CNFG_SS4_MMB0 = 58112,6,2,0 %; literal GRU$S_CNFG_SS4_MMB0 = 2; ! macro GRU$V_CNFG_SS3_MMB0 = 58112,8,2,0 %; literal GRU$S_CNFG_SS3_MMB0 = 2; ! macro GRU$V_CNFG_SS2_MMB0 = 58112,10,2,0 %; literal GRU$S_CNFG_SS2_MMB0 = 2; ! macro GRU$V_CNFG_SS1_MMB0 = 58112,12,2,0 %; literal GRU$S_CNFG_SS1_MMB0 = 2; ! macro GRU$V_CNFG_SS0_MMB0 = 58112,14,2,0 %; literal GRU$S_CNFG_SS0_MMB0 = 2; ! macro GRU$V_CNFG_SS7_MMB1 = 58112,16,2,0 %; literal GRU$S_CNFG_SS7_MMB1 = 2; ! macro GRU$V_CNFG_SS6_MMB1 = 58112,18,2,0 %; literal GRU$S_CNFG_SS6_MMB1 = 2; ! macro GRU$V_CNFG_SS5_MMB1 = 58112,20,2,0 %; literal GRU$S_CNFG_SS5_MMB1 = 2; ! macro GRU$V_CNFG_SS4_MMB1 = 58112,22,2,0 %; literal GRU$S_CNFG_SS4_MMB1 = 2; ! macro GRU$V_CNFG_SS3_MMB1 = 58112,24,2,0 %; literal GRU$S_CNFG_SS3_MMB1 = 2; ! macro GRU$V_CNFG_SS2_MMB1 = 58112,26,2,0 %; literal GRU$S_CNFG_SS2_MMB1 = 2; ! macro GRU$V_CNFG_SS1_MMB1 = 58112,28,2,0 %; literal GRU$S_CNFG_SS1_MMB1 = 2; ! macro GRU$V_CNFG_SS0_MMB1 = 58112,30,2,0 %; literal GRU$S_CNFG_SS0_MMB1 = 2; ! ! ! GRU LED register - 0x8780000800 ! macro GRU$L_LED = 59392,0,32,1 %; ! ! GRU RESET register - 0x8780000900 ! macro GRU$L_RESET = 59648,0,32,1 %; ! ! DS1287A register definitions ! literal KA0F05_DS1287A$S_KA0F05_DS1287A = 3624; macro KA0F05_DS1287A$L_PORT_INDEX = 3584,0,32,0 %; macro KA0F05_DS1287A$L_PORT_DATA = 3616,0,32,0 %; !*** MODULE $KDZDEF *** ! + ! KDZ11 Offset Definitions for Registers Accessible Through BI Node Private ! Space. Note that in making these registers available in virtual space, ! we have only mapped real registers. Therefore these virtual offsets are ! different than the hardware physical offsets. ! - literal KDZ$M_PCNTL_RSTRT = %X'1'; literal KDZ$M_PCNTL_PHYLOG = %X'2'; literal KDZ$M_PCNTL_SECENB = %X'4'; literal KDZ$M_PCNTL_STINIT = %X'8'; literal KDZ$M_PCNTL_STFAST = %X'10'; literal KDZ$M_PCNTL_ENBAPT = %X'20'; literal KDZ$M_PCNTL_STPASS = %X'40'; literal KDZ$M_PCNTL_RUN = %X'80'; literal KDZ$M_PCNTL_CLREVL = %X'200'; literal KDZ$M_PCNTL_WRMEM = %X'400'; literal KDZ$M_PCNTL_EV4 = %X'800'; literal KDZ$M_PCNTL_EV3 = %X'1000'; literal KDZ$M_PCNTL_EV2 = %X'2000'; literal KDZ$M_PCNTL_EV1 = %X'4000'; literal KDZ$M_PCNTL_EV0 = %X'8000'; literal KDZ$M_PCNTL_WWPO = %X'10000'; literal KDZ$M_PCNTL_NIDIS = %X'80000'; literal KDZ$M_PCNTL_CNSLIE = %X'100000'; literal KDZ$M_PCNTL_CNSLCL = %X'200000'; literal KDZ$M_PCNTL_CNSLIN = %X'400000'; literal KDZ$M_PCNTL_WWPE = %X'800000'; literal KDZ$M_PCNTL_RXDONE = %X'1000000'; literal KDZ$M_PCNTL_RXSTAT = %X'2000000'; literal KDZ$M_PCNTL_CLRIPI = %X'4000000'; literal KDZ$M_PCNTL_IPINTR = %X'8000000'; literal KDZ$M_PCNTL_CRDIE = %X'10000000'; literal KDZ$M_PCNTL_CLRCRD = %X'20000000'; literal KDZ$M_PCNTL_CRDINT = %X'40000000'; literal KDZ$S_KDZDEF = 44032; ! Old size name - synonym literal KDZ$S_KDZ = 44032; ! ! BIIC registers - here we reserve space for the 256 bytes that these ! registers occupy and we also fill out the virtual page to ! 512 bytes so that other items appear on page boundaries. ! Being able to address the BIIC via these virtual addresses ! allows a Scorpio CPU to determine its own node number. ! That is, a reference here is via node private space and ! always addresses a nodes own registers via a loop back ! request. ! macro KDZ$B_BIICBASE = 0,0,8,0 %; ! BIIC register Base ! ! Port Control CSR register ! macro KDZ$L_PCNTL = 512,0,32,0 %; ! Port Control CSR Register macro KDZ$V_PCNTL_RSTRT = 512,0,1,0 %; ! (RO) Front Panel Switch ! selecting RSTRT/HALT macro KDZ$V_PCNTL_PHYLOG = 512,1,1,0 %; ! (RO) Backplane Bit ! selecting PHYS/LOG Console macro KDZ$V_PCNTL_SECENB = 512,2,1,0 %; ! (RO) Front Panel Switch ! to lock out console input macro KDZ$V_PCNTL_STINIT = 512,3,1,0 %; ! Self-Test INIT. macro KDZ$V_PCNTL_STFAST = 512,4,1,0 %; ! (RO) Backplane bit to ! select Fast Self-Test. macro KDZ$V_PCNTL_ENBAPT = 512,5,1,0 %; ! Enable APT. macro KDZ$V_PCNTL_STPASS = 512,6,1,0 %; ! Self-Test Pass. macro KDZ$V_PCNTL_RUN = 512,7,1,0 %; ! 1=>Program mode,0=>Console macro KDZ$V_PCNTL_CLREVL = 512,9,1,0 %; ! Clear Event Lock macro KDZ$V_PCNTL_WRMEM = 512,10,1,0 %; ! Write Memory Bit macro KDZ$V_PCNTL_EV4 = 512,11,1,0 %; ! Event Bits - These macro KDZ$V_PCNTL_EV3 = 512,12,1,0 %; ! RO bits are event macro KDZ$V_PCNTL_EV2 = 512,13,1,0 %; ! codes from BIIC to macro KDZ$V_PCNTL_EV1 = 512,14,1,0 %; ! allow CPU to monitor macro KDZ$V_PCNTL_EV0 = 512,15,1,0 %; ! BI status macro KDZ$V_PCNTL_WWPO = 512,16,1,0 %; ! Write Wrong Parity Odd macro KDZ$V_PCNTL_NIDIS = 512,19,1,0 %; ! Disable NI Lance macro KDZ$V_PCNTL_CNSLIE = 512,20,1,0 %; ! Console Interrupt Enable macro KDZ$V_PCNTL_CNSLCL = 512,21,1,0 %; ! Clear Console Interrupt macro KDZ$V_PCNTL_CNSLIN = 512,22,1,0 %; ! Console Interrupt RCVD macro KDZ$V_PCNTL_WWPE = 512,23,1,0 %; ! Write Wrong Parity Even macro KDZ$V_PCNTL_RXDONE = 512,24,1,0 %; ! RX Done Interrupt macro KDZ$V_PCNTL_RXSTAT = 512,25,1,0 %; ! RX Status Interrupt macro KDZ$V_PCNTL_CLRIPI = 512,26,1,0 %; ! Clear IP Interrupt macro KDZ$V_PCNTL_IPINTR = 512,27,1,0 %; ! IP Interrupt RCVD macro KDZ$V_PCNTL_CRDIE = 512,28,1,0 %; ! CRD Interrupt Enable macro KDZ$V_PCNTL_CLRCRD = 512,29,1,0 %; ! Clear CRD Interrupt macro KDZ$V_PCNTL_CRDINT = 512,30,1,0 %; ! CRD Interrupt RCVD ! ! NI Packet Buffer ! macro KDZ$B_NIBUF = 1024,0,8,0 %; ! NI Packet Buffer Base ! ! EEPROM ! macro KDZ$B_EEPROM = 33792,0,8,0 %; ! EEPROM Base ! ! NI Data Register ! macro KDZ$L_NIDATA = 41984,0,32,0 %; ! NI Data Register ! ! NI Address Register ! macro KDZ$L_NIADDR = 42496,0,32,1 %; ! NI Address Register ! ! RCX50 Registers ! macro KDZ$B_RCX50 = 43008,0,8,0 %; ! RCX50 Registers ! ! Watch Chip Registers ! macro KDZ$B_WATCH = 43520,0,8,0 %; ! Watch Chip Registers !*** MODULE $KFDDEF *** ! ! KNOWN FILE DEVICE AND DIRECTORY BLOCK DEFINITIONS ! literal KFD$C_LENGTH = 17; ! Length of fixed area of kfd entry literal KFD$S_KFDDEF = 17; ! Old size name - synonym literal KFD$S_KFD = 17; macro KFD$L_LINK = 0,0,32,1 %; ! Device, Directory, Extension (KFD) list link macro KFD$L_KFELIST = 4,0,32,1 %; ! Ordered Known file entry list header macro KFD$W_SIZE = 8,0,16,0 %; ! Size of block macro KFD$B_TYPE = 10,0,8,0 %; ! Structure type macro KFD$B_SPARE = 11,0,8,0 %; ! spare macro KFD$W_REFCNT = 12,0,16,0 %; ! Number of KFE's with same KFD macro KFD$B_DEVLEN = 14,0,8,0 %; ! Length of Device string macro KFD$B_DIRLEN = 15,0,8,0 %; ! Length of Directory string macro KFD$B_DDTSTRLEN = 16,0,8,0 %; ! Length of Device, Directory, Type (DDT) string macro KFD$T_DDTSTR = 17,0,0,0 %; ! Offset to DDT string !*** MODULE $KFEDEF *** ! ! KNOWN FILE ENTRY DEFINITIONS ! literal KFE$M_PROTECT = %X'1'; literal KFE$M_LIM = %X'2'; literal KFE$M_PROCPRIV = %X'4'; literal KFE$M_OPEN = %X'8'; literal KFE$M_HDRRES = %X'10'; literal KFE$M_SHARED = %X'20'; literal KFE$M_KFE_NAMING = %X'40'; literal KFE$M_COMPRESS = %X'80'; literal KFE$M_NOPURGE = %X'100'; literal KFE$M_ACCOUNT = %X'200'; literal KFE$M_WRITEABLE = %X'400'; literal KFE$M_EXEONLY = %X'800'; literal KFE$M_DISCONTIGUOUS = %X'1000'; literal KFE$M_DELETE_PEND = %X'2000'; literal KFE$M_VERSION_SAFE = %X'4000'; literal KFE$M_DATA_RESIDENT = %X'8000'; literal KFE$M_AUTHPRIV = %X'1'; literal KFE$M_ARB_SUPPORT = %X'2'; literal KFE$M_GLX_WRITE = %X'4'; literal KFE$M_GLX_IDENT = %X'8'; literal KFE$M_ELF = %X'10'; literal KFE$M_SHARE_ADDR = %X'20'; literal KFE$M_RSRVD_6_31 = %X'FFFFFFC0'; literal KFE$K_LENGTH = 120; ! Length of fixed area of KFE entry literal KFE$C_LENGTH = 120; ! Length of fixed area of KFE entry ! Count of flags used literal KFE$K_NUMBER_OF_FLAGS = 22; ! Number of flag bits used. literal KFE$S_KFEDEF = 120; ! Old size name - synonym literal KFE$S_KFE = 120; macro KFE$L_HSHLNK = 0,0,32,1 %; ! Known file Hash table link macro KFE$L_KFELINK = 4,0,32,1 %; ! Ordered Known file entry list link macro KFE$W_SIZE = 8,0,16,0 %; ! Size of block macro KFE$B_TYPE = 10,0,8,0 %; ! Structure type macro KFE$B_HSHIDX = 11,0,8,0 %; ! KFE hash table index (index into vector of HSHQ's) macro KFE$L_KFD = 12,0,32,1 %; ! Device, Directory, Type block macro KFE$R_FLAGS_OVERLAY = 16,0,16,0 %; macro KFE$W_FLAGS = 16,0,16,0 %; ! Flags word macro KFE$R_FLAGS_BITS = 16,0,16,0 %; macro KFE$V_PROTECT = 16,0,1,0 %; ! Known file was installed protected macro KFE$V_LIM = 16,1,1,0 %; ! Linkable image macro KFE$V_PROCPRIV = 16,2,1,0 %; ! Use process privilege mask macro KFE$V_OPEN = 16,3,1,0 %; ! Image installed /OPEN macro KFE$V_HDRRES = 16,4,1,0 %; ! Image header block is resident macro KFE$V_SHARED = 16,5,1,0 %; ! Image is shared macro KFE$V_KFE_NAMING = 16,6,1,0 %; ! use KFE based name for global sections macro KFE$V_COMPRESS = 16,7,1,0 %; ! Image sections are compressed macro KFE$V_NOPURGE = 16,8,1,0 %; ! Image entry may not be purged macro KFE$V_ACCOUNT = 16,9,1,0 %; ! Image level accounting macro KFE$V_WRITEABLE = 16,10,1,0 %; ! Global sections are writeable macro KFE$V_EXEONLY = 16,11,1,0 %; ! Image has only execute access allowed macro KFE$V_DISCONTIGUOUS = 16,12,1,0 %; ! Image has resident sections macro KFE$V_DELETE_PEND = 16,13,1,0 %; ! Delete pending on KFE macro KFE$V_VERSION_SAFE = 16,14,1,0 %; ! Image is exempt from system version checks macro KFE$V_DATA_RESIDENT = 16,15,1,0 %; ! Image has resident read-only data sections macro KFE$W_GBLSECCNT = 18,0,16,0 %; ! Global section count if shared macro KFE$L_USECNT = 20,0,32,0 %; ! Usage counter macro KFE$R_WINDOW_OVERLAY = 24,0,32,0 %; macro KFE$L_WCB = 24,0,32,1 %; ! WCB address if open macro KFE$R_WINDOW_FIELDS = 24,0,32,0 %; macro KFE$R_FID_OVERLAY = 24,0,16,0 %; macro KFE$W_FID = 24,0,16,0 %; ! File id macro KFE$W_FID_NUM = 24,0,16,0 %; ! File number field of file id macro KFE$W_FID_SEQ = 26,0,16,0 %; ! File sequence number field of file id macro KFE$R_IMGHDR_OVERLAY = 28,0,32,0 %; macro KFE$L_IMGHDR = 28,0,32,1 %; ! Image header address if resident macro KFE$L_LDRIMG = 28,0,32,1 %; ! Pointer to IMGHDR (if ELF format) macro KFE$W_FID_RVN = 28,0,16,0 %; ! Relative volume number field of file id macro KFE$Q_PROCPRIV = 32,0,0,0 %; literal KFE$S_PROCPRIV = 8; ! Process privilege mask macro KFE$B_MATCHCTL = 40,0,8,0 %; ! Global section match control macro KFE$W_AMECOD = 42,0,16,0 %; ! Image header code specifying AME macro KFE$L_IDENT = 44,0,32,0 %; ! Global section ident value macro KFE$L_ORB = 48,0,32,1 %; ! Address of Object Rights Block macro KFE$W_SHRCNT = 52,0,16,0 %; ! High water mark for sharing macro KFE$W_MAXSHRISD = 54,0,16,0 %; ! Highest ISD number for which a global section exists macro KFE$L_KFERES_PTR = 56,0,32,1 %; ! Pointer to resident section description macro KFE$L_REF_COUNT = 60,0,32,0 %; ! Reference count macro KFE$L_PRIV_ISD_CNT = 64,0,32,0 %; ! Private, non-stack ISDs macro KFE$L_IMAGE_SIZE = 68,0,32,0 %; ! Size in bytes of installed image (if image header is opened) ! FILNAMLEN and FILNAM are now obsolete. Do not use them. Use IMAGENAME macro KFE$L_OBSOLETE_1 = 72,0,32,0 %; ! Shifted Off the Layout macro KFE$L_IMAGENAME_OFFSET = 76,0,32,0 %; ! Offset to Counted String of file (image) name macro KFE$R_FLAGS2_OVERLAY = 80,0,32,0 %; macro KFE$L_FLAGS2 = 80,0,32,0 %; ! Overflow Flags longword macro KFE$R_FLAGS2_BITS = 80,0,32,0 %; macro KFE$V_AUTHPRIV = 80,0,1,0 %; ! Authorized privs used macro KFE$V_ARB_SUPPORT = 80,1,1,0 %; ! An arb_support value was specified macro KFE$V_GLX_WRITE = 80,2,1,0 %; ! installed /write=galaxy macro KFE$V_GLX_IDENT = 80,3,1,0 %; ! installed /write=galaxy=ident macro KFE$V_ELF = 80,4,1,0 %; ! image is ELF format (IA64) macro KFE$V_SHARE_ADDR = 80,5,1,0 %; ! installed /share=address_data macro KFE$V_RSRVD_6_31 = 80,6,26,0 %; literal KFE$S_RSRVD_6_31 = 26; ! The unused bits macro KFE$AR_AUTHRIGHTS = 84,0,32,1 %; ! Image authorized rights macro KFE$AR_RIGHTS = 88,0,32,1 %; ! Image active rights (initial) macro KFE$L_ARB_SUPPORT = 92,0,32,0 %; ! ARB support compatibility flag macro KFE$Q_AUTHPRIV = 96,0,0,0 %; literal KFE$S_AUTHPRIV = 8; ! Image authorized privileges macro KFE$L_RISIG_OFFSET = 104,0,32,0 %; ! Offset to referenced image signiture macro KFE$W_FILVER = 108,0,16,0 %; ! file version number, used for INSTALL LIST macro KFE$Q_FILE_ID = 112,0,0,0 %; literal KFE$S_FILE_ID = 8; ! FID (even if the file is installed OPEN) !*** MODULE $KFE52DEF *** ! ! CIRRUS CIO module related definitions ! literal KFE52RAM$M_REV = %X'7FF'; literal KFE52RAM$M_SERIALNO = %X'3FF800'; literal KFE52RAM$M_MODULEID = %X'3C00000'; literal KFE52RAM$S_RAMDEF = 8; ! Old size name - synonym literal KFE52RAM$S_CIRRAM = 8; macro KFE52RAM$L_MODDATA = 0,0,32,0 %; ! macro KFE52RAM$V_REV = 0,0,11,0 %; literal KFE52RAM$S_REV = 11; ! Module revision filed macro KFE52RAM$V_SERIALNO = 0,11,11,0 %; literal KFE52RAM$S_SERIALNO = 11; ! Module serial number macro KFE52RAM$V_MODULEID = 0,22,4,0 %; literal KFE52RAM$S_MODULEID = 4; ! Module id type macro KFE52RAM$L_MODSTATUS = 4,0,32,0 %; ! Module status literal KFE52RAM$K_MOD_GOOD = 179; ! Good module status literal KFE52RAM$K_MOD_BAD = 76; ! Bad module status literal KFE52RAM$L_TRDB = 13312; ! Trace RAM data block ! SLIM offsets and definitions literal SLI520$M_TCA = %X'7C'; literal SLI520$M_TESTPTRS = %X'80'; literal SLI520$M_DIAGMODE = %X'100'; literal SLI520$M_DMASEL = %X'400'; literal SLI520$M_DISARB = %X'800'; literal SLI520$S_SLIMDEF = 4; ! Old size name - synonym literal SLI520$S_CIRSLIM = 4; macro SLI520$L_ICSR0 = 0,0,32,0 %; ! II32 Control register macro SLI520$V_TCA = 0,2,5,0 %; literal SLI520$S_TCA = 5; ! Trace RAM number macro SLI520$V_TESTPTRS = 0,7,1,0 %; ! Test pointers macro SLI520$V_DIAGMODE = 0,8,1,0 %; ! Diagnostic mode macro SLI520$V_DMASEL = 0,10,1,0 %; ! DMA select macro SLI520$V_DISARB = 0,11,1,0 %; ! Disable arbitration ! FIREWALL offsets literal FIR520$S_FIRDEF = 48; ! Old size name - synonym literal FIR520$S_CIRFIR = 48; macro FIR520$L_INTVEC0 = 0,0,32,0 %; ! SWIFT macro FIR520$L_INTVEC1 = 4,0,32,0 %; ! LANCE macro FIR520$L_INTVEC2 = 8,0,32,0 %; ! Not used macro FIR520$L_INTVEC3 = 12,0,32,0 %; ! PCM macro FIR520$L_UCCRVEC = 16,0,32,0 %; ! UCCR (read only) macro FIR520$L_DCCRVEC = 20,0,32,0 %; ! DCCR (read only) macro FIR520$L_WINVEC = 28,0,32,0 %; ! Vector that has won interrupt arbitration macro FIR520$L_IPL = 32,0,32,0 %; ! IPL settings for INTVEC0 - INTVEC3 (Interrupt Level) macro FIR520$L_IMR = 36,0,32,0 %; ! Interrupt Mask Register macro FIR520$L_ICS = 40,0,32,0 %; ! Interrupt Control/Status register. macro FIR520$L_PCMVEC = 44,0,32,0 %; ! PCM ! SCB offsets per section of the second page of the SCB. The second page ! of the SCB is divided into 16 sections each of which correspond to ! a slot (TR) number. literal KA520SCB$S_CIRCSCBDEF = 20; ! Old size name - synonym literal KA520SCB$S_CIRSCB = 20; macro KA520SCB$L_CONI = 0,0,32,0 %; ! Console input macro KA520SCB$L_CONO = 4,0,32,0 %; ! Console output macro KA520SCB$L_LANCE = 8,0,32,0 %; ! LANCE macro KA520SCB$L_SWIFT = 12,0,32,0 %; ! SWIFT macro KA520SCB$L_PCM = 16,0,32,0 %; ! PCM ! The physical byte offsets of various register from the beginning of a CIO ! module. literal KFE52$K_COMM_RAM = 0; ! COMM RAM literal KFE52$K_COMM_SIZE = 65536; ! COMM RAM size literal KFE52$K_SL_RAM = 65536; ! SWIFT/LANCE RAM literal KFE52$K_SL_SIZE = 196608; ! SWIFT/LANCE RAM size literal KFE52$K_LANCE_RAM = 65536; ! LANCE RAM literal KFE52$K_LANCE_SIZE = 65536; ! LANCE RAM size literal KFE52$K_SWIFT_RAM = 131072; ! SWIFT RAM literal KFE52$K_SWIFT_SIZE = 131072; ! SWIFT RAM size literal KFE52$K_ETH_ADR_ROM = 9043968; ! Ethernet address ROM literal KFE52$K_SSC_CSR = 9699328; ! SSC CSR and RAM literal KFE52$K_SSC_TOY_CLOCK = 9699436; ! SSC TOY clock literal KFE52$K_FIREWALL = 10485760; ! Firewall registers literal KFE52$K_DMA_BCNT = 10489856; ! DMA byte count literal KFE52$K_DMA_STL = 10489860; ! DMA sub transfer length literal KFE52$K_DMA_STS = 10489864; ! DMA status literal KFE52$K_PCM_CSR = 10498048; ! PCM CSR literal KFE52$K_FW_CSR = 10502144; ! Firewall CSR literal KFE52$K_CONS_CSR = 10510336; ! Console registers literal KFE52$K_SLIM_CSR = 12582912; ! SLIM CSR literal KFE52$K_SWIFT_CSR = 12582976; ! SWIFT CSR literal KFE52$K_LANCE_CSR = 12583040; ! LANCE CSR ! CONSOLE REGISTER offsets and definitions literal CON520$M_UTYP = %X'100'; literal CON520$M_UID = %X'E00'; literal CON520$M_UBRK = %X'1000'; literal CON520$M_UEIE = %X'2000'; literal CON520$M_UFIE = %X'4000'; literal CON520$M_UBSY = %X'8000'; literal CON520$M_DTYP = %X'100'; literal CON520$M_DID = %X'E00'; literal CON520$M_DEIE = %X'2000'; literal CON520$M_DFIE = %X'4000'; literal CON520$M_DBSY = %X'8000'; literal CON520$S_CONDEF = 8; ! Old size name - synonym literal CON520$S_CIRCON = 8; macro CON520$L_UCCR = 0,0,32,0 %; ! UPWARD Console Communication Register macro CON520$V_UDATA = 0,0,8,0 %; literal CON520$S_UDATA = 8; ! Data macro CON520$V_UTYP = 0,8,1,0 %; ! Type macro CON520$V_UID = 0,9,3,0 %; literal CON520$S_UID = 3; ! ID macro CON520$V_UBRK = 0,12,1,0 %; ! CIO module Broken macro CON520$V_UEIE = 0,13,1,0 %; ! Empty Interrupt enable macro CON520$V_UFIE = 0,14,1,0 %; ! Full Interrupt enable macro CON520$V_UBSY = 0,15,1,0 %; ! Busy macro CON520$L_DCCR = 4,0,32,0 %; ! DOWNWARD Console Communication Register macro CON520$V_DDATA = 4,0,8,0 %; literal CON520$S_DDATA = 8; ! Data macro CON520$V_DTYP = 4,8,1,0 %; ! Type macro CON520$V_DID = 4,9,3,0 %; literal CON520$S_DID = 3; ! ID macro CON520$V_DEIE = 4,13,1,0 %; ! Empty interrupt enable macro CON520$V_DFIE = 4,14,1,0 %; ! Full Interrupt enable macro CON520$V_DBSY = 4,15,1,0 %; ! Busy literal FWCSR520$M_TRACE_READ = %X'1'; literal FWCSR520$M_CPU_WRITE = %X'2'; literal FWCSR520$M_CPU_READ = %X'4'; literal FWCSR520$M_CPU_XCHK_ENA = %X'8'; literal FWCSR520$M_FW_LOCK = %X'10'; literal FWCSR520$M_II32_DRV = %X'20'; literal FWCSR520$M_DMR_ENA = %X'40'; literal FWCSR520$M_DIAG_MODE = %X'80'; literal FWCSR520$M_IO_XCHK_ERR = %X'100'; literal FWCSR520$M_DIAG_XCHK = %X'200'; literal FWCSR520$M_IO_XCHK_ENA = %X'400'; literal FWCSR520$M_MBZ = %X'800'; literal FWCSR520$M_RAIL_ID = %X'1000'; literal FWCSR520$M_SLOT_ID = %X'E000'; literal FWCSR520$S_FWCSRDEF = 4; ! Old size name - synonym literal FWCSR520$S_CIRFWCSR = 4; macro FWCSR520$L_FWCSR = 0,0,32,0 %; ! Firewall Control register macro FWCSR520$V_TRACE_READ = 0,0,1,0 %; ! Read Trace RAMs macro FWCSR520$V_CPU_WRITE = 0,1,1,0 %; ! CVAX write downward console macro FWCSR520$V_CPU_READ = 0,2,1,0 %; ! CVAX read upward console macro FWCSR520$V_CPU_XCHK_ENA = 0,3,1,0 %; ! CVAX crosscheck enable macro FWCSR520$V_FW_LOCK = 0,4,1,0 %; ! Firewall lock macro FWCSR520$V_II32_DRV = 0,5,1,0 %; ! 1132(T) drive macro FWCSR520$V_DMR_ENA = 0,6,1,0 %; ! DMR enable macro FWCSR520$V_DIAG_MODE = 0,7,1,0 %; ! Diagnostic mode macro FWCSR520$V_IO_XCHK_ERR = 0,8,1,0 %; ! UVAX crosscheck error macro FWCSR520$V_DIAG_XCHK = 0,9,1,0 %; ! Diagnostic crosscheck bit macro FWCSR520$V_IO_XCHK_ENA = 0,10,1,0 %; ! UVAX crosscheck enable macro FWCSR520$V_MBZ = 0,11,1,0 %; ! Must be zero macro FWCSR520$V_RAIL_ID = 0,12,1,0 %; ! Rail ID macro FWCSR520$V_SLOT_ID = 0,13,3,0 %; literal FWCSR520$S_SLOT_ID = 3; ! Slot ID macro FWCSR520$V_UNUSED = 0,16,16,0 %; literal FWCSR520$S_UNUSED = 16; ! Unused !*** MODULE $KFERESDEF *** ! ! KNOWN FILE ENTRY DEFINITIONS FOR RESIDENT SECTIONS ! ! Note: The image activator also copies this structure and ! expands the structure to represent the image's data ! sections which have been compressed in process space. ! literal KFERES$M_SHARE_LINK = %X'1'; literal KFERES$M_64BIT_SECTIONS = %X'2'; literal KFERES$K_FIXED_LENGTH = 32; literal KFERES$C_FIXED_LENGTH = 32; literal KFERES$S_KFERESDEF = 32; ! Old size name - synonym literal KFERES$S_KFERES = 36; macro KFERES$L_KFE = 0,0,32,1 %; ! Back pointer to KFE macro KFERES$L_COUNT = 4,0,32,0 %; ! Count of resident sections macro KFERES$W_SIZE = 8,0,16,0 %; ! Size of block macro KFERES$B_TYPE = 10,0,8,0 %; ! Structure type macro KFERES$B_SUBTYPE = 11,0,8,0 %; ! Subtype macro KFERES$L_DATA_COUNT = 12,0,32,0 %; ! Count of data sections macro KFERES$L_FIXUP_BUFFER = 16,0,32,1 %; ! Pointer to fixup buffer macro KFERES$L_FIXUP_SIZE = 20,0,32,0 %; ! Size of fixup buffer macro KFERES$R_FLAGS_OVERLAY = 24,0,32,0 %; macro KFERES$L_FLAGS = 24,0,32,0 %; ! Flags field macro KFERES$R_FLAGS_BITS = 24,0,8,0 %; macro KFERES$V_SHARE_LINK = 24,0,1,0 %; ! Image is installed in a special way ! to gain maximum performance (linkage ! has been made shareable). macro KFERES$V_64BIT_SECTIONS = 24,1,1,0 %; ! 64-bit section records macro KFERES$L_START_ADDRESS = 28,0,32,1 %; ! For images installed with shareable ! linkage, this is the starting P1 address macro KFERES$T_SECTIONS = 32,0,32,0 %; literal KFERES$S_SECTIONS = 4; ! Offset to sections ! (needs an abitrary nonzero length for C) literal KFERES$K_COMPRESSED_DATA = 0; ! For SDA use only literal KFERES$K_READ_ONLY_DATA = 1; literal KFERES$K_CODE = 2; literal KFERES$K_DZRO = 3; literal KFERES$K_WRT = 4; literal KFERES$K_LINKAGE = 5; literal KFERES$K_RESIDENT_CODE = 6; ! For SDA use only literal KFERES$K_RESIDENT_DATA = 7; ! For SDA use only literal KFERES$K_UNKNOWN = 8; ! For SDA use only literal KFERES$M_SHARESECT = %X'1'; literal KFERES$C_SECTION_LENGTH = 24; literal KFERES$K_SECTION_LENGTH = 24; literal KFERES$S_KFERESDEF_SECTION = 24; ! Old size name - synonym literal KFERES$S_KFERES_SECTION = 24; macro KFERES$L_VA = 0,0,32,1 %; ! Starting VA macro KFERES$L_LENGTH = 4,0,32,0 %; ! Length in bytes macro KFERES$L_VBN = 8,0,32,0 %; ! Starting VBN in image file macro KFERES$L_IMAGE_OFFSET = 12,0,32,1 %; ! VA offset in image macro KFERES$L_SECTION_TYPE = 16,0,32,0 %; ! Type of section macro KFERES$L_SECTION_FLAGS = 20,0,32,0 %; ! Name attributes macro KFERES$V_SHARESECT = 20,0,1,0 %; ! Section is shareable literal KFERES64$M_SHARESECT = %X'1'; literal KFERES64$C_SECTION_LENGTH = 48; literal KFERES64$K_SECTION_LENGTH = 48; literal KFERES64$S_KFERES_64BIT_SECTION = 48; macro KFERES64$L_NEXT = 0,0,32,1 %; ! Pointer to next KFERES64 macro KFERES64$L_VBN = 4,0,32,0 %; ! Starting VBN in image file macro KFERES64$W_SIZE = 8,0,16,0 %; ! Size of block macro KFERES64$B_TYPE = 10,0,8,0 %; ! Structure type macro KFERES64$B_SUBTYPE = 11,0,8,0 %; ! Subtype macro KFERES64$L_SECTION_TYPE = 12,0,32,0 %; ! Type of section macro KFERES64$L_SECTION_FLAGS = 16,0,32,0 %; ! Name attributes macro KFERES64$V_SHARESECT = 16,0,1,0 %; ! Section is shareable macro KFERES64$PQ_VA = 24,0,0,1 %; literal KFERES64$S_VA = 8; ! Starting VA macro KFERES64$Q_LENGTH = 32,0,0,0 %; literal KFERES64$S_LENGTH = 8; ! Length in bytes macro KFERES64$PQ_IMAGE_OFFSET = 40,0,0,1 %; literal KFERES64$S_IMAGE_OFFSET = 8; ! VA offset in image !*** MODULE $KFHDEF *** ! ! KNOWN FILE IMAGE HEADER DEFINITIONS *** obsolete, to be removed *** ! literal KFH$K_LENGTH = 12; ! LENGTH OF OVERHEAD AREA literal KFH$C_LENGTH = 12; ! LENGTH OF OVERHEAD AREA literal KFH$S_KFHDEF = 12; ! literal KFH$S_KFH = 12; macro KFH$L_BUFEND = 0,0,32,1 %; ! ADDRESS OF END OF KNOWN FILE HEADER macro KFH$L_KFIADR = 4,0,32,1 %; ! ADDRESS OF ASSOCIATED KNOWN FILE ENTRY macro KFH$W_SIZE = 8,0,16,0 %; ! SIZE OF DYNAMIC STRUCTURE macro KFH$B_TYPE = 10,0,8,0 %; ! DYNAMIC STRUCTURE TYPE ! THE REMAINDER OF THIS STRUCTURE CONTAINS THE IMAGE HEADER OF THE ! SPECIFIED KNOWN FILE. THE LOCATION KFI$L_IMGHDR IN THE KNOWN FILE ! ENTRY POINTS KFH$C_LENGTH INTO THIS STRUCTURE, I.E AT THE IMAGE HEADER ! ITSELF. ! !*** MODULE $KFIDEF *** ! ! KNOWN FILE ENTRY DEFINITIONS *** obsolete, to be removed *** ! literal KFI$M_KFIHD = %X'1'; literal KFI$M_FILIDOPEN = %X'2'; literal KFI$M_DONOTOPEN = %X'4'; literal KFI$M_NOREPLACE = %X'40'; literal KFI$M_MARKDEL = %X'80'; literal KFI$K_KFIHDLEN = 20; ! LENGTH OF KFI HEADER FIXED PORTION literal KFI$C_KFIHDLEN = 20; ! LENGTH OF KFI HEADER FIXED PORTION literal KFI$M_KFISEQ = %X'3'; literal KFI$M_KP_OPEN = %X'1'; literal KFI$M_KP_RESHDR = %X'2'; literal KFI$M_KP_SHARED = %X'4'; literal KFI$M_PROTECT = %X'8'; literal KFI$M_LIM = %X'40'; literal KFI$M_PROCPRIV = %X'80'; literal KFI$M_IS_RESHDR = %X'100'; literal KFI$M_IS_SHARED = %X'200'; literal KFI$M_SHMIDENT = %X'4000'; literal KFI$M_COMPATMOD = %X'8000'; literal KFI$K_LENGTH = 52; ! LENGTH OF FIXED AREA OF KFI ENTRY literal KFI$C_LENGTH = 52; ! LENGTH OF FIXED AREA OF KFI ENTRY literal KFI$S_KFIDEF = 52; ! Old size name - synonym literal KFI$S_KFI = 52; macro KFI$L_KFIQFL = 0,0,32,1 %; ! KNOWN FILE QUEUE FORWARD LINK macro KFI$L_KFIQBL = 4,0,32,1 %; ! KNOWN FILE QUEUE BACK LINK macro KFI$W_SIZE = 8,0,16,0 %; ! SIZE OF BLOCK macro KFI$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE macro KFI$B_KFICTL = 11,0,8,0 %; ! CONTROL BITS macro KFI$V_KFIHD = 11,0,1,0 %; ! KNOWN FILE HEADER BLOCK macro KFI$V_FILIDOPEN = 11,1,1,0 %; ! OPEN BY FILE ID IF SET macro KFI$V_DONOTOPEN = 11,2,1,0 %; ! DO NOT OPEN THE FILE IF SET macro KFI$V_NOREPLACE = 11,6,1,0 %; ! DELETE AND DO NOT REPLACE ENTRY macro KFI$V_MARKDEL = 11,7,1,0 %; ! ENTRY IS TO BE DELETED macro KFI$B_DEVUCB = 12,0,8,0 %; ! DEVICE UCB OFFSET macro KFI$B_DEVNAM = 12,0,8,0 %; ! NAME THE ABOVE CONSISTENTLY macro KFI$B_DIRNAM = 13,0,8,0 %; ! DIRECTORY NAME STRING OFFSET macro KFI$B_FILNAM = 14,0,8,0 %; ! FILE NAME STRING OFFSET macro KFI$B_TYPNAM = 15,0,8,0 %; ! FILE TYPE STRING OFFSET macro KFI$W_REFCNT = 16,0,16,0 %; ! REFERENCE COUNT macro KFI$B_KFIQNUM = 18,0,8,0 %; ! KFIQ NUMBER (INDEX INTO VECTOR OF KFIQ'S) macro KFI$B_KFISEQ = 19,0,8,0 %; ! KNOWN FILE ENTRY SEQUENCE NUMBER macro KFI$V_KFISEQ = 19,0,2,0 %; literal KFI$S_KFISEQ = 2; ! SEQUENCE NUMBER FIELD macro KFI$W_FLAGS = 20,0,16,0 %; ! FLAGS WORD macro KFI$V_KP_OPEN = 20,0,1,0 %; ! KEEP THE IMAGE FILE OPEN macro KFI$V_KP_RESHDR = 20,1,1,0 %; ! MAKE IMAGE HEADER RESIDENT macro KFI$V_KP_SHARED = 20,2,1,0 %; ! MAKE IMAGE SHARED macro KFI$V_PROTECT = 20,3,1,0 %; ! KNOWN FILE WAS INSTALLED PROTECTED macro KFI$V_LIM = 20,6,1,0 %; ! LINKABLE IMAGE macro KFI$V_PROCPRIV = 20,7,1,0 %; ! USE PROCESS PRIVILEGE MASK macro KFI$V_IS_RESHDR = 20,8,1,0 %; ! IMAGE HEADER BLOCK IS RESIDENT macro KFI$V_IS_SHARED = 20,9,1,0 %; ! IMAGE IS SHARED macro KFI$V_SHMIDENT = 20,14,1,0 %; ! SHARED MEMORY IDENT ALREADY SET macro KFI$V_COMPATMOD = 20,15,1,0 %; ! IMAGE IS COMPATABILITY MODE macro KFI$W_GBLSECCNT = 22,0,16,0 %; ! GLOBAL SECTION COUNT IF SHARED macro KFI$L_USECNT = 24,0,32,0 %; ! USAGE COUNTER macro KFI$L_WINDOW = 28,0,32,1 %; ! WCB ADDRESS IF OPEN macro KFI$W_FID = 28,0,16,0 %; ! FILE ID macro KFI$W_FID_NUM = 28,0,16,0 %; ! FILE NUMBER FIELD OF FILE ID macro KFI$W_FID_SEQ = 30,0,16,0 %; ! FILE SEQUENCE NUMBER FIELD OF FILE ID macro KFI$L_IMGHDR = 32,0,32,1 %; ! IMAGE HEADER ADDRESS IF RESIDENT macro KFI$W_FID_RVN = 32,0,16,0 %; ! RELATIVE VOLUME NUMBER FIELD OF FILE ID macro KFI$Q_PROCPRIV = 36,0,0,0 %; literal KFI$S_PROCPRIV = 8; ! PROCESS PRIVILEGE MASK macro KFI$B_MATCHCTL = 44,0,8,0 %; ! GLOBAL SECTION MATCH CONTROL macro KFI$W_AMECOD = 46,0,16,0 %; ! IMAGE HEADER CODE SPECIFYING AME macro KFI$L_IDENT = 48,0,32,0 %; ! GLOBAL SECTION IDENT VALUE !*** MODULE $KFPDEF *** ! ! KNOWN FILE POINTER BLOCK DEFINITIONS *** obsolete, to be removed *** ! literal KFP$S_KFPDEF = 16; literal KFP$S_KFP = 16; macro KFP$B_QUECOUNT = 0,0,8,0 %; ! INDEX OF LAST KNOWN FILE LIST IN USE macro KFP$W_SIZE = 8,0,16,0 %; ! SIZE OF POINTER BLOCK IN BYTES macro KFP$B_TYPE = 10,0,8,0 %; ! POINTER BLOCK TYPE macro KFP$B_TYPE1 = 11,0,8,0 %; ! TYPE OF STRUCTURE POINTED TO macro KFP$L_QUE0 = 12,0,32,0 %; ! POINTER TO KNOWN FILE QUEUE 0 !*** MODULE $KFPBDEF *** ! ! KNOWN FILE POINTER BLOCK DEFINITIONS ! literal KFPB$K_LENGTH = 16; ! Length of pointer block literal KFPB$C_LENGTH = 16; ! Length of pointer block literal KFPB$S_KFPBDEF = 16; literal KFPB$S_KFPB = 16; macro KFPB$L_KFDLST = 0,0,32,1 %; ! Device, Directory, Extension (KFD) list link macro KFPB$L_KFEHSHTAB = 4,0,32,1 %; ! Address of Known file name hash table macro KFPB$W_SIZE = 8,0,16,0 %; ! Size of pointer block in bytes macro KFPB$B_TYPE = 10,0,8,0 %; ! Pointer block type macro KFPB$B_SPARE = 11,0,8,0 %; ! spare byte macro KFPB$W_KFDLSTCNT = 12,0,16,0 %; ! Number of entries in KFD list macro KFPB$W_HSHTABLEN = 14,0,16,0 %; ! Length of Hash table !*** MODULE $KFRHDEF *** ! ! KNOWN FILE RESIDENT IMAGE HEADER DEFINITIONS ! literal KFRH$K_LENGTH = 12; ! Length of overhead area literal KFRH$C_LENGTH = 12; ! Length of overhead area literal KFRH$S_KFRHDEF = 12; ! Old size name - synonym ! literal KFRH$S_KFRH = 12; macro KFRH$L_BUFEND = 0,0,32,1 %; ! Address of end of known file header macro KFRH$W_ALIAS = 4,0,16,0 %; ! Use secondary name on activation macro KFRH$W_SIZE = 8,0,16,0 %; ! Size of dynamic structure macro KFRH$B_TYPE = 10,0,8,0 %; ! Dynamic structure type macro KFRH$B_HDRVER = 11,0,8,0 %; ! Image header version macro KFRH$T_IHD = 12,0,0,0 %; ! Offset to decoded Image Header ! THE REMAINDER OF THIS STRUCTURE CONTAINS THE IMAGE HEADER OF THE ! SPECIFIED KNOWN FILE. THE LOCATION KFE$L_IMGHDR IN THE KNOWN FILE ! ENTRY POINTS KFRH$C_LENGTH INTO THIS STRUCTURE, I.E AT THE IMAGE HEADER ! ITSELF. ! !*** MODULE $KPSTACKDEF IDENT X-2 *** ! KPSTKFP ! Optional saved floating point layout on the memory ! stack. ! ! Floating registers are 82 bits but are spilled to ! octaword boundries. ! literal KPSTKFP$S_KPSTKFP = 320; macro KPSTKFP$O_SAVED_F2 = 0,0,0,1 %; literal KPSTKFP$S_SAVED_F2 = 16; ! floating register F2 macro KPSTKFP$O_SAVED_F3 = 16,0,0,1 %; literal KPSTKFP$S_SAVED_F3 = 16; ! floating register F3 macro KPSTKFP$O_SAVED_F4 = 32,0,0,1 %; literal KPSTKFP$S_SAVED_F4 = 16; ! floating register F4 macro KPSTKFP$O_SAVED_F5 = 48,0,0,1 %; literal KPSTKFP$S_SAVED_F5 = 16; ! floating register F5 macro KPSTKFP$O_SAVED_F16 = 64,0,0,1 %; literal KPSTKFP$S_SAVED_F16 = 16; ! floating register F16 macro KPSTKFP$O_SAVED_F17 = 80,0,0,1 %; literal KPSTKFP$S_SAVED_F17 = 16; ! floating register F17 macro KPSTKFP$O_SAVED_F18 = 96,0,0,1 %; literal KPSTKFP$S_SAVED_F18 = 16; ! floating register F18 macro KPSTKFP$O_SAVED_F19 = 112,0,0,1 %; literal KPSTKFP$S_SAVED_F19 = 16; ! floating register F19 macro KPSTKFP$O_SAVED_F20 = 128,0,0,1 %; literal KPSTKFP$S_SAVED_F20 = 16; ! floating register F20 macro KPSTKFP$O_SAVED_F21 = 144,0,0,1 %; literal KPSTKFP$S_SAVED_F21 = 16; ! floating register F21 macro KPSTKFP$O_SAVED_F22 = 160,0,0,1 %; literal KPSTKFP$S_SAVED_F22 = 16; ! floating register F22 macro KPSTKFP$O_SAVED_F23 = 176,0,0,1 %; literal KPSTKFP$S_SAVED_F23 = 16; ! floating register F23 macro KPSTKFP$O_SAVED_F24 = 192,0,0,1 %; literal KPSTKFP$S_SAVED_F24 = 16; ! floating register F24 macro KPSTKFP$O_SAVED_F25 = 208,0,0,1 %; literal KPSTKFP$S_SAVED_F25 = 16; ! floating register F25 macro KPSTKFP$O_SAVED_F26 = 224,0,0,1 %; literal KPSTKFP$S_SAVED_F26 = 16; ! floating register F26 macro KPSTKFP$O_SAVED_F27 = 240,0,0,1 %; literal KPSTKFP$S_SAVED_F27 = 16; ! floating register F27 macro KPSTKFP$O_SAVED_F28 = 256,0,0,1 %; literal KPSTKFP$S_SAVED_F28 = 16; ! floating register F28 macro KPSTKFP$O_SAVED_F29 = 272,0,0,1 %; literal KPSTKFP$S_SAVED_F29 = 16; ! floating register F29 macro KPSTKFP$O_SAVED_F30 = 288,0,0,1 %; literal KPSTKFP$S_SAVED_F30 = 16; ! floating register F30 macro KPSTKFP$O_SAVED_F31 = 304,0,0,1 %; literal KPSTKFP$S_SAVED_F31 = 16; ! floating register F31 ! KPSTACK ! Saved context layout on the memory stack literal KPSTACK$M_SAVE_FP = %X'1'; literal KPSTACK$K_BASE_LENGTH = 176; literal KPSTACK$S_KPSTACK = 496; macro KPSTACK$Q_UNAT_PRESPILL = 0,0,0,1 %; literal KPSTACK$S_UNAT_PRESPILL = 8; ! UNAT before regs spilled macro KPSTACK$W_SIZE = 8,0,16,0 %; ! Structure size macro KPSTACK$B_TYPE = 10,0,8,0 %; ! DYN$C_MISC macro KPSTACK$B_SUBTYPE = 11,0,8,0 %; ! DYN$C_KPSTACK macro KPSTACK$L_FLAGS = 12,0,32,0 %; ! Flags/alignment macro KPSTACK$V_SAVE_FP = 12,0,1,0 %; ! Floating point array saved macro KPSTACK$Q_SAVED_R4 = 16,0,0,1 %; literal KPSTACK$S_SAVED_R4 = 8; ! Saved R4 macro KPSTACK$Q_SAVED_R5 = 24,0,0,1 %; literal KPSTACK$S_SAVED_R5 = 8; ! Saved R5 macro KPSTACK$Q_SAVED_R6 = 32,0,0,1 %; literal KPSTACK$S_SAVED_R6 = 8; ! Saved R6 macro KPSTACK$Q_SAVED_R7 = 40,0,0,1 %; literal KPSTACK$S_SAVED_R7 = 8; ! Saved R7 macro KPSTACK$Q_UNAT_POSTSPILL = 48,0,0,1 %; literal KPSTACK$S_UNAT_POSTSPILL = 8; ! UNAT after regs spilled macro KPSTACK$Q_SAVED_PR = 56,0,0,1 %; literal KPSTACK$S_SAVED_PR = 8; ! Predicate registers macro KPSTACK$Q_SAVED_B0 = 64,0,0,1 %; literal KPSTACK$S_SAVED_B0 = 8; ! branch reg B0 macro KPSTACK$Q_SAVED_B1 = 72,0,0,1 %; literal KPSTACK$S_SAVED_B1 = 8; ! branch reg B1 macro KPSTACK$Q_SAVED_B2 = 80,0,0,1 %; literal KPSTACK$S_SAVED_B2 = 8; ! branch reg B2 macro KPSTACK$Q_SAVED_B3 = 88,0,0,1 %; literal KPSTACK$S_SAVED_B3 = 8; ! branch reg B3 macro KPSTACK$Q_SAVED_B4 = 96,0,0,1 %; literal KPSTACK$S_SAVED_B4 = 8; ! branch reg B4 macro KPSTACK$Q_SAVED_B5 = 104,0,0,1 %; literal KPSTACK$S_SAVED_B5 = 8; ! branch reg B5 macro KPSTACK$Q_SAVED_LC = 112,0,0,1 %; literal KPSTACK$S_SAVED_LC = 8; ! ar.LC (loop counter) macro KPSTACK$Q_SAVED_RSC = 120,0,0,1 %; literal KPSTACK$S_SAVED_RSC = 8; ! ar.RSC macro KPSTACK$Q_SAVED_PFS = 128,0,0,1 %; literal KPSTACK$S_SAVED_PFS = 8; ! ar.PFS macro KPSTACK$Q_SAVED_RNAT = 136,0,0,1 %; literal KPSTACK$S_SAVED_RNAT = 8; ! ar.RNAT (after reg stack flush) macro KPSTACK$Q_SAVED_BSP = 144,0,0,1 %; literal KPSTACK$S_SAVED_BSP = 8; ! RSE backing store pointer macro KPSTACK$Q_SAVED_PSP = 152,0,0,1 %; literal KPSTACK$S_SAVED_PSP = 8; ! Previous stack pointer (unwind) macro KPSTACK$Q_SAVED_FPSR = 160,0,0,1 %; literal KPSTACK$S_SAVED_FPSR = 8; ! ar.FPSR macro KPSTACK$R_FP_REGS = 176,0,0,0 %; literal KPSTACK$S_FP_REGS = 320; ! optional floating point region ! KPSIG ! This is the layout of the base of a KP memory stack, which looks as follows: ! ! 0(SP) Scratch space for (sp at call to KP routine) ! 8(SP) called routine ! 16(SP) Saved GP (caller's GP) ! 24(SP) 00000000.00000000 (alignment) ! 32(SP) 00000000.00000000 } ! 40(SP) 00000000.00000000 } signature expected by code ! 48(SP) DEADDEAD.DEADDEAD } ! 56(SP) KPB address (highest useable address) ! [Guard Page] ! ! The low 4 quads are used by the IA64 implementation. The high 4 quads are ! required by both the Alpha and IA64 code. literal KPSIG$S_KPSIG = 64; macro KPSIG$Q_CALLED_SCR1 = 0,0,0,1 %; literal KPSIG$S_CALLED_SCR1 = 8; ! Scratch space for called routine macro KPSIG$Q_CALLED_SCR2 = 8,0,0,1 %; literal KPSIG$S_CALLED_SCR2 = 8; ! Scratch space for called routine macro KPSIG$Q_SAVED_GP = 16,0,0,1 %; literal KPSIG$S_SAVED_GP = 8; ! GP saved around call macro KPSIG$Q_ZERO1 = 32,0,0,0 %; literal KPSIG$S_ZERO1 = 8; ! MBZ macro KPSIG$Q_ZERO2 = 40,0,0,0 %; literal KPSIG$S_ZERO2 = 8; ! MBZ macro KPSIG$Q_DEAD_SIG = 48,0,0,0 %; literal KPSIG$S_DEAD_SIG = 8; ! 0xDEADDEAD.DEADDEAD macro KPSIG$PQ_KPB = 56,0,0,1 %; literal KPSIG$S_KPB = 8; ! pointer to KPB !*** MODULE $KRIPRDEF *** ! ------------------------------------------------------------------- ! KRIPR - IPF Kernel Register Holding Emulated Processor Registers ! literal KRIPR$M_IPL = %X'FF'; literal KRIPR$M_PREVMODE = %X'F00'; literal KRIPR$M_CURSTACKMODE = %X'F000'; literal KRIPR$M_INTERRUPT_DEPTH = %X'FF0000'; literal KRIPR$M_KT_ID = %X'FF000000'; literal KRIPR$M_FILL_6 = %X'3FFFFFFFFFFFFFFF'; literal KRIPR$M_SWIS_DISABLE_LOG = %X'4000000000000000'; literal KRIPR$M_SWIS_INHIBIT_LOG = %X'8000000000000000'; literal KRIPR$S_KRIPR = 8; macro KRIPR$Q_QUADWORD = 0,0,0,1 %; literal KRIPR$S_QUADWORD = 8; ! Entire register macro KRIPR$B_IPL = 0,0,8,1 %; ! IPL (needs only 5 bits, but unless we need more later, ! multiples of 4 bits makes it easier to read/debug macro KRIPR$B_MODES = 1,0,8,1 %; ! PREVMODE and CURSTACKMODE together macro KRIPR$B_INTERRUPT_DEPTH = 2,0,8,1 %; ! Count the depths of interrupt state (see interrupt pending in SRM) macro KRIPR$B_KT_ID = 3,0,8,1 %; ! Kernel thread id of current thread macro KRIPR$B_FILL_2 = 4,0,8,1 %; macro KRIPR$B_FILL_3 = 5,0,8,1 %; macro KRIPR$B_FILL_4 = 6,0,8,1 %; macro KRIPR$B_FLAGS = 7,0,8,1 %; macro KRIPR$V_IPL = 0,0,8,0 %; literal KRIPR$S_IPL = 8; ! IPL (needs only 5 bits, but unless we need more later, macro KRIPR$V_PREVMODE = 0,8,4,0 %; literal KRIPR$S_PREVMODE = 4; ! Previous mode. Needs only 2 bits, but (see IPL) macro KRIPR$V_CURSTACKMODE = 0,12,4,0 %; literal KRIPR$S_CURSTACKMODE = 4; ! Current stack mode. Needs only 2 bits, but (see IPL) macro KRIPR$V_INTERRUPT_DEPTH = 0,16,8,0 %; literal KRIPR$S_INTERRUPT_DEPTH = 8; ! Count the depths of interrupt state (see interrupt pending in SRM) macro KRIPR$V_KT_ID = 0,24,8,0 %; literal KRIPR$S_KT_ID = 8; ! Kernel thread id of current thread macro KRIPR$V_SWIS_DISABLE_LOG = 4,30,1,0 %; macro KRIPR$V_SWIS_INHIBIT_LOG = 4,31,1,0 %; ! ***************************************************** ! ! The following constants define which kernel registers ! are used for what purpose. When you want to reference ! them, use KR$C_ in place of the register symbols supplied ! by the language. For example, in C, you can access the ! SLOT_VA by saying ! ! __getReg(KR$C_SLOT_VA) ! ! ***************************************************** literal KR$C_SLOT_VA = 3079; ! Here is the virtual address of the CPU slot structure literal KR$C_CPUDB_VA = 3078; ! The virtual address of the CPU database literal KR$C_NEXT_TIMER = 3077; ! The value of the next timer interrupt literal KR$C_KRIPR = 3075; ! This register contains several different data as defined above !*** MODULE $LCADEF *** literal LCA$L_MEM_BCR0_L = 536870912; literal LCA$L_MEM_BCR0_H = 1; literal LCA$L_MEM_BCR1_L = 536870920; literal LCA$L_MEM_BCR1_H = 1; literal LCA$L_MEM_BCR2_L = 536870928; literal LCA$L_MEM_BCR2_H = 1; literal LCA$L_MEM_BCR3_L = 536870936; literal LCA$L_MEM_BCR3_H = 1; literal LCA$L_MEM_BMR0_L = 536870944; literal LCA$L_MEM_BMR0_H = 1; literal LCA$L_MEM_BMR1_L = 536870952; literal LCA$L_MEM_BMR1_H = 1; literal LCA$L_MEM_BMR2_L = 536870960; literal LCA$L_MEM_BMR2_H = 1; literal LCA$L_MEM_BMR3_L = 536870968; literal LCA$L_MEM_BMR3_H = 1; literal LCA$L_MEM_BTR0_L = 536870976; literal LCA$L_MEM_BTR0_H = 1; literal LCA$L_MEM_BTR1_L = 536870984; literal LCA$L_MEM_BTR1_H = 1; literal LCA$L_MEM_BTR2_L = 536870992; literal LCA$L_MEM_BTR2_H = 1; literal LCA$L_MEM_BTR3_L = 536871000; literal LCA$L_MEM_BTR3_H = 1; literal LCA$L_MEM_GTR_L = 536871008; literal LCA$L_MEM_GTR_H = 1; literal LCA$L_MEM_ESR_L = 536871016; literal LCA$L_MEM_ESR_H = 1; literal LCA$L_MEM_EAR_L = 536871024; literal LCA$L_MEM_EAR_H = 1; literal LCA$L_MEM_CAR_L = 536871032; literal LCA$L_MEM_CAR_H = 1; literal LCA$L_MEM_VGR_L = 536871040; literal LCA$L_MEM_VGR_H = 1; literal LCA$L_MEM_PLM_L = 536871048; literal LCA$L_MEM_PLM_H = 1; literal LCA$L_MEM_FOR_L = 536871056; literal LCA$L_MEM_FOR_H = 1; literal LCA$L_PMR_L = 536871064; literal LCA$L_PMR_H = 1; literal LCA$L_IOC_HAE_PA_L = -2147483648; literal LCA$L_IOC_HAE_PA_H = 1; literal LCA$L_IOC_CFG_CYC_PA_L = -2147483648; literal LCA$L_IOC_CFG_CYC_PA_H = 32; literal LCA$L_IOC_STAT0_PA_L = -2147483584; literal LCA$L_IOC_STAT0_PA_H = 1; literal LCA$L_IOC_STAT1_PA_L = -2147483552; literal LCA$L_IOC_STAT1_PA_H = 1; literal LCA$L_IOC_TBIA_PA_L = -2147483520; literal LCA$L_IOC_TBIA_PA_H = 1; literal LCA$L_IOC_TB_ENA_PA_L = -2147483648; literal LCA$L_IOC_TB_ENA_PA_H = 160; literal LCA$L_PCI_SFT_RST_PA_L = -2147483648; literal LCA$L_PCI_SFT_RST_PA_H = 192; literal LCA$L_PCI_PAR_DIS_PA_L = -2147483648; literal LCA$L_PCI_PAR_DIS_PA_H = 224; literal LCA$L_IOC_W_BASE0_PA_L = -2147483392; literal LCA$L_IOC_W_BASE0_PA_H = 1; literal LCA$L_IOC_W_BASE1_PA_L = -2147483360; literal LCA$L_IOC_W_BASE1_PA_H = 1; literal LCA$L_IOC_W_MASK0_PA_L = -2147483328; literal LCA$L_IOC_W_MASK0_PA_H = 1; literal LCA$L_IOC_W_MASK1_PA_L = -2147483296; literal LCA$L_IOC_W_MASK1_PA_H = 1; literal LCA$L_IOC_T_BASE0_PA_L = -2147483264; literal LCA$L_IOC_T_BASE0_PA_H = 1; literal LCA$L_IOC_T_BASE1_PA_L = -2147483232; literal LCA$L_IOC_T_BASE1_PA_H = 1; literal LCA$L_IOC_TB_TAG0_PA_L = -2130706432; literal LCA$L_IOC_TB_TAG0_PA_H = 1; literal LCA$L_IOC_TB_TAG1_PA_L = -2130706400; literal LCA$L_IOC_TB_TAG1_PA_H = 1; literal LCA$L_IOC_TB_TAG2_PA_L = -2130706368; literal LCA$L_IOC_TB_TAG2_PA_H = 1; literal LCA$L_IOC_TB_TAG3_PA_L = -2130706336; literal LCA$L_IOC_TB_TAG3_PA_H = 1; literal LCA$L_IOC_TB_TAG4_PA_L = -2130706304; literal LCA$L_IOC_TB_TAG4_PA_H = 1; literal LCA$L_IOC_TB_TAG5_PA_L = -2130706272; literal LCA$L_IOC_TB_TAG5_PA_H = 1; literal LCA$L_IOC_TB_TAG6_PA_L = -2130706240; literal LCA$L_IOC_TB_TAG6_PA_H = 1; literal LCA$L_IOC_TB_TAG7_PA_L = -2130706208; literal LCA$L_IOC_TB_TAG7_PA_H = 1; literal LCA$L_IOC_IACK_SC_PA_L = -1610612736; literal LCA$L_IOC_IACK_SC_PA_H = 1; literal LCA$L_PCI_IO_PA_L = -1073741824; literal LCA$L_PCI_IO_PA_H = 1; literal LCA$L_PCI_CFG_PA_L = -536870912; literal LCA$L_PCI_CFG_PA_H = 1; literal LCA$L_PCI_SPARSE_MEM_PA_L = 0; literal LCA$L_PCI_SPARSE_MEM_PA_H = 2; literal LCA$L_PCI_DENSE_MEM_PA_L = 0; literal LCA$L_PCI_DENSE_MEM_PA_H = 3; literal LCA$M_PMR_PRMDIV = %X'7'; literal LCA$M_PMR_OVRDIV = %X'38'; literal LCA$M_PMR_INTOVR = %X'40'; literal LCA$M_PMR_DMAOVR = %X'80'; literal LCA$M_PMR_OVRCC_EVEN = %X'FFFF0000'; literal LCA$M_PMR_OVRCC_ODD = %X'FFFFFF0000000000'; literal LCA$K_PMR_SPEED_IDLE = 4; literal LCA$K_PMR_SPEED_LOW = 2; literal LCA$K_PMR_SPEED_MEDIUM = 1; literal LCA$K_PMR_SPEED_HIGH = 0; literal LCA$M_HAE_BITS = %X'F8000000'; literal LCA$M_CFG_AD = %X'3'; literal LCA$M_STAT0_CMD = %X'F'; literal LCA$M_IOC_ERR = %X'10'; literal LCA$M_IOC_LOST_ERR = %X'20'; literal LCA$M_IOC_T_HIT = %X'40'; literal LCA$M_IOC_T_REF = %X'80'; literal LCA$M_IOC_ERR_CODE = %X'700'; literal LCA$M_STAT1_ADDR = %X'FFFFFFFF'; literal LCA$M_TB_EN = %X'80'; literal LCA$M_PCI_SFT_RESET = %X'40'; literal LCA$M_PCI_PAR_DIS = %X'20'; literal LCA$M_W_BASE0_BITS = %X'FFF00000'; literal LCA$M_W_BASE0_SG = %X'100000000'; literal LCA$M_W_BASE0_WEN = %X'200000000'; literal LCA$M_W_BASE1_BITS = %X'FFF00000'; literal LCA$M_W_BASE1_SG = %X'100000000'; literal LCA$M_W_BASE1_WEN = %X'200000000'; literal LCA$M_W_MASK0_BITS = %X'FFF00000'; literal LCA$M_W_MASK1_BITS = %X'FFF00000'; literal LCA$M_T_BASE0_BITS = %X'FFFFFC00'; literal LCA$M_T_BASE1_BITS = %X'FFFFFC00'; literal LCA$M_TB_TAG0_BITS = %X'FFFFE000'; literal LCA$M_TB_TAG1_BITS = %X'FFFFE000'; literal LCA$M_TB_TAG2_BITS = %X'FFFFE000'; literal LCA$M_TB_TAG3_BITS = %X'FFFFE000'; literal LCA$M_TB_TAG4_BITS = %X'FFFFE000'; literal LCA$M_TB_TAG5_BITS = %X'FFFFE000'; literal LCA$M_TB_TAG6_BITS = %X'FFFFE000'; literal LCA$M_TB_TAG7_BITS = %X'FFFFE000'; literal LCA$S_LCA = 24576; macro LCA$Q_BCR0 = 0,0,0,1 %; literal LCA$S_BCR0 = 8; macro LCA$Q_BCR1 = 8,0,0,1 %; literal LCA$S_BCR1 = 8; macro LCA$Q_BCR2 = 16,0,0,1 %; literal LCA$S_BCR2 = 8; macro LCA$Q_BCR3 = 24,0,0,1 %; literal LCA$S_BCR3 = 8; macro LCA$Q_BMR0 = 32,0,0,1 %; literal LCA$S_BMR0 = 8; macro LCA$Q_BMR1 = 40,0,0,1 %; literal LCA$S_BMR1 = 8; macro LCA$Q_BMR2 = 48,0,0,1 %; literal LCA$S_BMR2 = 8; macro LCA$Q_BMR3 = 56,0,0,1 %; literal LCA$S_BMR3 = 8; macro LCA$Q_BTR0 = 64,0,0,1 %; literal LCA$S_BTR0 = 8; macro LCA$Q_BTR1 = 72,0,0,1 %; literal LCA$S_BTR1 = 8; macro LCA$Q_BTR2 = 80,0,0,1 %; literal LCA$S_BTR2 = 8; macro LCA$Q_BTR3 = 88,0,0,1 %; literal LCA$S_BTR3 = 8; macro LCA$Q_GTR = 96,0,0,1 %; literal LCA$S_GTR = 8; macro LCA$Q_ESR = 104,0,0,1 %; literal LCA$S_ESR = 8; macro LCA$Q_EAR = 112,0,0,1 %; literal LCA$S_EAR = 8; macro LCA$Q_CAR = 120,0,0,1 %; literal LCA$S_CAR = 8; macro LCA$Q_VGR = 128,0,0,1 %; literal LCA$S_VGR = 8; macro LCA$Q_PLM = 136,0,0,1 %; literal LCA$S_PLM = 8; macro LCA$Q_FOR = 144,0,0,1 %; literal LCA$S_FOR = 8; macro LCA$Q_PMR = 152,0,0,1 %; literal LCA$S_PMR = 8; macro LCA$V_PMR_PRMDIV = 152,0,3,0 %; literal LCA$S_PMR_PRMDIV = 3; ! Primary speed divisor macro LCA$V_PMR_OVRDIV = 152,3,3,0 %; literal LCA$S_PMR_OVRDIV = 3; ! Override speed divisor macro LCA$V_PMR_INTOVR = 152,6,1,0 %; ! Interrupt selects override macro LCA$V_PMR_DMAOVR = 152,7,1,0 %; ! DMA selects override macro LCA$V_PMR_OVRCC_EVEN = 152,16,16,0 %; literal LCA$S_PMR_OVRCC_EVEN = 16; ! Even bits of Override CC macro LCA$V_PMR_OVRCC_ODD = 156,8,24,0 %; literal LCA$S_PMR_OVRCC_ODD = 24; ! Odd bits of Override CC macro LCA$Q_HAE = 8192,0,0,1 %; literal LCA$S_HAE = 8; macro LCA$V_HAE_BITS = 8192,27,5,0 %; macro LCA$Q_PCI_CFG_CYC = 8224,0,0,1 %; literal LCA$S_PCI_CFG_CYC = 8; macro LCA$V_CFG_AD = 8224,0,2,0 %; literal LCA$S_CFG_AD = 2; macro LCA$Q_STAT0 = 8256,0,0,1 %; literal LCA$S_STAT0 = 8; macro LCA$V_STAT0_CMD = 8256,0,4,0 %; literal LCA$S_STAT0_CMD = 4; macro LCA$V_IOC_ERR = 8256,4,1,0 %; macro LCA$V_IOC_LOST_ERR = 8256,5,1,0 %; macro LCA$V_IOC_T_HIT = 8256,6,1,0 %; macro LCA$V_IOC_T_REF = 8256,7,1,0 %; macro LCA$V_IOC_ERR_CODE = 8256,8,3,0 %; literal LCA$S_IOC_ERR_CODE = 3; macro LCA$Q_STAT1 = 8288,0,0,1 %; literal LCA$S_STAT1 = 8; macro LCA$V_STAT1_ADDR = 8288,0,32,0 %; literal LCA$S_STAT1_ADDR = 32; macro LCA$Q_TBIA = 8320,0,0,1 %; literal LCA$S_TBIA = 8; macro LCA$Q_TB_ENA = 8352,0,0,1 %; literal LCA$S_TB_ENA = 8; macro LCA$V_TB_EN = 8352,7,1,0 %; macro LCA$Q_PCI_SFT_RST = 8384,0,0,1 %; literal LCA$S_PCI_SFT_RST = 8; macro LCA$V_PCI_SFT_RESET = 8384,6,1,0 %; macro LCA$Q_PCI_PAR_DIS = 8416,0,0,1 %; literal LCA$S_PCI_PAR_DIS = 8; macro LCA$V_PCI_PAR_DIS = 8416,5,1,0 %; macro LCA$Q_W_BASE0 = 8448,0,0,1 %; literal LCA$S_W_BASE0 = 8; macro LCA$V_W_BASE0_BITS = 8448,20,12,0 %; macro LCA$V_W_BASE0_SG = 8452,0,1,0 %; macro LCA$V_W_BASE0_WEN = 8452,1,1,0 %; macro LCA$Q_W_BASE1 = 8480,0,0,1 %; literal LCA$S_W_BASE1 = 8; macro LCA$V_W_BASE1_BITS = 8480,20,12,0 %; macro LCA$V_W_BASE1_SG = 8484,0,1,0 %; macro LCA$V_W_BASE1_WEN = 8484,1,1,0 %; macro LCA$Q_W_MASK0 = 8512,0,0,1 %; literal LCA$S_W_MASK0 = 8; macro LCA$V_W_MASK0_BITS = 8512,20,12,0 %; macro LCA$Q_W_MASK1 = 8544,0,0,1 %; literal LCA$S_W_MASK1 = 8; macro LCA$V_W_MASK1_BITS = 8544,20,12,0 %; macro LCA$Q_T_BASE0 = 8576,0,0,1 %; literal LCA$S_T_BASE0 = 8; macro LCA$V_T_BASE0_BITS = 8576,10,22,0 %; macro LCA$Q_T_BASE1 = 8608,0,0,1 %; literal LCA$S_T_BASE1 = 8; macro LCA$V_T_BASE1_BITS = 8608,10,22,0 %; macro LCA$Q_TB_TAG0 = 16384,0,0,1 %; literal LCA$S_TB_TAG0 = 8; macro LCA$V_TB_TAG0_BITS = 16384,13,19,0 %; macro LCA$Q_TB_TAG1 = 16416,0,0,1 %; literal LCA$S_TB_TAG1 = 8; macro LCA$V_TB_TAG1_BITS = 16416,13,19,0 %; macro LCA$Q_TB_TAG2 = 16448,0,0,1 %; literal LCA$S_TB_TAG2 = 8; macro LCA$V_TB_TAG2_BITS = 16448,13,19,0 %; macro LCA$Q_TB_TAG3 = 16480,0,0,1 %; literal LCA$S_TB_TAG3 = 8; macro LCA$V_TB_TAG3_BITS = 16480,13,19,0 %; macro LCA$Q_TB_TAG4 = 16512,0,0,1 %; literal LCA$S_TB_TAG4 = 8; macro LCA$V_TB_TAG4_BITS = 16512,13,19,0 %; macro LCA$Q_TB_TAG5 = 16544,0,0,1 %; literal LCA$S_TB_TAG5 = 8; macro LCA$V_TB_TAG5_BITS = 16544,13,19,0 %; macro LCA$Q_TB_TAG6 = 16576,0,0,1 %; literal LCA$S_TB_TAG6 = 8; macro LCA$V_TB_TAG6_BITS = 16576,13,19,0 %; macro LCA$Q_TB_TAG7 = 16608,0,0,1 %; literal LCA$S_TB_TAG7 = 8; macro LCA$V_TB_TAG7_BITS = 16608,13,19,0 %; literal LCA$K_LENGTH = 24576; ! ! DS1287A register definitions ! literal LCA_DS1287A$S_LCA_DS1287A = 3624; macro LCA_DS1287A$L_PORT_INDEX = 3584,0,32,0 %; macro LCA_DS1287A$L_PORT_DATA = 3616,0,32,0 %; literal LCA_TAG_IDLE_CPU$K_ENABLE = 1; ! Enable Busy/Idle power management literal LCA_TAG_IDLE_CPU$K_DISABLE = 2; ! Disable Busy/Idle power management literal LCA_TAG_IDLE_CPU$K_SET_SPEED = 3; ! Set speed !*** MODULE $LCKCPUDEF *** ! ! LCKCPU - Lock manager per-CPU context block ! literal LCKCPU$K_LENGTH = 304; ! Length of LCKCPU literal LCKCPU$C_LENGTH = 304; ! Length of LCKCPU literal LCKCPU$C_CACHE_MIN = 128; ! low cache limit literal LCKCPU$C_CACHE_MAX = 256; ! high cache limit literal LCKCPU$C_LKB_DPC_MAX = 64; ! high LKB dpc limit literal LCKCPU$C_RSB_DPC_MAX = 32; ! high RSB dpc limit literal LCKCPU$C_LCKRQ_CACHE_MIN = 10; ! low LCKRQ cache limit literal LCKCPU$C_LCKRQ_CACHE_MAX = 25; ! high LCKRQ cache limit literal LCKCPU$C_FORCE_TRIM_MIN = 8; ! Trim to this if force trim set literal LCKCPU$C_FORCE_TRIM_MAX = 16; ! Set max to this if force trim set literal LCKCPU$C_RECOVERY_INCREMENT = 4; ! literal LCKCPU$S_LCKCPU = 304; macro LCKCPU$Q_LINK = 0,0,0,1 %; literal LCKCPU$S_LINK = 8; ! link to next LCKCPU block macro LCKCPU$W_MBO = 8,0,16,0 %; ! must-be-one field macro LCKCPU$B_TYPE = 10,0,8,0 %; ! structure type macro LCKCPU$B_SUBTYPE = 11,0,8,0 %; ! structure sub-type macro LCKCPU$L_PHY_ID = 12,0,32,1 %; ! CPU Id macro LCKCPU$Q_SIZE = 16,0,0,0 %; literal LCKCPU$S_SIZE = 8; ! structure size macro LCKCPU$Q_CPUDB = 24,0,0,1 %; literal LCKCPU$S_CPUDB = 8; ! pointer to per-CPU database macro LCKCPU$Q_RESERVED1 = 32,0,0,0 %; literal LCKCPU$S_RESERVED1 = 8; ! reserved macro LCKCPU$Q_RESERVED2 = 40,0,0,0 %; literal LCKCPU$S_RESERVED2 = 8; ! reserved macro LCKCPU$Q_RESERVED3 = 48,0,0,0 %; literal LCKCPU$S_RESERVED3 = 8; ! reserved macro LCKCPU$Q_RESERVED4 = 56,0,0,0 %; literal LCKCPU$S_RESERVED4 = 8; ! reserved macro LCKCPU$Q_LKB_ALLOC = 64,0,0,0 %; literal LCKCPU$S_LKB_ALLOC = 8; ! LKB allocations out of cache macro LCKCPU$Q_RSB_ALLOC = 72,0,0,0 %; literal LCKCPU$S_RSB_ALLOC = 8; ! RSB allocations out of cache macro LCKCPU$L_ENQNEW_LOC = 80,0,0,0 %; literal LCKCPU$S_ENQNEW_LOC = 8; ! new lock requests (local) macro LCKCPU$L_ENQNEW_IN = 88,0,0,0 %; literal LCKCPU$S_ENQNEW_IN = 8; ! new lock requests (incoming) macro LCKCPU$L_ENQNEW_OUT = 96,0,0,0 %; literal LCKCPU$S_ENQNEW_OUT = 8; ! new lock requests (outgoing) macro LCKCPU$L_ENQCVT_LOC = 104,0,0,0 %; literal LCKCPU$S_ENQCVT_LOC = 8; ! conversion requests (local) macro LCKCPU$L_ENQCVT_IN = 112,0,0,0 %; literal LCKCPU$S_ENQCVT_IN = 8; ! conversion requests (incoming) macro LCKCPU$L_ENQCVT_OUT = 120,0,0,0 %; literal LCKCPU$S_ENQCVT_OUT = 8; ! conversion requests (outgoing) macro LCKCPU$L_DEQ_LOC = 128,0,0,0 %; literal LCKCPU$S_DEQ_LOC = 8; ! dequeue requests (local) macro LCKCPU$L_DEQ_IN = 136,0,0,0 %; literal LCKCPU$S_DEQ_IN = 8; ! dequeue requests (incoming) macro LCKCPU$L_DEQ_OUT = 144,0,0,0 %; literal LCKCPU$S_DEQ_OUT = 8; ! dequeue requests (outgoing) macro LCKCPU$L_ENQWAIT = 152,0,0,0 %; literal LCKCPU$S_ENQWAIT = 8; ! lock requests that has to wait macro LCKCPU$L_ENQNOTQD = 160,0,0,0 %; literal LCKCPU$S_ENQNOTQD = 8; ! lock requests not queued macro LCKCPU$L_BLK_LOC = 168,0,0,0 %; literal LCKCPU$S_BLK_LOC = 8; ! blocking AST's (local) macro LCKCPU$L_BLK_IN = 176,0,0,0 %; literal LCKCPU$S_BLK_IN = 8; ! blocking AST's (incoming) macro LCKCPU$L_BLK_OUT = 184,0,0,0 %; literal LCKCPU$S_BLK_OUT = 8; ! blocking AST's (outgoing) macro LCKCPU$L_DIR_IN = 192,0,0,0 %; literal LCKCPU$S_DIR_IN = 8; ! directory functions (incoming) macro LCKCPU$L_DIR_OUT = 200,0,0,0 %; literal LCKCPU$S_DIR_OUT = 8; ! directory functions (outgoing) macro LCKCPU$Q_LKB_CACHE_LINK = 208,0,0,0 %; literal LCKCPU$S_LKB_CACHE_LINK = 8; macro LCKCPU$Q_RSB_CACHE_LINK = 216,0,0,0 %; literal LCKCPU$S_RSB_CACHE_LINK = 8; macro LCKCPU$L_LKB_CACHE_COUNT = 224,0,32,0 %; ! LKB cache macro LCKCPU$L_LKB_CACHE_MIN = 228,0,32,0 %; macro LCKCPU$L_LKB_CACHE_MAX = 232,0,32,0 %; macro LCKCPU$L_RSB_CACHE_COUNT = 236,0,32,0 %; ! RSB cache macro LCKCPU$L_RSB_CACHE_MIN = 240,0,32,0 %; macro LCKCPU$L_RSB_CACHE_MAX = 244,0,32,0 %; macro LCKCPU$Q_LKB_DPC_LINK = 248,0,0,0 %; literal LCKCPU$S_LKB_DPC_LINK = 8; macro LCKCPU$Q_RSB_DPC_LINK = 256,0,0,0 %; literal LCKCPU$S_RSB_DPC_LINK = 8; macro LCKCPU$L_LKB_DPC_COUNT = 264,0,32,0 %; ! LKB delete pending cache queue macro LCKCPU$L_LKB_DPC_MAX = 268,0,32,0 %; macro LCKCPU$L_RSB_DPC_COUNT = 272,0,32,0 %; ! RSB delete pending cache queue macro LCKCPU$L_RSB_DPC_MAX = 276,0,32,0 %; macro LCKCPU$L_LCKRQ_CACHE_LINK = 280,0,32,0 %; ! LCKRQ cache macro LCKCPU$L_LCKRQ_CACHE_COUNT = 284,0,32,0 %; macro LCKCPU$L_LCKRQ_CACHE_MIN = 288,0,32,0 %; macro LCKCPU$L_LCKRQ_CACHE_MAX = 292,0,32,0 %; macro LCKCPU$L_FORCE_TRIM = 296,0,32,0 %; ! LBS forces LKB/RSB trim to recover memory macro LCKCPU$L_FORCE_TRIM_COUNT = 300,0,32,0 %; !*** MODULE $LCKDLBDEF *** ! + ! LCKDLB - Lock manager deadlock context block ! - literal LCKDLB$K_LENGTH = 24; ! Length of LCKDLB literal LCKDLB$C_LENGTH = 24; ! Length of LCKDLB literal LCKDLB$S_LCKDLB = 24; macro LCKDLB$L_MAXERNG = 0,0,32,0 %; macro LCKDLB$L_MAXSRNG = 4,0,32,0 %; macro LCKDLB$L_PREV = 8,0,32,0 %; macro LCKDLB$L_SR4 = 12,0,32,0 %; macro LCKDLB$Q_SR6 = 16,0,0,0 %; literal LCKDLB$S_SR6 = 8; !*** MODULE $LCKMGRDEF *** ! + ! This macro defines the bit definitions for the global Lock Manager ! cell LCK$GL_FLAGS. ! ! - literal LCKMGR$M_CLUINT = %X'1'; literal LCKMGR$M_LCKINT = %X'2'; literal LCKMGR$M_CHK_BTR = %X'4'; literal LCKMGR$M_FRK_ENBL = %X'8'; literal LCKMGR$S_LCKMGRDEF = 1; ! Old size name - synonym literal LCKMGR$S_LCKMGR = 1; macro LCKMGR$V_CLUINT = 0,0,1,0 %; ! CLuster Init Complete macro LCKMGR$V_LCKINT = 0,1,1,0 %; ! Lock Manager Init Complete macro LCKMGR$V_CHK_BTR = 0,2,1,0 %; ! Check for better master macro LCKMGR$V_FRK_ENBL = 0,3,1,0 %; ! Fork interface enabled ! ! Define threshold values for dynamic remastering. ! literal lckmgr$K_RM8SEC_ACT_THRSH = 80; literal lckmgr$K_RM8SEC_SYS_THRSH = 80; ! Definitions for response codes for lock manager front end routines. ! ! literal FRTN$K_QUEIT = 0; ! request must be queued literal FRTN$K_GRNT1 = 1; ! request is compatible literal FRTN$K_GRNT2 = 2; ! rqst is compat, max-modes computed, grant waiters literal FRTN$K_GRNT3 = 3; ! rqst is compat, max-mode not computed, grant waiters literal FRTN$S_FRTN_CODES = 1; ! front end routine response codes macro FRTN$B_CODES = 0,0,8,0 %; ! ! Lock manager routine handling definitions ! literal LCK$K_CH_CVT_GRANTED = 1; literal LCK$K_CH_QUEUED_EXIT = 2; literal LCK$K_CH_CVTNOTQED = 3; literal LCK$K_CH_LOCAL_CVT = 4; literal LCK$K_CH_FORK_EXIT = 5; ! ! Lock manager routine handling definitions ! literal LCK$K_LH_LOCAL_LOCK = 1; literal LCK$K_LH_SYNC_EXIT = 2; literal LCK$K_LH_QUEUED_EXIT = 3; literal LCK$K_LH_NOT_QUEUED = 4; literal LCK$K_LH_FORK_EXIT = 5; ! ! Lock Manager Flags ! literal LCKMGR$M_HC = %X'1'; literal LCKMGR$M_PERCPU = %X'2'; literal LCKMGR$C_OFF = 0; literal LCKMGR$M_STATUS_BITS = %X'FF'; literal LCKMGR$M_MODE_BITS = %X'FF00'; literal LCKMGR$M_DISABLE_FAST_RM = %X'10000'; literal LCKMGR$M_RESERVED_UNUSED = %X'FE0000'; literal LCKMGR$M_CPUID_BITS = %X'FF000000'; literal LCKMGR$M_STATUS = %X'FF'; literal LCKMGR$M_MODE = %X'FF00'; literal LCKMGR$M_RESERVED = %X'FF0000'; literal LCKMGR$M_CPUID = %X'FF000000'; literal LCKMGR$S_LCKMGR_FLAGS = 4; macro LCKMGR$L_FLAGS = 0,0,32,0 %; macro LCKMGR$B_STATUS = 0,0,8,0 %; macro LCKMGR$V_HC = 0,0,1,0 %; macro LCKMGR$V_PERCPU = 0,1,1,0 %; macro LCKMGR$B_MODE = 1,0,8,0 %; macro LCKMGR$B_RESERVED = 2,0,8,0 %; macro LCKMGR$B_CPUID = 3,0,8,0 %; macro LCKMGR$V_DISABLE_FAST_RM = 0,16,1,0 %; macro LCKMGR$V_STATUS = 0,0,8,0 %; literal LCKMGR$S_STATUS = 8; macro LCKMGR$V_MODE = 0,8,8,0 %; literal LCKMGR$S_MODE = 8; macro LCKMGR$V_RESERVED = 0,16,8,0 %; literal LCKMGR$S_RESERVED = 8; macro LCKMGR$V_CPUID = 0,24,8,0 %; literal LCKMGR$S_CPUID = 8; !*** MODULE $LCKRQDEF *** ! ! LCKRQ - Lock manager request block ! literal LCKRQ$k_free = 0; literal LCKRQ$k_loaded = 1; literal LCKRQ$k_working = 2; literal LCKRQ$k_complete = 3; literal LCKRQ$k_delete = 4; literal LCKRQ$k_final_proc = -1; literal LCKRQ$k_rwscs = 1; literal LCKRQ$k_enq = -1; literal LCKRQ$k_cvt = 0; literal LCKRQ$k_deq = 1; literal LCKRQ$m_busy = %X'1'; literal LCKRQ$K_LENGTH = 320; ! Length of LCKRQ literal LCKRQ$C_LENGTH = 320; ! Length of LCKRQ literal LCKRQ$S_LCKRQ = 320; macro LCKRQ$L_flink = 0,0,32,1 %; macro LCKRQ$L_blink = 4,0,32,1 %; macro LCKRQ$w_size = 8,0,16,0 %; macro LCKRQ$b_type = 10,0,8,0 %; macro LCKRQ$b_flck = 11,0,8,0 %; ! FORK LOCK macro LCKRQ$l_fpc = 12,0,32,0 %; ! FORK PC macro LCKRQ$q_fr3 = 16,0,0,0 %; literal LCKRQ$s_fr3 = 8; ! FORK R3 macro LCKRQ$q_fr4 = 24,0,0,0 %; literal LCKRQ$s_fr4 = 8; ! FORK R4 macro LCKRQ$l_state = 32,0,32,0 %; macro LCKRQ$l_lksb_status = 40,0,32,0 %; ! lksb_status and lkid need macro LCKRQ$l_lkid = 44,0,32,0 %; ! to be adjacent fields macro LCKRQ$l_status = 48,0,32,0 %; macro LCKRQ$l_func = 52,0,32,0 %; macro LCKRQ$l_efn = 56,0,32,0 %; macro LCKRQ$l_lkmode = 60,0,32,0 %; macro LCKRQ$l_flags = 64,0,32,0 %; macro LCKRQ$l_parid = 68,0,32,0 %; macro LCKRQ$l_acmode = 72,0,32,0 %; macro LCKRQ$l_rng_flags = 76,0,32,0 %; macro LCKRQ$l_prev_mode = 80,0,32,0 %; macro LCKRQ$l_priority = 84,0,32,0 %; macro LCKRQ$l_pcb = 88,0,32,0 %; macro LCKRQ$l_rsnlen = 92,0,32,0 %; macro LCKRQ$T_resnam = 96,0,0,0 %; literal LCKRQ$s_resnam = 32; macro LCKRQ$Q_valblk = 128,0,0,0 %; literal LCKRQ$s_valblk = 16; macro LCKRQ$T_xvalblk = 128,0,0,0 %; literal LCKRQ$s_xvalblk = 64; macro LCKRQ$q_lksb = 192,0,0,0 %; literal LCKRQ$s_lksb = 8; macro LCKRQ$q_astadr = 200,0,0,0 %; literal LCKRQ$s_astadr = 8; macro LCKRQ$q_astprm = 208,0,0,0 %; literal LCKRQ$s_astprm = 8; macro LCKRQ$q_blkast = 216,0,0,0 %; literal LCKRQ$s_blkast = 8; macro LCKRQ$l_savd_tpid = 224,0,32,0 %; macro LCKRQ$l_grp_acmode = 228,0,32,0 %; macro LCKRQ$l_rsdmid = 232,0,32,0 %; macro LCKRQ$l_valblk_access = 236,0,32,0 %; macro LCKRQ$q_store_quad = 240,0,0,0 %; literal LCKRQ$s_store_quad = 8; macro LCKRQ$l_rqstsrng = 248,0,32,0 %; macro LCKRQ$l_rqsterng = 252,0,32,0 %; macro LCKRQ$l_fkb_flags = 256,0,32,0 %; macro LCKRQ$v_busy = 256,0,1,0 %; macro LCKRQ$l_ktb = 260,0,32,0 %; macro LCKRQ$q_seq = 264,0,0,0 %; literal LCKRQ$s_seq = 8; !*** MODULE $LCKSTRDEF *** ! ! LCKSTR - Lock manager structure context block ! literal LCKSTR$K_LENGTH = 384; ! Length of LCKSTR literal LCKSTR$C_LENGTH = 384; ! Length of LCKSTR literal LCKSTR$S_LCKSTR = 384; macro LCKSTR$Q_FILL1 = 0,0,0,1 %; literal LCKSTR$S_FILL1 = 8; ! reserved macro LCKSTR$W_MBO = 8,0,16,0 %; ! must-be-one field macro LCKSTR$B_TYPE = 10,0,8,0 %; ! structure type macro LCKSTR$B_SUBTYPE = 11,0,8,0 %; ! structure sub-type macro LCKSTR$L_FILL2 = 12,0,32,1 %; ! reserved macro LCKSTR$Q_SIZE = 16,0,0,0 %; literal LCKSTR$S_SIZE = 8; ! structure size macro LCKSTR$Q_queuelock = 24,0,0,1 %; literal LCKSTR$s_queuelock = 8; ! pointer to queue lock macro LCKSTR$q_lckrq_table = 32,0,0,0 %; literal LCKSTR$s_lckrq_table = 8; ! pointer to LCKRQ address table macro LCKSTR$q_lckrq_curidx = 40,0,0,0 %; literal LCKSTR$s_lckrq_curidx = 8; ! current index into LCKRQ address table macro LCKSTR$l_lckmgr_cpuid = 48,0,32,0 %; ! CPU id, where lckmgr_server process runs macro LCKSTR$l_lckmgr_pcb = 52,0,32,0 %; ! PCB address of lckmgr_server process macro LCKSTR$l_lckmgr_pid = 56,0,32,0 %; ! PID of lckmgr_server process macro LCKSTR$l_flag = 60,0,32,0 %; ! flag macro LCKSTR$q_spin_count = 64,0,0,0 %; literal LCKSTR$s_spin_count = 8; ! number of times lckmgr was in spinloop macro LCKSTR$q_spin_time_acc = 72,0,0,0 %; literal LCKSTR$s_spin_time_acc = 8; ! accumulated spin time in cycles macro LCKSTR$q_req_count = 80,0,0,0 %; literal LCKSTR$s_req_count = 8; ! number of lock requests handled macro LCKSTR$q_req_time_acc = 88,0,0,0 %; literal LCKSTR$s_req_time_acc = 8; ! accumulated time to work requests macro LCKSTR$l_overflow_queue = 96,0,32,0 %; ! overflow queue macro LCKSTR$l_overflow_shadow = 100,0,32,0 %; ! overflow shadow queue macro LCKSTR$l_sanity_counter = 104,0,32,0 %; ! sanity check counter macro LCKSTR$q_seq = 112,0,0,0 %; literal LCKSTR$s_seq = 8; ! sequence number macro LCKSTR$q_reserved1 = 120,0,0,0 %; literal LCKSTR$s_reserved1 = 8; macro LCKSTR$q_reserved2 = 128,0,0,0 %; literal LCKSTR$s_reserved2 = 8; macro LCKSTR$q_reserved3 = 136,0,0,0 %; literal LCKSTR$s_reserved3 = 8; macro LCKSTR$q_reserved4 = 144,0,0,0 %; literal LCKSTR$s_reserved4 = 8; macro LCKSTR$q_lckrq_nxtidx = 256,0,0,0 %; literal LCKSTR$s_lckrq_nxtidx = 8; ! next index into LCKRQ address table macro LCKSTR$l_fill3 = 256,0,32,0 %; macro LCKSTR$l_lckrq_shadidx = 260,0,32,0 %; ! shadow of current idx into LCKRQ table !*** MODULE $LCSDEF *** ! ! Structure(s) for RMS conversions between a local character set ! (e.g., Super DEC Kanji) and Unicode for filenames ! ! This structure, when inserted into the known extension queue, ! registers an RMS extension with the base RMS. It should contain ! entry points for a set of conversion functions for the selected ! local character set. ! literal LCS$C_BLN = 72; literal LCS$K_BLN = 72; literal LCS$S_LCS = 72; macro LCS$L_FLINK = 0,0,32,1 %; ! links to next and previous macro LCS$L_BLINK = 4,0,32,1 %; ! registered LCS structures. macro LCS$W_SIZE = 8,0,16,0 %; ! allocated size of structure macro LCS$W_NAMLEN = 10,0,16,0 %; ! length of extension name macro LCS$T_NAME = 12,0,0,0 %; literal LCS$S_NAME = 32; ! space for extension name macro LCS$A_CALC_VTF7_TO_LOCAL = 44,0,32,0 %; ! Calculate length of converted string (in local code-set). macro LCS$A_CONV_VTF7_TO_LOCAL = 48,0,32,0 %; ! Convert string from VTF-7 to local code-set. macro LCS$A_CALC_LOCAL_TO_VTF7 = 52,0,32,0 %; ! Calculate length of converted string (in VTF-7). macro LCS$A_CONV_LOCAL_TO_VTF7 = 56,0,32,0 %; ! Convert string from local code-set to VTF-7. macro LCS$A_CONV_FILESYS_TO_LOCAL = 60,0,32,0 %; ! Convert string from File System format to local code-set. macro LCS$A_BUILD_LOCAL_PQB = 64,0,32,0 %; ! Called by SYS$CREPRC to copy a LCS from a parent process to PQB. macro LCS$A_RESTORE_LOCAL_PQB = 68,0,32,0 %; ! Called by EXE$PROCSTRT to copy a LCS from PQB to a subprocess. !*** MODULE $LDBDEF *** ! ! $LOAD_DRIVER Data Block ! literal LDB$M_DDB = %X'1'; literal LDB$M_CRB = %X'2'; literal LDB$M_IDB = %X'4'; literal LDB$M_UCB = %X'8'; literal LDB$M_LINKED_UCB = %X'10'; literal LDB$M_NOADAP = %X'20'; literal LDB$M_CRBBLT = %X'40'; literal LDB$M_SCBVEC = %X'80'; literal LDB$M_REMOTE = %X'100'; literal LDB$M_SCS = %X'200'; literal LDB$M_SCSI_PORT = %X'400'; literal LDB$M_ADD_UNIT = %X'800'; literal LDB$M_SUD = %X'1000'; literal LDB$K_MAXVEC = 32; ! maximum # of interrupt vectors per device literal LDB$K_LENGTH = 532; literal LDB$C_LENGTH = 532; literal LDB$S_LDBDEF = 532; ! Old size name - synonym literal LDB$S_LDB = 532; macro LDB$PS_FLINK = 0,0,32,1 %; ! Link to next LDB macro LDB$PS_BLINK = 4,0,32,1 %; ! Link to previous LDB macro LDB$W_SIZE = 8,0,16,0 %; ! size of this structure macro LDB$B_TYPE = 10,0,8,0 %; ! structure type macro LDB$B_SUBTYPE = 11,0,8,0 %; ! structure subtype ! Status information macro LDB$L_FLAGS = 12,0,32,0 %; ! control and status flags macro LDB$V_DDB = 12,0,1,0 %; ! built a DDB macro LDB$V_CRB = 12,1,1,0 %; ! built a CRB macro LDB$V_IDB = 12,2,1,0 %; ! built an IDB macro LDB$V_UCB = 12,3,1,0 %; ! built a UCB macro LDB$V_LINKED_UCB = 12,4,1,0 %; ! UCB has been linked into DDB chain macro LDB$V_NOADAP = 12,5,1,0 %; ! connect to NULL adapter macro LDB$V_CRBBLT = 12,6,1,0 %; ! SYSLOA_CRB item was specified macro LDB$V_SCBVEC = 12,7,1,0 %; ! VECTOR is offset into SCB macro LDB$V_REMOTE = 12,8,1,0 %; ! device is on a remote system macro LDB$V_SCS = 12,9,1,0 %; ! associated driver requires SCS macro LDB$V_SCSI_PORT = 12,10,1,0 %; ! device is a SCSI port macro LDB$V_ADD_UNIT = 12,11,1,0 %; ! may be an "add unit" request macro LDB$V_SUD = 12,12,1,0 %; ! built a SUD ! Input items macro LDB$L_UNIT = 16,0,32,0 %; ! unit number to connect macro LDB$Q_CSR = 20,0,0,0 %; literal LDB$S_CSR = 8; ! CSR "magic number" macro LDB$Q_SYSID = 28,0,0,0 %; literal LDB$S_SYSID = 8; ! SCS SYSID of controller macro LDB$L_VECTOR = 36,0,0,0 %; literal LDB$S_VECTOR = 128; ! byte offset into SCB/vector table macro LDB$L_NUMVEC = 164,0,32,0 %; ! number of interrupt vectors macro LDB$L_MAXUNITS = 168,0,32,0 %; ! maximum number of units allowed ! Input/Output items macro LDB$Q_DLVR_DATA = 172,0,0,0 %; literal LDB$S_DLVR_DATA = 8; ! working copy of deliver data macro LDB$PS_USER_DLVR = 180,0,32,1 %; ! address of caller's deliver data macro LDB$L_NUMUNITS = 184,0,32,1 %; ! number of units to connect now ! Output items macro LDB$PS_ADP = 188,0,32,1 %; ! address of ADaPter control block macro LDB$PS_DPT = 192,0,32,1 %; ! address of Driver Prologue Table macro LDB$PS_SB = 196,0,32,1 %; ! address of System Block macro LDB$PS_DDB = 200,0,32,1 %; ! address of Device Data Block macro LDB$PS_CRB = 204,0,32,1 %; ! address of Channel Request Block macro LDB$PS_IDB = 208,0,32,1 %; ! address of Interrupt Dispatch Block macro LDB$PS_UCB = 212,0,32,1 %; ! address of Unit Control Block macro LDB$PS_FORK = 216,0,32,1 %; ! address of associated fork block ! Working data macro LDB$PS_LASTDDB = 220,0,32,1 %; ! DDB address returned by IOC$SEARCHALL macro LDB$IL_DPT_MAXUNITS = 224,0,32,1 %; ! DPT's view of MAXUNITS macro LDB$T_DPT_NAME = 228,0,0,0 %; literal LDB$S_DPT_NAME = 16; ! name stored in ASCIC format macro LDB$IB_DPT_NAMELEN = 228,0,8,0 %; ! character count in DPT_NAME macro LDB$T_DPT_NAMESTR = 229,0,0,0 %; literal LDB$S_DPT_NAMESTR = 15; ! actual string macro LDB$IL_DEVLEN = 244,0,32,1 %; ! length of device name in DEVNAM macro LDB$PS_SEARCHNAME = 248,0,32,1 %; ! name used for IOC$SEARCHALL macro LDB$IL_DDB_NAMELEN = 252,0,32,1 %; ! length of DEVNAM copied to DDB macro LDB$PS_DDB_NAME = 256,0,32,1 %; ! beginning of name to copy to DDB macro LDB$T_DEVNAM = 260,0,0,0 %; literal LDB$S_DEVNAM = 16; ! name of device being connected macro LDB$T_DRVNAM = 276,0,0,0 %; literal LDB$S_DRVNAM = 256; ! name stored in ASCIC format macro LDB$IB_DRVNAMLEN = 276,0,8,0 %; ! character count in DRVNAM macro LDB$T_DRVNAMSTR = 277,0,0,0 %; literal LDB$S_DRVNAMSTR = 255; ! actual string !*** MODULE $LDRDEF *** literal LDR$M_PAG = %X'1'; literal LDR$M_UNL = %X'2'; literal LDR$M_OVR = %X'4'; literal LDR$M_USER_BUF = %X'8'; literal LDR$M_NO_SLICE = %X'10'; literal LDR$S_LDR_DYN = 4; macro LDR$V_PAG = 0,0,1,0 %; ! If set, paging is disabled macro LDR$V_UNL = 0,1,1,0 %; ! Image is unloadable macro LDR$V_OVR = 0,2,1,0 %; ! If set, do not overlay image macro LDR$V_USER_BUF = 0,3,1,0 %; ! Optional user buffer ! is specified on input macro LDR$V_NO_SLICE = 0,4,1,0 %; ! Image is not to be sliced ! during load. !*** MODULE $LDRHPDEF *** literal LDRHP$K_CODE = 0; ! execlet code UR literal LDRHP$K_DATA = 1; ! execlet data URKW literal LDRHP$K_EXEC_DATA = 2; ! exec data area ERKW literal LDRHP$K_RES_CODE = 3; ! resident code UR literal LDRHP$K_RES_DATA = 4; ! resident data URKW literal LDRHP$K_EXEC_DATA_S2 = 5; ! s2 space exec data area ERKW literal LDRHP$K_CODE_S2 = 6; ! S2 space execlet code UR literal LDRHP$K_RES_CODE_S2 = 7; ! S2 space resident code UR literal LDRHP$K_NUM_TYPES = 8; ! number of page types literal LDRHP$M_ALLOC_FAIL = %X'1'; literal LDRHP$M_RELEASED = %X'2'; literal LDRHP$C_LENGTH = 128; literal LDRHP$K_LENGTH = 128; literal LDRHP$S_LDRHPDEF = 128; ! Old size name - synonym literal LDRHP$S_LDRHP = 128; macro LDRHP$Q_TYPE = 0,0,0,0 %; literal LDRHP$S_TYPE = 8; ! type, code or data page macro LDRHP$L_TYPE_L = 0,0,32,0 %; macro LDRHP$L_TYPE_H = 4,0,32,0 %; macro LDRHP$Q_SIZE = 8,0,0,0 %; literal LDRHP$S_SIZE = 8; ! size of huge page macro LDRHP$L_SIZE_L = 8,0,32,0 %; macro LDRHP$L_SIZE_H = 12,0,32,0 %; macro LDRHP$Q_VA = 16,0,0,1 %; literal LDRHP$S_VA = 8; ! Base VA of huge page macro LDRHP$L_VA_L = 16,0,32,1 %; macro LDRHP$L_VA_H = 20,0,32,1 %; macro LDRHP$Q_PA = 24,0,0,1 %; literal LDRHP$S_PA = 8; ! Base PA of huge page macro LDRHP$L_PA_L = 24,0,32,1 %; macro LDRHP$L_PA_H = 28,0,32,1 %; macro LDRHP$Q_SLICE_SIZE = 32,0,0,0 %; literal LDRHP$S_SLICE_SIZE = 8; ! size of allocation quantity macro LDRHP$L_SLICE_SIZE_L = 32,0,32,0 %; macro LDRHP$L_SLICE_SIZE_H = 36,0,32,0 %; macro LDRHP$Q_NEXT_SLICE = 40,0,0,0 %; literal LDRHP$S_NEXT_SLICE = 8; ! next available slice in page macro LDRHP$L_NEXT_SLICE_L = 40,0,32,0 %; macro LDRHP$L_NEXT_SLICE_H = 44,0,32,0 %; macro LDRHP$Q_FREE_SLICES = 48,0,0,0 %; literal LDRHP$S_FREE_SLICES = 8; ! free slices in page macro LDRHP$L_FREE_SLICES_L = 48,0,32,0 %; macro LDRHP$L_FREE_SLICES_H = 52,0,32,0 %; macro LDRHP$Q_USED_SLICES = 56,0,0,0 %; literal LDRHP$S_USED_SLICES = 8; ! used slices in page macro LDRHP$L_USED_SLICES_L = 56,0,32,0 %; macro LDRHP$L_USED_SLICES_H = 60,0,32,0 %; macro LDRHP$Q_STARTUP_PAGES = 64,0,0,0 %; literal LDRHP$S_STARTUP_PAGES = 8; ! pages in use when LDR$WRAPUP runs macro LDRHP$L_STARTUP_PAGES_L = 64,0,32,0 %; macro LDRHP$L_STARTUP_PAGES_H = 68,0,32,0 %; macro LDRHP$Q_BITMAP_SIZE = 72,0,0,0 %; literal LDRHP$S_BITMAP_SIZE = 8; ! size of huge page bitmap macro LDRHP$L_BITMAP_SIZE_L = 72,0,32,0 %; macro LDRHP$L_BITMAP_SIZE_H = 76,0,32,0 %; macro LDRHP$Q_BITMAP_VA = 80,0,0,1 %; literal LDRHP$S_BITMAP_VA = 8; ! base VA of huge page bitmap macro LDRHP$L_BITMAP_VA_L = 80,0,32,1 %; macro LDRHP$L_BITMAP_VA_H = 84,0,32,1 %; macro LDRHP$Q_FLAGS = 88,0,0,0 %; literal LDRHP$S_FLAGS = 8; ! flags macro LDRHP$R_FLAGS_BITS = 88,0,8,0 %; macro LDRHP$V_ALLOC_FAIL = 88,0,1,0 %; ! allocation attempt failed macro LDRHP$V_RELEASED = 88,1,1,0 %; ! unused pfns have been released macro LDRHP$L_FLAGS_L = 88,0,32,0 %; macro LDRHP$L_FLAGS_H = 92,0,32,0 %; macro LDRHP$Q_FAILPAGE_CNT = 96,0,0,0 %; literal LDRHP$S_FAILPAGE_CNT = 8; ! Count of pages in failed allocs macro LDRHP$L_FAILPAGE_CNT_L = 96,0,32,0 %; macro LDRHP$L_FAILPAGE_CNT_H = 100,0,32,0 %; macro LDRHP$Q_FAILPAGE_MAX = 104,0,0,0 %; literal LDRHP$S_FAILPAGE_MAX = 8; ! Size of biggest failed alloc macro LDRHP$L_FAILPAGE_MAX_L = 104,0,32,0 %; macro LDRHP$L_FAILPAGE_MAX_H = 108,0,32,0 %; macro LDRHP$Q_FAIL_PRE_CNT = 112,0,0,0 %; literal LDRHP$S_FAIL_PRE_CNT = 8; ! Count of failed allocs macro LDRHP$L_FAIL_PRE_CNT_L = 112,0,32,0 %; macro LDRHP$L_FAIL_PRE_CNT_H = 116,0,32,0 %; macro LDRHP$Q_FAIL_POST_CNT = 120,0,0,0 %; literal LDRHP$S_FAIL_POST_CNT = 8; ! Count of failed allocs macro LDRHP$L_FAIL_POST_CNT_L = 120,0,32,0 %; macro LDRHP$L_FAIL_POST_CNT_H = 124,0,32,0 %; !*** MODULE $LDRIMGDEF *** literal LDRISD$S_LDRISD = 72; macro LDRISD$I_VBN = 0,0,32,1 %; ! image section VBN macro LDRISD$I_TYPE = 4,0,32,0 %; ! ELF segment type macro LDRISD$W_SIZE = 8,0,16,1 %; ! size of this structure macro LDRISD$W_STX = 10,0,16,1 %; ! section table index macro LDRISD$I_FLAGS = 12,0,32,0 %; ! ELF segment flags macro LDRISD$P_BASE = 16,0,0,1 %; literal LDRISD$S_BASE = 8; ! process virtual image section base (relocated) macro LDRISD$I_LEN = 24,0,0,1 %; literal LDRISD$S_LEN = 8; ! image section length in memory (filled from filesz with demand zero) macro LDRISD$I_LINK_BASE = 32,0,0,1 %; literal LDRISD$S_LINK_BASE = 8; ! image section offset (linker base) macro LDRISD$I_LINK_END = 40,0,0,1 %; literal LDRISD$S_LINK_END = 8; ! image section end (unrelocated, rounded to 'bigpage') ! to avoid privileged applications depending on teh size of LDRISD, the size is recorded) macro LDRISD$I_FILESZ = 48,0,0,1 %; literal LDRISD$S_FILESZ = 8; ! image section length in file macro LDRISD$Q_RESERVED = 56,0,0,1 %; literal LDRISD$S_RESERVED = 16; ! reserve some space for debug/patch ! In support of Shared Address Data (SAD), an LDRRQI is created for each needed image. ! the LDRRQI contains dynamic table entries for needed images, plus the register ! image signature to verify that the proper image is activated. (if not, SAD cannot ! be used for that image activation) literal LDRRQI$S_LDRRQI = 80; macro LDRRQI$Q_NEEDED = 0,0,0,1 %; literal LDRRQI$S_NEEDED = 8; ! strtab index for needed image name macro LDRRQI$Q_NEEDED_IDENT = 8,0,0,1 %; literal LDRRQI$S_NEEDED_IDENT = 8; ! image ident (required IDENT of needed image) macro LDRRQI$Q_FIXUP_RELA_CNT = 16,0,0,1 %; literal LDRRQI$S_FIXUP_RELA_CNT = 8; ! count of fixups macro LDRRQI$Q_FIXUP_RELA_OFF = 24,0,0,1 %; literal LDRRQI$S_FIXUP_RELA_OFF = 8; ! dynseg offset to firs fixup macro LDRRQI$B_RISIG = 32,0,0,1 %; literal LDRRQI$S_RISIG = 32; ! image signiture macro LDRRQI$Q_RESERVED = 64,0,0,1 %; literal LDRRQI$S_RESERVED = 16; ! reserve some space for debug/patch literal LDRIMG$M_NOT_XQP = %X'1'; literal LDRIMG$M_DELAY_INIT = %X'2'; literal LDRIMG$M_NO_PFN_DB = %X'4'; literal LDRIMG$M_NOOVERLAY = %X'8'; literal LDRIMG$M_CAN_UNL = %X'10'; literal LDRIMG$M_UNL_PEN = %X'20'; literal LDRIMG$M_SYNC = %X'40'; literal LDRIMG$M_VALID = %X'80'; literal LDRIMG$M_GSTVA_VALID = %X'100'; literal LDRIMG$M_PAGED_RELOC = %X'200'; literal LDRIMG$M_NONPAGED_RELOC = %X'400'; literal LDRIMG$M_PAGED_FIXUPS = %X'800'; literal LDRIMG$M_NONPAGED_FIXUPS = %X'1000'; literal LDRIMG$M_SECOND_PASS_FIXUP = %X'2000'; literal LDRIMG$M_NO_SLICE = %X'4000'; literal LDRIMG$M_DYN_LOAD = %X'8000'; literal LDRIMG$M_NPAGED_LOAD = %X'10000'; literal LDRIMG$M_MSG_LOADED = %X'20000'; literal LDRIMG$M_INITIALIZED = %X'40000'; literal LDRIMG$M_INIT_GONE = %X'80000'; literal LDRIMG$C_LENGTH = 216; literal LDRIMG$K_LENGTH = 216; literal LDRIMG$S_LDRIMGDEF = 216; ! Old size name - synonym literal LDRIMG$S_LDRIMG = 216; macro LDRIMG$L_FLINK = 0,0,32,1 %; ! forward link macro LDRIMG$L_BLINK = 4,0,32,1 %; ! backward link macro LDRIMG$W_SIZE = 8,0,16,0 %; ! structure size macro LDRIMG$B_TYPE = 10,0,8,0 %; ! DYN$C_LOADCODE macro LDRIMG$B_SUBTYPE = 11,0,8,0 %; ! DYN$C_LDRIMG macro LDRIMG$R_FLAGS_OVERLAY = 12,0,32,0 %; macro LDRIMG$L_FLAGS = 12,0,32,0 %; ! status flags macro LDRIMG$R_FLAGS_BITS = 12,0,24,0 %; macro LDRIMG$V_NOT_XQP = 12,0,1,0 %; ! not opened by XQP macro LDRIMG$V_DELAY_INIT = 12,1,1,0 %; ! needs delayed initialization macro LDRIMG$V_NO_PFN_DB = 12,2,1,0 %; ! no PFN data base when loaded macro LDRIMG$V_NOOVERLAY = 12,3,1,0 %; ! not overlaid by bugcheck macro LDRIMG$V_CAN_UNL = 12,4,1,0 %; ! unloadable exec image macro LDRIMG$V_UNL_PEN = 12,5,1,0 %; ! exec image unload is pending macro LDRIMG$V_SYNC = 12,6,1,0 %; ! synchronize access to this block macro LDRIMG$V_VALID = 12,7,1,0 %; ! contents of this block are valid macro LDRIMG$V_GSTVA_VALID = 12,8,1,0 %; ! GSTVA contains a valid address macro LDRIMG$V_PAGED_RELOC = 12,9,1,0 %; ! paged relocations done macro LDRIMG$V_NONPAGED_RELOC = 12,10,1,0 %; ! nonpaged relocations done macro LDRIMG$V_PAGED_FIXUPS = 12,11,1,0 %; ! paged fix-ups done macro LDRIMG$V_NONPAGED_FIXUPS = 12,12,1,0 %; ! Non-paged fix-ups done macro LDRIMG$V_SECOND_PASS_FIXUP = 12,13,1,0 %; ! 2nd pass fixup required macro LDRIMG$V_NO_SLICE = 12,14,1,0 %; ! execlet not sliced macro LDRIMG$V_DYN_LOAD = 12,15,1,0 %; ! loaded by dynamic loader macro LDRIMG$V_NPAGED_LOAD = 12,16,1,0 %; ! paged code loaded nonpaged macro LDRIMG$V_MSG_LOADED = 12,17,1,0 %; ! message section found/loaded macro LDRIMG$V_INITIALIZED = 12,18,1,0 %; ! initialization complete macro LDRIMG$V_INIT_GONE = 12,19,1,0 %; ! when set, init sections have ! been deallocated - I64 only macro LDRIMG$Q_LINKTIME = 16,0,0,0 %; literal LDRIMG$S_LINKTIME = 8; ! link time macro LDRIMG$PQ_GP = 24,0,0,1 %; literal LDRIMG$S_GP = 8; ! gp value for this image macro LDRIMG$L_INIT_RTN = 32,0,0,1 %; literal LDRIMG$S_INIT_RTN = 8; ! delayed initialization routine macro LDRIMG$L_VERSION = 40,0,32,1 %; ! image version macro LDRIMG$L_WCB = 44,0,32,1 %; ! WCB pointer macro LDRIMG$L_PID = 48,0,32,1 %; ! pid of proc attempting load macro LDRIMG$L_CHAN = 52,0,32,1 %; ! chan number macro LDRIMG$L_BASIMGVEC = 56,0,32,1 %; ! VA of list of base image vectors macro LDRIMG$L_NUM_BASVEC = 60,0,32,1 %; ! number of base image contributions macro LDRIMG$L_SEQ = 64,0,32,1 %; ! sequence no. macro LDRIMG$L_UNLVEC = 68,0,32,1 %; ! VA of unload routine vector macro LDRIMG$L_REFCNT = 72,0,32,1 %; ! number of references pending macro LDRIMG$L_SYMVVA = 76,0,32,1 %; ! Address of symbol vector macro LDRIMG$L_SYMV_COUNT = 80,0,32,0 %; ! count of symbol vector entries macro LDRIMG$L_ANOMOLY = 84,0,32,0 %; ! count of unusuual conditions detected ! while loading this image macro LDRIMG$L_SSVEC = 88,0,32,1 %; ! Address of system service vectors macro LDRIMG$L_FST = 92,0,32,1 %; ! Address of FST for boot time IO macro LDRIMG$L_VEC_SEGMENT = 96,0,32,1 %; ! Address of segment(isect) with VEC attribute macro LDRIMG$L_SEGCOUNT = 100,0,32,0 %; ! count of segments macro LDRIMG$L_SEGMENTS = 104,0,32,1 %; ! pointer to ISD array macro LDRIMG$L_DYN_SEG = 108,0,32,1 %; ! pointer to the dynamic segment ISD macro LDRIMG$L_IMGNAMLEN = 112,0,32,0 %; ! count for image name macro LDRIMG$PS_IMGNAM = 116,0,32,1 %; ! image name string macro LDRIMG$p_IMCB = 120,0,32,1 %; ! pointer to IMCB (for process iamges) macro LDRIMG$L_NEEDED_COUNT = 124,0,32,0 %; ! count of needed images macro LDRIMG$p_TFRADR = 128,0,0,1 %; literal LDRIMG$S_TFRADR = 8; ! pointer to ELF transfer adress struct. macro LDRIMG$L_LINK_FLAGS = 136,0,32,0 %; ! linker flags (DT_VMS_LNKFLAGS) macro LDRIMG$PS_NEEDED = 140,0,32,1 %; ! pointer to array of pointers to needed images macro LDRIMG$PS_NEEDED_SPF = 144,0,32,1 %; ! array of pointers to 2nd pass fixups macro LDRIMG$L_LDRIMG_SIZE = 148,0,32,0 %; ! length of the LDRIMG structure. macro LDRIMG$L_LDRISD_SIZE = 152,0,32,0 %; ! length of each LDRISD structure. macro LDRIMG$L_XLATED = 156,0,32,0 %; ! translated image type. macro LDRIMG$L_PUBLIC_IMAGE_FLINK = 160,0,32,1 %; ! queue element for "public' execlets macro LDRIMG$L_PUBLIC_IMAGE_BLINK = 164,0,32,1 %; macro LDRIMG$L_PUBLIC_IMAGE_INDEX = 168,0,32,0 %; ! macro LDRIMG$PS_LDRRQI = 172,0,32,1 %; ! pointer to array of LDRRQI macro LDRIMG$PS_STRTAB = 176,0,32,1 %; ! pointer to string table macro LDRIMG$L_RESERVED_1 = 180,0,32,1 %; ! reserved space for debug/patch/align macro LDRIMG$Q_RESERVED_2 = 184,0,0,1 %; literal LDRIMG$S_RESERVED_2 = 32; ! reserve some space for debug/patch !*** MODULE $LIRDEF *** ! + ! $LIRDEF - LOADABLE IMAGE RECORD DEFINITION ! ! A LOADABLE IMAGE RECORD DEFINES A ALTERNATE EXEC IMAGE THAT CAN ! BE LOADED BY INIT OR SYSINIT INTO THE SYSTEM. ! - literal LIR$K_ID = 257; ! LIR ID plus version literal LIR$K_INIT = 0; ! INIT literal LIR$K_SYSINIT = 1; ! SYSINIT literal LIR$K_WARNING = 0; ! WARNING literal LIR$K_SUCCESS = 1; ! SUCCESS literal LIR$K_ERROR = 2; ! ERROR literal LIR$K_INFORMATION = 3; ! INFORMATION literal LIR$K_FIXED = 8; ! Length of fixed portion literal LIR$C_FIXED = 8; ! Length of fixed portion literal LIR$K_LENGTH = 256; ! Length of LIR literal LIR$C_LENGTH = 256; ! Length of LIR literal LIR$S_LIRDEF = 8; ! Old size name - synonym literal LIR$S_LIR = 8; macro LIR$W_ID = 0,0,16,0 %; ! LIR ID field macro LIR$W_PHASE = 2,0,16,0 %; ! LIR phase indicator ! LIR phase values macro LIR$W_SEVERITY = 4,0,16,0 %; ! LIR severity indicator ! LIR severity values macro LIR$B_ERR_LEN = 6,0,8,0 %; ! Error message length macro LIR$B_ERR_OFF = 7,0,8,0 %; ! Error message offset macro LIR$T_IMAGE_NAME = 8,0,0,0 %; ! Start of image name counted string !*** MODULE $LKBDEF *** ! + ! ! LKB - Lock Block ! ! Lock blocks represent lock requests (one block for each request). ! Each lock block has a corresponding entry in the lock id table which ! points to it. It is also linked onto one of the three state queues ! in a resource block (RSB). ! ! - literal LKB$M_FLAGS_VALID = %X'4'; literal LKB$M_PKAST = %X'10'; literal LKB$M_NODELETE = %X'20'; literal LKB$M_QUOTA = %X'40'; literal LKB$M_KAST = %X'80'; literal LKB$K_ACB64LEN = 64; ! Length of ACB64 portion of LKB literal LKB$M_DCPLAST = %X'1'; literal LKB$M_ASYNC = %X'4'; literal LKB$M_BLKASTQED = %X'8'; literal LKB$M_MSTCPY = %X'10'; literal LKB$M_NOQUOTA = %X'20'; literal LKB$M_TIMOUTQ = %X'40'; literal LKB$M_WASSYSOWN = %X'80'; literal LKB$M_CVTTOSYS = %X'100'; literal LKB$M_PROTECT = %X'200'; literal LKB$M_RESEND = %X'400'; literal LKB$M_RM_RBRQD = %X'800'; literal LKB$M_FLOCK = %X'1000'; literal LKB$M_IP = %X'2000'; literal LKB$M_CACHED = %X'4000'; literal LKB$M_RNGBLK = %X'8000'; literal LKB$M_BRL = %X'10000'; literal LKB$M_NEWSUBRNG = %X'20000'; literal LKB$M_CVTSUBRNG = %X'40000'; literal LKB$M_RNGCHG = %X'80000'; literal LKB$M_2PC_IP = %X'100000'; literal LKB$M_2PC_PEND = %X'200000'; literal LKB$M_BLKASTFLG = %X'400000'; literal LKB$M_GRSUBRNG = %X'800000'; literal LKB$M_PCACHED = %X'1000000'; literal LKB$M_VALBLKRD = %X'2000000'; literal LKB$M_VALBLKWRT = %X'4000000'; literal LKB$M_DPC = %X'8000000'; literal LKB$M_PERCPU = %X'10000000'; literal LKB$M_INDEX = %X'FFFFFF'; literal LKB$K_GRANTED = 1; ! Granted literal LKB$K_CONVERT = 0; ! Conversion literal LKB$K_WAITING = -1; ! Waiting literal LKB$K_RETRY = -2; ! Retry request literal LKB$K_SCSWAIT = -3; ! SCS wait literal LKB$K_RSPNOTQED = -4; ! Response not queued literal LKB$K_RSPQUEUED = -5; ! Response queued literal LKB$K_RSPGRANTD = -6; ! Response granted literal LKB$K_RSPDOLOCL = -7; ! Response do locally literal LKB$K_RSPRESEND = -8; ! Response resend literal LKB$K_RSPWAIT = -9; ! Response wait literal LKB$K_RSP2PCRDY = -10; ! Response ready literal LKB$K_RSPFATAL = -11; ! Fatal Message Response literal LKB$M_DBLKAST = %X'2'; literal LKB$K_LENGTH = 256; ! Length of LKB literal LKB$C_LENGTH = 256; ! Length of LKB literal LKB$S_LKBDEF = 256; ! Old size name - synonym literal LKB$S_LKB = 256; macro LKB$L_ASTQFL = 0,0,32,1 %; ! AST Queue forward link macro LKB$L_ASTQBL = 4,0,32,1 %; ! AST Queue backward link macro LKB$W_SIZE = 8,0,16,0 %; ! Size of LKB in bytes macro LKB$B_TYPE = 10,0,8,0 %; ! Structure type macro LKB$B_RMOD = 11,0,8,0 %; ! Access mode of request macro LKB$V_MODE = 11,0,2,0 %; literal LKB$S_MODE = 2; ! Mode subfield macro LKB$V_FLAGS_VALID = 11,2,1,0 %; ! ACB flags valid indicator macro LKB$V_PKAST = 11,4,1,0 %; ! Piggyback Special Kernel AST macro LKB$V_NODELETE = 11,5,1,0 %; ! Don't delete ACB on delivery macro LKB$V_QUOTA = 11,6,1,0 %; ! Account for quota macro LKB$V_KAST = 11,7,1,0 %; ! Special Kernel AST macro LKB$L_PID = 12,0,32,0 %; ! Process ID of requesting process macro LKB$L_ACB64X = 16,0,32,0 %; ! Offset to ACB64X structure macro LKB$L_ACB_FLAGS = 24,0,32,0 %; ! AST control flags macro LKB$L_TPID = 28,0,32,0 %; ! Kernel Thread ID macro LKB$L_KAST = 32,0,32,1 %; ! Special Kernel AST address macro LKB$PQ_AST = 40,0,0,1 %; literal LKB$S_AST = 8; ! Address of AST routine macro LKB$W_RQSEQNM = 40,0,16,0 %; ! Request sequence number macro LKB$Q_RQSEQNM = 40,0,0,0 %; literal LKB$S_RQSEQNM = 8; ! Request sequence number macro LKB$Q_ASTPRM = 48,0,0,0 %; literal LKB$S_ASTPRM = 8; ! AST parameter macro LKB$L_EPID = 48,0,32,0 %; ! EPID (Master copies only) macro LKB$Q_USER_THREAD_ID = 56,0,0,0 %; literal LKB$S_USER_THREAD_ID = 8; ! ACB unique user thread identifier macro LKB$L_ACB = 64,0,32,0 %; ! Pointer to ACB macro LKB$L_REFCNT = 68,0,32,0 %; ! Sub-LKB reference count macro LKB$L_FLAGS = 72,0,32,0 %; ! User specified flags macro LKB$L_STATUS = 76,0,32,0 %; ! Internal status macro LKB$V_DCPLAST = 76,0,1,0 %; ! Deliver Completion AST macro LKB$V_ASYNC = 76,2,1,0 %; ! Request completed asynchronously macro LKB$V_BLKASTQED = 76,3,1,0 %; ! Blocking AST has been queued macro LKB$V_MSTCPY = 76,4,1,0 %; ! LKB is a Master copy macro LKB$V_NOQUOTA = 76,5,1,0 %; ! Don't charge quota macro LKB$V_TIMOUTQ = 76,6,1,0 %; ! LKB is on timeout queue macro LKB$V_WASSYSOWN = 76,7,1,0 %; ! Was System Owned lock macro LKB$V_CVTTOSYS = 76,8,1,0 %; ! Convert to System Owned macro LKB$V_PROTECT = 76,9,1,0 %; ! Protected lock macro LKB$V_RESEND = 76,10,1,0 %; ! Resend during failover macro LKB$V_RM_RBRQD = 76,11,1,0 %; ! Remaster rebuild required macro LKB$V_FLOCK = 76,12,1,0 %; ! Fork lock macro LKB$V_IP = 76,13,1,0 %; ! Operation in progress macro LKB$V_CACHED = 76,14,1,0 %; ! LKB is in cache macro LKB$V_RNGBLK = 76,15,1,0 %; ! Range block specified macro LKB$V_BRL = 76,16,1,0 %; ! Indicate byte range lock macro LKB$V_NEWSUBRNG = 76,17,1,0 %; ! New sub-range request macro LKB$V_CVTSUBRNG = 76,18,1,0 %; ! Sub-range convert request macro LKB$V_RNGCHG = 76,19,1,0 %; ! Changing range macro LKB$V_2PC_IP = 76,20,1,0 %; ! Two phase operation in progress macro LKB$V_2PC_PEND = 76,21,1,0 %; ! Two phase operation pending macro LKB$V_BLKASTFLG = 76,22,1,0 %; ! Indicates BLKAST specified macro LKB$V_GRSUBRNG = 76,23,1,0 %; ! Granted sub-range lock macro LKB$V_PCACHED = 76,24,1,0 %; ! LKB is to be cached macro LKB$V_VALBLKRD = 76,25,1,0 %; ! Indicates read access to value block macro LKB$V_VALBLKWRT = 76,26,1,0 %; ! Indicates write access to value block macro LKB$V_DPC = 76,27,1,0 %; ! Delete pending cache macro LKB$V_PERCPU = 76,28,1,0 %; ! Per-CPU lock request macro LKB$L_LKST1 = 80,0,32,0 %; ! First lock status longword macro LKB$L_LKST2 = 84,0,32,0 %; ! Second lock status longword macro LKB$L_LKID = 84,0,32,0 %; ! Lock ID macro LKB$V_INDEX = 84,0,24,0 %; literal LKB$S_INDEX = 24; ! Lock ID Index macro LKB$V_SEQN = 84,24,8,0 %; literal LKB$S_SEQN = 8; ! Lock ID Sequence Number macro LKB$B_RQMODE = 88,0,8,0 %; ! Request mode macro LKB$B_GRMODE = 89,0,8,0 %; ! Granted mode macro LKB$B_TSLT = 90,0,8,0 %; ! Timestamp lifetime macro LKB$B_EFN = 91,0,8,0 %; ! Event Flag Number macro LKB$B_STATE = 92,0,8,0 %; ! Lock state macro LKB$L_STATE = 92,0,32,0 %; ! Lock state macro LKB$Q_SQFL = 96,0,0,1 %; literal LKB$S_SQFL = 8; ! State queue forward link macro LKB$Q_SQBL = 104,0,0,1 %; literal LKB$S_SQBL = 8; ! State queue backward link macro LKB$Q_OWNQFL = 112,0,0,1 %; literal LKB$S_OWNQFL = 8; ! Owner queue forward link macro LKB$Q_OWNQBL = 120,0,0,1 %; literal LKB$S_OWNQBL = 8; ! Owner queue backward link macro LKB$Q_TIMOUTQFL = 128,0,0,1 %; literal LKB$S_TIMOUTQFL = 8; ! Timeout queue forward link macro LKB$Q_TIMOUTQBL = 136,0,0,1 %; literal LKB$S_TIMOUTQBL = 8; ! Timeout queue backward link macro LKB$Q_PARENT = 144,0,0,1 %; literal LKB$S_PARENT = 8; ! Address of parent LKB macro LKB$Q_RSB = 152,0,0,1 %; literal LKB$S_RSB = 8; ! Address of owner RSB macro LKB$PQ_LKSB = 160,0,0,1 %; literal LKB$S_LKSB = 8; ! Address of lock status block macro LKB$L_DLCKPRI = 160,0,32,0 %; ! Deadlock priority (Master copies) macro LKB$L_RQSTSRNG = 168,0,32,1 %; ! Starting byte of requested range macro LKB$L_RQSTERNG = 172,0,32,1 %; ! Ending byte of requested range macro LKB$L_GRNTSRNG = 176,0,32,1 %; ! Starting byte of granted range macro LKB$L_GRNTERNG = 180,0,32,1 %; ! Ending byte of granted range macro LKB$L_LCKCTX = 184,0,32,1 %; ! Address of Lock Context Block macro LKB$L_REMLKID = 188,0,32,0 %; ! Remote Lock ID (Master) macro LKB$L_CSID = 192,0,32,0 %; ! Cluster System ID (Master only) macro LKB$Q_OLDASTPRM = 192,0,0,0 %; literal LKB$S_OLDASTPRM = 8; ! Old AST parameter macro LKB$PQ_OLDBLKAST = 200,0,0,1 %; literal LKB$S_OLDBLKAST = 8; ! Old Blocking AST address macro LKB$PQ_CPLASTADR = 208,0,0,1 %; literal LKB$S_CPLASTADR = 8; ! Address of Completion AST routine macro LKB$PQ_BLKASTADR = 216,0,0,1 %; literal LKB$S_BLKASTADR = 8; ! Address of Blocking AST routine macro LKB$L_PRIORITY = 224,0,32,0 %; ! Request's priority macro LKB$L_TSKPID = 228,0,32,0 %; ! Task ID macro LKB$L_RSDMID = 232,0,32,0 %; ! Resource Domain ID macro LKB$L_PCB = 236,0,32,0 %; ! Address of PCB macro LKB$L_LCKRQ = 240,0,32,0 %; ! Address of per-CPU lock request macro LKB$L_STATUS2 = 244,0,32,0 %; ! Internal status macro LKB$V_DBLKAST = 244,1,1,0 %; ! Deliver Blocking AST macro LKB$Q_DUETIME = 248,0,0,0 %; literal LKB$S_DUETIME = 8; ! duetime for waiting locks !*** MODULE $LMBDEF *** ! + ! LMB - Logical Memory Block ! ! Logical Memory Block definitions (for subsetted crash dumps) ! Layout of each Logical Memory Block and accompanying hole descriptor. ! Logical Memory Blocks are portions of selective memory dumps. "Holes" ! refer to areas of invalid or inaccessible virtual address space at the ! time of the dump. ! - literal LMB$C_SHARED_MEMORY = -2; ! Galaxy shared memory (complete) literal LMB$C_SHARED_REGION = -1; ! Galaxy shared memory region (single) literal LMB$C_PT = 0; ! PT Space literal LMB$C_S0S1 = 1; ! S0/S1 Space (excluding SPT window) literal LMB$C_S2 = 2; ! S2 Space (includes PFN database, GPT) literal LMB$C_REPLICATED_SYS = 3; ! Replicated system space (Wildfires etc) literal LMB$C_MMAPS = 4; ! Galaxy memory map pages literal LMB$C_KEY_PROCESS_PT = 5; ! Process page tables ... literal LMB$C_KEY_PROCESS_MEM = 6; ! ... and memory (current, swapper, other current, site-specific, HP-defined) literal LMB$C_KEY_GBL = 7; ! Global Pages (associated with key processes) literal LMB$C_OTHER_PROCESS_PT = 8; ! Process page tables ... literal LMB$C_OTHER_PROCESS_MEM = 9; ! ... and memory (all other processes) literal LMB$C_OTHER_GBL = 10; ! Global Pages (not associated with key processes) ! Make changes and additions before this line literal LMB$C_NUMTYPES = 11; ! The number of LMB types ! LMB flavors for process dumps literal LMB$C_PROCESS_SPACE = 256; ! Entire process space from zero to the L1PT page literal LMB$C_SYSTEM_SPACE = 257; ! Process-pertinent data in system space literal LMB$M_INCOMPLETE = %X'1'; literal LMB$K_LENGTH = 136; ! Logical mem block length literal LMB$C_LENGTH = 136; ! Logical mem block length literal LMB$S_LMBDEF = 136; ! Old size name - synonym literal LMB$S_LMB = 512; macro LMB$W_TYPE = 0,0,16,1 %; ! Type of LMB ! LMB flavors macro LMB$W_FLAGS = 2,0,16,0 %; ! Flags for this LMB macro LMB$V_INCOMPLETE = 2,0,1,0 %; ! LMB not completely written macro LMB$L_ACT_LENGTH = 4,0,32,1 %; ! LMB data actual length (blocks) macro LMB$L_NOCOMP_LENGTH = 8,0,32,1 %; ! as ACT_LENGTH without compression macro LMB$W_HOLE_TBL = 12,0,16,0 %; ! relative VBN in dump of start of the table ! describing the holes in the ! virtual address space. macro LMB$W_PMAP_TBL = 12,0,16,0 %; ! just another name for the same with ! shared memory dumps macro LMB$W_BADMEM_PTRS = 14,0,16,0 %; ! Offset of bad memory descriptor ! list. List terminates with -1 or ! at end of LMB block 1. ! Offset is from start of LMB block 1. macro LMB$L_TOTAL_HOLES = 16,0,32,0 %; ! Count of holes in LMB macro LMB$L_TOTAL_PMAPS = 16,0,32,0 %; ! count of PMAPs (fragments) in shared ! memory LMB macro LMB$L_PCBADR = 20,0,32,1 %; ! SVA of this process's PCB macro LMB$L_RAD = 20,0,32,0 %; ! RAD for this LMB of replicated system space macro LMB$Q_TIME_CHECK = 24,0,0,0 %; literal LMB$S_TIME_CHECK = 8; ! Ones-complement of EMB$Q_CR_TIME macro LMB$T_PROCESS_NAME = 32,0,0,0 %; literal LMB$S_PROCESS_NAME = 16; ! Process name (only for TYPE=PROCESS) macro LMB$PQ_START_VA = 48,0,0,1 %; literal LMB$S_START_VA = 8; ! Start of range of addresses searched ! for holes by BUGCHECK macro LMB$PQ_END_VA = 56,0,0,1 %; literal LMB$S_END_VA = 8; ! End of range of addresses searched ! for holes by BUGCHECK macro LMB$Q_START_OFFSET = 48,0,0,0 %; literal LMB$S_START_OFFSET = 8; ! Start of range of addresses dumped ! by DUMP_SHARED_MEMORY macro LMB$Q_END_OFFSET = 56,0,0,0 %; literal LMB$S_END_OFFSET = 8; ! End of range of addresses dumped ! by DUMP_SHARED_MEMORY macro LMB$T_REGION_TAG = 64,0,0,0 %; literal LMB$S_REGION_TAG = 64; ! Region name for shared memory LMBs macro LMB$L_CMAP_START = 128,0,32,0 %; ! Offset into compression map of first entry for this LMB macro LMB$L_CMAP_COUNT = 132,0,32,0 %; ! Count of compression map entries for this LMB literal LMB$K_HOLE_LENGTH = 16; literal LMB$C_HOLE_LENGTH = 16; ! Size of each hole table entry. literal LMB$S_LMB_HOLE = 16; macro LMB$PQ_HOLE_START_VA = 0,0,0,1 %; literal LMB$S_HOLE_START_VA = 8; ! Starting VA for this hole macro LMB$Q_HOLE_TOTAL_PAGES = 8,0,0,0 %; literal LMB$S_HOLE_TOTAL_PAGES = 8; ! Running total of pages of holes ! up to the starting VA of this hole ! Offset to get to the next hole ! table entry. literal LMB$S_LMB_BADMEM = 20; macro LMB$PQ_BADMEM_START = 0,0,0,1 %; literal LMB$S_BADMEM_START = 8; ! Starting VA of bad memory section macro LMB$PQ_BADMEM_END = 8,0,0,1 %; literal LMB$S_BADMEM_END = 8; ! Ending VA of bad memory section macro LMB$L_BADMEM_NEXT = 16,0,32,0 %; ! Size of one entry in bad memory table !*** MODULE $LMFITMDEF *** ! + ! LMFITMDEF - LMF internal item-list definitions ! ! Items lists used by the internal routines LMF$LOAD and LMF$UNLOAD, ! which manipulate the on-disk and in-memory License databases. ! These routines now have a callable interface, and the caller needs ! access to these item codes. ! - ! These are the item codes passed from the LMF utility to the callable ! routines in the item list. New codes should be added to the end. literal LMF$k_ldb = 0; literal LMF$k_producer = 1; literal LMF$k_product = 2; literal LMF$k_version = 3; literal LMF$k_issuer = 4; literal LMF$k_comment = 5; literal LMF$k_authorization = 6; literal LMF$k_units = 7; literal LMF$k_availability = 8; literal LMF$k_activity = 9; literal LMF$k_token = 10; literal LMF$k_termination = 11; literal LMF$k_date = 12; literal LMF$k_hardware_id = 13; literal LMF$k_checksum = 14; literal LMF$K_INCLUDE = 15; literal LMF$k_exclude = 16; literal LMF$k_options = 17; literal LMF$k_output_name = 18; literal LMF$k_extinct_qualifier = 19; literal LMF$k_load_qualifier = 20; literal LMF$k_cust_termination = 21; literal LMF$k_cust_date = 22; literal LMF$k_full_qualifier = 23; literal LMF$k_brief_qualifier = 24; literal LMF$k_creation_date = 25; literal LMF$K_LMF_version_number = 26; literal LMF$k_creating_username = 27; literal LMF$k_log_qualifier = 28; !*** MODULE $LGIDEF *** literal LGI$C_LENGTH = 24; ! Data structure length literal LGI$K_LENGTH = 24; ! Data structure length literal LGI$C_CHARTIME = 15; ! Terminal driver timeout value literal LGI$K_CHARTIME = 15; ! Terminal driver timeout value literal LGI$S_LGIDATDEF = 24; ! Old size name - synonym literal LGI$S_LGIDAT = 24; macro LGI$L_ORIGUIC = 0,0,32,0 %; ! Original UIC at job creation time macro LGI$T_OUTFNM = 4,0,0,0 %; literal LGI$S_OUTFNM = 20; ! For batch, file name/type of output ! for spooling log file in batch jobs literal LGI$M_OPENACCT = %X'1'; literal LGI$M_PASSWORD = %X'2'; literal LGI$M_PASSWORD2 = %X'4'; literal LGI$M_GENPWD = %X'8'; literal LGI$_PRIMARY_PASSWORD = 1; ! primary password literal LGI$_SECONDARY_PASSWORD = 2; ! secondary password literal LGI$_SOURCE_NODE = 3; ! source nodename literal LGI$_SOURCE_ID = 4; ! source id (username) literal LGI$_SOURCE_ADDRESS = 5; ! source DECnet address literal LGI$_SOURCE_TERMINAL = 6; ! source terminal literal LGI$_PARENT_USERNAME = 7; ! parent username literal LGI$_PARENT_PID = 8; ! parent PID literal LGI$_JOB_TYPE = 9; ! job type literal LGI$_MAX_CODE = 10; ! last item code (plus one) literal LGI$S_LGIAUTHDEF = 4; ! Old size name - synonym literal LGI$S_LGIAUTH = 4; macro LGI$L_AUTH_FLAGS = 0,0,32,0 %; macro LGI$V_OPENACCT = 0,0,1,0 %; ! account requires no passwords macro LGI$V_PASSWORD = 0,1,1,0 %; ! account has primary password macro LGI$V_PASSWORD2 = 0,2,1,0 %; ! account has secondary password macro LGI$V_GENPWD = 0,3,1,0 %; ! Extra bit returned by the ! VMS ACME for the old ! DECwindows login literal LGI$_DISUSER_STOP = 1; ! stop on error literal LGI$_DISUSER_RETURN = 2; ! return on error literal LGI$_VALIDATE_STOP = 1; ! stop on error literal LGI$_VALIDATE_RETURN = 2; ! return on error literal LGI$_GET_INPUT_STOP = 0; ! stop on error literal LGI$_GET_INPUT_HANGUP = 1; ! hangup quietly on error literal LGI$_GET_INPUT_RETURN_TMO = 2; ! return on timout literal LGI$M_NET_PROXY = %X'1'; literal LGI$M_NET_PREAUTH = %X'2'; literal LGI$M_NET_DEFAULT_USER = %X'4'; literal LGI$M_NET_PROXY_OK = %X'8'; literal LGI$M_NET_REM_INFO_PRESENT = %X'10'; literal LGI$S_LGINETDEF = 2; ! Old size name - synonym literal LGI$S_LGINET = 2; macro LGI$W_NET_AUTH_FLAGS = 0,0,16,0 %; macro LGI$V_NET_PROXY = 0,0,1,0 %; ! DECNET wants proxy login macro LGI$V_NET_PREAUTH = 0,1,1,0 %; ! DECNET has authenticated macro LGI$V_NET_DEFAULT_USER = 0,2,1,0 %; ! DECNET application or session ! database has username macro LGI$V_NET_PROXY_OK = 0,3,1,0 %; ! (local use) proxy validated macro LGI$V_NET_REM_INFO_PRESENT = 0,4,1,0 %; ! Phase V provided rem info literal LGI$S_LGIARG_VECTOR = 136; macro LGI$ICB_GET_INPUT = 0,0,32,0 %; ! Addresses of callbacks macro LGI$ICB_DECW_IDENT = 4,0,32,0 %; macro LGI$ICB_DECW_AUTH = 8,0,32,0 %; macro LGI$ICB_GET_SYSPWD = 12,0,32,0 %; macro LGI$ICB_USERPROMPT = 16,0,32,0 %; macro LGI$ICB_USERPARSE = 20,0,32,0 %; macro LGI$ICB_AUTOLOGIN = 24,0,32,0 %; macro LGI$ICB_PASSWORD = 28,0,32,0 %; macro LGI$ICB_CHECK_PASS = 32,0,32,0 %; macro LGI$ICB_VALIDATE = 36,0,32,0 %; macro LGI$ICB_ACCTEXPIRED = 40,0,32,0 %; macro LGI$ICB_PWDEXPIRED = 44,0,32,0 %; macro LGI$ICB_DISUSER = 48,0,32,0 %; macro LGI$ICB_MODALHOURS = 52,0,32,0 %; macro LGI$A_ICR_CREPRC_FLAGS = 56,0,32,0 %; ! Addresses of variables macro LGI$A_ICR_JOB_TYPE = 60,0,32,0 %; macro LGI$A_ICR_SUBPROCESS = 64,0,32,0 %; macro LGI$A_ICR_TERMINAL_DEV = 68,0,32,0 %; macro LGI$A_ICR_TT_PHYDEVNAM = 72,0,32,0 %; macro LGI$A_ICR_TT_ACCPORNAM = 76,0,32,0 %; macro LGI$A_ICR_CLINAME = 80,0,32,0 %; macro LGI$A_ICR_CLITABLES = 84,0,32,0 %; macro LGI$A_ICR_NCB = 88,0,32,0 %; macro LGI$A_ICR_LOGLINK = 92,0,32,0 %; macro LGI$A_ICR_REM_NODE_NAM = 96,0,32,0 %; macro LGI$A_ICR_REM_ID = 100,0,32,0 %; macro LGI$A_ICR_UAF_RECORD = 104,0,32,0 %; macro LGI$A_ICR_INPUT_RAB = 108,0,32,0 %; macro LGI$A_ICR_AUTOLOGIN = 112,0,32,0 %; macro LGI$A_ICR_USERNAME = 116,0,32,0 %; macro LGI$A_ICR_PWD1 = 120,0,32,0 %; macro LGI$A_ICR_PWD2 = 124,0,32,0 %; macro LGI$A_ICR_PWDCOUNT = 128,0,32,0 %; macro LGI$A_ICR_NETFLAGS = 132,0,32,0 %; literal LGI$ICR_INIT = 4; literal LGI$ICR_IACT_START = 8; literal LGI$ICR_DECWINIT = 12; literal LGI$ICR_IDENTIFY = 16; literal LGI$ICR_AUTHENTICATE = 20; literal LGI$ICR_CHKRESTRICT = 24; literal LGI$ICR_FINISH = 28; literal LGI$ICR_LOGOUT = 32; literal LGI$ICR_JOBSTEP = 36; literal LGI$ICR_CHKLICENSE = 40; literal LGI$S_LGICALLOUT_VECTOR = 44; macro LGI$L_ICR_ENTRY_COUNT = 0,0,32,0 %; macro LGI$A_ICR_INIT = 4,0,32,0 %; macro LGI$A_ICR_IACT_START = 8,0,32,0 %; macro LGI$A_ICR_DECWINIT = 12,0,32,0 %; macro LGI$A_ICR_IDENTIFY = 16,0,32,0 %; macro LGI$A_ICR_AUTHENTICATE = 20,0,32,0 %; macro LGI$A_ICR_CHKRESTRICT = 24,0,32,0 %; macro LGI$A_ICR_FINISH = 28,0,32,0 %; macro LGI$A_ICR_LOGOUT = 32,0,32,0 %; macro LGI$A_ICR_JOBSTEP = 36,0,32,0 %; macro LGI$A_ICR_CHKLICENSE = 40,0,32,0 %; literal LGI$M_UPCASE = %X'1'; literal LGI$M_SYNTAX = %X'2'; literal LGI$M_LENGTH = %X'4'; literal LGI$S_LGIPASS = 4; macro LGI$L_PASS_FLAGS = 0,0,32,0 %; macro LGI$V_UPCASE = 0,0,1,0 %; ! upcase password if appropriate macro LGI$V_SYNTAX = 0,1,1,0 %; ! check password syntax macro LGI$V_LENGTH = 0,2,1,0 %; ! check for maximum password length !*** MODULE $LOGDEF *** ! + ! LOG - LOGICAL NAME BLOCK ! ! THERE IS ONE LOGICAL NAME BLOCK FOR EACH LOGICAL NAME ASSIGNMENT IN A ! SYSTEM. LOGICAL NAME BLOCKS CAN BE LINKED INTO ONE OF THREE TABLES: ! 1. A PER PROCESS TABLE. ! 2. A GROUP WIDE TABLE. ! 3. THE SYSTEM WIDE TABLE. ! - literal LOG$K_LENGTH = 20; ! LENGTH OF FIXED PART OF LOG literal LOG$C_LENGTH = 20; ! LENGTH OF FIXED PART OF LOG literal LOG$C_SYSTEM = 0; ! SYSTEM NAME TABLE literal LOG$C_GROUP = 1; ! GROUP NAME TABLE literal LOG$C_PROCESS = 2; ! PROCESS NAME TABLE ! literal LOG$C_NAMLENGTH = 64; ! MAXIMUM LENGTH OF LOGICAL NAME STRING literal LOG$S_LOGDEF = 20; ! Old size name - synonym literal LOG$S_LOGNAME = 20; macro LOG$L_LTFL = 0,0,32,1 %; ! LOGICAL TABLE FORWARD LINK macro LOG$L_LTBL = 4,0,32,1 %; ! LOGICAL TABLE BACKWARD LINK macro LOG$W_SIZE = 8,0,16,0 %; ! SIZE OF LOG IN BYTES macro LOG$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE FOR LOG macro LOG$B_TABLE = 11,0,8,0 %; ! LOGICAL NAME TABLE TYPE macro LOG$W_GROUP = 12,0,16,0 %; ! CREATOR GROUP NUMBER macro LOG$B_AMOD = 14,0,8,0 %; ! ACCESS MODE OF CREATOR macro LOG$L_MBXUCB = 16,0,32,1 %; ! MAILBOX UCB ADDRESS macro LOG$T_NAME = 20,0,0,0 %; ! START OF LOGICAL NAME ! ! LOGICAL NAME TABLE NUMBERS ! ! MAXIMUM LENGTH OF LOGICAL NAME STRING ! !*** MODULE $LNMSTRDEF *** literal LNMB$M_NO_ALIAS = %X'1'; literal LNMB$M_CONFINE = %X'2'; literal LNMB$M_CRELOG = %X'4'; literal LNMB$M_TABLE = %X'8'; literal LNMB$M_NODELETE = %X'10'; literal LNMB$M_CLUSTERWIDE = %X'20'; literal LNMB$M_REMACTION = %X'40'; literal LNMB$S_LNMBDEF = 33; ! Old size name - synonym literal LNMB$S_LNMB = 33; macro LNMB$L_FLINK = 0,0,32,1 %; ! Forward link in list macro LNMB$L_BLINK = 4,0,32,1 %; ! Backward link in list macro LNMB$W_SIZE = 8,0,16,0 %; ! Size of LNMB in bytes macro LNMB$B_TYPE = 10,0,8,0 %; ! Structure type for LNMB macro LNMB$B_PAD = 11,0,8,1 %; ! Align to longword boundary macro LNMB$L_ACMODE = 12,0,32,0 %; ! Owner access mode / integrity level byte macro LNMB$L_TABLE = 16,0,32,1 %; ! Logical name table header address macro LNMB$L_LNMX = 20,0,32,1 %; ! Pointer to first LNMX macro LNMB$R_FLAG_BITS = 24,0,32,0 %; macro LNMB$L_FLAGS = 24,0,32,0 %; ! Name attributes macro LNMB$R_BITS = 24,0,8,0 %; literal LNMB$S_BITS = 1; macro LNMB$V_NO_ALIAS = 24,0,1,0 %; ! Do not allow outer mode alias macro LNMB$V_CONFINE = 24,1,1,0 %; ! Do not copy into subprocess macro LNMB$V_CRELOG = 24,2,1,0 %; ! Created with old $CRELOG service macro LNMB$V_TABLE = 24,3,1,0 %; ! This is a table name macro LNMB$V_NODELETE = 24,4,1,0 %; ! Do not allow this table to be deleted macro LNMB$V_CLUSTERWIDE = 24,5,1,0 %; ! Name is in a "clusterwide" table ! (this bit drives collision semantics, return of ! clusterwide as $TRNLNM attribute) ! (only this bit could be set for "clusterwide" name or table ! on a node booted standalone) macro LNMB$V_REMACTION = 24,6,1,0 %; ! Name is replicated on other cluster nodes ! (this bit drives replication and stall semantics) ! (if this is set, clusterwide should be set) macro LNMB$L_NAMELEN = 28,0,32,0 %; ! Length of logical name string macro LNMB$T_NAME = 32,0,8,0 %; ! Name string ! Translation blocks follow name - ! pointed to by LNMB$L_LNMX literal LNMX$M_CONCEALED = %X'1'; literal LNMX$M_TERMINAL = %X'2'; literal LNMX$C_HSHFCN = -128; ! Hash function value literal LNMX$C_BACKPTR = -127; ! Backpointer translation literal LNMX$C_TABLE = -126; ! Logical name table header literal LNMX$C_IGNORED_INDEX = -125; ! Modified back pointer for process-private names literal LNMX$C_CW_LINKS = -124; ! Links clusterwide LNMBs together literal LNMX$S_LNMXDEF = 25; ! Old size name - synonym literal LNMX$S_LNMX = 25; macro LNMX$R_FLAG_BITS = 0,0,32,0 %; macro LNMX$L_FLAGS = 0,0,32,0 %; ! Translation attributes macro LNMX$R_BITS = 0,0,8,0 %; literal LNMX$S_BITS = 1; macro LNMX$V_CONCEALED = 0,0,1,0 %; ! Do not display result of translation macro LNMX$V_TERMINAL = 0,1,1,0 %; ! Do not retranslate result of translation macro LNMX$L_INDEX = 4,0,32,1 %; ! Translation index macro LNMX$L_HASH = 8,0,32,1 %; ! Hash code for logical names in directories macro LNMX$L_NEXT = 12,0,32,1 %; ! Pointer to next lnmx macro LNMX$L_PAD = 16,0,32,0 %; ! Padding to keep quadword alignment macro LNMX$L_XLEN = 20,0,32,0 %; ! Length of translation string macro LNMX$T_XLATION = 24,0,8,0 %; ! Translation string ! Additional translation blocks follow xlation - ! pointed to by LNMX$L_NEXT. literal LNMX$S_CW_LNMX = 36; literal LNMX$S_CWLNMX = 36; macro LNMX$L_CW_FLINK = 24,0,32,1 %; ! Forward link for clusterwide names macro LNMX$L_CW_BLINK = 28,0,32,1 %; ! Backward link for clusterwide names macro LNMX$L_CW_LNMB = 32,0,32,1 %; ! Pointer to LNMB start address literal LNMTH$M_SHAREABLE = %X'1'; literal LNMTH$M_DIRECTORY = %X'2'; literal LNMTH$M_GROUP = %X'4'; literal LNMTH$M_SYSTEM = %X'8'; literal LNMTH$M_CLUSTERWIDE = %X'10'; literal LNMTH$M_REMACTION = %X'20'; literal LNMTH$K_LENGTH = 40; ! Length of header literal LNMTH$S_LNMTHDEF = 40; ! Old size name - synonym literal LNMTH$S_LNMTH = 40; macro LNMTH$R_FLAG_BITS = 0,0,32,0 %; macro LNMTH$L_FLAGS = 0,0,32,0 %; ! Logical name table flags macro LNMTH$R_BITS = 0,0,8,0 %; literal LNMTH$S_BITS = 1; macro LNMTH$V_SHAREABLE = 0,0,1,0 %; ! Logical name table is shareable (S0 space) macro LNMTH$V_DIRECTORY = 0,1,1,0 %; ! Logical name table is a directory table macro LNMTH$V_GROUP = 0,2,1,0 %; ! Logical name table is a group logical name table macro LNMTH$V_SYSTEM = 0,3,1,0 %; ! Logical name table is the system logical name table macro LNMTH$V_CLUSTERWIDE = 0,4,1,0 %; ! Table is "clusterwide" macro LNMTH$V_REMACTION = 0,5,1,0 %; ! Table is replicated on other cluster nodes macro LNMTH$L_HASH = 4,0,32,1 %; ! Address of hash table macro LNMTH$L_ORB = 8,0,32,1 %; ! Address of Object Rights Block macro LNMTH$L_NAME = 12,0,32,1 %; ! Address of containing LNMB block macro LNMTH$L_PARENT = 16,0,32,1 %; ! Address of parent table macro LNMTH$L_CHILD = 20,0,32,1 %; ! Address of a child table macro LNMTH$L_SIBLING = 24,0,32,1 %; ! Address of a sibling table macro LNMTH$L_QTABLE = 28,0,32,1 %; ! Address of table holding quota macro LNMTH$L_BYTESLM = 32,0,32,1 %; ! Initial quota macro LNMTH$L_BYTES = 36,0,32,1 %; ! Remaining quota literal LNMC$K_NUM_ENTRIES = 25; ! Number of table header entries. literal LNMC$K_LENGTH = 128; ! Length of header literal LNMC$S_LNMCDEF = 128; ! Old size name - synonym literal LNMC$S_LNMC = 128; macro LNMC$L_FLINK = 0,0,32,1 %; ! Forward link in list macro LNMC$L_BLINK = 4,0,32,1 %; ! Backward link in list macro LNMC$W_SIZE = 8,0,16,0 %; ! Size of LNMC in bytes macro LNMC$B_TYPE = 10,0,8,0 %; ! Structure type for LNMC macro LNMC$B_MODE = 11,0,8,0 %; ! Access mode macro LNMC$L_CACHEINDX = 12,0,32,0 %; ! Current entry number macro LNMC$L_TBLADDR = 16,0,32,1 %; ! Logical name table name address macro LNMC$L_PROCDIRSEQ = 20,0,32,0 %; ! Process directory sequence number macro LNMC$L_SYSDIRSEQ = 24,0,32,0 %; ! System directory sequence number macro LNMC$L_ENTRY = 28,0,0,1 %; literal LNMC$S_ENTRY = 100; ! Logical name table header addresses literal LNMHSH$C_BUCKET = 12; ! Length of fixed part of LNMHSH literal LNMHSH$K_BUCKET = 12; ! Length of fixed part of LNMHSH literal LNMHSH$S_LNMHSHDEF = 12; ! Old size name - synonym literal LNMHSH$S_LNMHSH = 12; macro LNMHSH$L_MASK = 0,0,32,0 %; ! Mask for hash value macro LNMHSH$W_SIZE = 8,0,16,0 %; ! Size of LNMHSH in bytes macro LNMHSH$B_TYPE = 10,0,8,0 %; ! Structure type for LNMHSH !*** MODULE $MADEF *** ! ! Definitions for Memory Attributes ! literal MA$C_WBU = 0; ! Write back, unordered literal MA$C_UC = 4; ! Non-coalescing, sequential & non-speculative literal MA$C_UCE = 5; ! Non-coalescing, sequential, non-speculative ! & fetchadd exported literal MA$C_WC = 6; ! Non-cached, Coalescing, non-seq., spec. literal MA$C_NAT = 7; ! NaT page !*** MODULE $MBADEF *** ! + ! MASSBUS ADAPTER REGISTER OFFSET DEFINITIONS ! - literal MBA$M_CSR_OT = %X'200000'; literal MBA$M_CSR_PU = %X'400000'; literal MBA$M_CSR_PD = %X'800000'; literal MBA$M_CSR_XMFLT = %X'4000000'; literal MBA$M_CSR_MT = %X'8000000'; literal MBA$M_CSR_URD = %X'20000000'; literal MBA$M_CSR_WS = %X'40000000'; literal MBA$M_CSR_PE = %X'80000000'; literal MBA$M_CR_INIT = %X'1'; literal MBA$M_CR_ABORT = %X'2'; literal MBA$M_CR_IE = %X'4'; literal MBA$M_SR_RDTO = %X'1'; literal MBA$M_SR_ISTO = %X'2'; literal MBA$M_SR_RDS = %X'4'; literal MBA$M_SR_ERCONF = %X'8'; literal MBA$M_SR_INVMAP = %X'10'; literal MBA$M_SR_MAPPE = %X'20'; literal MBA$M_SR_MDPE = %X'40'; literal MBA$M_SR_MBEXC = %X'80'; literal MBA$M_SR_MXF = %X'100'; literal MBA$M_SR_WCKLWR = %X'200'; literal MBA$M_SR_WCKUPR = %X'400'; literal MBA$M_SR_DLT = %X'800'; literal MBA$M_SR_DTABT = %X'1000'; literal MBA$M_SR_DTCOMP = %X'2000'; literal MBA$M_SR_SPE = %X'4000'; literal MBA$M_SR_ATTN = %X'10000'; literal MBA$M_SR_MCPE = %X'20000'; literal MBA$M_SR_NED = %X'40000'; literal MBA$M_SR_PGE = %X'80000'; literal MBA$M_SR_CBHUNG = %X'800000'; literal MBA$M_SR_CRD = %X'20000000'; literal MBA$M_SR_NRCONF = %X'40000000'; literal MBA$M_SR_DTBUSY = %X'80000000'; literal MBA$M_ERROR = 942079; ! PROGRAM ERROR literal MBA$S_MBADEF = 3072; ! Old size name - synonym literal MBA$S_MBA = 3072; macro MBA$L_CSR = 0,0,32,0 %; ! CONFIGURATION STATUS REGISTER macro MBA$V_CSR_ADCOD = 0,0,8,0 %; literal MBA$S_CSR_ADCOD = 8; ! ADAPTER CODE FIELD macro MBA$V_CSR_OT = 0,21,1,0 %; ! OVER TEMPERATURE macro MBA$V_CSR_PU = 0,22,1,0 %; ! ADAPTER POWER UP macro MBA$V_CSR_PD = 0,23,1,0 %; ! ADAPTER POWER DOWN macro MBA$V_CSR_XMFLT = 0,26,1,0 %; ! TRANSMITTER FAULT macro MBA$V_CSR_MT = 0,27,1,0 %; ! MULTIPLE TRANSMITTERS macro MBA$V_CSR_URD = 0,29,1,0 %; ! UNEXPECTED READ DATA macro MBA$V_CSR_WS = 0,30,1,0 %; ! WRITE SEQUENCE DATA macro MBA$V_CSR_PE = 0,31,1,0 %; ! SBI PARITY ERROR macro MBA$L_CR = 4,0,32,0 %; ! CONTROL REGISTER macro MBA$V_CR_INIT = 4,0,1,0 %; ! ADAPTER INITIALIZATION macro MBA$V_CR_ABORT = 4,1,1,0 %; ! ABORT OPERATION macro MBA$V_CR_IE = 4,2,1,0 %; ! INTERRUPT ENABLE macro MBA$L_SR = 8,0,32,0 %; ! STATUS REGISTER macro MBA$V_SR_RDTO = 8,0,1,0 %; ! READ DATA TIMEOUT macro MBA$V_SR_ISTO = 8,1,1,0 %; ! INTERFACE SEQUENCE TIMEOUT macro MBA$V_SR_RDS = 8,2,1,0 %; ! READ DATA SUBSTITUTE macro MBA$V_SR_ERCONF = 8,3,1,0 %; ! ERROR CONFIRMATION macro MBA$V_SR_INVMAP = 8,4,1,0 %; ! INVALID MAP REGISTER macro MBA$V_SR_MAPPE = 8,5,1,0 %; ! MAP PARITY ERROR macro MBA$V_SR_MDPE = 8,6,1,0 %; ! MASSBUS DATA PARITY ERROR macro MBA$V_SR_MBEXC = 8,7,1,0 %; ! MASSBUS EXCEPTION macro MBA$V_SR_MXF = 8,8,1,0 %; ! MISSED TRANSFER ERROR macro MBA$V_SR_WCKLWR = 8,9,1,0 %; ! WRITE CHECK ERROR LOWER BYTE macro MBA$V_SR_WCKUPR = 8,10,1,0 %; ! WRITE CHECK ERROR UPPER BYTE macro MBA$V_SR_DLT = 8,11,1,0 %; ! DATA LATE ERROR macro MBA$V_SR_DTABT = 8,12,1,0 %; ! DATA TRANSFER ABORTED macro MBA$V_SR_DTCOMP = 8,13,1,0 %; ! DATA TRANSFER COMPLETE macro MBA$V_SR_SPE = 8,14,1,0 %; ! SILO PARITY ERROR macro MBA$V_SR_ATTN = 8,16,1,0 %; ! MASSBUS ATTENTION macro MBA$V_SR_MCPE = 8,17,1,0 %; ! MASSBUS COMTROL PARITY ERROR macro MBA$V_SR_NED = 8,18,1,0 %; ! NONEXISTENT DRIVE macro MBA$V_SR_PGE = 8,19,1,0 %; ! PROGRAM ERROR macro MBA$V_SR_CBHUNG = 8,23,1,0 %; ! CB HUNG macro MBA$V_SR_CRD = 8,29,1,0 %; ! CORRECTED READ DATA macro MBA$V_SR_NRCONF = 8,30,1,0 %; ! NO RESPONSE CONFIRMATION macro MBA$V_SR_DTBUSY = 8,31,1,0 %; ! DATA TRANSFER BUSY ! ERROR BITS macro MBA$L_VAR = 12,0,32,1 %; ! VIRTUAL ADDRESS REGISTER macro MBA$L_BCR = 16,0,32,0 %; ! BYTE COUNT REGISTER macro MBA$L_DR = 20,0,32,0 %; ! DIAGNOSTIC REGISTER macro MBA$L_SELMR = 24,0,32,0 %; ! SELECTED MAP REGISTER macro MBA$L_ERB = 1024,0,32,1 %; ! BASE ADDRESS OF EXTERNAL REGISTERS macro MBA$V_ERB_UNIT = 1024,7,3,0 %; literal MBA$S_ERB_UNIT = 3; ! DRIVE UNIT NUMBER macro MBA$L_AS = 1040,0,32,0 %; ! ATTENTION SUMMARY REGISTER ! TO POSITION TO 2048 macro MBA$L_MAP = 2048,0,0,0 %; literal MBA$S_MAP = 1024; ! MAP REGISTERS !*** MODULE $mbr_infodef *** ! ! Ident X-5 ! ! MEM_INFODEF.SDL -- Membership info return structure and membership ! callback mask bits. ! ! Copyright © Digital Equipment Corporation, 1998. ! All rights reserved. ! ! The software contained on this media is proprietary to and ! embodies the confidential technology of Digital Equipment ! Corporation. Possession, use, duplication, or dissemination ! of the software and media is authorized only pursuant to a ! valid written license from Digital Equipment Corporation. ! ! RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure ! by the U.S. Government is subject to restrictions as set ! forth in Subparagraph (c) (1) (ii) of DFARS 252.227-7013, ! or in FAR 52.227-19, as applicable. ! ! -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- ! ! ! Description: This file contains the definition of the values and ! structures needed for the Galaxy get_member_info call ! and the membership callback call. ! ! Environment: OpenVMS Operating System, privileged kernel-mode ! ! Author: Paul Harter ! ! Modifications: ! ! X-5 PKH-G027 Paul K. Harter, Jr. 2-Apr-1998 ! Add constants for membership status values. ! ! X-4 AHM039 Drew Mason 16-Feb-1998 ! Add mask bits for join/leave parameter to membership ! callbacks. ! ! X-3 PKH-G012 Paul K. Harter, Jr. 13-Feb-1998 ! Add node state to return structure. Define constant ! MIREQ$_ALL_NODES for "*" node_id. ! ! X-2 PKH-G009 Paul K. Harter, Jr. 2-Feb-1998 ! Fix alignment of name field. ! ! X-1 PKH-G008 Paul K. Harter, Jr. 2-Feb-1998 ! Initial entry. ! ! Get member information requests literal mireq$_all = 0; literal mireq$_name = 1; literal mireq$_state = 2; literal mireq$_gxy_member = 3; literal mireq$_incarnation = 4; literal mireq$_heartbeat = 5; literal mireq$_time = 6; literal mireq$_too_big = 7; ! galaxy membership status values literal migms$_not_member = 0; literal migms$_member = 1; literal migms$_being_removed = 2; literal migms$_too_big = 3; literal mireq$_all_nodes = -1; ! request for info on all nodes literal minfo$c_length = 48; ! length of mbr_info struct literal minfo$S_mbr_info = 48; macro minfo$l_node_id = 0,0,32,0 %; ! node_id of node described macro minfo$l_state = 4,0,32,0 %; ! current node state from node block macro minfo$l_gxy_member = 8,0,32,0 %; ! galaxy membership status (see above) macro minfo$q_name = 16,0,0,0 %; literal minfo$s_name = 8; ! node's SCS node name macro minfo$q_incarnation = 24,0,0,0 %; literal minfo$s_incarnation = 8; ! incarnation at last join macro minfo$q_heartbeat = 32,0,0,0 %; literal minfo$s_heartbeat = 8; ! node's current heartbeat value macro minfo$q_time = 40,0,0,0 %; literal minfo$s_time = 8; ! time of last join (systime) ! Mask bits for join/leave parameter to membership callbacks. literal glxcbk$m_node_left = 1; ! some node left the Galaxy literal glxcbk$m_node_joined = 2; ! some node joined ! the Galaxy !*** MODULE $MBXDEF *** ! + ! SHARED MEMORY MAILBOX CONTROL BLOCK DEFINITIONS ! ! THERE IS ONE MAILBOX CONTROL BLOCK FOR EACH MAILBOX IN SHARED ! MEMORY. ANY PROCESSOR THAT WANTS TO ACCESS THE MAILBOX CREATES ! A UCB TO CONTROL ACCESS TO THE MAILBOX. ! - literal MBX$M_ALLOC = %X'1'; literal MBX$M_VALID = %X'2'; literal MBX$M_DELPEND = %X'4'; literal MBX$M_QUOTALCK = %X'8'; literal MBX$K_LENGTH = 48; ! LENGTH OF STRUCTURE literal MBX$C_LENGTH = 48; ! LENGTH OF STRUCTURE literal MBX$S_MBXDEF = 48; literal MBX$S_MBX = 48; macro MBX$Q_MSG = 0,0,0,0 %; literal MBX$S_MSG = 8; ! MESSAGE QUEUE LISTHEAD macro MBX$B_FLAGS = 8,0,8,0 %; ! FLAGS macro MBX$V_ALLOC = 8,0,1,0 %; ! MAILBOX ALLOCATED macro MBX$V_VALID = 8,1,1,0 %; ! MAILBOX INITIALIZED AND USEABLE macro MBX$V_DELPEND = 8,2,1,0 %; ! DELETE PENDING macro MBX$V_QUOTALCK = 8,3,1,0 %; ! QUOTA/COUNT MODIFICATION LOCK macro MBX$B_CREATPORT = 9,0,8,0 %; ! PORT NUMBER OF MAILBOX CREATOR macro MBX$W_UNIT = 10,0,16,0 %; ! MAILBOX UNIT NUMBER macro MBX$W_REF = 12,0,16,0 %; ! REFERENCE FLAGS (1 BIT/PORT) macro MBX$W_READER = 14,0,16,0 %; ! WAITING READER (1 BIT/PORT) macro MBX$W_READAST = 16,0,16,0 %; ! WAITING READ AST (1 BIT/PORT) macro MBX$W_WRITAST = 18,0,16,0 %; ! WAITING WRITE AST (1 BIT/PORT) macro MBX$W_MAXMSG = 20,0,16,0 %; ! MAXIMUM MESSAGE SIZE macro MBX$W_MSGCNT = 22,0,16,0 %; ! CURRENT NUMBER OF MESSAGES macro MBX$W_BUFFQUO = 24,0,16,0 %; ! BUFFER QUOTA macro MBX$W_PROT = 26,0,16,0 %; ! PROTECTION MASK macro MBX$L_OWNUIC = 28,0,32,0 %; ! OWNER UIC macro MBX$T_NAME = 32,0,0,0 %; literal MBX$S_NAME = 16; ! MAILBOX NAME (COUNTED STRING) ! *** THE LENGTH OF THIS STRUCTURE MUST BE AN EVEN MULTIPLE OF 8 *** ! *** BECAUSE THE MESSAGE QUEUE HEADER MUST BE QUADWORD ALIGNED *** !*** MODULE $MBOXDEF *** ! + ! - literal MBOX$K_MAX_MSGSIZE = 65535; ! Maximum mailbox message size literal MBOX_MSG$K_LENGTH = 56; ! LENGTH OF STRUCTURE literal MBOX_MSG$C_LENGTH = 56; ! LENGTH OF STRUCTURE literal MBOX_MSG$S_MBOX_MSG = 56; macro MBOX_MSG$PS_addr = 0,0,32,1 %; ! Address of Data in packet macro MBOX_MSG$l_flink = 0,0,32,1 %; ! Message flink for queue write macro MBOX_MSG$PS_uva32 = 4,0,32,1 %; ! Contains BUFIO$K_64 to for use of uva64 macro MBOX_MSG$l_blink = 4,0,32,1 %; ! Message blink for queued write macro MBOX_MSG$w_mbz = 8,0,16,0 %; ! Must be Zero macro MBOX_MSG$b_type = 10,0,8,0 %; ! Block type DYN$C_MISC macro MBOX_MSG$b_subtype = 11,0,8,0 %; ! Block subtype DYN$C_MBX_MSG macro MBOX_MSG$l_function = 12,0,32,0 %; ! Function code macro MBOX_MSG$PQ_uva64 = 16,0,0,1 %; literal MBOX_MSG$s_uva64 = 8; ! 64-bit Address of user buffer macro MBOX_MSG$l_size = 24,0,32,0 %; ! Block size macro MBOX_MSG$l_irp = 28,0,32,1 %; ! IRP macro MBOX_MSG$l_noreaderwaitqfl = 32,0,32,1 %; ! Queue to wait for macro MBOX_MSG$l_noreaderwaitqbl = 36,0,32,1 %; ! macro MBOX_MSG$l_pid = 40,0,32,0 %; ! PID (Will be zero for WRITE IO$M_NOWs) macro MBOX_MSG$l_datastart = 44,0,32,1 %; ! Start of Data in packet macro MBOX_MSG$w_datasize = 48,0,16,0 %; ! Data size macro MBOX_MSG$w_bufquocharge = 50,0,16,0 %; ! BUFQUO charged macro MBOX_MSG$l_thread_pid = 52,0,32,0 %; ! Kernel thread EPID (will be 0 for WRITE IO$M_NOWs) macro MBOX_MSG$R_data = 56,0,0,0 %; ! Data start literal MBOX_BUF$K_LENGTH = 40; ! LENGTH OF STRUCTURE literal MBOX_BUF$C_LENGTH = 40; ! LENGTH OF STRUCTURE literal MBOX_BUF$S_MBOX_BUF = 40; macro MBOX_BUF$PS_addr = 0,0,32,1 %; ! Address of Data in packet macro MBOX_BUF$PS_uva32 = 4,0,32,1 %; ! Contains BUFIO$K_64 to for use of uva64 macro MBOX_BUF$w_mbz = 8,0,16,0 %; ! Must be Zero macro MBOX_BUF$b_type = 10,0,8,0 %; ! Block type DYN$C_MISC macro MBOX_BUF$b_subtype = 11,0,8,0 %; ! Block subtype DYN$C_MBX_MSG macro MBOX_BUF$l_datastart = 12,0,32,1 %; ! Start of Data in packet macro MBOX_BUF$PQ_uva64 = 16,0,0,1 %; literal MBOX_BUF$s_uva64 = 8; ! 64-bit Address of user buffer macro MBOX_BUF$l_size = 24,0,32,0 %; ! Block size macro MBOX_BUF$w_datasize = 28,0,16,0 %; ! Data size macro MBOX_BUF$w_reqsize = 30,0,16,0 %; ! Data size requested macro MBOX_BUF$w_bufquocharge = 32,0,16,0 %; ! BUFQUO charged? macro MBOX_BUF$R_data = 40,0,0,0 %; ! Actual data !*** MODULE MCBDEF IDENT X-2 *** literal MCB$S_MCB = 24; macro MCB$L_FLINK = 0,0,32,1 %; ! Queue forward link macro MCB$L_BLINK = 4,0,32,1 %; ! Queue backward link macro MCB$W_SIZE = 8,0,16,0 %; ! Size of data structure macro MCB$B_TYPE = 10,0,8,0 %; ! Type DYN$C_SM macro MCB$B_SUBTYPE = 11,0,8,0 %; ! Subtype DYN$C_SM_MCB macro MCB$L_VCB = 12,0,32,1 %; ! Address of VCB for mount macro MCB$L_IMCV = 16,0,32,0 %; ! Internal mount context value macro MCB$L_EMCV = 20,0,32,0 %; ! External mount context value literal MCB$S_MCBDEF = 24; ! Old size name, synonym for MCB$S_MCB !*** MODULE $MCHKDEF *** ! + ! MACHINE CHECK ERROR RECOVERY BLOCK MASK BIT DEFFINITIONS ! BITS USED TO FILTER AND TEST FOR ERROR TYPES ! - literal MCHK$M_LOG = %X'1'; literal MCHK$M_MCK = %X'2'; literal MCHK$M_NEXM = %X'4'; literal MCHK$M_SYSLOA = %X'8'; literal MCHK$S_MCHKBITDEF = 1; ! Old size name - synonym literal MCHK$S_MCHKBIT = 1; macro MCHK$V_LOG = 0,0,1,0 %; ! Inhibit error log for the error macro MCHK$V_MCK = 0,1,1,0 %; ! Protect against machine checks macro MCHK$V_NEXM = 0,2,1,0 %; ! Protect against non-existent memory macro MCHK$V_SYSLOA = 0,3,1,0 %; ! Protect against recursive entry to handler ! Offset to state saved on the stack by EXE$MCHECK_PROTECT literal MCHK$K_LEN = 224; ! Length of structure literal MCHK$S_MCHKSAVDEF = 224; ! Old size name - synonym literal MCHK$S_MCHKSAV = 224; macro MCHK$IQ_SAVED_IPL = 0,0,0,0 %; literal MCHK$S_SAVED_IPL = 8; macro MCHK$IQ_SAVED_MASK_SP = 8,0,0,0 %; literal MCHK$S_SAVED_MASK_SP = 8; macro MCHK$IQ_SAVED_R02 = 16,0,0,0 %; literal MCHK$S_SAVED_R02 = 8; macro MCHK$IQ_SAVED_R03 = 24,0,0,0 %; literal MCHK$S_SAVED_R03 = 8; macro MCHK$IQ_SAVED_R04 = 32,0,0,0 %; literal MCHK$S_SAVED_R04 = 8; macro MCHK$IQ_SAVED_R05 = 40,0,0,0 %; literal MCHK$S_SAVED_R05 = 8; macro MCHK$IQ_SAVED_R06 = 48,0,0,0 %; literal MCHK$S_SAVED_R06 = 8; macro MCHK$IQ_SAVED_R07 = 56,0,0,0 %; literal MCHK$S_SAVED_R07 = 8; macro MCHK$IQ_SAVED_R08 = 64,0,0,0 %; literal MCHK$S_SAVED_R08 = 8; macro MCHK$IQ_SAVED_R09 = 72,0,0,0 %; literal MCHK$S_SAVED_R09 = 8; macro MCHK$IQ_SAVED_R10 = 80,0,0,0 %; literal MCHK$S_SAVED_R10 = 8; macro MCHK$IQ_SAVED_R11 = 88,0,0,0 %; literal MCHK$S_SAVED_R11 = 8; macro MCHK$IQ_SAVED_R12 = 96,0,0,0 %; literal MCHK$S_SAVED_R12 = 8; macro MCHK$IQ_SAVED_R13 = 104,0,0,0 %; literal MCHK$S_SAVED_R13 = 8; macro MCHK$IQ_SAVED_R14 = 112,0,0,0 %; literal MCHK$S_SAVED_R14 = 8; macro MCHK$IQ_SAVED_R15 = 120,0,0,0 %; literal MCHK$S_SAVED_R15 = 8; macro MCHK$IQ_SAVED_R16 = 128,0,0,0 %; literal MCHK$S_SAVED_R16 = 8; macro MCHK$IQ_SAVED_R17 = 136,0,0,0 %; literal MCHK$S_SAVED_R17 = 8; macro MCHK$IQ_SAVED_R26 = 144,0,0,0 %; literal MCHK$S_SAVED_R26 = 8; macro MCHK$IQ_SAVED_R29 = 152,0,0,0 %; literal MCHK$S_SAVED_R29 = 8; macro MCHK$IQ_SAVED_F02 = 160,0,0,0 %; literal MCHK$S_SAVED_F02 = 8; macro MCHK$IQ_SAVED_F03 = 168,0,0,0 %; literal MCHK$S_SAVED_F03 = 8; macro MCHK$IQ_SAVED_F04 = 176,0,0,0 %; literal MCHK$S_SAVED_F04 = 8; macro MCHK$IQ_SAVED_F05 = 184,0,0,0 %; literal MCHK$S_SAVED_F05 = 8; macro MCHK$IQ_SAVED_F06 = 192,0,0,0 %; literal MCHK$S_SAVED_F06 = 8; macro MCHK$IQ_SAVED_F07 = 200,0,0,0 %; literal MCHK$S_SAVED_F07 = 8; macro MCHK$IQ_SAVED_F08 = 208,0,0,0 %; literal MCHK$S_SAVED_F08 = 8; macro MCHK$IQ_SAVED_F09 = 216,0,0,0 %; literal MCHK$S_SAVED_F09 = 8; !*** MODULE $MCJDEF *** ! ! Magic Cookie Jar (to contain platform independent mapping IOHANDLES) ! literal MCJ$K_HEADER_LEN = 16; literal MCJ$S_MCJ = 32; macro MCJ$PS_IDB = 0,0,32,1 %; ! back pointer to IDB macro MCJ$L_CRUMB_COUNT = 4,0,32,0 %; ! number of handles MCJ will hold macro MCJ$W_SIZE = 8,0,16,0 %; ! size of MCJ macro MCJ$B_TYPE = 10,0,8,0 %; ! DYN$C_MISC macro MCJ$B_SUBTYPE = 11,0,8,0 %; ! DYN$C_MCJ macro MCJ$Q_COOKIES = 16,0,0,0 %; literal MCJ$S_COOKIES = 16; ! Minimum sized list macro MCJ$Q_ENTRIES = 16,0,0,0 %; literal MCJ$S_ENTRIES = 16; ! minimum sized list (preferred name) literal MCJ$K_LENGTH = 32; !*** MODULE $MFADEF *** ! + ! MFA - MESSAGE FILE ARRAY ! ! There is one Message File Array on any system. The array is a set of ! pointers to message files, both SYSMSG and file used by exec-lets. ! - literal MFA$K_LENGTH = 8; ! Length of MFA header literal MFA$C_LENGTH = 8; ! Length of MFA header literal MFA$S_MFADEF = 12; literal MFA$S_MFA = 12; macro MFA$W_SIZE = 0,0,16,0 %; ! Size of the array in bytes macro MFA$W_FILCNT = 2,0,16,0 %; ! Number of file pointers stored macro MFA$W_BUGCNT = 4,0,16,0 %; ! Count of events that shouldnt happen macro MFA$W_RSRVD = 6,0,16,0 %; ! Reserved, lonword align structure macro MFA$L_PTR_BASE = 8,0,32,0 %; ! Offset to first address !*** MODULE $MGTDEF *** ! ! MGTHDR -- V1 Management header for managed object packets. ! literal MGTHDR$K_ACT_HDR_MAJOR = 1; ! Major Rev. literal MGTHDR$K_ACT_HDR_MINOR = 1; ! Minor Rev. literal MGTHDR$K_RSP_HDR_MAJOR = 1; ! Major Rev. literal MGTHDR$K_RSP_HDR_MINOR = 1; ! Minor Rev. literal MGTHDR$K_REG_REQ_MAJOR = 1; ! Major Rev. literal MGTHDR$K_REG_REQ_MINOR = 2; ! Minor Rev. literal MGTHDR$K_REG_RSP_MAJOR = 1; ! Major Rev. literal MGTHDR$K_REG_RSP_MINOR = 1; ! Minor Rev. literal MGTHDR$K_DEREG_REQ_MAJOR = 1; ! Major Rev. literal MGTHDR$K_DEREG_REQ_MINOR = 1; ! Minor Rev. literal MGTHDR$K_DEREG_RSP_MAJOR = 1; ! Major Rev. literal MGTHDR$K_DEREG_RSP_MINOR = 1; ! Minor Rev. literal MGTHDR$K_RIGHTS_MAJOR = 1; ! Major Rev. literal MGTHDR$K_RIGHTS_MINOR = 1; ! Minor Rev. literal MGTHDR$M_V = %X'1'; literal MGTHDR$M_MORE = %X'2'; literal MGTHDR$M_CONTINUATION = %X'4'; literal MGTHDR$K_BASE_HDR_LENGTH = 16; ! Base Header length literal MGTHDR$C_BASE_HDR_LENGTH = 16; ! Old VAX style length literal MGTHDR$K_ACT_HDR_V1_1_LEN = 24; ! V1.1 Action header length literal MGTHDR$C_ACT_HDR_V1_1_LEN = 24; ! V1.1 Action header length literal MGTHDR$K_ACT_HDR_LEN = 24; ! Action header length literal MGTHDR$C_ACT_HDR_LEN = 24; ! Old VAX style length literal MGTHDR$R_ACT_PAR = 24; ! Beginning of Action parameters block literal MGTHDR$K_ACT_PAR_V1_1_LEN = 0; ! V1.1 Action parameter length literal MGTHDR$C_ACT_PAR_V1_1_LEN = 0; ! V1.1 Action parameter length literal MGTHDR$K_ACT_PAR_LEN = 0; ! Action parameter length literal MGTHDR$C_ACT_PAR_LEN = 0; ! Action parameter length literal MGTHDR$K_ACT_V1_1_LEN = 24; ! V1.1 Action length literal MGTHDR$C_ACT_V1_1_LEN = 24; ! V1.1 Action length literal MGTHDR$K_ACT_LEN = 24; ! Action length literal MGTHDR$C_ACT_LEN = 24; ! Action length literal MGTHDR$K_RSP_HDR_V1_1_LEN = 24; ! V1.1 Response header length literal MGTHDR$C_RSP_HDR_V1_1_LEN = 24; ! V1.1 Response header length literal MGTHDR$K_RSP_HDR_LEN = 24; ! Response header length literal MGTHDR$C_RSP_HDR_LEN = 24; ! Old VAX style length literal MGTHDR$R_RSP_PAR = 24; ! Beginning of Response parameters block literal MGTHDR$K_RSP_PAR_V1_1_LEN = 0; ! V1.1 Response parameter length literal MGTHDR$C_RSP_PAR_V1_1_LEN = 0; ! V1.1 Response parameter length literal MGTHDR$K_RSP_PAR_LEN = 0; ! Response parameter length literal MGTHDR$C_RSP_PAR_LEN = 0; ! Response parameter length literal MGTHDR$K_RSP_V1_1_LEN = 24; ! V1.1 Response length literal MGTHDR$C_RSP_V1_1_LEN = 24; ! V1.1 Response length literal MGTHDR$K_RSP_LEN = 24; ! Response length literal MGTHDR$C_RSP_LEN = 24; ! Response length literal MGTHDR$K_CONT_HDR_V1_1_LEN = 24; ! V1.1 Continuation header length literal MGTHDR$C_CONT_HDR_V1_1_LEN = 24; ! V1.1 Continuation header length literal MGTHDR$K_CONT_HDR_LEN = 24; ! Continuation header length literal MGTHDR$C_CONT_HDR_LEN = 24; ! Old VAX style length literal MGTHDR$R_CONT_PAR = 24; ! Beginning of Continuation parameters block literal MGTHDR$K_CONT_PAR_V1_1_LEN = 0; ! V1.1 Continuation parameter length literal MGTHDR$C_CONT_PAR_V1_1_LEN = 0; ! V1.1 Continuation parameter length literal MGTHDR$K_CONT_PAR_LEN = 0; ! Continuation parameter length literal MGTHDR$C_CONT_PAR_LEN = 0; ! Continuation parameter length literal MGTHDR$K_CONT_V1_1_LEN = 24; ! V1.1 Continuation length literal MGTHDR$C_CONT_V1_1_LEN = 24; ! V1.1 Continuation length literal MGTHDR$K_CONT_LEN = 24; ! Continuation length literal MGTHDR$C_CONT_LEN = 24; ! Continuation length literal MGTHDR$K_EVENT_HDR_V1_1_LEN = 24; ! V1.1 Event header length literal MGTHDR$C_EVENT_HDR_V1_1_LEN = 24; ! V1.1 Event header length literal MGTHDR$K_EVENT_HDR_LEN = 24; ! Event header length literal MGTHDR$C_EVENT_HDR_LEN = 24; ! Old VAX style length literal MGTHDR$R_EVENT_PAR = 24; ! Beginning of Event parameters block literal MGTHDR$K_EVENT_PAR_V1_1_LEN = 0; ! V1.1 Event parameter length literal MGTHDR$C_EVENT_PAR_V1_1_LEN = 0; ! V1.1 Event parameter length literal MGTHDR$K_EVENT_PAR_LEN = 0; ! Event parameter length literal MGTHDR$C_EVENT_PAR_LEN = 0; ! Event parameter length literal MGTHDR$K_EVENT_V1_1_LEN = 24; ! V1.1 Event length literal MGTHDR$C_EVENT_V1_1_LEN = 24; ! V1.1 Event length literal MGTHDR$K_EVENT_LEN = 24; ! Event length literal MGTHDR$C_EVENT_LEN = 24; ! Event length literal MGTHDR$K_DEREG_REQ_HDR_V1_1_LEN = 24; ! V1.1 Deregistration request header length literal MGTHDR$C_DEREG_REQ_HDR_V1_1_LEN = 24; ! V1.1 Deregistration request header length literal MGTHDR$K_DEREG_REQ_HDR_LEN = 24; ! Deregistration request header length literal MGTHDR$C_DEREG_REQ_HDR_LEN = 24; ! Deregistration request header length literal MGTHDR$R_DEREG_REQ_PAR = 24; ! Deregistration request parameters block literal MGTHDR$K_DEREG_REQ_PAR_V1_1_LEN = 0; ! V1.1 Deregistration request parameter length literal MGTHDR$C_DEREG_REQ_PAR_V1_1_LEN = 0; ! V1.1 Deregistration request parameter length literal MGTHDR$K_DEREG_REQ_PAR_LEN = 0; ! Deregistration request parameter length literal MGTHDR$C_DEREG_REQ_PAR_LEN = 0; ! Deregistration request parameter length literal MGTHDR$K_DEREG_REQ_V1_1_LEN = 24; ! V1.1 Deregistration request length literal MGTHDR$C_DEREG_REQ_V1_1_LEN = 24; ! V1.1 Deregistration request length literal MGTHDR$K_DEREG_REQ_LEN = 24; ! Deregistration request length literal MGTHDR$C_DEREG_REQ_LEN = 24; ! Deregistration request length literal MGTHDR$K_DEREG_RSP_HDR_V1_1_LEN = 24; ! V1.1 Deregistration response header length literal MGTHDR$C_DEREG_RSP_HDR_V1_1_LEN = 24; ! V1.1 Deregistration response header length literal MGTHDR$K_DEREG_RSP_HDR_LEN = 24; ! Deregistration response header length literal MGTHDR$C_DEREG_RSP_HDR_LEN = 24; ! Deregistration response header length literal MGTHDR$R_DEREG_RSP_OUTPUT = 24; ! Deregistration response output block literal MGTHDR$K_DEREG_RSP_OUT_V1_1_LEN = 0; ! V1.1 Deregistration response output length literal MGTHDR$C_DEREG_RSP_OUT_V1_1_LEN = 0; ! V1.1 Deregistration response output length literal MGTHDR$K_DEREG_RSP_OUT_LEN = 0; ! Deregistration response output length literal MGTHDR$C_DEREG_RSP_OUT_LEN = 0; ! Deregistration response output length literal MGTHDR$K_DEREG_RSP_V1_1_LEN = 24; ! V1.1 Deregistration response length literal MGTHDR$C_DEREG_RSP_V1_1_LEN = 24; ! V1.1 Deregistration response length literal MGTHDR$K_DEREG_RSP_LEN = 24; ! Deregistration response length literal MGTHDR$C_DEREG_RSP_LEN = 24; ! Deregistration response length literal MGTHDR$K_RIGHTS_HDR_V1_1_LEN = 24; ! V1.1 Access Rights header length literal MGTHDR$C_RIGHTS_HDR_V1_1_LEN = 24; ! V1.1 Access Rights header length literal MGTHDR$K_RIGHTS_HDR_LEN = 24; ! Access Rights header length literal MGTHDR$C_RIGHTS_HDR_LEN = 24; ! Access Rights header length literal MGTHDR$R_RIGHTS_PAR = 24; ! Access Rights parameters block literal MGTHDR$M_READ_ACCESS = %X'1'; literal MGTHDR$M_WRITE_ACCESS = %X'2'; literal MGTHDR$M_CONTROL_ACCESS = %X'4'; literal MGTHDR$K_RIGHTS_PAR_V1_1_LEN = 8; ! V1.1 Access Rights parameter length literal MGTHDR$C_RIGHTS_PAR_V1_1_LEN = 8; ! V1.1 Access Rights parameter length literal MGTHDR$K_RIGHTS_PAR_LEN = 8; ! Access Rights parameter length literal MGTHDR$C_RIGHTS_PAR_LEN = 8; ! Access Rights parameter length literal MGTHDR$K_RIGHTS_V1_1_LEN = 32; ! V1.1 Access Rights length literal MGTHDR$C_RIGHTS_V1_1_LEN = 32; ! V1.1 Access Rights length literal MGTHDR$K_RIGHTS_LEN = 32; ! Access Rights length literal MGTHDR$C_RIGHTS_LEN = 32; ! Access Rights length literal MGTHDR$K_REG_REQ_HDR_V1_1_LEN = 24; ! V1.1 Registration request header length literal MGTHDR$C_REG_REQ_HDR_V1_1_LEN = 24; ! V1.1 Registration request header length literal MGTHDR$K_REG_REQ_HDR_V1_2_LEN = 24; ! V1.2 Registration request header length literal MGTHDR$C_REG_REQ_HDR_V1_2_LEN = 24; ! V1.2 Registration request header length literal MGTHDR$K_REG_REQ_HDR_LEN = 24; ! Registration request header length literal MGTHDR$C_REG_REQ_HDR_LEN = 24; ! Registration request header length literal MGTHDR$R_REG_REQ_PAR = 24; ! Registration request parameters block literal MGTHDR$K_REG_REQ_PAR_V1_1_LEN = 56; ! V1.1 Registration request parameter length literal MGTHDR$C_REG_REQ_PAR_V1_1_LEN = 56; ! V1.1 Registration request parameter length literal MGTHDR$K_REG_REQ_PAR_V1_2_LEN = 56; ! V1.1 Registration request parameter length literal MGTHDR$C_REG_REQ_PAR_V1_2_LEN = 56; ! V1.1 Registration request parameter length literal MGTHDR$K_REG_REQ_PAR_LEN = 56; ! Registration request parameter length literal MGTHDR$C_REG_REQ_PAR_LEN = 56; ! Registration request parameter length literal MGTHDR$K_REG_REQ_V1_1_LEN = 80; ! V1.1 Registration request length literal MGTHDR$C_REG_REQ_V1_1_LEN = 80; ! V1.1 Registration request length literal MGTHDR$K_REG_REQ_V1_2_LEN = 80; ! V1.1 Registration request length literal MGTHDR$C_REG_REQ_V1_2_LEN = 80; ! V1.1 Registration request length literal MGTHDR$K_REG_REQ_LEN = 80; ! Registration request length literal MGTHDR$C_REG_REQ_LEN = 80; ! Registration request length literal MGTHDR$K_REG_RSP_HDR_V1_1_LEN = 24; ! V1.1 Registration response header length literal MGTHDR$C_REG_RSP_HDR_V1_1_LEN = 24; ! V1.1 Registration response header length literal MGTHDR$K_REG_RSP_HDR_LEN = 24; ! Registration response header length literal MGTHDR$C_REG_RSP_HDR_LEN = 24; ! Registration response header length literal MGTHDR$R_REG_RSP_OUTPUT = 24; ! Registration response output block literal MGTHDR$K_REG_RSP_OUT_V1_1_LEN = 16; ! V1.1 Registration response output length literal MGTHDR$C_REG_RSP_OUT_V1_1_LEN = 16; ! V1.1 Registration response output length literal MGTHDR$K_REG_RSP_OUT_LEN = 16; ! Registration response output length literal MGTHDR$C_REG_RSP_OUT_LEN = 16; ! Registration response output length literal MGTHDR$K_REG_RSP_V1_1_LEN = 40; ! V1.1 Registration response length literal MGTHDR$C_REG_RSP_V1_1_LEN = 40; ! V1.1 Registration response length literal MGTHDR$K_REG_RSP_LEN = 40; ! Registration response length literal MGTHDR$C_REG_RSP_LEN = 40; ! Registration response length literal MGTHDR$S_MGTHDR = 80; macro MGTHDR$B_HDR_LEN = 0,0,8,0 %; ! Header Len in bytes macro MGTHDR$V_HDR_LEN_QW = 0,3,5,0 %; literal MGTHDR$S_HDR_LEN_QW = 5; ! Length of data header in quadwords ! Also offset to object specific data macro MGTHDR$B_FLAGS = 1,0,8,0 %; ! Header flags macro MGTHDR$V_V = 1,0,1,0 %; ! Data Header is valid macro MGTHDR$V_MORE = 1,1,1,0 %; ! Another mgt data header follows macro MGTHDR$V_CONTINUATION = 1,2,1,0 %; ! Header for continuation data follows macro MGTHDR$V_FLAGS_MBZ = 1,3,5,0 %; literal MGTHDR$S_FLAGS_MBZ = 5; macro MGTHDR$B_HDR_MINOR = 2,0,8,0 %; ! Header Minor Revision macro MGTHDR$B_HDR_MAJOR = 3,0,8,0 %; ! Header Major Revision macro MGTHDR$B_MGT_FUNC = 4,0,8,0 %; ! Record type code: ! (see MGT_FUNC constant section for codes) macro MGTHDR$B_RSP_STATUS = 5,0,8,0 %; ! Action: SBZ ! Response: status of performing action. macro MGTHDR$W_PAR_LEN = 6,0,16,0 %; ! Total length of REC_TYP records following macro MGTHDR$L_OBJ_HANDLE = 8,0,32,0 %; ! Registration Handle of destination MO macro MGTHDR$L_SRC_OBJ_HANDLE = 12,0,32,0 %; ! Registration Handle of source MO ! Action, Response, and info Headers macro MGTHDR$B_ACTION = 16,0,8,0 %; ! Managed Object action codes ! (see ACTION constant section for codes) macro MGTHDR$B_NUM_PAR_RECS = 17,0,8,0 %; ! Number of Parameter Records macro MGTHDR$B_PAR_MINOR = 18,0,8,0 %; ! Minor Rev. of object specific params. macro MGTHDR$B_PAR_MAJOR = 19,0,8,0 %; ! Major Rev. of object specific action_params. macro MGTHDR$L_ACTION_SEQ = 20,0,32,0 %; ! Mgt station assigned action sequence number macro MGTHDR$L_ACTION_CTX = 20,0,32,0 %; ! Mgt station assigned action context ! the time that a structure has a member, it is defined ! before the structures that have members so that the ! "." operand has the right value. macro MGTHDR$L_ACCESS_RIGHTS = 24,0,32,0 %; ! Security access rights of the requestor macro MGTHDR$V_READ_ACCESS = 24,0,1,0 %; ! Able to request monitoring data macro MGTHDR$V_WRITE_ACCESS = 24,1,1,0 %; ! Able to request execution of fixes macro MGTHDR$V_CONTROL_ACCESS = 24,2,1,0 %; ! Able to configure/change Managed Object macro MGTHDR$L_SRC_OBJ_TYPE = 28,0,32,0 %; ! Source Object type ! (see SRC_OBJ_TYPE constant section for codes) macro MGTHDR$T_OBJ_NAME = 24,0,0,0 %; literal MGTHDR$S_OBJ_NAME = 32; ! Node unique ASCIZ obj name macro MGTHDR$B_OBJ_MINOR = 56,0,8,0 %; ! Managed Object minor version macro MGTHDR$B_OBJ_MAJOR = 57,0,8,0 %; ! Managed Object major version ! Kernel Mode objects: macro MGTHDR$Q_ACTION_ADDR = 64,0,0,0 %; literal MGTHDR$S_ACTION_ADDR = 8; ! $MGT_ACTION routine for ! kernel mode objects macro MGTHDR$Q_REQ_CTX = 72,0,0,0 %; literal MGTHDR$S_REQ_CTX = 8; ! Request context value ! Process objects: ! MGT_AST information for process mode objects macro MGTHDR$L_AST_EPID = 64,0,32,0 %; ! EPID for ASTs macro MGTHDR$L_AST_RSVD = 68,0,32,0 %; ! Reserved for quadword alignment ! Process Data Analyzers: ! DA_AST information for process mode data analyzers macro MGTHDR$L_DA_AST_EPID = 64,0,32,0 %; ! EPID for ASTs macro MGTHDR$L_DA_AST_RSVD = 68,0,32,0 %; ! Reserved for quadword alignment macro MGTHDR$T_DA_PASSWORD = 72,0,0,0 %; literal MGTHDR$S_DA_PASSWORD = 8; ! AM Password macro MGTHDR$B_RM_OBJ_MINOR = 24,0,8,0 %; ! RMDriver's minor version macro MGTHDR$B_RM_OBJ_MAJOR = 25,0,8,0 %; ! RMDriver's major version ! Kernel Mode objects: macro MGTHDR$A_RM_MGT_ACTION_ADDR = 32,0,0,0 %; literal MGTHDR$S_RM_MGT_ACTION_ADDR = 8; ! RMDriver's Management Action routine ! kernel mode objects ! ! MGTHDRV2 -- V2 Management header for managed object packets. ! literal MGTHDRV2$K_REQ_HDR_MAJOR = 2; ! Major Rev. literal MGTHDRV2$K_REQ_HDR_MINOR = 1; ! Minor Rev. literal MGTHDRV2$K_RSP_HDR_MAJOR = 2; ! Major Rev. literal MGTHDRV2$K_RSP_HDR_MINOR = 1; ! Minor Rev. literal MGTHDRV2$K_CONT_HDR_MAJOR = 2; ! Major Rev. literal MGTHDRV2$K_CONT_HDR_MINOR = 1; ! Minor Rev. literal MGTHDRV2$K_EVENT_HDR_MAJOR = 2; ! Major Rev. literal MGTHDRV2$K_EVENT_HDR_MINOR = 1; ! Minor Rev. literal MGTHDRV2$K_RIGHTS_HDR_MAJOR = 2; ! Major Rev. literal MGTHDRV2$K_RIGHTS_HDR_MINOR = 1; ! Minor Rev. literal MGTHDRV2$K_CTX_HDR_MAJOR = 2; ! Major Rev. literal MGTHDRV2$K_CTX_HDR_MINOR = 1; ! Minor Rev. literal MGTHDRV2$K_EOD_HDR_MAJOR = 2; ! Major Rev. literal MGTHDRV2$K_EOD_HDR_MINOR = 1; ! Minor Rev. literal MGTHDRV2$K_OBJ_NAME_LEN = 32; literal MGTHDRV2$C_OBJ_NAME_LEN = 32; literal MGTHDRV2$M_V = %X'1'; literal MGTHDRV2$M_MORE = %X'2'; literal MGTHDRV2$M_CONTINUATION = %X'4'; literal MGTHDRV2$M_CONTEXT = %X'8'; literal MGTHDRV2$M_EOD = %X'10'; literal MGTHDRV2$K_MINI_HDR_V2_1_LENGTH = 8; ! V2.1 Mini-Header length literal MGTHDRV2$C_MINI_HDR_V2_1_LENGTH = 8; ! V2.1 Old VAX style length literal MGTHDRV2$K_MINI_HDR_LENGTH = 8; ! Mini-Header length literal MGTHDRV2$C_MINI_HDR_LENGTH = 8; ! Old VAX style length literal MGTHDRV2$K_EOD_HDR_V2_1_LEN = 8; ! V2.1 EOD header length literal MGTHDRV2$C_EOD_HDR_V2_1_LEN = 8; ! V2.1 Old VAX EOD header length literal MGTHDRV2$K_EOD_HDR_LEN = 8; ! EOD header length literal MGTHDRV2$C_EOD_HDR_LEN = 8; ! EOD header Old VAX style length literal MGTHDRV2$K_BASE_HDR_V2_1_LENGTH = 16; ! V2.1 Base Header length literal MGTHDRV2$C_BASE_HDR_V2_1_LENGTH = 16; ! V2.1 Old VAX style length literal MGTHDRV2$K_BASE_HDR_LENGTH = 16; ! Base Header length literal MGTHDRV2$C_BASE_HDR_LENGTH = 16; ! Old VAX style length literal MGTHDRV2$K_ACT_HDR_V2_1_LEN = 24; ! V2.1 Action header length literal MGTHDRV2$C_ACT_HDR_V2_1_LEN = 24; ! V2.1 Action header length literal MGTHDRV2$K_ACT_HDR_LEN = 24; ! Action header length literal MGTHDRV2$C_ACT_HDR_LEN = 24; ! Old VAX style length literal MGTHDRV2$R_ACT_PAR = 24; ! Beginning of Action parameters block literal MGTHDRV2$K_RSP_HDR_V2_1_LEN = 24; ! V2.1 Response header length literal MGTHDRV2$C_RSP_HDR_V2_1_LEN = 24; ! V2.1 Response header length literal MGTHDRV2$K_RSP_HDR_LEN = 24; ! Response header length literal MGTHDRV2$C_RSP_HDR_LEN = 24; ! Old VAX style length literal MGTHDRV2$R_RSP_PAR = 24; ! Beginning of Response parameters block literal MGTHDRV2$K_CONT_HDR_V2_1_LEN = 24; ! V2.1 Continuation header length literal MGTHDRV2$C_CONT_HDR_V2_1_LEN = 24; ! V2.1 Continuation header length literal MGTHDRV2$K_CONT_HDR_LEN = 24; ! Continuation header length literal MGTHDRV2$C_CONT_HDR_LEN = 24; ! Old VAX style length literal MGTHDRV2$R_CONT_PAR = 24; ! Beginning of Continuation parameters block literal MGTHDRV2$K_EVENT_HDR_V2_1_LEN = 24; ! V2.1 Event header length literal MGTHDRV2$C_EVENT_HDR_V2_1_LEN = 24; ! V2.1 Event header length literal MGTHDRV2$K_EVENT_HDR_LEN = 24; ! Event header length literal MGTHDRV2$C_EVENT_HDR_LEN = 24; ! Old VAX style length literal MGTHDRV2$R_EVENT_PAR = 24; ! Beginning of Event parameters block literal MGTHDRV2$K_RIGHTS_HDR_V2_1_LEN = 24; ! V2.1 Access Rights header length literal MGTHDRV2$C_RIGHTS_HDR_V2_1_LEN = 24; ! V2.1 Access Rights header length literal MGTHDRV2$K_RIGHTS_HDR_LEN = 24; ! Access Rights header length literal MGTHDRV2$C_RIGHTS_HDR_LEN = 24; ! Access Rights header length literal MGTHDRV2$R_RIGHTS_PAR = 24; ! Access Rights parameters block literal MGTHDRV2$K_REG_REQ_HDR_V2_1_LEN = 24; ! V2.1 Registration request header length literal MGTHDRV2$C_REG_REQ_HDR_V2_1_LEN = 24; ! V2.1 Registration request header length literal MGTHDRV2$K_REG_REQ_HDR_V2_2_LEN = 24; ! V2.1 Registration request header length literal MGTHDRV2$C_REG_REQ_HDR_V2_2_LEN = 24; ! V2.1 Registration request header length literal MGTHDRV2$K_REG_REQ_HDR_LEN = 24; ! Registration request header length literal MGTHDRV2$C_REG_REQ_HDR_LEN = 24; ! Registration request header length literal MGTHDRV2$R_REG_REQ_PAR = 24; ! Registration request parameters block literal MGTHDRV2$K_REG_RSP_HDR_V2_1_LEN = 24; ! V2.1 Registration response header length literal MGTHDRV2$C_REG_RSP_HDR_V2_1_LEN = 24; ! V2.1 Registration response header length literal MGTHDRV2$K_REG_RSP_HDR_LEN = 24; ! Registration response header length literal MGTHDRV2$C_REG_RSP_HDR_LEN = 24; ! Registration response header length literal MGTHDRV2$R_REG_RSP_PAR = 24; ! Registration response output block literal MGTHDRV2$S_MGTHDRV2 = 24; macro MGTHDRV2$B_HDR_LEN = 0,0,8,0 %; ! Header Len in bytes macro MGTHDRV2$V_HDR_LEN_QW = 0,3,5,0 %; literal MGTHDRV2$S_HDR_LEN_QW = 5; ! Length of data header in quadwords ! Also offset to object specific data macro MGTHDRV2$B_FLAGS = 1,0,8,0 %; ! Header flags macro MGTHDRV2$V_V = 1,0,1,0 %; ! Data Header is valid macro MGTHDRV2$V_MORE = 1,1,1,0 %; ! Another mgt data header follows macro MGTHDRV2$V_CONTINUATION = 1,2,1,0 %; ! Header for continuation data follows ! Flags defined for V2.1 headers macro MGTHDRV2$V_CONTEXT = 1,3,1,0 %; ! Header for context data follows macro MGTHDRV2$V_EOD = 1,4,1,0 %; ! Mini-header for EOD record follows macro MGTHDRV2$B_HDR_MINOR = 2,0,8,0 %; ! Header Minor Revision macro MGTHDRV2$B_HDR_MAJOR = 3,0,8,0 %; ! Header Major Revision macro MGTHDRV2$B_MGT_FUNC = 4,0,8,0 %; ! Record type code: ! (see MGT_FUNC constant section for codes) macro MGTHDRV2$B_RSP_STATUS = 5,0,8,0 %; ! Action: SBZ ! Response: status of performing action. macro MGTHDRV2$W_PAR_LEN = 6,0,16,0 %; ! Total length of REC_TYP records following in quadwords macro MGTHDRV2$L_OBJ_HANDLE = 8,0,32,0 %; ! Registration Handle of destination MO macro MGTHDRV2$L_SRC_OBJ_HANDLE = 12,0,32,0 %; ! Registration Handle of source MO ! Action, Response, and info Headers macro MGTHDRV2$B_ACTION = 16,0,8,0 %; ! Managed Object action codes ! (see ACTION constant section for codes) macro MGTHDRV2$B_NUM_PAR_RECS = 17,0,8,0 %; ! Number of Parameter Records macro MGTHDRV2$B_PAR_MINOR = 18,0,8,0 %; ! Minor Rev. of object specific params. macro MGTHDRV2$B_PAR_MAJOR = 19,0,8,0 %; ! Major Rev. of object specific action_params. macro MGTHDRV2$L_ACTION_SEQ = 20,0,32,0 %; ! Mgt station assigned action sequence number macro MGTHDRV2$L_ACTION_CTX = 20,0,32,0 %; ! Mgt station assigned action context ! the time that a structure has a member, it is defined ! before the structures that have members so that the ! "." operand has the right value. ! ! MGT_FUNC constant section ! literal MGTHDR$K_REC_TYPE_RESERVED = 0; ! 0 - Keep reserved to detect failure to fill in field literal MGTHDR$K_REC_TYPE_ACT_REQ = 1; ! 1 - Request to act on managed object literal MGTHDR$K_REC_TYPE_ACT_RSP = 2; ! 2 - Response to ACT_REQ request literal MGTHDR$K_REC_TYPE_ACT_CONT = 3; ! 3 - Continuation info for preceeding action or response record literal MGTHDR$K_REC_TYPE_EVENT = 4; ! 4 - Unsolicited event notification literal MGTHDR$K_REC_TYPE_ACCESS_RIGHTS = 5; ! 5 - Requestor access rights ! End of codes defined in the MGTHDR V1.1 timeframe literal MGTHDR$K_REC_TYPE_ACT_CTX = 6; ! 6 - Context info for request literal MGTHDR$K_REC_TYPE_EOD = 7; ! 7 - End of data (uses mini-header only) literal MGTHDR$K_REC_TYPE_FIRST_UNUSED = 8; ! Insert new constants ahead of this one literal MGTHDR$K_REC_TYPE_FIRST_CODE = 0; ! First Management record type literal MGTHDR$K_REC_TYPE_V1_1_LASTCODE = 5; ! Last Management record type for V1.1 headers literal MGTHDR$K_REC_TYPE_LAST_CODE = 7; ! Last Management record type ! ! ACTION constant section ! ! RMDriver request codes for all other Managed Objects to process literal MOACT$K_MO_RESERVED = 0; ! 0 - Keep reserved to detect failure to fill in field ! Last 15 codes are common between all Managed Objects ! RMDriver request codes for all other Managed Objects to process literal MOACT$K_MO_DRIVER_STOPPED = 241; ! 241 - RMDriver has been stopped (informational) literal MOACT$K_MO_DRIVER_STARTED = 242; ! 242 - RMDriver has been (re)started (informational) ! End of codes defined in the MGTHDR V1.1 timeframe ! NOTE! Can not have more than MO_num_common_codes entries! literal MOACT$K_MO_FIRST_CODE = 0; ! First MO action code literal MOACT$K_MO_FIRST_COMMON_CODE = 241; ! First MO common action code literal MOACT$K_MO_NUM_COMMON_CODES = 15; ! Number of MO common action codes ! ! SRC_OBJ_TYPE constant section ! literal RMOBJ$K_RESERVED = 0; ! Reserved for error checking literal RMOBJ$K_RMDRIVER = 1; ! RMDRIVER itself literal RMOBJ$K_KERNEL_MO = 2; ! Kernel-mode Managed Object literal RMOBJ$K_USER_MO = 3; ! User-mode Managed Object literal RMOBJ$K_NETWORK_DA = 4; ! Network Data Analyzer literal RMOBJ$K_LOCAL_DA = 5; ! Local Data Analyzer ! End of codes defined in the MGTHDR V1.1 timeframe literal RMOBJ$K_FIRST_UNUSED = 6; ! Insert new constants ahead of this one literal RMOBJ$K_FIRST_OBJ_TYPE = 0; literal RMOBJ$K_V1_1_LAST_OBJ_TYPE = 5; literal RMOBJ$K_LAST_OBJ_TYPE = 5; literal RMOBJ$K_NUM_OBJ_TYPES = 6; ! ! Standard Management function request and response data ! ! As of V2 of the Management Headers, the request and response data ! fields will be based off of the start of the parameter section, and ! not the beginning of the Management Header. ! ! ! Access rights parameter section ! literal MGTRTSV2$M_READ_ACCESS = %X'1'; literal MGTRTSV2$M_WRITE_ACCESS = %X'2'; literal MGTRTSV2$M_CONTROL_ACCESS = %X'4'; literal MGTRTSV2$K_RIGHTS_PAR_V2_1_LEN = 8; ! V2.1 Access Rights parameter length literal MGTRTSV2$C_RIGHTS_PAR_V2_1_LEN = 8; ! V2.1 Access Rights parameter length literal MGTRTSV2$K_RIGHTS_PAR_LEN = 8; ! Access Rights parameter length literal MGTRTSV2$C_RIGHTS_PAR_LEN = 8; ! Access Rights parameter length literal MGTRTSV2$S_MGTRTSV2 = 8; macro MGTRTSV2$L_ACCESS_RIGHTS = 0,0,32,0 %; ! Security access rights of the requestor macro MGTRTSV2$V_READ_ACCESS = 0,0,1,0 %; ! Able to request monitoring data macro MGTRTSV2$V_WRITE_ACCESS = 0,1,1,0 %; ! Able to request execution of fixes macro MGTRTSV2$V_CONTROL_ACCESS = 0,2,1,0 %; ! Able to configure/change Managed Object macro MGTRTSV2$L_SRC_OBJ_TYPE = 4,0,32,0 %; ! Source Object type ! (see SRC_OBJ_TYPE constant section for codes) ! ! RMDAT -- RMDRIVER Managed Object and driver data for local Data Analyzers, etc. ! literal RMDAT$K_PAR_VER_MAJOR = 1; ! Minor Rev. literal RMDAT$K_PAR_VER_MINOR = 1; ! Major Rev. literal RMDAT$K_PAR_V1_1_LEN = 8; ! V1.1 RMDRIVER data parameter length literal RMDAT$C_PAR_V1_1_LEN = 8; ! V1.1 RMDRIVER data parameter length literal RMDAT$K_PAR_LEN = 8; ! RMDRIVER data parameter length literal RMDAT$C_PAR_LEN = 8; ! RMDRIVER data parameter length literal RMDAT$S_RMDAT = 8; macro RMDAT$L_OBJ_HANDLE = 0,0,32,0 %; ! RMDRIVER's Managed Object registration macro RMDAT$B_OBJ_MINOR = 4,0,8,0 %; ! RMDRIVER's Managed Object minor version macro RMDAT$B_OBJ_MAJOR = 5,0,8,0 %; ! RMDRIVER's Managed Object major version macro RMDAT$W_CAP_VER = 6,0,16,0 %; ! RMDRIVER's capability version ! ! Managed Object Registration parameter structures ! ! The next two structures are used by the MGT$REGISTER_KERNEL_MO ! One is for the input data to the routine, and the other is the ! output data from the routine. ! literal MGTKRREQ$K_OBJ_NAME_LEN = 32; literal MGTKRREQ$K_OBJ_HDR_VER_MAX = 8; ! Number of header versions ! handled by the Managed Object literal MGTKRREQ$K_V1_1_DATA_LEN = 72; ! Reg req data length literal MGTKRREQ$C_V1_1_DATA_LEN = 72; ! Old VAX style length literal MGTKRREQ$S_MGTKRREQ = 72; macro MGTKRREQ$T_OBJ_NAME = 0,0,0,0 %; literal MGTKRREQ$S_OBJ_NAME = 32; ! Node unique ASCIZ obj name macro MGTKRREQ$B_OBJ_MINOR = 32,0,8,0 %; ! Managed Object minor version macro MGTKRREQ$B_OBJ_MAJOR = 33,0,8,0 %; ! Managed Object major version ! Length to make quadword multiple macro MGTKRREQ$W_OBJ_HDR_VER = 40,0,0,0 %; literal MGTKRREQ$S_OBJ_HDR_VER = 16; ! Array of header versions handled ! by Managed Object, terminated ! by 0x0000 ! Kernel Mode objects on 64-bit processors: macro MGTKRREQ$Q_ACTION_ADDR = 56,0,0,0 %; literal MGTKRREQ$S_ACTION_ADDR = 8; ! $MGT_ACTION routine for ! kernel mode Managed Objects macro MGTKRREQ$Q_REQ_CTX = 64,0,0,0 %; literal MGTKRREQ$S_REQ_CTX = 8; ! Request context value ! Kernel Mode objects on 32-bit processors: macro MGTKRREQ$L_ACTION_ADDR = 56,0,32,0 %; ! $MGT_ACTION routine for ! kernel mode Managed Objects macro MGTKRREQ$L_ACTION_ADDR_RSVD = 60,0,32,0 %; ! Keep same spacing as QW structure macro MGTKRREQ$L_REQ_CTX = 64,0,32,0 %; ! Request context value macro MGTKRREQ$L_REQ_CTX_RSVD = 68,0,32,0 %; ! Keep same spacing as QW structure literal MGTKRRSP$K_V1_1_DATA_LEN = 32; ! Reg rsp data length literal MGTKRRSP$C_V1_1_DATA_LEN = 32; ! Old VAX style length literal MGTKRRSP$S_MGTKRRSP = 32; macro MGTKRRSP$B_RM_OBJ_MINOR = 0,0,8,0 %; ! RMDriver's Managed Object minor version macro MGTKRRSP$B_RM_OBJ_MAJOR = 1,0,8,0 %; ! RMDriver's Managed Object major version macro MGTKRRSP$Q_RM_SEC_TOKEN = 8,0,0,0 %; literal MGTKRRSP$S_RM_SEC_TOKEN = 8; ! Security token for accessing RMDriver functions ! Kernel Mode objects on 64-bit processors: macro MGTKRRSP$Q_ACTION_ADDR = 16,0,0,0 %; literal MGTKRRSP$S_ACTION_ADDR = 8; ! RMDriver's $MGT_ACTION routine ! for kernel mode objects ! Kernel Mode objects on 32-bit processors: macro MGTKRRSP$L_ACTION_ADDR = 16,0,32,0 %; ! RMDriver's $MGT_ACTION routine ! for kernel mode objects macro MGTKRRSP$L_ACTION_ADDR_RSVD = 20,0,32,0 %; ! Keep same spacing as QW structure macro MGTKRRSP$L_OBJ_HANDLE = 24,0,32,0 %; ! Newly assigned Managed Object handle macro MGTKRRSP$L_RM_OBJ_HANDLE = 28,0,32,0 %; ! RMDriver's Managed Object handle ! ! Management common error codes ! Note: Managed Object specific codes start at 128 (MGT$K_STS_FIRST_PRIVATE_CODE) ! literal MGT$K_STS_RESERVED = 0; ! Detect if this field has been set literal MGT$K_STS_SUCCESS = 1; ! Make equal to SS$_NORMAL literal MGT$K_STS_HDR_NOT_ALIGNED = 2; ! Request or response buffer not quadword aligned literal MGT$K_STS_HDR_NOT_VALID = 3; ! Management header not valid literal MGT$K_STS_HDR_INCOMPAT = 4; ! Incompatible header version literal MGT$K_STS_PAR_INCOMPAT = 5; ! Incompatible parameter version literal MGT$K_STS_PAR_INVALID = 6; ! Invalid parameter(s) literal MGT$K_STS_RSP_NO_ROOM = 7; ! No room in response buffer literal MGT$K_STS_RSP_NOSAMEBUF = 8; ! Using request buffer for response buffer is not implemented literal MGT$K_STS_RSP_RSVD2 = 9; ! Reserved response buffer error literal MGT$K_STS_REQ_NO_ROOM = 10; ! No room in request buffer to quadword-align request literal MGT$K_STS_REQ_ACT_INVALID = 11; ! Management Request action code is invalid (out of range) literal MGT$K_STS_REQ_ILLEGAL_DEST = 12; ! Management Request for destination MO is illegal literal MGT$K_STS_REQ_RESERVED_DEST = 13; ! Management Request for destination MO is reserved literal MGT$K_STS_REQ_UNIMPLEMENTED = 14; ! Management Request action code is not implemented literal MGT$K_STS_REQ_NOPRIV = 15; ! No privilege to execute Management Request literal MGT$K_STS_REQ_INVALID_PAR_LEN = 16; ! Management Request parameter length invalid for particular action literal MGT$K_STS_REQ_INVALID_PAR_RECS = 17; ! Management Request invalid number of parameter records literal MGT$K_STS_REQ_RSVD1 = 18; ! Reserved request buffer error literal MGT$K_STS_REQ_RSVD2 = 19; ! Reserved request buffer error literal MGT$K_STS_REQ_RSVD3 = 20; ! Reserved request buffer error literal MGT$K_STS_REQ_RSVD4 = 21; ! Reserved request buffer error literal MGT$K_STS_OBJ_HANDLE_INVALID = 22; ! Managed Object handle is not valid literal MGT$K_STS_OBJ_HANDLE_NOTFOUND = 23; ! Managed Object handle is not in the registration database literal MGT$K_STS_OBJ_HANDLE_STALE = 24; ! Managed Object has reregistered, giving it a new object handle literal MGT$K_STS_OBJ_HANDLE_UPDATED = 25; ! Managed Object just reregistered, updating the handle (success status) literal MGT$K_STS_OBJ_HANDLE_RSVD1 = 26; ! Reserved object handle error literal MGT$K_STS_OBJ_TYPE_INVALID = 27; ! Managed Object type is not valid (out of range) literal MGT$K_STS_OBJ_TYPE_RESERVED = 28; ! Managed Object type is reserved literal MGT$K_STS_OBJ_TYPE_RSVD1 = 29; ! Managed Object type error literal MGT$K_STS_OBJ_TYPE_RSVD2 = 30; ! Managed Object type error literal MGT$K_STS_OBJ_TYPE_RSVD3 = 31; ! Managed Object type error literal MGT$K_STS_OBJ_TYPE_RSVD4 = 32; ! Managed Object type error literal MGT$K_STS_CONT_INVALIDADD = 33; ! Adding a continuation header to a Mgt packet set with a context header literal MGT$K_STS_CONT_INVALIDATT = 34; ! Attaching a continuation packet to a Mgt packet set with a context header literal MGT$K_STS_CONT_INVALIDADR = 35; ! Continuation packet address given for attach is not in at the end of the MO packet set literal MGT$K_STS_CONT_INVALIDHDR = 36; ! Continuation header at the given address is not valid literal MGT$K_STS_CONT_RSVD1 = 37; ! Reserved cont header error literal MGT$K_STS_CONT_RSVD2 = 38; ! Reserved cont header error literal MGT$K_STS_CONT_DATA_INVALIDCOPY = 39; ! Continuation data packet already found for dest MO packet set literal MGT$K_STS_CONT_DATA_INVALIDREPL = 40; ! Continuation data packet doesn't exist for dest MO packet set literal MGT$K_STS_CONT_DATA_BADFORMAT = 41; ! Continuation data format is invalid literal MGT$K_STS_CONT_DATA_INVALID = 42; ! Continuation data value(s) is/are not valid ! ! The next three statuses indicate the result of trying to continue ! a data request. Basically, here is how the statuses relate ! to one another: ! ! STS_SUCCESS Continuation succeeded ! STS_CONT_DATA_CTX_FOUND_W Continuation continued with a warning ! STS_CONT_DATA_CTX_FOUND_E Continuation continued with an error ! STS_CONT_DATA_CTX_NOT_FND Continuation failed ! literal MGT$K_STS_CONT_DATA_CTX_FOUND_W = 43; ! Context for using this continuation data has changed, but ! the place to continue the data collection has been found ! with some certainty. This is a "warning"-level status. ! This warning status would signal to the data collector of ! the possibility of these data collection irregularities. ! It is up to the data collector whether to continue this ! data collection or start a new one. literal MGT$K_STS_CONT_DATA_CTX_FOUND_E = 44; ! Context for using this continuation data has changed, but ! the place to continue the data collection is a last-ditch ! effort. This is an "error"-level status. ! This error status would signal to the data collector that ! there is possibility of these data collection irregularities. ! It is up to the data collector whether to continue this ! data collection or start a new one. literal MGT$K_STS_CONT_DATA_CTX_NOT_FND = 45; ! Context for using this continuation data is no longer valid, ! and cannot be recovered. A new request must be started ! to collect data. This is a "fatal error"-level status. literal MGT$K_STS_CONT_DATA_RSVD1 = 46; ! Continuation data error literal MGT$K_STS_CONT_DATA_RSVD2 = 47; ! Continuation data error literal MGT$K_STS_CONT_DATA_RSVD3 = 48; ! Continuation data error literal MGT$K_STS_SEC_INCOMPAT_PAR = 49; ! Management Security buffer - incompatible parameter version literal MGT$K_STS_SEC_INVALID_PAR = 50; ! Management Security buffer - invalid parameter(s) literal MGT$K_STS_SEC_ILLEGAL_PAR = 51; ! Management Security buffer - illegal settings or ! combination of settings for the request literal MGT$K_STS_SEC_RSVD1 = 52; ! Management Security buffer - reserved literal MGT$K_STS_SEC_RSVD2 = 53; ! Management Security buffer - reserved literal MGT$K_STS_PKT_REP_INVSIZE = 54; ! MO packet lengths != for replace literal MGT$K_STS_PKT_RSVD1 = 55; ! MO packet reserved literal MGT$K_STS_PKT_RSVD2 = 56; ! MO packet reserved literal MGT$K_STS_PKT_RSVD3 = 57; ! MO packet reserved literal MGT$K_STS_PKT_RSVD4 = 58; ! MO packet reserved literal MGT$K_STS_EOD_INVALIDADD = 59; ! Adding an EOD header to a MO packet set with a continuation header ! or a context header literal MGT$K_STS_EOD_RSVD1 = 60; ! Reserved EOD header error literal MGT$K_STS_EOD_RSVD2 = 61; ! Reserved EOD header error literal MGT$K_STS_HDR_INFO_INVALID = 62; ! MO header info is invalid literal MGT$K_STS_HDR_INFO_UNEXPECTED = 63; ! MO header info is in an unexpected state literal MGT$K_STS_HDR_INFO_RSVD1 = 64; ! Reserved MO header info error literal MGT$K_STS_HDR_INFO_RSVD2 = 65; ! Reserved MO header info error literal MGT$K_STS_FIRST_PRIVATE_CODE = 128; ! First code value for Managed Object private error codes ! ! Older constants for compatibility ! literal MGT$K_STS_NOT_ALIGNED = 2; ! Request or response buffer not quadword aligned literal MGT$K_STS_INCOMPAT_HDR = 4; ! Incompatible header version literal MGT$K_STS_INCOMPAT_PAR = 5; ! Incompatible parameter version literal MGT$K_STS_INVALID_PAR = 6; ! Invalid parameter(s) literal MGTHDR$K_OBJ_NAME_LEN = 32; ! V1.1 header era definition !*** MODULE MMECBDEF IDENT X-4 *** literal MMECB$M_UNLOAD = %X'1'; literal MMECB$M_ALLOC = %X'2'; literal MMECB$M_BACKUP_FILE = %X'4'; literal MMECB$M_CLOSE_READ = %X'8'; literal MMECB$M_CLOSE_WRITE = %X'10'; literal MMECB$M_CONTINUATION_VOLUME = %X'20'; literal MMECB$M_DEALLOCATE = %X'40'; literal MMECB$M_DEVICE_AVAIL = %X'80'; literal MMECB$M_DEVICE_UNAVAIL = %X'100'; literal MMECB$M_DISMOUNT = %X'200'; literal MMECB$M_DISPLAY_MESSAGE = %X'400'; literal MMECB$M_EOV_READ = %X'800'; literal MMECB$M_EOV_WRITE = %X'1000'; literal MMECB$M_INITIALIZE = %X'2000'; literal MMECB$M_MOUNT = %X'4000'; literal MMECB$M_MOUNT_REQUEST = %X'8000'; literal MMECB$M_NEWVOL_REQUEST = %X'10000'; literal MMECB$M_NOTIFY_DEVICE = %X'20000'; literal MMECB$M_OPCOM_ACP = %X'40000'; literal MMECB$M_OPCOM_MOUNT = %X'80000'; literal MMECB$M_OPEN_READ = %X'100000'; literal MMECB$M_OPEN_WRITE = %X'200000'; literal MMECB$M_VOLUME_ONLINE = %X'400000'; literal MMECB$M_BACKUP_END = %X'800000'; literal MMECB$M_BACKUP_START = %X'1000000'; literal MMECB$M_WRITE_REQUEST = %X'2000000'; literal MMECB$M_MOUNT_END = %X'4000000'; literal MMECB$M_INIT_END = %X'8000000'; literal MMECB$M_NEWVOL_END = %X'10000000'; literal MMECB$M_DMTPRCDEL = %X'20000000'; literal MMECB$S_MMECB = 32; macro MMECB$W_FACILITY = 0,0,16,0 %; ! TMS facility code macro MMECB$W_MBUNIT = 2,0,16,0 %; ! Mailbox unit number macro MMECB$L_PID = 4,0,32,0 %; ! Pid of TMS process macro MMECB$W_SIZE = 8,0,16,0 %; ! Control block size macro MMECB$B_TYPE = 10,0,8,0 %; ! BLOCK TYPE CODE macro MMECB$B_SUBTYPE = 11,0,8,0 %; ! BLOCK SUBTYPE CODE macro MMECB$L_MBXUCB = 12,0,32,1 %; ! Mailbox UCB address macro MMECB$Q_ROUTINE_MASK = 16,0,0,0 %; literal MMECB$S_ROUTINE_MASK = 8; macro MMECB$V_UNLOAD = 16,0,1,0 %; macro MMECB$V_ALLOC = 16,1,1,0 %; macro MMECB$V_BACKUP_FILE = 16,2,1,0 %; macro MMECB$V_CLOSE_READ = 16,3,1,0 %; macro MMECB$V_CLOSE_WRITE = 16,4,1,0 %; macro MMECB$V_CONTINUATION_VOLUME = 16,5,1,0 %; macro MMECB$V_DEALLOCATE = 16,6,1,0 %; macro MMECB$V_DEVICE_AVAIL = 16,7,1,0 %; macro MMECB$V_DEVICE_UNAVAIL = 16,8,1,0 %; macro MMECB$V_DISMOUNT = 16,9,1,0 %; macro MMECB$V_DISPLAY_MESSAGE = 16,10,1,0 %; macro MMECB$V_EOV_READ = 16,11,1,0 %; macro MMECB$V_EOV_WRITE = 16,12,1,0 %; macro MMECB$V_INITIALIZE = 16,13,1,0 %; macro MMECB$V_MOUNT = 16,14,1,0 %; macro MMECB$V_MOUNT_REQUEST = 16,15,1,0 %; macro MMECB$V_NEWVOL_REQUEST = 16,16,1,0 %; macro MMECB$V_NOTIFY_DEVICE = 16,17,1,0 %; macro MMECB$V_OPCOM_ACP = 16,18,1,0 %; macro MMECB$V_OPCOM_MOUNT = 16,19,1,0 %; macro MMECB$V_OPEN_READ = 16,20,1,0 %; macro MMECB$V_OPEN_WRITE = 16,21,1,0 %; macro MMECB$V_VOLUME_ONLINE = 16,22,1,0 %; macro MMECB$V_BACKUP_END = 16,23,1,0 %; macro MMECB$V_BACKUP_START = 16,24,1,0 %; macro MMECB$V_WRITE_REQUEST = 16,25,1,0 %; macro MMECB$V_MOUNT_END = 16,26,1,0 %; macro MMECB$V_INIT_END = 16,27,1,0 %; macro MMECB$V_NEWVOL_END = 16,28,1,0 %; macro MMECB$V_DMTPRCDEL = 16,29,1,0 %; macro MMECB$L_MCL_FLINK = 24,0,32,1 %; ! Mount context list forward link macro MMECB$L_MCL_BLINK = 28,0,32,1 %; ! Mount context list backward link literal MMECB$S_MMECBDEF = 32; ! Old size name, synonym for MMECB$S_MMECB literal MME$M_WAS_RUNNING = %X'1'; literal MME$S_MMEFLAGS = 1; macro MME$B_FLAGS_MASK = 0,0,8,0 %; macro MME$V_WAS_RUNNING = 0,0,1,0 %; !*** MODULE $MMGDEF *** literal MMG$M_NO_MPL_FLUSH = 4; ! Don't flush MPL on SVAPTE requests literal MMG$V_NO_MPL_FLUSH = 2; ! (MMG$GL_FREWFLGS) literal MMG$M_NOWAIT = 2; ! Don't allow FREWSLE to resource wait literal MMG$V_NOWAIT = 1; ! on modified list back pressure literal MMG$M_NOLASTUPD = 1; ! Don't allow FREWSLE to update WSLAST literal MMG$V_NOLASTUPD = 0; ! (prevent WSLAST/WSSIZE interactions) literal MMG$M_TICK_ENABLE = 1; ! TICKING enable bit literal MMG$V_TICK_ENABLE = 0; ! (MMG$GB_CTLFLAGS) literal MMG$M_TROLL_ENABLE = 2; ! TROLLING enable bit literal MMG$V_TROLL_ENABLE = 1; ! (MMG$GB_CTLFLAGS) literal MMG$M_BOOTIME_MEMTEST = 4; ! Test all memory at boot time flag literal MMG$V_BOOTIME_MEMTEST = 2; ! (MMG$GB_CTLFLAGS) literal MMG$M_NO_MB = 8; ! Set NO_MB bit in PTE literal MMG$V_NO_MB = 3; ! (MMG$GB_CTLFLAGS) literal MMG$M_GH_LIMITED = 16; ! If set, GH regions cannot span page literal MMG$V_GH_LIMITED = 4; ! table pages (MMG$GB_CTLFLAGS) literal MMG$M_NO_PTCG = 32; ! If set, IA64 TBI invalidates will not use literal MMG$V_NO_PTCG = 5; ! ptc.g instructions (MMG$GB_CTLFLAGS) literal MMG$M_TICK_ACT = 1; ! TICKING activate bit literal MMG$V_TICK_ACT = 0; ! (MMG$GL_RECLAIM_FLAGS) ! Define the limit beyond which an MPL flush must not be delayed. This MUST ! be less than MPW$C_MAXREQCNT (32), which is defined in WRTMFYPAG. literal MMG$C_MPL_FLUSH_LIM = 16; ! Define the maximum size of an object name string for a global section: ! []$ ! 1 + 5 + 1 + 23 + 1 + 43 bytes = 74; round to quad literal MMG$C_SECOBJNAM_SIZE = 80; ! -F ,B,0 /* ending address of negated structure ! (needed to obtain length definition) literal MMG$K_LENGTH = -40; ! size of scratch area literal MMG$C_LENGTH = -40; ! size of scratch area literal MMG$M_DELGBLDON = %X'1'; literal MMG$M_RWAST_AT_IPL0_OCCURRED_PP = %X'2'; literal MMG$M_CHGPAGFIL = %X'1'; literal MMG$M_NOWAIT_IPL0 = %X'2'; literal MMG$M_NO_OVERMAP = %X'4'; literal MMG$M_PARTIAL_FIRST = %X'8'; literal MMG$M_PARTIAL_LAST = %X'10'; literal MMG$M_NO_IRP_DELETE = %X'20'; literal MMG$M_DELPAG_NOP = %X'40'; literal MMG$M_CLUSTER_DEL = %X'80'; literal MMG$M_WINDOW = %X'100'; literal MMG$M_SHARED_L3PTS = %X'200'; literal MMG$M_RWAST_AT_IPL0_ALLOWED = %X'400'; literal MMG$M_RWAST_AT_IPL0_OCCURRED = %X'800'; literal MMG$S_MMGDEF = 41; ! Old size name - synonym literal MMG$S_MMG = 41; macro MMG$L_PGFLCNT = -40,0,32,1 %; ! remaining page file quota macro MMG$L_PAGCNT = -36,0,32,1 %; ! Buffer Object page count macro MMG$L_EFBLK = -36,0,32,1 %; ! stored end-of-file block from WCB macro MMG$L_VFYFLAGS = -32,0,32,0 %; ! verified section flags and maximum ! access mode for writing macro MMG$L_SVSTARTVA = -28,0,32,1 %; ! saved starting virtual address macro MMG$L_PAGESUBR = -24,0,32,1 %; ! address of per page subroutine macro MMG$L_SAVRETADR = -20,0,32,1 %; ! saved return address range macro MMG$L_CALLEDIPL = -16,0,32,1 %; ! caller's IPL macro MMG$L_PER_PAGE = -12,0,32,0 %; ! per-page processing context area macro MMG$V_DELGBLDON = -12,0,1,0 %; ! global pages in this range already deleted macro MMG$V_RWAST_AT_IPL0_OCCURRED_PP = -12,1,1,0 %; ! RWAST at IPL 0 occured (per-proc cntxt) macro MMG$L_ACCESS_MODE = -8,0,32,0 %; ! maximized read access mode macro MMG$L_MMG_FLAGS = -4,0,32,0 %; ! memory management control flags macro MMG$V_CHGPAGFIL = -4,0,1,0 %; ! charge page file for this PTE macro MMG$V_NOWAIT_IPL0 = -4,1,1,0 %; ! abort instead of dropping to 0 macro MMG$V_NO_OVERMAP = -4,2,1,0 %; ! don't overmap macro MMG$V_PARTIAL_FIRST = -4,3,1,0 %; ! 1st PTE mapped must be marked 'partial' macro MMG$V_PARTIAL_LAST = -4,4,1,0 %; ! last PTE mapped must be marked 'partial' macro MMG$V_NO_IRP_DELETE = -4,5,1,0 %; ! Don't delete IRP when returning to ! mainline (UPDSEC) macro MMG$V_DELPAG_NOP = -4,6,1,0 %; ! DELPAG skipped a page macro MMG$V_CLUSTER_DEL = -4,7,1,0 %; ! DELPAG may do clustered deletions macro MMG$V_WINDOW = -4,8,1,0 %; ! PFN-mapped or memory resident page macro MMG$V_SHARED_L3PTS = -4,9,1,0 %; ! Mapping will use shared PTs macro MMG$V_RWAST_AT_IPL0_ALLOWED = -4,10,1,0 %; ! Allow RWAST at IPL 0 macro MMG$V_RWAST_AT_IPL0_OCCURRED = -4,11,1,0 %; ! RWAST at IPL 0 occurred literal MMG$M_RES_MEM_ZERO = %X'1'; literal MMG$M_RES_MEM_GROUP = %X'2'; literal MMG$M_RES_MEM_PTS = %X'4'; literal MMG$M_RES_MEM_GBLSEC = %X'8'; literal MMG$S_RES_MEM = 4; macro MMG$L_RES_MEM_FLAGS = 0,0,32,0 %; ! Reserved memory flags macro MMG$V_RES_MEM_ZERO = 0,0,1,0 %; ! Pages need to be zeroed macro MMG$V_RES_MEM_GROUP = 0,1,1,0 %; ! Group number match required macro MMG$V_RES_MEM_PTS = 0,2,1,0 %; ! Reserved memory is for page tables macro MMG$V_RES_MEM_GBLSEC = 0,3,1,0 %; ! Reserved memory is for (group or system) global section. literal MMG$M_COLOR_MUST = %X'1'; literal MMG$M_COLOR_RANDOM = %X'2'; literal MMG$M_ZEROED = %X'4'; literal MMG$M_CONTIG = %X'8'; literal MMG$K_NO_VPN = -1; ! No VPN specified (-1) literal MMG$K_NO_RAD = -1; ! No RAD specified (-1) literal MMG$K_BASE_RAD = -2; ! Use the OS base RAD (-2) literal MMG$S_ALLOCPFN_FLAGS = 4; macro MMG$L_ALLOCPFN_FLAGS = 0,0,32,0 %; ! Page flags macro MMG$V_COLOR_MUST = 0,0,1,0 %; ! Must return color specified macro MMG$V_COLOR_RANDOM = 0,1,1,0 %; ! Return a random color macro MMG$V_ZEROED = 0,2,1,0 %; ! Allocate zeroed page macro MMG$V_CONTIG = 0,3,1,0 %; ! Allocate contiguous PFNs for mapping ! ! values for "which list" constants returned by PTE/PFN checking routines ! literal MMG$C_PRIVATE = 1; literal MMG$C_SHARED = 2; literal MMG$C_IO = 3; literal MMG$K_POOLTYPE_NPP = 0; literal MMG$K_POOLTYPE_BAP = 1; literal MMG$K_POOLTYPE_MAXIMUM = 2; ! ! The following constants are only used by SDA: ! ! MMG$K_POOLTYPE_PAGED is the same as MMG$K_POOLTYPE_MAXIMUM ! MMG$K_POOLTYPE_P0 is MMG$K_POOLTYPE_PAGED + 1 ! MMG$K_POOLTYPE_P1 is MMG$K_POOLTYPE_P0 + 1 ! MMG$K_POOLTYPE_IMAGE is MMG$K_POOLTYPE_P1 + 1 ! ! If new pool types are added within MMG$K_POOLTYPE_MAXIMUM, these ! constants should be moved down and a corresponding change made to ! [SDA]EVAX_SDADEF.SDL ! literal MMG$K_POOLTYPE_PAGED = 2; literal MMG$K_POOLTYPE_P0 = 3; literal MMG$K_POOLTYPE_P1 = 4; literal MMG$K_POOLTYPE_IMAGE = 5; ! ! Return bitmask definitions for mmg$check_va_access ! literal MMG$M_VA_VALID = %X'1'; literal MMG$M_PTE_VALID = %X'2'; literal MMG$M_K_READ = %X'4'; literal MMG$M_K_WRITE = %X'8'; literal MMG$M_K_EXEC = %X'10'; literal MMG$M_PHYS_MEM = %X'20'; literal MMG$M_IO_MEM = %X'40'; literal MMG$M_UNK_MEM = %X'80'; literal MMG$S_CHECK_VA = 4; macro MMG$L_CHECK_VA_FLAGS = 0,0,32,0 %; ! Flags longword macro MMG$V_VA_VALID = 0,0,1,0 %; ! VA is valid (not in any gaps) macro MMG$V_PTE_VALID = 0,1,1,0 %; ! VA's PTE is valid macro MMG$V_K_READ = 0,2,1,0 %; ! VA is kernel readable macro MMG$V_K_WRITE = 0,3,1,0 %; ! VA is kernel writable macro MMG$V_K_EXEC = 0,4,1,0 %; ! VA is kernel executable macro MMG$V_PHYS_MEM = 0,5,1,0 %; ! VA maps real physical mem macro MMG$V_IO_MEM = 0,6,1,0 %; ! VA maps I/O space macro MMG$V_UNK_MEM = 0,7,1,0 %; ! VA map unkonwn memory. If set, there is no ! I/O space data, so the VA could map I/O space. literal MMG$C_STACK_PROCESS = 0; ! Process default stack literal MMG$C_STACK_KP = 1; ! KP stack literal MMG$C_STACK_KTHREAD = 2; ! Kernel thread stack literal MMG$C_JUST_I = 1; ! Just instruction literal MMG$C_JUST_D = 2; ! Just data literal MMG$C_BOTH_I_AND_D = 3; ! Both instruction and data ! ! This structure is used by MMG$DELPAG_64 in SYSCREDEL to throttle the ! number of processes that are tearing down virtual address space. ! ! It is recommended that this structure be allocated on a cache line ! boundary - 64 bytes for Alpha and 128 for IPF. ! literal MMG_DEL$S_DELPAG_MEM = 384; macro MMG_DEL$L_THROTTLE = 0,0,32,1 %; ! Number of processes in the throttle macro MMG_DEL$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro MMG_DEL$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE CODE macro MMG_DEL$B_SUBTYPE = 11,0,8,0 %; ! STRUCTURE SUB-TYPE CODE macro MMG_DEL$Q_DELPAG_ITERATIONS = 16,0,0,0 %; literal MMG_DEL$S_DELPAG_ITERATIONS = 8; macro MMG_DEL$Q_DROP_AVOIDED = 24,0,0,0 %; literal MMG_DEL$S_DROP_AVOIDED = 8; ! MMG Drop Avoided macro MMG_DEL$Q_TIMEDOUT = 32,0,0,0 %; literal MMG_DEL$S_TIMEDOUT = 8; ! Delpag MMG Hold Time Exceeded macro MMG_DEL$Q_LAST_ENTERED = 40,0,0,0 %; literal MMG_DEL$S_LAST_ENTERED = 8; ! Time (abstim_tics) of last entry macro MMG_DEL$Q_THROTTLED = 48,0,0,0 %; literal MMG_DEL$S_THROTTLED = 8; ! Throttled entries to DELPAG macro MMG_DEL$Q_NONTHROTTLED = 56,0,0,0 %; literal MMG_DEL$S_NONTHROTTLED = 8; ! Non-Throttled entries to DELPAG ! Offset to next cache line macro MMG_DEL$L_WAITERS = 128,0,32,1 %; ! Number of processes in the RW state macro MMG_DEL$Q_TOTAL_WAITS = 136,0,0,0 %; literal MMG_DEL$S_TOTAL_WAITS = 8; ! Total resource waits macro MMG_DEL$Q_LAST_STALL = 144,0,0,0 %; literal MMG_DEL$S_LAST_STALL = 8; ! Time (abstim_tics) of last stall macro MMG_DEL$L_MAX_WAITERS = 152,0,32,1 %; ! largest number of stalled processes ! offset to next cache line macro MMG_DEL$L_MMG_HOLD = 256,0,32,1 %; ! MMG Hold time in 10 microsecond units macro MMG_DEL$L_THROTTLE_LIMIT = 260,0,32,1 %; ! Max allowed into DELPAG ! offset to next cache line literal MMG_DEL$C_THROTTLE_VAS = 256; ! VA count needed for throttling literal MMG_DEL$C_HOLD_MAX = 100; ! Max MMG hold in 10us Units literal MMG_DEL$C_THROTTLE_DFLT = 4; ! Default Throttle count literal MMG_DEL$C_HOLD_DFLT = 7; ! Default MMG hold in 10us Units !*** MODULE $mondef *** ! Monitor Recording File Definitions literal MON$C_MAX_CPUS = 1024; ! maximum number of CPUs possible literal MON$K_CBB_SIZE = 176; ! ***************************************************************************************** ! ! FILE header record format ! ! Max length of user comment string literal MNR_HDR$K_CLASSBITS = 128; literal MNR_HDR$K_REVLEVELS = 144; literal MNR_HDR$K_SIZE = 272; literal MNR_HDR$K_MAXCOMLEN = 60; ! constant for user comment string size literal MNR_HDR$S_FILE_HDR = 272; macro MNR_HDR$B_TYPE = 0,0,8,0 %; ! Unsigned record type macro MNR_HDR$L_FLAGS = 1,0,32,0 %; literal MNR_HDR$S_FLAGS = 4; ! Flags macro MNR_HDR$v_rewrite = 1,0,1,0 %; ! YES -> Rewrite operation completed successfully macro MNR_HDR$v_filler = 1,1,31,0 %; literal MNR_HDR$s_filler = 31; ! Fill out rest of longword macro MNR_HDR$Q_BEGINNING = 8,0,0,1 %; literal MNR_HDR$S_BEGINNING = 8; ! Beginning time of request in system time units macro MNR_HDR$Q_ENDING = 16,0,0,1 %; literal MNR_HDR$S_ENDING = 8; ! Ending time of request in system time units macro MNR_HDR$L_INTERVAL = 24,0,32,1 %; ! Interval value in seconds macro MNR_HDR$O_REV0CLSBITS = 32,0,0,0 %; literal MNR_HDR$S_REV0CLSBITS = 16; ! Bit string of recorded classes which are at rev 0 ! NOTE -- The above item is included for compatibility with ! MONITOR structure levels MONSL001 and MONBA001 macro MNR_HDR$L_RECCT = 48,0,32,1 %; ! Count of all records in the file (incl header) macro MNR_HDR$T_LEVEL = 52,0,0,0 %; literal MNR_HDR$S_LEVEL = 8; ! MONITOR Recording File structure level identification macro MNR_HDR$T_IDENT = 52,0,0,0 %; literal MNR_HDR$S_IDENT = 8; ! MONITOR Recording File structure level identification macro MNR_HDR$T_COMMENT = 60,0,0,0 %; literal MNR_HDR$S_COMMENT = 60; ! User comment string macro MNR_HDR$W_COMLEN = 120,0,16,1 %; ! Actual length of user comment string macro MNR_HDR$O_CLASSBITS = 128,0,0,0 %; literal MNR_HDR$S_CLASSBITS = 16; ! Bit string of recorded classes macro MNR_HDR$T_REVLEVELS = 144,0,0,0 %; literal MNR_HDR$S_REVLEVELS = 128; ! Rev level for each recorded class literal MNR_OLDHDR$K_CLASSBITS = 115; literal MNR_OLDHDR$K_REVLEVELS = 131; literal MNR_OLDHDR$K_SIZE = 259; literal MNR_OLDHDR$K_MAXCOMLEN = 60; ! constant for user comment string size literal MNR_OLDHDR$S_FILE_HDR_OLD = 264; macro MNR_OLDHDR$B_TYPE = 0,0,8,0 %; ! Unsigned record type macro MNR_OLDHDR$L_FLAGS = 1,0,32,0 %; literal MNR_OLDHDR$S_FLAGS = 4; ! Flags macro MNR_OLDHDR$v_rewrite = 1,0,1,0 %; ! YES -> Rewrite operation completed successfully macro MNR_OLDHDR$v_filler = 1,1,31,0 %; literal MNR_OLDHDR$s_filler = 31; ! Fill out rest of longword macro MNR_OLDHDR$Q_BEGINNING = 5,0,0,1 %; literal MNR_OLDHDR$S_BEGINNING = 8; ! Beginning time of request in system time units macro MNR_OLDHDR$Q_ENDING = 13,0,0,1 %; literal MNR_OLDHDR$S_ENDING = 8; ! Ending time of request in system time units macro MNR_OLDHDR$L_INTERVAL = 21,0,32,1 %; ! Interval value in seconds macro MNR_OLDHDR$O_REV0CLSBITS = 25,0,0,0 %; literal MNR_OLDHDR$S_REV0CLSBITS = 16; ! Bit string of recorded classes which are at rev 0 ! NOTE -- The above item is included for compatibility with ! MONITOR structure levels MONSL001 and MONBA001 macro MNR_OLDHDR$L_RECCT = 41,0,32,1 %; ! Count of all records in the file (incl header) macro MNR_OLDHDR$T_LEVEL = 45,0,0,0 %; literal MNR_OLDHDR$S_LEVEL = 8; ! MONITOR Recording File structure level identification macro MNR_OLDHDR$T_IDENT = 45,0,0,0 %; literal MNR_OLDHDR$S_IDENT = 8; ! MONITOR Recording File structure level identification macro MNR_OLDHDR$T_COMMENT = 53,0,0,0 %; literal MNR_OLDHDR$S_COMMENT = 60; ! User comment string macro MNR_OLDHDR$W_COMLEN = 113,0,16,1 %; ! Actual length of user comment string macro MNR_OLDHDR$O_CLASSBITS = 115,0,0,0 %; literal MNR_OLDHDR$S_CLASSBITS = 16; ! Bit string of recorded classes macro MNR_OLDHDR$T_REVLEVELS = 131,0,0,0 %; literal MNR_OLDHDR$S_REVLEVELS = 128; ! Rev level for each recorded class ! ***************************************************************************************** ! ! SYSTEM information record format ! literal MNR_SYI$K_SIZE = 244; literal MNR_SYI$S_SYS_INFO = 248; macro MNR_SYI$B_TYPE = 0,0,8,0 %; ! Unsigned record type macro MNR_SYI$B_SPARE2 = 1,0,8,1 %; ! macro MNR_SYI$w_FLAGS = 2,0,16,0 %; literal MNR_SYI$S_FLAGS = 2; ! Flags macro MNR_SYI$v_clusmem = 2,0,1,0 %; ! YES => this node is a member of a cluster macro MNR_SYI$v_reserved1 = 2,1,1,0 %; ! Reserved bit macro MNR_SYI$v_vm = 2,2,1,0 %; ! YES => this node is vm macro MNR_SYI$v_ht = 2,3,1,0 %; ! YES => hyper thread enabled macro MNR_SYI$v_filler = 2,4,12,0 %; literal MNR_SYI$s_filler = 12; ! Fill out rest of word macro MNR_SYI$Q_BOOTTIME = 8,0,0,1 %; literal MNR_SYI$S_BOOTTIME = 8; ! Absolute system boot time in system time units macro MNR_SYI$W_MAXPRCCT = 16,0,16,1 %; ! MAXPROCESSCNT SYSGEN parameter macro MNR_SYI$W_MPCPUS = 18,0,16,1 %; ! Number of multiprocessing CPUs macro MNR_SYI$B_MPCPUS = 18,0,8,1 %; ! Number of multiprocessing CPUs macro MNR_SYI$T_NODENAME = 24,0,0,0 %; literal MNR_SYI$S_NODENAME = 16; ! DECnet node name of data source node macro MNR_SYI$L_BALSETMEM = 40,0,32,1 %; ! Balance set memory (in pages) macro MNR_SYI$L_MPWHILIM = 44,0,32,1 %; ! Modified Page List high limit (in pages) macro MNR_SYI$L_CPUTYPE = 48,0,32,1 %; ! CPU type code (in binary) macro MNR_SYI$B_INDEX = 52,0,8,1 %; ! Node table index for this node macro MNR_SYI$CBB_CPUCONF = 56,0,0,0 %; literal MNR_SYI$S_CPUCONF = 48; ! Embedded CBB block macro MNR_SYI$L_CPUCONF = 104,0,32,0 %; ! Active CPU mask macro MNR_SYI$B_VPCPUS = 232,0,8,1 %; ! Number of vector processor CPUs macro MNR_SYI$L_VPCONF = 236,0,32,1 %; ! Bitmask representing the system VP CPU configuration macro MNR_SYI$L_SPARE1 = 240,0,32,1 %; literal MNR_OLDSYI$K_SIZE = 52; literal MNR_OLDSYI$S_SYS_INFO_OLD = 56; macro MNR_OLDSYI$B_TYPE = 0,0,8,0 %; ! Unsigned record type macro MNR_OLDSYI$w_FLAGS = 1,0,16,0 %; literal MNR_OLDSYI$S_FLAGS = 2; ! Flags macro MNR_OLDSYI$v_clusmem = 1,0,1,0 %; ! YES => this node is a member of a cluster macro MNR_OLDSYI$v_reserved1 = 1,1,1,0 %; ! Reserved bit macro MNR_OLDSYI$v_filler = 1,2,14,0 %; literal MNR_OLDSYI$s_filler = 14; ! Fill out rest of word macro MNR_OLDSYI$Q_BOOTTIME = 3,0,0,1 %; literal MNR_OLDSYI$S_BOOTTIME = 8; ! Absolute system boot time in system time units macro MNR_OLDSYI$W_MAXPRCCT = 11,0,16,1 %; ! MAXPROCESSCNT SYSGEN parameter macro MNR_OLDSYI$B_MPCPUS = 13,0,8,1 %; ! Number of multiprocessing CPUs macro MNR_OLDSYI$T_NODENAME = 14,0,0,0 %; literal MNR_OLDSYI$S_NODENAME = 16; ! DECnet node name of data source node macro MNR_OLDSYI$L_BALSETMEM = 30,0,32,1 %; ! Balance set memory (in pages) macro MNR_OLDSYI$L_MPWHILIM = 34,0,32,1 %; ! Modified Page List high limit (in pages) macro MNR_OLDSYI$L_CPUTYPE = 38,0,32,1 %; ! CPU type code (in binary) macro MNR_OLDSYI$B_INDEX = 42,0,8,1 %; ! Node table index for this node macro MNR_OLDSYI$L_CPUCONF = 43,0,32,0 %; macro MNR_OLDSYI$B_VPCPUS = 47,0,8,1 %; ! Number of vector processor CPUs macro MNR_OLDSYI$L_VPCONF = 48,0,32,1 %; ! Bitmask representing the system VP CPU configuration ! ***************************************************************************************** ! ! NODE transition record format ! literal MNR_NTR$K_SIZE = 8; literal MNR_NTR$S_NODE_TRANS = 8; macro MNR_NTR$B_TYPE = 0,0,8,0 %; ! record type identifier macro MNR_NTR$B_INDEX = 1,0,8,1 %; ! node index macro MNR_NTR$W_SPARE1 = 2,0,16,1 %; ! macro MNR_NTR$L_SPARE2 = 4,0,32,1 %; ! ! ***************************************************************************************** ! ! RMS file record format ! literal MNR_FIL$S_RMS_FILE = 264; macro MNR_FIL$B_TYPE = 0,0,8,0 %; ! Record type identifier macro MNR_FIL$T_FILENAME = 1,0,0,0 %; literal MNR_FIL$S_FILENAME = 256; ! ***************************************************************************************** ! ! CLASS header and prefix record format ! literal MNR_CLS$K_SIZE = 16; literal MNR_CLS$K_HSIZE = 16; literal MNR_CLS$K_PROCESSES = 0; literal MNR_CLS$K_STATES = 1; literal MNR_CLS$K_MODES = 2; literal MNR_CLS$K_PAGE = 3; literal MNR_CLS$K_IO = 4; literal MNR_CLS$K_FCP = 5; literal MNR_CLS$K_POOL = 6; literal MNR_CLS$K_LOCK = 7; literal MNR_CLS$K_DECNET = 8; literal MNR_CLS$K_VMS2 = 9; literal MNR_CLS$K_VMS3 = 10; literal MNR_CLS$K_FILE_SYSTEM_CACHE = 11; literal MNR_CLS$K_DISK = 12; literal MNR_CLS$K_JDEVICE = 13; literal MNR_CLS$K_DLOCK = 14; literal MNR_CLS$K_SCS = 15; literal MNR_CLS$K_VMS1 = 16; literal MNR_CLS$K_SYSTEM = 17; literal MNR_CLS$K_ETHERNET = 18; literal MNR_CLS$K_CLUSTER = 19; literal MNR_CLS$K_RMS = 20; literal MNR_CLS$K_MSCP_SERVER = 21; literal MNR_CLS$K_TRANSACTION = 22; literal MNR_CLS$K_VECTOR = 23; literal MNR_CLS$K_VBS = 24; literal MNR_CLS$K_MVBS = 25; literal MNR_CLS$K_TIMER = 26; literal MNR_CLS$K_RLOCK = 27; literal MNR_CLS$K_ALIGN = 28; literal MNR_CLS$K_MAX_CLSNO = 28; literal MNR_CLS$K_ALL_CLSNO = 29; literal MNR_CLS$S_CLASS_HDR = 16; macro MNR_CLS$B_TYPE = 0,0,8,1 %; ! Unsigned record type macro MNR_CLS$B_FLAGS = 1,0,8,0 %; literal MNR_CLS$S_FLAGS = 1; ! Flags macro MNR_CLS$V_CONT = 1,0,1,0 %; ! The data for this interval continues in next record macro MNR_CLS$V_FILLER = 1,1,7,0 %; literal MNR_CLS$S_FILLER = 7; ! Fill out rest of byte macro MNR_CLS$B_INDEX = 2,0,8,1 %; ! Node table index macro MNR_CLS$W_RESERVED = 4,0,16,1 %; ! Reserved field macro MNR_CLS$Q_STAMP = 8,0,0,1 %; literal MNR_CLS$S_STAMP = 8; ! System time of collection literal MNR_OLDCLS$K_SIZE = 13; literal MNR_OLDCLS$K_HSIZE = 13; literal MNR_OLDCLS$S_CLASS_HDR_OLD = 16; macro MNR_OLDCLS$B_TYPE = 0,0,8,1 %; ! Unsigned record type macro MNR_OLDCLS$B_FLAGS = 1,0,8,0 %; literal MNR_OLDCLS$S_FLAGS = 1; ! Flags macro MNR_OLDCLS$V_CONT = 1,0,1,0 %; ! The data for this interval continues in next record macro MNR_OLDCLS$V_FILLER = 1,1,7,0 %; literal MNR_OLDCLS$S_FILLER = 7; ! Fill out rest of byte macro MNR_OLDCLS$B_INDEX = 2,0,8,1 %; ! Node table index macro MNR_OLDCLS$Q_STAMP = 3,0,0,1 %; literal MNR_OLDCLS$S_STAMP = 8; ! System time of collection macro MNR_OLDCLS$W_RESERVED = 11,0,16,1 %; ! Reserved field literal MNR_CMP$K_SIZE = 8; literal MNR_CMP$K_PSIZE = 8; literal MNR_CMP$S_CLASS_PRE = 8; macro MNR_CMP$L_ELTCT = 0,0,32,1 %; ! count of elements in this record macro MNR_CMP$L_PCTINT = 4,0,32,1 %; ! count of processes for this interval (only valid for PROCESS class) literal MNR_HOM$K_SIZE = 8; literal MNR_HOM$K_PSIZE = 8; literal MNR_HOM$S_CLASS_HOM = 8; macro MNR_HOM$L_ELTCT = 0,0,32,1 %; ! count of elements in this record macro MNR_HOM$L_RESERVED = 4,0,32,1 %; ! reserved ! ***************************************************************************************** ! ! ALIGN class record format ! literal MNR_ALI$K_SIZE = 16; literal MNR_ALI$S_ALIGN_CLASS = 16; macro MNR_ALI$L_ALIGN_KERNEL = 0,0,32,1 %; ! kernel mode alignment faults macro MNR_ALI$L_ALIGN_EXEC = 4,0,32,1 %; ! exec mode alignment faults macro MNR_ALI$L_ALIGN_SUPER = 8,0,32,1 %; ! super mode alignment faults macro MNR_ALI$L_ALIGN_USER = 12,0,32,1 %; ! user mode alignment faults ! ***************************************************************************************** ! ! CLUSTER class record format ! literal MNR_CLU$K_SIZE = 52; literal MNR_CLU$S_CLUSTER_CLASS = 56; macro MNR_CLU$L_CPU_BUSY = 0,0,32,1 %; ! CPU busy macro MNR_CLU$L_FRLIST = 4,0,32,1 %; ! number of pages on freelist macro MNR_CLU$L_RESERVED = 8,0,32,1 %; ! reserved field macro MNR_CLU$L_TOTAL_LOCKS = 12,0,32,1 %; ! total lock requests macro MNR_CLU$L_ENQNEWLOC = 16,0,32,1 %; ! enqueue requests (local) macro MNR_CLU$L_ENQNEWIN = 20,0,32,1 %; ! enqueue requests (incoming) macro MNR_CLU$L_ENQNEWOUT = 24,0,32,1 %; ! enqueue requests (outgoing) macro MNR_CLU$L_ENQCVTLOC = 28,0,32,1 %; ! conversion requests (local) macro MNR_CLU$L_ENQCVTIN = 32,0,32,1 %; ! conversion requests (incoming) macro MNR_CLU$L_ENQCVTOUT = 36,0,32,1 %; ! conversion requests (outgoing) macro MNR_CLU$L_DEQLOC = 40,0,32,1 %; ! dequeue requests (local) macro MNR_CLU$L_DEQIN = 44,0,32,1 %; ! dequeue requests (incoming) macro MNR_CLU$L_DEQOUT = 48,0,32,1 %; ! dequeue requests (outgoing) ! ***************************************************************************************** ! ! DECNET class record format ! literal MNR_NET$K_SIZE = 20; literal MNR_NET$S_DECNET_CLASS = 24; macro MNR_NET$L_ARRLOCPK = 0,0,32,1 %; ! arriving local packets macro MNR_NET$L_DEPLOCPK = 4,0,32,1 %; ! departing local packets macro MNR_NET$L_ARRTRAPK = 8,0,32,1 %; ! arriving transit packets macro MNR_NET$L_TRCNGLOS = 12,0,32,1 %; ! transit packet lost macro MNR_NET$L_RCVBUFFL = 16,0,32,1 %; ! receive buffer failures ! ***************************************************************************************** ! ! DISK class record format ! literal MNR_DSK$C_DISK_REV = 6; ! current revision is 6 literal MNR_DSK$K_SIZE = 44; literal MNR_DSK$S_DISK_CLASS = 48; macro MNR_DSK$W_ALLOCLS = 0,0,16,1 %; ! Allocation class macro MNR_DSK$W_UNITNO = 2,0,16,1 %; ! Unit number macro MNR_DSK$T_CTRLR = 4,0,32,1 %; ! Device name macro MNR_DSK$B_FLAGS = 8,0,8,1 %; ! Flags byte (low bit indicates served disk) macro MNR_DSK$B_REV = 9,0,8,1 %; ! revision macro MNR_DSK$W_MBZ = 10,0,16,1 %; ! must-be-zero macro MNR_DSK$L_SPARE1 = 12,0,32,1 %; ! spare macro MNR_DSK$T_NODENAME = 16,0,0,1 %; literal MNR_DSK$S_NODENAME = 8; ! Nodename macro MNR_DSK$T_VOLNAME = 24,0,0,0 %; literal MNR_DSK$S_VOLNAME = 12; ! Volume name macro MNR_DSK$Q_VOLNAMEL = 24,0,0,1 %; literal MNR_DSK$S_VOLNAMEL = 8; ! Volume name (low) macro MNR_DSK$L_VOLNAMEH = 32,0,32,1 %; ! Volume name (high) macro MNR_DSK$L_OPCNT = 36,0,32,1 %; ! Operation count macro MNR_DSK$L_IOQUELN = 40,0,32,1 %; ! Queue length accumulator literal MNR_OLDDSK$C_DISK_REV = 5; ! old format revision is 5 literal MNR_OLDDSK$K_SIZE = 37; literal MNR_OLDDSK$S_OLDDISK_CLASS = 40; macro MNR_OLDDSK$W_ALLOCLS = 0,0,16,1 %; ! Allocation class macro MNR_OLDDSK$T_CTRLR = 2,0,32,1 %; ! Device name macro MNR_OLDDSK$W_UNITNO = 6,0,16,1 %; ! Unit number macro MNR_OLDDSK$B_FLAGS = 8,0,8,1 %; ! Flags byte (low bit indicates served disk) macro MNR_OLDDSK$T_NODENAME = 9,0,0,1 %; literal MNR_OLDDSK$S_NODENAME = 8; ! Nodename macro MNR_OLDDSK$T_VOLNAMEL = 17,0,0,1 %; literal MNR_OLDDSK$S_VOLNAMEL = 8; ! Volume name (low) macro MNR_OLDDSK$T_VOLNAMEH = 25,0,32,1 %; ! Volume name (high) macro MNR_OLDDSK$L_OPCNT = 29,0,32,1 %; ! Operation count macro MNR_OLDDSK$L_IOQUELN = 33,0,32,1 %; ! Queue length accumulator ! ***************************************************************************************** ! ! DLOCK class record format ! literal MNR_DLO$K_SIZE = 60; literal MNR_DLO$S_DLOCK_CLASS = 64; macro MNR_DLO$L_ENQNEWLOC = 0,0,32,1 %; ! enqueue requests (local) macro MNR_DLO$L_ENQNEWIN = 4,0,32,1 %; ! enqueue requests (incoming) macro MNR_DLO$L_ENQNEWOUT = 8,0,32,1 %; ! enqueue requests (outgoing) macro MNR_DLO$L_ENQCVTLOC = 12,0,32,1 %; ! conversion requests (local) macro MNR_DLO$L_ENQCVTIN = 16,0,32,1 %; ! conversion requests (incoming) macro MNR_DLO$L_ENQCVTOUT = 20,0,32,1 %; ! conversion requests (outgoing) macro MNR_DLO$L_DEQLOC = 24,0,32,1 %; ! dequeue requests (local) macro MNR_DLO$L_DEQIN = 28,0,32,1 %; ! dequeue requests (incoming) macro MNR_DLO$L_DEQOUT = 32,0,32,1 %; ! dequeue requests (outgoing) macro MNR_DLO$L_BLKLOC = 36,0,32,1 %; ! blocking ASTs (local) macro MNR_DLO$L_BLKIN = 40,0,32,1 %; ! blocking ASTs (incoming) macro MNR_DLO$L_BLKOUT = 44,0,32,1 %; ! blocking ASTs (outgoing) macro MNR_DLO$L_DIRIN = 48,0,32,1 %; ! directory functions (incoming) macro MNR_DLO$L_DIROUT = 52,0,32,1 %; ! directory functions (outgoing) macro MNR_DLO$L_DLCKMSG = 56,0,32,1 %; ! deadlock message rate ! ***************************************************************************************** ! ! FCP class record format ! literal MNR_FCP$K_SIZE = 48; literal MNR_FCP$S_FCP_CLASS = 48; macro MNR_FCP$L_FCPCALLS = 0,0,32,1 %; ! FCP calls macro MNR_FCP$L_ALLOC = 4,0,32,1 %; ! disk allocation requests macro MNR_FCP$L_FCPCREATE = 8,0,32,1 %; ! new files macro MNR_FCP$L_FCPREAD = 12,0,32,1 %; ! read I/Os macro MNR_FCP$L_FCPWRITE = 16,0,32,1 %; ! write I/Os macro MNR_FCP$L_VOLWAIT = 20,0,32,1 %; ! volume lock waits macro MNR_FCP$L_FCPCPU = 24,0,32,1 %; ! CPU time spent in file system macro MNR_FCP$L_FCPFAULT = 28,0,32,1 %; ! count of pagefaults for file system macro MNR_FCP$L_FCPTURN = 32,0,32,1 %; ! window turns macro MNR_FCP$L_ACCESS = 36,0,32,1 %; ! count of file name lookup operations macro MNR_FCP$L_OPENS = 40,0,32,1 %; ! files opened macro MNR_FCP$L_ERASE = 44,0,32,1 %; ! count of erase I/O operations ! ***************************************************************************************** ! ! FILE_SYSTEM_CACHE class record format ! literal MNR_FIL$K_SIZE = 56; literal MNR_FIL$S_FILE_SYS_CLASS = 56; macro MNR_FIL$L_DIRFCB_HIT = 0,0,32,1 %; ! directory FCB cache hits macro MNR_FIL$L_DIRFCB_TRIES = 4,0,32,1 %; ! directory FCB cache attempts macro MNR_FIL$L_DIRDATA_HIT = 8,0,32,1 %; ! directory data cache hits macro MNR_FIL$L_DIRDATA_TRIES = 12,0,32,1 %; ! directory data cache attempts macro MNR_FIL$L_FILHDR_HIT = 16,0,32,1 %; ! file header cache hits macro MNR_FIL$L_FILHDR_TRIES = 20,0,32,1 %; ! file header cache attempts macro MNR_FIL$L_FIDHIT = 24,0,32,1 %; ! file ID cache hits macro MNR_FIL$L_FID_HIT = 24,0,32,1 %; ! macro MNR_FIL$L_FID_TRIES = 28,0,32,1 %; ! file ID cache attempts macro MNR_FIL$L_EXTHIT = 32,0,32,1 %; ! extent cache hits macro MNR_FIL$L_EXT_HIT = 32,0,32,1 %; ! macro MNR_FIL$L_EXT_TRIES = 36,0,32,1 %; ! extent cache attempts macro MNR_FIL$L_QUOHIT = 40,0,32,1 %; ! quota cache hits macro MNR_FIL$L_QUO_HIT = 40,0,32,1 %; ! macro MNR_FIL$L_QUO_TRIES = 44,0,32,1 %; ! quota cache attempts macro MNR_FIL$L_STORAGMAP_HIT = 48,0,32,1 %; ! storage bitmap cache hits macro MNR_FIL$L_STORAGMAP_TRIES = 52,0,32,1 %; ! storage bitmap cache attempts ! ***************************************************************************************** ! ! I/O class record format ! literal MNR_IO$K_SIZE = 56; literal MNR_IO$S_IO_CLASS = 56; macro MNR_IO$L_DIRIO = 0,0,32,1 %; ! count of direct I/O requests macro MNR_IO$L_BUFIO = 4,0,32,1 %; ! count of buffered I/O requests macro MNR_IO$L_MBWRITES = 8,0,32,1 %; ! mailbox writes macro MNR_IO$L_SPLTRANS = 12,0,32,1 %; ! count of split transfers macro MNR_IO$L_LOGNAM = 16,0,32,1 %; ! count of logical name translations macro MNR_IO$L_OPENS = 20,0,32,1 %; ! count of files opened macro MNR_IO$L_FAULTS = 24,0,32,1 %; ! total pagefaults macro MNR_IO$L_PREADS = 28,0,32,1 %; ! count of pages read from disk macro MNR_IO$L_PREADIO = 32,0,32,1 %; ! count of page read I/Os from disk macro MNR_IO$L_PWRITES = 36,0,32,1 %; ! count of pages written to pagefile macro MNR_IO$L_PWRITIO = 40,0,32,1 %; ! count of page write I/Os to pagefile macro MNR_IO$L_ISWPCNT = 44,0,32,1 %; ! count of inswap operations macro MNR_IO$L_FREECNT = 48,0,32,1 %; ! number of pages on freelist macro MNR_IO$L_MFYCNT = 52,0,32,1 %; ! number of pages on modified list ! ***************************************************************************************** ! ! LOCK class record format ! literal MNR_LCK$K_SIZE = 40; literal MNR_LCK$S_LOCK_CLASS = 40; macro MNR_LCK$L_ENQNEW = 0,0,32,1 %; ! enqueue requests macro MNR_LCK$L_ENQCVT = 4,0,32,1 %; ! conversion requests macro MNR_LCK$L_DEQ = 8,0,32,1 %; ! dequeue requests macro MNR_LCK$L_BLKAST = 12,0,32,1 %; ! blocking ASTs macro MNR_LCK$L_ENQWAIT = 16,0,32,1 %; ! ENQ waits macro MNR_LCK$L_ENQNOTQD = 20,0,32,1 %; ! ENQs not queued macro MNR_LCK$L_DLCKSRCH = 24,0,32,1 %; ! deadlock searches macro MNR_LCK$L_DLCKFND = 28,0,32,1 %; ! deadlocks found macro MNR_LCK$L_NUMLOCKS = 32,0,32,1 %; ! total number of locks macro MNR_LCK$L_NUMRES = 36,0,32,1 %; ! total number of resources ! ***************************************************************************************** ! ! MODES class record format ! literal MNR_MOD$K_SIZE = 36; literal MNR_MOD$S_MODES_CLASS = 40; macro MNR_MOD$L_CPUID = 0,0,32,1 %; ! CPU id macro MNR_MOD$B_CPUID = 0,0,8,1 %; macro MNR_MOD$L_INTER = 4,0,32,1 %; ! Interrupt stack time macro MNR_MOD$L_MPSYNC = 8,0,32,1 %; ! Multi-processor sync time macro MNR_MOD$L_KERNEL = 12,0,32,1 %; ! Kernel mode time macro MNR_MOD$L_EXEC = 16,0,32,1 %; ! exec mode time macro MNR_MOD$L_SUPER = 20,0,32,1 %; ! Supervisor mode time macro MNR_MOD$L_USER = 24,0,32,1 %; ! User mode time macro MNR_MOD$L_COMPAT = 28,0,32,1 %; ! Compatibility mode time macro MNR_MOD$L_IDLE = 32,0,32,1 %; ! Idle time literal MNR_OLDMOD$K_SIZE = 33; literal MNR_OLDMOD$S_OLDMODES_CLASS = 40; macro MNR_OLDMOD$B_CPUID = 0,0,8,1 %; macro MNR_OLDMOD$L_INTER = 1,0,32,1 %; ! Interrupt stack time macro MNR_OLDMOD$L_MPSYNC = 5,0,32,1 %; ! Multi-processor sync time macro MNR_OLDMOD$L_KERNEL = 9,0,32,1 %; ! Kernel mode time macro MNR_OLDMOD$L_EXEC = 13,0,32,1 %; ! exec mode time macro MNR_OLDMOD$L_SUPER = 17,0,32,1 %; ! Supervisor mode time macro MNR_OLDMOD$L_USER = 21,0,32,1 %; ! User mode time macro MNR_OLDMOD$L_COMPAT = 25,0,32,1 %; ! Compatibility mode time macro MNR_OLDMOD$L_IDLE = 29,0,32,1 %; ! Idle time ! ***************************************************************************************** ! ! MSCP_SERVER class record format ! literal MNR_MSC$K_SIZE = 52; literal MNR_MSC$S_MSCP_CLASS = 56; macro MNR_MSC$L_REQUEST = 0,0,32,1 %; ! count of I/O transfer requests macro MNR_MSC$L_READ = 4,0,32,1 %; ! count of read requests macro MNR_MSC$L_WRITE = 8,0,32,1 %; ! count of write requests macro MNR_MSC$L_FRAGMENT = 12,0,32,1 %; ! count of extra fragments macro MNR_MSC$L_SPLIT = 16,0,32,1 %; ! count of fragmented requests macro MNR_MSC$L_BUFWAIT = 20,0,32,1 %; ! count of requests that had to wait for buffer memory macro MNR_MSC$L_SIZE1 = 24,0,32,1 %; ! count of 1 block I/O requests macro MNR_MSC$L_SIZE2 = 28,0,32,1 %; ! count of 2-3 block requests macro MNR_MSC$L_SIZE3 = 32,0,32,1 %; ! count of 4-7 block requests macro MNR_MSC$L_SIZE4 = 36,0,32,1 %; ! count of 8-15 block requests macro MNR_MSC$L_SIZE5 = 40,0,32,1 %; ! count of 16-31 block requests macro MNR_MSC$L_SIZE6 = 44,0,32,1 %; ! count of 32-63 block requests macro MNR_MSC$L_SIZE7 = 48,0,32,1 %; ! count of 64+ block requests ! ***************************************************************************************** ! ! PAGE class record format ! literal MNR_PAG$K_SIZE = 52; literal MNR_PAG$S_PAGE_CLASS = 56; macro MNR_PAG$L_FAULTS = 0,0,32,1 %; ! page faults macro MNR_PAG$L_PREADS = 4,0,32,1 %; ! page reads from disk macro MNR_PAG$L_PREADIO = 8,0,32,1 %; ! page read I/Os macro MNR_PAG$L_PWRITES = 12,0,32,1 %; ! page writes to pagefile macro MNR_PAG$L_PWRITIO = 16,0,32,1 %; ! page write I/Os macro MNR_PAG$L_FREFLTS = 20,0,32,1 %; ! faults from freelist macro MNR_PAG$L_MFYFLTS = 24,0,32,1 %; ! faults from modified list macro MNR_PAG$L_DZROFLTS = 28,0,32,1 %; ! demand-zero faults macro MNR_PAG$L_GVALID = 32,0,32,1 %; ! global valid faults macro MNR_PAG$L_WRTINPROG = 36,0,32,1 %; ! write-in-progress faults macro MNR_PAG$L_SYSFAULTS = 40,0,32,1 %; ! system faults macro MNR_PAG$L_FREECNT = 44,0,32,1 %; ! free page count macro MNR_PAG$L_MFYCNT = 48,0,32,1 %; ! modified page count ! ***************************************************************************************** ! ! PROCESS class record format ! ! Number of bytes for FAO stack (display buffer) ! for a single process (PROCESSES class) literal MNR_PRO$K_PSIZE = 8; literal MNR_PRO$S_PRO_CLASS_PRE = 8; macro MNR_PRO$L_PCTREC = 0,0,32,1 %; ! Count of processes in this record macro MNR_PRO$L_PCTINT = 4,0,32,1 %; ! Count of processes for this interval literal MNR_PRO$K_REV3DSIZE = 72; ! Revision Level 3 boundary literal MNR_PRO$K_REV4DSIZE = 96; ! Revision Level 4 boundary literal MNR_PRO$C_PRO_REV = 4; ! current revision is 4 literal MNR_PRO$K_SIZE = 96; literal MNR_PRO$K_DSIZE = 96; literal MNR_PRO$K_FSIZE = 64; literal MNR_PRO$S_PROCESS_CLASS = 96; macro MNR_PRO$L_IPID = 0,0,32,1 %; ! Internal PID macro MNR_PRO$L_UIC = 4,0,32,1 %; ! UIC (Member is low-order word) macro MNR_PRO$W_STATE = 8,0,16,1 %; ! State value macro MNR_PRO$B_PRI = 10,0,8,1 %; ! Priority (negative value) macro MNR_PRO$T_LNAME = 16,0,0,1 %; literal MNR_PRO$S_LNAME = 16; ! Process name (counted string) macro MNR_PRO$L_GPGCNT = 32,0,32,1 %; ! Global page count macro MNR_PRO$L_PPGCNT = 36,0,32,1 %; ! Process page count macro MNR_PRO$L_STS = 40,0,32,1 %; ! PCB Status Vector (PCB$V_RES bit clear => swapped out) macro MNR_PRO$L_DIOCNT = 44,0,32,1 %; ! Direct I/O count macro MNR_PRO$L_PAGEFLTS = 48,0,32,1 %; ! Page fault count macro MNR_PRO$L_CPUTIM = 52,0,32,1 %; ! Accumulated CPU time (in ticks) macro MNR_PRO$L_BIOCNT = 56,0,32,1 %; ! Buffered I/O count macro MNR_PRO$L_EPID = 60,0,32,1 %; ! Extended PID macro MNR_PRO$L_EFWM = 64,0,32,1 %; ! Event flag wait mask (for MWAITs) macro MNR_PRO$L_RBSTRAN = 68,0,32,1 %; ! Real balance slot transitions (or faults) macro MNR_PRO$L_KERNEL_COUNTER = 72,0,32,1 %; ! kernel mode counter for this process macro MNR_PRO$L_EXECUTIVE_COUNTER = 76,0,32,1 %; ! executive mode counter for this process macro MNR_PRO$L_SUPERVISOR_COUNTER = 80,0,32,1 %; ! supervisor mode counter for this process macro MNR_PRO$L_USER_COUNTER = 84,0,32,1 %; ! user mode counter for this process macro MNR_PRO$L_RESERVED2 = 88,0,32,1 %; ! Reserved # 2 for future expansion macro MNR_PRO$L_RESERVED1 = 92,0,32,1 %; ! Reserved # 1 for future expansion literal MNR_OLDPRO$K_REV0DSIZE = 55; ! Revision Level 0 boundary literal MNR_OLDPRO$K_REV1DSIZE = 63; ! Revision Level 1 boundary literal MNR_OLDPRO$K_REV2DSIZE = 67; ! Revision Level 2 boundary literal MNR_OLDPRO$C_PRO_REV = 2; ! old format revision is 2 literal MNR_OLDPRO$K_SIZE = 67; literal MNR_OLDPRO$K_DSIZE = 67; literal MNR_OLDPRO$S_OLDPROCESS_CLASS = 72; macro MNR_OLDPRO$L_IPID = 0,0,32,1 %; ! Internal PID macro MNR_OLDPRO$L_UIC = 4,0,32,1 %; ! UIC (Member is low-order word) macro MNR_OLDPRO$W_STATE = 8,0,16,1 %; ! State value macro MNR_OLDPRO$B_PRI = 10,0,8,1 %; ! Priority (negative value) macro MNR_OLDPRO$T_LNAME = 11,0,0,1 %; literal MNR_OLDPRO$S_LNAME = 16; ! Process name (counted string) macro MNR_OLDPRO$L_GPGCNT = 27,0,32,1 %; ! Global page count macro MNR_OLDPRO$L_PPGCNT = 31,0,32,1 %; ! Process page count macro MNR_OLDPRO$L_STS = 35,0,32,1 %; ! PCB Status Vector (PCB$V_RES bit clear => swapped out) macro MNR_OLDPRO$L_DIOCNT = 39,0,32,1 %; ! Direct I/O count macro MNR_OLDPRO$L_PAGEFLTS = 43,0,32,1 %; ! Page fault count macro MNR_OLDPRO$L_CPUTIM = 47,0,32,1 %; ! Accumulated CPU time (in ticks) macro MNR_OLDPRO$L_BIOCNT = 51,0,32,1 %; ! Buffered I/O count macro MNR_OLDPRO$L_EPID = 55,0,32,1 %; ! Extended PID macro MNR_OLDPRO$L_EFWM = 59,0,32,1 %; ! Event flag wait mask (for MWAITs) macro MNR_OLDPRO$L_RBSTRAN = 63,0,32,1 %; ! Real balance slot transitions (or faults) ! ***************************************************************************************** ! ! RLOCK class record format ! literal MNR_RLO$K_SIZE = 28; literal MNR_RLO$S_RLOCK_CLASS = 32; macro MNR_RLO$L_RM_UNLOAD = 0,0,32,1 %; ! count of trees moved from this node (outbound) macro MNR_RLO$L_RM_MORE_ACT = 4,0,32,1 %; ! trees moved because of higher activity macro MNR_RLO$L_RM_BETTER = 8,0,32,1 %; ! trees moved because of higher LOCKDIRWT macro MNR_RLO$L_RM_SINGLE = 12,0,32,1 %; ! trees moved to node because of sole interest macro MNR_RLO$L_RM_MSG_SENT = 16,0,32,1 %; ! remaster messages sent macro MNR_RLO$L_RM_ACQUIRE = 20,0,32,1 %; ! count of trees moved to this node (inbound) macro MNR_RLO$L_RM_MSG_RCV = 24,0,32,1 %; ! remaster messages received ! ***************************************************************************************** ! ! RMS class record format ! literal MNR_RMS$K_SIZE = 276; literal MNR_RMS$S_RMS_CLASS = 280; macro MNR_RMS$L_FILNUM = 0,0,32,1 %; ! sequential number of the file macro MNR_RMS$B_FILNUM = 0,0,8,1 %; macro MNR_RMS$L_ORG = 4,0,32,1 %; ! file organization macro MNR_RMS$L_RESERVED1 = 8,0,32,1 %; ! macro MNR_RMS$L_SEQGETS = 12,0,32,1 %; ! count of sequential $GETs macro MNR_RMS$L_KEYGETS = 16,0,32,1 %; ! count of keyed $GETs macro MNR_RMS$L_RFAGETS = 20,0,32,1 %; ! count of $GETs by record-file-address macro MNR_RMS$Q_GETBYTES = 24,0,0,1 %; literal MNR_RMS$S_GETBYTES = 8; ! total number of bytes required for all $GETs macro MNR_RMS$L_SEQPUTS = 32,0,32,1 %; ! count of sequential $PUTs macro MNR_RMS$L_KEYPUTS = 36,0,32,1 %; ! count of keyed $PUTs macro MNR_RMS$Q_PUTBYTES = 40,0,0,1 %; literal MNR_RMS$S_PUTBYTES = 8; ! total number of bytes required for all $PUTs macro MNR_RMS$L_UPDATES = 48,0,32,1 %; ! count of $UPDATEs macro MNR_RMS$Q_UPDATEBYTES = 52,0,0,1 %; literal MNR_RMS$S_UPDATEBYTES = 8; ! total number of bytes required for all $UPDATEs macro MNR_RMS$L_DELETES = 60,0,32,1 %; ! count of $DELETEs macro MNR_RMS$L_TRUNCATES = 64,0,32,1 %; ! count of $TRUNCATEs macro MNR_RMS$L_TRUNCBLKS = 68,0,32,1 %; ! total blocks required for all $TRUNCATEs macro MNR_RMS$L_SEQFINDS = 72,0,32,1 %; ! count of sequential $FINDs macro MNR_RMS$L_KEYFINDS = 76,0,32,1 %; ! count of keyed $FINDS macro MNR_RMS$L_RFAFINDS = 80,0,32,1 %; ! count of $FINDs by record-file-address macro MNR_RMS$L_READS = 84,0,32,1 %; ! count of $READS macro MNR_RMS$Q_READBYTES = 88,0,0,1 %; literal MNR_RMS$S_READBYTES = 8; ! total bytes required for all $READs macro MNR_RMS$L_CONNECTS = 96,0,32,1 %; ! count of $CONNECTs macro MNR_RMS$L_DISCONNECTS = 100,0,32,1 %; ! count of $DISCONNECTs macro MNR_RMS$L_EXTENDS = 104,0,32,1 %; ! count of $EXTENDs macro MNR_RMS$L_EXTBLOCKS = 108,0,32,1 %; ! total blocks required for all $EXTENDs macro MNR_RMS$L_FLUSHES = 112,0,32,1 %; ! count of $FLUSHes macro MNR_RMS$L_REWINDS = 116,0,32,1 %; ! count of $REWINDs macro MNR_RMS$L_WRITES = 120,0,32,1 %; ! count of $WRITEs macro MNR_RMS$Q_WRITEBYTES = 124,0,0,1 %; literal MNR_RMS$S_WRITEBYTES = 8; ! total number of bytes required for all $WRITEs macro MNR_RMS$L_FLCKENQS = 132,0,32,1 %; ! file lock $ENQs macro MNR_RMS$L_FLCKDEQS = 136,0,32,1 %; ! file lock $DEQs macro MNR_RMS$L_FLCKCNVS = 140,0,32,1 %; ! file lock conversions macro MNR_RMS$L_LBLCKENQS = 144,0,32,1 %; ! local buffer $ENQs macro MNR_RMS$L_LBLCKDEQS = 148,0,32,1 %; ! local buffer $DEQs macro MNR_RMS$L_LBLCKCNVS = 152,0,32,1 %; ! local buffer conversions macro MNR_RMS$L_GBLCKENQS = 156,0,32,1 %; ! global buffer $ENQs macro MNR_RMS$L_GBLCKDEQS = 160,0,32,1 %; ! global buffer $DEQs macro MNR_RMS$L_GBLCKCNVS = 164,0,32,1 %; ! global buffer conversions macro MNR_RMS$L_GSLCKENQS = 168,0,32,1 %; ! global section $ENQs macro MNR_RMS$L_GSLCKDEQS = 172,0,32,1 %; ! global section $DEQs macro MNR_RMS$L_GSLCKCNVS = 176,0,32,1 %; ! global section conversions macro MNR_RMS$L_RLLCKENQS = 180,0,32,1 %; ! record lock $ENQs macro MNR_RMS$L_RLLCKDEQS = 184,0,32,1 %; ! record lock $DEQs macro MNR_RMS$L_RLLCKCNVS = 188,0,32,1 %; ! record lock conversions macro MNR_RMS$L_APPLCKENQS = 192,0,32,1 %; ! append lock $ENQs macro MNR_RMS$L_APPLCKDEQS = 196,0,32,1 %; ! append lock $DEQs macro MNR_RMS$L_APPLCKCNVS = 200,0,32,1 %; ! append lock conversions macro MNR_RMS$L_FLBLKASTS = 204,0,32,1 %; ! file lock blocking ASTs macro MNR_RMS$L_LBLBLKASTS = 208,0,32,1 %; ! local buffer blocking ASTs macro MNR_RMS$L_GBLBLKASTS = 212,0,32,1 %; ! global buffer blocking ASTs macro MNR_RMS$L_APPBLKASTS = 216,0,32,1 %; ! append lock blocking ASTs macro MNR_RMS$L_LCACHEHITS = 220,0,32,1 %; ! local cache hits macro MNR_RMS$L_LCACHEATT = 224,0,32,1 %; ! local cache attempts macro MNR_RMS$L_GCACHEHITS = 228,0,32,1 %; ! global cache hits macro MNR_RMS$L_GCACHEATT = 232,0,32,1 %; ! global cache attempts macro MNR_RMS$L_GBRDIRIOS = 236,0,32,1 %; ! global buffer read I/Os macro MNR_RMS$L_GBWDIRIOS = 240,0,32,1 %; ! global buffer write I/Os macro MNR_RMS$L_LBRDIRIOS = 244,0,32,1 %; ! local buffer read I/Os macro MNR_RMS$L_LBWDIRIOS = 248,0,32,1 %; ! local buffer write I/Os macro MNR_RMS$L_BKTSPLT = 252,0,32,1 %; ! bucket splits macro MNR_RMS$L_MBKTSPLT = 256,0,32,1 %; ! multi-bucket splits macro MNR_RMS$L_OPENS = 260,0,32,1 %; ! count of $CLOSEs macro MNR_RMS$L_CLOSES = 264,0,32,1 %; ! count of $OPENs macro MNR_RMS$L_RESERVED2 = 268,0,32,1 %; ! macro MNR_RMS$L_RESERVED3 = 272,0,32,1 %; ! literal MNR_OLDRMS$K_SIZE = 273; literal MNR_OLDRMS$S_OLDRMS_CLASS = 280; macro MNR_OLDRMS$B_FILNUM = 0,0,8,1 %; ! sequential number of the file macro MNR_OLDRMS$L_ORG = 1,0,32,1 %; ! file organization macro MNR_OLDRMS$L_RESERVED1 = 5,0,32,1 %; ! macro MNR_OLDRMS$L_SEQGETS = 9,0,32,1 %; ! count of sequential $GETs macro MNR_OLDRMS$L_KEYGETS = 13,0,32,1 %; ! count of keyed $GETs macro MNR_OLDRMS$L_RFAGETS = 17,0,32,1 %; ! count of $GETs by record-file-address macro MNR_OLDRMS$Q_GETBYTES = 21,0,0,1 %; literal MNR_OLDRMS$S_GETBYTES = 8; ! total number of bytes required for all $GETs macro MNR_OLDRMS$L_SEQPUTS = 29,0,32,1 %; ! count of sequential $PUTs macro MNR_OLDRMS$L_KEYPUTS = 33,0,32,1 %; ! count of keyed $PUTs macro MNR_OLDRMS$Q_PUTBYTES = 37,0,0,1 %; literal MNR_OLDRMS$S_PUTBYTES = 8; ! total number of bytes required for all $PUTs macro MNR_OLDRMS$L_UPDATES = 45,0,32,1 %; ! count of $UPDATEs macro MNR_OLDRMS$Q_UPDATEBYTES = 49,0,0,1 %; literal MNR_OLDRMS$S_UPDATEBYTES = 8; ! total number of bytes required for all $UPDATEs macro MNR_OLDRMS$L_DELETES = 57,0,32,1 %; ! count of $DELETEs macro MNR_OLDRMS$L_TRUNCATES = 61,0,32,1 %; ! count of $TRUNCATEs macro MNR_OLDRMS$L_TRUNCBLKS = 65,0,32,1 %; ! total blocks required for all $TRUNCATEs macro MNR_OLDRMS$L_SEQFINDS = 69,0,32,1 %; ! count of sequential $FINDs macro MNR_OLDRMS$L_KEYFINDS = 73,0,32,1 %; ! count of keyed $FINDS macro MNR_OLDRMS$L_RFAFINDS = 77,0,32,1 %; ! count of $FINDs by record-file-address macro MNR_OLDRMS$L_READS = 81,0,32,1 %; ! count of $READS macro MNR_OLDRMS$Q_READBYTES = 85,0,0,1 %; literal MNR_OLDRMS$S_READBYTES = 8; ! total bytes required for all $READs macro MNR_OLDRMS$L_CONNECTS = 93,0,32,1 %; ! count of $CONNECTs macro MNR_OLDRMS$L_DISCONNECTS = 97,0,32,1 %; ! count of $DISCONNECTs macro MNR_OLDRMS$L_EXTENDS = 101,0,32,1 %; ! count of $EXTENDs macro MNR_OLDRMS$L_EXTBLOCKS = 105,0,32,1 %; ! total blocks required for all $EXTENDs macro MNR_OLDRMS$L_FLUSHES = 109,0,32,1 %; ! count of $FLUSHes macro MNR_OLDRMS$L_REWINDS = 113,0,32,1 %; ! count of $REWINDs macro MNR_OLDRMS$L_WRITES = 117,0,32,1 %; ! count of $WRITEs macro MNR_OLDRMS$Q_WRITEBYTES = 121,0,0,1 %; literal MNR_OLDRMS$S_WRITEBYTES = 8; ! total number of bytes required for all $WRITEs macro MNR_OLDRMS$L_FLCKENQS = 129,0,32,1 %; ! file lock $ENQs macro MNR_OLDRMS$L_FLCKDEQS = 133,0,32,1 %; ! file lock $DEQs macro MNR_OLDRMS$L_FLCKCNVS = 137,0,32,1 %; ! file lock conversions macro MNR_OLDRMS$L_LBLCKENQS = 141,0,32,1 %; ! local buffer $ENQs macro MNR_OLDRMS$L_LBLCKDEQS = 145,0,32,1 %; ! local buffer $DEQs macro MNR_OLDRMS$L_LBLCKCNVS = 149,0,32,1 %; ! local buffer conversions macro MNR_OLDRMS$L_GBLCKENQS = 153,0,32,1 %; ! global buffer $ENQs macro MNR_OLDRMS$L_GBLCKDEQS = 157,0,32,1 %; ! global buffer $DEQs macro MNR_OLDRMS$L_GBLCKCNVS = 161,0,32,1 %; ! global buffer conversions macro MNR_OLDRMS$L_GSLCKENQS = 165,0,32,1 %; ! global section $ENQs macro MNR_OLDRMS$L_GSLCKDEQS = 169,0,32,1 %; ! global section $DEQs macro MNR_OLDRMS$L_GSLCKCNVS = 173,0,32,1 %; ! global section conversions macro MNR_OLDRMS$L_RLLCKENQS = 177,0,32,1 %; ! record lock $ENQs macro MNR_OLDRMS$L_RLLCKDEQS = 181,0,32,1 %; ! record lock $DEQs macro MNR_OLDRMS$L_RLLCKCNVS = 185,0,32,1 %; ! record lock conversions macro MNR_OLDRMS$L_APPLCKENQS = 189,0,32,1 %; ! append lock $ENQs macro MNR_OLDRMS$L_APPLCKDEQS = 193,0,32,1 %; ! append lock $DEQs macro MNR_OLDRMS$L_APPLCKCNVS = 197,0,32,1 %; ! append lock conversions macro MNR_OLDRMS$L_FLBLKASTS = 201,0,32,1 %; ! file lock blocking ASTs macro MNR_OLDRMS$L_LBLBLKASTS = 205,0,32,1 %; ! local buffer blocking ASTs macro MNR_OLDRMS$L_GBLBLKASTS = 209,0,32,1 %; ! global buffer blocking ASTs macro MNR_OLDRMS$L_APPBLKASTS = 213,0,32,1 %; ! append lock blocking ASTs macro MNR_OLDRMS$L_LCACHEHITS = 217,0,32,1 %; ! local cache hits macro MNR_OLDRMS$L_LCACHEATT = 221,0,32,1 %; ! local cache attempts macro MNR_OLDRMS$L_GCACHEHITS = 225,0,32,1 %; ! global cache hits macro MNR_OLDRMS$L_GCACHEATT = 229,0,32,1 %; ! global cache attempts macro MNR_OLDRMS$L_GBRDIRIOS = 233,0,32,1 %; ! global buffer read I/Os macro MNR_OLDRMS$L_GBWDIRIOS = 237,0,32,1 %; ! global buffer write I/Os macro MNR_OLDRMS$L_LBRDIRIOS = 241,0,32,1 %; ! local buffer read I/Os macro MNR_OLDRMS$L_LBWDIRIOS = 245,0,32,1 %; ! local buffer write I/Os macro MNR_OLDRMS$L_BKTSPLT = 249,0,32,1 %; ! bucket splits macro MNR_OLDRMS$L_MBKTSPLT = 253,0,32,1 %; ! multi-bucket splits macro MNR_OLDRMS$L_OPENS = 257,0,32,1 %; ! count of $CLOSEs macro MNR_OLDRMS$L_CLOSES = 261,0,32,1 %; ! count of $OPENs macro MNR_OLDRMS$L_RESERVED2 = 265,0,32,1 %; ! macro MNR_OLDRMS$L_RESERVED3 = 269,0,32,1 %; ! ! ***************************************************************************************** ! ! SCS class record format ! literal MNR_SCS$K_SIZE = 56; literal MNR_SCS$S_SCS_CLASS = 56; macro MNR_SCS$T_NODENAME = 0,0,0,1 %; literal MNR_SCS$S_NODENAME = 8; ! node name macro MNR_SCS$L_DGSENT = 8,0,32,1 %; ! datagrams sent macro MNR_SCS$L_DGRCVD = 12,0,32,1 %; ! datagrams received macro MNR_SCS$L_DGDISCARD = 16,0,32,1 %; ! datagrams discarded macro MNR_SCS$L_MSGSENT = 20,0,32,1 %; ! sequenced messages sent macro MNR_SCS$L_MSGRCVD = 24,0,32,1 %; ! sequenced messages received macro MNR_SCS$L_SNDATS = 28,0,32,1 %; ! block transfer send commands macro MNR_SCS$L_KBYTSENT = 32,0,32,1 %; ! KBytes sent by send-data commands macro MNR_SCS$L_REQDATS = 36,0,32,1 %; ! block transfer request commands macro MNR_SCS$L_KBYTREQD = 40,0,32,1 %; ! KBytes received by request-data commands macro MNR_SCS$L_KBYTMAPD = 44,0,32,1 %; ! block transfer KBytes mapped macro MNR_SCS$L_QCRCNT = 48,0,32,1 %; ! connections queued for send credits macro MNR_SCS$L_QBDTCNT = 52,0,32,1 %; ! connections queued for buffer descriptors ! ***************************************************************************************** ! ! STATES class record format ! literal MNR_STA$K_SIZE = 56; literal MNR_STA$S_STATES_CLASS = 56; macro MNR_STA$L_COLPG = 0,0,32,1 %; ! collided page wait macro MNR_STA$L_MWAIT = 4,0,32,1 %; ! misc resource wait macro MNR_STA$L_CEF = 8,0,32,1 %; ! common event flag wait macro MNR_STA$L_PFW = 12,0,32,1 %; ! pagefault wait macro MNR_STA$L_LEF = 16,0,32,1 %; ! local event flag macro MNR_STA$L_LEFO = 20,0,32,1 %; ! local event flag (outswapped) macro MNR_STA$L_HIB = 24,0,32,1 %; ! hibernate macro MNR_STA$L_HIBO = 28,0,32,1 %; ! hibernate (outswapped) macro MNR_STA$L_SUSP = 32,0,32,1 %; ! suspended macro MNR_STA$L_SUSPO = 36,0,32,1 %; ! suspended (outswapped) macro MNR_STA$L_FPG = 40,0,32,1 %; ! free page wait macro MNR_STA$L_COM = 44,0,32,1 %; ! compute state macro MNR_STA$L_COMO = 48,0,32,1 %; ! compute state (outswapped) macro MNR_STA$L_CUR = 52,0,32,1 %; ! current ! ***************************************************************************************** ! ! SYSTEM class record format ! literal MNR_SYS$K_SIZE = 36; literal MNR_SYS$S_SYSTEM_CLASS = 40; macro MNR_SYS$L_BUSY = 0,0,32,1 %; ! CPU busy macro MNR_SYS$L_OTHSTAT = 4,0,32,1 %; ! other states macro MNR_SYS$L_PROCS = 8,0,32,1 %; ! process count macro MNR_SYS$L_FAULTS = 12,0,32,1 %; ! page faults macro MNR_SYS$L_PREADIO = 16,0,32,1 %; ! page read I/Os macro MNR_SYS$L_FREECNT = 20,0,32,1 %; ! number of pages on freelist macro MNR_SYS$L_MFYCNT = 24,0,32,1 %; ! number of pages on modified list macro MNR_SYS$L_DIRIO = 28,0,32,1 %; ! total direct I/O count macro MNR_SYS$L_BUFIO = 32,0,32,1 %; ! total buffered I/O count ! ***************************************************************************************** ! ! TIMER class record format ! literal MNR_TMR$K_SIZE = 16; literal MNR_TMR$S_TIMER_CLASS = 16; macro MNR_TMR$L_TQE_TOTAL = 0,0,32,1 %; ! total TQEs macro MNR_TMR$L_TQE_SYSUB = 4,0,32,1 %; ! system subroutine TQEs macro MNR_TMR$L_TQE_TIMER = 8,0,32,1 %; ! timer TQEs macro MNR_TMR$L_TQE_WAKEUP = 12,0,32,1 %; ! wakeup TQEs ! ***************************************************************************************** ! ! TRANSACTION class record format ! literal MNR_TRA$K_SIZE = 56; literal MNR_TRA$S_TRANS_CLASS = 56; macro MNR_TRA$L_STARTS = 0,0,32,1 %; ! count of start transactions macro MNR_TRA$L_PREPARES = 4,0,32,1 %; ! count of transactions that have been prepared macro MNR_TRA$L_ONE_PHASE = 8,0,32,1 %; ! count of one-phase commits macro MNR_TRA$L_COMMITS = 12,0,32,1 %; ! count of transactions committed macro MNR_TRA$L_ABORTS = 16,0,32,1 %; ! count of aborted transactions macro MNR_TRA$L_ENDS = 20,0,32,1 %; ! count of end transactions macro MNR_TRA$L_BRANCHS = 24,0,32,1 %; ! count of transaction branches started macro MNR_TRA$L_ADDS = 28,0,32,1 %; ! count of transaction branches added macro MNR_TRA$L_BUCKETS1 = 32,0,32,1 %; ! 0-1 second transactions macro MNR_TRA$L_BUCKETS2 = 36,0,32,1 %; ! 1-2 second transactions macro MNR_TRA$L_BUCKETS3 = 40,0,32,1 %; ! 2-3 second transactions macro MNR_TRA$L_BUCKETS4 = 44,0,32,1 %; ! 3-4 second transactions macro MNR_TRA$L_BUCKETS5 = 48,0,32,1 %; ! 4-5 second transactions macro MNR_TRA$L_BUCKETS6 = 52,0,32,1 %; ! 5+ second transactions !*** MODULE $MPWDEF *** literal MPW$C_MAINTAIN = 1; literal MPW$C_SVAPTE = 2; literal MPW$C_OPCCRASH = 3; literal MPW$C_PAGE_TABLE = 4; literal MPW$C_IDLE = 0; literal MPW$C_MAINT_STATE = 1; literal MPW$C_SELECTIVE = 2; literal MPW$C_CRASH_STATE = 3; literal MPW$C_MAXSTATE = 4; literal MPW$C_DPTSCAN = 0; literal MPW$C_DGBLSC = 1; literal MPW$C_RELPHD = 2; literal MPW$C_FREELIM = 3; literal MPW$C_MPWCHECK = 4; literal MPW$C_CRASH = 5; literal MPW$C_MAXID = 6; literal MPW$M_RCODE = %X'FF'; literal MPW$M_RMODIFIERS = %X'FF00'; literal MPW$M_RESERVED = %X'FF0000'; literal MPW$M_IDCODE = %X'FF000000'; literal MPW$M_LOLIMIT = %X'100'; literal MPW$S_MPWDEF = 4; ! Old size name - synonym literal MPW$S_MPW = 4; ! Basic request code/modifiers structure macro MPW$L_MPW_ARG = 0,0,32,1 %; ! Entire MPW structure macro MPW$V_RCODE = 0,0,8,0 %; literal MPW$S_RCODE = 8; ! Request Code Field macro MPW$V_RMODIFIERS = 0,8,8,0 %; literal MPW$S_RMODIFIERS = 8; ! Request Modifiers Field macro MPW$V_RESERVED = 0,16,8,0 %; literal MPW$S_RESERVED = 8; macro MPW$V_IDCODE = 0,24,8,0 %; literal MPW$S_IDCODE = 8; ! Requestor ID code Field ! Request modifiers for MAINTAIN request macro MPW$V_LOLIMIT = 0,8,1,0 %; ! New MPL low limit specified in R1 !*** MODULE $MTLDEF *** ! + ! MOUNTED VOLUME LIST ENTRY. ONE SUCH ENTRY APPEARS IN THE PROCESS MOUNTED ! VOLUME LIST FOR EACH VOLUME MOUNTED BY THE PROCESS AS /SHARE OR /NOSHARE. ! IN ADDITION, EACH VOLUME MOUNTED /SYSTEM OR /GROUP HAS AN ENTRY IN THE ! SYSTEM WIDE MOUNTED VOLUME LIST. ! - literal MTL$K_LENGTH = 32; ! LENGTH OF STRUCTURE literal MTL$C_LENGTH = 32; ! LENGTH OF STRUCTURE literal MTL$S_MTLDEF = 32; literal MTL$S_MTL = 32; macro MTL$L_MTLFL = 0,0,32,1 %; ! FORWARD LIST POINTER macro MTL$L_MTLBL = 4,0,32,1 %; ! BACK LIST POINTER macro MTL$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro MTL$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE CODE macro MTL$B_STATUS = 11,0,8,0 %; ! STATUS BYTE macro MTL$V_VOLSET = 11,0,1,0 %; ! ENTRY IS FOR A VOLUME SET macro MTL$V_RVTVCB = 11,1,1,0 %; ! Entry is for a RVT/VCB volume set macro MTL$L_UCB = 12,0,32,1 %; ! POINTER TO DEVICE UCB macro MTL$L_LOGNAME = 16,0,32,1 %; ! POINTER TO ASSOCIATED LOGICAL NAME macro MTL$L_LOGNAM2 = 20,0,32,1 %; ! POINTER TO ALTERNATE LOGICAL NAME macro MTL$L_UIC = 28,0,32,0 %; ! Owner UIC !*** MODULE $MPMDEF *** ! + ! MULTIPORT MEMORY (MA780/MA750) ADAPTER REGISTER OFFSET DEFINITIONS ! - ! ! The UETP for the MA780 depends on some of the following definitions. Please ! let someone in that group know if the definitions change substantially. ! literal MPM$C_PORTS = 4; ! MAXIMUM NUMBER OF PORTS PER MEMORY literal MPM$M_CSR_PORT = %X'3'; literal MPM$M_CSR_ADCOD = %X'FF'; literal MPM$M_CSR_PU = %X'400000'; literal MPM$M_CSR_PD = %X'800000'; literal MPM$M_CSR_XMFLT = %X'4000000'; literal MPM$M_CSR_MT = %X'8000000'; literal MPM$M_CSR_IS = %X'10000000'; literal MPM$M_CSR_WS = %X'40000000'; literal MPM$M_CSR_PE = %X'80000000'; literal MPM$C_CSR_TYPE = 64; ! MULTIPORT ADAPTER TYPE CODE literal MPM$M_CR_MIE = %X'1'; literal MPM$M_CR_EIE = %X'2'; literal MPM$M_CR_ERRS = %X'FF000000'; literal MPM$M_SR_EIE = %X'2'; literal MPM$M_SR_SS = %X'2000'; literal MPM$M_SR_IDL = %X'4000'; literal MPM$M_SR_IT = %X'8000'; literal MPM$M_SR_AGP = %X'10000000'; literal MPM$M_SR_XDF = %X'20000000'; literal MPM$M_SR_MXF = %X'40000000'; literal MPM$M_SR_ACA = %X'80000000'; literal MPM$M_INV_ID = %X'FFFF'; literal MPM$M_INV_MEMSZ = %X'70000'; literal MPM$M_INV_STADR = %X'7FF00000'; literal MPM$M_INV_CACHF = %X'80000000'; literal MPM$M_ERR_ELR = %X'10000000'; literal MPM$M_ERR_HI = %X'20000000'; literal MPM$M_ERR_ICRD = %X'40000000'; literal MPM$M_ERR_IMP = %X'80000000'; literal MPM$M_CSR1_MIA = %X'400'; literal MPM$S_MPMDEF = 40; ! Old size name - synonym literal MPM$S_MPM = 40; macro MPM$L_CSR = 0,0,32,0 %; ! CONFIGURATION STATUS REGISTER macro MPM$V_CSR_PORT = 0,0,2,0 %; literal MPM$S_CSR_PORT = 2; ! PORT NUMBER macro MPM$V_CSR_ADCOD = 0,0,8,0 %; literal MPM$S_CSR_ADCOD = 8; ! ADAPTER CODE FIELD macro MPM$V_CSR_PU = 0,22,1,0 %; ! ADAPTER POWER UP macro MPM$V_CSR_PD = 0,23,1,0 %; ! ADAPTER POWER DOWN macro MPM$V_CSR_XMFLT = 0,26,1,0 %; ! TRANSMITTER FAULT macro MPM$V_CSR_MT = 0,27,1,0 %; ! MULTIPLE TRANSMITTERS macro MPM$V_CSR_IS = 0,28,1,0 %; ! INTERLOCK SEQUENCE macro MPM$V_CSR_WS = 0,30,1,0 %; ! WRITE SEQUENCE DATA macro MPM$V_CSR_PE = 0,31,1,0 %; ! SBI PARITY ERROR macro MPM$L_CR = 4,0,32,0 %; ! CONTROL REGISTER macro MPM$V_CR_MIE = 4,0,1,0 %; ! MASTER INTERRUPT ENABLE macro MPM$V_CR_EIE = 4,1,1,0 %; ! ERROR INTERRUPT ENABLE macro MPM$V_CR_ERRS = 4,24,8,0 %; literal MPM$S_CR_ERRS = 8; ! PORT INTERFACE ERRORS macro MPM$L_SR = 8,0,32,0 %; ! STATUS REGISTER macro MPM$V_SR_EIE = 8,1,1,0 %; ! ERROR INTERRUPT ENABLE macro MPM$V_SR_SS = 8,13,1,0 %; ! SINGLE STEP macro MPM$V_SR_IDL = 8,14,1,0 %; ! INVALIDATE DATA LOST IN MPC macro MPM$V_SR_IT = 8,15,1,0 %; ! INTERLOCK TIMEOUT macro MPM$V_SR_AGP = 8,28,1,0 %; ! ADMI GRANT PARITY ERROR macro MPM$V_SR_XDF = 8,29,1,0 %; ! XMIT DURING FAULT macro MPM$V_SR_MXF = 8,30,1,0 %; ! MULTIPLE XMITTER FAULT macro MPM$V_SR_ACA = 8,31,1,0 %; ! ADMI COMMAND ABORT macro MPM$L_INV = 12,0,32,0 %; ! INVALIDATION CONTROL REGISTER macro MPM$V_INV_ID = 12,0,16,0 %; literal MPM$S_INV_ID = 16; ! CACHED DEVICE NEXUS ID'S macro MPM$V_INV_MEMSZ = 12,16,3,0 %; literal MPM$S_INV_MEMSZ = 3; ! MEMORY SIZE (256KB BOARDS) macro MPM$V_INV_STADR = 12,20,11,0 %; literal MPM$S_INV_STADR = 11; ! STARTING SBI ADDR OF MEMORY macro MPM$V_INV_CACHF = 12,31,1,0 %; ! CACHED FORCE (IGNORE ID'S) macro MPM$L_ERR = 16,0,32,0 %; ! ARRAY ERROR REGISTER macro MPM$V_ERR_ELR = 16,28,1,0 %; ! ERROR LOG REQUEST macro MPM$V_ERR_HI = 16,29,1,0 %; ! HIGH ERROR RATE macro MPM$V_ERR_ICRD = 16,30,1,0 %; ! INHIBIT CRD ERRORS macro MPM$V_ERR_IMP = 16,31,1,0 %; ! INVALIDATE MAP PARITY ERROR macro MPM$L_CSR0 = 20,0,32,0 %; ! CONFIGURATION STATUS REGISTER 0 macro MPM$V_CSR0_POW = 20,4,4,0 %; literal MPM$S_CSR0_POW = 4; ! PER PORT POWER STATUS macro MPM$V_CSR0_ERR = 20,8,4,0 %; literal MPM$S_CSR0_ERR = 4; ! PER PORT ERROR STATUS macro MPM$V_CSR0_ONL = 20,12,4,0 %; literal MPM$S_CSR0_ONL = 4; ! PER PORT ONLINE STATUS macro MPM$L_CSR1 = 24,0,32,0 %; ! CONFIGURATION STATUS REGISTER 1 macro MPM$V_CSR1_MIA = 24,10,1,0 %; ! MULTIPLE INTERLOCK ACCEPTED macro MPM$L_MR = 28,0,32,0 %; ! MAINTENANCE REGISTER macro MPM$V_MR_UNIT = 28,14,2,0 %; literal MPM$S_MR_UNIT = 2; ! MEMORY UNIT NUMBER macro MPM$L_IIR = 32,0,32,0 %; ! INTERPORT INTERRUPT REQUEST REGISTER macro MPM$V_IIR_STS = 32,0,16,0 %; literal MPM$S_IIR_STS = 16; ! STATUS BITS (WRITE TO CLEAR) macro MPM$V_IIR_CTL = 32,16,16,0 %; literal MPM$S_IIR_CTL = 16; ! CONTROL BITS (WRITE TO SET STATUS BITS) macro MPM$L_IIE = 36,0,32,0 %; ! INTERPORT INTERRUPT ENABLE REGISTER macro MPM$V_IIE_STS = 36,0,16,0 %; literal MPM$S_IIE_STS = 16; ! CONTROL BITS (WRITE TO CLEAR) macro MPM$V_IIE_CTL = 36,16,16,0 %; literal MPM$S_IIE_CTL = 16; ! STATUS BITS (WRITE TO SET STATUS BITS) !*** MODULE $MSLGDEF *** ! + ! MSLG, MScp error LoG message definitions ! These definitions describe the format of the error log messages ! generated by MSCP and TMSCP devices. ! - ! ! Generic MSCP/TMSCP error log entry format ! literal MSLG$M_LF_SQNRS = %X'1'; literal MSLG$M_LF_RPLER = %X'10'; literal MSLG$M_LF_BBR = %X'20'; literal MSLG$M_LF_CONT = %X'40'; literal MSLG$M_LF_SUCC = %X'80'; literal MSLG$K_CNT_ERR = 0; literal MSLG$K_BUS_ADDR = 1; literal MSLG$K_DISK_TRN = 2; literal MSLG$K_SDI = 3; literal MSLG$K_SML_DSK = 4; literal MSLG$K_TAPE_TRN = 5; literal MSLG$K_STI_ERR = 6; literal MSLG$K_STI_DEL = 7; literal MSLG$K_STI_FEL = 8; literal MSLG$K_REPLACE = 9; literal MSLG$K_LDR_ERR = 10; literal MSLG$S_MSLG_CNT_ERR = 23; ! Old size name for MSLG_CNT_ERR aggregate literal MSLG$S_MSLG_BUS_ADDR = 28; ! Old size name for MSLG_BUS_ADDR aggregate literal MSLG$M_LFR_BR = %X'400'; literal MSLG$M_LFR_RI = %X'800'; literal MSLG$M_LFR_RF = %X'1000'; literal MSLG$M_LFR_TE = %X'2000'; literal MSLG$M_LFR_FE = %X'4000'; literal MSLG$M_LFR_RP = %X'8000'; literal MSLG$S_MSLG_SML_DSK = 41; ! Old size name for MSLG_SML_DSK aggregate. literal MSLG$S_GENERIC_MSCP_ERRLOG = 44; macro MSLG$L_CMD_REF = 0,0,32,0 %; ! Command reference number macro MSLG$W_UNIT = 4,0,16,0 %; ! Unit number macro MSLG$W_SEQ_NUM = 6,0,16,0 %; ! Sequence Number macro MSLG$B_FORMAT = 8,0,8,0 %; ! Format macro MSLG$B_FLAGS = 9,0,8,0 %; ! Error Log Message Flags macro MSLG$V_LF_SQNRS = 9,0,1,0 %; ! Sequence Number Reset macro MSLG$V_LF_RPLER = 9,4,1,0 %; ! Error during replacement macro MSLG$V_LF_BBR = 9,5,1,0 %; ! Bad block replacement request macro MSLG$V_LF_CONT = 9,6,1,0 %; ! Operation continuing macro MSLG$V_LF_SUCC = 9,7,1,0 %; ! Operation successful macro MSLG$W_EVENT = 10,0,16,0 %; ! Event Code macro MSLG$Q_CNT_ID = 12,0,0,0 %; literal MSLG$S_CNT_ID = 8; ! Controller ID macro MSLG$B_CNT_SVR = 20,0,8,0 %; ! Controller software version macro MSLG$B_CNT_HVR = 21,0,8,0 %; ! Controller hardware version macro MSLG$W_MULT_UNT = 22,0,16,0 %; ! Multi-unit Code macro MSLG$Z_CNT_ERR = 22,0,8,1 %; ! Controller dependent data - previously contained ! in MSLG_CNT_ERR aggregate ! Controller Error (MSLG$K_CNT_ERR) macro MSLG$Q_UNIT_ID = 24,0,0,0 %; literal MSLG$S_UNIT_ID = 8; ! Unit ID macro MSLG$L_BUS_ADDR = 24,0,32,1 %; ! Host Memory Access Error (MSLG$K_BUS_ADDR) ! Bus Address - previously contained in ! MSLG_BUS_ADDR aggregate macro MSLG$B_UNIT_SVR = 32,0,8,0 %; ! Unit software version macro MSLG$B_UNIT_HVR = 33,0,8,0 %; ! Unit hardware version macro MSLG$B_LEVEL = 34,0,8,0 %; ! Level macro MSLG$B_RETRY = 35,0,8,0 %; ! Retry macro MSLG$W_SDE_CYL = 34,0,16,0 %; ! Cylinder - used in MSLG_SML_DSK for MSLG$K_SML_DSK macro MSLG$W_RPL_FLGS = 34,0,16,0 %; ! Replace Flags - used in MSLG_REPLACE for MSLG$K_REPLACE macro MSLG$V_LFR_BR = 34,10,1,0 %; ! Bad RBN macro MSLG$V_LFR_RI = 34,11,1,0 %; ! RCT inconsistent macro MSLG$V_LFR_RF = 34,12,1,0 %; ! Reformat error macro MSLG$V_LFR_TE = 34,13,1,0 %; ! Tertiary revector macro MSLG$V_LFR_FE = 34,14,1,0 %; ! Forced error (data not recovered) macro MSLG$V_LFR_RP = 34,15,1,0 %; ! Replace attempted (block really bad) macro MSLG$L_VOL_SER = 36,0,32,0 %; ! Volume Serial Number (disks) macro MSLG$L_GAP_CNT = 36,0,32,0 %; ! Position - object count (tapes) macro MSLG$B_FMTR_SVR = 40,0,8,0 %; ! Formatter software version macro MSLG$B_FMTR_HVR = 41,0,8,0 %; ! Formatter hardware version macro MSLG$L_HDR_CODE = 40,0,32,0 %; ! Header Code - from MSLG_DISK_TRN aggregate for ! Disk Transfer Error (MSLG$K_DISK_TRN) macro MSLG$L_BAD_LBN = 40,0,32,0 %; ! Bad LBN - from MSLG_REPLACE aggregate for ! Bad Block Replacement Attempted (MSLG$K_REPLACE macro MSLG$Z_SML_DSK = 40,0,8,1 %; ! Controller or device dependent - used in MSLG_SML_DSK macro MSLG$Q_ML_ID = 36,0,0,0 %; literal MSLG$S_ML_ID = 8; ! Media loader identifier - ! used in MSLG_LDR_ERR for MSLG$K_LDR_ERR ! ! Controller Error (MSLG$K_CNT_ERR) ! ! Aggregate MSLG_CNT_ERR has been removed and it's fields have been ! incorporated into GENERIC_MSCP_ERRLOG. The following fields are ! specific to this error: ! CNT_ERR byte tag Z; /* Controller dependent data - this field is now ! ! Host Memory Access Error (MSLG$K_BUS_ADDR) ! ! Aggregate MSLG_BUS_ADDR has been removed and it's fields have been ! incorporated into GENERIC_MSCP_ERRLOG. The following fields are ! specific to this error: ! BUS_ADDR longword unsigned; /* Bus Address ! ! Disk Transfer Error (MSLG$K_DISK_TRN) ! literal MSLG$K_DISK_TRN_MSGSIZ = 44; ! Size of DISK_TRN_ERROR msg. literal MSLG$S_MSLG_DISK_TRN = 45; ! HDR_CODE - is now located in GENERIC_MSCP_ERRLOG macro MSLG$Z_DISK_TRN = 44,0,8,1 %; ! Controller or disk dependent data ! ! SDI Error (MSLG$K_SDI) ! literal MSLG$S_MSLG_SDI = 56; macro MSLG$Z_SDI = 44,0,0,0 %; literal MSLG$S_SDI = 12; ! SDI Information ! ! Small Disk Error (MSLG$K_SML_DSK) ! ! Aggregate MSLG_SML_DSK has been removed and it's fields have been ! incorporated into GENERIC_MSCP_ERRLOG. The following fields are ! specific to this error: ! SDE_CYL word unsigned; /* Cylinder ! SML_DSK byte tag Z; /* Controller or device dependent ! ! Tape Transfer Error (MSLG$K_STI_ERR) ! ! There are no special field definitions for tape transfer errors at this time. ! ! STI communication or command failure (MSLG$K_STI_ERR) ! STI drive error log (MSLG$K_STI_DEL) ! STI formatter error log (MSLG$K_STI_FEL) ! literal MSLG$S_MSLG_STI_ERR = 64; macro MSLG$Z_STI = 44,0,0,0 %; literal MSLG$S_STI = 20; ! STI Information ! ! Bad Block Replacement Attempted (MSLG$K_REPLACE) ! literal MSLG$K_REPLACE_MSGSIZ = 54; ! Size of REPLACE msg for BBR error logging literal MSLG$S_MSLG_REPLACE = 54; ! Replace Flags now located in GENERIC_MSCP_ERRLOG macro MSLG$L_OLD_RBN = 44,0,32,0 %; ! Previous RBN macro MSLG$L_NEW_RBN = 48,0,32,0 %; ! New RBN macro MSLG$W_CAUSE = 52,0,16,0 %; ! Event code causing replacement ! ! Media Loader Errors (MSLG$K_LDR_ERR) ! literal MSLG$S_MSLG_LDR_ERR = 49; ! The following fields have been moved to GENERIC_MSCP_ERRLOG macro MSLG$B_ML_SVR = 44,0,8,0 %; ! Media loader software version macro MSLG$B_ML_HVR = 45,0,8,0 %; ! Media loader hardware version macro MSLG$W_ML_UNIT = 46,0,16,0 %; ! Media loader unit number macro MSLG$Z_LDR_ERR = 48,0,8,1 %; ! Controller dependent data !*** MODULE $MSCPDEF *** ! ++ ! MSCP (Mass Storage Control Protocol) Definitions ! ! These definitions describe the format of the command and end message ! packets exchanged under MSCP between the host and the controller. ! -- literal MSCP$M_EU_NO = %X'FF'; literal MSCP$M_EU_SUBU = %X'7'; literal MSCP$M_EU_SUBC = %X'F8'; literal MSCP$K_EMS_CNSL = 0; literal MSCP$K_EMS_RP = 1; literal MSCP$K_EMS_RM = 2; literal MSCP$K_EMS_RK = 3; literal MSCP$K_EMS_RL = 4; literal MSCP$K_EMS_RX = 5; literal MSCP$K_EMS_FD1 = 6; literal MSCP$K_EMS_FD2 = 7; literal MSCP$K_EMS_FD3 = 8; literal MSCP$K_EMS_FD4 = 9; literal MSCP$K_EMS_FD5 = 10; literal MSCP$K_EMS_FD6 = 11; literal MSCP$K_EMS_FD7 = 12; literal MSCP$K_EMS_FD8 = 13; literal MSCP$M_EU_CTYPE = %X'F00'; literal MSCP$K_EMD_OLD = 0; literal MSCP$K_EMD_UDA = 1; literal MSCP$K_EMD_HSC = 2; literal MSCP$K_EMD_AZT = 3; literal MSCP$K_EMD_RDRX = 4; literal MSCP$K_EMD_EMUL = 5; literal MSCP$M_EU_DESIG = %X'7000'; literal MSCP$M_SHADOW = %X'8000'; literal MSCP$M_OP_ATTN = %X'40'; literal MSCP$M_OP_END = %X'80'; literal MSCP$M_MD_SEREC = %X'100'; literal MSCP$M_MD_SECOR = %X'200'; literal MSCP$M_MD_CLSEX = %X'2000'; literal MSCP$M_MD_COMP = %X'4000'; literal MSCP$M_MD_WRSEQ = %X'10'; literal MSCP$M_MD_WBKVL = %X'20'; literal MSCP$M_MD_WBKNV = %X'40'; literal MSCP$M_MD_SSHDW = %X'80'; literal MSCP$M_MD_SCCHL = %X'400'; literal MSCP$M_MD_SCCHH = %X'800'; literal MSCP$M_MD_ERROR = %X'1000'; literal MSCP$M_MD_EXPRS = %X'8000'; literal MSCP$M_MD_REWND = %X'2'; literal MSCP$M_MD_OBJCT = %X'4'; literal MSCP$M_MD_REVRS = %X'8'; literal MSCP$M_MD_UNLOD = %X'10'; literal MSCP$M_MD_IMMED = %X'40'; literal MSCP$M_MD_DLEOT = %X'80'; literal MSCP$M_MD_INHERLOG = %X'200'; literal MSCP$M_MD_CDATL = %X'1000'; literal MSCP$M_MD_SPNDW = %X'1'; literal MSCP$M_MD_ALLCD = %X'2'; literal MSCP$M_MD_DSOLV = %X'10'; literal MSCP$M_MD_FLENU = %X'1'; literal MSCP$M_MD_VOLTL = %X'2'; literal MSCP$M_MD_NXUNT = %X'1'; literal MSCP$M_MD_RIP = %X'1'; literal MSCP$M_MD_IGNMF = %X'2'; literal MSCP$M_MD_STWRP = %X'4'; literal MSCP$M_MD_CLWBL = %X'8'; literal MSCP$M_MD_SHDSP = %X'10'; literal MSCP$M_MD_EXCAC = %X'20'; literal MSCP$M_MD_PRIMR = %X'1'; literal MSCP$M_MD_CRNPR = %X'1'; literal MSCP$M_MD_ENRWR = %X'10'; literal MSCP$M_MD_TBC = %X'8000'; literal MSCP$M_MD_HISLO = %X'8'; literal MSCP$M_MD_SUPWL = %X'10'; literal MSCP$M_MD_REUSE = %X'80'; literal MSCP$M_MD_LOCSU = %X'1'; literal MSCP$M_MD_ESTCP = %X'2'; literal MSCP$M_MD_RETCP = %X'4'; literal MSCP$S_MSCP_MODIFIERS = 12; ! MSCP_MODIFIERS used to be an aggregate. ! We need to generate the old size field literal MSCP$M_EF_CPRET = %X'1'; literal MSCP$M_EF_DLS = %X'2'; literal MSCP$M_EF_PLS = %X'4'; literal MSCP$M_EF_EOT = %X'8'; literal MSCP$M_EF_SEREX = %X'10'; literal MSCP$M_EF_ERLOG = %X'20'; literal MSCP$M_EF_BBLKU = %X'40'; literal MSCP$M_EF_BBLKR = %X'80'; literal MSCP$M_EF_HISLO = %X'4'; literal MSCP$M_EF_ALLOF = %X'8'; literal MSCP$M_EF_FASTSKIP_USED = %X'80'; literal MSCP$M_ST_MASK = %X'1F'; literal MSCP$K_ST_SUCC = 0; literal MSCP$K_ST_ICMD = 1; literal MSCP$K_ST_ABRTD = 2; literal MSCP$K_ST_OFFLN = 3; literal MSCP$K_ST_AVLBL = 4; literal MSCP$K_ST_MFMTE = 5; literal MSCP$K_ST_WRTPR = 6; literal MSCP$K_ST_COMP = 7; literal MSCP$K_ST_DATA = 8; literal MSCP$K_ST_HSTBF = 9; literal MSCP$K_ST_CNTLR = 10; literal MSCP$K_ST_DRIVE = 11; literal MSCP$K_ST_FMTER = 12; literal MSCP$K_ST_BOT = 13; literal MSCP$K_ST_TAPEM = 14; literal MSCP$K_ST_SHST = 12; literal MSCP$K_ST_WHEAE = 13; literal MSCP$K_ST_RDTRN = 16; literal MSCP$K_ST_PLOST = 17; literal MSCP$K_ST_PRESE = 18; literal MSCP$K_ST_LED = 19; literal MSCP$K_ST_BBR = 20; literal MSCP$K_ST_IPARM = 21; literal MSCP$K_ST_INFO = 22; literal MSCP$K_ST_LOADR = 23; literal MSCP$K_ST_HOST = 24; literal MSCP$K_ST_UNREC = 20; literal MSCP$K_ST_SBCERR = 30; literal MSCP$K_ST_DIAG = 31; literal MSCP$K_ST_SBCOD = 32; literal MSCP$M_ST_SBCOD = %X'FFE0'; literal MSCP$K_SC_NORML = 0; ! Normal literal MSCP$K_SC_SDIGN = 1; ! Spin Down IGNored literal MSCP$K_SC_STCON = 2; ! STill CONnected literal MSCP$K_SC_DUPUN = 4; ! DUPlicate UNit number literal MSCP$K_SC_ALONL = 8; ! ALready ONLine literal MSCP$K_SC_STONL = 16; ! STill ONLine literal MSCP$K_SC_EOT = 32; ! EOT encountered (tapes only) literal MSCP$K_SC_INREP = 32; ! INcomplete REPlacement (disks only) literal MSCP$K_SC_IVRCT = 64; ! InValid RCT (disks only) literal MSCP$K_SC_RDONY = 128; ! ReaD ONlY volume format literal MSCP$M_SC_SDIGN = %X'20'; literal MSCP$M_SC_STCON = %X'40'; literal MSCP$M_SC_DUPUN = %X'80'; literal MSCP$M_SC_ALONL = %X'100'; literal MSCP$M_SC_STONL = %X'200'; literal MSCP$M_SC_EOT = %X'400'; literal MSCP$M_SC_INREP = %X'400'; literal MSCP$M_SC_IVRCT = %X'800'; literal MSCP$M_SC_RDONY = %X'1000'; literal MSCP$K_SC_INVML = 0; ! INValid Message Length ! Unit-Offline Subcode Values literal MSCP$K_SC_UNKNO = 0; ! UNKoNOwn unit or online to another controller literal MSCP$K_SC_NOVOL = 1; ! NO VOLume mounted or drive disabled (RUN/STOP) literal MSCP$K_SC_INOPR = 2; ! unit is INOPeRative literal MSCP$K_SC_UDSBL = 8; ! Unit disabled by field service or diagnostic literal MSCP$K_SC_EXUSE = 16; ! Exclusive use literal MSCP$K_SC_LDR = 32; ! Loader cycle error literal MSCP$M_SC_NOVOL = %X'20'; literal MSCP$M_SC_INOPR = %X'40'; literal MSCP$M_SC_UDSBL = %X'100'; literal MSCP$M_SC_EXUSE = %X'200'; literal MSCP$M_SC_LDR = %X'400'; literal MSCP$K_SC_CPYIP = 2; ! Copy in progress literal MSCP$K_SC_NOMEM = 4; ! No members in shadow set literal MSCP$K_SC_ALUSE = 32; ! Already in use literal MSCP$M_SC_CPYIP = %X'40'; literal MSCP$M_SC_NOMEM = %X'80'; literal MSCP$M_SC_ALUSE = %X'400'; literal MSCP$K_SC_IVHD = 2; literal MSCP$K_SC_NOSYNC = 3; literal MSCP$K_SC_SSCM = 4; literal MSCP$K_SC_NO512 = 5; literal MSCP$K_SC_NOFMT = 6; literal MSCP$K_SC_ECCER = 7; literal MSCP$K_SC_RCTBD = 8; literal MSCP$K_SC_NORBL = 9; ! Write-Protected Subcode Values literal MSCP$K_SC_DATAL = 8; ! Unit is DATA Loss write protected (data safety) literal MSCP$K_SC_SOFTW = 128; ! Unit is SOFTWare protected literal MSCP$K_SC_HARDW = 256; ! Unit is HARDWare protected literal MSCP$M_SC_DATAL = %X'100'; literal MSCP$M_SC_SOFTW = %X'1000'; literal MSCP$M_SC_HARDW = %X'2000'; literal MSCP$K_SC_FRCER = 0; ! Forced Error (disks) literal MSCP$K_SC_LGE = 0; ! Long Gap Encountered (tapes) literal MSCP$K_SC_MEDIA = 3; ! Media error. ! Host Buffer Access Error Subcode Values literal MSCP$K_SC_ODDTA = 1; literal MSCP$K_SC_ODDBC = 2; literal MSCP$K_SC_NXM = 3; literal MSCP$K_SC_MPAR = 4; literal MSCP$K_SC_IVPTE = 5; literal MSCP$K_SC_IVBFN = 6; literal MSCP$K_SC_BLENV = 7; literal MSCP$K_SC_ACVIO = 8; ! Controller Error Subcode Values literal MSCP$K_SC_DLATE = 1; literal MSCP$K_SC_EDCER = 2; literal MSCP$K_SC_DTSTR = 3; literal MSCP$K_SC_IEDC = 4; literal MSCP$K_SC_LACIN = 5; literal MSCP$K_SC_LACOU = 6; literal MSCP$K_SC_LACCB = 7; literal MSCP$K_SC_OVRUN = 8; literal MSCP$K_SC_MEMER = 9; literal MSCP$K_SC_REMRSRC = 10; literal MSCP$K_SC_RCONL = 20; literal MSCP$K_SC_RCONF = 21; literal MSCP$K_SC_BADSA = 22; literal MSCP$K_SC_NOSER = 23; literal MSCP$K_SC_NORES = 24; literal MSCP$K_SC_NOCRE = 25; literal MSCP$K_SC_BADPR = 26; literal MSCP$K_SC_NEGAK = 27; literal MSCP$K_SC_TMOUT = 28; literal MSCP$K_SC_LCONF = 29; literal MSCP$K_SC_DISCN = 30; ! Bad Block Replacement Subcode Values literal MSCP$K_SC_BBROK = 0; literal MSCP$K_SC_NOTRP = 1; literal MSCP$K_SC_RPLFL = 2; literal MSCP$K_SC_ICRCT = 3; literal MSCP$K_SC_DRVER = 4; literal MSCP$K_SC_RCTFULL = 5; literal MSCP$K_SC_RECURFAIL = 6; ! Unrecognized Media Subcode Values literal MSCP$K_SC_NOTAPEFMT = 1; ! Invalid Parameter Subcode Values literal MSCP$K_SC_IVKLN = 1; literal MSCP$K_SC_IVKTY = 2; literal MSCP$K_SC_IVKVL = 3; ! Media Loader Error Subcode Values literal MSCP$K_SC_ML_TMO = 1; literal MSCP$K_SC_ML_TXERR = 2; literal MSCP$K_SC_ML_PRTCL = 3; literal MSCP$K_SC_ML_ERROR = 4; ! Host Error Subcode Values literal MSCP$K_SC_SEGUNDR = 1; ! Write History Entry Access Error Subcode Values literal MSCP$K_SC_ALLOF = 1; literal MSCP$K_SC_TABFU = 2; literal MSCP$K_SC_NOENT = 8; literal MSCP$M_SC_ALLOF = %X'2'; literal MSCP$M_SC_TABFU = %X'4'; literal MSCP$M_SC_NOENT = %X'10'; literal MSCP$K_SC_DCDC = 3; ! Subcommand Error Status or Event Subcode Values literal MSCP$K_SC_DST_TIMOUT = 1; literal MSCP$K_SC_DST_INCSTA = 2; literal MSCP$K_SC_DST_UNRCOV = 4; literal MSCP$K_SC_SRC_TIMOUT = 1025; literal MSCP$K_SC_SRC_INCSTA = 1026; literal MSCP$K_SC_SRC_UNRCOV = 1028; literal MSCP$S_MSCP_SUBCODES = 12; literal MSCP$S_MSCP_BASIC_PKT = 12; macro MSCP$L_CMD_REF = 0,0,32,0 %; ! Command reference number macro MSCP$W_UNIT = 4,0,16,0 %; ! Unit number macro MSCP$V_EU_NO = 4,0,8,0 %; literal MSCP$S_EU_NO = 8; ! Emulated unit number macro MSCP$V_EU_SUBU = 4,0,3,0 %; literal MSCP$S_EU_SUBU = 3; ! Old-style unit number macro MSCP$V_EU_SUBC = 4,3,5,0 %; literal MSCP$S_EU_SUBC = 5; ! Old-style controller subtype macro MSCP$V_EU_CTYPE = 4,8,4,0 %; literal MSCP$S_EU_CTYPE = 4; ! Emulated controller type macro MSCP$V_EU_DESIG = 4,12,3,0 %; literal MSCP$S_EU_DESIG = 3; ! Emulated controller designator macro MSCP$V_SHADOW = 4,15,1,0 %; ! Shadow unit macro MSCP$B_CNT_ALCS = 4,0,8,0 %; macro MSCP$W_SEQ_NUM = 6,0,16,0 %; ! Sequence number (LAST error log) macro MSCP$B_OPCODE = 8,0,8,0 %; ! MSCP operation code macro MSCP$V_OP_ATTN = 8,6,1,0 %; ! Attention message macro MSCP$V_OP_END = 8,7,1,0 %; ! End message macro MSCP$W_MODIFIER = 10,0,16,0 %; ! MSCP command modifiers ! Generic MSCP Modifiers macro MSCP$V_MD_SEREC = 10,8,1,0 %; ! Suppress error recovery macro MSCP$V_MD_SECOR = 10,9,1,0 %; ! Suppress error correction macro MSCP$V_MD_CLSEX = 10,13,1,0 %; ! Clear serious exception macro MSCP$V_MD_COMP = 10,14,1,0 %; ! Compare macro MSCP$V_MD_WRSEQ = 10,4,1,0 %; ! Write shadow set 1 unit at a time macro MSCP$V_MD_WBKVL = 10,5,1,0 %; ! Write-back (volatile) macro MSCP$V_MD_WBKNV = 10,6,1,0 %; ! Write-back (non-volatile) macro MSCP$V_MD_SSHDW = 10,7,1,0 %; ! Suppress Shadowing macro MSCP$V_MD_SCCHL = 10,10,1,0 %; ! Suppress caching (low speed) macro MSCP$V_MD_SCCHH = 10,11,1,0 %; ! Suppress caching (high speed) macro MSCP$V_MD_ERROR = 10,12,1,0 %; ! Force error macro MSCP$V_MD_EXPRS = 10,15,1,0 %; ! Express request macro MSCP$V_MD_REWND = 10,1,1,0 %; ! Rewind macro MSCP$V_MD_OBJCT = 10,2,1,0 %; ! Object count macro MSCP$V_MD_REVRS = 10,3,1,0 %; ! Reverse macro MSCP$V_MD_UNLOD = 10,4,1,0 %; ! Unload macro MSCP$V_MD_IMMED = 10,6,1,0 %; ! Request immediate completion macro MSCP$V_MD_DLEOT = 10,7,1,0 %; ! Request detect LEOT macro MSCP$V_MD_INHERLOG = 10,9,1,0 %; ! Inhibit error logging macro MSCP$V_MD_CDATL = 10,12,1,0 %; ! Clear Cached Data Lost macro MSCP$V_MD_SPNDW = 10,0,1,0 %; ! Spin down macro MSCP$V_MD_ALLCD = 10,1,1,0 %; ! All class drivers macro MSCP$V_MD_DSOLV = 10,4,1,0 %; ! Disolve shadow set macro MSCP$V_MD_FLENU = 10,0,1,0 %; ! Flush entire unit macro MSCP$V_MD_VOLTL = 10,1,1,0 %; ! Flush volitile only macro MSCP$V_MD_NXUNT = 10,0,1,0 %; ! Next unit macro MSCP$V_MD_RIP = 10,0,1,0 %; ! Allow self-destruct (online only) macro MSCP$V_MD_IGNMF = 10,1,1,0 %; ! Ignore media format error (online only) macro MSCP$V_MD_STWRP = 10,2,1,0 %; ! Enable Set Write Protect macro MSCP$V_MD_CLWBL = 10,3,1,0 %; ! Clear Write-Back Data Lost macro MSCP$V_MD_SHDSP = 10,4,1,0 %; ! Shadow Unit Specified macro MSCP$V_MD_EXCAC = 10,5,1,0 %; ! Exclusive access macro MSCP$V_MD_PRIMR = 10,0,1,0 %; ! Primary replacement block macro MSCP$V_MD_CRNPR = 10,0,1,0 %; ! Connection Reference Number Present macro MSCP$V_MD_ENRWR = 10,4,1,0 %; ! Enable Re-Write Error Recovery (tapes) macro MSCP$V_MD_TBC = 10,15,1,0 %; ! To-be-continued (segmented tapes) macro MSCP$V_MD_HISLO = 10,3,1,0 %; ! History Log macro MSCP$V_MD_SUPWL = 10,4,1,0 %; ! Supplementary Write Log macro MSCP$V_MD_REUSE = 10,7,1,0 %; ! Reuse Entry macro MSCP$V_MD_LOCSU = 10,0,1,0 %; ! Local Source Unit macro MSCP$V_MD_ESTCP = 10,1,1,0 %; ! Establish Communications Paths macro MSCP$V_MD_RETCP = 10,2,1,0 %; ! Retain Communications Paths ! to keep the output compatible. macro MSCP$B_FLAGS = 9,0,8,0 %; ! End message flags macro MSCP$V_EF_CPRET = 9,0,1,0 %; ! Communication Paths Retained macro MSCP$V_EF_DLS = 9,1,1,0 %; ! Cached Data Lost (tapes only) macro MSCP$V_EF_PLS = 9,2,1,0 %; ! Position Lost (tapes only) macro MSCP$V_EF_EOT = 9,3,1,0 %; ! End of Tape Encountered (tapes only) macro MSCP$V_EF_SEREX = 9,4,1,0 %; ! Serious exception (tapes only) macro MSCP$V_EF_ERLOG = 9,5,1,0 %; ! Error log generated macro MSCP$V_EF_BBLKU = 9,6,1,0 %; ! Bad block unreported (disks only) macro MSCP$V_EF_BBLKR = 9,7,1,0 %; ! Bad block reported (disks only) macro MSCP$V_EF_HISLO = 9,2,1,0 %; ! History Logged macro MSCP$V_EF_ALLOF = 9,3,1,0 %; ! Allocation Failure macro MSCP$V_EF_FASTSKIP_USED = 9,7,1,0 %; ! MT$M_FASTSKIP_USED was set (TMSCP served tapes only) macro MSCP$W_STATUS = 10,0,16,0 %; ! End message status macro MSCP$V_ST_MASK = 10,0,5,0 %; literal MSCP$S_ST_MASK = 5; ! Status code bits macro MSCP$V_ST_SBCOD = 10,5,11,0 %; literal MSCP$S_ST_SBCOD = 11; ! Subcode bits ! Success Subcode Values macro MSCP$V_SC_SDIGN = 10,5,1,0 %; ! Spin Down IGNored macro MSCP$V_SC_STCON = 10,6,1,0 %; ! STill CONnected macro MSCP$V_SC_DUPUN = 10,7,1,0 %; ! DUPlicate UNit number macro MSCP$V_SC_ALONL = 10,8,1,0 %; ! ALready ONLine macro MSCP$V_SC_STONL = 10,9,1,0 %; ! STill ONLine macro MSCP$V_SC_EOT = 10,10,1,0 %; ! EOT encountered (tapes only) macro MSCP$V_SC_INREP = 10,10,1,0 %; ! INcomplete REPlacement (disks only) macro MSCP$V_SC_IVRCT = 10,11,1,0 %; ! InValid RCT (disks only) macro MSCP$V_SC_RDONY = 10,12,1,0 %; ! ReaD ONlY volume format ! Invalid Command Subcode Values macro MSCP$V_SC_NOVOL = 10,5,1,0 %; ! NO VOLume mounted or drive disabled (RUN/STOP) macro MSCP$V_SC_INOPR = 10,6,1,0 %; ! unit is INOPeRative macro MSCP$V_SC_UDSBL = 10,8,1,0 %; ! Unit disabled by field service or diagnostic macro MSCP$V_SC_EXUSE = 10,9,1,0 %; ! Exclusive use macro MSCP$V_SC_LDR = 10,10,1,0 %; ! Loader cycle error ! Unit-Available Subcode Values macro MSCP$V_SC_CPYIP = 10,6,1,0 %; ! Copy in progress macro MSCP$V_SC_NOMEM = 10,7,1,0 %; ! No members in shadow set macro MSCP$V_SC_ALUSE = 10,10,1,0 %; ! Already in use ! Media Format Error Subcode Values macro MSCP$V_SC_DATAL = 10,8,1,0 %; ! Unit is DATA Loss write protected (data safety) macro MSCP$V_SC_SOFTW = 10,12,1,0 %; ! Unit is SOFTWare protected macro MSCP$V_SC_HARDW = 10,13,1,0 %; ! Unit is HARDWare protected ! Data Error Subcode Values macro MSCP$V_SC_ALLOF = 10,1,1,0 %; macro MSCP$V_SC_TABFU = 10,2,1,0 %; macro MSCP$V_SC_NOENT = 10,4,1,0 %; ! Informational Event Subcode literal MSCP$K_OP_ABORT = 1; ! Abort literal MSCP$K_OP_ACCES = 16; ! Access literal MSCP$K_OP_ACCNM = 5; ! Access non-volatile memory literal MSCP$K_OP_AVAIL = 8; ! Available literal MSCP$K_OP_CMPCD = 17; ! Compare Controller Data literal MSCP$K_OP_COMP = 32; ! Compare Host Data literal MSCP$K_OP_DSPLY = 6; ! Display literal MSCP$K_OP_DTACP = 11; ! Determine Access Paths literal MSCP$K_OP_DCD = 13; ! Disk Copy Data literal MSCP$K_OP_ERASE = 18; ! Erase literal MSCP$K_OP_ERGAP = 22; ! Erase Gap (tapes only) literal MSCP$K_OP_FLUSH = 19; ! Flush literal MSCP$K_OP_FMT = 24; ! Format (as in floppy disks) literal MSCP$K_OP_GTCMD = 2; ! Get Command Status literal MSCP$K_OP_GTUNM = 7; ! Get Unit Name literal MSCP$K_OP_GTUNT = 3; ! Get Unit Status literal MSCP$K_OP_GTLDR = 7; ! Get Loader Status literal MSCP$K_OP_MOVE = 12; ! Move Media literal MSCP$K_OP_ONLIN = 9; ! Online literal MSCP$K_OP_RCEDC = 35; ! Read Controller Encryption/Decryption Code literal MSCP$K_OP_READ = 33; ! Read literal MSCP$K_OP_REPLC = 20; ! Replace literal MSCP$K_OP_REPOS = 37; ! Reposition (tapes only) literal MSCP$K_OP_STCON = 4; ! Set Controller Characteristics literal MSCP$K_OP_STUNT = 10; ! Set Unit Characteristics literal MSCP$K_OP_TERCO = 48; ! Terminate Class Driver/Server Connection literal MSCP$K_OP_WRITE = 34; ! Write literal MSCP$K_OP_WRITM = 36; ! Write Tape Mark literal MSCP$K_OP_WRHIM = 25; ! Write History Management ! MSCP End Message Codes literal MSCP$K_OP_END = 128; ! End Message Flag ! MSCP Attention Message Codes (listed in alphabetical order) literal MSCP$K_OP_ACPTH = 66; ! Access Path literal MSCP$K_OP_AVATN = 64; ! Available literal MSCP$K_OP_DUPUN = 65; ! Duplicate Unit Number literal MSCP$M_SLUN = %X'4000'; literal MSCP$K_SLUN_RSVP = 32767; ! SLUN to request unit number for this controller literal MSCP$S_GENERIC_MSCP = 14; ! MSCP Command Operation Codes (defined in alphabetical order) macro MSCP$V_SLUN = 12,14,1,0 %; ! Server Local Unit Number flag ! Aggregates MSCP_MODIFIERS and MSCP_SUBCODES have been ! incorporated into the GENERIC_MSCP aggregate. ! Definitions for MSCP Transfer Commands ! ! Also the FORMAT command, which includes a ! buffer descriptor just like transfer commands. literal MSCP$K_FMT_DFLT = 0; ! device's default literal MSCP$K_FMT_SING = 1; ! single density literal MSCP$K_FMT_DOUB = 2; ! double density literal MSCP$K_FMT_RX33 = 282; ! RX33 - ISO DIS8630-1985 literal MSCP$S_TRANSFER_COMMANDS = 52; macro MSCP$L_BYTE_CNT = 12,0,32,0 %; ! Byte count macro MSCP$B_BUFFER = 16,0,0,0 %; literal MSCP$S_BUFFER = 12; ! Buffer descriptor macro MSCP$L_LBN = 28,0,32,0 %; ! Logical block number macro MSCP$L_FRST_BAD = 28,0,32,0 %; ! First bad block macro MSCP$L_FMT_FUNC = 28,0,32,0 %; ! Format function macro MSCP$L_KEY_ID = 32,0,32,0 %; ! Key identifier macro MSCP$L_KEY_LGH = 36,0,32,0 %; ! Key length macro MSCP$L_KEY_BUF = 40,0,0,0 %; literal MSCP$S_KEY_BUF = 12; ! Key buffer descriptor macro MSCP$L_POSITION = 28,0,32,0 %; ! Position (object count) macro MSCP$L_TAPEREC = 32,0,32,0 %; ! Tape record byte count ! Definitions for Abort and Get Command Status Commands and End Messages literal MSCP$S_ABORT_GTCMD = 20; macro MSCP$L_OUT_REF = 12,0,32,0 %; ! Outstanding reference number macro MSCP$L_CMD_STS = 16,0,32,0 %; ! Command status ! Definitions for the Access Non-Volatile Memory Command and End Message literal MSCP$K_ANM_READ = 0; literal MSCP$K_ANM_EXCG = 1; literal MSCP$K_ANM_TSST = 2; literal MSCP$S_ACCNM = 56; macro MSCP$L_ANM_SIZE = 12,0,32,0 %; ! Non-Volatile Memory Size macro MSCP$L_ANM_OFFS = 16,0,32,0 %; ! Offset into Non-Volatile Memory macro MSCP$W_ANM_OPER = 20,0,16,0 %; ! Non-Volatile Memory Access Operation macro MSCP$W_ANM_DLGH = 22,0,16,0 %; ! Data Length macro MSCP$T_ANM_MEMD = 24,0,0,0 %; literal MSCP$S_ANM_MEMD = 32; ! Memory Data ! Definitions for Display Command and End Message literal MSCP$S_DISPLAY_CMD = 32; macro MSCP$W_DITEM = 12,0,16,0 %; ! Item code macro MSCP$W_DMODE = 14,0,16,0 %; ! Mode macro MSCP$T_DTEXT = 16,0,0,0 %; literal MSCP$S_DTEXT = 16; ! Display text ! Definitions for the Get Unit Status Command and End Message literal MSCP$M_UF_CMPRD = %X'1'; literal MSCP$M_UF_CMPWR = %X'2'; literal MSCP$M_UF_WBKNV = %X'40'; literal MSCP$M_UF_WRTPD = %X'100'; literal MSCP$M_UF_EXACC = %X'400'; literal MSCP$M_UF_SCCHH = %X'800'; literal MSCP$M_UF_WRTPS = %X'1000'; literal MSCP$M_UF_WRTPH = %X'2000'; literal MSCP$M_UF_576 = %X'4'; literal MSCP$M_UF_WHL = %X'8'; literal MSCP$M_UF_RMVBL = %X'80'; literal MSCP$M_UF_SSMST = %X'200'; literal MSCP$M_UF_SSMEM = %X'4000'; literal MSCP$M_UF_REPLC = %X'8000'; literal MSCP$M_UF_CACFL = %X'4'; literal MSCP$M_UF_EWRER = %X'8'; literal MSCP$M_UF_VARSP = %X'10'; literal MSCP$M_UF_VSMSU = %X'20'; literal MSCP$M_UF_LOADR = %X'200'; literal MSCP$M_UF_CACH = %X'8000'; literal MSCP$M_MTD_ENH = %X'1'; literal MSCP$M_COMP_SUP = %X'2'; literal MSCP$M_COMP_ENA = %X'4'; literal MSCP$M_SLUN_C = %X'1F'; literal MSCP$M_SLUN_D1 = %X'3E0'; literal MSCP$M_SLUN_D0 = %X'7C00'; literal MSCP$M_MTYP_N = %X'7F'; literal MSCP$M_MTYP_A2 = %X'F80'; literal MSCP$M_MTYP_A1 = %X'1F000'; literal MSCP$M_MTYP_A0 = %X'3E0000'; literal MSCP$M_MTYP_D1 = %X'7C00000'; literal MSCP$M_MTYP_D0 = %X'F8000000'; literal MSCP$K_CM_NOCPY = 0; literal MSCP$K_CM_COPY = 1; literal MSCP$K_CM_MGCPY = 2; literal MSCP$K_CM_MMRG = 3; literal MSCP$K_CM_HB_MMRG = 4; literal MSCP$M_TF_800 = %X'1'; literal MSCP$M_TF_PE = %X'2'; literal MSCP$M_TF_GCR = %X'4'; literal MSCP$M_TF_BLK = %X'8'; literal MSCP$M_TF_NOR = %X'1'; literal MSCP$M_TF_BHD = %X'2'; literal MSCP$M_TF_DN2 = %X'4'; literal MSCP$M_TF_DN3 = %X'8'; literal MSCP$M_TF_T87 = %X'10'; literal MSCP$M_TF_T87C = %X'20'; literal MSCP$M_TF_ENH = %X'2'; literal MSCP$M_TF_NDC = %X'4'; literal MSCP$M_TF_EDC = %X'8'; literal MSCP$M_TF_DCP = %X'2'; literal MSCP$M_TF_X82 = %X'1'; literal MSCP$M_TF_X85 = %X'2'; literal MSCP$M_TF_X5C = %X'4'; literal MSCP$K_TC_OLD = 0; literal MSCP$K_TC_9TR = 256; literal MSCP$K_TC_CTP = 512; literal MSCP$K_TC_HPC = 768; literal MSCP$K_TC_WOD = 1024; literal MSCP$K_TC_DAT = 1280; literal MSCP$K_TC_8MM = 1536; literal MSCP$K_TC_QIC = 1792; literal MSCP$M_TF_MASK = 255; ! Density field mask literal MSCP$K_TF_CODE = 256; ! Format code multiplier literal MSCP$S_ONLIN_STUNT = 44; ! DISK_TAPE was previously contained in aggregate ! ONLIN_STUNT. Although,the aggregate was deleted, literal MSCP$S_GTUNT = 50; macro MSCP$W_MULT_UNT = 12,0,16,0 %; ! Multi-unit code macro MSCP$W_UNT_FLGS = 14,0,16,0 %; ! Unit flags macro MSCP$V_UF_CMPRD = 14,0,1,0 %; ! Compare reads macro MSCP$V_UF_CMPWR = 14,1,1,0 %; ! Compare writes macro MSCP$V_UF_WBKNV = 14,6,1,0 %; ! Write-back (non-volatile) [disks only] macro MSCP$V_UF_WRTPD = 14,8,1,0 %; ! Write protect (data safety) macro MSCP$V_UF_EXACC = 14,10,1,0 %; ! Exclusive access macro MSCP$V_UF_SCCHH = 14,11,1,0 %; ! Suppress caching (High speed) macro MSCP$V_UF_WRTPS = 14,12,1,0 %; ! Write protect (software) macro MSCP$V_UF_WRTPH = 14,13,1,0 %; ! Write protect (hardware) macro MSCP$V_UF_576 = 14,2,1,0 %; ! 576 byte sectors macro MSCP$V_UF_WHL = 14,3,1,0 %; ! Write History Logging Support macro MSCP$V_UF_RMVBL = 14,7,1,0 %; ! Removeable media macro MSCP$V_UF_SSMST = 14,9,1,0 %; ! Shadow set master macro MSCP$V_UF_SSMEM = 14,14,1,0 %; ! Shadow set member macro MSCP$V_UF_REPLC = 14,15,1,0 %; ! Controller initiated bad block replacement macro MSCP$V_UF_CACFL = 14,2,1,0 %; ! Cache flushed macro MSCP$V_UF_EWRER = 14,3,1,0 %; ! Enhanced Write Error Recovery macro MSCP$V_UF_VARSP = 14,4,1,0 %; ! Variable speed unit macro MSCP$V_UF_VSMSU = 14,5,1,0 %; ! Variable speed mode suppression macro MSCP$V_UF_LOADR = 14,9,1,0 %; ! Media Loader Present macro MSCP$V_UF_CACH = 14,15,1,0 %; ! Write-back Caching macro MSCP$W_TAPE_CHAR = 16,0,16,0 %; ! Propagate Tape unit chars. macro MSCP$V_MTD_ENH = 16,0,1,0 %; ! VMS-TMSCP SERVER MTD ENHANCED (V7.2) macro MSCP$V_COMP_SUP = 16,1,1,0 %; ! Tape unit supports compaction macro MSCP$V_COMP_ENA = 16,2,1,0 %; ! Compaction enabled/disabled macro MSCP$Q_UNIT_ID = 20,0,0,0 %; literal MSCP$S_UNIT_ID = 8; ! Unit identifier macro MSCP$L_EXCL_LBA = 20,0,32,1 %; ! Excluded LBN area address [disks only] macro MSCP$L_EXCL_LBC = 24,0,32,0 %; ! Excluded LBN block count [disks only] macro MSCP$L_SLUN_ALLOCLS = 20,0,32,0 %; macro MSCP$W_SLUN_UNIT = 24,0,16,0 %; macro MSCP$W_SLUN_DEVNAME = 26,0,16,0 %; macro MSCP$V_SLUN_C = 26,0,5,0 %; literal MSCP$S_SLUN_C = 5; macro MSCP$V_SLUN_D1 = 26,5,5,0 %; literal MSCP$S_SLUN_D1 = 5; macro MSCP$V_SLUN_D0 = 26,10,5,0 %; literal MSCP$S_SLUN_D0 = 5; macro MSCP$L_DEV_PARM = 28,0,32,0 %; ! Device dependent parameters macro MSCP$L_MEDIA_ID = 28,0,32,0 %; ! Media type identifier macro MSCP$V_MTYP_N = 28,0,7,0 %; literal MSCP$S_MTYP_N = 7; ! Media # (i.e. 7 of RK07) macro MSCP$V_MTYP_A2 = 28,7,5,0 %; literal MSCP$S_MTYP_A2 = 5; ! Media name char. macro MSCP$V_MTYP_A1 = 28,12,5,0 %; literal MSCP$S_MTYP_A1 = 5; ! Media name continued macro MSCP$V_MTYP_A0 = 28,17,5,0 %; literal MSCP$S_MTYP_A0 = 5; ! " " " macro MSCP$V_MTYP_D1 = 28,22,5,0 %; literal MSCP$S_MTYP_D1 = 5; ! Dev mnemonic char. macro MSCP$V_MTYP_D0 = 28,27,5,0 %; literal MSCP$S_MTYP_D0 = 5; ! Mnemonic continued macro MSCP$W_SHDW_UNT = 32,0,16,0 %; ! Shadow unit macro MSCP$W_COPY_MOD = 34,0,16,0 %; ! Copy mode macro MSCP$W_SHDW_STS = 34,0,16,0 %; ! Shadow unit status macro MSCP$L_DMAXBCNT = 32,0,32,0 %; ! Unit MAXBCNT macro MSCP$W_FORMAT = 32,0,16,0 %; ! Original (Old) format macro MSCP$V_TF_800 = 32,0,1,0 %; ! NRZI 800 bpi macro MSCP$V_TF_PE = 32,1,1,0 %; ! Phase encoded 1600 bpi macro MSCP$V_TF_GCR = 32,2,1,0 %; ! Group code recording 6250 bpi macro MSCP$V_TF_BLK = 32,3,1,0 %; ! Block format (TK50) macro MSCP$V_TF_NOR = 32,0,1,0 %; ! Normal (low) density (833 bpi TK50) macro MSCP$V_TF_BHD = 32,1,1,0 %; ! Block mode High Density (1250 bpi TK70) macro MSCP$V_TF_DN2 = 32,2,1,0 %; ! Block mode Density 2 (TF85 compatible) macro MSCP$V_TF_DN3 = 32,3,1,0 %; ! Block mode Density 3 (TF86 compatible) macro MSCP$V_TF_T87 = 32,4,1,0 %; ! Tx87 compatible macro MSCP$V_TF_T87C = 32,5,1,0 %; ! Tx87 compatible compressed macro MSCP$V_TF_ENH = 32,1,1,0 %; ! Enhanced density macro MSCP$V_TF_NDC = 32,2,1,0 %; ! NOR with data comp. macro MSCP$V_TF_EDC = 32,3,1,0 %; ! ENH with data comp. macro MSCP$V_TF_DCP = 32,1,1,0 %; ! DAT compacted density macro MSCP$V_TF_X82 = 32,0,1,0 %; ! EXABYTE-8200 Compatible Density macro MSCP$V_TF_X85 = 32,1,1,0 %; ! EXABYTE-8500 Compatible Density macro MSCP$V_TF_X5C = 32,2,1,0 %; ! EXABYTE-8500 Compacted Density macro MSCP$W_SPEED = 34,0,16,0 %; ! Speed macro MSCP$W_TRACK = 36,0,16,0 %; ! Track size macro MSCP$W_GROUP = 38,0,16,0 %; ! Group size macro MSCP$W_CYLINDER = 40,0,16,0 %; ! Cylinder size macro MSCP$B_UNIT_SVR = 42,0,8,0 %; ! Unit software version macro MSCP$B_UNIT_HVR = 43,0,8,0 %; ! Unit hardware version macro MSCP$W_RCT_SIZE = 44,0,16,0 %; ! RCT size macro MSCP$B_RBNS = 46,0,8,0 %; ! RBNs per track macro MSCP$B_RCT_CPYS = 47,0,8,0 %; ! Number of RCT copies macro MSCP$W_LOAD_AVAIL = 48,0,16,0 %; ! Controller load available (VMS server load balancing) macro MSCP$W_FORMENU = 36,0,16,0 %; ! Format menu macro MSCP$B_FREECAP = 38,0,8,0 %; ! Free capacity ! Definitions for Online and Set Unit Characteristics Command and End Messages macro MSCP$L_UNT_SIZE = 36,0,32,0 %; ! Unit size macro MSCP$L_VOL_SER = 40,0,32,0 %; ! Volume serial number macro MSCP$L_MAXWTREC = 36,0,32,0 %; ! Maximum write record size macro MSCP$W_NOISEREC = 40,0,16,0 %; ! Noise record ! we still have to generate the size field. ! Definitions for the Read Controller Encrypt/Decrypt Code Command and End Message literal MSCP$S_RCEDC = 36; macro MSCP$L_CODE = 32,0,32,0 %; ! Encrypt/Decrypt Code Length ! Definitions for the Replace Command and End Message (disks only) literal MSCP$S_REPLC = 16; macro MSCP$L_RBN = 12,0,32,0 %; ! Replacement block number ! Definitions for the Reposition Command and End Message (tapes only) literal MSCP$S_REPOS = 20; macro MSCP$L_REC_CNT = 12,0,32,0 %; ! Record/Object count macro MSCP$L_TMGP_CNT = 16,0,32,0 %; ! Tape mark count macro MSCP$L_RCSKIPED = 12,0,32,0 %; ! Records skipped macro MSCP$L_TMSKIPED = 16,0,32,0 %; ! Tape markes skipped ! Definitions for the Set Controller Characteristics Command and End Message literal MSCP$M_CF_576 = %X'1'; literal MSCP$M_CF_SHADW = %X'2'; literal MSCP$M_CF_MLTHS = %X'4'; literal MSCP$M_CF_LDCD = %X'8'; literal MSCP$M_CF_THIS = %X'10'; literal MSCP$M_CF_OTHER = %X'20'; literal MSCP$M_CF_MISC = %X'40'; literal MSCP$M_CF_ATTN = %X'80'; literal MSCP$M_CF_RDCD = %X'100'; literal MSCP$M_CF_WHL = %X'200'; literal MSCP$M_CF_RDO = %X'400'; literal MSCP$M_CF_NFESC = %X'800'; literal MSCP$M_CF_LOAD = %X'2000'; literal MSCP$M_CF_EDCRP = %X'4000'; literal MSCP$M_CF_REPLC = %X'8000'; literal MSCP$M_CF_MTDEN = %X'4000'; literal MSCP$M_CF_SRT = %X'8000'; literal MSCP$K_CL_CNTRL = 1; literal MSCP$K_CL_DISK = 2; literal MSCP$K_CL_TAPE = 3; literal MSCP$K_CL_D144 = 4; literal MSCP$K_CL_LDR = 5; ! MSCP Controller Model literal MSCP$K_CM_HSC50 = 1; literal MSCP$K_CM_UDA50 = 2; literal MSCP$K_CM_RC25 = 3; literal MSCP$K_CM_EMULA = 4; literal MSCP$K_CM_TU81 = 5; literal MSCP$K_CM_UDA52 = 6; literal MSCP$K_CM_UDA50A = 6; literal MSCP$K_CM_RDRX = 7; literal MSCP$K_CM_TOPS = 8; literal MSCP$K_CM_TK50 = 9; literal MSCP$K_CM_TQK50 = 9; literal MSCP$K_CM_RUX50 = 10; literal MSCP$K_CM_AIO = 12; literal MSCP$K_CM_KFBTA = 12; literal MSCP$K_CM_KDA50 = 13; literal MSCP$K_CM_TK70 = 14; literal MSCP$K_CM_TQK70 = 14; literal MSCP$K_CM_RV20 = 15; literal MSCP$K_CM_RRD50 = 16; literal MSCP$K_CM_RRD50Q = 16; literal MSCP$K_CM_KDB50 = 18; literal MSCP$K_CM_RQDX3 = 19; literal MSCP$K_CM_RQDX4 = 20; literal MSCP$K_CM_DSSI_DISK = 21; literal MSCP$K_CM_DSSI_TAPE = 22; literal MSCP$K_CM_DSSI_DSKTAP = 23; literal MSCP$K_CM_DSSI_OTHER = 24; literal MSCP$K_CM_TUK50 = 25; literal MSCP$K_CM_RRD50U = 26; literal MSCP$K_CM_KDM70 = 27; literal MSCP$K_CM_TQL70 = 28; literal MSCP$K_CM_TM32 = 29; literal MSCP$K_CM_HSC70 = 32; literal MSCP$K_CM_HSC40 = 33; literal MSCP$K_CM_HSC60 = 34; literal MSCP$K_CM_HSC90 = 35; literal MSCP$K_CM_RN20 = 36; literal MSCP$K_CM_ENE10 = 37; literal MSCP$K_CM_TN10 = 38; literal MSCP$K_CM_HSJ40 = 40; literal MSCP$K_CM_HSC65 = 41; literal MSCP$K_CM_HSC95 = 42; literal MSCP$K_CM_HSJ80 = 46; literal MSCP$K_CM_KSB50 = 64; literal MSCP$K_CM_TK50_DEBNT = 65; literal MSCP$K_CM_TBK70 = 66; literal MSCP$K_CM_TBK7L = 68; literal MSCP$K_CM_RF30 = 96; literal MSCP$K_CM_RF71 = 97; literal MSCP$K_CM_TF85 = 98; literal MSCP$K_CM_TF70 = 99; literal MSCP$K_CM_RF31 = 100; literal MSCP$K_CM_RF72 = 101; literal MSCP$K_CM_RF73 = 102; literal MSCP$K_CM_RF32 = 103; literal MSCP$K_CM_RF35 = 104; literal MSCP$K_CM_RF36 = 108; literal MSCP$K_CM_RF74 = 109; literal MSCP$K_CM_TF86 = 110; literal MSCP$K_CM_HSD20 = 111; literal MSCP$K_CM_RF75 = 112; literal MSCP$K_CM_RF37 = 114; literal MSCP$K_CM_HSX50 = 128; literal MSCP$K_CM_ULTRIX = 248; literal MSCP$K_CM_SVS = 249; literal MSCP$S_STCON = 34; ! Allocation class (CNT_ALCS) is now part of union ! with UNIT structure in MSCP_BASIC_PKT macro MSCP$W_VERSION = 12,0,16,0 %; ! MSCP version macro MSCP$W_CNT_FLGS = 14,0,16,0 %; ! Controller flags macro MSCP$V_CF_576 = 14,0,1,0 %; ! 576 byte sectors [disks only] macro MSCP$V_CF_SHADW = 14,1,1,0 %; ! Shadowing [disks only] macro MSCP$V_CF_MLTHS = 14,2,1,0 %; ! Multi-Host macro MSCP$V_CF_LDCD = 14,3,1,0 %; ! Local Disk Copy Data macro MSCP$V_CF_THIS = 14,4,1,0 %; ! Enable this host's error log macro MSCP$V_CF_OTHER = 14,5,1,0 %; ! Enable other host's error log macro MSCP$V_CF_MISC = 14,6,1,0 %; ! Enable miscellaneous error log macro MSCP$V_CF_ATTN = 14,7,1,0 %; ! Enable attention messages macro MSCP$V_CF_RDCD = 14,8,1,0 %; ! Remote Disk Copy Data macro MSCP$V_CF_WHL = 14,9,1,0 %; ! Write History Logging Support macro MSCP$V_CF_RDO = 14,10,1,0 %; ! Restricted DISK COPY DATA Operations macro MSCP$V_CF_NFESC = 14,11,1,0 %; ! Class driver supports NOFE state changes macro MSCP$V_CF_LOAD = 14,13,1,0 %; ! Controller returns load available information macro MSCP$V_CF_EDCRP = 14,14,1,0 %; ! Data Encrypt/Decrypt Supported macro MSCP$V_CF_REPLC = 14,15,1,0 %; ! Controller Initiated Bad Block Replacement [disks only] macro MSCP$V_CF_MTDEN = 14,14,1,0 %; ! Class driver supports MTD (multi tape density) macro MSCP$V_CF_SRT = 14,15,1,0 %; ! Segemented Record Transfer macro MSCP$W_HST_TMO = 16,0,16,0 %; ! Host timeout macro MSCP$W_CNT_TMO = 16,0,16,0 %; ! Controller timeout macro MSCP$B_CNT_SVR = 18,0,8,0 %; ! Controller software version macro MSCP$B_CNT_HVR = 19,0,8,0 %; ! Controller hardware version macro MSCP$Q_TIME = 20,0,0,0 %; literal MSCP$S_TIME = 8; ! Quad-word date-time macro MSCP$Q_CNT_ID = 20,0,0,0 %; literal MSCP$S_CNT_ID = 8; ! Controller ID macro MSCP$L_MAXBCNT = 28,0,32,0 %; ! Maximum supported byte count macro MSCP$W_CONN_REF = 32,0,16,0 %; ! Connection reference number ! Controller and Unit identifier Classes. (Device Class) ! Definitions for Disk Data Copy Commands and End Messages literal MSCP$K_MIN_SIZ = 12; ! Shortest Command literal MSCP$C_MIN_SIZ = 12; ! Shortest Command literal MSCP$K_MXCMDLEN = 36; ! Longest Command literal MSCP$C_MXCMDLEN = 36; ! Longest Command literal MSCP$K_DCDCMDLEN = 60; ! DCD Command literal MSCP$C_DCDCMDLEN = 60; ! DCD Command literal MSCP$K_LEN = 50; ! Longest End Message literal MSCP$C_LEN = 50; ! Longest End Message literal MSCP$S_DCD = 60; macro MSCP$L_LBCOUNT = 12,0,32,0 %; ! Logical block count macro MSCP$W_SRC_UNUM = 16,0,16,0 %; ! Source unit number macro MSCP$Q_SRC_UID = 20,0,0,0 %; literal MSCP$S_SRC_UID = 8; ! Source unit identifier macro MSCP$L_DEST_LBN = 28,0,32,0 %; ! Destination LBN macro MSCP$W_HRN = 32,0,16,0 %; ! HRN or Entloc macro MSCP$W_ENT_ID = 34,0,16,0 %; ! Entry ID macro MSCP$L_SRC_LBN = 40,0,32,0 %; ! Source LBN macro MSCP$Q_PORT_ADR = 44,0,0,0 %; literal MSCP$S_PORT_ADR = 8; ! Source unit's subsystem port address macro MSCP$Q_SYS_ADR = 52,0,0,0 %; literal MSCP$S_SYS_ADR = 8; ! Source unit's subsystem system address macro MSCP$Z_SBC_STS = 16,0,0,0 %; literal MSCP$S_SBC_STS = 16; ! Subcommand status macro MSCP$W_ENT_LOC = 32,0,16,0 %; ! Entry locator ! Definitions for Write History Management Commands and End Messages literal MSCP$K_WHM_DALL = 1; literal MSCP$K_WHM_DHRN = 2; literal MSCP$K_WHM_DELO = 3; literal MSCP$K_WHM_RALL = 4; literal MSCP$K_WHM_RHRN = 5; literal MSCP$K_WHM_DAFC = 6; literal MSCP$S_WRHIM = 32; macro MSCP$B_WRHIS_BD = 16,0,0,0 %; literal MSCP$S_WRHIS_BD = 12; ! Write history buffer descriptor macro MSCP$W_UNIT_AL = 16,0,16,0 %; ! Unit allocated macro MSCP$W_SERV_AL = 18,0,16,0 %; ! Server allocated macro MSCP$W_SERV_UNAL = 20,0,16,0 %; ! Server unallocated macro MSCP$W_OPER = 28,0,16,0 %; ! Operation macro MSCP$W_COUNT = 28,0,16,0 %; ! Count macro MSCP$W_OFFSET = 30,0,16,0 %; ! Offset ! Definitions for Write History Entry literal WHIS$M_ET_TLIB = %X'4000'; literal WHIS$M_ET_ERR = %X'8000'; literal WHIS$K_WRITELOGLEN = 16; ! Write log length literal WHIS$C_WRITELOGLEN = 16; ! literal WHIS$S_WRITE_LOG_ENTRY = 16; macro WHIS$W_ELO = 0,0,16,0 %; ! Entry Locator macro WHIS$W_UNIT = 2,0,16,0 %; ! Unit Number macro WHIS$L_LENGTH = 4,0,32,0 %; ! Transfer Length macro WHIS$L_LBN = 8,0,32,0 %; ! Starting Logical Block Number macro WHIS$W_HRN = 12,0,16,0 %; ! Host Reference Number macro WHIS$W_ENTFLGS = 14,0,16,0 %; ! Entry Flags macro WHIS$V_ET_TLIB = 14,14,1,0 %; macro WHIS$V_ET_ERR = 14,15,1,0 %; ! Definitions for GET UNIT NAME command and end message literal MSCP$S_GET_UNIT_NAME = 44; macro MSCP$L_DDR_NAMELEN = 12,0,32,0 %; ! Length of dynamic name macro MSCP$T_DDR_NAME = 16,0,0,0 %; literal MSCP$S_DDR_NAME = 28; ! Dynamic name string !*** MODULE $MVLDEF *** ! + ! MAGNETIC TAPE VOLUME LIST ! THIS STRUCTURE DESCRIBES THE VOLUMES IN A VOLUME SET ! - literal MVL$K_FIXLEN = 36; ! LENGTH OF FIXED AREA OF STRUCTURE literal MVL$C_FIXLEN = 36; ! LENGTH OF FIXED AREA OF STRUCTURE literal MVL$S_MVLDEF = 36; literal MVL$S_MVL = 36; macro MVL$L_VCB = 0,0,32,1 %; ! ADDRESS OF VCB macro MVL$W_SIZE = 8,0,16,0 %; ! SIZE OF STRUCTURE macro MVL$B_TYPE = 10,0,8,0 %; ! TYPE OF STRUCTURE macro MVL$B_NVOLS = 11,0,8,0 %; ! NUMBER OF VOLUMES IN VOLUME SET macro MVL$T_SET_ID = 12,0,0,0 %; literal MVL$S_SET_ID = 6; ! FILE SET ID FOR THE VOLUME SET macro MVL$B_VOL_ACC = 18,0,8,0 %; ! VOLUME ACCESSIBILTY CHARACTER DEFAULT macro MVL$B_MOU_PRV = 19,0,8,0 %; ! USER'S MOUNT TIME PRIVILEGES macro MVL$V_VOLPRO = 19,0,1,0 %; ! VOLPRO PRIVILEGE macro MVL$V_OVRPRO = 19,1,1,0 %; ! OVERRIDE PRIVILEGE (BYPASS,SYSPRV,VOLPRO) macro MVL$V_OPER = 19,2,1,0 %; ! OPER PRIVILEDGE macro MVL$T_VOLOWNER = 20,0,0,0 %; literal MVL$S_VOLOWNER = 14; ! VOL1 ONER IDENTIFIER FIELD macro MVL$B_STDVER = 34,0,8,0 %; ! ANSI VERSION OF VOLUME SET ! THE FOLLOWING STRUCTURE IN REPEATED IN MVL FOR EACH REEL IN VOLUME SET literal MVL$K_LENGTH = 8; ! LENGTH OF STRUCTURE literal MVL$C_LENGTH = 8; ! LENGTH OF STRUCTURE literal MVL$S_MVLDEF1 = 8; literal MVL$S_MVL1 = 8; macro MVL$T_VOLLBL = 0,0,0,0 %; literal MVL$S_VOLLBL = 6; ! VOLUME LABEL macro MVL$B_RVN = 6,0,8,0 %; ! RELATIVE UNIT NUMBER macro MVL$B_STATUS = 7,0,8,0 %; ! STATUS OF VOLUME macro MVL$V_MOUNTED = 7,0,1,0 %; ! REEL IS MOUNTED macro MVL$V_UNUSED = 7,1,1,0 %; ! IS THIS ENTRY IN USE macro MVL$V_OVERIDE = 7,2,1,0 %; ! CAN OVERRIDE PROTECTION ON THIS REEL !*** MODULE $MVMSLDEF *** ! ++ ! $MVMSLDEF - mount verification messages list structure definition ! ! The MVMSL provides a mechanism for communicating information about ! mount verification messages to device driver special mount ! verification processing routines. ! -- literal MVMSL$M_NOSUFFIX = %X'1'; literal MVMSL$M_SUPRESS = %X'2'; literal MVMSL$K_LENGTH = 8; ! Length of a MVMSL entry. literal MVMSL$S_MVMSLDEF = 13; literal MVMSL$S_MVMSL = 13; macro MVMSL$B_MAXIDX = -5,0,8,0 %; ! Maximum legal MVMSL index. macro MVMSL$L_SNDMSGOFF = -4,0,32,1 %; ! Offset from MVMSL base to SEND_MESSAGE routine macro MVMSL$W_MSG_CODE = 0,0,16,0 %; ! The MSG$_ code for this entry. macro MVMSL$W_FLAGS = 2,0,16,0 %; ! Processing flags: macro MVMSL$V_NOSUFFIX = 2,0,1,0 %; ! Do not add suffix. macro MVMSL$V_SUPRESS = 2,1,1,0 %; ! May be suppressed. macro MVMSL$L_TEXTOFF = 4,0,32,1 %; ! Offset from MVMSL base to ASCIC message text. !*** MODULE $NAFDEF *** ! ++ ! ! Structure for network proxy login file, NETUAF.DAT (VMS version 4.x) ! ! -- literal NAF$M_TASK = %X'1'; literal NAF$M_BATCH = %X'2'; literal NAF$M_INTERACTIVE = %X'4'; literal NAF$K_LENGTH = 100; ! Length of record literal NAF$C_LENGTH = 100; ! Length of record literal NAF$S_NAFDEF = 100; literal NAF$S_NAF = 100; macro NAF$T_REMNAME = 0,0,0,0 %; literal NAF$S_REMNAME = 64; ! Combined nodename and remote username macro NAF$T_NODE = 0,0,0,0 %; literal NAF$S_NODE = 32; ! Node name macro NAF$T_REMUSER = 32,0,0,0 %; literal NAF$S_REMUSER = 32; ! Remote username macro NAF$T_LOCALUSER = 64,0,0,0 %; literal NAF$S_LOCALUSER = 32; ! Local username macro NAF$L_FLAGS = 96,0,32,1 %; ! Flags longword macro NAF$V_TASK = 96,0,1,0 %; ! Allow task=0 access macro NAF$V_BATCH = 96,1,1,0 %; ! Allow batch jobs macro NAF$V_INTERACTIVE = 96,2,1,0 %; ! Allow interactive login !*** MODULE $NAFV5DEF *** ! ++ ! ! Structure for network proxy login file, NETPROXY.DAT ! ! -- literal NAFV5$C_PROXY_FIXEDLEN = 4; literal NAFV5$K_PROXY_FIXEDLEN = 4; literal NAFV5$C_DEFPROXY = 1; ! Default proxy account literal NAFV5$C_PROXY = 2; ! NONdefault proxy account literal NAFV5$C_MAXPROXY = 15; ! Max number of proxy accounts literal NAFV5$K_MAXPROXY = 15; ! Max number of proxy accounts literal NAFV5$C_MAXPROXYLEN = 32; ! Max length of proxy string literal NAFV5$K_MAXPROXYLEN = 32; ! Max length of proxy string literal NAFV5$S_NAFV5PROXY = 4; macro NAFV5$W_PROXYLEN = 0,0,16,0 %; ! String length macro NAFV5$W_TYPE = 2,0,16,0 %; ! Type field macro NAFV5$T_PROXY = 4,0,0,0 %; ! Local proxy account name literal NAFV5$M_TASK = %X'1'; literal NAFV5$M_BATCH = %X'2'; literal NAFV5$M_INTERACTIVE = %X'4'; literal NAFV5$M_UIC = %X'8'; literal NAFV5$K_FIXEDLEN = 76; ! Length of fixed part of record literal NAFV5$C_FIXEDLEN = 76; ! Length of fixed part of record literal NAFV5$C_FORMAT1 = 1; ! format version # literal NAFV5$K_FORMAT1 = 1; ! format version # ! Define the max record size literal NAFV5$C_MAXREC = 656; literal NAFV5$K_MAXREC = 656; literal NAFV5$S_NAFV5DEF = 76; ! Old size name - synonym literal NAFV5$S_NAFV5 = 76; macro NAFV5$W_FORMAT = 0,0,16,0 %; ! Record format version macro NAFV5$W_RECLEN = 2,0,16,0 %; ! Record length macro NAFV5$W_NODELEN = 4,0,16,0 %; ! Length of remote node string macro NAFV5$W_REMUSERLEN = 6,0,16,0 %; ! Length of remote user string macro NAFV5$L_FLAGS = 8,0,32,1 %; ! Flags longword macro NAFV5$V_TASK = 8,0,1,0 %; ! Allow task=0 access macro NAFV5$V_BATCH = 8,1,1,0 %; ! Allow batch jobs macro NAFV5$V_INTERACTIVE = 8,2,1,0 %; ! Allow interactive login macro NAFV5$V_UIC = 8,3,1,0 %; ! Remote user uses UIC authentication macro NAFV5$T_REMNAME = 12,0,0,0 %; literal NAFV5$S_REMNAME = 64; ! Combined nodename and remote username macro NAFV5$T_NODE = 12,0,0,0 %; literal NAFV5$S_NODE = 32; ! Node name macro NAFV5$T_REMUSER = 44,0,0,0 %; literal NAFV5$S_REMUSER = 32; ! Remote username macro NAFV5$L_REMUIC = 44,0,32,0 %; ! Remote UIC macro NAFV5$W_REMUIC_MEM = 44,0,16,0 %; ! Member number macro NAFV5$W_REMUIC_GRP = 46,0,16,0 %; ! Group number !*** MODULE $NDTDEF *** ! + ! NEXUS DEVICE AND ADAPTER TYPE CODES ! - ! DEFINE CONSTANT TYPE CODES literal NDT$_MEM4NI = 8; ! MEMORY, 4K NOT INTERLEAVED literal NDT$_MEM4I = 9; ! MEMORY, 4K INTERLEAVED literal NDT$_MEM16NI = 16; ! MEMORY, 16K NOT INTERLEAVED literal NDT$_MEM16I = 17; ! MEMORY, 16K INTERLEAVED literal NDT$_MEM1664NI = 18; ! MEMORY, 16K AND 64K MIXED literal NDT$_MB = 32; ! MBA 0,1,2, OR 3 literal NDT$_UB0 = 40; ! UB ADAPTER OR INTERCONNECT 0, literal NDT$_UB1 = 41; ! 1, literal NDT$_UB2 = 42; ! 2, literal NDT$_UB3 = 43; ! OR 3 literal NDT$_DR32 = 48; ! DR32 0,1,2,... literal NDT$_CI = 56; ! CI780'S, CI750'S literal NDT$_MPM0 = 64; ! MULTIPORT MEMORY 0, literal NDT$_MPM1 = 65; ! 1, literal NDT$_MPM2 = 66; ! 2, literal NDT$_MPM3 = 67; ! OR 3 literal NDT$_DISK9 = 81; ! Disk on 009 literal NDT$_TERM9 = 82; ! Terminal on 009 literal NDT$_TAPE9 = 83; ! Tape on 009 literal NDT$_PRTR9 = 84; ! Printer on 009 literal NDT$_SFUN9 = 85; ! Spec. func. ctrllr. on 009 literal NDT$_USER9 = 86; ! User-defined device on 009 literal NDT$_MEM64NIL = 104; ! 64K NON-INTERLEAVED MEM, LOWER CONTROLLER literal NDT$_MEM64EIL = 105; ! 64K EXTERNALLY INTERLEAVED MEM, LOWER literal NDT$_MEM64NIU = 106; ! 64K NON-INTERLEAVED MEM, UPPER CONTROLLER literal NDT$_MEM64EIU = 107; ! 64K EXTERNALLY INTERLEAVED MEM, UPPER literal NDT$_MEM64I = 108; ! 64K INTERNALLY INTERLEAVED MEMORY literal NDT$_MEM256NIL = 112; ! 256K NON-INTERLEAVED MEM, LOWER CONTROLLER literal NDT$_MEM256EIL = 113; ! 256K EXTERNALLY INTERLEAVED MEM, LOWER literal NDT$_MEM256NIU = 114; ! 256K NON-INTERLEAVED MEM, UPPER CONTROLLER literal NDT$_MEM256EIU = 115; ! 256K EXTERNALLY INTERLEAVED MEM, UPPER literal NDT$_MEM256I = 116; ! 256K INTERNALLY INTERLEAVED MEMORY literal NDT$_KA410 = 128; ! VAXstar system literal NDT$_KA420 = 128; ! PVAX system literal NDT$_KA640 = 129; ! MAYFAIR II system literal NDT$_SHAC = 130; literal NDT$_SGEC = 131; literal NDT$_KA520CIO = 132; ! CIRRUS CIO module literal NDT$_KA520COMM = 133; ! CIRRUS COMM module literal NDT$_KA43 = 134; literal NDT$_KA440 = 135; literal NDT$_KA46 = 135; ! BI node device types. Note low word is hardware device type on BI. ! High order word (i.e. the 8000) distinguishes device as a BI device. ! First BI memory nodes literal NDT$_SCORMEM = -2147483647; ! Scorpio Memory ! Then other BI devices literal NDT$_BIMFA = -2147483391; ! BI Multi-Function Adapter literal NDT$_BUA = -2147483390; ! BI UNIBUS adapter literal NDT$_BLA = -2147483389; ! BI LESI adapter literal NDT$_KDZ11 = -2147483387; ! KDZ11 processor literal NDT$_KA810 = -2147483387; ! KA810 processor literal NDT$_NBI = -2147483386; ! BI-NMI Adapter literal NDT$_XBIB = -2147475193; ! BI-XMI Adapter literal NDT$_XBIB_PLUS = -2147475185; ! BI-XMI Plus Adapter literal NDT$_BCA = -2147483384; ! BI-CI Adapter literal NDT$_BICOMBO = -2147483383; ! BI Combo Board literal NDT$_BCI750 = -2147483381; ! Interim BI-CI Adapter literal NDT$_BIACP = -2147483380; ! Aurora Processor Module literal NDT$_BDA = -2147483378; ! BI-to-Disk Adapter literal NDT$_BSA = -2147467004; ! BI-to-SI Adapter literal NDT$_KSB50 = -2147467004; ! BI-to-SI Adapter literal NDT$_AIO = -2147466995; ! Aurora I/O Module literal NDT$_KFBTA = -2147466995; ! Aurora I/O Module literal NDT$_AIE_TK = -2147466997; ! Aurora I/O Extension Module literal NDT$_AIE_TKNI = -2147466994; ! Aurora I/O Extension Module literal NDT$_AIE_NI = -2147466993; ! Aurora I/O Extension Module literal NDT$_DEBNT = -2147466993; ! Aurora I/O Extension Module literal NDT$_DSB32 = -2147483382; ! BI-Hi speed sync comm adapter literal NDT$_LACP = -2147466996; ! BI-VAXstation 8000 graphics adapter literal NDT$_DEBNI = -2147483368; ! AIE varient literal NDT$_KWB = -2147450853; ! BI_KWB32 module ! XMI node device types. Note low word is hardware device type on XMI. literal NDT$_CIXCD = 3077; ! CI port CIXCD adapter literal NDT$_KFMSA = 2064; ! DSSI port KFMSA adapter literal NDT$_XCP = 32769; ! Calypso/CVAX CPU literal NDT$_XRP = 32898; ! RIGEL CPU literal NDT$_XMA = 16385; ! XMI Memory literal NDT$_XBI = 8193; ! XBI Adapter literal NDT$_XWATCH = 3076; ! XWATCH Adapter literal NDT$_XJA = 4097; ! XJA Adapter literal NDT$_AXA = 4098; ! AXA Adapter literal NDT$_HSX50 = 3106; literal NDT$_KDM70 = 3106; literal NDT$_XBI_PLUS = 8194; ! XBI-Plus adapter literal NDT$_X1202 = 32896; ! Mariah CPU literal NDT$_DEMNA = 3075; ! NI port - DEMNA adapter literal NDT$_XSA = 2085; ! XMI-SCSI adapter literal NDT$_LAMB = 4138; ! Laser-XMI adapter literal NDT$_XZA_SCSI = 3126; ! XMI-SCSI adapter literal NDT$_XZA_DSSI = 3121; ! XMI-DSSI adapter literal NDT$_CIMNA = 3119; ! XMI-CI adapter literal NDT$_DEMFA = 2083; ! XMI-FDDI adapter ! MBUS node devices. literal NDT$_MBUS_FTAM = -1878982655; ! Tape adapter literal NDT$_MBUS_FQAM = -1878982399; ! QBUS adapter literal NDT$_MBUS_LEGSS = -1878982654; ! LEGSS graphics literal NDT$_MBUS_FWIOM = -1878982652; ! I/O module literal NDT$_MBUS_KA60 = -1878982392; ! Dual CVAX CPU literal NDT$_MBUS_8MB = -1878917104; ! 8MB memory literal NDT$_MBUS_16MB = -1878916848; ! 16MB memory literal NDT$_MBUS_32MB = -1878916336; ! 32MB memory literal NDT$_MBUS_32MBA = -1878916080; ! 32MB memory literal NDT$_MBUS_64MB = -1878915824; ! 64MB memory literal NDT$_MBUS_128MB = -1878915312; ! 128MB memory literal NDT$_MBUS_8MBFS = -1862402032; ! 8MB Firestarter ! (TYC0002) keep UCODE constants for CI boot adapters here literal UCODE_CI780 = 1; literal UCODE_BCA = 2; literal UCODE_BCA_ONBOARD = 3; literal UCODE_ONBOARD = 4; literal NDT$_IOP = 8192; literal NDT$_KA0302_EV5_CPU = 49152; literal NDT$_KA0302_EV3_4MB = 32768; literal NDT$_KA0302_EV4_4MB = 32769; literal NDT$_KA0302_NV_4MB = 32770; literal NDT$_KA0302_EV3_1MB = 32771; literal NDT$_KA0302_EV4_1MB = 32772; literal NDT$_KA0302_NV_1MB = 32773; literal NDT$_KA0302_LEPMEM = 16385; literal NDT$_KA0302_MEM = 16384; literal NDT$_KA0302_IOP = 8192; literal NDT$_KA0C05_TLEP = 32784; literal NDT$_KA0C05_TLEP_EV5_1MB = 32784; literal NDT$_KA0C05_TLEP_EV5_4MB = 32785; literal NDT$_KA0C05_TLEP_EV5_16MB = 32786; literal NDT$_KA0C05_TLEP_2EV5_1MB = 32787; literal NDT$_KA0C05_TLEP_2EV5_4MB = 32788; literal NDT$_KA0C05_TLEP_2EV5_16MB = 32789; literal NDT$_KA0C05_TLEP_EV56_4MB = 32800; literal NDT$_KA0C05_TLEP_EV56_8MB = 32801; literal NDT$_KA0C05_TLEP_2EV56_4MB = 32802; literal NDT$_KA0C05_TLEP_2EV56_8MB = 32803; literal NDT$_KA0C08_TLEP_2EV6_4MB = 32805; literal NDT$_KA0C05_NV_MEM = 17408; literal NDT$_KA0C05_TMEM = 20480; literal NDT$_KA0C05_TIOP = 8192; literal NDT$_KA0C05_ITIOP = 8224; literal NDT$_FLAG = 12032; literal NDT$_HPC = 61184; literal NDT$_FVME_VENDOR_ID = 50336627; ! Vendor ID, FBUS-VME adapter literal NDT$_FVME = 100663297; ! FBUS-VME adapter software version literal NDT$_DEANA = 100745216; ! Module number = B2005 literal NDT$_FCA = 100728832; ! Module number = B2004 literal NDT$_FZA = 100777984; ! Module number = B2007 literal NDT$_FFA = 100761600; ! Module number = B2006 literal NDT$_FBE = 101711872; ! FBE is an exception literal NDT$_KA0202_FBUS = 842022912; ! Cobra Fbus bridge literal NDT$_KA0302_FBUS = 858800128; ! Laser Fbus bridge literal NDT$_KA0C05_FBUS = 875577344; ! TLaser Fbus bridge literal NDT$_PMAD = 1145130320; literal NDT$_PMAD_AA_H = 541147437; literal NDT$_PMAF = 1178684752; literal NDT$_PMAF_AA_H = 541147437; literal NDT$_PMAF_CA_H = 541147949; literal NDT$_PMAF_FA_H = 541148717; literal NDT$_PMAF_FD_H = 541345325; literal NDT$_PMAF_FS_H = 542328365; literal NDT$_PMAF_FU_H = 542459437; literal NDT$_PMAZ = 1514229072; literal NDT$_PMAZB_AA_H = 1094790466; literal NDT$_PMAZC_AA_H = 1094790467; literal NDT$_PMAB = 1111575888; literal NDT$_PMABV_AA_H = 1094790486; literal NDT$_AV01 = 825251393; literal NDT$_AV01B_AA_H = 1094790466; literal NDT$_PMAG = 1195461968; literal NDT$_PMAG_JA_H = 541149741; literal NDT$_PMAG_FA_H = 541148717; literal NDT$_PMAGB_BA_H = 1094856002; literal NDT$_PMAGD_AA_H = 1094790468; literal NDT$_PMAGC_H = 538976323; literal NDT$_PMAGC_AA_H = 1094790467; literal NDT$_PMAGC_BA_H = 1094856003; literal NDT$_PMAGC_DA_H = 1094987075; literal NDT$_PMAGD_H = 538976324; literal NDT$_PMAGC_EA_H = 1095052611; literal NDT$_PMAG_CA_H = 541147949; literal NDT$_PMAG_DA_H = 541148205; literal NDT$_DELTA = 1414284612; literal NDT$_DELTA_H = 538976321; literal NDT$_KZTS = 1398037067; literal NDT$_KZTSA_AA_H = 1094790465; literal NDT$_KZTSA_BA_H = 1094856001; literal NDT$_PMAT = 1413565776; literal NDT$_PMAT_AA_H = 541147437; literal NDT$_OTTO = 1330926671; literal NDT$_OTTO_H = 538976288; literal NDT$_DGLTA = 1414285124; literal NDT$_DGLTA_H = 1095118145; literal NDT$_EISA_SYSTEM_BOARD = 22; literal NDT$_AHA1742A = 33591300; literal NDT$_AHA1740 = 16814084; literal NDT$_DEPCA = 541238032; literal NDT$_CPQ3011 = 288362766; literal NDT$_CPQ3021 = 556798222; literal NDT$_CPQ3111 = 288428302; literal NDT$_CPQ3112 = 305205518; literal NDT$_CPQ3121 = 556863758; literal NDT$_CPQ3122 = 573640974; literal NDT$_CPQ3201 = 20058382; literal NDT$_CPQ3202 = 36835598; literal NDT$_CPQ3231 = 825364750; literal NDT$_CPQ3232 = 842141966; literal NDT$_PRO6000 = 6311746; literal NDT$_PRO6001 = 23088962; literal NDT$_PRO6002 = 39866178; literal NDT$_DEFEA = 19964688; literal NDT$_DEFEA_2 = 36741904; literal NDT$_KFESA = 3056400; literal NDT$_KFESB = 19833616; literal NDT$_KFESC = 36610832; literal NDT$_KFESD = 53388048; literal NDT$_MLX0075 = 1962973237; literal NDT$_MLX0077 = 1996527669; literal NDT$_DEC4250 = 1346544400; literal NDT$_DEC3003 = 53519120; literal NDT$_AHA1742A_FLOPPY = 1347374150; literal NDT$_NS16450 = 91216; literal NDT$_PC4XD_SERIAL = 1395934032; literal NDT$_PC4XD_PARALLEL = 1278493520; literal NDT$_DIGIBOARD = 1229408580; literal NDT$_PARALLEL_PORT = 1414680656; literal NDT$_SERIAL_PORT = 1414680659; literal NDT$_DE200 = 808600900; literal NDT$_AHA_1540 = 808727857; literal NDT$_SOUND_BOARD = 1314213715; literal NDT$_WD90C24 = 809059415; literal NDT$_KBD = 4473419; literal NDT$_MOUS = 1398099789; literal NDT$_COM1 = 827150147; literal NDT$_COM2 = 843927363; literal NDT$_FLOP = 1347374150; literal NDT$_DE20 = 808600900; literal NDT$_LPT1 = 827609164; literal NDT$_DW11 = 825317188; literal NDT$_DT20 = 808604740; literal NDT$_PCXB = 1113080656; literal NDT$_IDEM = 1296385097; literal NDT$_IDES = 1397048393; literal NDT$_USBC = 1128420181; literal NDT$_CYPRESS = -963440512; literal NDT$_DIGITAL_PCI_VENDOR_ID = 4113; literal NDT$_PBB = 69649; literal NDT$_TULIP = 135185; literal NDT$_FOCUS = 200721; literal NDT$_TGA = 266257; literal NDT$_MFPCI = 331793; literal NDT$_PVIC = 397329; literal NDT$_ZEPHYR = 462865; literal NDT$_KZPSA = 528401; literal NDT$_DC21140 = 593937; literal NDT$_DC21143 = 1642513; literal NDT$_TGA2 = 856081; literal NDT$_PFI = 987153; literal NDT$_DC21041 = 1314833; literal NDT$_DGLPB = 1445905; literal NDT$_PVPCI = 1511441; literal NDT$_PCIRM = 1576977; literal NDT$_PPB0 = 2101265; literal NDT$_PPB1 = 2166801; literal NDT$_PPB2 = 2232337; literal NDT$_PPB3 = 2363409; literal NDT$_PPB4 = 2428945; literal NDT$_PPB5 = 2494481; literal NDT$_DEGPA_SA = 70318; literal NDT$_DEGPA_TA = 135854; literal NDT$_DEGXA = 380048612; literal NDT$_DEGX2_SA = 373822692; literal NDT$_DEGX2_TA = 373888228; literal NDT$_CIPCA = 106958997; literal NDT$_TC4048 = 84414682; literal NDT$_RACORE = -2125197073; literal NDT$_NCR53C810 = 69632; literal NDT$_NCR53C810A = 331776; literal NDT$_NCR53C825 = 200704; literal NDT$_KFPSA = -2147282944; literal NDT$_SATURN = 75792518; literal NDT$_MERCURY = 75661446; literal NDT$_i82558 = 304709766; literal NDT$_QLOGIC = 270536823; literal NDT$_PCMCIA_PD6729 = 285216787; literal NDT$_MYLEX = 69737; literal NDT$_PCI1280 = 808586769; literal NDT$_HOT_PLUG = -1594421743; literal NDT$_MACH32 = 1096290306; literal NDT$_MACH64 = 1196953602; literal NDT$_MACH64C = 1129844738; literal NDT$_DEC864 = -2000661709; literal NDT$_S3TRIO = -2012130509; literal NDT$_METEOR = 2101295; literal NDT$_FAX_MODEM = 5783878; literal NDT$_XIRCOM = 5128524; literal NDT$_NCR53C710 = 1; literal NDT$_DC253 = 2; literal NDT$_SCRIPT_RAM = 3; literal NDT$_DS1287 = 4; literal NDT$_Z85C30 = 5; literal NDT$_EEROM = 6; literal NDT$_NIADRROM = 7; literal NDT$_FEPROM = 8; literal NDT$_PCD8584 = 9; literal NDT$_NCR53C710_DSSI = 10; literal NDT$_TC_INTERFACE = 11; literal NDT$_SCSI_INTERFACE = 12; literal NDT$_CXTURBO = 13; literal NDT$_COREIO = 14; literal NDT$_NCR53C94 = 15; literal NDT$_LANCE = 16; literal NDT$_AMD79C30 = 17; literal NDT$_KA0202_CPU = 18; literal NDT$_KA0202_MEM = 19; literal NDT$_KA0202_IO = 20; literal NDT$_VTI82C106_PP = 21; literal NDT$_KA0902_CPU = 23; literal NDT$_KA0902_MEM = 24; literal NDT$_KA0902_IIO = 25; literal NDT$_KA0902_EIO = 26; literal NDT$_KA1605_PCI = 27; literal NDT$_KA1605_CPU = 28; literal NDT$_KA1605_MEMORY = 29; literal NDT$_KA1605_GCD = 30; literal NDT$_HPC_PCI = 541282632; literal NDT$_KA2308_QSA = 49; literal NDT$_KA2308_QSD = 50; literal NDT$_KA2308_DIR = 51; literal NDT$_KA2308_IOP = 52; literal NDT$_KA2308_PCA = 53; literal NDT$_KA2308_PCI = 54; literal NDT$_KA2308_GP = 55; literal NDT$_KA2308_HS = 56; literal NDT$_KA2308_MEM = 57; literal NDT$_KA2308_DTAG = 58; literal NDT$_KA270F_PCI = 59; literal NDT$_MCD = 4473677; literal NDT$_COREIO_HW_ID_MASK_LO = -1; literal NDT$_COREIO_HW_ID_MASK_HI = 0; literal NDT$_EISA_HW_ID_MASK_LO = -1; literal NDT$_EISA_HW_ID_MASK_HI = -1; literal NDT$_FBUS_HW_ID_MASK_LO = -16384; literal NDT$_FBUS_HW_ID_MASK_HI = 16777215; literal NDT$_LBUS_HW_ID_MASK_LO = -1; literal NDT$_LBUS_HW_ID_MASK_HI = 0; literal NDT$_PCI_HW_ID_MASK_LO = -1; literal NDT$_PCI_HW_ID_MASK_HI = 0; literal NDT$_PCMCIA_HW_ID_MASK_LO = -1; literal NDT$_PCMCIA_HW_ID_MASK_HI = 0; literal NDT$_TURBO_HW_ID_MASK_LO = -1; literal NDT$_TURBO_HW_ID_MASK_HI = -1; literal NDT$_XBUS_HW_ID_MASK_LO = -1; literal NDT$_XBUS_HW_ID_MASK_HI = 0; literal NDT$_XMI_HW_ID_MASK_LO = 65535; literal NDT$_XMI_HW_ID_MASK_HI = 0; literal NDT$_VTI_COMBO_HW_ID_MASK_LO = -1; literal NDT$_VTI_COMBO_HW_ID_MASK_HI = 0; literal NDT$_TLASER_HW_ID_MASK_LO = 65535; literal NDT$_TLASER_HW_ID_MASK_HI = 0; !*** MODULE $NFBDEF *** ! ! The following generic field identifiers are defined for all databases. ! literal NFB$C_ENDOFLIST = 0; ! Used to terminate the field i.d. literal NFB$C_WILDCARD = 1; ! Field i.d. used for "match all" database searches literal NFB$C_CTX_SIZE = 64; ! Length of context area in P2 buffer ! ! The following codes are passed in the second IOSB longword to qualify ! as SS$_ILLCNTRFUNC error. ! ! The high order word of these error codes must be 0 ! so that they won't be confused with field i.d.s literal NFB$_ERR_FCT = 1; ! Unrecognized NFB$B_FCT value. literal NFB$_ERR_DB = 2; ! Unrecognized NFB$B_DATABASE value. literal NFB$_ERR_P1 = 3; ! The P1 buffer is invalid. literal NFB$_ERR_P2 = 4; ! The P2 buffer is invalid. literal NFB$_ERR_P3 = 5; ! The P3 buffer is invalid. literal NFB$_ERR_P4 = 6; ! The P4 buffer is invalid. literal NFB$_ERR_P5 = 7; ! The P5 buffer should not have been specified. literal NFB$_ERR_P6 = 8; ! The P6 buffer should not have been specified. literal NFB$_ERR_CELL = 9; ! Unrecognized NFB$B_CELL value. literal NFB$_ERR_OPER = 10; ! Unrecognized NFB$B_OPER value. literal NFB$_ERR_SRCH = 11; ! Unrecognized NFB$L_SRCH_KEY field ID literal NFB$_ERR_SRCH2 = 12; ! Unrecognized NFB$L_SRCH2_KEY field ID literal NFB$_ERR_OPER2 = 13; ! Unrecognized NFB$B_OPER2 value. literal NFB$_ERR_FLAGS = 14; ! Undefined bits in NFB$B_FLAGS were not zero. literal NFB$_ERR_LOCK = 15; ! Lock was not granted ! ! Define the P1 buffer format ! literal NFB$C_DECLNAME = 21; ! Declare name literal NFB$C_DECLOBJ = 22; ! Declare object literal NFB$C_DECLSERV = 23; ! Declare server process available ! Resume defining function codes literal NFB$C_LOGEVENT = 28; ! Log a network event literal NFB$C_READEVENT = 29; ! Read current raw event queue (used by EVL only) ! Resume defining function codes literal NFB$C_FC_DELETE = 33; ! Remove an entry from the data base. literal NFB$C_FC_SHOW = 34; ! Return specified field values. literal NFB$C_FC_SET = 35; ! Set/modify the field values. literal NFB$C_FC_CLEAR = 36; ! Clear specified field values. literal NFB$C_FC_ZERCOU = 37; ! Zero (and optionally read) counters literal NFB$C_FC_LOOP = 38; ! Loop (used only to PSI to loop an X.25 line) literal NFB$C_REBUILD_PROXY = 39; ! Rebuild the proxy data base literal NFB$C_ADD_PROXY = 40; ! Add/Modify proxy DB entry literal NFB$C_DELETE_PROXY = 41; ! Remove/Delete proxy access ! Maximum FCT value literal NFB$C_FC_MAX = 41; ! Maximum FCT value literal NFB$M_ERRUPD = %X'1'; literal NFB$M_MULT = %X'2'; literal NFB$M_NOCTX = %X'4'; literal NFB$M_LOCAL = %X'8'; literal NFB$C_DB_LNI = 1; ! Local node literal NFB$C_DB_NDI = 2; ! Common nodes literal NFB$C_DB_OBI = 3; ! Network objects literal NFB$C_DB_CRI = 4; ! Circuits literal NFB$C_DB_PLI = 5; ! Lines literal NFB$C_DB_EFI = 6; ! Event logging filters literal NFB$C_DB_ESI = 7; ! Event logging sinks literal NFB$C_DB_LLI = 8; ! Logical-links literal NFB$C_DB_XNI = 9; ! X.25 networks literal NFB$C_DB_XGI = 10; ! X.25 groups literal NFB$C_DB_XDI = 11; ! X.25 DTEs literal NFB$C_DB_XS5 = 12; ! X.25 server literal NFB$C_DB_XD5 = 13; ! X.25 destinations literal NFB$C_DB_XS9 = 14; ! X.29 server literal NFB$C_DB_XD9 = 15; ! X.29 destinations literal NFB$C_DB_XTI = 16; ! X.25 trace facility literal NFB$C_DB_XTT = 17; ! X.25 tracepoints literal NFB$C_DB_SPI = 18; ! Server Process literal NFB$C_DB_AJI = 19; ! Adjacency information literal NFB$C_DB_ARI = 20; ! Area information ! (The following codes are reserved for future PSIACP ! databases. These codes should only be used in the ! event PSIACP needs a database code before a new ! new NETACP can be supplied to support it). literal NFB$C_DB_XDTE = 21; ! PSI reserved database literal NFB$C_DB_PSI2 = 22; ! PSI reserved database literal NFB$C_DB_PSI3 = 23; ! PSI reserved database literal NFB$C_DB_PSI4 = 24; ! PSI reserved database literal NFB$C_DB_PSI5 = 25; ! PSI reserved database literal NFB$C_DB_SDI = 26; ! Service (DLE) information literal NFB$C_DB_XAI = 27; ! X.25 access database literal NFB$C_DB_PROXY = 28; ! Proxy data base literal NFB$C_DB_XXX = 29; ! Last database definition for NFB$C_DB_MAX calc. ! Maximum DATABASE value literal NFB$C_DB_MAX = 28; ! Maximum DATABASE value literal NFB$C_OP_EQL = 0; ! Match if SEARCH_KEY value EQL database entry field literal NFB$C_OP_GTRU = 1; ! Match if SEARCH_KEY value GTRU database entry field literal NFB$C_OP_LSSU = 2; ! Match if SEARCH_KEY value LSSU database entry field literal NFB$C_OP_NEQ = 3; ! Match if SEARCH_KEY value NEQ database entry field ! The following may only be used internally by NETACP literal NFB$C_OP_FNDMIN = 4; ! Find entry with minimum key value literal NFB$C_OP_FNDMAX = 5; ! Find entry with maximum key value literal NFB$C_OP_FNDPOS = 6; ! Find entry position in database ! Maximum operator function literal NFB$C_OP_MAXFCT = 3; ! Maximum operator function literal NFB$C_OP_MAXINT = 6; ! Maximum internal function literal NFB$K_LENGTH = 16; ! Minimum structure size. literal NFB$C_LENGTH = 16; ! Minimum structure size. ! counted strings. If the "cell size" is non-zero, it literal NFB$S_NFBDEF = 20; ! Old size name - synonym literal NFB$S_NFB = 20; macro NFB$B_FCT = 0,0,8,0 %; ! A function code as follows: ! Function codes for the NFB ! (leaving room for 20 obsolete function codes) ! (leave room for 4 obsolete function codes) ! (leave room for 3 obsolete function codes) macro NFB$B_FLAGS = 1,0,8,0 %; ! Miscellaneous control flags macro NFB$V_ERRUPD = 1,0,1,0 %; ! Update position context, even on error macro NFB$V_MULT = 1,1,1,0 %; ! Process as many entries as can be fit into P4 macro NFB$V_NOCTX = 1,2,1,0 %; ! Don't update position context, even if successful ! (used to stay on an entry for a while). This ! flag Overrides the ERRUPD flag. macro NFB$V_LOCAL = 1,3,1,0 %; ! Signal that REBUILD_PROXY should only be ! performed locally macro NFB$B_DATABASE = 2,0,8,0 %; ! A code identifying the database as follows: ! ZERO is an illegal value for this field macro NFB$B_OPER = 3,0,8,0 %; ! Specifies the sense of the search (e.g. EQL, GEQU) ! when comparing against the SRCH_KEY field. macro NFB$L_SRCH_KEY = 4,0,32,0 %; ! Search key field identifier specifying the key used ! to locate the entry in the database. This search is ! controlled by the sense of the NFB$B_OPER field. ! ! If this field has the value "NFB$C_WILDCARD", then ! the very next entry in the list is assumed to be the ! target of the search. ! ! If this field is not specified (zero), then it ! is assumed to be NFB$C_WILDCARD (no search key). ! macro NFB$L_SRCH2_KEY = 8,0,32,0 %; ! Secondary search key field ID specifying the key used ! to locate the entry in the database. This search is ! controlled by the sense of the NFB$B_OPER2 field. ! ! If both SRCH_KEY and SRCH2_KEY are specified, then ! only those database entries matching both search keys ! will be processed. ! ! If this field is not specified (zero), then it ! is assumed to be NFB$C_WILDCARD (no search key). ! macro NFB$B_OPER2 = 12,0,8,0 %; ! Specifies the sense of the search (e.g. EQL, GEQU) ! when comparing against the SRCH2_KEY field. macro NFB$B_MBZ1 = 13,0,8,0 %; ! Reserved. MBZ. macro NFB$W_CELL_SIZE = 14,0,16,0 %; ! Some of the field values found in the P4 buffer are ! indicates the number of bytes which each string in ! the P4 buffer occupies. If it is zero then strings ! fields are stored as variable lengthed strings. macro NFB$L_FLDID = 16,0,32,0 %; ! Cell containing the first field ID -- the list ! of field IDs begins here and continues to the ! end of the structure. ! ! The list may be terminated before the end of the ! structure by placing the value NFB$C_ENDOFLIST ! in the longword following the last field ID. ! ! ! Define the "field i.d." format. ! literal NFB$M_INX = %X'FFFF'; literal NFB$M_TYP = %X'30000'; literal NFB$M_SPARE = %X'FC0000'; literal NFB$M_DB = %X'FF000000'; literal NFB$C_TYP_BIT = 0; ! Field type for bits literal NFB$C_TYP_V = 0; ! Field type for bits literal NFB$C_TYP_LNG = 1; ! Field type for longwords literal NFB$C_TYP_L = 1; ! Field type for longwords literal NFB$C_TYP_STR = 2; ! Field type for strings literal NFB$C_TYP_S = 2; ! Field type for strings ! literal NFB$S_NFBDEF1 = 4; ! Old size name - synonym literal NFB$S_NFB1 = 4; macro NFB$L_PARAM_ID = 0,0,32,0 %; ! Define parameter ID longword macro NFB$V_INX = 0,0,16,0 %; literal NFB$S_INX = 16; ! Index into semantic table macro NFB$V_TYP = 0,16,2,0 %; literal NFB$S_TYP = 2; ! Field type (string, bit, etc.) macro NFB$V_SPARE = 0,18,6,0 %; literal NFB$S_SPARE = 6; ! Reserved, MBZ macro NFB$V_DB = 0,24,8,0 %; literal NFB$S_DB = 8; ! Data-base i.d. ! Define useful symbols for storing and retreiving binary and string ! values from the P2 and P4 buffers ! literal NFB$S_NFBDEF2 = 4; ! old size name - synonym literal NFB$S_NFB2 = 4; macro NFB$L_LNG_VALUE = 0,0,32,0 %; ! Longword value literal NFB$S_NFBDEF3 = 4; ! old size name - synonym literal NFB$S_NFB3 = 4; macro NFB$L_BIT_VALUE = 0,0,32,0 %; ! Boolean value literal NFB$C_NDI_LCK = 33554433; ! Set if conditionally writable fields are not writable literal NFB$C_NDI_LOO = 33554434; ! Set if CNF is for a "loopback" node literal NFB$C_NDI_REA = 33554435; ! Set if node is reachable ! literal NFB$C_NDI_TAD = 33619984; ! "transformed address" - uses local node address ! for the local NDI (instead of zero as does ADD) literal NFB$C_NDI_CTA = 33619985; ! Absolute due time for logging counters literal NFB$C_NDI_ADD = 33619986; ! Address literal NFB$C_NDI_CTI = 33619987; ! Counter timer literal NFB$C_NDI_ACL = 33619988; ! Active links literal NFB$C_NDI_DEL = 33619989; ! Delay literal NFB$C_NDI_DTY = 33619990; ! Destination Type literal NFB$C_NDI_DCO = 33619991; ! Destination Cost literal NFB$C_NDI_DHO = 33619992; ! Destination Hops literal NFB$C_NDI_SDV = 33619993; ! Service Device literal NFB$C_NDI_CPU = 33619994; ! CPU type literal NFB$C_NDI_STY = 33619995; ! Software type literal NFB$C_NDI_DAD = 33619996; ! Dump address literal NFB$C_NDI_DCT = 33619997; ! Dump count literal NFB$C_NDI_OHO = 33619998; ! Host literal NFB$C_NDI_IHO = 33619999; ! Host literal NFB$C_NDI_ACC = 33620000; ! Access switch (inbound, outbound, etc) literal NFB$C_NDI_PRX = 33620001; ! ** obsolete ** (Node proxy parameter) literal NFB$C_NDI_NND = 33620002; ! Next node address literal NFB$C_NDI_SNV = 33620003; ! Service Node Version literal NFB$C_NDI_INB = 33620004; ! Async Line - Inbound node type ! literal NFB$C_NDI_COL = 33685568; ! Collating field literal NFB$C_NDI_HAC = 33685569; ! Node address/loop linename combination literal NFB$C_NDI_CNT = 33685570; ! Counters literal NFB$C_NDI_NNA = 33685571; ! Name literal NFB$C_NDI_SLI = 33685572; ! Service line literal NFB$C_NDI_SPA = 33685573; ! Service password literal NFB$C_NDI_LOA = 33685574; ! Load file literal NFB$C_NDI_SLO = 33685575; ! Secondary loader literal NFB$C_NDI_TLO = 33685576; ! Tertiary loader literal NFB$C_NDI_SID = 33685577; ! Software ID literal NFB$C_NDI_DUM = 33685578; ! Dump file literal NFB$C_NDI_SDU = 33685579; ! Secondary dumper literal NFB$C_NDI_NLI = 33685580; ! Loopback Line literal NFB$C_NDI_DLI = 33685581; ! Destination Line literal NFB$C_NDI_PUS = 33685582; ! Privileged user id literal NFB$C_NDI_PAC = 33685583; ! Privileged account literal NFB$C_NDI_PPW = 33685584; ! Privileged password literal NFB$C_NDI_NUS = 33685585; ! Non-privileged user id literal NFB$C_NDI_NAC = 33685586; ! Non-privileged account literal NFB$C_NDI_NPW = 33685587; ! Non-privileged password literal NFB$C_NDI_RPA = 33685588; ! Receive password literal NFB$C_NDI_TPA = 33685589; ! Transmit password literal NFB$C_NDI_DFL = 33685590; ! Diagnostic load file literal NFB$C_NDI_HWA = 33685591; ! Hardware NI address (ROM address) literal NFB$C_NDI_LPA = 33685592; ! Loop assistant NI address literal NFB$C_NDI_NNN = 33685593; ! Next node name to destination (goes with NND) literal NFB$C_NDI_LAA = 33685594; ! Load Assist Agent literal NFB$C_NDI_LAP = 33685595; ! Load Assist Parameter literal NFB$C_NDI_MFL = 33685596; ! Management File ! literal NFB$C_LNI_LCK = 16777217; ! Set if conditionally writable fields are not writable literal NFB$C_LNI_ALI = 16777218; ! Set if ALIAS INBOUND has been enabled literal NFB$C_LNI_IPR = 16777219; ! Incoming proxy enabled/disabled literal NFB$C_LNI_OPR = 16777220; ! Outgoing proxy enabled/disabled literal NFB$C_LNI_DNS = 16777221; ! DNS interface enabled/disabled ! literal NFB$C_LNI_ADD = 16842768; ! Address literal NFB$C_LNI_ACL = 16842769; ! Total number of active links literal NFB$C_LNI_ITI = 16842770; ! Incoming timer literal NFB$C_LNI_OTI = 16842771; ! Outgoing timer literal NFB$C_LNI_STA = 16842772; ! State literal NFB$C_LNI_MLK = 16842773; ! Maximum links literal NFB$C_LNI_DFA = 16842774; ! Delay factor literal NFB$C_LNI_DWE = 16842775; ! Delay weight literal NFB$C_LNI_IAT = 16842776; ! Inactivity timer literal NFB$C_LNI_RFA = 16842777; ! Retransmit factor literal NFB$C_LNI_ETY = 16842778; ! Executor Type literal NFB$C_LNI_RTI = 16842779; ! Routing timer literal NFB$C_LNI_RSI = 16842780; ! Routing suppression timer literal NFB$C_LNI_SAD = 16842781; ! Subaddress ! (lower word = lower limit, upper word = upper limit) literal NFB$C_LNI_MAD = 16842782; ! Maximum address literal NFB$C_LNI_MLN = 16842783; ! Maximum lines literal NFB$C_LNI_MCO = 16842784; ! Maximum cost literal NFB$C_LNI_MHO = 16842785; ! Maximum hops literal NFB$C_LNI_MVI = 16842786; ! Maximum visits literal NFB$C_LNI_MBU = 16842787; ! Maximum buffers literal NFB$C_LNI_BUS = 16842788; ! Forwarding buffer size literal NFB$C_LNI_LPC = 16842789; ! Loop count literal NFB$C_LNI_LPL = 16842790; ! Loop length literal NFB$C_LNI_LPD = 16842791; ! Loop Data type literal NFB$C_LNI_DAC = 16842792; ! Default access switch (inbound, outbound, etc) literal NFB$C_LNI_fill1 = 16842793; ! Place holder, used to be Default proxy access (inbound, outbound, etc) literal NFB$C_LNI_PIQ = 16842794; ! Pipeline quota literal NFB$C_LNI_LPH = 16842795; ! Loop help type of assistance given to loop requestors literal NFB$C_LNI_BRT = 16842796; ! Broadcast routing timer literal NFB$C_LNI_MAR = 16842797; ! Maximum areas literal NFB$C_LNI_MBE = 16842798; ! Maximum nonrouters on NI literal NFB$C_LNI_MBR = 16842799; ! Maximum routers on NI literal NFB$C_LNI_AMC = 16842800; ! Area maximum cost literal NFB$C_LNI_AMH = 16842801; ! Area maximum hops literal NFB$C_LNI_SBS = 16842802; ! Segment buffer size literal NFB$C_LNI_ALA = 16842803; ! Alias local node address (cluster address) literal NFB$C_LNI_ALM = 16842804; ! Alias maximum links literal NFB$C_LNI_PSP = 16842805; ! Path split policy normal/interim literal NFB$C_LNI_MPS = 16842806; ! Maximum path split literal NFB$C_LNI_MDO = 16842807; ! Maximum Declared Object ! literal NFB$C_LNI_COL = 16908352; ! Collating field literal NFB$C_LNI_NAM = 16908353; ! Local node name literal NFB$C_LNI_CNT = 16908354; ! Counters literal NFB$C_LNI_IDE = 16908355; ! Identification literal NFB$C_LNI_MVE = 16908356; ! Management version literal NFB$C_LNI_NVE = 16908357; ! Nsp version literal NFB$C_LNI_RVE = 16908358; ! Routing version literal NFB$C_LNI_PHA = 16908359; ! Physical NI address (current address) literal NFB$C_LNI_IDP = 16908360; ! IDP of ISO address literal NFB$C_LNI_DNM = 16908361; ! DNS namespace ! literal NFB$C_OBI_LCK = 50331649; ! Set if conditionally writable fields are not writable literal NFB$C_OBI_SET = 50331650; ! Set if a "set" QIO has ever modified the CNF. If ! not then the CNF was due to a "declare name/obect" ! only and may be deleted when the declaring process ! breaks the channel over which the object was declared literal NFB$C_OBI_ALO = 50331651; ! Alias Outgoing enabled/disabled literal NFB$C_OBI_ALI = 50331652; ! Alias Incoming enabled/disabled ! literal NFB$C_OBI_LPR = 50397200; ! Low order privileges literal NFB$C_OBI_HPR = 50397201; ! High order privileges literal NFB$C_OBI_DOV = 50397202; ! Point to Owners UCB literal NFB$C_OBI_CHN = 50397203; ! Owner's channel literal NFB$C_OBI_NUM = 50397204; ! Number literal NFB$C_OBI_PID = 50397205; ! Process id literal NFB$C_OBI_PRX = 50397206; ! Proxy login switch (inbound, outbound, etc) ! literal NFB$C_OBI_COL = 50462784; ! Collating field literal NFB$C_OBI_ZNA = 50462785; ! Zero obj+name identifier literal NFB$C_OBI_SFI = 50462786; ! Parsed file i.d. literal NFB$C_OBI_IAC = 50462787; ! Default inbound combined access control string literal NFB$C_OBI_NAM = 50462788; ! Name literal NFB$C_OBI_FID = 50462789; ! File id literal NFB$C_OBI_USR = 50462790; ! User id literal NFB$C_OBI_ACC = 50462791; ! Account literal NFB$C_OBI_PSW = 50462792; ! Password literal NFB$C_OBI_OCPRV = 50462793; ! Outgoing Connect Privileges ! literal NFB$C_CRI_LCK = 67108865; ! D Set if conditionally writable fields are ! not writable literal NFB$C_CRI_SER = 67108866; ! D Set if Service functions not allowed literal NFB$C_CRI_BLK_FILL = 67108867; ! Filler (BLK retired) literal NFB$C_CRI_VER_FILL = 67108868; ! Filler (VER retired) literal NFB$C_CRI_DLM = 67108869; ! E Circuit to be used as X.25 datalink, if set ! If clear, circuit is for X.25 native use literal NFB$C_CRI_OWPID = 67174416; ! D PID of temp owner of line in service state literal NFB$C_CRI_CTA = 67174417; ! D Absolute due time for counter logging literal NFB$C_CRI_SRV = 67174418; ! D Service substate qualifier literal NFB$C_CRI_STA = 67174419; ! C State literal NFB$C_CRI_SUB = 67174420; ! C Substate literal NFB$C_CRI_LCT = 67174421; ! C Counter timer literal NFB$C_CRI_PNA = 67174422; ! E Adjacent node address literal NFB$C_CRI_BLO = 67174423; ! E Partner's receive block size literal NFB$C_CRI_COS = 67174424; ! E Cost literal NFB$C_CRI_HET = 67174425; ! E Hello timer literal NFB$C_CRI_LIT = 67174426; ! E Listen timer literal NFB$C_CRI_MRC = 67174427; ! E Maximum recalls literal NFB$C_CRI_RCT = 67174428; ! E Recall timer literal NFB$C_CRI_POL = 67174429; ! D Polling state literal NFB$C_CRI_PLS = 67174430; ! D Polling substate literal NFB$C_CRI_USE = 67174431; ! X Usage literal NFB$C_CRI_TYP = 67174432; ! C Type literal NFB$C_CRI_CHN = 67174433; ! X X.25 Channel literal NFB$C_CRI_MBL = 67174434; ! X Maximum block literal NFB$C_CRI_MWI = 67174435; ! X Maximum window literal NFB$C_CRI_TRI = 67174436; ! D Tributary literal NFB$C_CRI_BBT = 67174437; ! D Babble timer literal NFB$C_CRI_TRT = 67174438; ! D Transmit timer literal NFB$C_CRI_MRB = 67174439; ! D Maximum receive buffers literal NFB$C_CRI_MTR = 67174440; ! D Maximum transmits literal NFB$C_CRI_ACB = 67174441; ! D Active base literal NFB$C_CRI_ACI = 67174442; ! D Active increment literal NFB$C_CRI_IAB = 67174443; ! D Inactive base literal NFB$C_CRI_IAI = 67174444; ! D Inactive increment literal NFB$C_CRI_IAT = 67174445; ! D Inactive threshold literal NFB$C_CRI_DYB = 67174446; ! D Dying base literal NFB$C_CRI_DYI = 67174447; ! D Dying increment literal NFB$C_CRI_DYT = 67174448; ! D Dying threshold literal NFB$C_CRI_DTH = 67174449; ! D Dead threshold literal NFB$C_CRI_MST = 67174450; ! D Maintenance mode state (0 => On, 1 => Off> literal NFB$C_CRI_XPT = 67174451; ! E Transport protocol to use literal NFB$C_CRI_MRT = 67174452; ! E Maximum routers on this NI literal NFB$C_CRI_RPR = 67174453; ! E Router priority literal NFB$C_CRI_DRT = 67174454; ! E Designated router on NI (node address) literal NFB$C_CRI_VER = 67174455; ! D Verification Enabled/Disabled/Inbound on circuit ! literal NFB$C_CRI_COL = 67240000; ! D Collating field literal NFB$C_CRI_NAM = 67240001; ! C Circuit name literal NFB$C_CRI_VMSNAM = 67240002; ! D Device name in VMS format literal NFB$C_CRI_CHR = 67240003; ! D Characteristics buffer for startup control QIO literal NFB$C_CRI_CNT = 67240004; ! C Counters literal NFB$C_CRI_P2P = 67240005; ! D Line's PhaseII partner name (for loopback) literal NFB$C_CRI_LOO = 67240006; ! E Loopback name literal NFB$C_CRI_PNN = 67240007; ! E Adjacent node name literal NFB$C_CRI_NUM = 67240008; ! X Call Number literal NFB$C_CRI_DTE = 67240009; ! X DTE literal NFB$C_CRI_DEVNAM = 67240010; ! D Device name in VMS format, with unit included literal NFB$C_CRI_net = 67240011; ! XD Network name ! literal NFB$C_PLI_LCK = 83886081; ! D Set if conditionally writable fields are ! not writable literal NFB$C_PLI_SER = 83886082; ! D Service literal NFB$C_PLI_DUP = 83886083; ! C Duplex (set if half) literal NFB$C_PLI_CON = 83886084; ! C Controller (set if loopback) literal NFB$C_PLI_CLO = 83886085; ! C Clock mode (set if internal) literal NFB$C_PLI_SWI = 83886086; ! D Async Line - Switch literal NFB$C_PLI_HNG = 83886087; ! D Async Line - Hangup ! literal NFB$C_PLI_CTA = 83951632; ! D Absolute time for counter read and clear literal NFB$C_PLI_STA = 83951633; ! C State literal NFB$C_PLI_SUB = 83951634; ! C Substate literal NFB$C_PLI_LCT = 83951635; ! D Counter timer literal NFB$C_PLI_PRO = 83951636; ! C Protocol literal NFB$C_PLI_STI = 83951637; ! D Service timer literal NFB$C_PLI_HTI = 83951638; ! L Holdback timer literal NFB$C_PLI_MBL = 83951639; ! L Maximum block literal NFB$C_PLI_MRT = 83951640; ! L Maximum retransmits literal NFB$C_PLI_MWI = 83951641; ! L Maximum window literal NFB$C_PLI_SLT = 83951642; ! D Scheduling timer literal NFB$C_PLI_DDT = 83951643; ! D Dead timer literal NFB$C_PLI_DLT = 83951644; ! D Delay timer literal NFB$C_PLI_SRT = 83951645; ! D Stream timer literal NFB$C_PLI_BFN = 83951646; ! D Receive buffers literal NFB$C_PLI_BUS = 83951647; ! D Action routine returns bufsiz used for line literal NFB$C_PLI_PLVEC = 83951648; ! D PLVEC i.d. literal NFB$C_PLI_RTT = 83951649; ! D Retransmit timer literal NFB$C_PLI_MOD = 83951650; ! L X.25 mode (DCE, DTE, etc). literal NFB$C_PLI_LPC = 83951651; ! L Loop count literal NFB$C_PLI_LPL = 83951652; ! L Loop length literal NFB$C_PLI_LPD = 83951653; ! L Loop Data type literal NFB$C_PLI_EPT = 83951654; ! E Ethernet protocol type for datalink literal NFB$C_PLI_LNS = 83951655; ! D Async Line - Line speed literal NFB$C_PLI_BFS = 83951656; ! C Line buffer size (overrides executor bufsiz) literal NFB$C_PLI_TPI = 83951657; ! D Transmit Pipeline literal NFB$C_PLI_TREQ = 83951658; ! F Requested TRT literal NFB$C_PLI_TVX = 83951659; ! F Valid transmission time literal NFB$C_PLI_REST_TTO = 83951660; ! F Restricted token timeout literal NFB$C_PLI_RPE = 83951661; ! F Ring purger enable literal NFB$C_PLI_ECHO_DAT = 83951662; ! F Echo data literal NFB$C_PLI_ECHO_LEN = 83951663; ! F Echo length literal NFB$C_PLI_T_NEG = 83951664; ! F Negotiated TRT literal NFB$C_PLI_DAT = 83951665; ! F Duplicate address flag literal NFB$C_PLI_UN_DAT = 83951666; ! F Upstream neighbor DA flag literal NFB$C_PLI_RPS = 83951667; ! F Ring purger state literal NFB$C_PLI_RER = 83951668; ! F Ring error reason literal NFB$C_PLI_NBR_PHY = 83951669; ! F Neighbor PHY type literal NFB$C_PLI_LEE = 83951670; ! F Link error estimate literal NFB$C_PLI_RJR = 83951671; ! F Reject reason ! literal NFB$C_PLI_COL = 84017216; ! D Collating field literal NFB$C_PLI_NAM = 84017217; ! C Line name literal NFB$C_PLI_VMSNAM = 84017218; ! D Device name in VMS format literal NFB$C_PLI_CHR = 84017219; ! D Set-mode $QIO line Characteristics buffer literal NFB$C_PLI_CNT = 84017220; ! C Counters literal NFB$C_PLI_MCD = 84017221; ! L Filespec for microcode dump (initiates dump) literal NFB$C_PLI_HWA = 84017222; ! D NI hardware address (ROM address) literal NFB$C_PLI_DEVNAM = 84017223; ! D Device name in VMS format, with unit included literal NFB$C_PLI_NET = 84017224; ! L Network name literal NFB$C_PLI_NIF_TARG = 84017225; ! F NIF target literal NFB$C_PLI_SIF_CONF_TARG = 84017226; ! F SIF configuration target literal NFB$C_PLI_SIF_OP_TARG = 84017227; ! F SIF operation target literal NFB$C_PLI_ECHO_TARG = 84017228; ! F Echo target literal NFB$C_PLI_MAC_CHR = 84017229; ! F Set-mode $QIO MAC line characteristics buffer literal NFB$C_PLI_UNA = 84017230; ! F Upstream neighbor literal NFB$C_PLI_OLD_UNA = 84017231; ! F Old upstream neighbor literal NFB$C_PLI_DNA = 84017232; ! F Downstream neighbor literal NFB$C_PLI_OLD_DNA = 84017233; ! F Old downstream neighbor ! literal NFB$C_EFI_LCK = 100663297; ! Set if conditionally writable fields are not writable ! literal NFB$C_EFI_SIN = 100728848; literal NFB$C_EFI_SP1 = 100728849; literal NFB$C_EFI_B1 = 100728850; literal NFB$C_EFI_B2 = 100728851; ! literal NFB$C_EFI_COL = 100794432; ! Collating field literal NFB$C_EFI_EVE = 100794433; literal NFB$C_EFI_SB1 = 100794434; literal NFB$C_EFI_SB2 = 100794435; literal NFB$C_EFI_SB3 = 100794436; ! literal NFB$C_ESI_LCK = 117440513; ! Set if conditionally writable fields are not writable ! literal NFB$C_ESI_SNK = 117506064; literal NFB$C_ESI_STA = 117506065; literal NFB$C_ESI_SP1 = 117506066; literal NFB$C_ESI_B1 = 117506067; literal NFB$C_ESI_B2 = 117506068; ! literal NFB$C_ESI_COL = 117571648; ! Collating field literal NFB$C_ESI_LNA = 117571649; literal NFB$C_ESI_SB1 = 117571650; literal NFB$C_ESI_SB2 = 117571651; literal NFB$C_ESI_SB3 = 117571652; ! literal NFB$C_LLI_LCK = 134217729; ! Set if conditionally writable fields are not writable ! literal NFB$C_LLI_DLY = 134283280; ! Round trip delay time literal NFB$C_LLI_STA = 134283281; ! State literal NFB$C_LLI_LLN = 134283282; ! Local link number literal NFB$C_LLI_RLN = 134283283; ! Remote link number literal NFB$C_LLI_PNA = 134283284; ! Partner's node address literal NFB$C_LLI_PID = 134283285; ! External Process I.D. literal NFB$C_LLI_IPID = 134283286; ! Internal Process I.D. literal NFB$C_LLI_XWB = 134283287; ! Pointer to XWB literal NFB$C_LLI_CNT = 134283288; ! Counters ! literal NFB$C_LLI_COL = 134348864; ! Collating field literal NFB$C_LLI_USR = 134348865; ! User name literal NFB$C_LLI_PRC = 134348866; ! Process name literal NFB$C_LLI_PNN = 134348867; ! Partner's node name literal NFB$C_LLI_RID = 134348868; ! Partner's process i.d. ! literal NFB$C_XNI_LCK = 150994945; ! Set if conditionally writable fields are not writable literal NFB$C_XNI_MNS_FILL = 150994946; ! X.25 multi-network support (set if enabled) [No longer used] ! literal NFB$C_XNI_CAT = 151060496; ! Call timer literal NFB$C_XNI_CLT = 151060497; ! Clear timer literal NFB$C_XNI_DBL = 151060498; ! Default data literal NFB$C_XNI_DWI = 151060499; ! Default window literal NFB$C_XNI_MBL = 151060500; ! Maximum data literal NFB$C_XNI_MCL = 151060501; ! Maximum clears literal NFB$C_XNI_MRS = 151060502; ! Maximum resets literal NFB$C_XNI_MST = 151060503; ! Maximum restarts literal NFB$C_XNI_MWI = 151060504; ! Maximum window literal NFB$C_XNI_RST = 151060505; ! Reset timer literal NFB$C_XNI_STT = 151060506; ! Restart timer ! literal NFB$C_XNI_COL = 151126080; ! Collating field literal NFB$C_XNI_netent = 151126081; ! Network literal NFB$C_XNI_PROF = 151126082; ! Profile name ! literal NFB$C_XDI_LCK = 184549377; ! Set if conditionally writable fields are not writable ! literal NFB$C_XDI_ACH = 184614928; ! Active channels literal NFB$C_XDI_ASW = 184614929; ! Active switched literal NFB$C_XDI_CTM = 184614930; ! Counter timer literal NFB$C_XDI_MCH = 184614931; ! Maximum channels literal NFB$C_XDI_STA = 184614932; ! State literal NFB$C_XDI_SUB = 184614933; ! Substate literal NFB$C_XDI_MCI = 184614934; ! Maximum circuits [VMS only] literal NFB$C_XDI_CAT = 184614935; ! Call timer literal NFB$C_XDI_CLT = 184614936; ! Clear timer literal NFB$C_XDI_DBL = 184614937; ! Default data literal NFB$C_XDI_DWI = 184614938; ! Default window literal NFB$C_XDI_MBL = 184614939; ! Maximum data literal NFB$C_XDI_MCL = 184614940; ! Maximum clears literal NFB$C_XDI_MRS = 184614941; ! Maximum resets literal NFB$C_XDI_MST = 184614942; ! Maximum restarts literal NFB$C_XDI_MWI = 184614943; ! Maximum window literal NFB$C_XDI_RST = 184614944; ! Reset timer literal NFB$C_XDI_STT = 184614945; ! Restart timer literal NFB$C_XDI_mode = 184614946; ! DTE Mode literal NFB$C_XDI_itt = 184614947; ! Interrupt timer ! literal NFB$C_XDI_COL = 184680512; ! Collating field literal NFB$C_XDI_DTE = 184680513; ! DTE address literal NFB$C_XDI_CHN = 184680514; ! Channels literal NFB$C_XDI_LIN = 184680515; ! Line literal NFB$C_XDI_dnt = 184680516; ! Network literal NFB$C_XDI_CNT = 184680517; ! Counters ! literal NFB$C_XGI_LCK = 167772161; ! Set if conditionally writable fields are not writable ! literal NFB$C_XGI_GNM = 167837712; ! Group number literal NFB$C_XGI_GTY = 167837713; ! Group type ! literal NFB$C_XGI_COL = 167903296; ! Collating field. This field must be unique across ! all entries in this database. It consists of the ! group-name string followed by the DTE address. literal NFB$C_XGI_GRP = 167903297; ! Group name literal NFB$C_XGI_GDT = 167903298; ! Group DTE address literal NFB$C_XGI_gnt = 167903299; ! Group Network ! literal NFB$C_XS5_LCK = 201326593; ! Set if conditionally writable fields are not writable ! literal NFB$C_XS5_MCI = 201392144; ! Maximum circuits allowed literal NFB$C_XS5_STA = 201392145; ! State literal NFB$C_XS5_ACI = 201392146; ! Active circuits literal NFB$C_XS5_CTM = 201392147; ! Counter timer ! literal NFB$C_XS5_COL = 201457728; ! Collating field. This field must be unique across ! all entries in this database. literal NFB$C_XS5_CNT = 201457729; ! Counters ! literal NFB$C_XD5_LCK = 218103809; ! Set if conditionally writable fields are not writable ! literal NFB$C_XD5_PRI = 218169360; ! Priority literal NFB$C_XD5_SAD = 218169361; ! Subaddress range ! (lower word = lower limit, upper word = upper limit) literal NFB$C_XD5_NOD = 218169362; ! Remote node address containing server (gateways only) literal NFB$C_XD5_red = 218169363; ! Redirect reason ! literal NFB$C_XD5_COL = 218234944; ! Collating field. This field must be unique across ! all entries in this database. literal NFB$C_XD5_DST = 218234945; ! Destination DTE address literal NFB$C_XD5_CMK = 218234946; ! Call mask literal NFB$C_XD5_CVL = 218234947; ! Call value literal NFB$C_XD5_GRP = 218234948; ! Group name literal NFB$C_XD5_SDTE = 218234949; ! Sending DTE address (formally number) literal NFB$C_XD5_OBJ = 218234950; ! && Object name literal NFB$C_XD5_FIL = 218234951; ! Command procedure to execute when starting object literal NFB$C_XD5_USR = 218234952; ! User name literal NFB$C_XD5_PSW = 218234953; ! Password literal NFB$C_XD5_ACC = 218234954; ! Account literal NFB$C_XD5_cdte = 218234955; ! Called DTE literal NFB$C_XD5_rdte = 218234956; ! Receiving DTE literal NFB$C_XD5_net = 218234957; ! Network literal NFB$C_XD5_emk = 218234958; ! Extension mask literal NFB$C_XD5_evl = 218234959; ! Extension value literal NFB$C_XD5_acl = 218234960; ! ACL, a list of ACE'structure, parto of ORB literal NFB$C_XD5_idte = 218234961; ! Incoming address ! literal NFB$C_XS9_LCK = 234881025; ! Set if conditionally writable fields are not writable ! literal NFB$C_XS9_MCI = 234946576; ! Maximum circuits allowed literal NFB$C_XS9_STA = 234946577; ! State literal NFB$C_XS9_ACI = 234946578; ! Active circuits literal NFB$C_XS9_CTM = 234946579; ! Counter timer ! literal NFB$C_XS9_COL = 235012160; ! Collating field. This field must be unique across ! all entries in this database. literal NFB$C_XS9_CNT = 235012161; ! Counters ! literal NFB$C_XD9_LCK = 251658241; ! Set if conditionally writable fields are not writable ! literal NFB$C_XD9_PRI = 251723792; ! Priority literal NFB$C_XD9_SAD = 251723793; ! Subaddress range ! (lower word = lower limit, upper word = upper limit) literal NFB$C_XD9_NOD = 251723794; ! Remote node address containing server (gateways only) literal NFB$C_XD9_red = 251723795; ! Redirect reason ! literal NFB$C_XD9_COL = 251789376; ! Collating field. This field must be unique across ! all entries in this database. literal NFB$C_XD9_DST = 251789377; ! Destination DTE address literal NFB$C_XD9_CMK = 251789378; ! Call mask literal NFB$C_XD9_CVL = 251789379; ! Call value literal NFB$C_XD9_GRP = 251789380; ! Group name literal NFB$C_XD9_sdte = 251789381; ! Sending DTE literal NFB$C_XD9_OBJ = 251789382; ! && Object name literal NFB$C_XD9_FIL = 251789383; ! Command procedure to execute when starting object literal NFB$C_XD9_USR = 251789384; ! User name literal NFB$C_XD9_PSW = 251789385; ! Password literal NFB$C_XD9_ACC = 251789386; ! Account literal NFB$C_XD9_cdte = 251789387; ! Caller DTE literal NFB$C_XD9_rdte = 251789388; ! Receiving DTE literal NFB$C_XD9_net = 251789389; ! Network literal NFB$C_XD9_emk = 251789390; ! Extension mask literal NFB$C_XD9_evl = 251789391; ! Extension value literal NFB$C_XD9_acl = 251789392; ! ACL, a list of ACE'structure, parto of ORB literal NFB$C_XD9_idte = 251789393; ! Incoming address ! literal NFB$C_XTI_LCK = 268435457; ! Set if conditionally writable fields are not writable ! literal NFB$C_XTI_STA = 268501008; ! State literal NFB$C_XTI_BFZ = 268501009; ! Buffer size literal NFB$C_XTI_CPL = 268501010; ! Capture limit literal NFB$C_XTI_MBK = 268501011; ! Maximum blocks/file literal NFB$C_XTI_MBF = 268501012; ! Maximum number of buffers literal NFB$C_XTI_MVR = 268501013; ! Maximum trace file version number ! literal NFB$C_XTI_COL = 268566592; ! Collating field. This field must be unique across ! all entries in this database. literal NFB$C_XTI_FNM = 268566593; ! Trace file name ! literal NFB$C_XTT_LCK = 285212673; ! Set if conditionally writable fields are not writable ! literal NFB$C_XTT_TST = 285278224; ! State literal NFB$C_XTT_CPS = 285278225; ! Capture size ! literal NFB$C_XTT_COL = 285343808; ! Collating field. This field must be unique across ! all entries in this database. literal NFB$C_XTT_TPT = 285343809; ! Tracepoint name ! literal NFB$C_XAI_LCK = 452984833; ! Set if conditionally writable fields are not writable ! literal NFB$C_XAI_NDA = 453050384; ! Node address ! literal NFB$C_XAI_COL = 453115968; ! Collating field literal NFB$C_XAI_NET = 453115969; ! Network literal NFB$C_XAI_USR = 453115970; ! User id literal NFB$C_XAI_PSW = 453115971; ! Password literal NFB$C_XAI_ACC = 453115972; ! Account literal NFB$C_XAI_NOD = 453115973; ! Node id ! literal NFB$C_XDTE_LCK = 352321537; ! Set if conditionally writable fields are not writable ! C(,$C_XDTE_,(((NFB$C_DB_XDTE@24)+(NFB$C_TYP_LNG@16)+16)),1 literal NFB$C_XDTE_COL = 352452672; ! Collating field literal NFB$C_XDTE_NET = 352452673; ! Network literal NFB$C_XDTE_DTE = 352452674; ! DTE address literal NFB$C_XDTE_ID = 352452675; ! ID list, ARB rights list literal NFB$C_XDTE_ACL = 352452676; ! ACL, a list of ACE's, part of ORB ! literal NFB$C_SPI_LCK = 301989889; ! Set if conditionally writable fields are not writable literal NFB$C_SPI_PRL = 301989890; ! Proxy flag which initially started server process ! literal NFB$C_SPI_PID = 302055440; ! Server PID literal NFB$C_SPI_IRP = 302055441; ! IRP of waiting DECLSERV QIO (0 if process active) literal NFB$C_SPI_CHN = 302055442; ! Channel associated with DECLSERV IRP literal NFB$C_SPI_RNA = 302055443; ! Remote node address which initially started server ! literal NFB$C_SPI_COL = 302121024; ! Collating field literal NFB$C_SPI_ACS = 302121025; ! ACS used to initally start server process literal NFB$C_SPI_RID = 302121026; ! Remote user ID which initially started server literal NFB$C_SPI_SFI = 302121027; ! Last (current) SFI given to server process literal NFB$C_SPI_NCB = 302121028; ! Last (current) NCB given to server process literal NFB$C_SPI_PNM = 302121029; ! Last (current) process name given to server ! literal NFB$C_AJI_LCK = 318767105; ! Set if conditionally writable fields are not writable literal NFB$C_AJI_REA = 318767106; ! Reachable (set if two-way communication established) literal NFB$C_AJI_RRA = 318767107; ! Reachable Routing Adjacency ! literal NFB$C_AJI_ADD = 318832656; ! Node address literal NFB$C_AJI_TYP = 318832657; ! Node type literal NFB$C_AJI_LIT = 318832658; ! Listen timer for this adjacency literal NFB$C_AJI_BLO = 318832659; ! Partner's block size literal NFB$C_AJI_RPR = 318832660; ! Partner's router priority (on NI) ! literal NFB$C_AJI_COL = 318898240; ! Collating field literal NFB$C_AJI_NNA = 318898241; ! Node name literal NFB$C_AJI_CIR = 318898242; ! Circuit name ! literal NFB$C_SDI_LCK = 436207617; ! Set if conditionally writable fields are not writable ! literal NFB$C_SDI_SUB = 436273168; ! Service substate literal NFB$C_SDI_PID = 436273169; ! PID of process owning this DLE link ! literal NFB$C_SDI_COL = 436338752; ! Collating field literal NFB$C_SDI_CIR = 436338753; ! Circuit name literal NFB$C_SDI_PHA = 436338754; ! Service physical address (BC only) literal NFB$C_SDI_PRC = 436338755; ! Name of process owning this DLE link ! literal NFB$C_ARI_LCK = 335544321; ! Set if conditionally writable fields are not writable literal NFB$C_ARI_REA = 335544322; ! Set if node is reachable ! literal NFB$C_ARI_ADD = 335609872; ! Address literal NFB$C_ARI_DCO = 335609873; ! Destination Cost literal NFB$C_ARI_DHO = 335609874; ! Destination Hops literal NFB$C_ARI_NND = 335609875; ! Next node address ! literal NFB$C_ARI_COL = 335675456; ! Collating field literal NFB$C_ARI_DLI = 335675457; ! Circuit used for normal traffic to area ! literal NFB$C_PROXY_LCK = 469762049; ! Set if conditionally writable fields are not writable ! literal NFB$C_PROXY_RUIC = 469827600; ! Remote UIC ! literal NFB$C_PROXY_RNODE = 469893184; ! Remote node literal NFB$C_PROXY_RNAME = 469893185; ! Remote user name literal NFB$C_PROXY_DEFACCOUNT = 469893186; ! Default local proxy account literal NFB$C_PROXY_ACCOUNT1 = 469893187; ! Local proxy account literal NFB$C_PROXY_ACCOUNT2 = 469893188; ! Local proxy account literal NFB$C_PROXY_ACCOUNT3 = 469893189; ! Local proxy account literal NFB$C_PROXY_ACCOUNT4 = 469893190; ! Local proxy account literal NFB$C_PROXY_ACCOUNT5 = 469893191; ! Local proxy account literal NFB$C_PROXY_ACCOUNT6 = 469893192; ! Local proxy account literal NFB$C_PROXY_ACCOUNT7 = 469893193; ! Local proxy account literal NFB$C_PROXY_ACCOUNT8 = 469893194; ! Local proxy account literal NFB$C_PROXY_ACCOUNT9 = 469893195; ! Local proxy account literal NFB$C_PROXY_ACCOUNT10 = 469893196; ! Local proxy account literal NFB$C_PROXY_ACCOUNT11 = 469893197; ! Local proxy account literal NFB$C_PROXY_ACCOUNT12 = 469893198; ! Local proxy account literal NFB$C_PROXY_ACCOUNT13 = 469893199; ! Local proxy account literal NFB$C_PROXY_ACCOUNT14 = 469893200; ! Local proxy account literal NFB$C_PROXY_ACCOUNT15 = 469893201; ! Local proxy account literal NFB$C_PROXY_HASHKEY = 469893202; ! Hash key lookup string literal NFB$C_PROXY_COL = 469893184; ! Collating field literal NFB$C_PROXY_MAXACC = 15; ! Maximum numver of local proxy accounts ! including the default literal NFB$S_NFBDEF4 = 2; ! old size name - synonym literal NFB$S_NFB4 = 2; macro NFB$W_STR_COUNT = 0,0,16,0 %; ! String count field macro NFB$B_STR_TEXT = 2,0,0,0 %; ! Start of string data ! ! Define identifiers for each parameter in all database ! ! ** The low order 16 bits for each parameter must be unique ** ! *** with respect to all other parameters in its particular *** ! ** database. ** ! ! Define a field identifier index for each parameter in the NDI database. ! ! ! Boolean parameters ! ! "Longword" Parameters ! ! String parameters ! ! Define a field identifier index for each parameter in the LNI database. ! ! ! Boolean parameters ! ! "Longword parameters ! ! String parameters ! ! Define a field identifier index for each parameter in the OBI database. ! ! ! Boolean Parameters ! ! Longword Parameters ! ! String Parameters ! ! Define a field identifier index for each parameter in the CRI database. ! ! ! /* Use ! /* ---- ! C = common ! E = Executor (used by Transport) ! X = Native X.25 network management ! D = DECnet (not X.25) ! ! ! Boolean Parameters ! ! ! "Longword" parameters ! ! String Parameters ! ! Define a field identifier index for each parameter in the PLI database. ! ! C = common ! L = LAPB (X.25) ! D = DDCMP (not X.25) ! E = Ethernet ! F = FDDI ! T = Token Ring ! ! /* Use ! ---- ! ! Boolean Parameters ! ! "Longword" Parameters ! ! String Parameters ! ! Define a field identifier index for each parameter in the EFI database. ! ! ! Boolean Parameters ! ! "Longword" Parameters ! ! String Parameters ! ! Define a field identifier index for each parameter in the ESI database. ! ! ! Boolean Parameters ! ! "Longword" Parameters ! ! String Parameters ! ! Define a field identifier index for each parameter in the LLI database. ! ! ! Boolean Parameters ! ! Longword Parameters ! ! String Parameters ! ! X.25 network parameters (part of MODULE X25-PROTOCOL) ! ! Define a field identifier index for each parameter in the XNI database. ! ! ! Boolean Parameters ! ! "Longword" Parameters ! ! String Parameters ! ! X.25 DTE parameters (qualified by a given network) ! ! Define a field identifier index for each parameter in the XDI database. ! ! ! Boolean Parameters ! ! "Longword" Parameters ! ! String Parameters ! ! X.25 group parameters (qualified by a given DTE) ! ! Define a field identifier index for each parameter in the XGI database. ! ! ! Boolean Parameters ! ! "Longword" Parameters ! ! String Parameters ! ! X.25 server parameters (global parameters for all destinations) ! ! Define a field identifier index for each parameter in the XS5 database. ! ! ! Boolean Parameters ! ! "Longword" Parameters ! ! String Parameters ! ! X.25 destination parameters (part of MODULE X25-SERVER) ! ! Define a field identifier index for each parameter in the XD5 database. ! ! ! Boolean Parameters ! ! "Longword" Parameters ! ! String Parameters ! ! X.29 server parameters (global parameters for all destinations) ! ! Define a field identifier index for each parameter in the XS9 database. ! ! ! Boolean Parameters ! ! "Longword" Parameters ! ! String Parameters ! ! X.29 destination parameters (part of MODULE X29-SERVER) ! ! Define a field identifier index for each parameter in the XD9 database. ! ! ! Boolean Parameters ! ! "Longword" Parameters ! ! String Parameters ! ! X.25 tracing facility (global) parameters. ! ! Define a field identifier index for each parameter in the XTI database. ! ! ! Boolean Parameters ! ! "Longword" Parameters ! ! String Parameters ! ! X.25 tracpoint (local) parameters. ! ! Define a field identifier index for each parameter in the XTT database. ! ! ! Boolean Parameters ! ! "Longword" Parameters ! ! String Parameters ! ! X.25 Access (qualified by a given network) ! ! Define a field identifier index for each parameter in the XAI database. ! ! ! Boolean Parameters ! ! "Longword" Parameters ! ! String Parameters ! ! X.25 Security (qualified by a given network) ! ! Define a field identifier index for each parameter in the XDTE database. ! ! ! Boolean Parameters ! ! ! "Longword" Parameters ! ! ) ! ! String Parameters ! ! Define SPI (Server Process) parameters ! ! ! Boolean Parameters ! ! Longword Parameters ! ! String Parameters ! ! Define AJI (Adjacency) parameters ! ! ! Boolean Parameters ! ! Longword Parameters ! ! String Parameters ! ! Define SDI (Service DLE) parameters ! ! ! Boolean Parameters ! ! Longword Parameters ! ! String Parameters ! ! Define the AREA database (read only) for level 2 Phase IV routers only. ! ! ! Boolean parameters ! ! "Longword" Parameters ! ! String parameters ! ! Define the PROXY database ! ! ! Boolean parameters ! ! "Longword" Parameters ! ! String parameters ! !*** MODULE $DRDEF *** ! ! DISCONNECT REASONS ! literal NET$C_DR_NORMAL = 0; ! NO ERROR (SYNCH DISCONNECT) literal NET$C_DR_RSU = 1; ! COULDN'T ALLOCATE UCB ADDRESS literal NET$C_DR_NONODE = 2; ! Unrecognized node name literal NET$C_DR_SHUT = 3; ! NODE OR LINE SHUTTING DOWN literal NET$C_DR_NOBJ = 4; ! UNKNOWN OBJECT TYPE OR PROCESS literal NET$C_DR_FMT = 5; ! ILLEGAL PROCESS NAME FIELD literal NET$C_DR_BUSY = 6; ! Object too busy literal NET$C_DR_PROTCL = 7; ! GENERAL PROTOCOL ERROR literal NET$C_DR_THIRD = 8; ! THIRD PARTY DISCONNECT literal NET$C_DR_ABORT = 9; ! DISCONNECT ABORT literal NET$C_DR_IVNODE = 2; ! Invalid node name format literal NET$C_DR_NONZ = 21; ! NON-ZERO DST ADDRESS literal NET$C_DR_BADLNK = 22; ! INCONSISTENT DSTLNK literal NET$C_DR_ZERO = 23; ! ZERO SOURCE ADDRESS literal NET$C_DR_BADFC = 24; ! FCVAL ILLEGAL literal NET$C_DR_NOCON = 32; ! NO CONNECT SLOTS AVAILABLE literal NET$C_DR_ACCESS = 34; ! INVALID ACCESS CONTROL literal NET$C_DR_BADSRV = 35; ! LOGICAL LINK SERVICES MISMATCH literal NET$C_DR_ACCNT = 36; ! INVALID ACCOUNT INFORMATION literal NET$C_DR_SEGSIZ = 37; ! SEGSIZE TOO SMALL literal NET$C_DR_EXIT = 38; ! USER EXIT OR TIMEOUT literal NET$C_DR_NOPATH = 39; ! NO PATH TO DESTINATION NODE literal NET$C_DR_LOSS = 40; ! LOSS OF DATA HAS OCCURRED literal NET$C_DR_NOLINK = 41; ! ILLEGAL MSG FOR LINK NOLINK STATE literal NET$C_DR_CONF = 42; ! REAL DISCONNECT CONFIRM literal NET$C_DR_IMLONG = 43; ! IMAGE DATA FIELD TOO LONG literal NET$C_DR_MISLSCV = 50; ! MISSING CRYPTOGRAPHIC KEY literal NET$C_DR_EXPSCV = 51; ! EXPIRED CRYPTOGRAPHIC KEY literal NET$C_DR_MACFAIL = 53; ! INTEGRITY CHECK FAILED literal NET$C_DR_SRVMMAT = 54; ! CRYPTOGRAPHIC SERVICE MISMATCH literal NET$C_DR_VERFAIL = 55; ! CRYPTOGRAPHIC CONNECT VERIFICATION FAILURE literal NET$C_DR_CSWRAP = 56; ! CRYPTOGRAPHIC SEQUENCE SPACE EXHAUSED ! The following two are NOT valid disconnect reason codes. They are ! used locally. These were previously hardcoded in NETDRVSES. literal NET$C_DR_INVALID = 100; ! Link is IO$_DEACCESS'ed literal NET$C_DR_DEACC = 102; ! Reason field never setup !*** MODULE $NMADEF *** ! ! Object type ! literal NMA$C_OBJ_NIC = 19; ! Nice listener ! ! Function codes ! literal NMA$C_FNC_LOA = 15; ! Request down-line load literal NMA$C_FNC_DUM = 16; ! Request up-line dump literal NMA$C_FNC_TRI = 17; ! Trigger bootstrap literal NMA$C_FNC_TES = 18; ! Test literal NMA$C_FNC_CHA = 19; ! Change parameter literal NMA$C_FNC_REA = 20; ! Read information literal NMA$C_FNC_ZER = 21; ! Zero counters literal NMA$C_FNC_SYS = 22; ! System-specific function ! ! Option byte ! ! common to change parameter, read information and zero counters ! literal NMA$M_OPT_ENT = %X'7'; literal NMA$M_OPT_CLE = %X'40'; literal NMA$M_OPT_PER = %X'80'; literal NMA$M_OPT_INF = %X'70'; literal NMA$C_OPINF_SUM = 0; ! Summary literal NMA$C_OPINF_STA = 1; ! Status literal NMA$C_OPINF_CHA = 2; ! Characteristics literal NMA$C_OPINF_COU = 3; ! Counters literal NMA$C_OPINF_EVE = 4; ! Events ! literal NMA$M_OPT_ACC = %X'80'; literal NMA$M_OPT_REA = %X'80'; literal NMA$C_SYS_RST = 1; ! Rsts literal NMA$C_SYS_RSX = 2; ! Rsx family literal NMA$C_SYS_TOP = 3; ! Tops-20 literal NMA$C_SYS_VMS = 4; ! Vms literal NMA$C_SYS_RT = 5; ! RT-11 ! literal NMA$C_ENT_NOD = 0; ! Node literal NMA$C_ENT_LIN = 1; ! Line literal NMA$C_ENT_LOG = 2; ! Logging literal NMA$C_ENT_CIR = 3; ! Circuit literal NMA$C_ENT_MOD = 4; ! Module literal NMA$C_ENT_ARE = 5; ! Area ! literal NMA$C_SENT_PROXY = 2; ! Proxies literal NMA$C_SENT_ALI = 3; ! Alias literal NMA$C_SENT_OBJ = 4; ! Object literal NMA$C_SENT_PRO = 5; ! Process literal NMA$C_SENT_SYS = 6; ! System literal NMA$C_SENT_LNK = 7; ! Links literal NMA$C_SENT_WLD = -30; ! Wildcarded entity literal NMA$M_ENT_EXE = %X'80'; literal NMA$C_ENT_WAR = -7; ! Wildcarded area literal NMA$C_ENT_WAD = -6; ! Wildcarded address literal NMA$C_ENT_ADJ = -4; ! Adjacent literal NMA$C_ENT_ACT = -2; ! Active literal NMA$C_ENT_KNO = -1; ! Known literal NMA$C_ENT_ADD = 0; ! Node address literal NMA$C_ENT_ALL = -3; ! All literal NMA$C_ENT_LOO = -3; ! Loop ! literal NMA$C_SNK_CON = 1; ! Console literal NMA$C_SNK_FIL = 2; ! File literal NMA$C_SNK_MON = 3; ! Monitor ! literal NMA$M_CNT_TYP = %X'FFF'; literal NMA$M_CNT_MAP = %X'1000'; literal NMA$M_CNT_WID = %X'6000'; literal NMA$M_CNT_COU = %X'8000'; literal NMA$M_CNT_WIL = %X'2000'; literal NMA$M_CNT_WIH = %X'4000'; literal NMA$S_NMADEF = 2; ! Old size name - synonym literal NMA$S_NMA = 2; macro NMA$V_OPT_ENT = 0,0,3,0 %; literal NMA$S_OPT_ENT = 3; ! Entity type ! ! change parameter ! macro NMA$V_OPT_CLE = 0,6,1,0 %; ! Clear parameter ! ! common to change parameter or read information ! macro NMA$V_OPT_PER = 0,7,1,0 %; ! Permanent parameters ! ! read information ! macro NMA$V_OPT_INF = 0,4,3,0 %; literal NMA$S_OPT_INF = 3; ! Information type mask ! test ! macro NMA$V_OPT_ACC = 0,7,1,0 %; ! Access control included ! ! zero ! macro NMA$V_OPT_REA = 0,7,1,0 %; ! Read and zero ! ! System types ! ! Entity types. This numbering scheme must be used in non-system-specific ! NICE messages. (See below for conflicting system-specific entities). ! ! System-specific (function 22) entity types. This numbering scheme ! for objects must be used in any entity type in system-specific NICE ! messages. ! macro NMA$V_ENT_EXE = 0,7,1,0 %; ! Executor indicator flag for response messages ! ! Entity identification format types ! ! Logging sink types ! ! Counter data type values ! macro NMA$V_CNT_TYP = 0,0,12,0 %; literal NMA$S_CNT_TYP = 12; ! Type mask macro NMA$V_CNT_MAP = 0,12,1,0 %; ! Bitmapped indicator macro NMA$V_CNT_WID = 0,13,2,0 %; literal NMA$S_CNT_WID = 2; ! Width field mask macro NMA$V_CNT_COU = 0,15,1,0 %; ! Counter indicator macro NMA$V_CNT_WIL = 0,13,1,0 %; ! Width field low bit macro NMA$V_CNT_WIH = 0,14,1,0 %; ! Width field high bit ! ! Node area and address extraction ! literal NMA$M_PTY_TYP = %X'7FFF'; literal NMA$C_PTY_MAX = 15; ! Maximum fields within coded multiple literal NMA$M_PTY_CLE = %X'3F'; literal NMA$M_PTY_MUL = %X'40'; literal NMA$M_PTY_COD = %X'80'; literal NMA$M_PTY_CMU = %X'C0'; literal NMA$M_PTY_NLE = %X'F'; literal NMA$M_PTY_NTY = %X'30'; literal NMA$M_PTY_ASC = %X'40'; literal NMA$C_NTY_DU = 0; ! Unsigned decimal literal NMA$C_NTY_DS = 1; ! Signed decimal literal NMA$C_NTY_H = 2; ! Hexidecimal literal NMA$C_NTY_O = 3; ! Octal ! NLE values (length of number): literal NMA$C_NLE_IMAGE = 0; ! Image field (byte-counted) literal NMA$C_NLE_BYTE = 1; ! Byte literal NMA$C_NLE_WORD = 2; ! Word literal NMA$C_NLE_LONG = 4; ! Longword literal NMA$C_NLE_QUAD = 8; ! Quadword ! literal NMA$C_PTY_AI = 64; ! ASCII image (ASC=1) literal NMA$C_PTY_HI = 32; ! Hex image (NTY=H, NLE=IMAGE) literal NMA$C_PTY_H1 = 33; ! Hex byte (NTY=H, NLE=BYTE) literal NMA$C_PTY_H2 = 34; ! Hex word (NTY=H, NLE=WORD) literal NMA$C_PTY_H4 = 36; ! Hex byte (NTY=H, NLE=LONG) literal NMA$C_PTY_DU1 = 1; ! Decimal unsigned byte (NTY=DU,NLE=BYTE) literal NMA$C_PTY_DU2 = 2; ! Decimal unsigned word (NTY=DU,NLE=WORD) literal NMA$C_PTY_CD1 = 129; ! Coded decimal byte (COD=1, 1 byte) literal NMA$C_PTY_CM2 = 194; ! Coded multiple, 2 fields literal NMA$C_PTY_CM3 = 195; ! Coded multiple, 3 fields literal NMA$C_PTY_CM4 = 196; ! Coded multiple, 4 fields literal NMA$C_PTY_CM5 = 197; ! Coded multiple, 5 fields ! literal NMA$C_CTLVL_UI = 3; ! User interface literal NMA$C_CTLVL_XID = 175; ! literal NMA$C_CTLVL_XID_P = 191; ! literal NMA$C_CTLVL_TEST = 227; ! literal NMA$C_CTLVL_TEST_P = 243; ! ! literal NMA$C_PCCI_STA = 0; ! State (coded byte of NMA$C_STATE_) literal NMA$C_PCCI_SUB = 1; ! Substate (coded byte of NMA$C_LINSS_) literal NMA$C_PCCI_SER = 100; ! Service (coded byte of NMA$C_LINSV_) literal NMA$C_PCCI_LCT = 110; ! Counter timer (word) literal NMA$C_PCCI_SPY = 120; ! Service physical address (NI address) literal NMA$C_PCCI_SSB = 121; ! Service substate (coded byte of NMA$C_LINSS_) literal NMA$C_PCCI_CNO = 200; ! Connected node literal NMA$C_PCCI_COB = 201; ! Connected object literal NMA$C_PCCI_LOO = 400; ! Loopback name (ascic) literal NMA$C_PCCI_ADJ = 800; ! Adjacent node literal NMA$C_PCCI_DRT = 801; ! Designated router on NI literal NMA$C_PCCI_BLO = 810; ! Block size (word) literal NMA$C_PCCI_COS = 900; ! Cost (byte) literal NMA$C_PCCI_MRT = 901; ! Maximum routers on NI (byte) literal NMA$C_PCCI_RPR = 902; ! Router priority on NI (byte) literal NMA$C_PCCI_HET = 906; ! Hello timer (word) literal NMA$C_PCCI_LIT = 907; ! Listen timer (word) literal NMA$C_PCCI_BLK = 910; ! Blocking (coded byte of NMA$C_CIRBLK_) literal NMA$C_PCCI_MRC = 920; ! Maximum recalls (byte) literal NMA$C_PCCI_RCT = 921; ! Recall timer (word) literal NMA$C_PCCI_NUM = 930; ! Number (ascic) literal NMA$C_PCCI_USR = 1000; ! User entity identification literal NMA$C_PCCI_POL = 1010; ! Polling state (coded byte of NMA$C_CIRPST_) literal NMA$C_PCCI_PLS = 1011; ! Polling substate (coded byte) literal NMA$C_PCCI_OWN = 1100; ! Owner entity identification literal NMA$C_PCCI_LIN = 1110; ! Line (ascic) literal NMA$C_PCCI_USE = 1111; ! Usage (coded byte of NMA$C_CIRUS_) literal NMA$C_PCCI_TYP = 1112; ! Type (coded byte of NMA$C_CIRTY_) literal nma$c_pcci_net = 1119; ! Network (ascic) literal NMA$C_PCCI_DTE = 1120; ! DTE (ascic) literal NMA$C_PCCI_CHN = 1121; ! Channel (word) literal NMA$C_PCCI_MBL = 1122; ! Maximum data (word) literal NMA$C_PCCI_MWI = 1123; ! Maximum window (byte) literal NMA$C_PCCI_TRI = 1140; ! Tributary (byte) literal NMA$C_PCCI_BBT = 1141; ! Babble timer (word) literal NMA$C_PCCI_TRT = 1142; ! Transmit timer (word) literal NMA$C_PCCI_RTT = 1143; ! Retransmit timer (word) literal NMA$C_PCCI_MRB = 1145; ! Maximum receive buffers (coded byte) ! 0-254 is value, 255 = UNLIMITED literal NMA$C_PCCI_MTR = 1146; ! Maximum transmits (byte) literal NMA$C_PCCI_ACB = 1150; ! Active base (byte) literal NMA$C_PCCI_ACI = 1151; ! Active increment (byte) literal NMA$C_PCCI_IAB = 1152; ! Inactive base (byte) literal NMA$C_PCCI_IAI = 1153; ! Inactive increment (byte) literal NMA$C_PCCI_IAT = 1154; ! Inactive threshold (byte) literal NMA$C_PCCI_DYB = 1155; ! Dying base (byte) literal NMA$C_PCCI_DYI = 1156; ! Dying increment (byte) literal NMA$C_PCCI_DYT = 1157; ! Dying threshold (byte) literal NMA$C_PCCI_DTH = 1158; ! Dead threshold (byte) ! literal NMA$C_PCCI_RSX_MAC = 2320; ! Multipoint active ratio literal NMA$C_PCCI_RSX_LOG = 2380; ! Logical name literal NMA$C_PCCI_RSX_DLG = 2385; ! Designated name literal NMA$C_PCCI_RSX_ACT = 2390; ! Actual name ! literal NMA$C_PCCI_VER = 2700; ! Verification (coded byte of NMA$C_CIRVE_) literal NMA$C_PCCI_XPT = 2720; ! Transport type (coded byte of NMA$C_CIRXPT_) ! VMS Specific codes that are used for the X21 project literal NMA$C_PCCI_IRC = 2750; ! Incoming Reverse literal NMA$C_PCCI_ORC = 2751; ! Outgoing Reverse literal NMA$C_PCCI_GRP = 2752; ! Cug literal NMA$C_PCCI_NOP = 2753; ! National Facility Data literal NMA$C_PCCI_CAL = 2754; ! Call request "Now/Clear" literal NMA$C_PCCI_INA = 2755; ! Inactive literal NMA$C_PCCI_RED = 2756; ! Redirected status literal NMA$C_PCCI_MOD = 2757; ! Time-cut Mode status "Auto/Noauto" literal NMA$C_PCCI_REQ = 2758; ! Request timer T1 literal NMA$C_PCCI_DTW = 2759; ! Dte waiting timer t2 literal NMA$C_PCCI_PRO = 2760; ! Progress timer t3a literal NMA$C_PCCI_INF = 2761; ! Information timer t4a literal NMA$C_PCCI_ACC = 2762; ! Accepted timer t4b literal NMA$C_PCCI_CLR = 2763; ! Request timer t5 literal NMA$C_PCCI_DTC = 2764; ! Dte clear timer t6 literal NMA$C_PCCI_CCG = 2765; ! Charging timer t7 literal NMA$C_PCCI_ESA = 2766; ! Enhanced Subaddress literal NMA$C_PCCI_DTI = 2767; ! DTE provided info literal NMA$C_PCCI_SWC = 2768; ! Switched - set line leased literal NMA$C_PCCI_TIC = 2769; ! Timecutting on/off literal NMA$C_PCCI_CSG = 2770; ! Send signal-data enable/disable literal NMA$C_PCCI_AAS = 2771; ! Abbreviated address. literal NMA$C_PCCI_DTS = 2772; ! DTE Status literal NMA$C_PCCI_CAS = 2773; ! Call Status literal NMA$C_PCCI_CPS = 2774; ! Call-Progress Status literal NMA$C_PCCI_CNT = 2775; ! Counter . literal NMA$C_PCCI_RAT = 2776; ! Rate item read only for show literal NMA$C_PCCI_PRD = 2777; ! Period hh:mm-hh:mm literal NMA$C_PCCI_DAY = 2778; ! day of week literal NMA$C_PCCI_BFN = 2779; ! number of buffers for driver to issue literal NMA$C_PCCI_BSZ = 2780; ! size of buffer to allocate. literal NMA$C_PCCI_MDM = 2781; ! Modem signals on/off literal NMA$C_PCCI_DTL = 2782; ! DTE-List element. literal NMA$C_PCCI_IDL = 2783; ! Idle time literal NMA$C_PCCI_IMT = 2784; ! Initial Minimum timer literal NMA$C_PCCI_CAC = 2785; ! Call accept control literal NMA$C_PCCI_ORD = 2786; ! Outgoing request Delay literal NMA$C_PCCI_CID = 2787; ! Calling DTE id ! literal NMA$C_PCCI_MST = 2810; ! Maintenance state ! literal NMA$C_PCCI_SRV_LOG = 3380; ! Logical name literal NMA$C_PCCI_SRV_DLG = 3385; ! Designated name literal NMA$C_PCCI_SRV_ACT = 3390; ! Actual name ! literal NMA$C_PCLI_STA = 0; ! State (coded byte of NMA$C_STATE_) literal NMA$C_PCLI_SUB = 1; ! Substate (coded byte of NMA$C_LINSS_) literal NMA$C_PCLI_SER = 100; ! Service (coded byte of NMA$C_LINSV_) literal NMA$C_PCLI_LCT = 110; ! Counter timer (word) literal NMA$C_PCLI_LOO = 400; ! Loopback name (ascic) [V2 only] literal NMA$C_PCLI_ADJ = 800; ! Adjacent node [V2 only] literal NMA$C_PCLI_BLO = 810; ! Block size (word) [V2 only] literal NMA$C_PCLI_COS = 900; ! Cost (byte) [V2 only] literal NMA$C_PCLI_DEV = 1100; ! Device (ascic) literal NMA$C_PCLI_BFN = 1105; ! Receive buffers literal NMA$C_PCLI_CON = 1110; ! Controller (coded byte of NMA$C_LINCN_) literal NMA$C_PCLI_DUP = 1111; ! Duplex (coded byte of NMA$C_DPX_) literal NMA$C_PCLI_PRO = 1112; ! Protocol (coded byte of NMA$C_LINPR_) literal NMA$C_PCLI_LTY = 1112; ! Type (coded byte of NMA$C_LINTY_) [V2 only] literal NMA$C_PCLI_CLO = 1113; ! Clock (coded byte of NMA$C_LINCL_) literal NMA$C_PCLI_STI = 1120; ! Service timer (word) literal NMA$C_PCLI_NTI = 1121; ! Normal timer (word) [V2 only] literal NMA$C_PCLI_RTT = 1121; ! Retransmit timer (word) literal NMA$C_PCLI_HTI = 1122; ! Holdback timer (word) literal NMA$C_PCLI_MBL = 1130; ! Maximum block (word) literal NMA$C_PCLI_MRT = 1131; ! Maximum retransmits (byte) literal NMA$C_PCLI_MWI = 1132; ! Maximum window (byte) literal NMA$C_PCLI_TRI = 1140; ! Tributary (byte) [V2 only] literal NMA$C_PCLI_SLT = 1150; ! Scheduling timer (word) literal NMA$C_PCLI_DDT = 1151; ! Dead timer (word) literal NMA$C_PCLI_DLT = 1152; ! Delay timer (word) literal NMA$C_PCLI_SRT = 1153; ! Stream timer (word) literal NMA$C_PCLI_HWA = 1160; ! Hardware address (NI address) ! literal NMA$C_PCLI_TREQ = 1161; ! Requested TRT literal NMA$C_PCLI_TVX = 1162; ! Valid transmission time literal NMA$C_PCLI_REST_TTO = 1163; ! Restricted token timeout literal NMA$C_PCLI_RPE = 1164; ! Ring purger enable literal NMA$C_PCLI_NIF_TARG = 1165; ! NIF target literal NMA$C_PCLI_SIF_CONF_TARG = 1166; ! SIF configuration target literal NMA$C_PCLI_SIF_OP_TARG = 1167; ! SIF operation target literal NMA$C_PCLI_ECHO_TARG = 1168; ! Echo target literal NMA$C_PCLI_ECHO_DAT = 1169; ! Echo data ! literal NMA$C_PCLI_STN_ADR = 1170; ! Station address literal NMA$C_PCLI_FNC_ADR = 1171; ! Functional address literal NMA$C_PCLI_GRP_ADR = 1172; ! Group address literal NMA$C_PCLI_UNA = 1173; ! Upstream neighbor (in common with FDDI) literal NMA$C_PCLI_RNG_NUM = 1174; ! Ring number literal NMA$C_PCLI_AUTH_PR = 1175; ! Authorized access priority literal NMA$C_PCLI_RNG_SPD = 1176; ! Ring speed literal NMA$C_PCLI_ETR = 1177; ! Early token release literal NMA$C_PCLI_SRC_ROU = 1178; ! Source routing literal NMA$C_PCLI_ADR_TYP = 1179; ! Address type literal NMA$C_PCLI_A_TIM = 1400; ! Aging timer ! literal NMA$C_PCLI_ECHO_LEN = 1180; ! Echo length literal NMA$C_PCLI_LAST_NIF = 1181; ! Last NIF literal NMA$C_PCLI_LAST_SIF = 1182; ! Last SIF literal NMA$C_PCLI_LAST_ECHO = 1183; ! Last echo literal NMA$C_PCLI_T_NEG = 1184; ! Negotiated TRT literal NMA$C_PCLI_DAT = 1185; ! Duplicate address flag literal NMA$C_PCLI_OLD_UNA = 1187; ! Old upstream neighbor literal NMA$C_PCLI_UN_DAT = 1188; ! Upstream neighbor DA flag literal NMA$C_PCLI_DNA = 1189; ! Downstream neighbor literal NMA$C_PCLI_OLD_DNA = 1192; ! Old downstream neighbor literal NMA$C_PCLI_RPS = 1193; ! Ring purger state literal NMA$C_PCLI_RER = 1194; ! Ring error reason literal NMA$C_PCLI_FDE = 1198; ! Full duplex enable literal NMA$C_PCLI_NBR_PHY = 1300; ! Neighbor PHY type literal NMA$C_PCLI_LEE = 1301; ! Link error estimate literal NMA$C_PCLI_RJR = 1302; ! Reject reason literal NMA$C_PCLI_NET = 1190; ! Network name (ascic) literal NMA$C_PCLI_XMD = 1191; ! X.25 line mode (coded byte of NMA$C_X25MD_) ! literal NMA$C_PCLI_RSX_OWN = 2300; ! Owner literal NMA$C_PCLI_RSX_CCS = 2310; ! Controller CSR literal NMA$C_PCLI_RSX_UCS = 2311; ! Unit CSR literal NMA$C_PCLI_RSX_VEC = 2312; ! Vector literal NMA$C_PCLI_RSX_PRI = 2313; ! Priority literal NMA$C_PCLI_RSX_MDE = 2321; ! Dead polling ratio literal NMA$C_PCLI_RSX_LLO = 2330; ! Location ! 0, Firstfit literal NMA$C_PCLI_RSX_LOG = 2380; ! Logical name literal NMA$C_PCLI_RSX_DLG = 2385; ! Designated name literal NMA$C_PCLI_RSX_ACT = 2390; ! Actual name ! literal NMA$C_PCLI_MCD = 2701; ! Micro-code dump filespec (ascic) literal NMA$C_PCLI_EPT = 2720; ! Ethernet Protocol Type (hex word) literal NMA$C_PCLI_LNS = 2730; ! Line speed (word) literal NMA$C_PCLI_SWI = 2740; ! SWITCH (coded byte of nma$c_linswi_) literal NMA$C_PCLI_HNG = 2750; ! HANGUP (coded byte of NMA$C_LINHNG_) literal NMA$C_PCLI_TPI = 2760; ! Transmit pipeline literal nma$c_pcli_nrzi = 2761; ! NRZI bit encoding literal nma$c_pcli_code = 2762; ! Character code (encoded as CODE_) ! This section are parameters for 802 support. literal NMA$C_PCLI_FMT = 2770; ! Packet format(coded of linfm_) literal NMA$C_PCLI_SRV = 2771; ! Driver service coded of linsr literal NMA$C_PCLI_SAP = 2772; ! SAP literal NMA$C_PCLI_GSP = 2773; ! GSP literal NMA$C_PCLI_PID = 2774; ! PID literal NMA$C_PCLI_CNM = 2775; ! Client name literal NMA$C_PCLI_CCA = 2776; ! Can change address literal NMA$C_PCLI_APC = 2777; ! Allow promiscuous client literal NMA$C_PCLI_MED = 2778; ! Communication medium literal NMA$C_PCLI_PNM = 2779; ! Port name literal NMA$C_PCLI_SNM = 2780; ! Station name ! This section for Token Ring-specific line parameters literal NMA$C_PCLI_MONCONTEND = 2781; ! Monitor Contendor literal NMA$C_PCLI_CACHE_ENT = 2782; ! SR Cache Entr literal NMA$C_PCLI_ROUTEDIS = 2783; ! SR Discover Tmr ! This includes generic parameters for LAN devices literal NMA$C_PCLI_LINEMEDIA = 2784; ! UTP, STP, AUI, TP, AUTO, UNSPECIFIED literal NMA$C_PCLI_LINESPEED = 2785; ! 10,100,4,16,1000,10000 ! This section for ATM and Emulated LAN specific line parameters literal NMA$C_PCLI_LES_HWA = 2786; ! LAN Emulation Server Address literal NMA$C_PCLI_PVC_REQ = 2787; ! PVC Request literal NMA$C_PCLI_PVC = 2788; ! PVC List literal NMA$C_PCLI_ELAN_STATE_REQ = 2789; ! Emulated LAN State request literal NMA$C_PCLI_ELAN_STATE_RSP = 2790; ! Emulated LAN State response literal NMA$C_PCLI_EVENT_REQ = 2791; ! Set ATM Event Mask literal NMA$C_PCLI_EVENT = 2792; ! ATM Event Mask literal NMA$C_PCLI_EXT_SENSE_REQ = 2793; ! ATM Extended Sense Request literal NMA$C_PCLI_EXT_SENSE = 2794; ! ATM Extended Sense Response literal NMA$C_PCLI_ELAN_BUS = 2795; ! ELAN Brdcst Server ATM Address literal NMA$C_PCLI_ELAN_PAR = 2796; ! ELAN Parent ATM Device literal NMA$C_PCLI_ELAN_DESC = 2797; ! ELAN Description String literal NMA$C_PCLI_NUM_PVC = 2798; ! Number of PVC literal NMA$C_PCLI_MAXPVC = 64; ! Maximum number of PVC ! This section for ATM Classical IP specific line parameters literal NMA$C_PCLI_CLIP_LIS_HWA = 2702; ! CLIP LIS ATM Address literal NMA$C_PCLI_CLIP_STATE_REQ = 2703; ! CLIP LIS State Request literal NMA$C_PCLI_CLIP_STATE_RSP = 2704; ! CLIP LIS State Response literal NMA$C_PCLI_CLIP_IP_ADDR = 2705; ! CLIP Client IP Address literal NMA$C_PCLI_CLIP_IP_SUBNET = 2706; ! CLIP Client IP Subnet literal NMA$C_PCLI_CLIP_NAME = 2707; ! CLIP LIS Name literal NMA$C_PCLI_CLIP_USER_TYPE = 2708; ! CLIP User type literal NMA$C_PCLI_CLIP_ATM_ADDR = 2709; ! CLIP Client ATM Address literal NMA$C_PCLI_CLIP_PAR = 2711; ! CLIP Parent Device literal NMA$C_PCLI_CLIP_PVC_IP_ADDR = 2712; ! CLIP Parent Device literal NMA$C_PCLI_CLIP_PVC_STATUS = 2713; ! CLIP Parent Device literal NMA$C_PCLI_CLIP_GET_PVC = 2714; ! Sense PVC state ! This section is for Logical LAN specific line parameters literal NMA$C_PCLI_LLAN_STATE_REQ = 2715; ! LLAN State Request literal NMA$C_PCLI_LLAN_STATE_RSP = 2716; ! LLAN State Response literal NMA$C_PCLI_LLAN_FAILSET = 2717; ! LLAN Failset literal NMA$C_PCLI_FAIL_PRI = 2718; ! Failover Priority ! This section is for VLAN specific line parameters literal NMA$C_PCLI_VLAN_DATA = 2719; ! VLAN DATA ! literal NMA$C_PCLI_BUS = 2801; ! Buffer size (word) literal NMA$C_PCLI_NMS = 2810; ! Number of DMP/DMF synch chars (word) literal NMA$C_PCLI_PHA = 2820; ! Physical NI address of UNA (hex string) literal NMA$C_PCLI_DPA = 2821; ! (same as HWA) ; Default UNA physical address (hex string) literal NMA$C_PCLI_PTY = 2830; ! Ethernet Protocol type (word) literal NMA$C_PCLI_MCA = 2831; ! UNA Multicast address list (special) ! (See NMA$C_LINMC_) literal NMA$C_PCLI_JUMBO = 2832; ! Jumbo frames mode literal NMA$C_PCLI_FLOW = 2833; ! Flow control mode literal NMA$C_PCLI_AUTONEG = 2834; ! Auto-negotiation mode literal NMA$C_PCLI_ILP = 2839; ! DELUA Internal Loopback mode ! (coded byte of NMA$C_STATE_) literal NMA$C_PCLI_PRM = 2840; ! UNA Promiscuous mode (coded byte of NMA$C_STATE_) literal NMA$C_PCLI_MLT = 2841; ! UNA Multicast address mode (coded byte of NMA$C_STATE_) literal NMA$C_PCLI_PAD = 2842; ! UNA Padding mode (coded byte of NMA$C_STATE_) literal NMA$C_PCLI_DCH = 2843; ! UNA Data chaining mode (coded byte of NMA$C_STATE_) literal NMA$C_PCLI_CRC = 2844; ! UNA CRC mode (coded byte of NMA$C_STATE_) literal NMA$C_PCLI_HBQ = 2845; ! UNA Hardware Buffer Quota (word) literal NMA$C_PCLI_ACC = 2846; ! UNA protocol access mode (coded byte of NMA$C_ACC_) literal NMA$C_PCLI_EKO = 2847; ! UNA Echo mode (coded byte of NMA$C_STATE_) literal NMA$C_PCLI_BSZ = 2848; ! UNA Device Buffer size literal NMA$C_PCLI_DES = 2849; ! UNA destination Ethernet address literal NMA$C_PCLI_RET = 2850; ! PCL number of retries (word) literal NMA$C_PCLI_MOD = 2851; ! PCL address mode (coded byte of NMA$C_LINMO_) literal NMA$C_PCLI_RIB = 2852; ! PCL retry-if-busy state (coded byte of NMA$C_STATE_) literal NMA$C_PCLI_MNTL = 2860; ! Maintenance loopback mode for devices ! which support several different loop back modes literal NMA$C_PCLI_INTL0 = 2861; ! Internal loopback level 0 literal NMA$C_PCLI_INTL1 = 2862; ! Internal loopback level 1 literal NMA$C_PCLI_INTL2 = 2863; ! Internal loopback level 2 literal NMA$C_PCLI_INTL3 = 2864; ! Internal loopback level 3 literal NMA$C_PCLI_FRA = 2865; ! Framing address for Bisync literal NMA$C_PCLI_STI1 = 2866; ! State info 1st longword literal NMA$C_PCLI_STI2 = 2867; ! State info 2st longword literal NMA$C_PCLI_TMO = 2868; ! Wait for CTS time out value for DMF sync half duplex literal NMA$C_PCLI_MCL = 2869; ! Clear modem on deassign of channel literal NMA$C_PCLI_SYC = 2870; ! BISYNC protocol sync char literal NMA$C_PCLI_BPC = 2871; ! Number of bits per character literal NMA$C_PCLI_MBS = 2872; ! Maximum buffer size literal NMA$C_PCLI_RES = 2873; ! Restart value (coded byte of LINRES_) literal NMA$C_PCLI_XFC = 2874; ! Transmit FC (coded byte of NMA$C_STATE_) literal NMA$C_PCLI_RFC = 2875; ! Receive FC (coded byte of NMA$C_STATE_) ! IO$M_UPDATE_MAP I/O Subfunction parameters (Token Ring) literal NMA$C_PCLI_MAP = 2876; ! FCA Map Functions literal NMA$C_MAP_ADD = 0; ! Add Entry literal NMA$C_MAP_CHANGE = 1; ! Change Entry literal NMA$C_MAP_DELETE = 2; ! Delete Entry literal NMA$C_PCLI_MRB = 2877; ! Maximum Receive Buffers (for user) literal NMA$C_PCLI_MINRCV = 2878; ! Minimum Receive Buffers (for netman) literal NMA$C_PCLI_MAXRCV = 2879; ! Maximum Receive Buffers (for netman) ! IO$M_ROUTE I/O Subfunction parameters (Token Ring) literal NMA$C_PCLI_ROUTE = 2880; ! SR Functions literal NMA$C_SR_ADD = 0; ! Add route literal NMA$C_SR_DEL = 1; ! Delete route literal NMA$C_PCLI_SRC = 2881; ! Source address list ! Regular IO$M_SENSEMODE/IO$M_STARTUP parameters (Token Ring) literal NMA$C_PCLI_FCA = 2883; ! FCA list (RO) literal NMA$C_PCLI_XAC = 2884; ! Xmit AC literal NMA$C_PCLI_RAC = 2885; ! Recv AC literal NMA$C_PCLI_FAMODE = 2886; ! Func. Addr. Mode literal NMA$C_PCLI_SRMODE = 2887; ! SR mode literal NMA$C_SR_TRANSPARENT = 0; ! Xparent SR mode literal NMA$C_SR_SELF = 1; ! SR done by self ! literal NMA$C_PCLI_SRV_OWN = 3300; ! Owner literal NMA$C_PCLI_SRV_UCS = 3311; ! Unit CSR literal NMA$C_PCLI_SRV_VEC = 3312; ! Vector literal NMA$C_PCLI_SRV_PRI = 3313; ! Priority literal NMA$C_PCLI_SRV_LOG = 3380; ! Logical name literal NMA$C_PCLI_SRV_DLG = 3385; ! Designated name literal NMA$C_PCLI_SRV_ACT = 3390; ! Actual name ! literal NMA$C_LINMD_CSMACD = 10; ! literal NMA$C_LINMD_FDDI = 11; ! literal NMA$C_LINMD_CI = 12; ! literal NMA$C_LINMD_TR = 13; ! literal NMA$C_LINMD_ATM = 14; ! ! literal NMA$C_PCCO_RTR = 110; ! Reservation timer (word) ! literal NMA$C_PCLD_ASS = 10; ! Assistance flag (coded byte of NMA$C_ASS_) ! literal NMA$C_PCLP_ASS = 10; ! Assistance flag (coded byte of NMA$C_ASS_) ! literal NMA$C_PCCN_CIR = 100; ! NI circuit name (ascic) literal NMA$C_PCCN_SUR = 110; ! Surveillance flag (coded byte of NMA$C_SUR_) literal NMA$C_PCCN_ELT = 111; ! Elapsed time literal NMA$C_PCCN_PHA = 120; ! Physical address (NI address) literal NMA$C_PCCN_LRP = 130; ! Time of last report literal NMA$C_PCCN_MVR = 20001; ! Maintenance version literal NMA$C_PCCN_FCT = 20002; ! Function list literal NMA$C_PCCN_CUS = 20003; ! Current console user (NI address) literal NMA$C_PCCN_RTR = 20004; ! Reservation timer (word) literal NMA$C_PCCN_CSZ = 20005; ! Command buffer size (word) literal NMA$C_PCCN_RSZ = 20006; ! Response buffer size (word) literal NMA$C_PCCN_HWA = 20007; ! Hardware address (NI address) literal NMA$C_PCCN_DTY = 20100; ! Device type (coded byte of NMA$C_SOFD_) literal NMA$C_PCCN_SFI = 20200; ! Software ID literal NMA$C_PCCN_SPR = 20300; ! System processor (coded word) literal NMA$C_PCCN_DLK = 20400; ! Data link type (coded word) ! literal NMA$C_PCLO_STA = 0; ! State (coded byte of NMA$C_STATE_) literal NMA$C_PCLO_LNA = 100; ! System/name (ascic) literal NMA$C_PCLO_SIN = 200; ! Sink node literal NMA$C_PCLO_EVE = 201; ! Events ! literal NMA$C_PCXA_NOD = 320; ! Node literal NMA$C_PCXA_USR = 330; ! User (ascic) literal NMA$C_PCXA_SPW = 331; ! Password to set (ascic) literal NMA$C_PCXA_RPW = 331; ! Password to read (coded byte of NMA$C_NODPW_) literal NMA$C_PCXA_ACC = 332; ! Account (ascic) literal NMA$C_PCXA_NET = 1110; ! Network (ascic) ! literal NMA$C_PCXA_RSX_ADS = 2310; ! Destination literal NMA$C_PCXA_RSX_ANB = 2320; ! Number literal NMA$C_PCXA_RSX_ASC = 2330; ! Scope ! literal NMA$C_PCXA_SRV_ADS = 3310; ! Destination literal NMA$C_PCXA_SRV_ANB = 3320; ! Number literal NMA$C_PCXA_SRV_ASC = 3330; ! Scope ! literal NMA$C_PCXP_STA = 0; ! State (coded byte of NMA$C_STATE_) literal NMA$C_PCXP_SBS = 1; ! Substate, qualified by DTE (coded byte of NMA$C_XPRSB_) literal NMA$C_PCXP_CTM = 100; ! Counter timer (word) literal NMA$C_PCXP_ACH = 1000; ! Active channels (word) literal NMA$C_PCXP_ASW = 1010; ! Active switched (word) literal NMA$C_PCXP_DTE = 1100; ! DTE (ascic) literal NMA$C_PCXP_GRP = 1101; ! Group (ascic) literal NMA$C_pcxp_netent = 1110; ! Network entity (ascic) literal NMA$C_pcxp_dnt = 1111; ! DTE Network (ascic) literal NMA$C_PCXP_LIN = 1120; ! Line (ascic) literal NMA$C_PCXP_CHN = 1130; ! Channels literal NMA$C_PCXP_MCH = 1131; ! Maximum channels (word) literal NMA$C_PCXP_DBL = 1140; ! Default data (word) literal NMA$C_PCXP_DWI = 1141; ! Default window (byte) literal NMA$C_PCXP_MBL = 1150; ! Maximum data (word) literal NMA$C_PCXP_MWI = 1151; ! Maximum window (byte) literal NMA$C_PCXP_MCL = 1152; ! Maximum clears (byte) literal NMA$C_PCXP_MRS = 1153; ! Maximum resets (byte) literal NMA$C_PCXP_MST = 1154; ! Maximum restarts (byte) literal NMA$C_PCXP_CAT = 1160; ! Call timer (byte) literal NMA$C_PCXP_CLT = 1161; ! Clear timer (byte) literal NMA$C_PCXP_RST = 1162; ! Reset timer (byte) literal NMA$C_PCXP_STT = 1163; ! Restart timer (byte) literal NMA$C_pcxp_itt = 1164; ! Interrupt timer (byte) literal NMA$C_PCXP_GDT = 1170; ! Group DTE (ascic) literal NMA$C_PCXP_GNM = 1171; ! Group number (word) literal NMA$C_PCXP_GTY = 1172; ! Group type (coded byte of NMA$C_XPRTY_) literal NMA$C_pcxp_gnt = 1173; ! Group Network name (ascic) literal nma$c_pcxp_mode = 1180; ! DTE mode (coded byte of NMA$C_X25MD_) literal nma$c_pcxp_prof = 1190; ! Profile (ascic) ! literal NMA$C_PCXP_RSX_PMC = 2300; ! Maximum circuits ! literal NMA$C_PCXP_MCI = 2710; ! Maximum circuits, qualified by DTE ! literal NMA$C_PCXP_SRV_PMC = 3300; ! Maximum circuits ! literal nma$c_pcxs_sta = 1; ! State (coded byte of NMA$C_STATE_) literal NMA$C_PCXS_CTM = 100; ! Counter timer (word) literal NMA$C_PCXS_ACI = 200; ! Active circuits (word) literal NMA$C_PCXS_DST = 300; ! Destination (ascic) literal NMA$C_PCXS_MCI = 310; ! Maximum circuits (word) literal NMA$C_PCXS_NOD = 320; ! Node literal NMA$C_PCXS_USR = 330; ! Username literal NMA$C_PCXS_SPW = 331; ! Password to set (ascic) literal NMA$C_PCXS_RPW = 331; ! Password to read (coded byte of NMA$C_NODPW_) literal NMA$C_PCXS_ACC = 332; ! Account (ascic) literal NMA$C_PCXS_OBJ = 340; ! Object literal NMA$C_PCXS_PRI = 350; ! Priority (byte) literal NMA$C_PCXS_CMK = 351; ! Call mask (byte-counted hex) literal NMA$C_PCXS_CVL = 352; ! Call value (byte-counted hex) literal NMA$C_PCXS_GRP = 353; ! Group (ascic) literal NMA$C_PCXS_SDTE = 354; ! Sending DTE, formally "Number" (ascic) literal NMA$C_PCXS_SAD = 355; ! Subaddresses literal nma$c_pcxs_red = 390; ! Redirect reason (coded byte nma$c_x25red_) literal nma$c_pcxs_cdte = 391; ! Called DTE (ascic) literal nma$c_pcxs_rdte = 392; ! Receiving DTE (ascic) literal nma$c_pcxs_net = 393; ! Network (ascic) literal nma$C_pcxs_emk = 394; ! Extension mask (ascic) literal nma$C_pcxs_evl = 395; ! Extension value (ascic) literal nma$C_pcxs_idte = 396; ! Incoming address (ascii) ! literal NMA$C_PCXS_RSX_5ST = 2310; ! State ! 0, On literal NMA$C_PCXS_FIL = 2710; ! Object filespec (ascic) ! literal NMA$C_PCXS_SRV_5ST = 3310; ! State ! 0, On literal NMA$C_PCXT_STA = 0; ! State (coded byte of NMA$C_STATE_) literal NMA$C_PCXT_BSZ = 100; ! Buffer size (word) literal NMA$C_PCXT_MBK = 101; ! Maximum blocks/file (word) literal NMA$C_PCXT_FNM = 102; ! Filename (ascic) literal NMA$C_PCXT_MBF = 103; ! Maximum number of buffers (word) literal NMA$C_PCXT_CPL = 104; ! Global data capture limit (word) literal NMA$C_PCXT_MVR = 105; ! Maximum trace file version (word) literal NMA$C_PCXT_TPT = 106; ! Trace point name (ascic) literal NMA$C_PCXT_CPS = 110; ! Per-trace capture size (word) literal NMA$C_PCXT_TST = 111; ! Per-trace state (coded byte of NMA$C_STATE_) ! literal NMA$C_PCNO_STA = 0; ! State (coded byte of NMA$C_STATE_) literal NMA$C_PCNO_PHA = 10; ! Physical address (NI address) literal NMA$C_PCNO_IDE = 100; ! Identification (ascic) literal NMA$C_PCNO_MVE = 101; ! Management version (3 bytes) literal NMA$C_PCNO_SLI = 110; ! Service circuit (ascic) literal NMA$C_PCNO_SPA = 111; ! Service password (8 bytes) literal NMA$C_PCNO_SDV = 112; ! Service device (coded byte of NMA$C_SOFD_) literal NMA$C_PCNO_CPU = 113; ! CPU type (coded byte of NMA$C_CPU_) literal NMA$C_PCNO_HWA = 114; ! Hardware address (NI address) literal NMA$C_PCNO_SNV = 115; ! Service node version (coded byte of NMA$C_SVN_) literal NMA$C_PCNO_LOA = 120; ! Load file (ascic) literal NMA$C_PCNO_SLO = 121; ! Secondary loader (ascic) literal NMA$C_PCNO_TLO = 122; ! Tertiary loader (ascic) literal NMA$C_PCNO_DFL = 123; ! Diagnostic file (ascic) literal NMA$C_PCNO_STY = 125; ! Software type (coded byte of NMA$C_SOFT_) literal NMA$C_PCNO_SID = 126; ! Software ID (ascic) literal NMA$C_PCNO_MFL = 127; ! Management File (ascic) literal NMA$C_PCNO_DUM = 130; ! Dump file (ascic) literal NMA$C_PCNO_SDU = 131; ! Secondary dumper (ascic) literal NMA$C_PCNO_DAD = 135; ! Dump address (longword) literal NMA$C_PCNO_DCT = 136; ! Dump count (longword) literal NMA$C_PCNO_OHO = 140; ! Host (read only parameter) literal NMA$C_PCNO_IHO = 141; ! Host (write only parameter) literal NMA$C_PCNO_LPC = 150; ! Loop count (word) literal NMA$C_PCNO_LPL = 151; ! Loop length (word) literal NMA$C_PCNO_LPD = 152; ! Loop Data type (coded byte of NMA$C_LOOP_) literal NMA$C_PCNO_LPA = 153; ! Loop assistant physical address (NI address) literal NMA$C_PCNO_LPH = 154; ! Loop help type (coded byte) literal NMA$C_PCNO_LPN = 155; ! Loop circuit node literal NMA$C_PCNO_LAN = 156; ! Loop circuit assistant node literal NMA$C_PCNO_CTI = 160; ! Counter timer (word) literal NMA$C_PCNO_NNA = 500; ! Name literal NMA$C_PCNO_NLI = 501; ! Circuit (ascic) literal NMA$C_PCNO_ADD = 502; ! Address literal NMA$C_PCNO_ITI = 510; ! Incoming timer (word) literal NMA$C_PCNO_OTI = 511; ! Outgoing timer (word) literal NMA$C_PCNO_IPR = 522; ! Incoming Proxy literal NMA$C_PCNO_OPR = 523; ! Outgoing Proxy literal NMA$C_PCNO_ACL = 600; ! Active links (word) literal NMA$C_PCNO_DEL = 601; ! Delay (word) literal NMA$C_PCNO_NVE = 700; ! Nsp version (3 bytes) literal NMA$C_PCNO_MLK = 710; ! Maximum links (word) literal NMA$C_PCNO_DFA = 720; ! Delay factor (byte) literal NMA$C_PCNO_DWE = 721; ! Delay weight (byte) literal NMA$C_PCNO_IAT = 722; ! Inactivity timer (word) literal NMA$C_PCNO_RFA = 723; ! Retransmit factor (word) literal NMA$C_PCNO_DTY = 810; ! Destination Type (coded byte of NMA$C_XPRTY_) literal NMA$C_PCNO_DCO = 820; ! Destination Cost (word) literal NMA$C_PCNO_DHO = 821; ! Destination Hops (byte) literal NMA$C_PCNO_DLI = 822; ! Destination circuit (ascic) literal NMA$C_PCNO_NND = 830; ! Next node to destination literal NMA$C_PCNO_RVE = 900; ! Routing version (3 bytes) literal NMA$C_PCNO_ETY = 901; ! Executor Type (coded byte of NMA$C_NODTY_) literal NMA$C_PCNO_RTI = 910; ! Routing timer (word) literal NMA$C_PCNO_SAD = 911; ! Subaddress (2 words) literal NMA$C_PCNO_BRT = 912; ! Broadcast routing timer (word) literal NMA$C_PCNO_MAD = 920; ! Maximum address (word) literal NMA$C_PCNO_MLN = 921; ! Maximum circuits (word) literal NMA$C_PCNO_MCO = 922; ! Maximum cost (word) literal NMA$C_PCNO_MHO = 923; ! Maximum hops (byte) literal NMA$C_PCNO_MVI = 924; ! Maximum visits (byte) literal NMA$C_PCNO_MAR = 925; ! Maximum areas (byte) literal NMA$C_PCNO_MBE = 926; ! Maximum broadcast nonrouters (word) literal NMA$C_PCNO_MBR = 927; ! Maximum broadcast routers (word) literal NMA$C_PCNO_AMC = 928; ! Area maximum cost (word) literal NMA$C_PCNO_AMH = 929; ! Area maximum hops (byte) literal NMA$C_PCNO_MBU = 930; ! Maximum buffers (word) literal NMA$C_PCNO_BUS = 931; ! Executor buffer size (word) literal NMA$C_PCNO_SBS = 932; ! Segment buffer size (word) literal NMA$C_PCNO_MPS = 933; ! Maximum path splits literal NMA$C_PCNO_FBS = 933; ! Forwarding buffer size (word) ! literal NMA$C_PCNO_RSX_RPA = 2300; ! Receive password ! 0, Password set literal NMA$C_PCNO_RSX_TPA = 2301; ! Transmit password ! 0, Password set literal NMA$C_PCNO_RSX_VER = 2310; ! Verification state ! 0, On literal NMA$C_PCNO_PUS = 2704; ! Privileged user id literal NMA$C_PCNO_PAC = 2705; ! Privileged account literal NMA$C_PCNO_PPW = 2706; ! Privileged password literal NMA$C_PCNO_NUS = 2712; ! Non-privileged user id literal NMA$C_PCNO_NAC = 2713; ! Non-privileged account literal NMA$C_PCNO_NPW = 2714; ! Non-privileged password literal NMA$C_PCNO_RPA = 2720; ! Receive password literal NMA$C_PCNO_TPA = 2721; ! Transmit password literal NMA$C_PCNO_ACC = 2730; ! Access (coded byte of NMA$C_ACES_) literal NMA$C_PCNO_DAC = 2731; ! Default access (coded byte of NMA$C_ACES_) literal NMA$C_PCNO_PIQ = 2740; ! Pipeline quota (word) literal NMA$C_PCNO_ALI = 2742; ! Alias incoming (coded byte of ALIINC)) literal NMA$C_PCNO_ALM = 2743; ! Alias Maximum links literal NMA$C_PCNO_ALN = 2744; ! Alias node literal NMA$C_PCNO_PRX = 2750; ! Proxy access (coded byte of NMA$C_ACES_) !! Obsolete: Only for LIST/PURGE literal NMA$C_PCNO_DPX = 2751; ! Default proxy access (coded byte of NMA$C_ACES_) literal NMA$C_PCNO_COP = 2760; ! Remote nodefor COPY command literal NMA$C_PCNO_INB = 2765; ! Inbound for async DECnet. literal NMA$C_PCNO_LAA = 2770; ! Load Assist Agent literal NMA$C_PCNO_LAP = 2771; ! Load Assist Parameter literal NMA$C_PCNO_PSP = 2780; ! Path Splits Policy ! (Coded byte f PSPCY) literal NMA$C_PCNO_MDO = 2785; ! Maximum Declared Objects literal NMA$C_PCNO_DNS = 2790; ! DNS interface literal NMA$C_PCNO_IDP = 2791; ! IDP of ISO address literal NMA$C_PCNO_DNM = 2792; ! DNS namespace ! literal NMA$C_PCNO_SRV_RPA = 3300; ! Receive password ! 0, Password set literal NMA$C_PCNO_SRV_TPA = 3301; ! Transmit password ! 0, Password set literal NMA$C_PCNO_SRV_VER = 3310; ! Verification state ! 0, On literal NMA$C_PCNO_SRV_ACB = 3402; ! Active control buffers literal NMA$C_PCNO_SRV_ASB = 3404; ! Active small buffers literal NMA$C_PCNO_SRV_ALB = 3406; ! Active large buffers literal NMA$C_PCNO_SRV_MCB = 3410; ! Maximum control buffers literal NMA$C_PCNO_SRV_MSB = 3420; ! Maximum small buffers literal NMA$C_PCNO_SRV_MLB = 3430; ! Maximum large buffers literal NMA$C_PCNO_SRV_LBS = 3431; ! Large buffer size literal NMA$C_PCNO_SRV_NRB = 3440; ! Minimum receive buffers literal NMA$C_PCNO_SRV_CPT = 3450; ! CEX pool: total bytes literal NMA$C_PCNO_SRV_CPF = 3452; ! CEX pool: number of segments literal NMA$C_PCNO_SRV_CPL = 3454; ! CEX pool: largest segment literal NMA$C_PCNO_SRV_XPT = 3460; ! Extended pool: total bytes literal NMA$C_PCNO_SRV_XPF = 3462; ! Extended pool: number of segments literal NMA$C_PCNO_SRV_XPL = 3464; ! Extended pool: largest segment ! literal NMA$C_PCAR_STA = 0; ! State (coded byte of NMA$C_STATE_) literal NMA$C_PCAR_COS = 820; ! Cost (word) literal NMA$C_PCAR_HOP = 821; ! Hops (byte) literal NMA$C_PCAR_CIR = 822; ! Circuit (ascic) literal NMA$C_PCAR_NND = 830; ! Next node to area ! literal NMA$C_PCOB_OAN = 400; ! Active name literal NMA$C_PCOB_OAC = 410; ! Active links literal NMA$C_PCOB_ONA = 500; ! Name literal NMA$C_PCOB_OCO = 510; ! Copies literal NMA$C_PCOB_OUS = 511; ! User literal NMA$C_PCOB_OVE = 520; ! Verification literal NMA$C_PCOB_NAM = 500; ! Name literal NMA$C_PCOB_NUM = 513; ! Number literal NMA$C_PCOB_FID = 530; ! File id literal NMA$C_PCOB_PID = 535; ! Process id literal NMA$C_PCOB_PRV = 540; ! Privilege list literal NMA$C_PCOB_OCPRV = 542; ! Outgoing connect privilege list literal NMA$C_PCOB_USR = 550; ! User id literal NMA$C_PCOB_ACC = 551; ! Account literal NMA$C_PCOB_PSW = 552; ! Password literal NMA$C_PCOB_PRX = 560; ! Proxy access (coded byte of NMA$C_ACES_) literal NMA$C_PCOB_ALO = 565; ! Alias outgoing- coded byte of nma$c_alout literal NMA$C_PCOB_ALI = 566; ! Alias incoming- coded byte of nma$c_alinc ! literal NMA$C_PCLK_STA = 0; ! State literal NMA$C_PCLK_PID = 101; ! Process id literal NMA$C_PCLK_NID = 102; ! Partner Node literal NMA$C_PCLK_LAD = 105; ! Link address [V2 only] ! entity is node rather than link ! literal NMA$C_PCLK_DLY = 110; ! Round trip delay time (word) literal NMA$C_PCLK_RLN = 120; ! Remote link number (word) literal NMA$C_PCLK_RID = 121; ! Remote identification, PID or username (ascic) literal NMA$C_PCLK_USR = 130; ! Username of link owner (ascic) literal NMA$C_PCLK_PRC = 131; ! Process name of link owner (ascic) ! literal NMA$C_CTCIR_ZER = 0; ! Seconds since last zeroed literal NMA$C_CTCIR_APR = 800; ! Terminating packets received literal NMA$C_CTCIR_DPS = 801; ! Originating packets sent literal NMA$C_CTCIR_ACL = 802; ! Terminating congestion loss literal NMA$C_CTCIR_CRL = 805; ! Corruption loss literal NMA$C_CTCIR_TPR = 810; ! Transit packets received literal NMA$C_CTCIR_TPS = 811; ! Transit packets sent literal NMA$C_CTCIR_TCL = 812; ! Transit congestion loss literal NMA$C_CTCIR_LDN = 820; ! Circuit down literal NMA$C_CTCIR_IFL = 821; ! Initialization failure literal NMA$C_CTCIR_AJD = 822; ! Adjacency down events literal NMA$C_CTCIR_PAJ = 900; ! Peak adjacencies literal NMA$C_CTCIR_BRC = 1000; ! Bytes received literal NMA$C_CTCIR_BSN = 1001; ! Bytes sent literal NMA$C_CTCIR_MBY = 1002; ! Multicast bytes received literal NMA$C_CTCIR_DBR = 1010; ! Data blocks received literal NMA$C_CTCIR_DBS = 1011; ! Data blocks sent literal NMA$C_CTCIR_DEI = 1020; ! Data errors inbound literal NMA$C_CTCIR_DEO = 1021; ! Data errors outbound literal NMA$C_CTCIR_RRT = 1030; ! Remote reply timeouts literal NMA$C_CTCIR_LRT = 1031; ! Local reply timeouts literal NMA$C_CTCIR_RBE = 1040; ! Remote buffer errors literal NMA$C_CTCIR_LBE = 1041; ! Local buffer errors literal NMA$C_CTCIR_SIE = 1050; ! Selection intervals elapsed literal NMA$C_CTCIR_SLT = 1051; ! Selection timeouts literal NMA$C_CTCIR_UBU = 1065; ! NI user buffer unavailable literal NMA$C_CTCIR_RPE = 1100; ! Remote process errors [V2 only] literal NMA$C_CTCIR_LPE = 1101; ! Local process errors [V2 only] literal NMA$C_CTCIR_LIR = 1240; ! Locally initiated resets literal NMA$C_CTCIR_RIR = 1241; ! Remotely initiated resets literal NMA$C_CTCIR_NIR = 1242; ! Network initiated resets ! literal NMA$C_CTCIR_MNE = 2701; ! Multicast received for protocol ! type, but not enabled literal NMA$C_CTCIR_ERI = 2750; ! PCL Errors inbound, bit-mapped ! 0 CRC error on receive literal NMA$C_CTCIR_ERO = 2751; ! PCL Errors outbound, bit-mapped ! 1 CRC on transmit literal NMA$C_CTCIR_RTO = 2752; ! PCL Remote timeouts, bit-mapped ! 0 Receiver busy literal NMA$C_CTCIR_LTO = 2753; ! PCL Local timeouts literal NMA$C_CTCIR_BER = 2754; ! PCL Remote buffer errors literal NMA$C_CTCIR_BEL = 2755; ! PCL Local buffer errors ! literal NMA$C_CTLIN_ZER = 0; ! Seconds since last zeroed literal NMA$C_CTLIN_APR = 800; ! Arriving packets received [V2 only] literal NMA$C_CTLIN_DPS = 801; ! Departing packets sent [V2 only] literal NMA$C_CTLIN_ACL = 802; ! Arriving congestion loss [V2 only] literal NMA$C_CTLIN_TPR = 810; ! Transit packets received [V2 only] literal NMA$C_CTLIN_TPS = 811; ! Transit packets sent [V2 only] literal NMA$C_CTLIN_TCL = 812; ! Transit congestion loss [V2 only] literal NMA$C_CTLIN_LDN = 820; ! Line down [V2 only] literal NMA$C_CTLIN_IFL = 821; ! Initialization failure [V2 only] literal NMA$C_CTLIN_BRC = 1000; ! Bytes received literal NMA$C_CTLIN_BSN = 1001; ! Bytes sent literal NMA$C_CTLIN_MBY = 1002; ! Multicast bytes received literal NMA$C_CTLIN_DBR = 1010; ! Data blocks received literal NMA$C_CTLIN_DBS = 1011; ! Data blocks sent literal NMA$C_CTLIN_MBL = 1012; ! Multicast blocks received literal NMA$C_CTLIN_BID = 1013; ! Blocks sent, initially deferred literal NMA$C_CTLIN_BS1 = 1014; ! Blocks sent, single collision literal NMA$C_CTLIN_BSM = 1015; ! Blocks sent, multiple collisions literal NMA$C_CTLIN_MFC = 1016; ! MAC frame count literal NMA$C_CTLIN_MEC = 1017; ! MAC error count literal NMA$C_CTLIN_MLC = 1018; ! MAC lost count literal NMA$C_CTLIN_DEI = 1020; ! Data errors inbound literal NMA$C_CTLIN_DEO = 1021; ! Data errors outbound literal NMA$C_CTLIN_RRT = 1030; ! Remote reply timeouts literal NMA$C_CTLIN_LRT = 1031; ! Local reply timeouts literal NMA$C_CTLIN_RII = 1032; ! Ring initializations initiated literal NMA$C_CTLIN_RIR = 1033; ! Ring initializations received literal NMA$C_CTLIN_RBI = 1034; ! Ring beacons initiated literal NMA$C_CTLIN_DAT = 1035; ! Duplicate address test failures literal NMA$C_CTLIN_DTD = 1036; ! Duplicate tokens detected literal NMA$C_CTLIN_RPR = 1037; ! Ring purge errors literal NMA$C_CTLIN_FSE = 1038; ! FCI strip errors literal NMA$C_CTLIN_TRI = 1039; ! Traces initiated literal NMA$C_CTLIN_RBE = 1040; ! Remote buffer errors literal NMA$C_CTLIN_LBE = 1041; ! Local buffer errors literal NMA$C_CTLIN_TRR = 1042; ! Traces initiated literal NMA$C_CTLIN_DBC = 1043; ! Directed beacons received literal NMA$C_CTLIN_SIE = 1050; ! Selection intervals elapsed [V2 only] literal NMA$C_CTLIN_SLT = 1051; ! Selection timeouts [V2 only] literal NMA$C_CTLIN_SFL = 1060; ! Send failure literal NMA$C_CTLIN_CDC = 1061; ! Collision detect check failure literal NMA$C_CTLIN_RFL = 1062; ! Receive failure literal NMA$C_CTLIN_UFD = 1063; ! Unrecognized frame destination literal NMA$C_CTLIN_OVR = 1064; ! Data overrun literal NMA$C_CTLIN_SBU = 1065; ! System buffer unavailable literal NMA$C_CTLIN_UBU = 1066; ! User buffer unavailable literal NMA$C_CTLIN_SFR = 1070; ! Send failures (Token Ring) literal NMA$C_CTLIN_RFR = 1071; ! Receive failures (Token Ring) literal NMA$C_CTLIN_IFR = 1072; ! Insertion failures literal NMA$C_CTLIN_RGF = 1073; ! Ring failures literal NMA$C_CTLIN_RPG = 1074; ! Ring purges literal NMA$C_CTLIN_MNC = 1075; ! Monitor contention literal NMA$C_CTLIN_BCN = 1076; ! Beaconing conditions literal NMA$C_CTLIN_LER = 1080; ! Line errors literal NMA$C_CTLIN_IER = 1081; ! Internal errors literal NMA$C_CTLIN_BER = 1082; ! Burst errors literal NMA$C_CTLIN_RAE = 1083; ! Ring poll AC errors literal NMA$C_CTLIN_ADS = 1084; ! Abort delimiters sent literal NMA$C_CTLIN_PIE = 1085; ! Private isolating errors literal NMA$C_CTLIN_TLF = 1086; ! Transmit lost frames literal NMA$C_CTLIN_RCE = 1087; ! Receiver congestion errors literal NMA$C_CTLIN_FCE = 1088; ! Frame copied errors literal NMA$C_CTLIN_FER = 1089; ! Frequency errors (802.5 defined but not implemented) literal NMA$C_CTLIN_TER = 1090; ! Token errors literal NMA$C_CTLIN_PNE = 1091; ! Private non-isolating errors literal NMA$C_CTLIN_RPE = 1100; ! Remote process errors literal NMA$C_CTLIN_LPE = 1101; ! Local process errors literal NMA$C_CTLIN_EBE = 1200; ! Elasticity buffer errors literal NMA$C_CTLIN_LCT = 1201; ! LCT rejects literal NMA$C_CTLIN_LEM = 1202; ! LEM rejects literal NMA$C_CTLIN_LNK = 1203; ! Link errors literal NMA$C_CTLIN_CNC = 1204; ! Connections completed ! literal NMA$S_NMADEF1 = 2; ! Old size name - synonym literal NMA$S_NMA1 = 2; macro NMA$W_NODE = 0,0,16,0 %; macro NMA$V_ADDR = 0,0,10,0 %; literal NMA$S_ADDR = 10; macro NMA$V_AREA = 0,10,6,0 %; literal NMA$S_AREA = 6; ! ! Parameter ID word (DATA ID) ! macro NMA$V_PTY_TYP = 0,0,15,0 %; literal NMA$S_PTY_TYP = 15; ! Type mask ! ! Parameter data type byte (DATA TYPE) ! macro NMA$V_PTY_CLE = 0,0,6,0 %; literal NMA$S_PTY_CLE = 6; ! Coded length mask macro NMA$V_PTY_MUL = 0,6,1,0 %; ! Coded multiple indicator macro NMA$V_PTY_COD = 0,7,1,0 %; ! Coded indicator macro NMA$V_PTY_CMU = 0,6,2,0 %; literal NMA$S_PTY_CMU = 2; ! Coded multiple macro NMA$V_PTY_NLE = 0,0,4,0 %; literal NMA$S_PTY_NLE = 4; ! Number length mask macro NMA$V_PTY_NTY = 0,4,2,0 %; literal NMA$S_PTY_NTY = 2; ! Number type mask macro NMA$V_PTY_ASC = 0,6,1,0 %; ! Ascii image indicator ! NTY values (how to display number): ! Define standard values for the DATA TYPE byte ! ! Parameters for 802 control support ! ! Circuit parameters ! ! RSX-specific circuit parameters ! ! VMS-specific circuit NICE parameters [2700 - 2799] ! ! ! VMS-specific datalink only circuit parameters [2800 - 2899] ! ! (these will never be used in NICE messages). ! ! Server Base specific Circuit parameters ! ! Line parameters ! ! FDDI-specific line parameters ! ! Token Ring specific line parameters ! (Upstream Neighbor Address used by both FDDI and Token Ring) ! ! FDDI-specific line parameters continued ! ! RSX-specific line parameters ! ! 1, Topdown ! VMS-specific line NICE parameters [2700 - 2799] ! ! VMS-specific datalink only line parameters [2800 - 2899] ! ! (these will never be used in NICE messages). ! ! Server Base specific line parameters ! ! Communication Medium parameters ! ! Console module parameters ! ! Loader module parameters ! ! Looper module parameters ! ! Configurator module parameters ! ! Logging parameters ! ! X.25 Access module parameters ! ! RSX-specific X.25-Access module parameters ! ! Server Base specific X.25-Access module parameters ! ! X.25 Protocol module parameters ! ! RSX-specific X.25-Protocol Module parameters ! ! VMS-specific X25-PROTOCOL NICE parameters [2700 - 2799] ! ! Server Base specific X.25-Protocol Module parameters ! ! X.25 server module parameters ! ! RSX-specific X.25-Server Module parameters ! ! 1, Off ! ! VMS-specific X25-SERVER NICE parameters [2700 - 2799] ! ! Server Base specific X.25-Server Module parameters ! ! 1, Off ! ! X.25 trace module parameters (VMS-specific) ! ! Node parameters ! ! RSX-Specific Node (Executor) parameters ! ! 1, Off ! ! VMS-specific node parameters ! ! Server Base specific Node (Executor) parameters ! ! 1, Off ! Area parameters ! ! VMS-specific object parameters ! ! VMS-specific link parameters ! ! CM-1/2, DU-2 (link !), HI-4 (pid) ! Circuit counters ! ! VMS-specific circuit counters ! ! 2 Timeout on word ! 1 Transmitter offline ! 2 Receiver offline ! Line counters ! ! Line counter flags (byte offset will be 0) ! literal NMA$M_CTLIN_BTL = %X'8'; literal NMA$M_CTLIN_FCS = %X'10'; literal NMA$M_CTLIN_TRJ = %X'20'; literal NMA$S_NMADEF2 = 1; ! Old size name - synonym literal NMA$S_NMA2 = 1; macro NMA$V_CTLIN_BTL = 0,3,1,0 %; ! block too long macro NMA$V_CTLIN_FCS = 0,4,1,0 %; ! frame check macro NMA$V_CTLIN_TRJ = 0,5,1,0 %; ! REJ sent literal NMA$M_CTLIN_RRJ = %X'8'; literal NMA$S_NMADEF3 = 1; ! Old size name - synonym literal NMA$S_NMA3 = 1; macro NMA$V_CTLIN_RRJ = 0,3,1,0 %; ! REJ received literal NMA$M_CTLIN_RRN = %X'4'; literal NMA$S_NMADEF4 = 1; ! Old size name - synonym literal NMA$S_NMA4 = 1; macro NMA$V_CTLIN_RRN = 0,2,1,0 %; ! RNR received literal NMA$M_CTLIN_TRN = %X'4'; literal NMA$S_NMADEF5 = 1; ! Old size name - synonym literal NMA$S_NMA5 = 1; macro NMA$V_CTLIN_TRN = 0,2,1,0 %; ! RNR sent literal NMA$M_CTLIN_INR = %X'10'; literal NMA$M_CTLIN_FMS = %X'20'; literal NMA$S_NMADEF6 = 1; ! Old size name - synonym literal NMA$S_NMA6 = 1; macro NMA$V_CTLIN_INR = 0,4,1,0 %; ! invalid N(R) received macro NMA$V_CTLIN_FMS = 0,5,1,0 %; ! FRMR sent literal NMA$M_CTLIN_TUN = %X'4'; literal NMA$M_CTLIN_RUN = %X'10'; literal NMA$M_CTLIN_FMR = %X'20'; literal NMA$C_CTLIN_MBS = 2701; ! Multicast packets transmitted literal NMA$C_CTLIN_MSN = 2702; ! Multicast bytes transmitted literal NMA$C_CTLIN_RME = 2750; ! PCL Remote errors, bit-mapped ! 0 TDM bus busy literal NMA$C_CTLIN_LCE = 2751; ! PCL Local errors, bit-mapped ! 0 Transmitter overrun literal NMA$C_CTLIN_MSE = 2752; ! PCL master/secondary errors, bit-mapped ! 1 Master down literal NMA$C_CTNOD_ZER = 0; ! Seconds since last zeroed literal NMA$C_CTNOD_BRC = 600; ! Bytes received literal NMA$C_CTNOD_BSN = 601; ! Bytes sent literal NMA$C_CTNOD_MRC = 610; ! Messages received literal NMA$C_CTNOD_MSN = 611; ! Messages sent literal NMA$C_CTNOD_CRC = 620; ! Connects received literal NMA$C_CTNOD_CSN = 621; ! Connects sent literal NMA$C_CTNOD_RTO = 630; ! Response timeouts literal NMA$C_CTNOD_RSE = 640; ! Received connect resource errors literal NMA$C_CTNOD_BUN = 650; ! Buffer unavailable literal NMA$C_CTNOD_MLL = 700; ! Maximum logical links active literal NMA$C_CTNOD_APL = 900; ! Aged packet loss literal NMA$C_CTNOD_NUL = 901; ! Node unreachable packet loss literal NMA$C_CTNOD_NOL = 902; ! Node out-of-range packet loss literal NMA$C_CTNOD_OPL = 903; ! Oversized packet loss literal NMA$C_CTNOD_PFE = 910; ! Packet format error literal NMA$C_CTNOD_RUL = 920; ! Partial routing update loss literal NMA$C_CTNOD_VER = 930; ! Verification reject ! literal NMA$C_CTNOD_SRV_SYC = 3310; ! Control buffer failures literal NMA$C_CTNOD_SRV_SYS = 3320; ! Small buffer failures literal NMA$C_CTNOD_SRV_SYL = 3330; ! Large buffer failures literal NMA$C_CTNOD_SRV_SYR = 3340; ! Receive buffer failures ! literal NMA$C_CTXP_ZER = 0; ! Seconds since last zeroed literal NMA$C_CTXP_BRC = 1000; ! Bytes received literal NMA$C_CTXP_BSN = 1001; ! Bytes sent literal NMA$C_CTXP_BLR = 1010; ! Data blocks received literal NMA$C_CTXP_BLS = 1011; ! Data blocks sent literal NMA$C_CTXP_CRC = 1200; ! Calls received literal NMA$C_CTXP_CSN = 1201; ! Calls sent literal NMA$C_CTXP_FSR = 1210; ! Fast selects received literal NMA$C_CTXP_FSS = 1211; ! Fast selects sent literal NMA$C_CTXP_MSA = 1220; ! Maximum switched circuits active literal NMA$C_CTXP_MCA = 1221; ! Maximum channels active literal NMA$C_CTXP_RSE = 1230; ! Received call resource errors literal NMA$C_CTXP_LIR = 1240; ! Locally initiated resets literal NMA$C_CTXP_RIR = 1241; ! Remotely initiated resets literal NMA$C_CTXP_NIR = 1242; ! Network initiated resets literal NMA$C_CTXP_RST = 1250; ! Restarts ! literal NMA$C_CTXS_ZER = 0; ! Seconds since last zeroed literal NMA$C_CTXS_MCA = 200; ! Maximum circuits active literal NMA$C_CTXS_ICR = 210; ! Incoming calls rejected, no resources literal NMA$C_CTXS_LLR = 211; ! Logical links rejected, no resources ! literal NMA$C_LOOP_MIX = 2; ! Mixed literal NMA$C_LOOP_ONE = 1; ! Ones literal NMA$C_LOOP_ZER = 0; ! Zeroes ! literal NMA$C_LOOP_DCNT = 1; ! Default count literal NMA$C_LOOP_DSIZ = 40; ! Default message size ! literal NMA$C_LOOP_XMIT = 0; ! Transmit literal NMA$C_LOOP_RECV = 1; ! Receive literal NMA$C_LOOP_FULL = 2; ! Full (both transmit and receive) ! literal NMA$C_STATE_ON = 0; ! On literal NMA$C_STATE_OFF = 1; ! Off ! literal NMA$C_DNS_ENA = 0; ! Enabled literal NMA$C_DNS_DIS = 1; ! Disabled ! literal NMA$C_STATE_SER = 2; ! Service (circuit/line only) literal NMA$C_STATE_CLE = 3; ! Cleared ! literal NMA$C_STATE_HOL = 2; ! Hold ! literal NMA$C_STATE_SHU = 2; ! Shut literal NMA$C_STATE_RES = 3; ! Restricted literal NMA$C_STATE_REA = 4; ! Reachable literal NMA$C_STATE_UNR = 5; ! Unreachable ! PVM0001+ literal NMA$C_PCNO_DMAD = 1023; ! ! PVM0001- literal NMA$C_ASS_ENA = 0; ! Enabled literal NMA$C_ASS_DIS = 1; ! Disabled ! literal NMA$C_SUR_ENA = 0; ! Enabled literal NMA$C_SUR_DIS = 1; ! Disabled ! literal NMA$C_LINSS_STA = 0; ! Starting literal NMA$C_LINSS_REF = 1; ! Reflecting literal NMA$C_LINSS_LOO = 2; ! Looping literal NMA$C_LINSS_LOA = 3; ! Loading literal NMA$C_LINSS_DUM = 4; ! Dumping literal NMA$C_LINSS_TRI = 5; ! Triggering literal NMA$C_LINSS_ASE = 6; ! Autoservice literal NMA$C_LINSS_ALO = 7; ! Autoloading literal NMA$C_LINSS_ADU = 8; ! Autodumping literal NMA$C_LINSS_ATR = 9; ! Autotriggering literal NMA$C_LINSS_SYN = 10; ! Synchronizing literal NMA$C_LINSS_FAI = 11; ! Failed literal NMA$C_LINSS_RUN = 12; ! Running literal NMA$C_LINSS_UNS = 13; ! Unsyncronised literal NMA$C_LINSS_IDL = 14; ! Idle (PSI-only) ! literal NMA$C_CIRTY_POI = 0; ! DDCMP Point literal NMA$C_CIRTY_CON = 1; ! DDCMP Controller literal NMA$C_CIRTY_TRI = 2; ! DDCMP Tributary literal NMA$C_CIRTY_X25 = 3; ! X25 literal NMA$C_CIRTY_DMC = 4; ! DDCMP DMC compatibility mode (DMP) ! /* CIRTY_LAPB, 5 /* LAPB *** remove once all references have been changed to LAPB *** literal NMA$C_CIRTY_NI = 6; ! NI literal NMA$C_CIRTY_TRNG = 11; ! Token Ring literal NMA$C_CIRTY_FDDI = 12; ! FDDI ! literal NMA$C_LINSV_ENA = 0; ! Enabled literal NMA$C_LINSV_DIS = 1; ! Disabled ! literal NMA$C_CIRPST_AUT = 1; ! Automatic literal NMA$C_CIRPST_ACT = 2; ! Active literal NMA$C_CIRPST_INA = 3; ! Inactive literal NMA$C_CIRPST_DIE = 4; ! Dying literal NMA$C_CIRPST_DED = 5; ! Dead ! literal NMA$C_CIRBLK_ENA = 0; ! Enabled literal NMA$C_CIRBLK_DIS = 1; ! Disabled ! literal NMA$C_CIRUS_PER = 0; ! Permanent literal NMA$C_CIRUS_INC = 1; ! Incoming literal NMA$C_CIRUS_OUT = 2; ! Outgoing ! literal NMA$C_CIRHS_ENA = 0; ! Enabled literal NMA$C_CIRHS_DIS = 1; ! Disabled ! literal NMA$C_CIRBF_UNL = 255; ! Unlimited ! literal NMA$C_CIRVE_ENA = 0; ! Enabled literal NMA$C_CIRVE_DIS = 1; ! Disabled literal NMA$C_CIRVE_INB = 2; ! Inbound ! literal NMA$C_CIRXPT_ZND = 1; ! Z-node literal NMA$C_CIRXPT_PH2 = 2; ! Force Phase II on this circuit literal NMA$C_CIRXPT_PH3 = 3; ! Routing III literal NMA$C_CIRXPT_RO3 = 3; ! Routing III literal NMA$C_CIRXPT_NR4 = 4; ! Nonrouting Phase IV ! literal NMA$C_DPX_FUL = 0; ! Full literal NMA$C_DPX_HAL = 1; ! Half literal NMA$C_DPX_MPT = 4; ! Multipoint ! literal NMA$C_LINCN_NOR = 0; ! Normal literal NMA$C_LINCN_LOO = 1; ! Loop ! literal NMA$C_LINPR_POI = 0; ! DDCMP Point literal NMA$C_LINPR_CON = 1; ! DDCMP Controller literal NMA$C_LINPR_TRI = 2; ! DDCMP Tributary literal NMA$C_LINPR_DMC = 4; ! DDCMP DMC compatibility mode (DMP) literal NMA$C_LINPR_LAPB = 5; ! LAPB literal NMA$C_LINPR_NI = 6; ! NI literal NMA$C_LINPR_BSY = 9; ! BISYNC (not really - just Genbyte) literal NMA$C_LINPR_GENBYTE = 9; ! Genbyte (real name) literal nma$c_linpr_lapbe = 10; ! LAPBE literal nma$c_LINPR_TRNG = 11; ! Token Ring literal nma$c_LINPR_FDDI = 12; ! FDDI literal nma$c_linpr_ea_hdlc = 20; ! Extended addressing HDLC literal nma$c_linpr_sdlc = 21; ! SDLC literal nma$c_linpr_bisync = 22; ! IBM Bisync protocol (not BSY framing) literal nma$c_linpr_swift = 23; ! SWIFT Bisync variant literal nma$c_linpr_chips = 24; ! CHIPS Bisync variant literal nma$m_linpr_mop = 128; ! MOP support ! literal nma$c_code_ascii = 1; ! ASCII character code literal nma$c_code_ebcdic = 2; ! EBCDIC character code ! literal NMA$C_LINPR_MAS = 1; ! Master (controls clock signals) literal NMA$C_LINPR_NEU = 2; ! Neutral (uses master's clock signals) literal NMA$C_LINPR_SEC = 0; ! Secondary (backup for master failure) ! literal NMA$C_LINCL_EXT = 0; ! External literal NMA$C_LINCL_INT = 1; ! Internal ! literal NMA$C_LINFM_802E = 0; ! 802 Extended literal NMA$C_LINFM_ETH = 1; ! Ethernet literal NMA$C_LINFM_802 = 2; ! 802 literal NMA$C_LINFM_SMT = 4; ! SMT (FDDI) literal NMA$C_LINFM_ATM = 6; ! ATM (native) ! literal NMA$C_LINCN_LEN = 0; ! Local Entity Name literal NMA$C_LINCN_NAM = 1; ! Ascii Name ! literal NMA$C_LINSR_USR = 1; ! User supplied literal NMA$C_LINSR_CLI = 2; ! Class I ! literal NMA$C_LINSWI_DIS = 1; ! Switch disabled literal NMA$C_LINSWI_ENA = 0; ! Switch enabled ! literal NMA$C_LINRPE_ON = 1; ! Ring purge on literal NMA$C_LINRPE_OFF = 0; ! Ring purge off ! literal NMA$C_LINATY_HIORD = 0; ! DECnet address literal NMA$C_LINATY_HW = 1; ! Hardware address literal NMA$C_LINATY_USER = 2; ! User supplied address ! literal NMA$C_LINRNG_FOUR = 0; ! 4 Mbps literal NMA$C_LINRNG_SIXTN = 1; ! 16 Mbps ! literal NMA$C_LINETR_ENA = 0; ! Enabled literal NMA$C_LINETR_DIS = 1; ! Disabled ! literal NMA$C_LINSRC_ENA = 0; ! Enabled literal NMA$C_LINSRC_DIS = 1; ! Disabled ! literal NMA$C_MEDIA_STP = 0; ! STP literal NMA$C_MEDIA_UTP = 1; ! UTP literal NMA$C_MEDIA_AUI = 2; ! AUI literal NMA$C_MEDIA_TP = 3; ! TP literal NMA$C_MEDIA_AUTO = 4; ! Auto-sense literal NMA$C_MEDIA_UNSPECIFIED = 5; ! Unspecified literal NMA$C_MEDIA_BNC = 6; ! BNC literal NMA$C_MEDIA_MULTI = 7; ! Fiber - multimode literal NMA$C_MEDIA_SINGLE = 8; ! Fiber - singlemode literal NMA$C_MEDIA_ANY = 65535; ! Any ! literal NMA$C_LINHNG_DIS = 1; ! Hangup disabled literal NMA$C_LINHNG_ENA = 0; ! Hangup enabled ! literal NMA$C_LINRES_DIS = 1; ! Restart disabled literal NMA$C_LINRES_ENA = 0; ! Restart enabled ! literal NMA$C_LINTY_POI = 0; ! DDCMP Point literal NMA$C_LINTY_CON = 1; ! DDCMP Controller literal NMA$C_LINTY_TRI = 2; ! DDCMP Tributary literal NMA$C_LINTY_DMC = 3; ! DDCMP DMC compatibility mode (DMP) ! literal NMA$C_LINMC_SET = 1; ! Set address(es) literal NMA$C_LINMC_CLR = 2; ! Clear address(es) literal NMA$C_LINMC_CAL = 3; ! Clear entire list of multicast addresses literal NMA$C_LINMC_SDF = 4; ! Set physical address to DECnet default ! literal NMA$C_LINDAT_UNK = 0; ! Unknown literal NMA$C_LINDAT_SUC = 1; ! Success literal NMA$C_LINDAT_DUP = 2; ! Duplicate ! literal NMA$C_LINUN_DAT_UNK = 0; ! Unknown literal NMA$C_LINUN_DAT_SUC = 1; ! Success literal NMA$C_LINUN_DAT_DUP = 2; ! Duplicate ! literal NMA$C_LINRPS_OFF = 0; ! Off literal NMA$C_LINRPS_CAN = 1; ! Candidate literal NMA$C_LINRPS_NON = 2; ! Non-purger literal NMA$C_LINRPS_PUR = 3; ! Purger ! literal NMA$C_LINRER_NOE = 0; ! No error literal NMA$C_LINRER_RII = 5; ! Ring init initiated literal NMA$C_LINRER_RIR = 6; ! Ring init received literal NMA$C_LINRER_RBI = 7; ! Ring beaconing initiated literal NMA$C_LINRER_DAD = 8; ! Duplicate address detected literal NMA$C_LINRER_DTD = 9; ! Duplicate token detected literal NMA$C_LINRER_RPE = 10; ! Ring purge error literal NMA$C_LINRER_FSE = 11; ! FCI strip error literal NMA$C_LINRER_ROC = 12; ! Ring OP oscillation literal NMA$C_LINRER_DBR = 13; ! Directed beacon received literal NMA$C_LINRER_PCTI = 14; ! PC trace initiated literal NMA$C_LINRER_PCTR = 15; ! PC trace received ! literal NMA$C_LINNBR_PHY_A = 0; ! A literal NMA$C_LINNBR_PHY_B = 1; ! B literal NMA$C_LINNBR_PHY_S = 2; ! S literal NMA$C_LINNBR_PHY_M = 3; ! M literal NMA$C_LINNBR_PHY_U = 4; ! Unknown ! literal NMA$C_LINRJR_NON = 0; ! None literal NMA$C_LINRJR_LLCT = 1; ! Local LCT literal NMA$C_LINRJR_RLCT = 2; ! Remote LCT literal NMA$C_LINRJR_LCTB = 3; ! LCT both sides literal NMA$C_LINRJR_LEM = 4; ! LEM reject literal NMA$C_LINRJR_TOP = 5; ! Topology error literal NMA$C_LINRJR_NRJ = 6; ! Noise reject literal NMA$C_LINRJR_RRJ = 7; ! Remote reject literal NMA$C_LINRJR_TIP = 8; ! Trace in progress literal NMA$C_LINRJR_TRD = 9; ! Trace received-disabled literal NMA$C_LINRJR_STA = 10; ! Standby literal NMA$C_LINRJR_LCTE = 11; ! LCT protocol error ! literal NMA$C_ACC_SHR = 1; ! Shared access (default protocol user) literal NMA$C_ACC_LIM = 2; ! Limited access (point-to-point conn.) literal NMA$C_ACC_EXC = 3; ! Exclusive access (allow no others) literal NMA$C_ACC_SEL = 4; ! Selective access (source address filtering) ! literal NMA$C_LINMO_AUT = 1; ! Auto address mode literal NMA$C_LINMO_SIL = 2; ! Silo address mode ! literal NMA$C_X25MD_DTE = 1; ! line operates as DTE literal NMA$C_X25MD_DCE = 2; ! line operates as DCE literal NMA$C_X25MD_DTL = 3; ! line is a DTE in loopback literal NMA$C_X25MD_DCL = 4; ! line is a DCE in loopback literal nma$c_x25md_neg = 5; ! line negotiates mode of operation ! literal nma$c_x25red_busy = 0; ! redirected beacuse DTE was Busy literal nma$c_x25red_out_of_order = 1; ! redirected beacuse DTE was out of order literal nma$c_x25red_systematic = 2; ! redirected systematically ! literal NMA$C_NODTY_ROU = 0; ! Routing Phase III literal NMA$C_NODTY_NON = 1; ! Nonrouting Phase III literal NMA$C_NODTY_PHA = 2; ! Phase II literal NMA$C_NODTY_AREA = 3; ! Area literal NMA$C_NODTY_RT4 = 4; ! Routing Phase IV literal NMA$C_NODTY_NR4 = 5; ! Nonrouting Phase IV literal NMA$C_NODTY_AREAP = 6; ! Area Phase IV' literal NMA$C_NODTY_RT4P = 7; ! Routing Phase IV' literal NMA$C_NODTY_NR4P = 8; ! Nonrouting Phase IV' ! literal NMA$C_NODINB_ROUT = 1; ! Router literal NMA$C_NODINB_ENDN = 2; ! Endnode ! literal NMA$C_NODPW_SET = 0; ! Password set ! literal NMA$C_CPU_8 = 0; ! PDP-8 processor literal NMA$C_CPU_11 = 1; ! PDP-11 processor literal NMA$C_CPU_1020 = 2; ! Decsystem 10/20 processor literal NMA$C_CPU_VAX = 3; ! Vax processor ! literal NMA$C_NODSNV_PH3 = 0; ! Phase III literal NMA$C_NODSNV_PH4 = 1; ! Phase IV ! literal NMA$C_SOFT_SECL = 0; ! Secondary loader literal NMA$C_SOFT_TERL = 1; ! Tertiary loader literal NMA$C_SOFT_OSYS = 2; ! Operating system literal NMA$C_SOFT_DIAG = 3; ! Diagnostics ! literal NMA$C_ACES_NONE = 0; ! None literal NMA$C_ACES_INCO = 1; ! Incoming literal NMA$C_ACES_OUTG = 2; ! Outgoing literal NMA$C_ACES_BOTH = 3; ! Both literal NMA$C_ACES_REQU = 4; ! Required ! literal NMA$C_ALIINC_ENA = 0; ! Enabled literal NMA$C_ALIINC_DIS = 1; ! Disabled ! literal NMA$C_ALOUT_ENA = 0; ! Enabled literal NMA$C_ALOUT_DIS = 1; ! Disabled ! literal NMA$C_ALINC_ENA = 0; ! Enabled literal NMA$C_ALINC_DIS = 1; ! Disabled ! literal NMA$C_PRXY_ENA = 0; ! Enabled literal NMA$C_PRXY_DIS = 1; ! Disabled ! literal NMA$C_PSPCY_NOR = 0; ! Normal literal NMA$C_PSPCY_INT = 1; ! Interim ! literal NMA$C_XPRTY_BIL = 1; ! Bilateral ! literal NMA$C_XPRST_ON = 0; ! On literal NMA$C_XPRST_OFF = 1; ! Off literal NMA$C_XPRST_SHU = 2; ! Shut ! literal NMA$C_XPRMN_ENA = 0; ! Enabled literal NMA$C_XPRMN_DIS = 1; ! Disabled ! literal NMA$C_XPRSB_RUN = 12; ! Running literal NMA$C_XPRSB_UNS = 13; ! Unsynchronized literal NMA$C_XPRSB_SYN = 10; ! Synchronizing ! literal NMA$C_Clear_String = 0; ! Clear string value literal NMA$C_Clear_Longword = -1; ! Clear longword value literal NMA$C_CAL_CLR = 0; ! Call clear literal NMA$C_CAL_NOW = 1; ! Call now literal NMA$C_DAY_ALL = 0; literal NMA$C_DAY_MON = 1; literal NMA$C_DAY_TUE = 2; literal NMA$C_DAY_WED = 3; literal NMA$C_DAY_THU = 4; literal NMA$C_DAY_FRI = 5; literal NMA$C_DAY_SAT = 6; literal NMA$C_DAY_SUN = 7; literal NMA$C_TIC_No_Cut = 0; ! Inhibit timecutting literal NMA$C_TIC_Cut = 1; ! Perform Timecutting literal NMA$C_CSG_No_Signal = 0; ! Inhibit call-signal data literal NMA$c_CSG_Signal = 1; ! Send call-signal data literal NMA$c_IRC_DIS = 0; ! Incoming Reverse Disable literal NMA$c_IRC_ENA = 1; ! Incoming Reverse Enable literal NMA$c_ORC_DIS = 0; ! Outgoing Reverse Enable literal NMA$c_ORC_ENA = 1; ! Outgoing Reverse Disable literal NMA$c_RED_DIS = 0; ! Redirect Enable literal NMA$c_RED_ENA = 1; ! Redirect Disable literal NMA$c_MOD_NOAUTO = 0; ! Mode AUTO time-cutting literal NMA$c_MOD_AUTO = 1; ! Mode non-auto time-cutting literal NMA$c_SWC_DIS = 0; ! Enable switched mode literal NMA$c_SWC_ENA = 1; ! Set line for Leased operation literal NMA$c_MDM_OFF = 0; ! Enable modem signals literal NMA$c_MDM_ON = 1; ! Disable modem signals literal NMA$c_DTS_NO_CABLE = 1; ! DTE does not have X21 cable literal NMA$c_DTS_NO_X21_CABLE = 2; ! DTE has none-X21 cable. literal NMA$c_DTS_READY = 3; ! DCE is not ready literal NMA$c_DTS_NOT_READY = 4; ! DTE is signalling Not-Ready to network. literal NMA$c_DTS_ACTIVE = 5; ! DTE in normal working mode. literal NMA$c_DTS_NO_OUTGOING = 6; ! Outgoing calls prohibitedin normal working mode. literal NMA$c_CAS_NONE = 1; ! Call-Status - No call active literal NMA$c_CAS_OUT = 2; ! Outgoing call active literal NMA$c_CAS_IN = 3; ! Incoming call active literal NMA$c_CAS_OUT_R = 4; ! Outgoing reverse active literal NMA$c_CAS_IN_R = 5; ! Incoming reverse active literal NMA$c_DTL_ACCEPT = 1; ! Accept call from literal NMA$c_DTL_REJECT = 2; ! Reject call from literal NMA$C_CAC_MAN = 1; ! X21 controls connect/accept literal NMA$C_CAC_AUTO_CONNECT = 2; ! Driver connects automatically literal NMA$C_CAC_AUTO_ACCEPT = 3; ! Enhanced subaddressing ! literal NMA$C_JAN = 1; literal NMA$C_FEB = 2; literal NMA$C_MAR = 3; literal NMA$C_APR = 4; literal NMA$C_MAY = 5; literal NMA$C_JUN = 6; literal NMA$C_JUL = 7; literal NMA$C_AUG = 8; literal NMA$C_SEP = 9; literal NMA$C_OCT = 10; literal NMA$C_NOV = 11; literal NMA$C_DEC = 12; ! literal NMA$C_SOFD_DP = 0; ! DP11-DA (OBSOLETE) literal NMA$C_SOFD_UNA = 1; ! DEUNA UNIBUS CSMA/CD communication link literal NMA$C_SOFD_DU = 2; ! DU11-DA synchronous line interface literal NMA$C_SOFD_CNA = 3; ! DECNA CSMA/CD communication link literal NMA$C_SOFD_DL = 4; ! DL11-C, -E, or -WA synchronous line interface literal NMA$C_SOFD_QNA = 5; ! DEQNA CSMA/CD communication link literal NMA$C_SOFD_DQ = 6; ! DQ11-DA (OBSOLETE) literal NMA$C_SOFD_CI = 7; ! Computer Interconnect Interface literal NMA$C_SOFD_DA = 8; ! DA11-B or -AL UNIBUS link literal NMA$C_SOFD_PCL = 9; ! PCL11-B multiple CPU link literal NMA$C_SOFD_DUP = 10; ! DUP11-DA synchronous line interface literal NMA$C_SOFD_LUA = 11; ! DELUA CSMA/CD communication link literal NMA$C_SOFD_DMC = 12; ! DMC11-DA/AR, -FA/AR, -MA/AL or -MD/AL interprocessor link literal NMA$C_SOFD_LNA = 13; ! MicroServer Lance CSMA/CD communication link literal NMA$C_SOFD_DN = 14; ! DN11-BA or -AA automatic calling unit literal NMA$C_SOFD_DLV = 16; ! DLV11-E, -F, -J, MXV11-A or -B asynchronous line literal NMA$C_SOFD_LCS = 17; ! Lance/Decserver 100 CSMA/CD communication link literal NMA$C_SOFD_DMP = 18; ! DMP11 multipoint interprocessor link literal NMA$C_SOFD_AMB = 19; ! AMBER (OBSOLETE) literal NMA$C_SOFD_DTE = 20; ! DTE20 PDP-11 to KL10 interface literal NMA$C_SOFD_DBT = 21; ! DEBET CSMA/CD communication link literal NMA$C_SOFD_DV = 22; ! DV11-AA/BA synchronous line multiplexer literal NMA$C_SOFD_BNA = 23; ! DEBNA BI CSMA/CD communication link literal NMA$C_SOFD_BNT = 23; ! DEBNT **obsolete** literal NMA$C_SOFD_DZ = 24; ! DZ11-A, -B, -C, -D asynchronous line multiplexer literal NMA$C_SOFD_LPC = 25; ! LANCE/PCXX CSMA/CD communication link literal NMA$C_SOFD_DSV = 26; ! DSV11 Q-bus synchronous link literal NMA$C_SOFD_CEC = 27; ! 3-COM/IBM-PC CSMA/CD communication link literal NMA$C_SOFD_KDP = 28; ! KMC11/DUP11-DA synchronous line multiplexer literal NMA$C_SOFD_IEC = 29; ! Interlan/IBM-PC CSMA/CD communication link literal NMA$C_SOFD_KDZ = 30; ! KMC11/DZ11-A, -B, -C, or -D asynchronous line multiplexer literal NMA$C_SOFD_UEC = 31; ! Univation/RAINBOW-100 CSMA/CD communication link literal NMA$C_SOFD_KL8 = 32; ! KL8-J (OBSOLETE) literal NMA$C_SOFD_DS2 = 33; ! LANCE/DECserver 200 CSMA/CD communication link literal NMA$C_SOFD_DMV = 34; ! DMV11 interprocessor link literal NMA$C_SOFD_DS5 = 35; ! DECserver 500 CSMA/CD communication link literal NMA$C_SOFD_DPV = 36; ! DPV11 synchronous line interface literal NMA$C_SOFD_LQA = 37; ! DELQA CSMA/CD communication link literal NMA$C_SOFD_DMF = 38; ! DMF32 synchronous line unit literal NMA$C_SOFD_SVA = 39; ! DESVA CSMA/CD communication link literal NMA$C_SOFD_DMR = 40; ! DMR11-AA, -AB, -AC, or -AE interprocessor link literal NMA$C_SOFD_MUX = 41; ! MUXserver 100 CSMA/CD communication link literal NMA$C_SOFD_KMY = 42; ! KMS11-PX synchronous line interface with X.25 Level 2 microcode literal NMA$C_SOFD_DEP = 43; ! DEPCA PCSG/IBM-PC CSMA/CD communication link literal NMA$C_SOFD_KMX = 44; ! KMS11-BD/BE synchronous line interface with X.25 Level 2 microcode literal NMA$C_SOFD_LTM = 45; ! LTM (911) Ethernet monitor literal NMA$C_SOFD_DMB = 46; ! DMB-32 BI synchronous line multiplexer literal NMA$C_SOFD_DES = 47; ! DESNC Ethernet Encryption Module literal NMA$C_SOFD_KCP = 48; ! KCP synchronous/asynchronous line literal NMA$C_SOFD_MX3 = 49; ! MUXServer 300 CSMA/CD communication link literal NMA$C_SOFD_SYN = 50; ! MicroServer synchronous line interface literal NMA$C_SOFD_MEB = 51; ! DEMEB multiport bridge CSMA/CD communication link literal NMA$C_SOFD_DSB = 52; ! DSB32 BI synchronous line interface literal NMA$C_SOFD_BAM = 53; ! DEBAM LANBridge-200 Data Link literal NMA$C_SOFD_DST = 54; ! DST-32 TEAMmate synchronous line interface (DEC423) literal NMA$C_SOFD_FAT = 55; ! DEFAT DataKit Server CSMA/CD communication link literal NMA$C_SOFD_RSM = 56; ! DERSM - Remote Segment Monitor literal NMA$C_SOFD_RES = 57; ! DERES - Remote Environmental Sensor literal NMA$C_SOFD_3C2 = 58; ! 3COM Etherlink II (part number 3C503) literal NMA$C_SOFD_3CM = 59; ! 3COM Etherlink/MC (part number 3C523) literal NMA$C_SOFD_DS3 = 60; ! DECServer 300 CSMA/CD communication link literal NMA$C_SOFD_MF2 = 61; ! Mayfair-2 CSMA/CD communication link literal NMA$C_SOFD_MMR = 62; ! DEMMR Ethernet Multiport Manageable Repeater literal NMA$C_SOFD_VIT = 63; ! Vitalink TransLAN III/IV (NP3A) Bridge literal NMA$C_SOFD_VT5 = 64; ! Vitalink TransLAN 350 (NPC25) Bridge literal NMA$C_SOFD_BNI = 65; ! DEBNI BI CSMA/CD communication link literal NMA$C_SOFD_MNA = 66; ! DEMNA XMI CSMA/CD communication link literal NMA$C_SOFD_PMX = 67; ! PMAX (KN01) CSMA/CD communication link literal NMA$C_SOFD_NI5 = 68; ! Interlan NI5210-8 CSMA/CD comm link for IBM PC XT/AT literal NMA$C_SOFD_NI9 = 69; ! Interlan NI9210 CSMA/CD comm link for IBM PS/2 literal NMA$C_SOFD_KMK = 70; ! KMS11-K DataKit UNIBUS adapter literal NMA$C_SOFD_3CP = 71; ! Etherlink Plus (part number 3C505) literal NMA$C_SOFD_DP2 = 72; ! DPNserver-200 CSMA/CD communication link literal NMA$C_SOFD_ISA = 73; ! SGEC CSMA/CD communication link literal NMA$C_SOFD_DIV = 74; ! DIV-32 DEC WAN controller-100 literal NMA$C_SOFD_QTA = 75; ! DEQTA CSMA/CD communication link literal NMA$C_SOFD_B15 = 76; ! LANbridge-150 CSMA/CD communication link literal NMA$C_SOFD_WD8 = 77; ! WD8003 Family CSMA/CD communication link literal NMA$C_SOFD_ILA = 78; ! BICC ISOLAN 4110-2 PC/AT CSMA/CD communication link literal NMA$C_SOFD_ILM = 79; ! BICC ISOLAN 4110-3 PC MicroChannel CSMA/CD comm link literal NMA$C_SOFD_APR = 80; ! Apricot Xen-S and Qi CSMA/CD adapter literal NMA$C_SOFD_ASN = 81; ! AST EtherNode CSMA/CD communication link literal NMA$C_SOFD_ASE = 82; ! AST Ethernet CSMA/CD communication link literal NMA$C_SOFD_TRW = 83; ! TRW HC-2001 CSMA/CD communication link literal NMA$C_SOFD_EDX = 84; ! Ethernet-XT/AT CSMA/CD communication link literal NMA$C_SOFD_EDA = 85; ! Ethernet-AT CSMA/CD communication link literal NMA$C_SOFD_DR2 = 86; ! DECrouter-250 CSMA/CD communication link literal NMA$C_SOFD_SCC = 87; ! DECrouter-250 DUSCC serial comm link (DDCMP or HDLC) literal NMA$C_SOFD_DCA = 88; ! DCA Series 300 Net Processor CSMA/CD communication link literal NMA$C_SOFD_TIA = 89; ! LANcard/E CSMA/CD controllers literal NMA$C_SOFD_FBN = 90; ! DEFEB DECbridge-500 CSMA/CD communication link literal NMA$C_SOFD_FEB = 91; ! DEFEB DECbridge-500 FDDI communication link literal NMA$C_SOFD_FCN = 92; ! DEFCN DECconcentrator-500 wiring concentrator FDDI comm link literal NMA$C_SOFD_MFA = 93; ! DEMFA FDDI communication link literal NMA$C_SOFD_MXE = 94; ! MIPS workstation family CSMA/CD communication links literal NMA$C_SOFD_CED = 95; ! Cabletron Ethernet Desktop Network Interface CSMA/CD comm link literal NMA$C_SOFD_C20 = 96; ! 3Com CS/200 terminal server CSMA/CD comm link literal NMA$C_SOFD_CS1 = 97; ! 3Com CS/1 terminal server CSMA/CD comm link literal NMA$C_SOFD_C2M = 98; ! 3Com CS/210, CS/2000, CS/2100 terminal server CSMA/CD comm link literal NMA$C_SOFD_ACA = 99; ! ACA/32000 system CSMA/CD comm link literal NMA$C_SOFD_GSM = 100; ! Gandalf StarMaster CSMA/CD comm link literal NMA$C_SOFD_DSF = 101; ! DSF32 2 line sync comm link for Cirrus literal NMA$C_SOFD_CS5 = 102; ! 3Com CS/50 terminal server CSMA/CD comm link literal NMA$C_SOFD_XIR = 103; ! XIRCOM PE10B2 CSMA/CD comm link literal NMA$C_SOFD_KFE = 104; ! KFE52 CSMA/CD comm link for Cirrus literal NMA$C_SOFD_RT3 = 105; ! rtVAX-300 SGEC-based CSMA/CD comm link literal NMA$C_SOFD_SPI = 106; ! Spiderport M250 terminal server CSMA/CD comm link literal NMA$C_SOFD_FOR = 107; ! LAT gateway CSMA/CD comm link literal NMA$C_SOFD_MER = 108; ! Meridian CSMA/CD comm link drivers literal NMA$C_SOFD_PER = 109; ! Persoft CSMA/CD comm link drivers literal NMA$C_SOFD_STR = 110; ! AT&T StarLan-10 twisted pair comm link literal NMA$C_SOFD_MPS = 111; ! MIPSfair SGEC CSMA/CD comm link literal NMA$C_SOFD_L20 = 112; ! LPS20 print server CSMA/CD comm link literal NMA$C_SOFD_VT2 = 113; ! Vitalink TransLAN 320 Bridge literal NMA$C_SOFD_DWT = 114; ! VT-1000 DECwindows terminal literal NMA$C_SOFD_WGB = 115; ! DEWGB Work Group Bridge CSMA/CD comm link literal NMA$C_SOFD_ZEN = 116; ! Zenith Z-LAN4000 XT, AT and MicroChannel Z-LAN comm link literal NMA$C_SOFD_TSS = 117; ! Thursby Software Systems CSMA/CD comm link drivers literal NMA$C_SOFD_MNE = 118; ! 3MIN (KN02-BA) integral CSMA/CD comm link literal NMA$C_SOFD_FZA = 119; ! DEFZA TurboChannel FDDI comm link literal NMA$C_SOFD_90L = 120; ! DS90L terminal server CSMA/CD comm link literal NMA$C_SOFD_CIS = 121; ! Cisco Systems terminal servers CSMA/CD comm link literal NMA$C_SOFD_STC = 122; ! STRTC terminal servers literal NMA$C_SOFD_UBE = 123; ! Ungermann-Bass PC2030, PC3030 CSMA/CD comm link literal NMA$C_SOFD_DW2 = 124; ! DECwindows terminal II CSMA/CD comm link literal NMA$C_SOFD_FUE = 125; ! Fujitsu Etherstar MB86950 CSMA/CD comm link literal NMA$C_SOFD_M38 = 126; ! MUXServer 380 CSMA/CD comm link literal NMA$C_SOFD_NTI = 127; ! NTI Group PC Ethernet Card CSMA/CD comm link literal NMA$C_SOFD_RAD = 130; ! RADLINX LAN Gateway CSMA/CD comm link literal NMA$C_SOFD_INF = 131; ! Infotron Commix series terminal server CSMA/CD comm link literal NMA$C_SOFD_XMX = 132; ! Xyplex MAXserver series terminal server CSMA/CD comm link literal NMA$C_SOFD_NDI = 133; ! NDIS data link driver for MS/DOS systems CSMA/CD comm link literal NMA$C_SOFD_ND2 = 134; ! NDIS data link driver for OS/2 systems CSMA/CD comm link literal NMA$C_SOFD_TRN = 135; ! DEC LANcontroller 520 Token Ring comm link literal NMA$C_SOFD_DEV = 136; ! Develcon Electronics Ltd. LAT gateway CSMA/CD comm link literal NMA$C_SOFD_ACE = 137; ! Acer 5220, 5270 adapter CSMA/CD comm link literal NMA$C_SOFD_PNT = 138; ! ProNet-4/18 #1390 802.5 comm link literal NMA$C_SOFD_ISE = 139; ! Network Integration Server 600 CSMA/CD line card literal NMA$C_SOFD_IST = 140; ! Network Integration Server 600 T1 sync line card literal NMA$C_SOFD_ISH = 141; ! Network Integration Server 64 kb HDLC line card literal NMA$C_SOFD_ISF = 142; ! Network Integration Server 600 FDDI line card literal NMA$C_SOFD_DSW = 149; ! DSW-21 single line serial comm link literal NMA$C_SOFD_DW4 = 150; ! DSW-41/42 single/dual line serial comm link literal NMA$C_SOFD_ITC = 154; ! DEC 4000 TGEC CSMA/CD adapter literal NMA$C_SOFD_FTA = 160; ! DEFTA FDDI adapter literal NMA$C_SOFD_FAA = 161; ! Futurebus FDDI literal NMA$C_SOFD_FEA = 162; ! EISAbus FDDI literal NMA$C_SOFD_FQA = 169; ! DEFQA Q-bus FDDI adapter literal NMA$C_SOFD_A35 = 170; ! DEC 3000-400/500 CSMA/CD adapter literal NMA$C_SOFD_V49 = 172; ! VAXstation 4000-90 CSMA/CD adapter literal NMA$C_SOFD_TRA = 175; ! DETRA-AA Turbochannel 802.5 token ring comm link literal NMA$C_SOFD_TRB = 176; ! DETRA-BA Turbochannel token ring adapter literal NMA$C_SOFD_ERA = 182; ! DE422 EISA-bus PC CSMA/CD comm link literal NMA$C_SOFD_A33 = 188; ! DEC 3000-300 CSMA/CD adapter literal NMA$C_SOFD_TRE = 189; ! DW300 EISA Token Ring literal NMA$C_SOFD_ETA = 202; ! TULIP EISA bus CSMA/CD adapter literal NMA$C_SOFD_EWA = 203; ! TULIP PCI bus CSMA/CD adapter literal NMA$C_SOFD_FWA = 204; ! FOCUS PCI bus FDDI adapter (no such product) literal NMA$C_SOFD_EIA = 204; ! 8255X PCI bus Ethernet adapter literal NMA$C_SOFD_AZA = 213; ! OTTO Turbochannel ATM adapter literal NMA$C_SOFD_FPA = 216; ! DEFPA PCI bus FDDI adapter literal NMA$C_SOFD_GPA = 217; ! DEGPA PCI bus Gigabit Ethernet adapter literal NMA$C_SOFD_GP3 = 250; ! Broadcom 5700, 5701, 5703 PCI/PCI-X bus Gigabit Ethernet adapter literal NMA$C_SOFD_EIG = 251; ! Intel 82540 Gigabit Ethernet adapter literal NMA$C_SOFD_LLA = 252; ! Logical LAN literal NMA$C_SOFD_TRP = 253; ! TC4048 PCI TR adapter literal NMA$C_SOFD_ELA = 254; ! Emulated LAN over ATM literal NMA$C_SOFD_EBA = 255; ! Shared Memory LAN ! literal NMA$_SUCCESS = 1; ! Unqualified success literal NMA$_SUCCFLDRPL = 9; ! Success with field replaced literal NMA$_BADFID = 0; ! Invalid field id code literal NMA$_BADDAT = 8; ! Invalid data format literal NMA$_BADOPR = 16; ! Invalid operation literal NMA$_BUFTOOSMALL = 24; ! Buffer too small literal NMA$_FLDNOTFND = 32; ! Field not found ! literal NMA$C_OPN_MIN = 0; ! Minimum ! literal NMA$C_OPN_NODE = 0; ! Nodes literal NMA$C_OPN_LINE = 1; ! Lines literal NMA$C_OPN_LOG = 2; ! Logging literal NMA$C_OPN_OBJ = 3; ! Object literal NMA$C_OPN_CIR = 4; ! Circuit literal NMA$C_OPN_X25 = 5; ! Module X25 literal NMA$C_OPN_X29 = 6; ! Module X29 literal NMA$C_OPN_CNF = 7; ! Module Configurator literal NMA$C_OPN_MAX = 7; ! Maximum ! permanent database files literal NMA$C_OPN_ALL = 127; ! All opened files ! literal NMA$C_OPN_AC_RO = 0; ! Read Only literal NMA$C_OPN_AC_RW = 1; ! Read write ! literal NMA$C_FN2_DLL = 2; ! Down line load literal NMA$C_FN2_ULD = 3; ! Upline Dump literal NMA$C_FN2_TRI = 4; ! Trigger remote bootstrap literal NMA$C_FN2_LOO = 5; ! Loop back test literal NMA$C_FN2_TES = 6; ! Send test message to be looped literal NMA$C_FN2_SET = 7; ! Set parameter literal NMA$C_FN2_REA = 8; ! Read Parameter literal NMA$C_FN2_ZER = 9; ! Zero counters literal NMA$C_FN2_LNS = 14; ! Line service ! literal NMA$C_OP2_CHNST = 5; ! Node operational status literal NMA$C_OP2_CHLST = 8; ! Line operational status ! literal NMA$C_OP2_RENCT = 0; ! Local node counters literal NMA$C_OP2_RENST = 1; ! local node status literal NMA$C_OP2_RELCT = 4; ! Line counters literal NMA$C_OP2_RELST = 5; ! Line status ! literal NMA$C_OP2_ZENCT = 0; ! Local Node counters literal NMA$C_OP2_ZELCT = 2; ! Line counters ! literal NMA$C_EN2_KNO = 0; ! Known lines literal NMA$C_EN2_LID = 1; ! Line id literal NMA$C_EN2_LCN = 2; ! Line convenience name ! literal NMA$C_STS_SUC = 1; ! Success literal NMA$C_STS_MOR = 2; ! Request accepted, more to come literal NMA$C_STS_PAR = 3; ! Partial reply ! literal NMA$C_STS_DON = -128; ! Done ! literal NMA$C_STS_FUN = -1; ! Unrecognized function or option literal NMA$C_STS_INV = -2; ! Invalid message format literal NMA$C_STS_PRI = -3; ! Privilege violation literal NMA$C_STS_SIZ = -4; ! Oversized management command message literal NMA$C_STS_MPR = -5; ! Network management program error literal NMA$C_STS_PTY = -6; ! Unrecognized parameter type literal NMA$C_STS_MVE = -7; ! Incompatible management version literal NMA$C_STS_CMP = -8; ! Unrecognised component literal NMA$C_STS_IDE = -9; ! Invalid identification format literal NMA$C_STS_LCO = -10; ! Line communication error literal NMA$C_STS_STA = -11; ! Component in wrong state literal NMA$C_STS_FOP = -13; ! File open error literal NMA$C_STS_FCO = -14; ! Invalid file contents literal NMA$C_STS_RES = -15; ! Resource error literal NMA$C_STS_PVA = -16; ! Invalid parameter value literal NMA$C_STS_LPR = -17; ! Line protocol error literal NMA$C_STS_FIO = -18; ! File i/o error literal NMA$C_STS_MLD = -19; ! Mirror link disconnected literal NMA$C_STS_ROO = -20; ! No room for new entry literal NMA$C_STS_MCF = -21; ! Mirror connect failed literal NMA$C_STS_PNA = -22; ! Parameter not applicable literal NMA$C_STS_PLO = -23; ! Parameter value too long literal NMA$C_STS_HAR = -24; ! Hardware failure literal NMA$C_STS_OPE = -25; ! Operation failure literal NMA$C_STS_SYS = -26; ! System-specific management ! function not supported literal NMA$C_STS_PGP = -27; ! Invalid parameter grouping literal NMA$C_STS_BLR = -28; ! Bad loopback response literal NMA$C_STS_PMS = -29; ! Parameter missing ! literal NMA$C_STS_ALI = -127; ! Invalid alias identification literal NMA$C_STS_OBJ = -126; ! Invalid object identification literal NMA$C_STS_PRO = -125; ! Invalid process identification literal NMA$C_STS_LNK = -124; ! Invalid link identification ! literal NMA$C_FOPDTL_PDB = 0; ! Permanent database literal NMA$C_FOPDTL_LFL = 1; ! Load file literal NMA$C_FOPDTL_DFL = 2; ! Dump file literal NMA$C_FOPDTL_SLF = 3; ! Secondary loader literal NMA$C_FOPDTL_TLF = 4; ! Tertiary loader literal NMA$C_FOPDTL_SDF = 5; ! Secondary dumper literal NMA$C_FOPDTL_PDR = 6; ! Permanent Database,on remote node literal NMA$C_FOPDTL_MFL = 7; ! Management file ! literal NMA$C_NCEDTL_NNA = 0; ! No node name set literal NMA$C_NCEDTL_INN = 1; ! Invalid node name format literal NMA$C_NCEDTL_UNA = 2; ! Unrecognised node name literal NMA$C_NCEDTL_UNR = 3; ! Node unreachable literal NMA$C_NCEDTL_RSC = 4; ! Network resources literal NMA$C_NCEDTL_RJC = 5; ! Rejected by object literal NMA$C_NCEDTL_ONA = 6; ! Invalid object name format literal NMA$C_NCEDTL_OBJ = 7; ! Unrecognised object literal NMA$C_NCEDTL_ACC = 8; ! Access control rejected literal NMA$C_NCEDTL_BSY = 9; ! Object too busy literal NMA$C_NCEDTL_NRS = 10; ! No response from object literal NMA$C_NCEDTL_NSD = 11; ! Node shut down literal NMA$C_NCEDTL_DIE = 12; ! Node or object failed literal NMA$C_NCEDTL_DIS = 13; ! Disconnect by object literal NMA$C_NCEDTL_ABO = 14; ! Abort by object literal NMA$C_NCEDTL_ABM = 15; ! Abort by management ! literal NMA$C_OPEDTL_DCH = 0; ! Data check literal NMA$C_OPEDTL_TIM = 1; ! Timeout literal NMA$C_OPEDTL_ORN = 2; ! Data overrun literal NMA$C_OPEDTL_ACT = 3; ! Unit is active literal NMA$C_OPEDTL_BAF = 4; ! Buffer allocation failure literal NMA$C_OPEDTL_RUN = 5; ! Protocol running literal NMA$C_OPEDTL_DSC = 6; ! Line disconnected literal NMA$C_OPEDTL_FTL = 8; ! Fatal hardware error literal NMA$C_OPEDTL_MNT = 11; ! DDCMP maintainance message received literal NMA$C_OPEDTL_LST = 12; ! Data lost due to buffer size mismatch literal NMA$C_OPEDTL_THR = 13; ! Threshold error literal NMA$C_OPEDTL_TRB = 14; ! Tributary malfunction literal NMA$C_OPEDTL_STA = 15; ! DDCMP start message received literal NMA$S_NMADEF7 = 1; ! Old size name - synonym literal NMA$S_NMA7 = 1; macro NMA$V_CTLIN_TUN = 0,2,1,0 %; ! transmit underrun macro NMA$V_CTLIN_RUN = 0,4,1,0 %; ! receive underrun macro NMA$V_CTLIN_FMR = 0,5,1,0 %; ! FRMR received ! ! VMS-specific line counters ! ! 1 Message rejected ! 2 Message truncated ! 3 Receiver offline ! 4 Receiver busy ! 5 Transmitter offline ! 1 CRC error on transmit ! 2 CRC error on receive ! 3 Timeouts ! 4 Non-existant memory transmit ! 5 Non-existant memory receive ! 6 Buffer to small ! 7 Failed to open channel ! 8 Memory overflow ! 2 Now master ! ! Node counters ! ! Server Base Specific Executor Node Counters ! ! X.25 Protocol module counters ! ! X.25 Server module counters ! ! Coded parameter values ! ! ! Loop test block type coded values ! ! Default values for loop functions ! ! Values for LOOP HELP ! ! State coded values ! ! DNS interface ! ! circuit/line/process specific state values ! ! logging specific state values ! ! node specific state values ! ! ! Default value for EXECUTOR MAXIMUM ADDRESS. ! Note: DNA Network Management does not specify a default. ! This is defined for VMS only, for compatibility with ! previous releases that used a hard coded value in ! [NETACP.SRC]NETCONFIG.MAR. ! ! ! ! Looper/loader assistance coded values ! ! Configurator surveillance coded values ! ! Circuit/Line substate coded values ! ! Circuit type coded values [In V2, line type coded values] ! ! Circuit/Line Service ! ! Circuit polling state ! ! Circuit blocking values ! ! Circuit usage values ! ! Circuit parameter, Handshake Required ! ! Circuit maximum receive buffers ! ! Circuit verification [VMS only] ! ! Circuit (desired) transport type [VMS only] ! ! Line duplex coded values ! ! Line controller mode ! ! Line protocol values (same as CIRTY_) ! ! Character encoding ! ! Line protocol values for the PCL-11B ! ! Line clock values ! ! Line packet format types. Note that only the Ethernet format is ! allowed to be odd. All other format values must be even. ! ! Line client name types. ! ! Line services ! ! Line Switch states ! ! Ring purger enable states (FDDI) ! ! Address type (Token Ring) ! ! Ring speed (Token Ring) ! ! Early token release (Token Ring) ! ! Source routing (Token Ring) ! ! Line Media (LAN) ! ! Line Hangup state ! ! Line Restart state ! ! Line type coded values [V2 only] ! ! Line multicast address function code [VMS datalink only]. ! Destination and physical address function codes too [VMS datalink only]. ! ! Duplicate address flag states (FDDI) ! ! Upstream neighbor DA flag states (FDDI) ! ! Ring purger states (FDDI) ! ! Ring error reason states (FDDI) ! ! Neighbor PHY type states (FDDI) ! ! Reject reason states (FDDI) ! ! NI line protocol access mode [VMS datalink only] ! ! PCL-11B address mode ! ! X.25 line mode ! ! X.25 server redirect reason ! ! Node type values ! ! Node inbound states ! ! Node password values ! ! Node CPU type codes ! ! Service node version coded values ! ! Node software type code ! ! Node access (and default access) codes ! ! Executor Alias incoming values ! ! Object alias outgoing ! ! Object alias incoming ! ! Executor Proxy ! ! Path Split Policy ! ! X.25 Protocol type values ! ! X.25 protocol state values ! ! X.25 protocol multi-network support flag ! ! X.25 protocol DTE substate values ! ! X21 literals ! ! Months of the Year Codes ! ! Service device codes (MOP) ! ! Status codes for field support routines ! ! Permanent database file ID codes ! ! Open access codes ! ! Define Phase II NICE function codes ! ! Change parameters (volatile only) ! ! Read Information (Status and Counters only) ! ! Zero counters ! ! Line entity codes ! ! NML Return codes ! ! Error details ! ! ! STS_FOP and STS_FIO ! ! STS_MLD, STS_MCF ! ! STS_OPE ! !*** MODULE $NMBDEF *** ! + ! ! FORMAT OF THE FILE NAME BLOCK. THE FILE NAME BLOCK IS USED AS AN INTERNAL ! INTERFACE TO THE DIRECTORY SCAN ROUTINE, AND IS ALSO THE FORMAT OF A ! DIRECTORY RECORD. ! ! - literal NMB$K_DIRENTRY = 16; ! LENGTH OF DIRECTORY ENTRY literal NMB$C_DIRENTRY = 16; ! LENGTH OF DIRECTORY ENTRY literal NMB$M_ALLVER = %X'8'; literal NMB$M_ALLTYP = %X'10'; literal NMB$M_ALLNAM = %X'20'; literal NMB$M_WILD = %X'100'; literal NMB$M_NEWVER = %X'200'; literal NMB$M_SUPERSEDE = %X'400'; literal NMB$M_FINDFID = %X'800'; literal NMB$M_LOWVER = %X'4000'; literal NMB$M_HIGHVER = %X'8000'; literal NMB$K_LENGTH = 40; ! LENGTH OF NAME BLOCK literal NMB$C_LENGTH = 40; ! LENGTH OF NAME BLOCK literal NMB$S_NMBDEF = 40; literal NMB$S_NMB = 40; macro NMB$W_FID = 0,0,0,0 %; literal NMB$S_FID = 6; ! FILE ID macro NMB$W_FID_NUM = 0,0,16,0 %; ! FID - FILE NUMBER macro NMB$W_FID_SEQ = 2,0,16,0 %; ! FID - FILE SEQUENCE NUMBER macro NMB$W_FID_RVN = 4,0,16,0 %; ! FID - RELATIVE VOLUME NUMBER macro NMB$W_NAME = 6,0,0,0 %; literal NMB$S_NAME = 6; ! FILE NAME (RAD-50) macro NMB$W_TYPE = 12,0,16,0 %; ! FILE TYPE (RAD-50) macro NMB$W_VERSION = 14,0,16,1 %; ! VERSION NUMBER macro NMB$W_FLAGS = 16,0,16,0 %; ! NAME STATUS FLAGS macro NMB$V_ALLVER = 16,3,1,0 %; ! MATCH ALL VERSIONS macro NMB$V_ALLTYP = 16,4,1,0 %; ! MATCH ALL TYPES macro NMB$V_ALLNAM = 16,5,1,0 %; ! MATCH ALL NAMES macro NMB$V_WILD = 16,8,1,0 %; ! WILD CARDS IN FILE NAME macro NMB$V_NEWVER = 16,9,1,0 %; ! MAXIMIZE VERSION NUMBER macro NMB$V_SUPERSEDE = 16,10,1,0 %; ! SUPERSEDE EXISTING FILE macro NMB$V_FINDFID = 16,11,1,0 %; ! SEARCH FOR FILE ID macro NMB$V_LOWVER = 16,14,1,0 %; ! LOWER VERSION OF FILE EXISTS macro NMB$V_HIGHVER = 16,15,1,0 %; ! HIGHER VERSION OF FILE EXISTS macro NMB$B_ASCNAMSIZ = 18,0,8,0 %; macro NMB$T_ASCNAMTXT = 19,0,0,0 %; literal NMB$S_ASCNAMTXT = 19; macro NMB$W_CONTEXT = 38,0,16,0 %; ! START POINT FOR NEXT FIND !*** MODULE $NSAARGDEF *** ! + ! Security Auditing argument list definitions ! - ! + ! Argument list header offset definitions ! - literal NSA$M_ARG_FLAG_ALARM = %X'1'; literal NSA$M_ARG_FLAG_JOURN = %X'2'; literal NSA$M_ARG_FLAG_MANDY = %X'4'; literal NSA$C_ARGHDR_LENGTH = 12; literal NSA$K_ARGHDR_LENGTH = 12; literal NSA$S_NSAARGHDRDEF = 12; ! Old size name - synonym literal NSA$S_NSAARGHDR = 12; macro NSA$L_ARG_COUNT = 0,0,32,0 %; ! Argument list count macro NSA$L_ARG_ID = 4,0,32,0 %; ! Record identification longword macro NSA$W_ARG_TYPE = 4,0,16,0 %; ! Record type macro NSA$W_ARG_SUBTYPE = 6,0,16,0 %; ! Record subtype macro NSA$B_ARG_FLAG = 8,0,8,0 %; ! Flags byte macro NSA$V_ARG_FLAG_ALARM = 8,0,1,0 %; ! Generate alarm for this record macro NSA$V_ARG_FLAG_JOURN = 8,1,1,0 %; ! Journal this record macro NSA$V_ARG_FLAG_MANDY = 8,2,1,0 %; ! Mandatory auditing macro NSA$B_ARG_PKTNUM = 9,0,8,0 %; ! Number of packets macro NSA$T_ARG_SPARE = 10,0,16,0 %; literal NSA$S_ARG_SPARE = 2; ! Spare bytes macro NSA$T_ARG_LIST = 12,0,0,0 %; ! + ! Data packet argument passing mechanism definitions ! - literal NSA$K_ARG_MECH_BYTE = 0; ! Byte value literal NSA$K_ARG_MECH_WORD = 1; ! Word value literal NSA$K_ARG_MECH_LONG = 2; ! Longword value literal NSA$K_ARG_MECH_QUAD = 3; ! Quadword value literal NSA$K_ARG_MECH_DESCR = 4; ! Descriptor literal NSA$K_ARG_MECH_ADESCR = 5; ! Address of descriptor literal NSA$K_ARG_MECHNUM = 6; ! + ! Argument list definitions ! - ! File access literal NSA$C_ARG1_LENGTH = 52; literal NSA$K_ARG1_LENGTH = 52; literal NSA$S_NSAARG1DEF = 52; ! Old size name - synonym literal NSA$S_NSAARG1 = 52; macro NSA$L_ARG1_FACMOD_TM = 12,0,32,0 %; ! FACMOD type and mechanism macro NSA$L_ARG1_FACMOD = 16,0,32,0 %; ! File access mode macro NSA$L_ARG1_FILNAM_TM = 20,0,32,0 %; ! FILNAM type and mechanism macro NSA$L_ARG1_FILNAM_SIZ = 24,0,32,0 %; ! File name size macro NSA$L_ARG1_FILNAM_PTR = 28,0,32,0 %; ! File name address macro NSA$L_ARG1_IMGNAM_TM = 32,0,32,0 %; ! IMGNAM type and mechanism macro NSA$Q_ARG1_IMGNAM = 36,0,0,0 %; literal NSA$S_ARG1_IMGNAM = 8; ! Image name macro NSA$L_ARG1_PRIVUSED_TM = 44,0,32,0 %; ! PRIVUSED type and mechanism macro NSA$L_ARG1_PRIVUSED = 48,0,32,0 %; ! Privileges used for access ! Volume mount literal NSA$C_ARG2_LENGTH = 96; literal NSA$K_ARG2_LENGTH = 96; literal NSA$S_NSAARG2DEF = 96; ! Old size name - synonym literal NSA$S_NSAARG2 = 96; macro NSA$L_ARG2_UIC_TM = 12,0,32,0 %; ! UIC type and mechanism macro NSA$L_ARG2_UIC = 16,0,32,0 %; ! Volume UIC macro NSA$L_ARG2_VOLPRO_TM = 20,0,32,0 %; ! VOLPRO type and mechanism macro NSA$L_ARG2_VOLPRO = 24,0,32,0 %; ! Volume protection macro NSA$L_ARG2_MOUFLG_TM = 28,0,32,0 %; ! MOUFLG type and mechanism macro NSA$L_ARG2_MOUFLG = 32,0,32,0 %; ! Mount flags macro NSA$L_ARG2_IMGNAM_TM = 36,0,32,0 %; ! IMGNAM type and mechanism macro NSA$Q_ARG2_IMGNAM = 40,0,0,0 %; literal NSA$S_ARG2_IMGNAM = 8; ! Image name macro NSA$L_ARG2_DEVNAM_TM = 48,0,32,0 %; ! DEVNAM type and mechanism macro NSA$L_ARG2_DEVNAM_SIZ = 52,0,32,0 %; ! Device name size macro NSA$L_ARG2_DEVNAM_PTR = 56,0,32,0 %; ! Device name address macro NSA$L_ARG2_LOGNAM_TM = 60,0,32,0 %; ! LOGNAM type and mechanism macro NSA$L_ARG2_LOGNAM_SIZ = 64,0,32,0 %; ! Logical name size macro NSA$L_ARG2_LOGNAM_PTR = 68,0,32,0 %; ! Logical name address macro NSA$L_ARG2_VOLNAM_TM = 72,0,32,0 %; ! VOLNAM type and mechanism macro NSA$L_ARG2_VOLNAM_SIZ = 76,0,32,0 %; ! Volume name size macro NSA$L_ARG2_VOLNAM_PTR = 80,0,32,0 %; ! Volume name address macro NSA$L_ARG2_VOLSNAM_TM = 84,0,32,0 %; ! VOLSNAM type and mechanism macro NSA$L_ARG2_VOLSNAM_SIZ = 88,0,32,0 %; ! Volume set name size macro NSA$L_ARG2_VOLSNAM_PTR = 92,0,32,0 %; ! Volume set name address ! Volume dismount literal NSA$C_ARG3_LENGTH = 80; literal NSA$K_ARG3_LENGTH = 80; literal NSA$S_NSAARG3DEF = 80; ! Old size name - synonym literal NSA$S_NSAARG3 = 80; macro NSA$L_ARG3_DMOUFLG_TM = 12,0,32,0 %; ! DMOUFLG type and mechanism macro NSA$L_ARG3_DMOUFLG = 16,0,32,0 %; ! Dismount flags macro NSA$L_ARG3_IMGNAM_TM = 20,0,32,0 %; ! IMGNAM type and mechanism macro NSA$Q_ARG3_IMGNAM = 24,0,0,0 %; literal NSA$S_ARG3_IMGNAM = 8; ! Image name macro NSA$L_ARG3_DEVNAM_TM = 32,0,32,0 %; ! DEVNAM type and mechanism macro NSA$L_ARG3_DEVNAM_SIZ = 36,0,32,0 %; ! Device name size macro NSA$L_ARG3_DEVNAM_PTR = 40,0,32,0 %; ! Device name address macro NSA$L_ARG3_LOGNAM_TM = 44,0,32,0 %; ! LOGNAM type and mechanism macro NSA$L_ARG3_LOGNAM_SIZ = 48,0,32,0 %; ! Logical name size macro NSA$L_ARG3_LOGNAM_PTR = 52,0,32,0 %; ! Logical name address macro NSA$L_ARG3_VOLNAM_TM = 56,0,32,0 %; ! VOLNAM type and mechanism macro NSA$L_ARG3_VOLNAM_SIZ = 60,0,32,0 %; ! Volume name size macro NSA$L_ARG3_VOLNAM_PTR = 64,0,32,0 %; ! Volume name address macro NSA$L_ARG3_VOLSNAM_TM = 68,0,32,0 %; ! VOLSNAM type and mechanism macro NSA$L_ARG3_VOLSNAM_SIZ = 72,0,32,0 %; ! Volume set name size macro NSA$L_ARG3_VOLSNAM_PTR = 76,0,32,0 %; ! Volume set name address ! Global section access literal NSA$C_ARG4_LENGTH = 64; literal NSA$K_ARG4_LENGTH = 64; literal NSA$S_NSAARG4DEF = 64; ! Old size name - synonym literal NSA$S_NSAARG4 = 64; macro NSA$L_ARG4_FACMOD_TM = 12,0,32,0 %; ! FACMOD type and mechanism macro NSA$L_ARG4_FACMOD = 16,0,32,0 %; ! File access mode macro NSA$L_ARG4_FILNAM_TM = 20,0,32,0 %; ! FILNAM type and mechanism macro NSA$L_ARG4_FILNAM_SIZ = 24,0,32,0 %; ! File name size macro NSA$L_ARG4_FILNAM_PTR = 28,0,32,0 %; ! File name address macro NSA$L_ARG4_IMGNAM_TM = 32,0,32,0 %; ! IMGNAM type and mechanism macro NSA$Q_ARG4_IMGNAM = 36,0,0,0 %; literal NSA$S_ARG4_IMGNAM = 8; ! Image name macro NSA$L_ARG4_SECNAM_TM = 44,0,32,0 %; ! SECNAM type and mechanism macro NSA$L_ARG4_SECNAM_SIZ = 48,0,32,0 %; ! File name size macro NSA$L_ARG4_SECNAM_PTR = 52,0,32,0 %; ! File name address macro NSA$L_ARG4_PRIVUSED_TM = 56,0,32,0 %; ! PRIVUSED type and mechanism macro NSA$L_ARG4_PRIVUSED = 60,0,32,0 %; ! Privileges used for access !*** MODULE $NSABDEF *** ! ! Define the layout of the Non-discretionary Security Audit Block. ! ! The NSAB is the structure which is passed to the internal auditing entry ! point (NSA$AUDIT_EVENT) and contains a list of audit packets along with ! a couple of flags. ! literal NSAB$M_NONPAGED = %X'1'; literal NSAB$M_NUKENSAB = %X'2'; literal NSAB$C_HDR_LENGTH = 72; literal NSAB$K_HDR_LENGTH = 72; literal NSAB$S_NSABDEF = 72; literal NSAB$S_NSAB = 72; macro NSAB$L_FLINK = 0,0,32,1 %; ! FLINK macro NSAB$L_BLINK = 4,0,32,1 %; ! BLINK macro NSAB$W_SIZE = 8,0,16,0 %; ! size of NSAB buffer macro NSAB$B_TYPE = 10,0,8,0 %; ! type of structure (DYN$C_NSAB) macro NSAB$B_SUBTYPE = 11,0,8,0 %; ! subtype field (not used) ! incarnations macro NSAB$L_FLAGS = 16,0,32,0 %; ! miscellaneous flags macro NSAB$V_NONPAGED = 16,0,1,0 %; ! message entry is non-paged pool macro NSAB$V_NUKENSAB = 16,1,1,0 %; ! force NSAB deallocation macro NSAB$L_SUPPLIED = 20,0,32,0 %; ! supplied packet mask macro NSAB$L_BASEADDR = 24,0,32,1 %; ! address of NSAB to deallocate macro NSAB$L_AUDIT_BLOCK = 28,0,32,1 %; ! address of audit buffer macro NSAB$B_ACB = 32,0,0,0 %; literal NSAB$S_ACB = 36; ! ACB used to wake audit server macro NSAB$L_SENDER_EPID = 68,0,32,0 %; ! sender's EPID !*** MODULE $NSAEVTDEF *** ! + ! Non-Discretionary Security Auditing event definitions. This macro defines ! the bits which are used to enable alarm and audit events for each class of ! system security relevant event. This definition also defines the format of ! the mandatory process auditing event vectors. ! - literal NSA$S_NSAAXPDEF = 40; ! Old size name - synonym literal NSA$S_NSAAXP = 40; macro NSA$L_EVT_FAILURE = 8,0,32,0 %; ! Access failures event mask macro NSA$L_EVT_SUCCESS = 12,0,32,0 %; ! Successful access event mask macro NSA$L_EVT_SYSPRV = 16,0,32,0 %; ! Success due to SYSPRV event mask macro NSA$L_EVT_BYPASS = 20,0,32,0 %; ! Success due to BYPASS event mask macro NSA$L_EVT_UPGRADE = 24,0,32,0 %; ! Success due to UPGRADE event mask macro NSA$L_EVT_DOWNGRADE = 28,0,32,0 %; ! Success due to DOWNGRADE event mask macro NSA$L_EVT_GRPPRV = 32,0,32,0 %; ! Success due to GRPPRV event mask macro NSA$L_EVT_READALL = 36,0,32,0 %; ! Success due to READALL event mask literal NSA$K_NUM_OBJECT_ACCESS = 8; ! number of privileged access arrays literal NSA$M_EVT_CREATION = %X'1'; literal NSA$M_EVT_DEACCESS = %X'2'; literal NSA$M_EVT_DELETION = %X'4'; literal NSA$K_NUM_ACC_OTHER = 3; ! number of "other" bits literal NSA$K_ACCESS_LENGTH = 36; ! size of object access event mask literal NSA$S_NSAACCDEF = 36; ! Old size name - synonym literal NSA$S_NSAACC = 36; macro NSA$L_ACC_FAILURE = 0,0,32,0 %; ! Access failures event mask macro NSA$L_ACC_SUCCESS = 4,0,32,0 %; ! Successful access event mask macro NSA$L_ACC_SYSPRV = 8,0,32,0 %; ! Success due to SYSPRV event mask macro NSA$L_ACC_BYPASS = 12,0,32,0 %; ! Success due to BYPASS event mask macro NSA$L_ACC_UPGRADE = 16,0,32,0 %; ! Success due to UPGRADE event mask macro NSA$L_ACC_DOWNGRADE = 20,0,32,0 %; ! Success due to DOWNGRADE event mask macro NSA$L_ACC_GRPPRV = 24,0,32,0 %; ! Success due to GRPPRV event mask macro NSA$L_ACC_READALL = 28,0,32,0 %; ! Success due to READALL event mask macro NSA$L_ACC_OTHER = 32,0,32,0 %; ! other object-specific events macro NSA$V_EVT_CREATION = 32,0,1,0 %; ! object creation macro NSA$V_EVT_DEACCESS = 32,1,1,0 %; ! object deaccess macro NSA$V_EVT_DELETION = 32,2,1,0 %; ! object delete (devices) literal NSA$M_EVT_ACL = %X'1'; literal NSA$M_EVT_MOUNT = %X'2'; literal NSA$M_EVT_UAF = %X'4'; literal NSA$M_EVT_INSTAL = %X'8'; literal NSA$M_EVT_AUDIT = %X'10'; literal NSA$M_EVT_CUSTOMER = %X'20'; literal NSA$M_EVT_CSS = %X'40'; literal NSA$M_EVT_LP = %X'80'; literal NSA$M_EVT_SYSTIME = %X'100'; literal NSA$M_EVT_SYSGEN = %X'200'; literal NSA$M_EVT_IDENTIFIER = %X'400'; literal NSA$M_EVT_CONNECTION = %X'800'; literal NSA$M_EVT_NCP = %X'1000'; literal NSA$M_EVT_AUTHENTICATION = %X'2000'; literal NSA$K_NUM_SYS_EVENTS = 14; ! number of system event types literal NSA$K_NUM_LOGIN_EVENTS = 4; ! number of login event types literal NSA$K_NUM_PRIV_EVENTS = 2; ! number of priv audit event types literal NSA$M_PRC_CREPRC = %X'1'; literal NSA$M_PRC_DELPRC = %X'2'; literal NSA$M_PRC_SCHDWK = %X'4'; literal NSA$M_PRC_CANWAK = %X'8'; literal NSA$M_PRC_WAKE = %X'10'; literal NSA$M_PRC_SUSPND = %X'20'; literal NSA$M_PRC_RESUME = %X'40'; literal NSA$M_PRC_GRANTID = %X'80'; literal NSA$M_PRC_REVOKID = %X'100'; literal NSA$M_PRC_GETJPI = %X'200'; literal NSA$M_PRC_FORCEX = %X'400'; literal NSA$M_PRC_SIGPRC = %X'800'; literal NSA$M_PRC_SETPRI = %X'1000'; literal NSA$M_PRC_PRCTERM = %X'2000'; literal NSA$M_PRC_CPU_CAPABILITIES = %X'4000'; literal NSA$M_PRC_PROCESS_CAPABILITIES = %X'8000'; literal NSA$M_PRC_PROCESS_AFFINITY = %X'10000'; literal NSA$M_PRC_SET_IMPLICIT_AFFINITY = %X'20000'; literal NSA$K_NUM_PROCESS_EVENTS = 18; ! number of process control bits literal NSA$M_EVT_ILLFORMED = %X'1'; literal NSA$K_NUM_AUDIT_EVENTS = 1; ! number of audit event types literal NSA$M_PSB_CREATE = %X'1'; literal NSA$M_PSB_DELETE = %X'2'; literal NSA$M_PSB_MODIFY = %X'4'; literal NSA$K_NUM_PERSONA_EVENTS = 3; ! number of persona control bits literal NSA$C_EVT_LENGTH = 40; ! size of alarm or audit event mask literal NSA$K_EVT_LENGTH = 40; ! size of alarm or audit event mask literal NSA$S_NSAEVTDEF = 40; ! Old size name - synonym literal NSA$S_NSAEVT = 40; macro NSA$L_EVT_SYS = 0,0,32,0 %; ! miscellaneous system event mask macro NSA$V_EVT_ACL = 0,0,1,0 %; ! ACL requested alarms and audits macro NSA$V_EVT_MOUNT = 0,1,1,0 %; ! MOUNT and DISMOUNT requests ! modifications made to the system macro NSA$V_EVT_UAF = 0,2,1,0 %; ! or network authorization files macro NSA$V_EVT_INSTAL = 0,3,1,0 %; ! INSTALL operations macro NSA$V_EVT_AUDIT = 0,4,1,0 %; ! SET AUDIT operations (obsolete) macro NSA$V_EVT_CUSTOMER = 0,5,1,0 %; ! Customer events macro NSA$V_EVT_CSS = 0,6,1,0 %; ! CSS events macro NSA$V_EVT_LP = 0,7,1,0 %; ! LP events macro NSA$V_EVT_SYSTIME = 0,8,1,0 %; ! System time modification macro NSA$V_EVT_SYSGEN = 0,9,1,0 %; ! SYSGEN parameter modification macro NSA$V_EVT_IDENTIFIER = 0,10,1,0 %; ! Identifier auditing (as privilege) macro NSA$V_EVT_CONNECTION = 0,11,1,0 %; ! Connection auditing macro NSA$V_EVT_NCP = 0,12,1,0 %; ! NCP command line auditing macro NSA$V_EVT_AUTHENTICATION = 0,13,1,0 %; ! DAS auditing macro NSA$B_EVT_LOGB = 4,0,8,0 %; ! breakin detection event mask macro NSA$B_EVT_LOGI = 5,0,8,0 %; ! login event mask macro NSA$B_EVT_LOGF = 6,0,8,0 %; ! login failure event mask macro NSA$B_EVT_LOGO = 7,0,8,0 %; ! logout event mask macro NSA$Q_PRVAUD_SUCCESS = 8,0,0,0 %; literal NSA$S_PRVAUD_SUCCESS = 8; ! successfull privilege audit mask macro NSA$Q_PRVAUD_FAILURE = 16,0,0,0 %; literal NSA$S_PRVAUD_FAILURE = 8; ! successfull privilege audit mask macro NSA$L_EVT_PROCESS = 24,0,32,0 %; ! process control auditing macro NSA$V_PRC_CREPRC = 24,0,1,0 %; ! Create process macro NSA$V_PRC_DELPRC = 24,1,1,0 %; ! Delete process macro NSA$V_PRC_SCHDWK = 24,2,1,0 %; ! Schedule process wakeup macro NSA$V_PRC_CANWAK = 24,3,1,0 %; ! Cancel process wakeup macro NSA$V_PRC_WAKE = 24,4,1,0 %; ! Wake process macro NSA$V_PRC_SUSPND = 24,5,1,0 %; ! Suspend process macro NSA$V_PRC_RESUME = 24,6,1,0 %; ! Resume process macro NSA$V_PRC_GRANTID = 24,7,1,0 %; ! Grant identifier macro NSA$V_PRC_REVOKID = 24,8,1,0 %; ! Revoke identifier macro NSA$V_PRC_GETJPI = 24,9,1,0 %; ! Get job or process information macro NSA$V_PRC_FORCEX = 24,10,1,0 %; ! Force image exit macro NSA$V_PRC_SIGPRC = 24,11,1,0 %; ! Signal process (undocumented) macro NSA$V_PRC_SETPRI = 24,12,1,0 %; ! Set process priority macro NSA$V_PRC_PRCTERM = 24,13,1,0 %; ! Detect process termination (undocumented) macro NSA$V_PRC_CPU_CAPABILITIES = 24,14,1,0 %; ! Change in CPU capability macro NSA$V_PRC_PROCESS_CAPABILITIES = 24,15,1,0 %; ! Change in process capability macro NSA$V_PRC_PROCESS_AFFINITY = 24,16,1,0 %; ! Change in process affinity macro NSA$V_PRC_SET_IMPLICIT_AFFINITY = 24,17,1,0 %; ! Change in implicit affinity macro NSA$L_EVT_AUDIT = 28,0,32,0 %; ! miscellaneous audit event mask macro NSA$V_EVT_ILLFORMED = 28,0,1,0 %; ! Ill-formed TCB audit macro NSA$L_EVT_PERSONA = 32,0,32,0 %; ! persona auditing macro NSA$V_PSB_CREATE = 32,0,1,0 %; ! Create persona macro NSA$V_PSB_DELETE = 32,1,1,0 %; ! Delete persona macro NSA$V_PSB_MODIFY = 32,2,1,0 %; ! Modify persona literal NSA$M_EVT_LOG_BAT = %X'1'; literal NSA$M_EVT_LOG_DIA = %X'2'; literal NSA$M_EVT_LOG_LOC = %X'4'; literal NSA$M_EVT_LOG_REM = %X'8'; literal NSA$M_EVT_LOG_NET = %X'10'; literal NSA$M_EVT_LOG_SUB = %X'20'; literal NSA$M_EVT_LOG_DET = %X'40'; literal NSA$M_EVT_LOG_SRV = %X'80'; literal NSA$K_NUM_JOB_TYPES = 8; ! number of job types literal NSA$S_NSAEVTLOGBITS = 1; macro NSA$V_EVT_LOG_BAT = 0,0,1,0 %; ! batch macro NSA$V_EVT_LOG_DIA = 0,1,1,0 %; ! dialup macro NSA$V_EVT_LOG_LOC = 0,2,1,0 %; ! local macro NSA$V_EVT_LOG_REM = 0,3,1,0 %; ! remote macro NSA$V_EVT_LOG_NET = 0,4,1,0 %; ! network macro NSA$V_EVT_LOG_SUB = 0,5,1,0 %; ! subprocess macro NSA$V_EVT_LOG_DET = 0,6,1,0 %; ! detached process macro NSA$V_EVT_LOG_SRV = 0,7,1,0 %; ! server thread literal NSA$C_OLD_EVT_LENGTH = 40; literal NSA$K_OLD_EVT_LENGTH = 40; literal NSA$S_NSAOLDEVTDEF = 40; ! Old size name - synonym literal NSA$S_NSAOLDEVT = 40; ! **************************************************************************** ! The following file access masks must be contiguous and in the current order ! **************************************************************************** macro NSA$L_OLD_EVT_FAILURE = 8,0,32,0 %; ! Access failures event mask macro NSA$L_OLD_EVT_SUCCESS = 12,0,32,0 %; ! Successful access event mask macro NSA$L_OLD_EVT_SYSPRV = 16,0,32,0 %; ! Success due to SYSPRV event mask macro NSA$L_OLD_EVT_BYPASS = 20,0,32,0 %; ! Success due to BYPASS event mask macro NSA$L_OLD_EVT_UPGRADE = 24,0,32,0 %; ! Success due to UPGRADE event mask macro NSA$L_OLD_EVT_DOWNGRADE = 28,0,32,0 %; ! Success due to DOWNGRADE event mask macro NSA$L_OLD_EVT_GRPPRV = 32,0,32,0 %; ! Success due to GRPPRV event mask macro NSA$L_OLD_EVT_READALL = 36,0,32,0 %; ! Success due to READALL event mask ! **************************************************************************** ! End of file access masks ! **************************************************************************** literal NSA$S_ALARM_NAME = 32; ! maximum length of an alarm name literal NSA$S_AUDIT_NAME = 65; ! maximum length of an audit name literal NSA$S_IMAGE_NAME = 1022; ! maximum size of an image name (XQP) literal NSA$S_JOURNAL_NAME = 65; ! maximum length of alarm or audit name literal NSA$K_MAX_JOURNALS = 1; ! maximum number of alarm or audit journals literal NSA$S_MSGFILNAM = 32; ! maximum size of message file name literal NSA$K_SCRATCH_PAGES = 10; ! number of scratch P1 pages (NSA$A_SCRATCH) literal NSA$K_SCRATCH_LENGTH = 5120; ! byte length of P1 scratch space literal NSA$S_NSACONDEF = 4; ! Old size name - synonym literal NSA$S_NSACON = 4; literal NSA$S_SYSUAF_FIELDS = 8; macro NSA$Q_SYSUAF_FIELDS = 0,0,0,0 %; ! SYSUAF flags: macro NSA$V_SYSUAF_ACCESS = 0,0,1,0 %; ! ACCESS modified (obsolete) macro NSA$V_SYSUAF_ACCOUNT = 0,1,1,0 %; ! ACCOUNT modified macro NSA$V_SYSUAF_ASTLM = 0,2,1,0 %; ! ASTLM modified macro NSA$V_SYSUAF_BATCH = 0,3,1,0 %; ! BATCH modified macro NSA$V_SYSUAF_BIOLM = 0,4,1,0 %; ! BIOLM modified macro NSA$V_SYSUAF_BYTLM = 0,5,1,0 %; ! BYTLM modified macro NSA$V_SYSUAF_CLI = 0,6,1,0 %; ! CLI modified macro NSA$V_SYSUAF_CLITABLES = 0,7,1,0 %; ! CLITABLES modified macro NSA$V_SYSUAF_CPUTIME = 0,8,1,0 %; ! CPUTIME modified macro NSA$V_SYSUAF_DEFPRIVILEGES = 0,9,1,0 %; ! DEFPRIVILEGES modified macro NSA$V_SYSUAF_DEVICE = 0,10,1,0 %; ! DEVICE modified macro NSA$V_SYSUAF_DIALUP = 0,11,1,0 %; ! DIALUP modified macro NSA$V_SYSUAF_DIOLM = 0,12,1,0 %; ! DIOLM modified macro NSA$V_SYSUAF_DIRECTORY = 0,13,1,0 %; ! DIRECTORY modified macro NSA$V_SYSUAF_ENQLM = 0,14,1,0 %; ! ENQLM modified macro NSA$V_SYSUAF_EXPIRATION = 0,15,1,0 %; ! EXPIRATION modified macro NSA$V_SYSUAF_FILLM = 0,16,1,0 %; ! FILLM modified macro NSA$V_SYSUAF_FLAGS = 0,17,1,0 %; ! FLAGS modified macro NSA$V_SYSUAF_INTERACTIVE = 0,18,1,0 %; ! INTERACTIVE modified (obsolete) macro NSA$V_SYSUAF_JTQUOTA = 0,19,1,0 %; ! JTQUOTA modified macro NSA$V_SYSUAF_LGICMD = 0,20,1,0 %; ! LGICMD modified macro NSA$V_SYSUAF_LOCAL = 0,21,1,0 %; ! LOCAL modified macro NSA$V_SYSUAF_MAXDETACH = 0,22,1,0 %; ! MAXDETACH modified macro NSA$V_SYSUAF_MAXJOBS = 0,23,1,0 %; ! MAXJOBS modified macro NSA$V_SYSUAF_MAXACCTJOBS = 0,24,1,0 %; ! MAXACCTJOBS modified macro NSA$V_SYSUAF_NETWORK = 0,25,1,0 %; ! NETWORK modified macro NSA$V_SYSUAF_OWNER = 0,26,1,0 %; ! OWNER modified macro NSA$V_SYSUAF_PASSWORD = 0,27,1,0 %; ! PASSWORD modified macro NSA$V_SYSUAF_PBYTLM = 0,28,1,0 %; ! PBYTLM modified macro NSA$V_SYSUAF_PFLAGS = 0,29,1,0 %; ! PFLAGS modified (obsolete) macro NSA$V_SYSUAF_P_RESTRICT = 0,30,1,0 %; ! P_RESTRICT modified (obsolete) macro NSA$V_SYSUAF_PGFLQUOTA = 0,31,1,0 %; ! PGFLQUOTA modified macro NSA$V_SYSUAF_PRCLM = 4,0,1,0 %; ! PRCLM modified macro NSA$V_SYSUAF_PRIMEDAYS = 4,1,1,0 %; ! PRIMEDAYS modified macro NSA$V_SYSUAF_PRIORITY = 4,2,1,0 %; ! PRIORITY modified macro NSA$V_SYSUAF_PRIVILEGES = 4,3,1,0 %; ! PRIVILEGES modified macro NSA$V_SYSUAF_PWDLIFETIME = 4,4,1,0 %; ! PWDLIFETIME modified macro NSA$V_SYSUAF_PWDMINIMUM = 4,5,1,0 %; ! PWDMINIMUM modified macro NSA$V_SYSUAF_QUEPRIORITY = 4,6,1,0 %; ! QUEPRIORITY modified macro NSA$V_SYSUAF_REMOTE = 4,7,1,0 %; ! REMOTE modified macro NSA$V_SYSUAF_SFLAGS = 4,8,1,0 %; ! SFLAGS modified (obsolete) macro NSA$V_SYSUAF_S_RESTRICT = 4,9,1,0 %; ! S_RESTRICT modified (obsolete) macro NSA$V_SYSUAF_SHRFILLM = 4,10,1,0 %; ! SHRFILLM modified macro NSA$V_SYSUAF_TQELM = 4,11,1,0 %; ! TQELM modified macro NSA$V_SYSUAF_UIC = 4,12,1,0 %; ! UIC modified macro NSA$V_SYSUAF_WSDEFAULT = 4,13,1,0 %; ! WSDEFAULT modified macro NSA$V_SYSUAF_WSEXTENT = 4,14,1,0 %; ! WSEXTENT modified macro NSA$V_SYSUAF_WSQUOTA = 4,15,1,0 %; ! WSQUOTA modified macro NSA$V_SYSUAF_ENCRYPT = 4,16,1,0 %; ! PRIMARY password hash algorithm modified macro NSA$V_SYSUAF_ENCRYPT2 = 4,17,1,0 %; ! SECONDARY password hash algorithm modified macro NSA$V_SYSUAF_SALT = 4,18,1,0 %; ! SALT modified macro NSA$V_SYSUAF_PASSWORD2 = 4,19,1,0 %; ! Secondary PASSWORD modified macro NSA$V_SYSUAF_PWD_DATE = 4,20,1,0 %; ! Password expiration date macro NSA$V_SYSUAF_PWD2_DATE = 4,21,1,0 %; ! Secondary password expiration date macro NSA$V_SYSUAF_LOGFAILS = 4,22,1,0 %; ! LOGFAILS modified macro NSA$V_SYSUAF_LASTLOGIN_I = 4,23,1,0 %; ! LASTLOGIN_I modified macro NSA$V_SYSUAF_LASTLOGIN_N = 4,24,1,0 %; ! LASTLOGIN_N modified macro NSA$V_SYSUAF_MIN_CLASS = 4,25,1,0 %; ! MIN_CLASS modified macro NSA$V_SYSUAF_MAX_CLASS = 4,26,1,0 %; ! MAX_CLASS modified macro NSA$V_SYSUAF_USER_DATA = 4,27,1,0 %; ! user data area modified macro NSA$V_SYSUAF_DEF_CLASS = 4,28,1,0 %; ! DEF_CLASS modified literal NSA$S_FIELD_TBL_ENTRY = 16; macro NSA$L_FLD_NAME = 0,0,32,0 %; ! Address of ascid field name macro NSA$W_FLD_OFFSET = 4,0,16,0 %; ! Offset into record macro NSA$W_FLD_SIZE = 6,0,16,0 %; ! Size of field macro NSA$L_FLD_FMT_RTN = 8,0,32,1 %; ! Format routine macro NSA$L_FLD_FMT_P1 = 12,0,32,0 %; ! Parameter to format rtn literal NSA$M_SUM_FILE = %X'1'; literal NSA$M_SUM_PRIV = %X'2'; literal NSA$M_SUM_DEJAVU = %X'80000000'; literal NSA$S_NSASUMMARYBITS = 4; macro NSA$V_SUM_FILE = 0,0,1,0 %; ! file access auditing enabled macro NSA$V_SUM_PRIV = 0,1,1,0 %; ! privilege auditing enabled macro NSA$V_SUM_DEJAVU = 0,31,1,0 %; ! auditing running in past !*** MODULE $NSAFAIDEF *** ! ! Define the security auditing failure mode vectors. ! literal NSA$M_FAIL_WAIT = %X'1'; literal NSA$M_FAIL_CRASH = %X'2'; literal NSA$M_FAIL_IGNORE = %X'4'; literal NSA$M_MSG_LOST = %X'1'; literal NSA$C_FAI_LENGTH = 12; literal NSA$K_FAI_LENGTH = 12; literal NSA$S_NSAFAIDEF = 12; literal NSA$S_NSAFAI = 12; macro NSA$W_FAILURE_MODE = 0,0,16,0 %; macro NSA$V_FAIL_WAIT = 0,0,1,0 %; ! Wait for resources macro NSA$V_FAIL_CRASH = 0,1,1,0 %; ! Crash the system macro NSA$V_FAIL_IGNORE = 0,2,1,0 %; ! Drop failed audits macro NSA$W_FAILURE_FLAGS = 2,0,16,0 %; macro NSA$V_MSG_LOST = 2,0,1,0 %; ! Alarms lost message written? macro NSA$L_LOST_COUNT = 4,0,32,0 %; ! Failure count macro NSA$W_SIZE = 8,0,16,0 %; ! Stucture size macro NSA$B_TYPE = 10,0,8,0 %; ! Structure type (DYN$C_NSA) macro NSA$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype (DYN$C_NSA_FAILURE) !*** MODULE $NSAIDTDEF *** ! + ! Security Auditing Impure Data Table offset definitions ! - literal NSA$C_IDT_LENGTH = 4794; literal NSA$K_IDT_LENGTH = 4794; literal NSA$K_IDT_PAGES = 10; ! Number of pages for IDT literal NSA$S_NSAIDTDEF = 4794; literal NSA$S_NSAIDT = 4794; macro NSA$T_IDT_ALARM_HDR = 0,0,0,0 %; literal NSA$S_IDT_ALARM_HDR = 46; ! Alarm header buffer macro NSA$T_IDT_RECORD_BUF = 46,0,0,0 %; literal NSA$S_IDT_RECORD_BUF = 1024; ! Record buffer macro NSA$Q_IDT_RECORD_DESCR = 1070,0,0,0 %; literal NSA$S_IDT_RECORD_DESCR = 8; ! Record buffer descriptor macro NSA$T_IDT_RECORD_DT = 1078,0,0,0 %; literal NSA$S_IDT_RECORD_DT = 128; ! Record descriptor table ! audit journal channel number) !*** MODULE $NSAIFPDEF *** literal NSAP$M_MANDATORY = %X'1'; literal NSAP$M_PRIVMASK = %X'2'; literal NSAP$M_PROCPRIV = %X'4'; literal NSAP$M_AUTHPRIV = %X'8'; literal NSAP$M_AUDIT = %X'10'; literal NSAP$M_ALTPRIV = %X'20'; literal NSAP$M_IDENTIFIER = %X'40'; literal NSAP$M_INTERNAL = %X'80'; literal NSAP$M_IMAGEID = %X'100'; literal NSAP$M_ONEBIT = %X'200'; literal NSAP$M_NOPROBE = %X'400'; literal NSAP$M_FLUSH = %X'800'; literal NSAP$M_SERVER = %X'1000'; literal NSAP$M_NOFAILAUD = %X'2000'; literal NSAP$M_NOSUCCAUD = %X'4000'; literal NSAP$M_KTBVALID = %X'8000'; literal NSAP$M_PSBVALID = %X'10000'; literal NSAP$K_LENGTH = 28; ! size of input potion of control block literal NSAP$S_NSAIFPDEF = 28; literal NSAP$S_NSAIFP = 28; macro NSAP$L_FLAGS = 0,0,32,0 %; macro NSAP$V_MANDATORY = 0,0,1,0 %; ! force privilege audit macro NSAP$V_PRIVMASK = 0,1,1,0 %; ! caller supplied address of privilege mask macro NSAP$V_PROCPRIV = 0,2,1,0 %; ! check permanent privilege mask macro NSAP$V_AUTHPRIV = 0,3,1,0 %; ! check authorized privilege mask macro NSAP$V_AUDIT = 0,4,1,0 %; ! privilege audit required macro NSAP$V_ALTPRIV = 0,5,1,0 %; ! check alternate mask supplied by caller macro NSAP$V_IDENTIFIER = 0,6,1,0 %; ! check identifier instead of privilege macro NSAP$V_INTERNAL = 0,7,1,0 %; ! privilege check being performed on behalf of TCB macro NSAP$V_IMAGEID = 0,8,1,0 %; ! identifier was located in image rights list segment macro NSAP$V_ONEBIT = 0,9,1,0 %; ! privilege mask contained only a single bit macro NSAP$V_NOPROBE = 0,10,1,0 %; ! do not probe item list macro NSAP$V_FLUSH = 0,11,1,0 %; ! force audit server buffer flush macro NSAP$V_SERVER = 0,12,1,0 %; ! audit from trusted (TCB) server macro NSAP$V_NOFAILAUD = 0,13,1,0 %; ! do not audit failures macro NSAP$V_NOSUCCAUD = 0,14,1,0 %; ! do not audit success macro NSAP$V_KTBVALID = 0,15,1,0 %; ! KTB address in R4 is accurate ! (reflects the applicable KTB when PCB) macro NSAP$V_PSBVALID = 0,16,1,0 %; ! PSB referenced by KTB is current ! (no need to perform a lazy assume or import ARB) macro NSAP$L_AUDIT_MASK = 4,0,32,0 %; ! audit mask (NSA$W_FLAGS) macro NSAP$L_AUDIT_LIST = 8,0,32,1 %; ! address of optional audit message itemlist macro NSAP$L_MESSAGE = 12,0,32,0 %; ! privilege audit message code ($NSA) macro NSAP$L_AUDSTS = 12,0,32,0 %; ! privilege audit return status macro NSAP$Q_ALTPRIV = 16,0,0,0 %; literal NSAP$S_ALTPRIV = 8; ! alternate privilege mask to check macro NSAP$Q_PRIV = 16,0,0,0 %; literal NSAP$S_PRIV = 8; ! mask of privileges that were checked (success) macro NSAP$Q_AUDPRIV = 16,0,0,0 %; literal NSAP$S_AUDPRIV = 8; ! mask of privileges to audit (success/failure) macro NSAP$Q_FAILPRIV = 16,0,0,0 %; literal NSAP$S_FAILPRIV = 8; ! mask of privileges that caller lacked (failure) macro NSAP$L_IDENTIFIER = 16,0,32,0 %; ! identifier to check macro NSAP$L_REPLY_MAILBOX = 24,0,32,1 %; ! reply mailbox descriptor address !*** MODULE $NSASDEF *** ! Define the layout of the structure returned by NSA$SIZE_NSAB. literal NSAS$M_NOALARM = %X'1'; literal NSAS$M_NOAUDIT = %X'2'; literal NSAS$M_NOPROBE = %X'4'; literal NSAS$M_PRIVS_SUPPLIED = %X'8'; literal NSAS$K_MAX_JOURNALS = 1; ! maximum number of alarm or audit journals literal NSAS$K_LENGTH = 76; ! define length of structure literal NSAS$S_NSASDEF = 76; ! Old size name - synonym literal NSAS$S_NSAS = 76; macro NSAS$L_SIZE = 0,0,32,0 %; ! size of required packet list macro NSAS$L_SUPPLIED = 4,0,32,0 %; ! supplied packet mask macro NSAS$L_EVENT = 8,0,32,0 %; ! event type/subtype as longword macro NSAS$W_EVENT_TYPE = 8,0,16,0 %; ! event type macro NSAS$W_EVENT_SUBTYPE = 10,0,16,0 %; ! event subtype macro NSAS$L_FACILITY = 12,0,32,0 %; ! event facility macro NSAS$L_FLAGS = 16,0,32,0 %; ! flags macro NSAS$V_NOALARM = 16,0,1,0 %; ! do not copy alarm packets macro NSAS$V_NOAUDIT = 16,1,1,0 %; ! do not copy audit packets macro NSAS$V_NOPROBE = 16,2,1,0 %; ! do not probe item list macro NSAS$V_PRIVS_SUPPLIED = 16,3,1,0 %; ! did the caller supply a priv mask ! or identifier list? macro NSAS$L_ACCESS_DESIRED = 20,0,32,0 %; ! actual access desired macro NSAS$L_PRIVS_USED = 24,0,32,0 %; ! actual privs used (as longword) macro NSAS$Q_PRIVS_USED = 24,0,0,0 %; literal NSAS$S_PRIVS_USED = 8; ! actual privs used (as quadword) macro NSAS$L_ALARM_COUNT = 32,0,32,0 %; ! number of alarm journals present macro NSAS$L_AUDIT_COUNT = 36,0,32,0 %; ! number of audit journals present macro NSAS$L_MIN_CLASS_ADDR = 40,0,32,1 %; ! address of min. class mask macro NSAS$L_MAX_CLASS_ADDR = 44,0,32,1 %; ! address of max. class mask macro NSAS$Q_OBJECT_CLASS = 48,0,0,0 %; literal NSAS$S_OBJECT_CLASS = 8; ! object class name descriptor macro NSAS$R_CLASS_DESC = 48,0,0,0 %; literal NSAS$S_CLASS_DESC = 8; macro NSAS$W_CLASS_LENGTH = 48,0,16,0 %; ! object class name length macro NSAS$L_CLASS_ADDR = 52,0,32,1 %; ! object class name buffer address macro NSAS$Q_ALARM_LIST = 56,0,0,0 %; literal NSAS$S_ALARM_LIST = 8; ! array of alarm journals descriptors macro NSAS$Q_AUDIT_LIST = 64,0,0,0 %; literal NSAS$S_AUDIT_LIST = 8; ! array of audit journals descriptors macro NSAS$L_FINAL_STATUS = 72,0,32,0 %; ! actual final status !*** MODULE $NTEDEF *** ! + ! NOTIFICATION TABLE ENTRY DEFINITIONS ! ! NOTIFICATION TABLE ENTRIES ARE USED BY THE NOTIFICATION MODULE ROUTINES. ! EACH ENTRY STORES THE INFORMATION NEEDED FOR A SINGLE NOTIFICATION. THE ! SYSTEM MAINTAINS TWO TABLES OF SUCH ENTRIES, ONE EACH FOR JOIN NOTIFICATION ! AND REMOVAL NOTIFICATION. ! ! - literal NTE$K_LENGTH = 12; ! LENGTH OF AN ENTRY literal NTE$C_LENGTH = 12; ! LENGTH OF AN ENTRY literal NTE$S_NTEDEF = 12; literal NTE$S_NTE = 12; macro NTE$L_NOTIFN_LIST_HDR = 0,0,32,0 %; macro NTE$W_NOTIFNEFL = 0,0,16,0 %; ! INDEX OF FIRST NOTIFICATION ENTRY ON THE TABLE macro NTE$W_NOOFENT = 2,0,16,0 %; ! NUMBER OF ENTRIES IN THE TABLE macro NTE$L_NOTIFN_ID = 0,0,32,0 %; macro NTE$W_LINK = 0,0,16,0 %; ! LINK TO THE NEXT ENTRY ON THE LIST macro NTE$W_SEQNO = 2,0,16,0 %; ! SEQUENCE NUMBER OF THIS ENTRY macro NTE$L_ROUTINE_ADDRESS = 4,0,32,1 %; ! ADDRESS OF ROUTINE TO BE CALLED DURING NOTIFICATION macro NTE$L_FREE_LIST_HDR = 4,0,32,0 %; macro NTE$W_FREEFL = 4,0,16,0 %; ! INDEX OF FIRST FREE ENTRY ON THE TABLE macro NTE$L_NOTIFN_PARAM = 8,0,32,0 %; ! PARAMETER TO BE PASSED TO THE ROUTINE macro NTE$L_TYPE_DEFN = 8,0,32,0 %; macro NTE$W_SIZE = 8,0,16,0 %; ! SIZE OF THE TABLE macro NTE$B_TYPE = 10,0,8,0 %; ! TYPE OF THE DATA STRUCTURE macro NTE$B_SUBTYPE = 11,0,8,0 %; ! SUBTYPE OF THE DATA STRUCTURE !*** MODULE $OCBDEF *** ! + ! OCB - Object Class Block ! ! This structures contains information about a security Object ! Class Block. ! ! - literal OCB$M_ACC_BITS_ALLOC = %X'1'; literal OCB$M_IMP_GRP_NAMING = %X'2'; literal OCB$M_CREATE = %X'4'; literal OCB$M_DEACCESS = %X'8'; literal OCB$M_DELETE = %X'10'; literal OCB$K_LENGTH = 203; ! Length of structure literal OCB$S_OCBDEF = 203; ! Old size name - synonym literal OCB$S_OCB = 203; macro OCB$L_FLINK = 0,0,32,1 %; ! Forward link macro OCB$L_BLINK = 4,0,32,1 %; ! Backward link macro OCB$W_SIZE = 8,0,16,0 %; ! Allocation size macro OCB$B_TYPE = 10,0,8,0 %; ! Structure type macro OCB$B_SUBTYPE = 11,0,8,0 %; ! Subtype macro OCB$L_FLAGS = 20,0,32,0 %; ! Processing flags macro OCB$V_ACC_BITS_ALLOC = 20,0,1,0 %; ! Bitname XLATE allocated macro OCB$V_IMP_GRP_NAMING = 20,1,1,0 %; ! Implicit group namespace macro OCB$V_CREATE = 20,2,1,0 %; ! Object class supports creation auditing macro OCB$V_DEACCESS = 20,3,1,0 %; ! Object class supports deaccess auditing macro OCB$V_DELETE = 20,4,1,0 %; ! Object class supports deletion auditing (devices) macro OCB$L_OBJECT_TYPE = 24,0,32,0 %; ! Object type value macro OCB$L_CLASS_ORB = 28,0,32,0 %; ! Class rights block macro OCB$L_DEFAULT_ORB = 32,0,32,0 %; ! Default rights block macro OCB$L_ACCESS_BITNAMES = 36,0,32,1 %; ! Ptr to access bitnames macro OCB$L_SUPPORT_RTNS = 40,0,32,1 %; ! Ptr to support rtns dispatch macro OCB$AR_ACC_AUDITS = 44,0,32,1 %; ! Ptr to access audits macro OCB$AR_ACC_ALARMS = 48,0,32,1 %; ! Ptr to access alarms macro OCB$L_ACCESS_MODES = 52,0,32,0 %; ! Mask of valid access modes macro OCB$L_ACC_BITNAME_SIZE = 60,0,32,0 %; ! Size of pool for bitname table macro OCB$L_ACC_BITNAME_LENGTH = 64,0,32,0 %; ! Length of access bitname table ! macro OCB$T_ACCESS_AUDITS = 68,0,0,0 %; literal OCB$S_ACCESS_AUDITS = 48; ! Access audits macro OCB$T_ACCESS_ALARMS = 116,0,0,0 %; literal OCB$S_ACCESS_ALARMS = 48; ! Access alarms ! macro OCB$L_NAME_LENGTH = 164,0,32,0 %; ! Length of class name macro OCB$AR_CLASS_PROT_ALARMS = 172,0,32,1 %; ! Ptr to class alarms macro OCB$AR_CLASS_PROT_AUDITS = 176,0,32,1 %; ! Ptr to class audits macro OCB$T_NAME = 180,0,0,0 %; literal OCB$S_NAME = 23; ! Class name string !*** MODULE $OLCKDEF *** ! + ! OLCK - ORB LOCK ! ! This structures contains information about an outstanding LOCK ! on the Object Rights Block of a specific resourse. It is ! maintained in a per process database (CTL$GQ_ORB_LOCKDB) used ! to control ACL modifications through $CHANGE_ACL. ! ! - literal OLCK$M_RESV_1 = %X'1'; literal OLCK$K_FIXED_LEN = 30; ! Fixed length literal OLCK$K_MAX_RSN = 33; ! Maximum resource name literal OLCK$S_OLCKDEF = 30; ! Old size name - synonym literal OLCK$S_OLCK = 30; macro OLCK$L_FLINK = 0,0,32,1 %; ! Forward link macro OLCK$L_BLINK = 4,0,32,1 %; ! Backward link macro OLCK$W_SIZE = 8,0,16,0 %; ! Allocation size macro OLCK$B_TYPE = 10,0,8,0 %; ! Structure type macro OLCK$B_STYPE = 11,0,8,0 %; ! Subtype macro OLCK$L_LOCKID = 12,0,32,0 %; ! Lockid macro OLCK$B_PRV_LKMODE = 16,0,8,0 %; ! Previous lock mode macro OLCK$B_CUR_LKMODE = 17,0,8,0 %; ! Current lock mode macro OLCK$W_FLAGS = 18,0,16,0 %; ! Processing flags macro OLCK$V_RESV_1 = 18,0,1,0 %; ! reserved for future macro OLCK$L_RESV_1 = 20,0,32,0 %; ! Reserved macro OLCK$L_RESV_2 = 24,0,32,0 %; ! for future use macro OLCK$W_RSN_SIZE = 28,0,16,0 %; ! Size of resource name macro OLCK$T_RSN = 30,0,0,0 %; ! Resource name string !*** MODULE $ORBDEF *** ! + ! ! Object's Rights Block - structure defining the protection information ! for various objects within the system. ! ! - literal ORB$M_PROT_16 = %X'1'; literal ORB$M_ACL_QUEUE = %X'2'; literal ORB$M_MODE_VECTOR = %X'4'; literal ORB$M_NOACL = %X'8'; literal ORB$M_CLASS_PROT = %X'10'; literal ORB$M_NOAUDIT = %X'20'; literal ORB$M_MODE_VALID = %X'80'; literal ORB$M_PROFILE_LOCKED = %X'100'; literal ORB$M_INDIRECT_ACL = %X'200'; literal ORB$M_BOOTTIME = %X'400'; literal ORB$M_UNMODIFIED = %X'800'; literal ORB$M_DAMAGED = %X'1000'; literal ORB$M_TEMPLATE = %X'2000'; literal ORB$M_TRANSITION = %X'4000'; literal ORB$M_EXT_NAMEBLOCK = %X'8000'; literal ORB$K_LENGTH = 124; ! Structure length literal ORB$C_LENGTH = 124; ! Structure length literal ORB$K_DEVNAM_LENGTH = 64; ! size of static device name literal ORB$C_DEVNAM_LENGTH = 64; ! size of static device name literal ORB$S_ORBDEF = 125; ! Old ORB size field for compatability literal ORB$S_ORB = 125; macro ORB$L_OWNER = 0,0,32,0 %; ! Object's owner macro ORB$W_UICMEMBER = 0,0,16,0 %; ! Member number macro ORB$W_UICGROUP = 2,0,16,0 %; ! Group number macro ORB$L_ACL_MUTEX = 4,0,32,0 %; ! Mutex for this ACL macro ORB$W_SIZE = 8,0,16,0 %; ! Size of the ORB in bytes macro ORB$B_TYPE = 10,0,8,0 %; ! Structure type macro ORB$B_SUBTYPE = 11,0,8,0 %; ! Subtype of ORB block: ! 0 - normal ORB ! 1 - block used to contain a name (only) macro ORB$W_FLAGS = 12,0,16,0 %; ! System protection field macro ORB$B_FLAGS_1 = 12,0,8,0 %; ! first byte of flags macro ORB$B_FLAGS_2 = 13,0,8,0 %; ! second byte of flags macro ORB$B_FLAGS = 12,0,8,0 %; ! first byte of flags macro ORB$V_PROT_16 = 12,0,1,0 %; ! Use word not vector protection macro ORB$V_ACL_QUEUE = 12,1,1,0 %; ! (*temp*) remove at later time macro ORB$V_MODE_VECTOR = 12,2,1,0 %; ! Use vector not byte mode protection macro ORB$V_NOACL = 12,3,1,0 %; ! Object cannot have an ACL macro ORB$V_CLASS_PROT = 12,4,1,0 %; ! Security classification is valid macro ORB$V_NOAUDIT = 12,5,1,0 %; ! Do not perform $CHKPRO auditing macro ORB$V_MODE_VALID = 12,7,1,0 %; ! Access mode protection is valid macro ORB$V_PROFILE_LOCKED = 12,8,1,0 %; ! Object locked, no modification allowed ! The PROFILE_LOCKED flag is intended to be set when the profile cannot ! reasonably be modified. I.e., the protection of a volume set may only be ! altered if the root volume of the set is mounted, though mounting a selected ! volume from a volume set is supported. macro ORB$V_INDIRECT_ACL = 12,9,1,0 %; ! Use the ACL from the template ! ORB (ORB$L_TEMPLATE) macro ORB$V_BOOTTIME = 12,10,1,0 %; ! ORB created prior to securty object init. macro ORB$V_UNMODIFIED = 12,11,1,0 %; ! ORB has not been explicitly modified macro ORB$V_DAMAGED = 12,12,1,0 %; ! Deny access to all but system (BADACL) macro ORB$V_TEMPLATE = 12,13,1,0 %; ! This orb is a template macro ORB$V_TRANSITION = 12,14,1,0 %; ! Profile content uncertain -- ! eg. cluster instantiation macro ORB$V_EXT_NAMEBLOCK = 12,15,1,0 %; ! ORB name is store in a separate 'ORB' block ! macro ORB$W_REFCOUNT = 14,0,16,0 %; ! Reference count macro ORB$Q_MODE_PROT = 16,0,0,0 %; literal ORB$S_MODE_PROT = 8; ! Mode protection vector macro ORB$L_MODE_PROTL = 16,0,32,0 %; ! Low longword of vector macro ORB$L_MODE_PROTH = 20,0,32,0 %; ! High longword of vector macro ORB$L_MODE = 16,0,32,0 %; ! Simple access mode macro ORB$L_SYS_PROT = 24,0,32,0 %; ! System protection field macro ORB$W_PROT = 24,0,16,0 %; ! Standard SOGW protection macro ORB$L_OWN_PROT = 28,0,32,0 %; ! Owner protection field macro ORB$L_GRP_PROT = 32,0,32,0 %; ! Group protection field macro ORB$L_WOR_PROT = 36,0,32,0 %; ! World protection field macro ORB$L_ACLFL = 40,0,32,1 %; ! ACL queue forward link macro ORB$L_ACL_COUNT = 40,0,32,0 %; ! Count of ACL segments macro ORB$L_ACLBL = 44,0,32,1 %; ! ACL queue backward link macro ORB$L_ACL_DESC = 44,0,32,1 %; ! Address of ACL segment descriptor list macro ORB$R_MIN_CLASS = 48,0,0,0 %; literal ORB$S_MIN_CLASS = 20; macro ORB$R_MAX_CLASS = 68,0,0,0 %; literal ORB$S_MAX_CLASS = 20; macro ORB$W_NAME_LENGTH = 88,0,16,0 %; ! Length of object name macro ORB$L_NAME_POINTER = 92,0,32,1 %; ! Pointer to object name macro ORB$L_OCB = 96,0,32,1 %; ! Pointer to Object Class Block macro ORB$L_TEMPLATE_ORB = 100,0,32,1 %; ! Pointer to template ORB macro ORB$L_OBJECT_SPECIFIC = 104,0,32,1 %; ! Object class specific usage cell macro ORB$L_ORIGINAL_ORB = 108,0,32,1 %; ! Pointer to another ORB macro ORB$L_UPDSEQ = 112,0,32,0 %; ! Update sequence number macro ORB$L_MUTEX_ADDRESS = 116,0,32,1 %; ! Address of mutex for CHKPRO macro ORB$L_RESERVE2 = 120,0,32,1 %; ! for future use macro ORB$T_OBJECT_NAME = 124,0,8,0 %; ! Start of object name !*** MODULE $OSRDEF *** ! + ! Object Support Routine flag definitions. ! ! This structure contains the flag definitions that are used ! to control processing between the security object management ! services and the Object Support Routines. These are internal ! flags used within the services and should not be used in the ! system service interfaces. ! - literal OSR$M_ACCESS_CHECKED = %X'1'; literal OSR$M_MOD_MAC = %X'2'; literal OSR$M_NO_LOCK_RSN = %X'4'; literal OSR$M_RUNDOWN = %X'8'; literal OSR$M_WRITE = %X'10'; literal OSR$M_MOD_ORB = %X'20'; literal OSR$M_MOD_ACL = %X'40'; literal OSR$M_MOD_FOR = %X'80'; literal OSR$M_KERNEL_SETITM = %X'100'; literal OSR$M_KERNEL_CLONE_PROFILE = %X'200'; literal OSR$M_KERNEL_UPDATE_PROFILE = %X'400'; literal OSR$M_KERNEL_RUNDOWN = %X'800'; literal OSR$M_KERNEL_CHECK_ACCESS = %X'1000'; literal OSR$M_KERNEL_TRANQUILITY = %X'2000'; literal OSR$M_KERNEL_FIXUP_BTIME_ORBS = %X'4000'; literal OSR$M_RELCTX = %X'8000'; literal OSR$M_SELECT_NAME = %X'10000'; literal OSR$M_SELECT_HANDLE = %X'20000'; literal OSR$M_EMBED_OBJNAM = %X'40000'; literal OSR$M_CLUSTER_OBJECT = %X'80000'; literal OSR$M_CONTEXT_NAME = %X'100000'; literal OSR$M_CLUSTER_NOTIFY = %X'200000'; literal OSR$M_TEMPORARY = %X'400000'; literal OSR$M_PERMANENT = %X'800000'; literal OSR$M_NEW_OBJECT = %X'1000000'; literal OSR$M_NO_CREATE = %X'2000000'; literal OSR$M_NO_MAC_DAC = %X'4000000'; literal OSR$M_NO_MAC_AUDIT = %X'8000000'; literal OSR$M_MO_MAC_RANGE = %X'10000000'; literal OSR$M_NO_MAC = %X'20000000'; literal OSR$S_OSRDEF = 4; ! Old size name - synonym literal OSR$S_OSR = 4; macro OSR$V_ACCESS_CHECKED = 0,0,1,0 %; ! Bypass chkpro in $xETSOI macro OSR$V_MOD_MAC = 0,1,1,0 %; ! Secrecy/integrity hanged macro OSR$V_NO_LOCK_RSN = 0,2,1,0 %; ! No need to build lock rsn in preprocess OSR macro OSR$V_RUNDOWN = 0,3,1,0 %; ! Rundown OSR call required for $xETSOI macro OSR$V_WRITE = 0,4,1,0 %; ! Write operation $SETSOI macro OSR$V_MOD_ORB = 0,5,1,0 %; ! ORB (proper) was modified macro OSR$V_MOD_ACL = 0,6,1,0 %; ! ORB ACL was modified macro OSR$V_MOD_FOR = 0,7,1,0 %; ! Foreign char was modified macro OSR$V_KERNEL_SETITM = 0,8,1,0 %; ! Process set itmlist processing in k_mode macro OSR$V_KERNEL_CLONE_PROFILE = 0,9,1,0 %; ! Call clone_profile OSR in k_mode macro OSR$V_KERNEL_UPDATE_PROFILE = 0,10,1,0 %; ! Call update_profile OSR in k_mode macro OSR$V_KERNEL_RUNDOWN = 0,11,1,0 %; ! Call rundown OSR in k_mode macro OSR$V_KERNEL_CHECK_ACCESS = 0,12,1,0 %; ! Call check_access OSR in k_mode macro OSR$V_KERNEL_TRANQUILITY = 0,13,1,0 %; ! Call set/clear trauility in K-mode macro OSR$V_KERNEL_FIXUP_BTIME_ORBS = 0,14,1,0 %; ! Call fixup_btime_orbs OSR in k_mode macro OSR$V_RELCTX = 0,15,1,0 %; ! Release OSR context macro OSR$V_SELECT_NAME = 0,16,1,0 %; ! Select object by name macro OSR$V_SELECT_HANDLE = 0,17,1,0 %; ! Select object by handle macro OSR$V_EMBED_OBJNAM = 0,18,1,0 %; ! Embed object name in ORB macro OSR$V_CLUSTER_OBJECT = 0,19,1,0 %; ! Cluster visible object macro OSR$V_CONTEXT_NAME = 0,20,1,0 %; ! Use object name from context ! for cluster distribution macro OSR$V_CLUSTER_NOTIFY = 0,21,1,0 %; ! Cluster notification ! (for volumes) macro OSR$V_TEMPORARY = 0,22,1,0 %; ! Temporary object ! eg. foreign monted disk macro OSR$V_PERMANENT = 0,23,1,0 %; ! Not temporary macro OSR$V_NEW_OBJECT = 0,24,1,0 %; ! Any existing profile is stale macro OSR$V_NO_CREATE = 0,25,1,0 %; ! Don't create a new profile. macro OSR$V_NO_MAC_DAC = 0,26,1,0 %; ! Concurrent MAC/DAC modifications ! not supported macro OSR$V_NO_MAC_AUDIT = 0,27,1,0 %; ! Suppress $SET_SECURITY MAC audits macro OSR$V_MO_MAC_RANGE = 0,28,1,0 %; ! MAC range not supported macro OSR$V_NO_MAC = 0,29,1,0 %; ! MAC modifications not supported ! + ! The OSR context area is an overlay of the UNC$S/T_OSR_CONTEXT area ! in the universal context area structure ($UNCDEF). If the size of ! this area is larger then UNC$S_OSR_CONTEXT, you must enlarge the ! universal context area defintion. There are ASSUMEs in the ROUTINES ! that allocate the context structure. ! - literal OSRCTX$M_CLS_INIT = %X'1'; literal OSRCTX$M_CLS_TMPNAM = %X'2'; literal OSRCTX$M_LNT_INIT = %X'1'; literal OSRCTX$M_LNT_ACCESS_QUAL = %X'2'; literal OSRCTX$M_DEV_CHAN = %X'1'; literal OSRCTX$M_DEV_TEMPLATE = %X'2'; literal OSRCTX$M_DEV_ALL = %X'4'; literal OSRCTX$M_FIL_DEACCESS = %X'1'; literal OSRCTX$M_VOL_DEACCESS = %X'1'; literal OSRCTX$S_OSR_CTXDEF = 16; ! Old size name - synonym literal OSRCTX$S_OSR_CTX = 16; macro OSRCTX$L_CLS_OCB = 0,0,32,1 %; ! Original OCB macro OSRCTX$L_CLS_FLAGS = 4,0,32,1 %; ! Processing flags macro OSRCTX$V_CLS_INIT = 4,0,1,0 %; ! Initialized macro OSRCTX$V_CLS_TMPNAM = 4,1,1,0 %; ! Template present macro OSRCTX$L_CLS_TMPNAM_LENGTH = 8,0,32,0 %; ! Template name length macro OSRCTX$L_CLS_TMPNAM = 12,0,32,0 %; ! Template name macro OSRCTX$L_LNT_FLAGS = 0,0,32,1 %; ! Processing flags macro OSRCTX$V_LNT_INIT = 0,0,1,0 %; ! Initialized macro OSRCTX$V_LNT_ACCESS_QUAL = 0,1,1,0 %; ! Access qualifier present macro OSRCTX$B_LNT_ACCESS_MODE = 4,0,8,0 %; ! Access mode macro OSRCTX$B_LNT_RESV_1 = 5,0,8,0 %; ! Reserved for future macro OSRCTX$W_LNT_OBJNAM_LEN = 6,0,16,0 %; ! LNT name (without access mode) macro OSRCTX$L_LNT_RESV_2 = 8,0,32,0 %; ! Reserved for future macro OSRCTX$L_LNT_RESV_3 = 12,0,32,0 %; ! Reserved for future macro OSRCTX$L_CEF_RESV_1 = 0,0,32,0 %; ! Reserved macro OSRCTX$L_CEF_RESV_2 = 4,0,32,0 %; ! macro OSRCTX$L_CEF_RESV_3 = 8,0,32,0 %; ! for macro OSRCTX$W_CEF_RESV_4 = 12,0,16,0 %; ! macro OSRCTX$W_CEF_RESV_5 = 14,0,16,0 %; ! future use macro OSRCTX$L_DEV_ORB = 0,0,32,1 %; ! Active device ORB macro OSRCTX$L_DEV_RESV_2 = 4,0,32,0 %; ! macro OSRCTX$L_DEV_RESV_3 = 8,0,32,0 %; ! macro OSRCTX$W_DEV_CHAN = 12,0,16,0 %; ! channel # macro OSRCTX$W_DEV_FLAGS = 14,0,16,1 %; ! processing flags macro OSRCTX$V_DEV_CHAN = 14,0,1,0 %; ! channel assigned by OSRs macro OSRCTX$V_DEV_TEMPLATE = 14,1,1,0 %; ! dealing with template device macro OSRCTX$V_DEV_ALL = 14,2,1,0 %; ! devcie allocated by OSRs macro OSRCTX$L_FIL_RESV_1 = 0,0,32,0 %; ! Reserved macro OSRCTX$L_FIL_RESV_2 = 4,0,32,0 %; ! for macro OSRCTX$L_FIL_RESV_3 = 8,0,32,0 %; ! future use macro OSRCTX$W_FIL_CHANNEL = 12,0,16,0 %; ! macro OSRCTX$W_FIL_FLAGS = 14,0,16,1 %; ! File context flags macro OSRCTX$V_FIL_DEACCESS = 14,0,1,0 %; ! Deaccess file at OSR rundown macro OSRCTX$L_QUE_RESV_1 = 0,0,32,0 %; ! Reserved macro OSRCTX$L_QUE_RESV_2 = 4,0,32,0 %; ! macro OSRCTX$L_QUE_RESV_3 = 8,0,32,0 %; ! for macro OSRCTX$W_QUE_RESV_4 = 12,0,16,0 %; ! macro OSRCTX$W_QUE_RESV_5 = 14,0,16,0 %; ! future use macro OSRCTX$L_PRC_RESV_1 = 0,0,32,0 %; ! Reserved macro OSRCTX$L_PRC_RESV_2 = 4,0,32,0 %; ! macro OSRCTX$L_PRC_RESV_3 = 8,0,32,0 %; ! for macro OSRCTX$W_PRC_RESV_4 = 12,0,16,0 %; ! macro OSRCTX$W_PRC_RESV_5 = 14,0,16,0 %; ! future use macro OSRCTX$L_SEC_TRANQ_CNT = 0,0,32,0 %; ! Tranquility count (MAC) macro OSRCTX$L_SEC_RESV_2 = 4,0,32,0 %; ! Reserved macro OSRCTX$L_SEC_RESV_3 = 8,0,32,0 %; ! for macro OSRCTX$W_SEC_RESV_4 = 12,0,16,0 %; ! macro OSRCTX$W_SEC_RESV_5 = 14,0,16,0 %; ! future use macro OSRCTX$L_VOL_RESV_1 = 0,0,32,0 %; ! Reserved macro OSRCTX$L_VOL_RESV_2 = 4,0,32,0 %; ! for macro OSRCTX$L_VOL_RESV_3 = 8,0,32,0 %; ! future use macro OSRCTX$W_VOL_CHANNEL = 12,0,16,0 %; ! macro OSRCTX$W_VOL_FLAGS = 14,0,16,1 %; ! Volume context flags macro OSRCTX$V_VOL_DEACCESS = 14,0,1,0 %; ! Deassign channel at OSR rundown macro OSRCTX$L_RSDM_DOMAIN = 0,0,32,0 %; ! Domain number macro OSRCTX$L_RSDM_LOCKID = 4,0,32,0 %; ! Tranquility lock id (MAC) macro OSRCTX$L_RSDM_RESV_3 = 8,0,32,0 %; ! Reserved macro OSRCTX$W_RSDM_RESV_4 = 12,0,16,0 %; ! for macro OSRCTX$W_RSDM_RESV_5 = 14,0,16,0 %; ! future use !*** MODULE $OSRVDEF *** ! + ! OSRV - Object Support Routine Vectors ! ! This structures contains information about the security Object ! Support Routine dispatch Vectors. It is through these dispatch ! vectors that the various security subsystem components callout ! to the object class specific functions. ! - literal OSRV$K_LENGTH = 68; ! Size of the vectors literal OSRV$S_OSRVDEF = 68; literal OSRV$S_OSRV = 68; macro OSRV$L_ACCESS_EXCEPTION = 0,0,32,0 %; ! $CHKPRO access exception macro OSRV$L_CLONE_PROFILE = 4,0,32,0 %; ! Clone object profile macro OSRV$L_GET_ITEM = 8,0,32,0 %; ! Get foreign item processing macro OSRV$L_PREPROCESS = 12,0,32,0 %; ! Preprocess (setup) macro OSRV$L_RUNDOWN = 16,0,32,0 %; ! Postprocessing (cleanup) macro OSRV$L_SET_ITEM = 20,0,32,0 %; ! Get foreign item processing macro OSRV$L_UPDATE_PROFILE = 24,0,32,0 %; ! Update the object profile macro OSRV$L_CHECK_ACCESS = 28,0,32,0 %; ! $CHECK_ACCESS routine macro OSRV$L_FIXUP_BTIME_ORBS = 32,0,32,0 %; ! Fixup any boot time ORBs macro OSRV$L_RESOLVE_ACL = 36,0,32,0 %; ! Fixup ACL indirection macro OSRV$L_READ_PROFILE = 40,0,32,0 %; ! re-read profile from ! backing store (volume support) macro OSRV$L_SET_TRANQUILITY = 44,0,32,0 %; ! establish tranquility macro OSRV$L_CLEAR_TRANQUILITY = 48,0,32,0 %; ! relinquish tranquility macro OSRV$L_CHECK_ACCESS_PSB = 52,0,32,0 %; ! macro OSRV$L_RESERVED_2 = 56,0,32,0 %; ! reserved macro OSRV$L_RESERVED_3 = 60,0,32,0 %; ! reserved macro OSRV$L_RESERVED_4 = 64,0,32,0 %; ! reserved !*** MODULE $OSSFLGDEF *** ! + ! Security Object Information context flags definitions. ! ! This structure contains the flag definitions that are used ! in ctl$gl_oss_flags ! ! - literal OSSFLG$M_RNDWN_DCLR = %X'1'; literal OSSFLG$S_OSSFLGDEF = 1; literal OSSFLG$S_OSSFLG = 1; macro OSSFLG$V_RNDWN_DCLR = 0,0,1,0 %; ! Rundown handler declared !*** MODULE $P1PLDEF *** ! + ! Process pool log entry ! - literal P1PLE$K_LENGTH = 32; ! Size of structure literal P1PLE$C_LENGTH = 32; ! Size of structure literal P1PLE$S_P1PLE = 32; macro P1PLE$Q_DEA_PC = 0,0,0,0 %; literal P1PLE$S_DEA_PC = 8; macro P1PLE$Q_ALO_PC = 8,0,0,0 %; literal P1PLE$S_ALO_PC = 8; macro P1PLE$L_SIZE = 16,0,32,0 %; macro P1PLE$L_VA = 20,0,32,0 %; macro P1PLE$Q_TIME = 24,0,0,0 %; literal P1PLE$S_TIME = 8; literal P1PL$M_MATCH = %X'1'; literal P1PL$M_COMPRESS = %X'2'; literal P1PL$S_P1PL = 64; macro P1PL$L_SIZE = 0,0,32,0 %; macro P1PL$L_NEXT = 4,0,32,0 %; macro P1PL$Q_REGION_ID = 8,0,0,0 %; literal P1PL$S_REGION_ID = 8; macro P1PL$L_FLAGS = 16,0,32,0 %; macro P1PL$V_MATCH = 16,0,1,0 %; ! Mark deallocation in matching allocation entry macro P1PL$V_COMPRESS = 16,1,1,0 %; ! Compress if log full: eliminate matched alloc/dealloc records macro P1PL$L_COMPRESS_COUNT = 20,0,32,0 %; macro P1PL$L_DEALLOC_COUNT = 24,0,32,0 %; macro P1PL$L_ALLOC_COUNT = 28,0,32,0 %; macro P1PL$A_ENTRY = 32,0,0,0 %; literal P1PL$S_ENTRY = 32; ! Beginn of log entries !*** MODULE $PACDEF *** ! + ! PACDEF ! - literal PAC$K_LENGTH = 16; literal PAC$C_LENGTH = 16; literal PAC$S_PAC = 16; macro PAC$T_NAME = 0,0,32,0 %; literal PAC$S_NAME = 4; ! Port name macro PAC$L_SPARE = 4,0,32,0 %; ! Possible expansion macro PAC$L_ALLOCLS = 12,0,32,0 %; ! The allocation class for this port !*** MODULE $PKBDEF *** ! + ! PKBDEF ! - literal PKB$K_LENGTH = 80; literal PKB$C_LENGTH = 80; literal PKB$S_PKB = 80; ! The fork block macro PKB$PS_FQFL = 0,0,32,1 %; ! Fork queue forward link macro PKB$PS_FQBL = 4,0,32,1 %; ! Fork queue backward link macro PKB$W_SIZE = 8,0,16,0 %; ! Size of PKB in bytes macro PKB$B_TYPE = 10,0,8,0 %; ! Structure type (use DYN$C_FKB here ! and use SIZE field to see if PKB). macro PKB$B_FLCK = 11,0,8,0 %; ! Fork lock number macro PKB$PS_FPC = 12,0,32,1 %; ! Fork PC macro PKB$Q_FR3 = 16,0,0,1 %; literal PKB$S_FR3 = 8; ! Fork R3 macro PKB$Q_FR4 = 24,0,0,1 %; literal PKB$S_FR4 = 8; ! Fork R4 ! The LKSB or IOSB macro PKB$W_STATUS = 32,0,16,0 %; ! Status macro PKB$W_COUNT = 34,0,16,0 %; ! Unused (if IOSB, byte count) macro PKB$L_LOCKID = 36,0,32,0 %; ! Lock ID (if IOSB, DEVDEPEND bits) ! The resource descriptor macro PKB$L_RESNAM_D = 40,0,32,1 %; ! Descriptor macro PKB$W_RESNAM_LENGTH = 40,0,16,0 %; ! Length macro PKB$B_RESNAM_TYPE = 42,0,8,0 %; ! Type macro PKB$B_RESNAM_SUBTYPE = 43,0,8,0 %; ! Subtype macro PKB$PS_RESNAM_P = 44,0,32,1 %; ! Pointer to resource ! The resource name macro PKB$T_RESNAM = 48,0,0,0 %; literal PKB$S_RESNAM = 32; ! Resource name text macro PKB$T_RESNAM_TEXT = 48,0,8,0 %; ! First character of text !*** MODULE $PKRDEF *** ! ! Definitions for Protection Key Register ! literal PKR$M_V = %X'1'; literal PKR$M_WD = %X'2'; literal PKR$M_RD = %X'4'; literal PKR$M_XD = %X'8'; literal PKR$M_MBZ0 = %X'F0'; literal PKR$M_KEY = %X'FFFFFF00'; literal PKR$M_MBZ1 = %X'FFFFFFFF00000000'; literal PKR$S_PKR = 8; macro PKR$R_PKR_UNION = 0,0,0,0 %; literal PKR$S_PKR_UNION = 8; macro PKR$Q_PROTECTION_KEY = 0,0,0,0 %; literal PKR$S_PROTECTION_KEY = 8; macro PKR$V_V = 0,0,1,0 %; ! Valid macro PKR$V_WD = 0,1,1,0 %; ! Write disable macro PKR$V_RD = 0,2,1,0 %; ! Read diable macro PKR$V_XD = 0,3,1,0 %; ! Execute disable macro PKR$V_MBZ0 = 0,4,4,0 %; literal PKR$S_MBZ0 = 4; ! Reserved PKR{7:4} (MBZ) macro PKR$V_KEY = 0,8,24,0 %; literal PKR$S_KEY = 24; ! Protection key macro PKR$V_MBZ1 = 4,0,32,0 %; literal PKR$S_MBZ1 = 32; ! Reserved PKR{63:32} (MBZ) literal PKR$C_SIZE = 16; ! Number of protection key registers ! ! Definitions for the keys and the registers reserved to load the keys ! literal PKR$C_DEF_KEY = 0; ! the default or ignore key value literal PKR$C_FOE_KEY = 1; ! the Fault On Execution key value literal PKR$C_MAX_USED_KEY = 1; ! max used key value literal PKR$C_DEF_REG = 0; ! the PK register for the default key literal PKR$C_FOE_REG = 1; ! the PK register for the FOE key literal PKR$C_MAX_USED_REG = 1; ! max used register number !*** MODULE $PKTADEF *** literal PKTA$M_TM_ACTIVE = %X'1'; literal PKTA$M_AVOID_PREEMPT = %X'2'; literal PKTA$M_IMF_PENDING = %X'4'; literal PKTA$M_EVENT_NO_FLAG = %X'1'; literal PKTA$S_PKTA = 336; macro PKTA$Q_TM_FLAGS = 0,0,0,0 %; literal PKTA$S_TM_FLAGS = 8; ! Threads manager flags macro PKTA$V_TM_ACTIVE = 0,0,1,0 %; ! Threads manager is active macro PKTA$V_AVOID_PREEMPT = 0,1,1,0 %; ! Try to avoid preemption macro PKTA$V_IMF_PENDING = 0,2,1,0 %; ! IMSEM-free upcall is coming macro PKTA$Q_PERSONA_HANDLE = 8,0,0,0 %; literal PKTA$S_PERSONA_HANDLE = 8; ! Security persona handle macro PKTA$L_PERSONA_ID = 8,0,32,0 %; ! macro PKTA$L_SECURITY_RESERVED = 12,0,32,0 %; ! ! macro PKTA$Q_IEEE_FP_CONTROL = 16,0,0,0 %; literal PKTA$S_IEEE_FP_CONTROL = 8; ! IEEE exceptions control register macro PKTA$Q_AST_ADDRESS = 24,0,0,1 %; literal PKTA$S_AST_ADDRESS = 8; ! User AST routine macro PKTA$Q_IOSA = 24,0,0,0 %; literal PKTA$S_IOSA = 8; ! start of embedded iosa macro PKTA$Q_IOSB = 24,0,0,0 %; literal PKTA$S_IOSB = 8; ! start of embedded iosa macro PKTA$L_IOSA_STATUS = 24,0,32,0 %; ! iosa$l_status macro PKTA$Q_AST_PARAMETER = 32,0,0,0 %; literal PKTA$S_AST_PARAMETER = 8; ! User AST parameter macro PKTA$Q_IOSA_COUNT = 32,0,0,0 %; literal PKTA$S_IOSA_COUNT = 8; ! IOSA$Q_COUNT macro PKTA$Q_AST_THREAD_ID = 40,0,0,0 %; literal PKTA$S_AST_THREAD_ID = 8; ! Target user mode thread ID macro PKTA$Q_IOSA_CONTEXT_Q = 40,0,0,0 %; literal PKTA$S_IOSA_CONTEXT_Q = 8; ! IOSA$Q_CONTEXT_Q macro PKTA$Q_POSTEF = 48,0,0,0 %; literal PKTA$S_POSTEF = 8; ! Posted event flags macro PKTA$Q_IOSA_CONTEXT_ID = 48,0,0,0 %; literal PKTA$S_IOSA_CONTEXT_ID = 8; ! IOSA$Q_CONTEXT_ID macro PKTA$Q_THREAD_EVENTS = 56,0,0,0 %; literal PKTA$S_THREAD_EVENTS = 8; ! Other events to be reported to thread manager macro PKTA$V_EVENT_NO_FLAG = 56,0,1,0 %; ! The no-flag event macro PKTA$Q_SW_FEN_U = 64,0,0,0 %; literal PKTA$S_SW_FEN_U = 8; ! Don't use for other flags because of synchronization macro PKTA$Q_FP_RESTORE_AREA = 72,0,0,0 %; literal PKTA$S_FP_RESTORE_AREA = 8; ! Pointer to register save area to restore FP regs from ! It should be ponter_quad (FLOAT), but I don't think SDL understands that. macro PKTA$Q_RPCC_64_CONTEXT = 80,0,0,0 %; literal PKTA$S_RPCC_64_CONTEXT = 8; ! Context to allow returning a 64-bit time value with SYS$RPCC_64 macro PKTA$Q_UW_SPARE_1 = 88,0,0,0 %; literal PKTA$S_UW_SPARE_1 = 8; macro PKTA$Q_UW_SPARE_2 = 96,0,0,0 %; literal PKTA$S_UW_SPARE_2 = 8; macro PKTA$Q_KTB = 104,0,0,1 %; literal PKTA$S_KTB = 8; ! Address of KTB for this thread macro PKTA$L_PID = 112,0,32,0 %; ! PID for this thread macro PKTA$L_EPID = 116,0,32,0 %; ! EPID for this thread macro PKTA$Q_PHD = 120,0,0,1 %; literal PKTA$S_PHD = 8; ! Address of PHD macro PKTA$Q_KSTACK_BASE = 128,0,0,1 %; literal PKTA$S_KSTACK_BASE = 8; ! Kstack base address macro PKTA$Q_STACK = 136,0,0,1 %; literal PKTA$S_STACK = 32; ! STACK pointer array macro PKTA$Q_STACKLIM = 168,0,0,1 %; literal PKTA$S_STACKLIM = 32; ! STACK limit pointer macro PKTA$Q_FRED = 200,0,0,1 %; literal PKTA$S_FRED = 8; ! Address of FRED macro PKTA$Q_REGSTACK = 208,0,0,1 %; literal PKTA$S_REGSTACK = 32; ! Register stack pointer array macro PKTA$Q_REGSTACKLIM = 240,0,0,1 %; literal PKTA$S_REGSTACKLIM = 32; ! Register stack limit array macro PKTA$Q_STACK_PEAK = 272,0,0,0 %; literal PKTA$S_STACK_PEAK = 32; ! Memory stack peak array macro PKTA$Q_REGSTACK_PEAK = 304,0,0,0 %; literal PKTA$S_REGSTACK_PEAK = 32; ! Register stack peak array literal PKTA$S_URUW = 104; ! Length URUW section literal PKTA$S_UREW = 232; ! Length UREW section literal PKTA$C_LENGTH = 336; ! Length PKTA literal PKTA$K_LENGTH = 336; ! Length PKTA literal PKTA$S_PKTADEF = 336; ! Old size name - synonym !*** MODULE $PBDEF *** ! + ! PB - SCS PATH BLOCK ! ! THE PB HAS INFORMATION ABOUT THE PHYSICAL PATH TO ANOTHER ! SYSTEM IN A CLUSTER. PATH BLOCKS TO THE SAME SYSTEM ARE ! LINKED TOGETHER TO THE SYSTEM BLOCK (SB). ! - literal PB$C_CLOSED = 0; ! NEWLY CREATED PATHBLOCK literal PB$C_ST_SENT = 1; ! START SENT literal PB$C_ST_REC = 2; ! START RECEIVED literal PB$C_OPEN = 3; ! OPEN PORT-PORT VIRTUAL CIRCUIT ! CI port virtual circuit failure states literal PB$C_STALL_SETCKT = 4; ! SETCKT stalled by pool problem literal PB$C_CLOSE_CKT = 5; ! SETCKT in progress literal PB$C_NOTIFY_VCFAIL = 6; ! SYSAP notification for failed VC in progress literal PB$C_STALL_CACHE = 7; ! Cache Clear stalled by pool problem literal PB$C_CACHE_CLEAR = 8; ! Cache Clear in progress literal PB$C_NOTIFY_PWFAIL = 9; ! SYSAP notification for failed port in progress ! literal PB$C_VC_FAIL = 32768; ! VC FAILURE IN PROGRESS STATE (No longer used for CI) literal PB$C_PWR_FAIL = 16384; ! PWR FAIL RECOVERY IN PROGRESS STATE (No longer used for CI) literal PB$M_DUALPATH = %X'80000000'; literal PB$C_CI780 = 2; ! CI780 PORT literal PB$C_CI750 = 2; ! CI750 PORT (=CI780) literal PB$C_HSC = 4; ! HSC PORT literal PB$C_KL10 = 6; ! KLIPA PORT literal PB$C_CINT = 7; ! CI NODE TESTER literal PB$C_NI = 8; ! NI-SCA (LAVC) PORT literal PB$C_PS = 9; ! PASSTHRU PORT literal PB$C_BCA = 11; ! BI-CI PORT literal PB$C_BVPSSP = 12; ! BVP STORAGE PORT literal PB$C_BVPNI = 13; ! BVP NI PORT literal PB$C_CIXCD = 14; ! XMI-CI PORT CIXCD literal PB$C_CIXCDAC = 16; ! XMI-CI N_PORT ALPHA CIXCD literal PB$C_CITCA = 17; literal PB$C_CIPCA = 18; literal PB$C_MC = 19; literal PB$C_SMCI = 20; literal PB$C_SII = 32; literal PB$C_KFQSA = 33; literal PB$C_SHAC = 34; literal PB$C_XON = 35; literal PB$C_SWIFT = 36; literal PB$C_KFMSA = 37; literal PB$C_N710 = 38; literal PB$C_KFMSB = 39; literal PB$C_RF70 = 48; literal PB$C_RF71 = 48; literal PB$C_RF30 = 49; literal PB$C_RF31 = 50; literal PB$C_RF72 = 51; literal PB$C_RF32 = 52; literal PB$C_RF73 = 53; literal PB$C_RF31F = 54; literal PB$C_RF35 = 55; literal PB$C_RF36 = 58; literal PB$C_RF37 = 59; literal PB$C_RF74 = 60; literal PB$C_RF75 = 61; literal PB$C_TF70 = 64; literal PB$C_TF30 = 65; literal PB$C_TF85 = 65; literal PB$C_TF86 = 66; literal PB$C_HSJ = 80; literal PB$C_HSD = 81; literal PB$C_HSF = 82; literal PB$C_HSJ80 = 83; literal PB$C_EF51 = 96; literal PB$C_EF52 = 97; literal PB$C_EF53 = 98; literal PB$C_EF54 = 99; literal PB$C_EF58 = 100; literal PB$M_SRSNTDATWM = %X'80'; literal PB$M_MAINT = %X'1'; literal PB$C_UNINIT = 0; ! UNINITIALIZED, literal PB$C_DISAB = 1; ! DISABLED literal PB$C_ENAB = 2; ! ENABLED ! literal PB$M_CUR_CBL = %X'1'; literal PB$M_CUR_PS = %X'1'; literal PB$M_TIM = %X'1'; literal PB$M_VCCHK_ENB = %X'2'; literal PB$M_SCS_EXP = %X'4'; literal PB$M_NEW_MSG = %X'8'; literal PB$M_UNUSED = %X'10'; literal PB$M_CREDIT = %X'20'; literal PB$M_DISC = %X'40'; literal PB$M_STORAGE = %X'80'; literal PB$M_CLONE = %X'100'; literal PB$C_SMCI_LOAD_CLASS = 2147483647; ! SMCI Load Class literal PB$C_MC_LOAD_CLASS = 800; ! Memory Channel Load Class literal PB$C_CI_LOAD_CLASS = 140; ! CI Load Class literal PB$C_DSSI_LOAD_CLASS = 48; ! DSSI Load Class literal PB$C_NI_LOAD_CLASS = 10; ! NI Default Load Class literal PB$K_LENGTH = 172; ! LENGTH OF A PATH BLOCK literal PB$C_LENGTH = 172; ! LENGTH OF A PATH BLOCK literal PB$S_PBDEF = 172; ! Old size name - synonym literal PB$S_PB = 172; macro PB$L_FLINK = 0,0,32,1 %; ! FWD LINK TO NEXT PB macro PB$L_BLINK = 4,0,32,1 %; ! BACK LINK TO PREVIOUS PB macro PB$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro PB$B_TYPE = 10,0,8,0 %; ! SCS STRUCTURE TYPE macro PB$B_SUBTYP = 11,0,8,0 %; ! SCS STRUCT SUBTYPE FOR PB macro PB$B_RSTATION = 12,0,0,0 %; literal PB$S_RSTATION = 6; ! REMOTE STATION ADDRESS macro PB$W_STATE = 18,0,16,0 %; ! PATH STATE ! STATE DEFINITIONS: ! 0 ORIGIN, INCREMENTS OF 1 macro PB$L_RPORT_TYP = 20,0,32,0 %; ! HARDWARE PORT TYPE CODE macro PB$V_PORT_TYP = 20,0,31,0 %; literal PB$S_PORT_TYP = 31; ! HARDWARE PORT TYPE, macro PB$V_DUALPATH = 20,31,1,0 %; ! 0/1 FOR SINGLE PATH/DUAL PATH PORT macro PB$L_RPORT_REV = 24,0,32,0 %; ! REMOTE PORT HW REV LEVEL macro PB$V_RPORT_REV_SPARE = 24,0,30,0 %; literal PB$S_RPORT_REV_SPARE = 30; ! Spare macro PB$V_RPORT_SPC_REV = 24,30,1,0 %; ! 0 = -A / 1 = -B macro PB$V_RPORT_REV_RESV1 = 24,31,1,0 %; ! Reserved macro PB$L_RPORT_FCN = 28,0,32,0 %; ! REMOTE PORT FUNCTION MASK macro PB$V_MBZ = 28,0,7,0 %; literal PB$S_MBZ = 7; ! reserved MBZ macro PB$V_SRSNTDATWM = 28,7,1,0 %; ! Send/Rec SNTDATWM (*not* in CI Port Arch) macro PB$B_RST_PORT = 32,0,8,0 %; ! OWNING PORT WHICH RESET REMOTE PORT macro PB$B_RSTATE = 33,0,8,0 %; ! REMOTE PORT STATUS: macro PB$V_MAINT = 33,0,1,0 %; ! 0/1 FOR MAINTENANCE MODE NO/YES macro PB$V_STATE = 33,1,2,0 %; literal PB$S_STATE = 2; ! REMOTE PORT STATE: ! DEFINE REMOTE STATES, 0 ORIGIN macro PB$W_RETRY = 34,0,16,0 %; ! START HANDSHAKE RETRY COUNT macro PB$T_LPORT_NAME = 36,0,32,0 %; literal PB$S_LPORT_NAME = 4; ! LOCAL PORT DEVICE NAME macro PB$B_CBL_STS = 40,0,8,0 %; ! CABLE STATUS TO THE REMOTE macro PB$V_CUR_CBL = 40,0,1,0 %; ! 1/0 FOR CURRENT STATUS OK/BAD macro PB$B_P0_STS = 41,0,8,0 %; ! PATH 0 STATUS macro PB$B_P1_STS = 42,0,8,0 %; ! PATH 1 STATUS macro PB$V_CUR_PS = 42,0,1,0 %; ! 1/0 FOR CURRENT STATUS OK/BROKEN macro PB$L_PDT = 44,0,32,1 %; ! ADDR OF PORT DESCRIPTOR TABLE FOR ! LOCAL PORT macro PB$L_SBLINK = 48,0,32,1 %; ! LINK TO SYSTEM BLOCK macro PB$L_CDTLST = 52,0,32,1 %; ! LINK TO FIRST CDT OVER THIS PATH ! (0 IF NO CDT'S) macro PB$L_WAITQFL = 56,0,32,1 %; ! SCS SEND MSG WAIT QUEUE FLINK macro PB$L_WAITQBL = 60,0,32,1 %; ! SCS SEND MSG WAIT QUEUE BLINK macro PB$L_DUETIME = 60,0,32,0 %; ! START HANDSHAKE TIMER macro PB$L_SCSMSG = 64,0,32,1 %; ! ADDR OF SCS MESSAGE BUFFER macro PB$W_STS = 68,0,16,0 %; ! PATH BLOCK STATUS macro PB$V_TIM = 68,0,1,0 %; ! HANDSHAKE TIMEOUT IN PROGRESS macro PB$V_VCCHK_ENB = 68,1,1,0 %; ! VC timeout checking enabled macro PB$V_SCS_EXP = 68,2,1,0 %; ! SCS message expected during timeout period macro PB$V_NEW_MSG = 68,3,1,0 %; ! New message arrived during timeout period macro PB$V_UNUSED = 68,4,1,0 %; ! Unused bit macro PB$V_CREDIT = 68,5,1,0 %; ! SCS receive credit on free queue macro PB$V_DISC = 68,6,1,0 %; ! SCS disconnect request is in progress macro PB$V_STORAGE = 68,7,1,0 %; ! Storage only port (A DSSA port) macro PB$V_CLONE = 68,8,1,0 %; ! Clone (duplicate) node detected macro PB$W_VCFAIL_RSN = 70,0,16,0 %; ! VC FAILURE REASON (VMS ! STATUS CODE macro PB$B_PROTOCOL = 72,0,8,0 %; ! PPD PROTOCOL LEVEL macro PB$L_RPORT_MULT = 76,0,32,0 %; ! LARGEST PACKET MULTIPLE OF THE REMOTE PORT (CI ONLY) ! SHIFTED TO BIT POSITION <30:28> macro PB$L_TIME_STAMP = 80,0,32,0 %; ! (TYC 9-Mar-89) PB INSERTION TO CONFIG. DB TIME STAMP macro PB$L_SHARE_FLINK = 84,0,32,1 %; ! (TYC 15-Feb-89) FWD LINK TO NEXT PB IN LOAD SHARE QUEUE macro PB$L_SHARE_BLINK = 88,0,32,1 %; ! (TYC 15-Feb-89) BACK LINK TO PREVIOUS PB IN LOAD SHARE QUEUE macro PB$L_LOAD_CLASS = 92,0,32,1 %; ! VC's Load class - set by port to indicate ! max performance of underlying hardware. ! Interconnect load class values (Raw HW BW in Mb/S): macro PB$L_VC_COST = 92,0,32,0 %; ! Load Sharing Cost for this Virtual Circuit (to be removed) macro PB$L_PRIORITY = 96,0,32,1 %; ! VC's current priority for connection selection, ! Includes both PB$ & PDT$ management priorities macro PB$L_MGT_PRIORITY = 100,0,32,1 %; ! Management priority value assigned to this VC. macro PB$L_VC_ADDR = 104,0,32,0 %; ! Address of Interconnect specific VC state block ! (eg: a PEdriver VC$ structure). SBZ if port doesn't have any. macro PB$T_LPORT_NAME_ALIAS = 116,0,0,0 %; literal PB$S_LPORT_NAME_ALIAS = 16; ! copy of LOCAL PORT DEVICE NAME ! ! Tracing cells ! macro PB$L_CONT_ID = 132,0,32,0 %; ! Current continuation ID mask ! Trace buffer address. ! 0 - tracing deselected for this pb ! 1 - trace buffer to be allocated ! other - allocated and selected macro PB$A_TRACE_BUFFER = 136,0,32,0 %; ! Trace buffer adddress ! Debug fields macro PB$L_DBG0 = 140,0,32,0 %; macro PB$L_DBG1 = 144,0,32,0 %; macro PB$L_DBG2 = 148,0,32,0 %; macro PB$L_DBG3 = 152,0,32,0 %; macro PB$L_DBG4 = 156,0,32,0 %; macro PB$L_DBG5 = 160,0,32,0 %; macro PB$L_DBG6 = 164,0,32,0 %; macro PB$L_DBG7 = 168,0,32,0 %; !*** MODULE $PBHDEF *** ! + ! DEFINE PERFORMANCE BUFFER HEADER ! - literal PBH$K_START = 13; ! START OF DATA AREA literal PBH$C_START = 13; ! START OF DATA AREA literal PBH$K_LENGTH = 512; ! LENGTH OF PERFORMANCE DATA BUFFER literal PBH$C_LENGTH = 512; ! LENGTH OF PERFORMANCE DATA BUFFER literal PBH$S_PBHDEF = 512; literal PBH$S_PBH = 512; macro PBH$L_BUFRFL = 0,0,32,1 %; ! BUFFER FORWARD LINK macro PBH$L_BUFRBL = 4,0,32,1 %; ! BUFFER BACKWARD LINK macro PBH$W_SIZE = 8,0,16,0 %; ! SIZE OF PERFORMANCE DATA BUFFER macro PBH$B_TYPE = 10,0,8,0 %; ! DATA STRUCTURE TYPE macro PBH$W_MSGCNT = 11,0,16,0 %; ! COUNT OF MESSAGES IN BUFFER !*** MODULE $PBODEF *** ! + ! PBO - SCS$CONFIG_PTH CALL OUTPUT ARRAY FORMAT ! ! THE OUTPUT ARRAY RETURNED FROM THE SCS$CONFIG_PTH CALL. DATA IS MOSTLY COPIED ! FROM THE PATH BLOCK (PB) BEING LOOKED UP. ! - literal PBO$M_SRSNTDATWM = %X'80'; literal PBO$C_NXT_VC = 32; ! SPECIFIER OF NEXT VC (PB) literal PBO$K_NXT_VC = 32; ! TO THIS SYSTEM (12 BYTE ! SPECIFIER FOLLOWS:) literal PBO$C_LENGTH = 52; ! LENGTH OF PBO literal PBO$K_LENGTH = 52; ! LENGTH OF PBO literal PBO$S_PBODEF = 52; ! Old size name - synonym literal PBO$S_PBO = 52; macro PBO$B_RSTATION = 0,0,0,0 %; literal PBO$S_RSTATION = 6; ! REMOTE STATION ADDR macro PBO$W_STATE = 6,0,16,0 %; ! PATH STATE macro PBO$L_RPORT_TYP = 8,0,32,0 %; ! REMOTE PORT HW PORT TYPE macro PBO$L_RPORT_REV = 12,0,32,0 %; ! REMOTE PORT REV LEVEL macro PBO$L_RPORT_FCN = 16,0,32,0 %; ! REMOTE PORT FUNCTION MASK macro PBO$V_MBZ = 16,0,7,0 %; literal PBO$S_MBZ = 7; ! reserved MBZ macro PBO$V_SRSNTDATWM = 16,7,1,0 %; ! Send/Rec SNTDATWM (*not* in CI Port Arch) macro PBO$B_RST_PORT = 20,0,8,0 %; ! OWNING PORT WHICH LAST ! RESET THIS REMOTE macro PBO$B_RSTATE = 21,0,8,0 %; ! REMOTE PORT STATE macro PBO$W_RETRY = 22,0,16,0 %; ! START HANDSHAKE RETRIES LEFT macro PBO$T_LPORT_NAME = 24,0,32,0 %; literal PBO$S_LPORT_NAME = 4; ! LOCAL PORT DEVICE NAME macro PBO$B_CBL_STS = 28,0,8,0 %; ! CURRENT CABLE STATUS macro PBO$B_P0_STS = 29,0,8,0 %; ! PATH 0 STATUS macro PBO$B_P1_STS = 30,0,8,0 %; ! PATH 1 STATUS macro PBO$B_NXT_RSTAT = 32,0,0,0 %; literal PBO$S_NXT_RSTAT = 6; ! REMOTE STATION ADDR macro PBO$T_NXT_LPORT = 40,0,32,0 %; literal PBO$S_NXT_LPORT = 4; ! LOCAL PORT NAME ON NXT PB macro PBO$B_SYSTEMID = 44,0,0,0 %; literal PBO$S_SYSTEMID = 6; ! ID OF SYSTEM ASSOC WITH ! THIS PB !*** MODULE $PCIDEF *** ! ! ! ============================================================================ ! PCI Type-0 Configuration Space ! ============================================================================ ! literal PCI$K_VENDOR_ID = 0; literal PCI$K_DEVICE_ID = 2; literal PCI$K_COMMAND = 4; literal PCI$M_IO_ENABLE = %X'1'; literal PCI$M_MEM_ENABLE = %X'2'; literal PCI$M_BUS_MASTER_ENABLE = %X'4'; literal PCI$M_SPECIAL_CYCLE_ENABLE = %X'8'; literal PCI$M_INVAL_ENABLE = %X'10'; literal PCI$M_PALETTE_SNOOP_ENABLE = %X'20'; literal PCI$M_PARITY_ENABLE = %X'40'; literal PCI$M_WAIT_CYCLE_ENABLE = %X'80'; literal PCI$M_SERR_ENABLE = %X'100'; literal PCI$M_BACK_TO_BACK_ENABLE = %X'200'; literal PCI$M_INT_DISABLE = %X'400'; literal PCI$K_STATUS = 6; literal PCI$M_INT_STATUS = %X'8'; literal PCI$M_CAP_LIST = %X'10'; literal PCI$M_SPEED_66MHZ = %X'20'; literal PCI$M_RSVD_1 = %X'40'; literal PCI$M_FAST_BB_CAPABLE = %X'80'; literal PCI$M_DATA_PARITY_DETECT = %X'100'; literal PCI$M_DEVSEL_TIMING = %X'600'; literal PCI$M_SIGNAL_TARGET_ABORT = %X'800'; literal PCI$M_RCV_TARGET_ABORT = %X'1000'; literal PCI$M_RCV_MASTER_ABORT = %X'2000'; literal PCI$M_SIGNAL_SERR = %X'4000'; literal PCI$M_DETECT_PE = %X'8000'; literal PCI$K_REVISION_ID = 8; literal PCI$K_PROGRAMMING_IF = 9; literal PCI$K_SUB_CLASS = 10; literal PCI$K_BASE_CLASS = 11; literal PCI$K_CACHE_LINE_SIZE = 12; literal PCI$K_LATENCY_TIMER = 13; literal PCI$K_HEADER_TYPE = 14; literal PCI$K_BIST = 15; literal PCI$K_BASE_ADDRESS_0 = 16; literal PCI$K_BASE_ADDRESS_1 = 20; literal PCI$K_BASE_ADDRESS_2 = 24; literal PCI$K_BASE_ADDRESS_3 = 28; literal PCI$K_BASE_ADDRESS_4 = 32; literal PCI$K_BASE_ADDRESS_5 = 36; literal PCI$K_CARDBUS_CIS = 40; literal PCI$K_SUB_VNDR = 44; literal PCI$K_SUB_ID = 46; literal PCI$K_EXP_ROM_BASE = 48; literal PCI$K_CAPABILITIES_POINTER = 52; literal PCI$K_INTR_LINE = 60; literal PCI$K_INTR_PIN = 61; literal PCI$K_MIN_GNT = 62; literal PCI$K_MAX_LAT = 63; literal PCI$S_PCIDEF = 64; ! Old PCI size for compatibility ! The following constants apply to the DEVSEL timing field in the STATUS register literal PCI$K_DEVSEL_FAST = 0; literal PCI$K_DEVSEL_MEDIUM = 1; literal PCI$K_DEVSEL_SLOW = 2; ! The following constants apply to the BASE_CLASS byte literal PCI$K_NOT_IMPLEMENTED = 0; literal PCI$K_MASS_STORAGE_CTRLR = 1; literal PCI$K_NETWORK_CTRLR = 2; literal PCI$K_DISPLAY_CTRLR = 3; literal PCI$K_MULTIMEDIA_DEVICE = 4; literal PCI$K_MEMORY_CTRLR = 5; literal PCI$K_BRIDGE_DEVICE = 6; literal PCI$K_UNDEFINED = 255; ! The following sub class definitions apply to the Mass Storage Base Class literal PCI$K_SCSI_CTRLR = 0; literal PCI$K_IDE_CTRLR = 1; literal PCI$K_FLOPPY_CTRLR = 2; literal PCI$K_IPI_CTRLR = 3; literal PCI$K_OTHER_MASS_STORAGE = 80; ! The following sub class definitions apply to the Network Controller Base Class literal PCI$K_NI_CTRLR = 0; literal PCI$K_TOKEN_CTRLR = 1; literal PCI$K_FDDI_CTRLR = 2; literal PCI$K_OTHER_NETWORK = 80; ! The following sub class definitions apply to the Display Controller Base Class literal PCI$K_VGA_CTRLR = 0; literal PCI$K_XGA_CTRLR = 1; literal PCI$K_OTHER_DISPLAY = 80; ! The following sub class definitions apply to the Multimedia Device Base Class literal PCI$K_VIDEO_CTRLR = 0; literal PCI$K_AUDIO_CTRLR = 1; literal PCI$K_OTHER_MULTIMEDIA = 80; ! The following sub class definitions apply to the Memory Controller Base Class literal PCI$K_RAM = 0; literal PCI$K_FLASH = 1; literal PCI$K_OTHER_MEMORY = 80; ! The following sub class definitions apply to the Bridge Device Base Class literal PCI$K_HOST_BRIDGE = 0; literal PCI$K_ISA_BRIDGE = 1; literal PCI$K_EISA_BRIDGE = 2; literal PCI$K_MC_BRIDGE = 3; literal PCI$K_PCI_PCI_BRIDGE = 4; literal PCI$K_PCMCIA_BRIDGE = 5; literal PCI$K_OTHER_BRIDGE = 80; ! The following constants apply to the Interrupt Pin byte literal PCI$K_INTR_PIN_NOT_USED = 0; literal PCI$K_INTR_PIN_INTA = 1; literal PCI$K_INTR_PIN_INTB = 2; literal PCI$K_INTR_PIN_INTC = 3; literal PCI$K_INTR_PIN_INTD = 4; literal PCI$K_MAX_DEVICES = 32; literal PCI$K_LENGTH = 64; literal PCI$S_PCI = 64; macro PCI$W_VENDOR_ID = 0,0,16,1 %; macro PCI$W_DEVICE_ID = 2,0,16,1 %; macro PCI$W_COMMAND = 4,0,16,1 %; macro PCI$V_IO_ENABLE = 4,0,1,0 %; ! 0 macro PCI$V_MEM_ENABLE = 4,1,1,0 %; ! 1 macro PCI$V_BUS_MASTER_ENABLE = 4,2,1,0 %; ! 2 macro PCI$V_SPECIAL_CYCLE_ENABLE = 4,3,1,0 %; ! 3 macro PCI$V_INVAL_ENABLE = 4,4,1,0 %; ! 4 macro PCI$V_PALETTE_SNOOP_ENABLE = 4,5,1,0 %; ! 5 macro PCI$V_PARITY_ENABLE = 4,6,1,0 %; ! 6 macro PCI$V_WAIT_CYCLE_ENABLE = 4,7,1,0 %; ! 7 macro PCI$V_SERR_ENABLE = 4,8,1,0 %; ! 8 macro PCI$V_BACK_TO_BACK_ENABLE = 4,9,1,0 %; ! 9 macro PCI$V_INT_DISABLE = 4,10,1,0 %; ! 10 PCI Spec V2.3 macro PCI$W_STATUS = 6,0,16,1 %; macro PCI$V_INT_STATUS = 6,3,1,0 %; ! 3 macro PCI$V_CAP_LIST = 6,4,1,0 %; ! 4 macro PCI$V_SPEED_66MHZ = 6,5,1,0 %; ! 5 macro PCI$V_RSVD_1 = 6,6,1,0 %; ! 6 macro PCI$V_FAST_BB_CAPABLE = 6,7,1,0 %; ! 7 macro PCI$V_DATA_PARITY_DETECT = 6,8,1,0 %; ! 8 macro PCI$V_DEVSEL_TIMING = 6,9,2,0 %; literal PCI$S_DEVSEL_TIMING = 2; ! 10:9 macro PCI$V_SIGNAL_TARGET_ABORT = 6,11,1,0 %; ! 11 macro PCI$V_RCV_TARGET_ABORT = 6,12,1,0 %; ! 12 macro PCI$V_RCV_MASTER_ABORT = 6,13,1,0 %; ! 13 macro PCI$V_SIGNAL_SERR = 6,14,1,0 %; ! 14 macro PCI$V_DETECT_PE = 6,15,1,0 %; ! 15 macro PCI$B_REVISION_ID = 8,0,8,1 %; macro PCI$B_PROGRAMMING_IF = 9,0,8,1 %; macro PCI$B_SUB_CLASS = 10,0,8,1 %; macro PCI$B_BASE_CLASS = 11,0,8,1 %; macro PCI$B_CACHE_LINE_SIZE = 12,0,8,1 %; macro PCI$B_LATENCY_TIMER = 13,0,8,1 %; macro PCI$B_HEADER_TYPE = 14,0,8,1 %; macro PCI$B_BIST = 15,0,8,1 %; macro PCI$L_BASE_ADDRESS_0 = 16,0,32,1 %; macro PCI$L_BASE_ADDRESS_1 = 20,0,32,1 %; macro PCI$L_BASE_ADDRESS_2 = 24,0,32,1 %; macro PCI$L_BASE_ADDRESS_3 = 28,0,32,1 %; macro PCI$L_BASE_ADDRESS_4 = 32,0,32,1 %; macro PCI$L_BASE_ADDRESS_5 = 36,0,32,1 %; macro PCI$L_CARDBUS_CIS = 40,0,32,1 %; macro PCI$W_SUB_VNDR = 44,0,16,1 %; macro PCI$W_SUB_ID = 46,0,16,1 %; macro PCI$L_EXP_ROM_BASE = 48,0,32,1 %; macro PCI$B_CAPABILITIES_POINTER = 52,0,8,1 %; macro PCI$L_RESERVED_3 = 52,0,32,1 %; macro PCI$L_RESERVED_4 = 56,0,32,1 %; macro PCI$B_INTR_LINE = 60,0,8,1 %; macro PCI$B_INTR_PIN = 61,0,8,1 %; macro PCI$B_MIN_GNT = 62,0,8,1 %; macro PCI$B_MAX_LAT = 63,0,8,1 %; ! ! ! ============================================================================ ! PCI Capabilities Identifiers ! ============================================================================ ! These constants apply to the CAPABILITIES field identified by the ! CAPABILITIES POINTER. For more details, see Appendix H of the ! PCI 3.0 spec. ! literal PCI$K_PMI_CAP = 1; ! 1 Power Management Interface literal PCI$K_AGP_CAP = 2; ! 2 see http://www.agpforum.org literal PCI$K_VPD_CAP = 3; ! 3 see sec. 6.4 of PCI 2.3 spec literal PCI$K_SID_CAP = 4; ! 4 Slot ID, see PPB spec literal PCI$K_MSI_CAP = 5; ! 5 see sec. 6.8 of PCI 2.3 spec literal PCI$K_PHS_CAP = 6; ! 6 see http://www.picmg.org literal PCI$K_PCIX_CAP = 7; ! 7 see PCI-X addendum literal PCI$K_AMD_CAP = 8; ! 8 reserved for AMD literal PCI$K_VSID_CAP = 9; ! 9 Vendor-specific literal PCI$K_DBG_CAP = 10; ! A Debug port literal PCI$K_CRC_CAP = 11; ! B see http://www.picmg.org literal PCI$K_HP_CAP = 12; ! C Hot Plug Controller literal PCI$K_PPB_VID = 13; ! D PCI-PCI Bridge Subsystem Vendor ID literal PCI$K_AGP_8X = 14; ! E see http://www.agpforum.org literal PCI$K_SECURE_CAP = 15; ! F secure device literal PCI$K_PCIE_CAP = 16; ! 10 PCI Express literal PCI$K_MSIX_CAP = 17; ! 11 MSI-X Capability ! ! ! ============================================================================ ! Base Address Register ! ============================================================================ ! literal PCI$M_BASE_ADDRESS_MEM_IO = %X'1'; literal PCI$M_BASE_ADDRESS_TYPE = %X'6'; literal PCI$M_BASE_ADDRESS_PREFETCHABLE = %X'8'; literal PCI$M_BASE_ADDRESS_BITS_31_4 = %X'FFFFFFF0'; literal PCI$S_BASE_ADDRESS = 4; macro PCI$L_BASE_ADDRESS = 0,0,32,1 %; macro PCI$V_BASE_ADDRESS_MEM_IO = 0,0,1,0 %; macro PCI$V_BASE_ADDRESS_TYPE = 0,1,2,0 %; literal PCI$S_BASE_ADDRESS_TYPE = 2; macro PCI$V_BASE_ADDRESS_PREFETCHABLE = 0,3,1,0 %; macro PCI$V_BASE_ADDRESS_BITS_31_4 = 0,4,28,0 %; literal BASE_ADDR_32 = 0; literal BASE_ADDR_BELOW_1MB = 1; literal BASE_ADDR_64 = 2; literal BASE_ADDR_RESERVED = 3; ! ! ! ============================================================================ ! PCI_NODE_NUMBER ! ============================================================================ ! literal PCI$M_PCI_NODE_NUMBER_FUNCTION = %X'7'; literal PCI$M_PCI_NODE_NUMBER_DEVICE = %X'F8'; literal PCI$M_PCI_NODE_NUMBER_BUS = %X'FF00'; literal PCI$M_PCI_NODE_NUMBER_OFFSET = %X'FFFF0000'; literal PCI$S_PCI_NODE_NUMBER = 8; macro PCI$Q_PCI_NODE_NUMBER_Q = 0,0,0,1 %; literal PCI$S_PCI_NODE_NUMBER_Q = 8; macro PCI$L_PCI_NODE_NUMBER_L = 0,0,32,1 %; macro PCI$L_PCI_NODE_NUMBER = 0,0,32,1 %; macro PCI$L_PCI_NODE_NUMBER_H = 4,0,32,1 %; macro PCI$V_PCI_NODE_NUMBER_FUNCTION = 0,0,3,0 %; literal PCI$S_PCI_NODE_NUMBER_FUNCTION = 3; macro PCI$V_PCI_NODE_NUMBER_DEVICE = 0,3,5,0 %; literal PCI$S_PCI_NODE_NUMBER_DEVICE = 5; macro PCI$V_PCI_NODE_NUMBER_BUS = 0,8,8,0 %; literal PCI$S_PCI_NODE_NUMBER_BUS = 8; macro PCI$V_PCI_NODE_NUMBER_OFFSET = 0,16,16,0 %; literal PCI$S_PCI_NODE_NUMBER_OFFSET = 16; macro PCI$V_PCI_NODE_NUMBER_SEGMENT = 4,0,16,0 %; literal PCI$S_PCI_NODE_NUMBER_SEGMENT = 16; macro PCI$V_PCI_NODE_NUMBER_RESERVED = 4,16,16,0 %; literal PCI$S_PCI_NODE_NUMBER_RESERVED = 16; ! ! ! ============================================================================ ! Hardware ID field ! ============================================================================ ! literal PCI$S_PCI_BUSARRAY_HARDWARE_ID = 8; macro PCI$Q_PCI_HARDWARE_ID = 0,0,0,1 %; literal PCI$S_PCI_HARDWARE_ID = 8; macro PCI$W_PCI_HARDWARE_ID_VENDOR = 0,0,16,1 %; macro PCI$W_PCI_HARDWARE_ID_DEVICE = 2,0,16,1 %; macro PCI$W_PCI_HARDWARE_ID_SUB_VNDR = 4,0,16,1 %; macro PCI$W_PCI_HARDWARE_ID_SUB_ID = 6,0,16,1 %; ! ! ! ============================================================================ ! PCIERR Structure ! ============================================================================ ! literal PCIERR$K_LENGTH = 72; literal PCIERR$S_PCIERR = 72; macro PCIERR$V_DEVICE_NUMBER = 0,11,5,0 %; literal PCIERR$S_DEVICE_NUMBER = 5; macro PCIERR$B_BUS_NUMBER = 2,0,8,0 %; macro PCIERR$L_FRAME_SIZE = 4,0,32,0 %; macro PCIERR$R_PCI = 8,0,0,0 %; literal PCIERR$S_PCI = 64; ! ! ! ============================================================================ ! PCIFLAGS structure ! ============================================================================ ! literal PCIFLAGS$M_FILL1 = %X'FFFFFF00'; literal PCIFLAGS$M_DATA_PARITY_DETECT = %X'1'; literal PCIFLAGS$M_SIGNAL_TARGET_ABORT = %X'2'; literal PCIFLAGS$M_RCV_TARGET_ABORT = %X'4'; literal PCIFLAGS$M_RCV_MASTER_ABORT = %X'8'; literal PCIFLAGS$M_SIGNAL_SERR = %X'10'; literal PCIFLAGS$M_DETECT_PE = %X'20'; literal PCIFLAGS$M_FILL2 = %X'C0'; literal PCIFLAGS$M_FILL3 = %X'FFFFFF00'; literal PCIFLAGS$S_PCIFLAGS = 4; macro PCIFLAGS$B_PCIFLAGS = 0,0,8,0 %; macro PCIFLAGS$V_DATA_PARITY_DETECT = 0,0,1,0 %; ! From PCI stat<8> macro PCIFLAGS$V_SIGNAL_TARGET_ABORT = 0,1,1,0 %; ! Same as stat<11:15> macro PCIFLAGS$V_RCV_TARGET_ABORT = 0,2,1,0 %; macro PCIFLAGS$V_RCV_MASTER_ABORT = 0,3,1,0 %; macro PCIFLAGS$V_SIGNAL_SERR = 0,4,1,0 %; macro PCIFLAGS$V_DETECT_PE = 0,5,1,0 %; literal ERRTAG$K_PCIERR = 16; ! ! ! ============================================================================ ! Generic PCI capabilities header fields ! ============================================================================ ! ! See PCI Local Bus Specification Revision 3.0 Section 6.8 ! ! This definition creates constants that are offsets into a PCI Capabiltiy ! block for a given device. These offsets are the same for any Capability ! block. ! ! PCICAP$K_ID - offset to the field containing the ID of this ! capability. ! ! PCICAP$K_NEXT - offset to field contianing the offset into the device's ! PCI Config Space of the next Capability Block. Contains ! zero if this is the last block. ! ! PCICAP$K_CONTROL - offset to the field containing the control word for ! this capability ! literal PCICAP$K_ID = 0; literal PCICAP$K_NEXT = 1; literal PCICAP$K_CONTROL = 2; literal PCICAP$S_PCICAP = 4; macro PCICAP$B_ID = 0,0,8,0 %; macro PCICAP$B_NEXT = 1,0,8,0 %; macro PCICAP$W_CONTROL = 2,0,16,0 %; ! ! ! ============================================================================ ! MSI Control Register definition ! ============================================================================ ! ! See PCI Local Bus Specification Revision 3.0 Section 6.8.2 ! ! msi$v_enable - RW if set, the device will deliver interrupts as MSI. ! ! msi$v_multi_cap - RO encodes the number of vectors requested by this ! device. ! ! msi$v_multi_ena - RW encodes the number of vectors assigned to this ! device by configuration code. ! ! msi$v_addr64_cap - RO if set, the device writes its message to a 64-bit ! physical address. ! ! msi$v_per_vec_cap - RO if set, this device supports per-vector MSI masking ! capability. ! literal MSI$M_ENABLE = %X'1'; literal MSI$M_MULTI_CAP = %X'E'; literal MSI$M_MULTI_ENA = %X'70'; literal MSI$M_ADDR64_CAP = %X'80'; literal MSI$M_PER_VEC_CAP = %X'100'; literal MSI$S_MSI_CONTROL = 2; macro MSI$W_CONTROL = 0,0,16,0 %; macro MSI$V_ENABLE = 0,0,1,0 %; macro MSI$V_MULTI_CAP = 0,1,3,0 %; literal MSI$S_MULTI_CAP = 3; macro MSI$V_MULTI_ENA = 0,4,3,0 %; literal MSI$S_MULTI_ENA = 3; macro MSI$V_ADDR64_CAP = 0,7,1,0 %; macro MSI$V_PER_VEC_CAP = 0,8,1,0 %; ! ! ! ============================================================================ ! Generic MSI ! ============================================================================ ! ! This definition creates constants that are offsets into the MSI PCI ! Capabiltiy block for a given device. ! ! See PCI Local Bus Specification Revision 3.0 Section 6.8.2 ! ! ************** ! * IMPORTANT ** ! ************** ! ! 1. If the ADDR64_CAP bit is set, you must use the MSI64 structure to ! access the following fields: ! . upper 32 bits of address ! . MESSAGE ! . VEC_MASK ! . VEC_PENDING ! ! 2. VEC_MASK and VEC_PENDING are only valid for access if the PER_VEC_CAP ! bit is set. ! literal MSICAP$K_CAP_ID = 0; literal MSICAP$K_NEXT_CAP = 1; literal MSICAP$K_CONTROL = 2; literal MSICAP$K_ADDRESS = 4; literal MSICAP$K_MESSAGE = 8; literal MSICAP$K_RESERVED = 10; literal MSICAP$K_BASIC_LENGTH = 12; literal MSICAP$K_VEC_MASK = 12; literal MSICAP$K_VEC_PENDING = 16; literal MSICAP$K_VEC_LENGTH = 20; literal MSICAP$K_VEC_AREA = 8; literal MSICAP$S_MSICAP = 20; macro MSICAP$B_CAP_ID = 0,0,8,0 %; macro MSICAP$B_NEXT_CAP = 1,0,8,0 %; macro MSICAP$R_CONTROL = 2,0,16,0 %; literal MSICAP$S_CONTROL = 2; macro MSICAP$L_ADDRESS = 4,0,32,0 %; macro MSICAP$W_MESSAGE = 8,0,16,0 %; macro MSICAP$W_RESERVED = 10,0,16,0 %; macro MSICAP$L_VEC_MASK = 12,0,32,0 %; macro MSICAP$L_VEC_PENDING = 16,0,32,0 %; ! ! ! ============================================================================ ! MSI64 - MSI with 64 bit message address ! ============================================================================ ! ! This definition creates constants that are offsets into the MSI PCI ! Capabiltiy block for a given device. ! ! See PCI Local Bus Specification Revision 3.0 Section 6.8.2 ! ! ************** ! * IMPORTANT ** ! ************** ! ! 1. This structure is valid ONLY if the ADDR64_CAP bit is set. ! ! 2. VEC_MASK and VEC_PENDING are only valid for access if the PER_VEC_CAP ! bit is set. ! literal MSI64CAP$K_CAP_ID = 0; literal MSI64CAP$K_NEXT_CAP = 1; literal MSI64CAP$K_CONTROL = 2; literal MSI64CAP$K_ADDRESS_LO = 4; literal MSI64CAP$K_ADDRESS_HI = 8; literal MSI64CAP$K_MESSAGE = 12; literal MSI64CAP$K_RESERVED = 14; literal MSI64CAP$K_BASIC_LENGTH = 16; literal MSI64CAP$K_VEC_MASK = 16; literal MSI64CAP$K_VEC_PENDING = 20; literal MSI64CAP$K_VEC_LENGTH = 24; literal MSI64CAP$K_VEC_AREA = 8; literal MSI64CAP$S_MSI64CAP = 24; macro MSI64CAP$B_CAP_ID = 0,0,8,0 %; macro MSI64CAP$B_NEXT_CAP = 1,0,8,0 %; macro MSI64CAP$R_CONTROL = 2,0,16,0 %; literal MSI64CAP$S_CONTROL = 2; macro MSI64CAP$L_ADDRESS_LO = 4,0,32,0 %; macro MSI64CAP$L_ADDRESS_HI = 8,0,32,0 %; macro MSI64CAP$W_MESSAGE = 12,0,16,0 %; macro MSI64CAP$W_RESERVED = 14,0,16,0 %; macro MSI64CAP$L_VEC_MASK = 16,0,32,0 %; macro MSI64CAP$L_VEC_PENDING = 20,0,32,0 %; ! ! ! ============================================================================ ! MSI 32-Bit Address Format ! ============================================================================ ! ! This definition of the Message Interrupt Message Address was obtained from ! The Intel IA64 Software Developers Manual, Volume 2, Figure 5-16 and Table ! 5-15. ! literal MSIADDR$M_RESERVED = %X'7'; literal MSIADDR$M_IR = %X'8'; literal MSIADDR$M_EID = %X'FF0'; literal MSIADDR$M_ID = %X'FF000'; literal MSIADDR$S_MSIADDR = 4; macro MSIADDR$L_ADDRESS = 0,0,32,0 %; macro MSIADDR$V_RESERVED = 0,0,3,0 %; literal MSIADDR$S_RESERVED = 3; macro MSIADDR$V_IR = 0,3,1,0 %; macro MSIADDR$V_EID = 0,4,8,0 %; literal MSIADDR$S_EID = 8; macro MSIADDR$V_ID = 0,12,8,0 %; literal MSIADDR$S_ID = 8; ! ! ! ============================================================================ ! MSI 64-Bit Address Format ! ============================================================================ ! ! This definition of the Message Interrupt Message Address was obtained from ! The Intel IA64 Software Developers Manual, Volume 2, Figure 5-16 and Table ! 5-15. ! literal MSIADDR64$M_RESERVED = %X'7'; literal MSIADDR64$M_IR = %X'8'; literal MSIADDR64$M_EID = %X'FF0'; literal MSIADDR64$M_ID = %X'FF000'; literal MSIADDR64$S_MSIADDR64 = 8; macro MSIADDR64$Q_ADDRESS = 0,0,0,0 %; literal MSIADDR64$S_ADDRESS = 8; macro MSIADDR64$L_ADDRESS_LO = 0,0,32,1 %; macro MSIADDR64$V_RESERVED = 0,0,3,0 %; literal MSIADDR64$S_RESERVED = 3; macro MSIADDR64$V_IR = 0,3,1,0 %; macro MSIADDR64$V_EID = 0,4,8,0 %; literal MSIADDR64$S_EID = 8; macro MSIADDR64$V_ID = 0,12,8,0 %; literal MSIADDR64$S_ID = 8; macro MSIADDR64$L_ADDRESS_HI = 4,0,32,1 %; ! ! ! ============================================================================ ! MSI Message Format ! ============================================================================ ! ! This definition of the Interrupt Message format was obtained from the ! Intel IA64 Software Developers Manual, Volume 2, Figure 5-17 and Table ! 5-16. ! literal MSIMSG$M_VECTOR = %X'FF'; literal MSIMSG$M_DELMODE = %X'700'; literal MSIMSG$S_MSIMSG = 4; macro MSIMSG$L_MSG = 0,0,32,0 %; macro MSIMSG$W_MSG = 0,0,16,0 %; macro MSIMSG$V_VECTOR = 0,0,8,0 %; literal MSIMSG$S_VECTOR = 8; macro MSIMSG$V_DELMODE = 0,8,3,0 %; literal MSIMSG$S_DELMODE = 3; ! ! ! ============================================================================ ! MSI-X Control Register Format ! ============================================================================ ! ! See PCI Local Bus Specification Revision 3.0 Section 6.8.2 ! ! msix$v_table_size - number of entries in the Vector Table, which is ! also the number of bits in the Pending Bit Array, ! maximum 2048. ! ! msix$v_function_mask - Masks all messages from this device ! ! msix$v_enable - Enables MSI-X interrupt delivery for this device. ! literal MSIX$M_TABLE_SIZE = %X'7FF'; literal MSIX$M_RESERVED = %X'3800'; literal MSIX$M_FUNCTION_MASK = %X'4000'; literal MSIX$M_ENABLE = %X'8000'; literal MSIX$S_MSIX_CONTROL = 2; macro MSIX$W_CONTROL = 0,0,16,0 %; macro MSIX$V_TABLE_SIZE = 0,0,11,0 %; literal MSIX$S_TABLE_SIZE = 11; ! 10:0 macro MSIX$V_RESERVED = 0,11,3,0 %; literal MSIX$S_RESERVED = 3; ! 13:11 macro MSIX$V_FUNCTION_MASK = 0,14,1,0 %; ! 14 macro MSIX$V_ENABLE = 0,15,1,0 %; ! 15 ! ! ! ============================================================================ ! MSI-X Offset Register Format ! ============================================================================ ! ! See PCI Local Bus Specification Revision 3.0 Section 6.8.2 ! ! msix$v_bir - Three-bit field that encodes the offset into the device's ! PCI config space of the BAR that has the base address in ! of the Vector Table or Pending Bit Array, as the case may ! be. ! ! msix$v_offset - The 29-bit field containing the offset into the base ! address identified by the BAR of the Table or PBA. ! literal MSIX$M_BIR = %X'7'; literal MSIX$M_OFFSET = %X'FFFFFFF8'; literal MSIX$S_MSIX_OFFSET_REG = 4; macro MSIX$L_OFFSET = 0,0,32,0 %; macro MSIX$V_BIR = 0,0,3,0 %; literal MSIX$S_BIR = 3; ! 2:0 macro MSIX$V_OFFSET = 0,3,29,0 %; literal MSIX$S_OFFSET = 29; ! 31:3 ! ! ! ============================================================================ ! MSI-X Capability Format ! ============================================================================ ! ! See PCI Local Bus Specification Revision 3.0 Section 6.8.2 ! ! The constants generated by this definition are byte offsets into the ! MSI-X Capability Block in PCI Config space. ! ! MSIXCAP$K_CAP_ID - Offset to field contianing the ID of this ! Capability, for MSI-X, 0x11. ! ! MSIXCAP$K_NEXT_CAP - Offset to field containing the offset from the ! base of PCI config space fof the device to the ! next Capability block of the device. Contains ! zero if no more Capability blocks. ! ! MSIXCAP$K_CONTROL - Offset to field containing the MSI-X Capability ! control bits. ! ! MSIXCAP$K_TABLE_OFFSET - Offset to field whose low three bits encode the ! offset into PCI Config space of the BAR that has ! the base address of the Vector Table, and whose ! upper 29 bits contain the offset of the Vector ! Table into the space identified by the BAR. ! ! MSIXCAP$K_PBA_OFFSET - Offset to field whose low three bits encode the ! offset into PCI Config space of the BAR that has ! the base address of the Pending Bit Array, and ! whose upper 29 bits contain the offset of the ! Pending Bit Array into the space identified by ! the BAR. ! literal MSIXCAP$K_CAP_ID = 0; literal MSIXCAP$K_NEXT_CAP = 1; literal MSIXCAP$K_CONTROL = 2; literal MSIXCAP$K_TABLE_OFFSET = 4; literal MSIXCAP$K_PBA_OFFSET = 8; literal MSIXCAP$K_LENGTH = 12; literal MSIXCAP$K_SIZE = 12; literal MSIXCAP$S_MSIXCAP = 12; macro MSIXCAP$B_CAP_ID = 0,0,8,0 %; macro MSIXCAP$B_NEXT_CAP = 1,0,8,0 %; macro MSIXCAP$R_CONTROL = 2,0,16,0 %; literal MSIXCAP$S_CONTROL = 2; macro MSIXCAP$R_TABLE_OFFSET = 4,0,32,0 %; literal MSIXCAP$S_TABLE_OFFSET = 4; macro MSIXCAP$R_PBA_OFFSET = 8,0,32,0 %; literal MSIXCAP$S_PBA_OFFSET = 4; ! ! ! ============================================================================ ! MSI-X Table Entry Control Register ! ============================================================================ ! See PCI Local Bus Specification Revision 3.0 Section 6.8.2 ! ! msix_entry$v_mask - masks the vector of the corresponding Vector Table ! MSIX_ENTRY$M_MASK Entry ! literal MSIX_ENTRY$M_MASK = %X'1'; literal MSIX_ENTRY$M_RESERVED = %X'FFFFFFFE'; literal MSIX_ENTRY$S_MSIX_ENTRY_CONTROL = 4; macro MSIX_ENTRY$L_CONTROL = 0,0,32,0 %; macro MSIX_ENTRY$V_MASK = 0,0,1,0 %; macro MSIX_ENTRY$V_RESERVED = 0,1,31,0 %; literal MSIX_ENTRY$S_RESERVED = 31; ! ! ! ============================================================================ ! MSI-X Table Entry ! ============================================================================ ! ! See PCI Local Bus Specification Revision 3.0 Section 6.8.2 ! ! This definition generates constants that are offsets into the MSI-X ! Vector Table. ! ! MSIX_ENTRY$K_ADDRESS - offset of the MSI-X Address field in the MSI-X ! Table Entry ! msix_entry$q_address - quadword displacement to next field in Table Entry ! ! ! MSIX_ENTRY$K_DATA - offset of the MSI-X Data field in the MSI-X Table ! Entry. ! msix_entry$l_data - longword displacement to next field in Table Entry ! ! ! MSIX_ENTRY$K_CONTROL - offset of the MSI-X Control field in the MSI-X ! Table Entry. ! msix_entry$r_control - displacement of the MSI-X Control field formatted ! as MSIX_ENTRY_CONTROL (see above). ! literal MSIX_ENTRY$K_ADDRESS = 0; literal MSIX_ENTRY$K_DATA = 8; literal MSIX_ENTRY$K_CONTROL = 12; literal MSIX_ENTRY$K_LENGTH = 16; literal MSIX_ENTRY$K_SIZE = 16; literal MSIX_ENTRY$S_MSIX_ENTRY = 16; macro MSIX_ENTRY$Q_ADDRESS = 0,0,0,0 %; literal MSIX_ENTRY$S_ADDRESS = 8; macro MSIX_ENTRY$L_DATA = 8,0,32,0 %; macro MSIX_ENTRY$R_CONTROL = 12,0,32,0 %; literal MSIX_ENTRY$S_CONTROL = 4; ! ! ! ================================================================== ! MSI and MSI-X Abstracted Data Structures for System Use ! ================================================================== ! ! These abstracted data areas are used to store the information ! obtained from the PCI Config Header MSI and MSI-X capability ! blocks, making it unnecessary to spin any more PCI config access ! cycles to obtain it again. For drivers, this information will ! be made available through ioc$node_data() calls. ! ! ------------------------------------------------------------------- ! MSI Abstracted Data Area ! ------------------------------------------------------------------- ! ! msi$r_address - Target Physical Address for the MSI Message ! formatted as MSIADDR64 (see above). ! ! msi$r_message - Message sent to Target Address formatted as ! MSIMSG (see above). ! literal MSI$S_MSI = 16; ! ! Target Physical Address ! macro MSI$R_ADDRESS = 0,0,0,0 %; literal MSI$S_ADDRESS = 8; ! ! The Message ! macro MSI$R_MESSAGE = 8,0,32,0 %; literal MSI$S_MESSAGE = 4; ! ! ! -------------------------------------------------------------------- ! MSIX Abstracted Data Area ! -------------------------------------------------------------------- ! ! The MSIX area, because it is a system level data area, is ! permanently, mapped and the IOHANDLEs for it are stored here. ! ! msix$q_table_iohandle - IO Handle for access to the MSIX ! Vector Table. ! ! msix$q_pba_iohandle - IO Handle for access to the Pending ! Bit Array. ! ! msix$w_entry_count - number of entries in the Vector Table ! literal MSIX$S_MSIX = 24; ! ! IOHANDLE of the MSI-X Vector Table ! macro MSIX$Q_TABLE_IOHANDLE = 0,0,0,0 %; literal MSIX$S_TABLE_IOHANDLE = 8; ! ! IOHANDLE of the Pending Bit Array ! macro MSIX$Q_PBA_IOHANDLE = 8,0,0,0 %; literal MSIX$S_PBA_IOHANDLE = 8; macro MSIX$W_ENTRY_COUNT = 16,0,16,0 %; ! ! ! -------------------------------------------------------------------- ! MSIDATA Abstracted MSI Union ! -------------------------------------------------------------------- ! ! msidata$r_msi - space required for MSI data block format ! msidata$r_msix - space required for MSI-X data block format ! literal MSIDATA$S_MSIDATA = 24; macro MSIDATA$r_msi = 0,0,0,0 %; literal MSIDATA$s_msi = 16; macro MSIDATA$r_msix = 0,0,0,0 %; literal MSIDATA$s_msix = 24; ! ! ! -------------------------------------------------------------------- ! MSIABS Abstracted MSI Data Block ! -------------------------------------------------------------------- ! ! This structure abstracts the fields of the MSI or MSI-X Capabilty. ! Only one of these capabilities will be enabled. OpenVMS will enable ! the MSI-X capability of a device if it supports both MSI and MSI-X. ! ! The salient information about the MSI or MSI-X capability is ! stored and updated in this structure for the system-level interface ! to driver code provided by ioc$node_data() and ioc$node_function ! routines. ! ! msiabs$l_cfg_offset - Offset into the device's PCI Config space ! of its MSI or MSI-X Capabilitly Block. ! ! msiabs$w_control - Copy of the most recent write to the control ! register of the MSI or MSI-X capability. ! ! msiabs$w_type - contains one of: ! IOC$K_INTDEL_IOSAPIC - not MSI or MSI-X capable ! IOC$K_INTDEL_MSI - MSI enabled ! IOC$K_INTDEL_MSIX - MSI-X enabled ! The contents of this field tell the user how ! to format the data areas of this structure, ! whetehr for MSI or MSI-X. ! ! msiabs$r_data - MSI or MSI-X specific data area formatted ! according to the contents of msiabs$w_type ! literal MSIABS$S_MSIABS = 32; macro MSIABS$L_CFG_OFFSET = 0,0,32,0 %; ! PCI Config Offset of MSI Cap Block macro MSIABS$W_CONTROL = 4,0,16,0 %; ! Copy of the MSI* Control Register ! ! The msiabs$w_type field indicates how to format the msiabs$r_data ! field, in C terms, whether to cast it as MSI or MSIX. ! macro MSIABS$W_TYPE = 6,0,16,0 %; macro MSIABS$R_DATA = 8,0,0,0 %; literal MSIABS$S_DATA = 24; !*** MODULE $PCMCIADEF *** literal TPLCODE$K_CISTPL_NULL = 0; literal TPLCODE$K_CISTPL_DEVICE = 1; literal TPLCODE$K_CISTPL_CHECKSUM = 16; literal TPLCODE$K_CISTPL_LONGLINK_A = 17; literal TPLCODE$K_CISTPL_LONGLINK_C = 18; literal TPLCODE$K_CISTPL_LLINKTARGET = 19; literal TPLCODE$K_CISTPL_NO_LINK = 20; literal TPLCODE$K_CISTPL_VERS_1 = 21; literal TPLCODE$K_CISTPL_ALTSTR = 22; literal TPLCODE$K_CISTPL_DEVICE_A = 23; literal TPLCODE$K_CISTPL_JEDEC_C = 24; literal TPLCODE$K_CISTPL_JEDEC_A = 25; literal TPLCODE$K_CISTPL_CONFIG = 26; literal TPLCODE$K_CISTPL_CFTABLE_ENTRY = 27; literal TPLCODE$K_CISTPL_DEVICE_OC = 28; literal TPLCODE$K_CISTPL_DEVCIE_OA = 29; literal TPLCODE$K_CISTPL_DEVICE_GEO = 30; literal TPLCODE$K_CISTPL_DEVICE_GEO_A = 31; literal TPLCODE$K_CISTPL_MANFID = 32; literal TPLCODE$K_CISTPL_FUNCID = 33; literal TPLCODE$K_CISTPL_FUNCE = 34; literal TPLCODE$K_CISTPL_SWIL = 35; literal TPLCODE$K_CISTPL_VERS_2 = 64; literal TPLCODE$K_CISTPL_FORMAT = 65; literal TPLCODE$K_CISTPL_GEOMETRY = 66; literal TPLCODE$K_CISTPL_BYTEORDER = 67; literal TPLCODE$K_CISTPL_DATE = 68; literal TPLCODE$K_CISTPL_BATTERY = 69; literal TPLCODE$K_CISTPL_ORG = 70; literal TPLCODE$K_CISTPL_END = 255; literal TPLDID$K_DSPEED_NULL = 0; literal TPLDID$K_DSPEED_250NS = 1; literal TPLDID$K_DSPEED_200NS = 2; literal TPLDID$K_DSPEED_150NS = 3; literal TPLDID$K_DSPEED_100NS = 4; literal TPLDID$K_DSPEED_EXT = 7; literal TPLDID$K_DTYPE_NULL = 0; literal TPLDID$K_DTYPE_ROM = 1; literal TPLDID$K_DTYPE_OTPROM = 2; literal TPLDID$K_DTYPE_EPROM = 3; literal TPLDID$K_DTYPE_EEPROM = 4; literal TPLDID$K_DTYPE_FLASH = 5; literal TPLDID$K_DTYPE_SRAM = 6; literal TPLDID$K_DTYPE_DRAM = 7; literal TPLDID$K_DTYPE_FUNCSPEC = 13; literal TPLDID$K_DTYPE_EXTEND = 14; literal TPLDID$K_SIZE_512B = 0; literal TPLDID$K_SIZE_2K = 1; literal TPLDID$K_SIZE_8K = 2; literal TPLDID$K_SIZE_32K = 3; literal TPLDID$K_SIZE_128K = 4; literal TPLDID$K_SIZE_512K = 5; literal TPLDID$K_SIZE_2M = 6; literal TPLFID$K_MULTI_FUNC = 0; literal TPLFID$K_MEMORY = 1; literal TPLFID$K_SERIAL_PORT = 2; literal TPLFID$K_PARALLEL_PORT = 3; literal TPLFID$K_FIXED_DISK = 4; literal TPLFID$K_VIDEO_ADAPTER = 5; literal TPLFID$K_NETWORK_LAN = 6; literal TPLFID$K_AIMS = 7; literal TPLFID_SYSINIT$K_POST = 1; literal TPLFID_SYSINIT$K_ROM = 2; !*** MODULE PCSAMPLEDEF *** literal PCBUF$C_STRUCTURE_VERSION = 2; ! ! Slot constraining values ! literal PCBUF$C_MAX_SLOT_CNT = 32768; ! Maximum number of slots literal PCBUF$C_MIN_SLOT_CNT = 128; ! Minimum number of slots ! ! Slot structure definition ! literal PCSLT$C_LENGTH = 16; literal PCSLT$S_PCSLTDEF = 16; ! Old size name - synonym literal PCSLT$S_PCSLT = 16; macro PCSLT$L_PC = 0,0,32,1 %; ! Program counter macro PCSLT$L_PS = 4,0,32,0 %; ! Process status macro PCSLT$L_COUNTER = 8,0,32,0 %; ! Indicates which counter fired macro PCSLT$L_PID = 12,0,32,0 %; ! ID of current process ! ! Buffer descriptor structure ! literal PCDSC$C_LENGTH = 20; literal PCDSC$S_PCDSCDEF = 20; ! Old size name - synonym literal PCDSC$S_PCDSC = 20; macro PCDSC$L_BUFFER = 0,0,32,1 %; ! Pointer to buffer in use macro PCDSC$R_OVER_1 = 4,0,0,0 %; literal PCDSC$S_OVER_1 = 8; macro PCDSC$R_SLOT_INFO = 4,0,0,0 %; literal PCDSC$S_SLOT_INFO = 8; macro PCDSC$L_CUR_SLOT = 4,0,32,0 %; ! Index of next slot macro PCDSC$L_SLOT_CNT = 8,0,32,0 %; ! Number of slots in the buffer macro PCDSC$R_COUNTER_INFO = 4,0,0,0 %; literal PCDSC$S_COUNTER_INFO = 8; macro PCDSC$L_COUNTER_0 = 4,0,32,0 %; macro PCDSC$L_COUNTER_1 = 8,0,32,0 %; macro PCDSC$L_BUFF_SIZE = 12,0,32,0 %; ! Size of memory block for descriptor macro PCDSC$L_RING_PTR = 16,0,32,1 %; ! Fake buffer pointer to next buffer ! ! Buffer structure ! literal PCBUF$C_HDR_SIZE = 32; ! Buffer header size literal PCBUF$C_MAX_LENGTH = 524320; ! Maximum buffer size literal PCBUF$S_PCBUFDEF = 524320; ! Old size name - synonym literal PCBUF$S_PCBUF = 524320; macro PCBUF$L_NEXT_BUFF = 0,0,32,1 %; ! Pointer to next buffer macro PCBUF$L_BUFF_SIZE = 4,0,32,0 %; ! Size of memory block used for buffer macro PCBUF$L_FULL_FLAG = 8,0,32,0 %; ! Buffer is full macro PCBUF$L_CPU_ID = 12,0,32,0 %; ! CPU index macro PCBUF$Q_BEGIN_TIME = 16,0,0,0 %; literal PCBUF$S_BEGIN_TIME = 8; ! Time buffer was started macro PCBUF$B_SCRATCH = 24,0,0,1 %; literal PCBUF$S_SCRATCH = 8; ! Used to force slot alignment macro PCBUF$B_DATA_AREA = 32,0,0,1 %; literal PCBUF$S_DATA_AREA = 524288; ! Data slots literal PCBUF$C_MIN_LENGTH = 2080; ! Minimum buffer size !*** MODULE $PCTXDEF *** ! + ! ! Define: FCLE_MBD (FCLE API Mapped Buffer Descriptor) ! ! ! - literal FCLE_MBD$S_FCLE_MBD = 56; ! Flink and Blink pointers macro FCLE_MBD$PS_QFL = 0,0,32,1 %; macro FCLE_MBD$PS_QBL = 4,0,32,1 %; ! Size, type and subtype in standard OpenVMS structure locations macro FCLE_MBD$W_SIZE = 8,0,16,1 %; macro FCLE_MBD$B_TYPE = 10,0,8,1 %; macro FCLE_MBD$B_SUBTYPE = 11,0,8,1 %; macro FCLE_MBD$L_FLAGS = 12,0,32,0 %; ! Quadword available for whatever the user wants macro FCLE_MBD$Q_USER_DATA = 16,0,0,0 %; literal FCLE_MBD$S_USER_DATA = 8; ! Logical Size - this is the number of leading bytes of this buffer which ! will be read or written the next time this MBD is used. It will be initialized ! to the number of bytes mapped. It can be changed by a caller prior to use and ! read by a caller after use. Again: this size always refers to the leading ! bytes of the buffer macro FCLE_MBD$IS_LOGICAL_SIZE = 24,0,32,1 %; ! This is only used to store a VA if the caller mapping a buffer passes in a ! VA, and it's only so the caller can always find a VA from an MBD. If they ! want to use it for something else that's OK with the Kernel, because it ! never references the address of a buffer mapped by an MBD macro FCLE_MBD$Q_VA = 28,0,0,1 %; literal FCLE_MBD$S_VA = 8; ! Buffer byte offset macro FCLE_MBD$IS_BOFF = 36,0,32,1 %; ! Mapped size, the absolute maximum number of bytes which can be ! addressed by this MBD. macro FCLE_MBD$IS_BCNT = 40,0,32,1 %; ! Buffer SVAPTE macro FCLE_MBD$PS_SVAPTE = 44,0,32,1 %; ! Number of physical pages spanned (and MRs allocated) macro FCLE_MBD$IS_PAGES = 48,0,32,1 %; ! Number of bytes transferred macro FCLE_MBD$IS_TRANSFER_BCNT = 52,0,32,1 %; ! ! There is one PCBVEC for each protocol (PCTX) so protocol specific ! data is unioned in the PCBVEC to save space. ! literal PCBVEC$K_FORMAT_VERSION = 2; literal PCBVEC$S_PCBVEC = 128; ! ! Only bump this version number if the PCBVEC is changed in ! such a way that all drivers will need to be recompiled ! macro PCBVEC$IS_FORMAT_VERSION = 0,0,32,1 %; ! ! Unused entries have been added in the middle of the common vectors ! at the end of the protocol specific vectors. Use these unused ! entries add new vectors. This will save us from ! having to compile all drivers when only one protocol is ! affected. ! macro PCBVEC$R_VECTOR_UNION = 4,0,0,0 %; literal PCBVEC$S_VECTOR_UNION = 120; macro PCBVEC$PS_VECTOR_ARRAY = 4,0,32,1 %; literal PCBVEC$S_VECTOR_ARRAY = 4; macro PCBVEC$R_VECTORS_STRUCTURE = 4,0,0,0 %; literal PCBVEC$S_VECTORS_STRUCTURE = 120; macro PCBVEC$PS_EXCHANGE_ABORTED = 4,0,32,1 %; macro PCBVEC$PS_PRLI_IND = 8,0,32,1 %; macro PCBVEC$PS_PRLO_IND = 12,0,32,1 %; macro PCBVEC$PS_BUFFER_WANTED = 16,0,32,1 %; macro PCBVEC$PS_BUFFER_FILLED = 20,0,32,1 %; macro PCBVEC$PS_BUFFER_RELEASED = 24,0,32,1 %; macro PCBVEC$PS_PAUSE = 28,0,32,1 %; macro PCBVEC$PS_RESUME = 32,0,32,1 %; macro PCBVEC$PS_LINK_STATE = 36,0,32,1 %; macro PCBVEC$PS_PAUSE_FC_LA = 40,0,32,1 %; macro PCBVEC$PS_RESUME_FC_LA = 44,0,32,1 %; macro PCBVEC$PS_CMD_TIMEOUT = 48,0,32,1 %; macro PCBVEC$PS_ELS_IND = 52,0,32,1 %; macro PCBVEC$PS_ELS_CNF = 56,0,32,1 %; macro PCBVEC$PS_PORT_STATE = 60,0,32,1 %; macro PCBVEC$PS_CHANGE_PREFERRED = 64,0,32,1 %; macro PCBVEC$PS_CREATE_TARGET = 68,0,32,1 %; ! X-6 macro PCBVEC$PS_UNUSED2 = 72,0,32,1 %; macro PCBVEC$PS_UNUSED3 = 76,0,32,1 %; macro PCBVEC$PS_UNUSED4 = 80,0,32,1 %; macro PCBVEC$PS_UNUSED5 = 84,0,32,1 %; ! ! This union is for data that is only needed by a specific ! protocol. ! macro PCBVEC$R_PROTOCOL_VECTOR_UNION = 88,0,0,0 %; literal PCBVEC$S_PROTOCOL_VECTOR_UNION = 36; macro PCBVEC$R_FCP_STRUCTURE = 88,0,32,0 %; literal PCBVEC$S_FCP_STRUCTURE = 4; macro PCBVEC$PS_RBUN_INIT = 88,0,32,1 %; macro PCBVEC$R_FCLE_STRUCTURE = 88,0,0,0 %; literal PCBVEC$S_FCLE_STRUCTURE = 36; macro PCBVEC$PS_CONFIRMATION = 88,0,32,1 %; macro PCBVEC$PS_INDICATION = 92,0,32,1 %; macro PCBVEC$PS_GET_PREQ_BUF = 96,0,32,1 %; macro PCBVEC$PS_RET_PREQ_BUF = 100,0,32,1 %; macro PCBVEC$PS_UNUSED6 = 104,0,32,1 %; macro PCBVEC$PS_UNUSED7 = 108,0,32,1 %; macro PCBVEC$PS_UNUSED8 = 112,0,32,1 %; macro PCBVEC$PS_UNUSED9 = 116,0,32,1 %; macro PCBVEC$PS_UNUSED10 = 120,0,32,1 %; ! ! There is only one ULPVEC per system ! literal ULPVEC$K_FORMAT_VERSION = 3; literal ulp$K_DEBUG = 0; literal ulp$K_FCP_SCSI = 1; literal ulp$K_LAN = 2; literal ulp$K_ELS = 3; ! Define buffer context values for ULP$MAP literal ulp$K_GENERAL_DATA = 1; literal ulp$K_FCP_DATA = 2; literal ulp$K_FCP_CMD_RSP = 3; literal ulp$K_ELS_REQ_RSP = 4; literal ulp$K_QUEUE_BUFFER = 5; literal ULPVEC$S_ULPVEC = 264; ! ! Only bump this version number if the ULPVEC is changed in ! such a way that all drivers will need to be recompiled ! macro ULPVEC$IS_FORMAT_VERSION = 0,0,32,1 %; macro ULPVEC$R_VECTOR_UNION = 4,0,0,0 %; literal ULPVEC$S_VECTOR_UNION = 260; macro ULPVEC$PS_VECTOR_ARRAY = 4,0,32,1 %; literal ULPVEC$S_VECTOR_ARRAY = 4; macro ULPVEC$R_VECTORS_STRUCTURE = 4,0,0,0 %; literal ULPVEC$S_VECTORS_STRUCTURE = 260; ! ************************************************** ! ULP (Upper Level Protocol) Vectors ! ************************************************** macro ULPVEC$PS_DISCONNECT = 4,0,32,1 %; macro ULPVEC$PS_GET_REQUESTS = 8,0,32,1 %; macro ULPVEC$PS_GET_REQUEST_DATA = 12,0,32,1 %; macro ULPVEC$PS_GET_EXCHANGES = 16,0,32,1 %; macro ULPVEC$PS_GET_EXCHANGE_DATA = 20,0,32,1 %; macro ULPVEC$PS_MAP = 24,0,32,1 %; macro ULPVEC$PS_UNMAP = 28,0,32,1 %; macro ULPVEC$PS_RESET = 32,0,32,1 %; macro ULPVEC$PS_QUEUE_BUFFER_ULP = 36,0,32,1 %; macro ULPVEC$PS_QUEUE_BUFFER_EXCHANGE = 40,0,32,1 %; macro ULPVEC$PS_SEND_SEQUENCE = 44,0,32,1 %; macro ULPVEC$PS_OPEN_EXCHANGE = 48,0,32,1 %; macro ULPVEC$PS_ABORT_REQUEST = 52,0,32,1 %; macro ULPVEC$PS_ABORT_EXCHANGE = 56,0,32,1 %; macro ULPVEC$PS_BROADCAST_FRAME = 60,0,32,1 %; macro ULPVEC$PS_ALLOC_MBD = 64,0,32,1 %; macro ULPVEC$PS_FREE_MBD = 68,0,32,1 %; macro ULPVEC$PS_CLONE_MBD = 72,0,32,1 %; macro ULPVEC$PS_DELETED_VECTOR = 76,0,32,1 %; macro ULPVEC$PS_GET_FCLA = 80,0,32,1 %; macro ULPVEC$PS_VALIDATE_FCLA = 84,0,32,1 %; macro ULPVEC$PS_INIT_LINK = 88,0,32,1 %; macro ULPVEC$PS_GET_PORT_WWID = 92,0,32,1 %; macro ULPVEC$PS_CANCEL_REQUEST = 96,0,32,1 %; macro ULPVEC$PS_ALLOC_MAPPED_BUFFER = 100,0,32,1 %; macro ULPVEC$PS_FREE_MAPPED_BUFFER = 104,0,32,1 %; macro ULPVEC$PS_GET_LINK_DATA = 108,0,32,1 %; macro ULPVEC$PS_FP_REQUEST = 112,0,32,1 %; macro ULPVEC$PS_FP_SEND = 116,0,32,1 %; macro ULPVEC$PS_FREE_RBUN = 120,0,32,1 %; macro ULPVEC$PS_BUS_ADDRESS = 124,0,32,1 %; macro ULPVEC$PS_UNUSED1 = 128,0,32,1 %; macro ULPVEC$PS_UNUSED2 = 132,0,32,1 %; macro ULPVEC$PS_UNUSED3 = 136,0,32,1 %; macro ULPVEC$PS_UNUSED4 = 140,0,32,1 %; ! *************************************************** ! ELS (Extended Link Service) Vectors ! *************************************************** macro ULPVEC$PS_ELS_ALLOC_PAYLOADS = 144,0,32,1 %; macro ULPVEC$PS_ELS_DEALLOC_PAYLOADS = 148,0,32,1 %; macro ULPVEC$PS_ELS_SEND = 152,0,32,1 %; macro ULPVEC$PS_ELS_SEND_CMD = 156,0,32,1 %; macro ULPVEC$PS_ELS_SEND_RSP = 160,0,32,1 %; macro ULPVEC$PS_ALLOC_LS_RJT = 164,0,32,1 %; macro ULPVEC$PS_ALLOC_LS_ACC = 168,0,32,1 %; macro ULPVEC$PS_UNUSED5 = 172,0,32,1 %; macro ULPVEC$PS_UNUSED6 = 176,0,32,1 %; macro ULPVEC$PS_UNUSED7 = 180,0,32,1 %; ! ! The following data are specific to particular ! protocols but we can't union then together because ! there is only one ULPVEC per system. ! ! ******************************************************** ! FCP (SCSI FibreChannel Protocol) Vectors ! ******************************************************** macro ULPVEC$PS_FCP_ALLOC_PAYLOADS = 184,0,32,1 %; macro ULPVEC$PS_FCP_DEALLOC_PAYLOADS = 188,0,32,1 %; macro ULPVEC$PS_FCP_SEND = 192,0,32,1 %; macro ULPVEC$PS_COMPLETION_PROCESSING = 196,0,32,1 %; macro ULPVEC$PS_WRITE_DATA = 200,0,32,1 %; macro ULPVEC$PS_READ_DATA = 204,0,32,1 %; macro ULPVEC$PS_FCP_SEND_RSP = 208,0,32,1 %; macro ULPVEC$PS_SET_CONNECTION_CHAR = 212,0,32,1 %; macro ULPVEC$PS_FCP_ABORT = 216,0,32,1 %; macro ULPVEC$PS_EVENT = 220,0,32,1 %; macro ULPVEC$PS_TRIGGER = 224,0,32,1 %; ! X-8 macro ULPVEC$PS_UNUSED9 = 228,0,32,1 %; macro ULPVEC$PS_UNUSED10 = 232,0,32,1 %; ! ********************************************************* ! FCLE (LAN over Fibre Channel) Vectors ! ********************************************************* macro ULPVEC$PS_GET_FC_LA_DATA = 236,0,32,1 %; macro ULPVEC$PS_BROADCAST = 240,0,32,1 %; macro ULPVEC$PS_SEQUENCE = 244,0,32,1 %; macro ULPVEC$PS_FCLE_ABORT = 248,0,32,1 %; macro ULPVEC$PS_CLOSE_EXCHANGE = 252,0,32,1 %; macro ULPVEC$PS_RET_MBD_LIST = 256,0,32,1 %; macro ULPVEC$PS_HARD_RESET = 260,0,32,1 %; ! Define ULP_ID values ! + ! ! Define: PCTX (Protocol Context) ! ! One Protocol Context is created for each ULP which connects to the Shell ! ! - literal PCTX$M_BROADCAST = %X'1'; literal PCTX$M_INITIAL_PREEMPT = %X'2'; literal PCTX$K_FORMAT_VERSION = 2; ! format of the PCTX literal PCTX$M_CLASS2 = 4; literal PCTX$M_CLASS3 = 8; literal PCTX$V_CLASS2 = 2; literal PCTX$V_CLASS3 = 3; literal PCTX$S_PCTX = 272; ! Forward link macro PCTX$PS_QFL = 0,0,32,1 %; ! Backward link macro PCTX$PS_QBL = 4,0,32,1 %; ! Structure (allocation) size macro PCTX$W_SIZE = 8,0,16,1 %; ! Structure type (DYN$C_MISC) macro PCTX$B_TYPE = 10,0,8,1 %; ! Structure subtype (DYN$C_PCTX) macro PCTX$B_SUBTYPE = 11,0,8,1 %; ! Define some flags ! All flags macro PCTX$L_FLAGS = 12,0,32,1 %; ! Individual flags macro PCTX$L_FLAGS_STRUCTURE = 12,0,32,0 %; macro PCTX$V_BROADCAST = 12,0,1,0 %; ! Boolean: true if protocol can do broadcast macro PCTX$V_INITIAL_PREEMPT = 12,1,1,0 %; ! Boolean: true if initial preemptive target ! creation has taken place. ! ! Only bump this version number if the PCTX is changed in ! such a way that all drivers will need to be recompiled ! macro PCTX$IS_FORMAT_VERSION = 16,0,32,1 %; ! Shell Context pointer macro PCTX$PS_SCTX = 20,0,32,1 %; ! Unit Context pointer macro PCTX$PS_UCTX = 24,0,32,1 %; ! Ring on which this protocol is enabled macro PCTX$IS_RING = 28,0,32,1 %; ! Return the UCB to the ULP macro PCTX$PS_FC_AD_UCB = 32,0,32,1 %; ! ULP fork lock index macro PCTX$IS_FLCK = 36,0,32,0 %; ! Protocol Callback Context to be passed to each callback macro PCTX$Q_PCBCTX = 40,0,0,0 %; literal PCTX$S_PCBCTX = 8; ! ULP KPB (this does not need to be specified and it may be NULL) macro PCTX$PS_ULP_KPB = 48,0,32,1 %; ! Protocol ID given to the adapter ( FCPH$K_ ) macro PCTX$IS_PROTOCOL = 52,0,32,0 %; ! Protocol specified when ULP connected ( ULP$K_ ) macro PCTX$IS_PROTOCOL_ID = 56,0,32,0 %; ! Load PCI address space for adapter ID information macro PCTX$PS_CHS = 60,0,32,1 %; ! Pointer used to define a protocol port specific data ! for the Fibre Channel adapter. macro PCTX$PS_PROTODEF = 64,0,32,1 %; ! ULP vector pointer macro PCTX$PS_ULPVEC = 68,0,32,1 %; ! PCB vector structure macro PCTX$R_PCBVEC = 72,0,0,0 %; literal PCTX$S_PCBVEC = 128; ! ! This union is for protocol specific data cells ! macro PCTX$R_PROTOCOL_SPECIFIC_DATA = 200,0,0,0 %; literal PCTX$S_PROTOCOL_SPECIFIC_DATA = 72; ! ! FCP protocol specific ! macro PCTX$R_FCPDEF = 200,0,0,0 %; literal PCTX$S_FCPDEF = 60; ! Resource Bundle Lookaside List pointer macro PCTX$PS_RBUN_LAL = 200,0,32,1 %; ! Sequence number to allow LAL to be used with EXE$LAL_INSERT/REMOVE_FIRST macro PCTX$L_RBUN_LAL_SEQNUM = 204,0,32,0 %; ! Prebuilt READ IOCB command longword (i.e. FCP_IREAD for FCP protocol) macro PCTX$L_FP_IOCB_READ_ICB = 208,0,32,0 %; ! Maximum data buffer byte count in an RBUN macro PCTX$L_MAX_RBUN_BCNT = 212,0,32,1 %; ! Prebuilt WRITE IOCB command longword (i.e. FCP_IWRITE for FCP protocol) macro PCTX$L_FP_IOCB_WRITE_ICB = 216,0,32,0 %; ! Value at which we'll start drain TQE macro PCTX$L_RBUN_DRAIN_THRESHOLD = 220,0,32,1 %; ! Total number of RBUNs, free and in use macro PCTX$L_TOTAL_RBUNS = 224,0,32,1 %; ! Number of unhandled RBUN allocation failures macro PCTX$L_RBUN_ALLOC_FAILURES = 228,0,32,1 %; ! TQE used to check & drain RBUNs macro PCTX$PS_RBUN_DRAIN_TQE = 232,0,32,1 %; macro PCTX$R_RBUN_DRAIN_UNION = 240,0,0,0 %; literal PCTX$S_RBUN_DRAIN_UNION = 8; macro PCTX$Q_RBUN_DRAIN_ACTIVE = 240,0,0,0 %; literal PCTX$S_RBUN_DRAIN_ACTIVE = 8; macro PCTX$R_RBUN_DRAIN_STRUCT = 240,0,0,0 %; literal PCTX$S_RBUN_DRAIN_STRUCT = 8; macro PCTX$PS_RBUN_DRAIN_LAL = 240,0,32,1 %; macro PCTX$L_RBUN_DRAIN_COUNT = 244,0,32,0 %; ! ! These two values are pointers to the SPDT data ! macro PCTX$L_SPL_PORT = 248,0,32,1 %; macro PCTX$PS_MAX_FP_BCNT = 252,0,32,1 %; macro PCTX$L_SPL_DYN = 256,0,32,1 %; ! X-7 ! ! FCLE protocol specific ! macro PCTX$R_FCLEDEF = 200,0,0,0 %; literal PCTX$S_FCLEDEF = 72; ! macro PCTX$PS_FCLE_LOAD_CRCTX = 200,0,32,1 %; ! macro PCTX$PS_FCLE_ALLOC_CRCTX = 204,0,32,1 %; ! size of the pre-queued adapter buffers for the fcle ring macro PCTX$L_FCLE_PREQ_BUF_SIZE = 208,0,32,0 %; ! list of available FCCDs macro PCTX$PS_FCLE_FCCD_LIST = 212,0,32,1 %; ! A count of mbd_list arrays passed up the LAN ULP. ! The count is decremented as the ULP returns each mbd_list. macro PCTX$L_OUTSTANDING_MBD_LISTS = 216,0,32,0 %; ! Number of FCCDs to preallocate macro PCTX$L_FCLE_MAX_FCCDS = 220,0,32,1 %; ! ! LAN Driver private data ! macro PCTX$L_LAN_P1 = 224,0,32,0 %; macro PCTX$L_LAN_P2 = 228,0,32,0 %; macro PCTX$L_LAN_P3 = 232,0,32,0 %; macro PCTX$L_LAN_P4 = 236,0,32,0 %; macro PCTX$L_LAN_P5 = 240,0,32,0 %; macro PCTX$L_LAN_P6 = 244,0,32,0 %; ! ! unspecified reserved data ! macro PCTX$L_FCLE_P1 = 248,0,32,0 %; macro PCTX$L_FCLE_P2 = 252,0,32,0 %; macro PCTX$L_FCLE_P3 = 256,0,32,0 %; macro PCTX$L_FCLE_P4 = 260,0,32,0 %; macro PCTX$L_FCLE_P5 = 264,0,32,0 %; macro PCTX$L_FCLE_P6 = 268,0,32,0 %; ! ! These constants define the Fibre Channel class of service ! capabilities of the connection ! ! ! LNK$K_UP and LNK$K_DOWN are returned in pcbvec$ps_link_state ! literal LNK$K_INITIAL = 0; ! Initial link state (suppresses initial report, MBZ) literal LNK$K_UP = 1; ! Link is up literal LNK$K_DOWN = 2; ! Link is down !*** MODULE $PD6729DEF *** literal PD6729$K_CHIP_REVISION = 0; literal PD6729$K_INTERFACE_STATUS = 1; literal PD6729$K_POWER_CONTROL = 2; literal PD6729$K_INTR_AND_CONTROL = 3; literal PD6729$K_CARD_STAT_CHANGE = 4; literal PD6729$K_MGMT_INTR_CNFG = 5; literal PD6729$K_MAPPING_ENABLE = 6; literal PD6729$K_IO_WINDOW_CTRL = 7; literal PD6729$K_MISC_CONTROL_1 = 22; literal PD6729$K_FIFO_CONTROL = 23; literal PD6729$K_MISC_CONTROL_2 = 30; literal PD6729$K_CHIP_INFO = 31; literal PD6729$K_ATA_CONTROL = 38; literal PD6729$K_EXT_INDEX = 46; literal PD6729$K_EXT_DATA = 47; literal PD6729$K_SETUP_TIME_0 = 58; literal PD6729$K_CMD_TIME_0 = 59; literal PD6729$K_RECOVERY_TIME_0 = 60; literal PD6729$K_SETUP_TIME_1 = 61; literal PD6729$K_CMD_TIME_1 = 62; literal PD6729$K_RECOVERY_TIME_1 = 63; literal PD6729$K_IO_START_LOW_0 = 8; literal PD6729$K_IO_START_HIGH_0 = 9; literal PD6729$K_IO_END_LOW_0 = 10; literal PD6729$K_IO_END_HIGH_0 = 11; literal PD6729$K_IO_OFFSET_LOW_0 = 54; literal PD6729$K_IO_OFFSET_HIGH_0 = 55; literal PD6729$K_IO_START_LOW_1 = 12; literal PD6729$K_IO_START_HIGH_1 = 13; literal PD6729$K_IO_END_LOW_1 = 14; literal PD6729$K_IO_END_HIGH_1 = 15; literal PD6729$K_IO_OFFSET_LOW_1 = 56; literal PD6729$K_IO_OFFSET_HIGH_1 = 57; literal PD6729$K_MEM_START_LOW_0 = 16; literal PD6729$K_MEM_START_HIGH_0 = 17; literal PD6729$K_MEM_END_LOW_0 = 18; literal PD6729$K_MEM_END_HIGH_0 = 19; literal PD6729$K_MEM_OFFSET_LOW_0 = 20; literal PD6729$K_MEM_OFFSET_HIGH_0 = 21; literal PD6729$K_MEM_START_LOW_1 = 24; literal PD6729$K_MEM_START_HIGH_1 = 25; literal PD6729$K_MEM_END_LOW_1 = 26; literal PD6729$K_MEM_END_HIGH_1 = 27; literal PD6729$K_MEM_OFFSET_LOW_1 = 28; literal PD6729$K_MEM_OFFSET_HIGH_1 = 29; literal PD6729$K_MEM_START_LOW_2 = 32; literal PD6729$K_MEM_START_HIGH_2 = 33; literal PD6729$K_MEM_END_LOW_2 = 34; literal PD6729$K_MEM_END_HIGH_2 = 35; literal PD6729$K_MEM_OFFSET_LOW_2 = 36; literal PD6729$K_MEM_OFFSET_HIGH_2 = 37; literal PD6729$K_MEM_START_LOW_4 = 48; literal PD6729$K_MEM_START_HIGH_4 = 49; literal PD6729$K_MEM_END_LOW_4 = 50; literal PD6729$K_MEM_END_HIGH_4 = 51; literal PD6729$K_MEM_OFFSET_LOW_4 = 52; literal PD6729$K_MEM_OFFSET_HIGH_4 = 53; literal PD6729$K_EXT_CONTROL_1 = 3; literal PD6729$K_MEM_UPPER_0 = 5; literal PD6729$K_MEM_UPPER_1 = 6; literal PD6729$K_MEM_UPPER_2 = 7; literal PD6729$K_MEM_UPPER_3 = 8; literal PD6729$K_MEM_UPPER_4 = 9; literal PD6729$K_EXTERNAL_DATA = 10; literal PD6729$K_EXT_CONTROL_2 = 11; literal PD6729$K_SOCKET_SHIFT = 6; literal PD6729$K_SOCKET_OFFSET = 64; literal PD6729$K_INDEX = 0; literal PD6729$K_DATA = 1; literal PD6729$K_LOW_POWER_DYNAMIC = 2; literal PD6729$K_CARD_ENABLE = 128; literal PD6729$K_AUTO_POWER = 32; literal PD6729$K_VCC = 16; literal PD6729$K_DATA_PATH_16 = 128; literal PD6729$K_REG_ACTIVE = 64; literal PD6729$K_NOT_RESET = 64; literal PD6729$K_IO = 32; literal PD6729$K_BATTERY_STATUS = 1; literal PD6729$K_BATTERY_WARN = 2; literal PD6729$K_READY_ENABLE = 4; literal PD6729$K_CARD_DETECT_ENABLE = 8; literal PD6729$K_MEM_MAP_ENABLE_0 = 1; literal PD6729$K_MEM_MAP_ENABLE_1 = 2; literal PD6729$K_MEM_MAP_ENABLE_2 = 4; literal PD6729$K_MEM_MAP_ENABLE_3 = 8; literal PD6729$K_MEM_MAP_ENABLE_4 = 16; literal PD6729$K_IO_MAP_ENABLE_0 = 64; literal PD6729$K_IO_MAP_ENABLE_1 = 128; literal PD6729$K_CARD_DETECT_MASK = 12; literal PD6729$K_NO_CARD = 0; literal PD6729$K_CARD_DETECT = 12; literal PD6729$K_PD6729_INTA = 3; literal PD6729$K_PD6729_INTB = 4; literal PD6729$K_PD6729_INTC = 5; literal PD6729$K_PD6729_INTD = 7; !*** MODULE $PDTLISTDEF *** ! + ! SCS PDT LIST (TYC 15-Feb-89) ! ! THIS DATA STRUCTURE CONTAINS A VECTOR LISTING UP TO 32 PDT ADDRESSES OF ! DYNAMIC LOAD SHARING PORTS. THE INDEX IS MAINTAINED IN THE SCS ! LOAD SHARING PORT BIT MAP. ! - literal PDTLIST$C_MAX_INDEX = 32; literal PDTLIST$K_LENGTH = 140; literal PDTLIST$C_LENGTH = 140; literal PDTLIST$S_PDTLISTDEF = 16; literal PDTLIST$S_PDTLIST = 16; macro PDTLIST$L_FLINK = -12,0,32,1 %; ! FWD LINK macro PDTLIST$L_BLINK = -8,0,32,1 %; ! BCK LINK macro PDTLIST$W_SIZE = -4,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro PDTLIST$B_TYPE = -2,0,8,0 %; ! SCS STRUCTURE TYPE macro PDTLIST$B_SUBTYP = -1,0,8,0 %; ! SCS STRUCTURE SUBTYPE FOR PDTLIST macro PDTLIST$L_PDTADDR = 0,0,32,1 %; ! FIRST PDT ADDRESS !*** MODULE $PEMCLSTDEF *** literal CLST$S_CLSTDEF = 52; macro CLST$A_FAILURE_FLINK = 0,0,32,0 %; macro CLST$A_FAILURE_BLINK = 4,0,32,0 %; macro CLST$W_SIZE = 8,0,16,0 %; macro CLST$B_TYPE = 10,0,8,0 %; macro CLST$B_SUBTYPE = 11,0,8,0 %; macro CLST$L_COMP_ENTRIES = 12,0,32,0 %; macro CLST$A_CLST_FLINK = 16,0,32,0 %; macro CLST$A_CLST_BLINK = 20,0,32,0 %; macro CLST$A_HW_HASH_LINK = 24,0,32,0 %; macro CLST$A_DECNET_HASH_LINK = 28,0,32,0 %; macro CLST$A_LOCAL_ADAPTER = 32,0,32,0 %; macro CLST$A_REMOTE_ADAPTER = 36,0,32,0 %; macro CLST$A_PACKET_LOSS_FLINK = 40,0,32,0 %; macro CLST$A_PACKET_LOSS_BLINK = 44,0,32,0 %; macro CLST$L_REFERENCE_COUNT = 48,0,32,0 %; macro CLST$AA_COMP_LIST = 52,0,0,0 %; !*** MODULE $PEMCOMPDEF *** literal COMP$C_MAX_NAME_LEN = 110; literal COMP$C_NODE = 1; literal COMP$C_ADAPTER = 2; literal COMP$C_COMPONENT = 3; literal COMP$C_CLOUD = 4; literal COMP$C_INVALID = 5; literal COMP$M_HW_ADDR_VALID = %X'1'; literal COMP$M_DECNET_ADDR_VALID = %X'2'; literal COMP$M_PRIMARY_SUSPECT = %X'4'; literal COMP$M_SECONDARY_SUSPECT = %X'8'; literal COMP$M_PRIMARY_LOSS_SUSPECT = %X'10'; literal COMP$M_SECONDARY_LOSS_SUSPECT = %X'20'; literal COMP$M_CLEAR_LOSS_COUNT = %X'40'; literal COMP$S_COMPDEF = 72; macro COMP$A_SUSPECT_FLINK = 0,0,32,0 %; macro COMP$A_SUSPECT_BLINK = 4,0,32,0 %; macro COMP$W_SIZE = 8,0,16,0 %; macro COMP$B_TYPE = 10,0,8,0 %; macro COMP$B_SUBTYPE = 11,0,8,0 %; macro COMP$B_NAME_LEN = 12,0,8,0 %; macro COMP$B_NODENAME_LEN = 13,0,8,0 %; macro COMP$B_COMP_TYPE = 14,0,8,0 %; macro COMP$B_FLAGS = 15,0,8,0 %; macro COMP$V_HW_ADDR_VALID = 15,0,1,0 %; macro COMP$V_DECNET_ADDR_VALID = 15,1,1,0 %; macro COMP$V_PRIMARY_SUSPECT = 15,2,1,0 %; macro COMP$V_SECONDARY_SUSPECT = 15,3,1,0 %; macro COMP$V_PRIMARY_LOSS_SUSPECT = 15,4,1,0 %; macro COMP$V_SECONDARY_LOSS_SUSPECT = 15,5,1,0 %; macro COMP$V_CLEAR_LOSS_COUNT = 15,6,1,0 %; macro COMP$A_NAME = 16,0,32,0 %; macro COMP$AB_HW_ADDR = 20,0,0,0 %; literal COMP$S_HW_ADDR = 6; macro COMP$AB_DECNET_ADDR = 26,0,0,0 %; literal COMP$S_DECNET_ADDR = 6; macro COMP$A_COMP_FLINK = 32,0,32,0 %; macro COMP$A_COMP_BLINK = 36,0,32,0 %; macro COMP$L_REFERENCE_COUNT = 40,0,32,0 %; macro COMP$L_WORKING_COUNT = 44,0,32,0 %; macro COMP$L_SUSPECT_COUNT = 48,0,32,0 %; macro COMP$L_PRIME_SUSPECT = 52,0,32,0 %; macro COMP$L_SECONDARY_SUSPECT = 56,0,32,0 %; macro COMP$L_PACKET_LOSS = 60,0,32,0 %; macro COMP$A_PACKET_LOSS_FLINK = 64,0,32,0 %; macro COMP$A_PACKET_LOSS_BLINK = 68,0,32,0 %; !*** MODULE $PFBDEF *** ! + ! PAGE FAULT MONITOR BUFFER ! - literal PFB$B_USER_BUFFER = 12; literal PFB$B_BUFFER = 20; ! Beginning of PC/VA pairs literal PFB$K_LENGTH = 524; ! Length of PFB literal PFB$C_LENGTH = 524; ! Length of PFB literal PFB$S_PFBDEF = 524; literal PFB$S_PFB = 524; macro PFB$L_FLINK = 0,0,32,1 %; ! Forward link macro PFB$L_BLINK = 4,0,32,1 %; ! Back link macro PFB$W_SIZE = 8,0,16,0 %; ! Structure size macro PFB$B_TYPE = 10,0,8,0 %; ! Dynamic structure type (PFB) macro PFB$R_USER_BUFFER = 12,0,0,0 %; literal PFB$S_USER_BUFFER = 512; ! Buffer returned to user macro PFB$L_RECCNT = 12,0,32,0 %; ! Record count macro PFB$L_OVERFLOW = 16,0,32,0 %; ! Overflow count !*** MODULE $PFLDEF *** ! + ! PAGE FILE CONTROL BLOCK ! - ! ! ***** L_VBN, L_WINDOW, and L_PFC must be the same offset values as the ! ***** equivalently named offsets in $SECDEF ! literal PFL$M_INITED = %X'1'; literal PFL$M_PAGFILFUL = %X'2'; literal PFL$M_SWPFILFUL = %X'4'; literal PFL$M_SWAP_FILE = %X'8'; literal PFL$M_DINSPEN = %X'10'; literal PFL$M_STOPPER = %X'80000000'; literal PFL$K_MAX_EXPO_INDEX = 6; ! Length of DIR_CLUSTERS array; in a quad are literal PFL$C_MAX_EXPO_INDEX = 6; ! at most 2@6 = 64 bits set... literal PFL$K_ALLOC2DIR_SHIFT = 4; ! Shift right to get literal PFL$C_ALLOC2DIR_SHIFT = 4; ! directory bit count literal PFL$K_ALLOC2DIR_SIZE = 16; ! Number of bits covered literal PFL$C_ALLOC2DIR_SIZE = 16; ! by 1 directory bit literal PFL$M_ALLOC2DIR_MASK = 65535; ! Bitmask covering bits ! per dir bit literal PFL$K_LENGTH = 156; ! SIZE OF PAGE FILE CONTROL BLOCK literal PFL$C_LENGTH = 156; ! SIZE OF PAGE FILE CONTROL BLOCK literal PFL$S_PFLDEF = 164; ! Old size name - synonym literal PFL$S_PFL = 168; macro PFL$L_FLINK = 0,0,32,1 %; ! Forward link to next PFL macro PFL$L_BLINK = 4,0,32,1 %; ! Back link to previous PFL macro PFL$W_SIZE = 8,0,16,0 %; ! SIZE OF PAGE FILE CONTROL BLOCK macro PFL$B_TYPE = 10,0,8,0 %; ! PAGE FILE CONTROL BLOCK TYPE CODE macro PFL$L_PFC = 12,0,32,0 %; ! PAGE FAULT CLUSTER FOR PAGE READS macro PFL$L_VBN = 16,0,32,0 %; macro PFL$Q_VBN = 16,0,0,0 %; literal PFL$S_VBN = 8; macro PFL$L_WINDOW = 24,0,32,1 %; ! WINDOW ADDRESS macro PFL$L_BITMAPSIZ = 28,0,32,0 %; ! SIZE IN BYTES OF PAGE FILE macro PFL$L_FREPAGCNT = 32,0,32,0 %; ! COUNT - 1 OF PAGES WHICH MAY BE ALLOCATED ! BIT = 1 MEANS AVAILABLE macro PFL$PQ_BITMAP = 40,0,0,1 %; literal PFL$S_BITMAP = 8; macro PFL$L_BITMAP = 40,0,32,1 %; ! ADDRESS OF START OF BIT MAP macro PFL$L_BITMAP_HI = 44,0,32,0 %; macro PFL$PQ_BITMAP_DIR = 48,0,0,1 %; literal PFL$S_BITMAP_DIR = 8; ! Pointer to bitmap "directory" macro PFL$Q_LAST_DIR_QUAD = 56,0,0,0 %; literal PFL$S_LAST_DIR_QUAD = 8; ! Save initial value of last directory quad macro PFL$L_ALLOCSIZ = 64,0,32,0 %; ! CURRENT ALLOCATION REQUEST SIZE macro PFL$L_RSRVPAGCNT = 68,0,32,0 %; ! Count of pages which may be reserved macro PFL$L_SWPREFCNT = 72,0,32,0 %; ! No. of processes using this file for swapping macro PFL$L_POOLBYTES = 76,0,32,1 %; ! Save actually allocated pool size macro PFL$L_S2PAGES = 80,0,32,1 %; ! and number of S2 pages for deallocation macro PFL$L_MINFREPAGCNT = 84,0,32,0 %; ! Minimum free page count macro PFL$L_PGFLX = 88,0,32,0 %; ! Page file vector index macro PFL$L_FLAGS = 92,0,32,0 %; ! FLAGS FOR THIS PAGE FILE macro PFL$V_INITED = 92,0,1,0 %; ! THIS PAGE FILE IS USABLE macro PFL$V_PAGFILFUL = 92,1,1,0 %; ! REQUEST FOR PAGING SPACE HAS FAILED macro PFL$V_SWPFILFUL = 92,2,1,0 %; ! REQUEST FOR SWAPPING SPACE HAS FAILED macro PFL$V_SWAP_FILE = 92,3,1,0 %; ! This is a swap file macro PFL$V_DINSPEN = 92,4,1,0 %; ! File deinstall pending macro PFL$V_STOPPER = 92,31,1,0 %; ! RESERVED FOR ALL TIME (MUST NEVER BE SET) macro PFL$L_REFCNT = 96,0,32,0 %; ! No. of pages used in this pagefile macro PFL$L_MAXVBN = 100,0,32,0 %; ! MASK APPLIED TO PTE WITH PAGING FILE ! BACKING STORE ADDRESS macro PFL$L_STARTBYTE = 104,0,32,1 %; ! Starting byte offset for next scan macro PFL$L_MAX_ALLOC_EXPO = 108,0,32,1 %; ! Look for 2**"this" consecutive directory bits macro PFL$L_CUR_ALLOC_EXPO = 112,0,32,1 %; ! Current allocation size exponent macro PFL$L_BITMAP_QUADS = 116,0,32,1 %; ! Bitmap size in quadwords macro PFL$L_DIR_QUADS = 120,0,32,1 %; ! Directory size in quadwords macro PFL$L_DIR_CLUSTER = 124,0,0,1 %; literal PFL$S_DIR_CLUSTER = 32; ! Counters of directory clusters by size macro PFL$L_BITMAPLOC = 160,0,32,0 %; ! BITMAP MUST be at last and quad aligned ! if it's included here !*** MODULE $PFLMAPDEF *** ! + ! PAGE FILE MAPPING WINDOW BLOCK ! - literal PFLMAP$M_PGFLPAG = %X'FFFFFF'; literal PFLMAP$M_PGFLX = %X'FF000000'; literal PFLMAP$M_PAGCNT = %X'FFFFFFFF00000000'; literal PFLMAP$S_PFLMAPENTRY = 8; macro PFLMAP$V_PGFLPAG = 0,0,24,0 %; literal PFLMAP$S_PGFLPAG = 24; ! Page file page number macro PFLMAP$V_PGFLX = 0,24,8,0 %; literal PFLMAP$S_PGFLX = 8; ! Page file index macro PFLMAP$V_PAGCNT = 4,0,32,0 %; literal PFLMAP$S_PAGCNT = 32; ! Pages in this pointer literal PFLMAP$C_SHIFT_COUNT = 6; literal PFLMAP$C_MAXPTRS = 64; literal PFLMAP$K_LENGTH = 536; ! Size of structure literal PFLMAP$C_LENGTH = 536; ! Size of structure literal PFLMAP$S_PFLMAPDEF = 536; literal PFLMAP$S_PFLMAP = 536; macro PFLMAP$L_PAGECNT = 0,0,32,0 %; ! Total pages in all pointers macro PFLMAP$W_SIZE = 8,0,16,0 %; ! Size of structure macro PFLMAP$B_TYPE = 10,0,8,0 %; ! Structure type (DYN$C_PFLMAP) macro PFLMAP$B_ACTPTRS = 11,0,8,0 %; ! No. of active pointers in window ! Allow for 2**sc pointers macro PFLMAP$Q_PTR = 16,0,0,0 %; literal PFLMAP$S_PTR = 520; ! Beginning of mapping pointers !*** MODULE $PFREEDEF *** ! + ! PFREE - Pool free block ! ! This defines the common layout of a pool free block. Some fields are used ! only by pool checking code. NOTE WELL: Some of these fields must be at the ! same offsets as in the fork block. ! - literal PFREE$K_LENGTH = 36; ! Length of poisoned block header literal PFREE$S_PFREEDEF = 36; literal PFREE$S_PFREE = 40; macro PFREE$L_FLINK = 0,0,32,1 %; ! Forward link macro PFREE$L_BLINK = 4,0,32,1 %; ! Queue backward link macro PFREE$L_FREE_SIZE = 4,0,32,0 %; ! Free block size macro PFREE$W_SIZE = 8,0,16,0 %; ! Standard size field macro PFREE$B_TYPE = 10,0,8,0 %; ! Standard type field macro PFREE$B_FLCK = 11,0,8,0 %; ! Fork lock index macro PFREE$B_RMOD = 11,0,8,0 %; ! Request mode macro PFREE$B_SUBTYPE = 11,0,8,0 %; ! Block subtype macro PFREE$L_DEAL_PC = 12,0,32,1 %; ! Deallocater return PC macro PFREE$L_FPC = 12,0,32,1 %; ! Fork PC macro PFREE$L_IPL = 16,0,32,0 %; ! COM$DRVDEALMEM IPL macro PFREE$Q_FR3 = 16,0,0,1 %; literal PFREE$S_FR3 = 8; ! Fork R3 macro PFREE$L_CDDM_PC = 24,0,32,1 %; ! COM$DRVDEALMEM return PC macro PFREE$Q_FR4 = 24,0,0,1 %; literal PFREE$S_FR4 = 8; ! Fork R4 macro PFREE$L_CHECKSUM = 32,0,32,0 %; ! Pool poisoning checksum !*** MODULE $PFSDEF *** literal PFS$M_PFM = %X'3FFFFFFFFF'; literal PFS$M_PEC = %X'3F0000000000000'; literal PFS$M_PPL = %X'C000000000000000'; literal PFS$S_PFS = 8; ! ! Previous Function State Register ! *************************************** macro PFS$IQ_PREV_FUNC_STATE = 0,0,0,0 %; literal PFS$S_PREV_FUNC_STATE = 8; macro PFS$V_PFM = 0,0,38,0 %; literal PFS$S_PFM = 38; ! Previous frame marker macro PFS$V_RV1 = 4,6,14,0 %; literal PFS$S_RV1 = 14; ! Reserved macro PFS$V_PEC = 4,20,6,0 %; literal PFS$S_PEC = 6; ! Previous epilog count macro PFS$V_RV2 = 4,26,4,0 %; literal PFS$S_RV2 = 4; ! Reserved macro PFS$V_PPL = 4,30,2,0 %; literal PFS$S_PPL = 2; ! Previous Privilege Level !*** MODULE $PHDDEF *** ! ! Process Header Definitions. The process header contains the swappable ! scheduler and memory management data bases for a process in the balance set. ! literal PHD$M_ASTEN = %X'F'; literal PHD$M_ASTSR = %X'F0'; literal PHD$M_ASTEN_KEN = %X'1'; literal PHD$M_ASTEN_EEN = %X'2'; literal PHD$M_ASTEN_SEN = %X'4'; literal PHD$M_ASTEN_UEN = %X'8'; literal PHD$M_ASTSR_KPD = %X'10'; literal PHD$M_ASTSR_EPD = %X'20'; literal PHD$M_ASTSR_SPD = %X'40'; literal PHD$M_ASTSR_UPD = %X'80'; literal PHD$M_PME = %X'4'; literal PHD$M_AC = %X'8'; literal PHD$M_MFL = %X'10'; literal PHD$M_MFH = %X'20'; literal PHD$M_DFH = %X'80000'; literal PHD$C_HWPCBLEN = 352; ! Length of HWPCB literal PHD$K_HWPCBLEN = 352; ! Length of HWPCB ! literal PHD$C_FPR_COUNT = 32; ! Count of saved FP registers literal PHD$K_FPR_COUNT = 32; ! Count of saved FP registers literal PHD$M_SW_FEN = %X'1'; literal PHD$M_AST_PENDING = %X'80000000'; literal PHD$M_PFMFLG = %X'1'; literal PHD$M_DALCSTX = %X'2'; literal PHD$M_WSPEAKCHK = %X'4'; literal PHD$M_NOACCVIO = %X'8'; literal PHD$M_IWSPEAKCK = %X'10'; literal PHD$M_IMGDMP = %X'20'; literal PHD$M_NO_WS_CHNG = %X'40'; literal PHD$M_SPARE_8 = %X'80'; literal PHD$M_LOCK_HEADER = %X'100'; literal PHD$M_FREWSLE_ACTIVE = %X'200'; literal PHD$K_LENGTH = 2928; ! Length of fixed part of process header literal PHD$C_LENGTH = 2928; ! Length of fixed part of the process header literal PHD$S_PHD = 2928; macro PHD$Q_PRIVMSK = 0,0,0,0 %; literal PHD$S_PRIVMSK = 8; ! Privilege mask macro PHD$W_SIZE = 8,0,16,0 %; ! Structure size macro PHD$B_TYPE = 10,0,8,0 %; ! Dynamic structure type (PHD) ! ! Working set list pointers - these contain longword offsets from the beginning ! of the process header. ! macro PHD$L_WSLIST = 12,0,32,0 %; ! 1st working set list entry macro PHD$L_WSLOCK = 16,0,32,0 %; ! 1st locked working set list entry macro PHD$L_WSDYN = 20,0,32,0 %; ! 1st dynamic working set list entry macro PHD$L_WSNEXT = 24,0,32,0 %; ! Last WSL entry replaced macro PHD$L_WSLAST = 28,0,32,0 %; ! Last WSL entry in list ! ! The following three longwords specify the maximum and initial working set ! sizes for the process. Rather than containing the count of pages, they ! contains the longword index to what would be the last working set list entry. ! macro PHD$L_WSEXTENT = 32,0,32,0 %; ! Max working set size against borrowing macro PHD$L_WSQUOTA = 36,0,32,0 %; ! Quota on working set size macro PHD$L_DFWSCNT = 40,0,32,0 %; ! Default working set size macro PHD$L_CPULIM = 44,0,32,0 %; ! Limit on CPU time for process ! ! Process Section Table data base - PST_BASE_OFFSET is the byte offset ! from the beginning of the process header to the first longword beyond ! the process section table. PST_LAST and PST_FREE are section table ! indices to section table entries. ! macro PHD$L_PST_BASE_OFFSET = 48,0,32,0 %; ! Byte offset to base of PST ! First longword not in PST ! PST grows backwards from here macro PHD$L_PST_LAST = 52,0,32,0 %; ! End of process section table ! (index of last PSTE allocated) macro PHD$L_PST_FREE = 56,0,32,0 %; ! Head of free PSTE list ! (index of first free PSTE) ! ! MMG Context ! macro PHD$L_IOREFC = 60,0,32,0 %; ! Num reasons to keep PHD resident due to pages locked for I/O macro PHD$Q_NEXT_REGION_ID = 64,0,0,0 %; literal PHD$S_NEXT_REGION_ID = 8; ! Next user-defined region id macro PHD$L_PST_BASE_MAX = 72,0,32,1 %; ! section index of top PST macro PHD$L_EMPTPG = 76,0,32,0 %; ! Count of empty working set pages macro PHD$L_DFPFC = 80,0,32,0 %; ! Default page fault cluster macro PHD$L_PGTBPFC = 84,0,32,0 %; ! Page table cluster factor ! ! Quotas and Limits ! macro PHD$L_ASTLM = 88,0,32,0 %; ! AST limit macro PHD$L_PSHARED = 92,0,32,0 %; ! process shared object flag macro PHD$L_WSSIZE = 96,0,32,0 %; ! Current allowed working set size macro PHD$L_DIOCNT = 100,0,32,0 %; ! Direct I/O count macro PHD$L_BIOCNT = 104,0,32,0 %; ! Buffered I/O count macro PHD$L_PHVINDEX = 108,0,32,0 %; ! Process header vector index macro PHD$Q_FREDPTR = 112,0,0,1 %; literal PHD$S_FREDPTR = 8; ! pointer to first FRED page macro PHD$Q_LEFC = 120,0,0,0 %; literal PHD$S_LEFC = 8; ! Local event flags macro PHD$L_LEFC_0 = 120,0,32,0 %; ! Cluster 0 macro PHD$L_LEFC_1 = 124,0,32,0 %; ! Cluster 1 ! ! Hardware Privileged Context Block (HWPCB) - This structure must be aligned to ! a 128 byte boundary. Natural alignment prevents the structure from crossing a ! page boundary. ! ! NOTE WELL: There are bit symbols defined here for accessing the saved ASTEN, ! ASTSR, FEN and DATFX values in the HWPCB. These symbols are NOT to be used when ! interfacing to the ASTEN, ASTSR, FEN or DATFX internal processor registers directly. ! See the specific internal register definitions for bitmasks and constants ! to be used when interfacing to the IPRs directly. ! macro PHD$Q_HWPCB = 128,0,0,0 %; literal PHD$S_HWPCB = 8; ! Base of HWPCB macro PHD$Q_KSP = 128,0,0,0 %; literal PHD$S_KSP = 8; ! Kernel stack pointer macro PHD$Q_ESP = 136,0,0,0 %; literal PHD$S_ESP = 8; ! Executive stack pointer macro PHD$Q_SSP = 144,0,0,0 %; literal PHD$S_SSP = 8; ! Supervisor stack pointer macro PHD$Q_USP = 152,0,0,0 %; literal PHD$S_USP = 8; ! User stack pointer ! Verified for IA64 port - KLN macro PHD$Q_KPFS = 160,0,0,0 %; literal PHD$S_KPFS = 8; ! PFS of thread switched out macro PHD$Q_KRNAT = 168,0,0,0 %; literal PHD$S_KRNAT = 8; ! RNAT of thread switched out macro PHD$PQ_KBSP = 176,0,0,1 %; literal PHD$S_KBSP = 8; ! Kernel Backing Store Pointer macro PHD$PQ_EBSP = 184,0,0,1 %; literal PHD$S_EBSP = 8; ! Exec Backing Store Pointer macro PHD$PQ_SBSP = 192,0,0,1 %; literal PHD$S_SBSP = 8; ! Supervisor Backing Store Pointer macro PHD$PQ_UBSP = 200,0,0,1 %; literal PHD$S_UBSP = 8; ! User Backing Store Pointer ! Verified for IA64 port - KLN macro PHD$Q_PTBR = 208,0,0,0 %; literal PHD$S_PTBR = 128; ! Page table PFN (Only VRNX 0,15 are used) macro PHD$Q_ASN = 336,0,0,0 %; literal PHD$S_ASN = 64; ! ASN/Region IDs (only VRN 0,7 used) macro PHD$Q_ASTSR_ASTEN = 400,0,0,0 %; literal PHD$S_ASTSR_ASTEN = 8; ! ASTSR / ASTEN quadword macro PHD$V_ASTEN = 400,0,4,0 %; literal PHD$S_ASTEN = 4; ! AST Enable Register macro PHD$V_ASTSR = 400,4,4,0 %; literal PHD$S_ASTSR = 4; ! AST Pending Summary Register macro PHD$V_ASTEN_KEN = 400,0,1,0 %; ! Kernel AST Enable = 1 macro PHD$V_ASTEN_EEN = 400,1,1,0 %; ! Executive AST Enable = 1 macro PHD$V_ASTEN_SEN = 400,2,1,0 %; ! Supervisor AST Enable = 1 macro PHD$V_ASTEN_UEN = 400,3,1,0 %; ! User AST Enable = 1 macro PHD$V_ASTSR_KPD = 400,4,1,0 %; ! Kernel AST Pending = 1 macro PHD$V_ASTSR_EPD = 400,5,1,0 %; ! Executive AST Pending = 1 macro PHD$V_ASTSR_SPD = 400,6,1,0 %; ! Supervisor AST Pending = 1 macro PHD$V_ASTSR_UPD = 400,7,1,0 %; ! User AST Pending = 1 ! Process Attributes Section replaces Alpha FEN quadword macro PHD$IQ_PAS = 408,0,0,0 %; literal PHD$S_PAS = 8; ! Floating Point Disable / modified / PME / DATFX macro PHD$IL_PAS_L = 408,0,32,0 %; macro PHD$IL_PAS_H = 412,0,32,0 %; macro PHD$V_PME = 408,2,1,0 %; ! Performance Monitor Enable macro PHD$V_AC = 408,3,1,0 %; ! Data Alignment Check macro PHD$V_MFL = 408,4,1,0 %; ! Low FPRs modified macro PHD$V_MFH = 408,5,1,0 %; ! High FPRs modified macro PHD$V_DFH = 408,19,1,0 %; ! High Floating Point Disable ! fill_44 bitfield length 44 fill; macro PHD$Q_CC = 416,0,0,0 %; literal PHD$S_CC = 8; ! Cycle Counter macro PHD$Q_UNQ = 424,0,0,0 %; literal PHD$S_UNQ = 8; ! Process Unique Value (IA64 R13) macro PHD$B_PMOD = 432,0,8,0 %; ! Previous mode macro PHD$B_RESERVED_1 = 433,0,0,1 %; literal PHD$S_RESERVED_1 = 7; macro PHD$Q_PAL_RSVD = 440,0,0,1 %; literal PHD$S_PAL_RSVD = 40; ! Reserved for PAL Scratch ! End of Hardware Privileged Context Block (HWPCB). ! ! ! Floating Point Register Save Area. There is space for 32 floating ! point registers, F0 through F30, and the FPCR. Note that F31 is a ! fixed sink register that doesn't need to be saved. ! macro PHD$Q_FPR = 480,0,0,1 %; literal PHD$S_FPR = 1936; ! Space for 120 FP regs plus FP status and alignment macro PHD$Q_FPSR = 480,0,0,0 %; literal PHD$S_FPSR = 8; ! ar.fpsr, floating point status register macro PHD$q_reserved_2 = 488,0,0,0 %; literal PHD$s_reserved_2 = 8; ! alignment macro PHD$Q_F2 = 496,0,0,0 %; literal PHD$S_F2 = 16; ! F2 macro PHD$Q_F3 = 512,0,0,0 %; literal PHD$S_F3 = 16; ! F3 macro PHD$Q_F4 = 528,0,0,0 %; literal PHD$S_F4 = 16; ! F4 macro PHD$Q_F5 = 544,0,0,0 %; literal PHD$S_F5 = 16; ! F5 macro PHD$Q_F12 = 560,0,0,0 %; literal PHD$S_F12 = 16; ! F12 macro PHD$Q_F13 = 576,0,0,0 %; literal PHD$S_F13 = 16; ! F13 macro PHD$Q_F14 = 592,0,0,0 %; literal PHD$S_F14 = 16; ! F14 macro PHD$Q_F15 = 608,0,0,0 %; literal PHD$S_F15 = 16; ! F15 macro PHD$Q_F16 = 624,0,0,0 %; literal PHD$S_F16 = 16; ! F16 macro PHD$Q_F17 = 640,0,0,0 %; literal PHD$S_F17 = 16; ! F17 macro PHD$Q_F18 = 656,0,0,0 %; literal PHD$S_F18 = 16; ! F18 macro PHD$Q_F19 = 672,0,0,0 %; literal PHD$S_F19 = 16; ! F19 macro PHD$Q_F20 = 688,0,0,0 %; literal PHD$S_F20 = 16; ! F20 macro PHD$Q_F21 = 704,0,0,0 %; literal PHD$S_F21 = 16; ! F21 macro PHD$Q_F22 = 720,0,0,0 %; literal PHD$S_F22 = 16; ! F22 macro PHD$Q_F23 = 736,0,0,0 %; literal PHD$S_F23 = 16; ! F23 macro PHD$Q_F24 = 752,0,0,0 %; literal PHD$S_F24 = 16; ! F24 macro PHD$Q_F25 = 768,0,0,0 %; literal PHD$S_F25 = 16; ! F25 macro PHD$Q_F26 = 784,0,0,0 %; literal PHD$S_F26 = 16; ! F26 macro PHD$Q_F27 = 800,0,0,0 %; literal PHD$S_F27 = 16; ! F27 macro PHD$Q_F28 = 816,0,0,0 %; literal PHD$S_F28 = 16; ! F28 macro PHD$Q_F29 = 832,0,0,0 %; literal PHD$S_F29 = 16; ! F29 macro PHD$Q_F30 = 848,0,0,0 %; literal PHD$S_F30 = 16; ! F30 macro PHD$Q_F31 = 864,0,0,0 %; literal PHD$S_F31 = 16; ! High Bank of floating registers are stored here: ! There are any number of schemes possible to avoid saving and restoring under ! various situations. For example, there is no reason to save these if we got ! context switched after making a system service call, since they are scratch regs. ! For now, however, we will save them if and only if MFH is set. macro PHD$Q_F32 = 880,0,0,0 %; literal PHD$S_F32 = 16; macro PHD$Q_F33 = 896,0,0,0 %; literal PHD$S_F33 = 16; macro PHD$Q_F34 = 912,0,0,0 %; literal PHD$S_F34 = 16; macro PHD$Q_F35 = 928,0,0,0 %; literal PHD$S_F35 = 16; macro PHD$Q_F36 = 944,0,0,0 %; literal PHD$S_F36 = 16; macro PHD$Q_F37 = 960,0,0,0 %; literal PHD$S_F37 = 16; macro PHD$Q_F38 = 976,0,0,0 %; literal PHD$S_F38 = 16; macro PHD$Q_F39 = 992,0,0,0 %; literal PHD$S_F39 = 16; macro PHD$Q_F40 = 1008,0,0,0 %; literal PHD$S_F40 = 16; macro PHD$Q_F41 = 1024,0,0,0 %; literal PHD$S_F41 = 16; macro PHD$Q_F42 = 1040,0,0,0 %; literal PHD$S_F42 = 16; macro PHD$Q_F43 = 1056,0,0,0 %; literal PHD$S_F43 = 16; macro PHD$Q_F44 = 1072,0,0,0 %; literal PHD$S_F44 = 16; macro PHD$Q_F45 = 1088,0,0,0 %; literal PHD$S_F45 = 16; macro PHD$Q_F46 = 1104,0,0,0 %; literal PHD$S_F46 = 16; macro PHD$Q_F47 = 1120,0,0,0 %; literal PHD$S_F47 = 16; macro PHD$Q_F48 = 1136,0,0,0 %; literal PHD$S_F48 = 16; macro PHD$Q_F49 = 1152,0,0,0 %; literal PHD$S_F49 = 16; macro PHD$Q_F50 = 1168,0,0,0 %; literal PHD$S_F50 = 16; macro PHD$Q_F51 = 1184,0,0,0 %; literal PHD$S_F51 = 16; macro PHD$Q_F52 = 1200,0,0,0 %; literal PHD$S_F52 = 16; macro PHD$Q_F53 = 1216,0,0,0 %; literal PHD$S_F53 = 16; macro PHD$Q_F54 = 1232,0,0,0 %; literal PHD$S_F54 = 16; macro PHD$Q_F55 = 1248,0,0,0 %; literal PHD$S_F55 = 16; macro PHD$Q_F56 = 1264,0,0,0 %; literal PHD$S_F56 = 16; macro PHD$Q_F57 = 1280,0,0,0 %; literal PHD$S_F57 = 16; macro PHD$Q_F58 = 1296,0,0,0 %; literal PHD$S_F58 = 16; macro PHD$Q_F59 = 1312,0,0,0 %; literal PHD$S_F59 = 16; macro PHD$Q_F60 = 1328,0,0,0 %; literal PHD$S_F60 = 16; macro PHD$Q_F61 = 1344,0,0,0 %; literal PHD$S_F61 = 16; macro PHD$Q_F62 = 1360,0,0,0 %; literal PHD$S_F62 = 16; macro PHD$Q_F63 = 1376,0,0,0 %; literal PHD$S_F63 = 16; macro PHD$Q_F64 = 1392,0,0,0 %; literal PHD$S_F64 = 16; macro PHD$Q_F65 = 1408,0,0,0 %; literal PHD$S_F65 = 16; macro PHD$Q_F66 = 1424,0,0,0 %; literal PHD$S_F66 = 16; macro PHD$Q_F67 = 1440,0,0,0 %; literal PHD$S_F67 = 16; macro PHD$Q_F68 = 1456,0,0,0 %; literal PHD$S_F68 = 16; macro PHD$Q_F69 = 1472,0,0,0 %; literal PHD$S_F69 = 16; macro PHD$Q_F70 = 1488,0,0,0 %; literal PHD$S_F70 = 16; macro PHD$Q_F71 = 1504,0,0,0 %; literal PHD$S_F71 = 16; macro PHD$Q_F72 = 1520,0,0,0 %; literal PHD$S_F72 = 16; macro PHD$Q_F73 = 1536,0,0,0 %; literal PHD$S_F73 = 16; macro PHD$Q_F74 = 1552,0,0,0 %; literal PHD$S_F74 = 16; macro PHD$Q_F75 = 1568,0,0,0 %; literal PHD$S_F75 = 16; macro PHD$Q_F76 = 1584,0,0,0 %; literal PHD$S_F76 = 16; macro PHD$Q_F77 = 1600,0,0,0 %; literal PHD$S_F77 = 16; macro PHD$Q_F78 = 1616,0,0,0 %; literal PHD$S_F78 = 16; macro PHD$Q_F79 = 1632,0,0,0 %; literal PHD$S_F79 = 16; macro PHD$Q_F80 = 1648,0,0,0 %; literal PHD$S_F80 = 16; macro PHD$Q_F81 = 1664,0,0,0 %; literal PHD$S_F81 = 16; macro PHD$Q_F82 = 1680,0,0,0 %; literal PHD$S_F82 = 16; macro PHD$Q_F83 = 1696,0,0,0 %; literal PHD$S_F83 = 16; macro PHD$Q_F84 = 1712,0,0,0 %; literal PHD$S_F84 = 16; macro PHD$Q_F85 = 1728,0,0,0 %; literal PHD$S_F85 = 16; macro PHD$Q_F86 = 1744,0,0,0 %; literal PHD$S_F86 = 16; macro PHD$Q_F87 = 1760,0,0,0 %; literal PHD$S_F87 = 16; macro PHD$Q_F88 = 1776,0,0,0 %; literal PHD$S_F88 = 16; macro PHD$Q_F89 = 1792,0,0,0 %; literal PHD$S_F89 = 16; macro PHD$Q_F90 = 1808,0,0,0 %; literal PHD$S_F90 = 16; macro PHD$Q_F91 = 1824,0,0,0 %; literal PHD$S_F91 = 16; macro PHD$Q_F92 = 1840,0,0,0 %; literal PHD$S_F92 = 16; macro PHD$Q_F93 = 1856,0,0,0 %; literal PHD$S_F93 = 16; macro PHD$Q_F94 = 1872,0,0,0 %; literal PHD$S_F94 = 16; macro PHD$Q_F95 = 1888,0,0,0 %; literal PHD$S_F95 = 16; macro PHD$Q_F96 = 1904,0,0,0 %; literal PHD$S_F96 = 16; macro PHD$Q_F97 = 1920,0,0,0 %; literal PHD$S_F97 = 16; macro PHD$Q_F98 = 1936,0,0,0 %; literal PHD$S_F98 = 16; macro PHD$Q_F99 = 1952,0,0,0 %; literal PHD$S_F99 = 16; macro PHD$Q_F100 = 1968,0,0,0 %; literal PHD$S_F100 = 16; macro PHD$Q_F101 = 1984,0,0,0 %; literal PHD$S_F101 = 16; macro PHD$Q_F102 = 2000,0,0,0 %; literal PHD$S_F102 = 16; macro PHD$Q_F103 = 2016,0,0,0 %; literal PHD$S_F103 = 16; macro PHD$Q_F104 = 2032,0,0,0 %; literal PHD$S_F104 = 16; macro PHD$Q_F105 = 2048,0,0,0 %; literal PHD$S_F105 = 16; macro PHD$Q_F106 = 2064,0,0,0 %; literal PHD$S_F106 = 16; macro PHD$Q_F107 = 2080,0,0,0 %; literal PHD$S_F107 = 16; macro PHD$Q_F108 = 2096,0,0,0 %; literal PHD$S_F108 = 16; macro PHD$Q_F109 = 2112,0,0,0 %; literal PHD$S_F109 = 16; macro PHD$Q_F110 = 2128,0,0,0 %; literal PHD$S_F110 = 16; macro PHD$Q_F111 = 2144,0,0,0 %; literal PHD$S_F111 = 16; macro PHD$Q_F112 = 2160,0,0,0 %; literal PHD$S_F112 = 16; macro PHD$Q_F113 = 2176,0,0,0 %; literal PHD$S_F113 = 16; macro PHD$Q_F114 = 2192,0,0,0 %; literal PHD$S_F114 = 16; macro PHD$Q_F115 = 2208,0,0,0 %; literal PHD$S_F115 = 16; macro PHD$Q_F116 = 2224,0,0,0 %; literal PHD$S_F116 = 16; macro PHD$Q_F117 = 2240,0,0,0 %; literal PHD$S_F117 = 16; macro PHD$Q_F118 = 2256,0,0,0 %; literal PHD$S_F118 = 16; macro PHD$Q_F119 = 2272,0,0,0 %; literal PHD$S_F119 = 16; macro PHD$Q_F120 = 2288,0,0,0 %; literal PHD$S_F120 = 16; macro PHD$Q_F121 = 2304,0,0,0 %; literal PHD$S_F121 = 16; macro PHD$Q_F122 = 2320,0,0,0 %; literal PHD$S_F122 = 16; macro PHD$Q_F123 = 2336,0,0,0 %; literal PHD$S_F123 = 16; macro PHD$Q_F124 = 2352,0,0,0 %; literal PHD$S_F124 = 16; macro PHD$Q_F125 = 2368,0,0,0 %; literal PHD$S_F125 = 16; macro PHD$Q_F126 = 2384,0,0,0 %; literal PHD$S_F126 = 16; macro PHD$Q_F127 = 2400,0,0,0 %; literal PHD$S_F127 = 16; ! ! End of Floating Point Register Save Area. ! ! ! Note: The Alpha architecture defines that the FEN bit in HWPCB cannot ! be read, so a separate software FEN bit must be kept. For performance ! reasons, we make this bit the low-bit. ! ! Note2: This field must immediately follow the floating point register ! save area. Do not move this field. By placing this field after ! the FPR save area, this field can be referenced using $FREDDEF ! as well as this data structure. ! macro PHD$L_FLAGS2 = 2416,0,32,0 %; ! Flags2 longword macro PHD$V_SW_FEN = 2416,0,1,0 %; ! Software FEN bit macro PHD$V_AST_PENDING = 2416,31,1,0 %; ! AST pending optimization macro PHD$L_EXTRACPU = 2420,0,32,0 %; ! Accumulated CPU time limit extension macro PHD$Q_ASNSEQ = 2424,0,0,0 %; literal PHD$S_ASNSEQ = 8; ! Address Space Number (Region ID) Sequence macro PHD$L_EXTDYNWS = 2432,0,32,0 %; ! Extra dynamic working set list entries ! above required WSFLUID minimum macro PHD$L_PAGEFLTS = 2436,0,32,0 %; ! Count of page faults macro PHD$L_FOW_FLTS = 2440,0,32,0 %; ! Count of Fault On Write faults incurred macro PHD$L_FOR_FLTS = 2444,0,32,0 %; ! Count of Fault On Read faults incurred macro PHD$L_FOE_FLTS = 2448,0,32,0 %; ! Count of Fault On Execute faults incurred macro PHD$L_CPUTIM = 2452,0,32,0 %; ! Accumulated CPU time charged macro PHD$L_CPUMODE = 2456,0,32,0 %; ! Access mode to notify about cputime macro PHD$L_AWSMODE = 2460,0,32,0 %; ! Access mode flag for auto WS AST macro PHD$Q_WSL = 2464,0,0,1 %; literal PHD$S_WSL = 8; ! pointer to WSL ! ! Page Table Statistics ! macro PHD$L_PTCNTLCK = 2472,0,32,0 %; ! Count of page tables containing ! 1 or more locked WSLEs macro PHD$L_PTCNTVAL = 2476,0,32,0 %; ! Count of page tables containing ! 1 or more valid WSLEs macro PHD$L_PTCNTACT = 2480,0,32,0 %; ! Count of active page tables macro PHD$L_PTCNTMAX = 2484,0,32,0 %; ! Max count of page tables ! which have non-zero PTEs macro PHD$Q_LOGIN = 2488,0,0,0 %; literal PHD$S_LOGIN = 8; ! system time at process creation macro PHD$Q_VIRTPEAK = 2496,0,0,0 %; literal PHD$S_VIRTPEAK = 8; ! peak virtual size macro PHD$L_WSPEAK = 2504,0,32,0 %; ! peak workingset size macro PHD$L_WSFLUID = 2508,0,32,1 %; ! Guaranteed number of fluid WS pages macro PHD$L_WSAUTH = 2512,0,32,0 %; ! Authorized working set size macro PHD$L_WSAUTHEXT = 2516,0,32,0 %; ! Authorized WS extent macro PHD$L_RESLSTH = 2520,0,32,1 %; ! Pointer to resource list macro PHD$L_AUTHPRI = 2524,0,32,0 %; ! Initial process priority macro PHD$Q_AUTHPRIV = 2528,0,0,0 %; literal PHD$S_AUTHPRIV = 8; ! Authorized privileges mask macro PHD$Q_IMAGPRIV = 2536,0,0,0 %; literal PHD$S_IMAGPRIV = 8; ! Installed image privileges mask macro PHD$L_IMGCNT = 2544,0,32,0 %; ! Image counter bumped by SYSRUNDWN macro PHD$L_PFLTRATE = 2548,0,32,0 %; ! Page fault rate macro PHD$L_PFLREF = 2552,0,32,0 %; ! Page faults at end of last interval macro PHD$L_TIMREF = 2556,0,32,0 %; ! Time at end of last interval macro PHD$L_PGFLTIO = 2560,0,32,0 %; ! Count of pagefault I/O macro PHD$R_MIN_CLASS = 2564,0,0,0 %; literal PHD$S_MIN_CLASS = 20; ! Minimum authorized security clearance macro PHD$R_MAX_CLASS = 2584,0,0,0 %; literal PHD$S_MAX_CLASS = 20; ! Maximum authorized security clearance macro PHD$L_VOLUMES = 2604,0,32,0 %; ! count of volumes mounted macro PHD$Q_WSL_NEXT = 2608,0,0,1 %; literal PHD$S_WSL_NEXT = 8; ! VA of next page for WSL Expansion macro PHD$Q_WSL_LAST = 2616,0,0,1 %; literal PHD$S_WSL_LAST = 8; ! VA of last page for WSL Expansion macro PHD$Q_PAGEFILE_REFS = 2624,0,0,1 %; literal PHD$S_PAGEFILE_REFS = 8; ! process references to pagefiles macro PHD$L_PAGEFILE_REFS_LO = 2624,0,32,1 %; ! lo longword macro PHD$L_PAGEFILE_REFS_HI = 2628,0,32,1 %; ! hi longword macro PHD$Q_ISTART = 2632,0,0,0 %; literal PHD$S_ISTART = 8; ! image activation time ! ! ***** BE CAREFUL ABOUT SYNCHRONIZING ACCESS TO THESE FLAGS !! ***** ! ! Before adding new flags to this longword, READ and UNDERSTAND the following. ! ! Any new flag that requires a change to this synchronization model means that ! all references to the longword containing these flags must be reviewed. ! ! The current set of flags is synchronized in the following way. All flags are ! written only in process context. Therefore, their basic synchronization is ! by executing at IPL=IPL$_MMG. Note that this is NOT the same as saying that ! the MMG spinlock is needed. (Requiring all writes to occur under MMG would ! work, but it's overkill given the current set of flags.) ! ! Some of these flags are written at lower IPLs using Load-Locked/Store-Conditional ! sequences. This is OK, because any write at IPL$_MMG will cause the lower IPL ! write to be reexecuted. Writes at IPL$_MMG need not be interlocked since the writes ! are synchronized by virtue of occurring at the synchronization IPL. ! ! EXCEPTION !! ! ! If the flags are for the system PHD, then being at IPL$_MMG is not enough ! protection. In this case only, even the writes that occur at this IPL must ! be done as interlocked sequences since this is not a case of being limited ! to process context only. ! macro PHD$L_FLAGS = 2640,0,32,0 %; ! Flags longword macro PHD$V_PFMFLG = 2640,0,1,0 %; ! Page fault monitoring enabled macro PHD$V_DALCSTX = 2640,1,1,0 %; ! Need to deallocate section indices macro PHD$V_WSPEAKCHK = 2640,2,1,0 %; ! Check for new working set size (proc) macro PHD$V_NOACCVIO = 2640,3,1,0 %; ! Set after inswap of process header macro PHD$V_IWSPEAKCK = 2640,4,1,0 %; ! Check for new working set size (image) macro PHD$V_IMGDMP = 2640,5,1,0 %; ! Take image dump on error exit macro PHD$V_NO_WS_CHNG = 2640,6,1,0 %; ! No change to working set or swapping ! (Transient use by MMG code only) macro PHD$V_LOCK_HEADER = 2640,8,1,0 %; ! Do not swap process header ! (Transient use by MMG code only) macro PHD$V_FREWSLE_ACTIVE = 2640,9,1,0 %; ! FREWSLE critical section is active for ! a specific process context ! ! Cluster-Wide Process Services ! macro PHD$L_PSCANCTX_SEQNUM = 2644,0,32,0 %; ! PSCAN sequence number macro PHD$Q_PSCANCTX_QUEUE = 2648,0,0,0 %; literal PHD$S_PSCANCTX_QUEUE = 8; ! Queue of PSCAN blocks macro PHD$L_ICPUTIM = 2656,0,32,0 %; ! initial image CPU time macro PHD$L_IFAULTS = 2660,0,32,0 %; ! initial image fault count macro PHD$L_IFAULTIO = 2664,0,32,0 %; ! initial image fault I/O count macro PHD$L_IWSPEAK = 2668,0,32,0 %; ! image workingset peak macro PHD$L_IPAGEFL = 2672,0,32,0 %; ! image pagefile peak usage macro PHD$L_IDIOCNT = 2676,0,32,0 %; ! initial image direct I/O count macro PHD$L_IBIOCNT = 2680,0,32,0 %; ! initial image buffered I/O count macro PHD$L_IVOLUMES = 2684,0,32,0 %; ! initial image volume mount count ! ! PTE Backpointer range for process page table pages which cannot be deleted ! by the modified page writer due to VA space creation in progress. ! macro PHD$PQ_PT_NO_DELETE1 = 2688,0,0,1 %; literal PHD$S_PT_NO_DELETE1 = 8; ! Low PTE backpointer macro PHD$PQ_PT_NO_DELETE2 = 2696,0,0,1 %; literal PHD$S_PT_NO_DELETE2 = 8; ! High PTE backpointer macro PHD$Q_FREE_PTE_COUNT = 2704,0,0,0 %; literal PHD$S_FREE_PTE_COUNT = 8; ! Count of free PTEs ! ! Beginning of process permanent region descriptors for P0, P1 and P2 ! ** Warning *** ! The layout of the following fields must match rdedef.sdl ! ************** ! macro PHD$Q_P0_RDE = 2712,0,0,1 %; literal PHD$S_P0_RDE = 8; ! RDE for P0 space macro PHD$PS_P0_VA_LIST_FLINK = 2712,0,32,1 %; ! Pointer to first RDE in P0 macro PHD$PS_P0_VA_LIST_BLINK = 2716,0,32,1 %; ! Pointer to last RDE in P0 macro PHD$L_P0_FLAGS = 2728,0,32,0 %; ! P0 RDE flags macro PHD$L_P0_REGION_PROT = 2732,0,32,0 %; ! Region protection macro PHD$Q_P0_REGION_ID = 2736,0,0,0 %; literal PHD$S_P0_REGION_ID = 8; ! P0 region id macro PHD$PQ_P0_START_VA = 2744,0,0,1 %; literal PHD$S_P0_START_VA = 8; ! Starting address of P0 region macro PHD$Q_P0_REGION_SIZE = 2752,0,0,0 %; literal PHD$S_P0_REGION_SIZE = 8; ! Size of P0 region macro PHD$PQ_P0_FIRST_FREE_VA = 2760,0,0,1 %; literal PHD$S_P0_FIRST_FREE_VA = 8; ! 1st free VA at end of P0 space macro PHD$L_FREP0VA = 2760,0,32,1 %; ! 1st free VA at end of P0 space macro PHD$Q_P1_RDE = 2768,0,0,1 %; literal PHD$S_P1_RDE = 8; ! RDE for P0 space macro PHD$PS_P1_VA_LIST_FLINK = 2768,0,32,1 %; ! Pointer to first RDE in P0 macro PHD$PS_P1_VA_LIST_BLINK = 2772,0,32,1 %; ! Pointer to last RDE in P0 macro PHD$L_P1_FLAGS = 2784,0,32,0 %; ! P1 RDE flags macro PHD$L_P1_REGION_PROT = 2788,0,32,0 %; ! Region protection macro PHD$Q_P1_REGION_ID = 2792,0,0,0 %; literal PHD$S_P1_REGION_ID = 8; ! P1 region id macro PHD$PQ_P1_START_VA = 2800,0,0,1 %; literal PHD$S_P1_START_VA = 8; ! Starting address of P1 region macro PHD$Q_P1_REGION_SIZE = 2808,0,0,0 %; literal PHD$S_P1_REGION_SIZE = 8; ! Size of P1 region macro PHD$PQ_P1_FIRST_FREE_VA = 2816,0,0,1 %; literal PHD$S_P1_FIRST_FREE_VA = 8; ! 1st free VA at end of P1 space macro PHD$L_FREP1VA = 2816,0,32,1 %; ! 1st free VA at end of P1 space macro PHD$Q_P2_RDE = 2824,0,0,1 %; literal PHD$S_P2_RDE = 8; ! RDE for P0 space macro PHD$PS_P2_VA_LIST_FLINK = 2824,0,32,1 %; ! Pointer to first RDE in P0 macro PHD$PS_P2_VA_LIST_BLINK = 2828,0,32,1 %; ! Pointer to last RDE in P0 macro PHD$L_P2_FLAGS = 2840,0,32,0 %; ! P2 RDE flags macro PHD$L_P2_REGION_PROT = 2844,0,32,0 %; ! Region protection macro PHD$Q_P2_REGION_ID = 2848,0,0,0 %; literal PHD$S_P2_REGION_ID = 8; ! P2 region id macro PHD$PQ_P2_START_VA = 2856,0,0,1 %; literal PHD$S_P2_START_VA = 8; ! Starting address of P2 region macro PHD$Q_P2_REGION_SIZE = 2864,0,0,0 %; literal PHD$S_P2_REGION_SIZE = 8; ! Size of P2 region macro PHD$PQ_P2_FIRST_FREE_VA = 2872,0,0,1 %; literal PHD$S_P2_FIRST_FREE_VA = 8; ! 1st free VA at end of P2 space ! ! End of process permanent region descriptors for P0, P1 and P2 ! macro PHD$Q_IMAGE_AUTHPRIV = 2880,0,0,0 %; literal PHD$S_IMAGE_AUTHPRIV = 8; ! Installed image authorized privs macro PHD$Q_IMAGE_PERMPRIV = 2888,0,0,0 %; literal PHD$S_IMAGE_PERMPRIV = 8; ! Installed image initial privs macro PHD$AR_IMAGE_AUTHRIGHTS = 2896,0,32,1 %; ! Installed image authorized rights macro PHD$AR_IMAGE_RIGHTS = 2900,0,32,1 %; ! Installed image initial rights macro PHD$AR_SUBSYSTEM_AUTHRIGHTS = 2904,0,32,1 %; ! Subsystem authorized rights macro PHD$AR_SUBSYSTEM_RIGHTS = 2908,0,32,1 %; ! Subsystem initial rights ! ! For threaded processors, we have a field to hold fractional CPU time ticks ! macro PHD$Q_PARTIAL_CPUTIM_TICKS = 2912,0,0,0 %; literal PHD$S_PARTIAL_CPUTIM_TICKS = 8; ! Count up partial ticks for threaded processors ! ! End of the fixed portion of the process header. ! literal PHD$S_PHDDEF = 2928; ! Old size name - synonym !*** MODULE $PIBDEF *** ! + ! PERFORMANCE I/O INFORMATION BLOCK ! - literal PIB$S_PIBDEF = 1; ! Old size name - synonym literal PIB$S_PIB = 1; macro PIB$B_TYPE = 0,0,8,0 %; ! TYPE OF ENTRY ! ! START OF I/O REQUEST TRANSACTION MESSAGE BLOCK ! literal PIB$K_SRQ_SIZE = 32; ! LENGTH OF START I/O MESSAGE literal PIB$C_SRQ_SIZE = 32; ! LENGTH OF START I/O MESSAGE ! literal PIB$S_PIBDEF1 = 32; ! Old size name - synonym literal PIB$S_PIB1 = 32; macro PIB$B_SRQ_PRI = 1,0,8,0 %; ! BASE PRIORITY OF PROCESS macro PIB$W_SRQ_ACON = 2,0,16,0 %; ! Access control info from WCB or 0 macro PIB$Q_SRQ_TIME = 4,0,0,0 %; literal PIB$S_SRQ_TIME = 8; ! TIME OF I/O TRANSACTION macro PIB$L_SRQ_SEQN = 12,0,32,0 %; ! SEQUENCE NUMBER OF I/O TRANSACTION macro PIB$L_SRQ_PID = 16,0,32,0 %; ! REQUESTER PID macro PIB$L_SRQ_UCB = 20,0,32,1 %; ! ADDRESS OF DEVICE UCB macro PIB$W_SRQ_FUNC = 24,0,16,0 %; ! I/O FUNCTION CODE macro PIB$W_SRQ_STS = 26,0,16,0 %; ! I/O PACKET STATUS macro PIB$B_SRQ_ACCESS = 28,0,8,0 %; ! Access control info from WCB or 0 ! START OF I/O TRANSACTION MESSAGE BLOCK ! literal PIB$K_SIO_SIZE = 24; ! LENGTH OF I/O TRANSACTION MESSAGE literal PIB$C_SIO_SIZE = 24; ! LENGTH OF I/O TRANSACTION MESSAGE ! literal PIB$S_PIBDEF2 = 24; ! Old size name - synonym literal PIB$S_PIB2 = 24; macro PIB$Q_SIO_TIME = 4,0,0,0 %; literal PIB$S_SIO_TIME = 8; ! TIME OF TRANSACTION macro PIB$L_SIO_SEQN = 12,0,32,0 %; ! SEQUENCE NUMBER OF TRANSACTION macro PIB$L_SIO_MEDIA = 16,0,32,1 %; ! TRANSFER MEDIA ADDRESS macro PIB$L_SIO_BCNT = 20,0,32,0 %; ! TRANSFER BYTE COUNT ! END OF I/O TRANSACTION MESSAGE BLOCK ! literal PIB$K_EIO_SIZE = 24; ! LENGTH OF END OF I/O TRANSACTION literal PIB$C_EIO_SIZE = 24; ! LENGTH OF END OF I/O TRANSACTION ! literal PIB$S_PIBDEF3 = 24; ! Old size name - synonym literal PIB$S_PIB3 = 24; macro PIB$Q_EIO_TIME = 4,0,0,0 %; literal PIB$S_EIO_TIME = 8; ! TIME OF TRANSACTION macro PIB$L_EIO_SEQN = 12,0,32,0 %; ! SEQUENCE NUMBER OF TRANSACTION macro PIB$Q_EIO_IOSB = 16,0,0,0 %; literal PIB$S_EIO_IOSB = 8; ! FINAL I/O STATUS ! END OF I/O REQUEST MESSAGE BLOCK ! literal PIB$K_ERQ_SIZE = 16; ! LENGTH OF END OF I/O REQUEST TRANSACTION literal PIB$C_ERQ_SIZE = 16; ! LENGTH OF END OF I/O REQUEST TRANSACTION ! literal PIB$K_SRQ = 0; ! START OF I/O REQUEST literal PIB$K_SIO = 1; ! START OF I/O TRANSACTION literal PIB$K_EIO = 2; ! END OF I/O TRANSACTION literal PIB$K_ERQ = 3; ! END OF I/O REQUEST literal PIB$K_ARQ = 4; ! ABORTED I/O REQUEST literal PIB$S_PIBDEF4 = 16; ! Old size name - synonym literal PIB$S_PIB4 = 16; macro PIB$Q_ERQ_TIME = 4,0,0,0 %; literal PIB$S_ERQ_TIME = 8; ! TIME OF TRANSACTION macro PIB$L_ERQ_SEQN = 12,0,32,0 %; ! SEQUENCE NUMBER OF TRANSACTION ! I/O MESSAGE BLOCK ENTRY TYPE CODES ! literal PIB$K_ARQ_SIZE = 16; ! LENGTH OF ABORTED I/O TRANSACTION literal PIB$C_ARQ_SIZE = 16; ! LENGTH OF ABORTED I/O TRANSACTION ! literal PIB$S_PIBDEF5 = 16; ! Old size name - synonym literal PIB$S_PIB5 = 16; macro PIB$Q_ARQ_TIME = 4,0,0,0 %; literal PIB$S_ARQ_TIME = 8; ! TIME OF TRANSACTION macro PIB$L_ARQ_SEQN = 12,0,32,0 %; ! SEQUENCE NUMBER OF TRANSACTION ! ABORTED I/O REQUEST MESSAGE BLOCK ! !*** MODULE $PIPPDDEF *** literal PIPPD$C_OK = 0; literal PIPPD$C_VCC = 1; literal PIPPD$C_INVBN = 2; literal PIPPD$C_BLV = 3; literal PIPPD$C_ACCV = 4; literal PIPPD$C_NP = 5; literal PIPPD$C_PSV = 6; literal PIPPD$C_URP = 7; literal PIPPD$C_INVDP = 8; literal PIPPD$C_OSEQ = 9; literal PIPPD$C_DG = 1; literal PIPPD$C_MSG = 2; literal PIPPD$C_CNF = 3; literal PIPPD$C_IDREQ = 5; literal PIPPD$C_RST = 6; literal PIPPD$C_STRT = 7; literal PIPPD$C_DATREQ0 = 8; literal PIPPD$C_DATREQ1 = 9; literal PIPPD$C_DATREQ2 = 10; literal PIPPD$C_ID = 11; literal PIPPD$C_LB = 13; literal PIPPD$C_SNTDAT = 16; literal PIPPD$C_RETDAT = 17; literal PIPPD$C_DGREC = 33; literal PIPPD$C_MSGREC = 34; literal PIPPD$C_CNFREC = 35; literal PIPPD$C_IDREC = 43; literal PIPPD$C_DATREC = 49; literal PIPPD$M_OPCODE = %X'1F'; literal PIPPD$M_LP = %X'100'; literal PIPPD$M_NS = %X'E00'; literal PIPPD$M_M = %X'7000'; literal PIPPD$M_DATA = %X'10'; literal PIPPD$M_NR = %X'E00'; literal PIPPD$C_P0 = 1; literal PIPPD$C_P1 = 2; literal PIPPD$M_RP = %X'600'; literal PIPPD$M_SP = %X'3000'; literal PIPPD$M_FR = %X'8000'; literal PIPPD$M_DSA = %X'8000'; literal PIPPD$M_RSP = %X'1'; literal PIPPD$M_DISP = %X'2'; literal PIPPD$M_VC = %X'4'; literal PIPPD$M_Q = %X'18'; literal PIPPD$C_TEXT1 = 24; literal PIPPD$C_LENGTH = 26; literal PIPPD$C_START = 0; literal PIPPD$C_STACK = 1; literal PIPPD$C_ACK = 2; literal PIPPD$C_SCS_DG = 3; literal PIPPD$C_SCS_MSG = 4; literal PIPPD$C_ELOG = 5; literal PIPPD$C_HOSTSHUT = 6; literal PIPPD$C_FU_DG = 7; literal PIPPD$C_CACHECLR = 32768; literal PIPPD$C_CKTCLSD = 32769; literal PIPPD$C_CNF_LEN = 8; literal PIPPD$C_CNFREC_LEN = 8; literal PIPPD$C_DATREC_LEN = 8; literal PIPPD$C_IDREQ_LEN = 8; literal PIPPD$C_RST_LEN = 8; literal PIPPD$M_MAINT = %X'1'; literal PIPPD$C_UNINIT = 0; literal PIPPD$C_DISAB = 1; literal PIPPD$C_ENAB = 2; literal PIPPD$M_STATE = %X'6'; literal PIPPD$M_AST = %X'700'; literal PIPPD$M_XRPE = %X'800'; literal PIPPD$M_AARB = %X'1000'; literal PIPPD$M_XNR = %X'2000'; literal PIPPD$M_MAX_BODY_LEN = %X'1FFF0000'; literal PIPPD$M_CSZ = %X'E0000000'; literal PIPPD$M_NUM_MEMS = %X'FF'; literal PIPPD$M_SMV = %X'1000'; literal PIPPD$M_RDP_SUP = %X'2000'; literal PIPPD$M_FSN_SUP = %X'4000'; literal PIPPD$M_SA_SUP = %X'8000'; literal PIPPD$C_ID_LEN = 48; literal PIPPD$C_IDREC_LEN = 48; literal PIPPD$C_DATREQ_LEN = 28; literal PIPPD$C_SNTDAT_LEN = 16; literal PIPPD$C_RETDAT_LEN = 16; literal PIPPD$C_XXXDAT_LEN = 16; literal PIPPD$C_STRT_LEN = 12; literal PIPPD$S_PIPPD = 72; macro PIPPD$PS_FLINK = 0,0,32,1 %; macro PIPPD$PS_BLINK = 4,0,32,1 %; macro PIPPD$W_SIZE = 8,0,16,0 %; macro PIPPD$B_TYPE = 10,0,8,0 %; macro PIPPD$B_SUBTYPE = 11,0,8,0 %; macro PIPPD$PS_C710D = 12,0,32,1 %; macro PIPPD$B_PORT = 16,0,8,0 %; macro PIPPD$B_STATUS = 17,0,8,0 %; macro PIPPD$V_OPCODE = 18,0,5,0 %; literal PIPPD$S_OPCODE = 5; macro PIPPD$V_LP = 18,8,1,0 %; macro PIPPD$V_NS = 18,9,3,0 %; literal PIPPD$S_NS = 3; macro PIPPD$V_M = 18,12,3,0 %; literal PIPPD$S_M = 3; macro PIPPD$V_DATA = 18,4,1,0 %; macro PIPPD$V_NR = 18,9,3,0 %; literal PIPPD$S_NR = 3; macro PIPPD$V_RP = 18,9,2,0 %; literal PIPPD$S_RP = 2; macro PIPPD$V_SP = 18,12,2,0 %; literal PIPPD$S_SP = 2; macro PIPPD$V_FR = 18,15,1,0 %; macro PIPPD$V_DSA = 18,15,1,0 %; macro PIPPD$W_OPCODE = 18,0,16,0 %; macro PIPPD$V_RSP = 20,0,1,0 %; macro PIPPD$V_DISP = 20,1,1,0 %; macro PIPPD$V_VC = 20,2,1,0 %; macro PIPPD$V_Q = 20,3,2,0 %; literal PIPPD$S_Q = 2; macro PIPPD$W_FLAGS = 20,0,16,0 %; macro PIPPD$W_LENGTH1 = 22,0,16,0 %; macro PIPPD$B_TEXT1 = 24,0,8,0 %; macro PIPPD$W_LENGTH2 = 24,0,16,0 %; macro PIPPD$B_TEXT2 = 26,0,8,0 %; macro PIPPD$W_MTYPE = 26,0,16,0 %; macro PIPPD$Q_XCT_ID = 24,0,0,0 %; literal PIPPD$S_XCT_ID = 8; macro PIPPD$L_RPORT_TYP = 32,0,32,0 %; macro PIPPD$L_RPORT_REV = 36,0,32,0 %; macro PIPPD$L_RPORT_FCN = 40,0,32,0 %; macro PIPPD$B_RESET_PORT = 44,0,8,0 %; macro PIPPD$V_MAINT = 45,0,1,0 %; macro PIPPD$V_STATE = 45,1,2,0 %; literal PIPPD$S_STATE = 2; macro PIPPD$B_RPORT_STATE = 45,0,24,1 %; literal PIPPD$S_RPORT_STATE = 3; macro PIPPD$V_AST = 48,8,3,0 %; literal PIPPD$S_AST = 3; macro PIPPD$V_XRPE = 48,11,1,0 %; macro PIPPD$V_AARB = 48,12,1,0 %; macro PIPPD$V_XNR = 48,13,1,0 %; macro PIPPD$V_MAX_BODY_LEN = 48,16,13,0 %; literal PIPPD$S_MAX_BODY_LEN = 13; macro PIPPD$V_CSZ = 48,29,3,0 %; literal PIPPD$S_CSZ = 3; macro PIPPD$L_PORT_FCN_EXT1 = 48,0,32,0 %; macro PIPPD$V_NUM_MEMS = 52,0,8,0 %; literal PIPPD$S_NUM_MEMS = 8; macro PIPPD$V_SMV = 52,12,1,0 %; macro PIPPD$V_RDP_SUP = 52,13,1,0 %; macro PIPPD$V_FSN_SUP = 52,14,1,0 %; macro PIPPD$V_SA_SUP = 52,15,1,0 %; macro PIPPD$L_PORT_FCN_EXT2 = 52,0,32,0 %; macro PIPPD$Q_SUB_MAP = 56,0,0,0 %; literal PIPPD$S_SUB_MAP = 8; macro PIPPD$B_UNUSEDID = 64,0,0,0 %; literal PIPPD$S_UNUSEDID = 8; macro PIPPD$L_XCT_LEN = 32,0,32,0 %; macro PIPPD$L_SND_NAME = 36,0,32,0 %; macro PIPPD$L_SND_BOFF = 40,0,32,0 %; macro PIPPD$Q_SND_BUFF = 36,0,0,0 %; literal PIPPD$S_SND_BUFF = 8; macro PIPPD$L_REC_NAME = 44,0,32,0 %; macro PIPPD$L_REC_BOFF = 48,0,32,0 %; macro PIPPD$Q_REC_BUFF = 44,0,0,0 %; literal PIPPD$S_REC_BUFF = 8; macro PIPPD$Q_BUFF = 32,0,0,0 %; literal PIPPD$S_BUFF = 8; macro PIPPD$B_DATA = 40,0,8,0 %; macro PIPPD$L_ST_ADDR = 32,0,32,1 %; literal DSSI$C_STS_GOOD = 97; literal DSSI$C_MAX_PKT = 4114; literal DSSI$C_NUM_PAGES = 8; literal DSSI$C_RETRY_IMMED = 8; literal DSSI$C_RETRY_DELAY = 512; literal DSSI$C_TIMER = 100000; literal DSSI$C_CMD_DSSI = 224; literal DSSI$M_MBZ = %X'F'; literal DSSI$M_REQ_ACK = %X'F0'; literal DSSI$S_DSSI_CMD = 6; macro DSSI$B_OPCODE = 0,0,8,0 %; macro DSSI$V_MBZ = 1,0,4,0 %; literal DSSI$S_MBZ = 4; macro DSSI$V_REQ_ACK = 1,4,4,0 %; literal DSSI$S_REQ_ACK = 4; macro DSSI$B_FLAGS = 1,0,8,0 %; macro DSSI$B_DST_PORT = 2,0,8,0 %; macro DSSI$B_SRC_PORT = 3,0,8,0 %; macro DSSI$W_SIZE = 4,0,16,0 %; literal DSSI$C_DG = 1; literal DSSI$C_MSG = 2; literal DSSI$C_CNF = 3; literal DSSI$C_IDREQ = 5; literal DSSI$C_RST = 6; literal DSSI$C_STRT = 7; literal DSSI$C_DATREQ0 = 8; literal DSSI$C_DATREQ1 = 9; literal DSSI$C_DATREQ2 = 10; literal DSSI$C_ID = 11; literal DSSI$C_LB = 13; literal DSSI$C_SNTDAT = 16; literal DSSI$C_RETDAT = 17; literal DSSI$M_OPCODE = %X'1F'; literal DSSI$M_LP = %X'100'; literal DSSI$M_NS = %X'E00'; literal DSSI$M_M = %X'7000'; literal DSSI$M_DATA = %X'10'; literal DSSI$M_NR = %X'E00'; literal DSSI$C_P0 = 1; literal DSSI$C_P1 = 2; literal DSSI$M_RP = %X'600'; literal DSSI$M_SP = %X'3000'; literal DSSI$M_FR = %X'8000'; literal DSSI$M_DSA = %X'8000'; literal DSSI$C_START = 0; literal DSSI$C_STACK = 1; literal DSSI$C_ACK = 2; literal DSSI$C_SCS_DG = 3; literal DSSI$C_SCS_MSG = 4; literal DSSI$C_ELOG = 5; literal DSSI$C_HOSTSHUT = 6; literal DSSI$C_FU_DG = 7; literal DSSI$C_CNF_LEN = 10; literal DSSI$C_CNFREC_LEN = 10; literal DSSI$C_DATREC_LEN = 10; literal DSSI$C_IDREQ_LEN = 10; literal DSSI$C_RST_LEN = 10; literal DSSI$M_MAINT = %X'1'; literal DSSI$C_UNINIT = 0; literal DSSI$C_DISAB = 1; literal DSSI$C_ENAB = 2; literal DSSI$M_STATE = %X'6'; literal DSSI$M_AST = %X'700'; literal DSSI$M_XRPE = %X'800'; literal DSSI$M_AARB = %X'1000'; literal DSSI$M_XNR = %X'2000'; literal DSSI$M_MAX_BODY_LEN = %X'1FFF0000'; literal DSSI$M_CSZ = %X'E0000000'; literal DSSI$M_NUM_MEMS = %X'FF'; literal DSSI$M_SMV = %X'1000'; literal DSSI$M_RDP_SUP = %X'2000'; literal DSSI$M_FSN_SUP = %X'4000'; literal DSSI$M_SA_SUP = %X'8000'; literal DSSI$C_ID_LEN = 50; literal DSSI$C_IDREC_LEN = 50; literal DSSI$C_DATREQ_LEN = 30; literal DSSI$C_SNTDAT_LEN = 18; literal DSSI$C_RETDAT_LEN = 18; literal DSSI$C_XXXDAT_LEN = 18; literal DSSI$C_STRT_LEN = 14; literal DSSI$S_DSSI_DAT = 50; macro DSSI$V_OPCODE = 0,0,5,0 %; literal DSSI$S_OPCODE = 5; macro DSSI$V_LP = 0,8,1,0 %; macro DSSI$V_NS = 0,9,3,0 %; literal DSSI$S_NS = 3; macro DSSI$V_M = 0,12,3,0 %; literal DSSI$S_M = 3; macro DSSI$V_DATA = 0,4,1,0 %; macro DSSI$V_NR = 0,9,3,0 %; literal DSSI$S_NR = 3; macro DSSI$V_RP = 0,9,2,0 %; literal DSSI$S_RP = 2; macro DSSI$V_SP = 0,12,2,0 %; literal DSSI$S_SP = 2; macro DSSI$V_FR = 0,15,1,0 %; macro DSSI$V_DSA = 0,15,1,0 %; macro DSSI$W_OPCODE = 0,0,16,0 %; macro DSSI$B_TEXT = 2,0,8,0 %; macro DSSI$W_MTYPE = 2,0,16,0 %; macro DSSI$Q_XCT_ID = 2,0,0,0 %; literal DSSI$S_XCT_ID = 8; macro DSSI$L_RPORT_TYP = 10,0,32,0 %; macro DSSI$L_RPORT_REV = 14,0,32,0 %; macro DSSI$L_RPORT_FCN = 18,0,32,0 %; macro DSSI$B_RESET_PORT = 22,0,8,0 %; macro DSSI$V_MAINT = 23,0,1,0 %; macro DSSI$V_STATE = 23,1,2,0 %; literal DSSI$S_STATE = 2; macro DSSI$B_RPORT_STATE = 23,0,24,1 %; literal DSSI$S_RPORT_STATE = 3; macro DSSI$V_AST = 26,8,3,0 %; literal DSSI$S_AST = 3; macro DSSI$V_XRPE = 26,11,1,0 %; macro DSSI$V_AARB = 26,12,1,0 %; macro DSSI$V_XNR = 26,13,1,0 %; macro DSSI$V_MAX_BODY_LEN = 26,16,13,0 %; literal DSSI$S_MAX_BODY_LEN = 13; macro DSSI$V_CSZ = 26,29,3,0 %; literal DSSI$S_CSZ = 3; macro DSSI$L_PORT_FCN_EXT1 = 26,0,32,0 %; macro DSSI$V_NUM_MEMS = 30,0,8,0 %; literal DSSI$S_NUM_MEMS = 8; macro DSSI$V_SMV = 30,12,1,0 %; macro DSSI$V_RDP_SUP = 30,13,1,0 %; macro DSSI$V_FSN_SUP = 30,14,1,0 %; macro DSSI$V_SA_SUP = 30,15,1,0 %; macro DSSI$L_PORT_FCN_EXT2 = 30,0,32,0 %; macro DSSI$Q_SUB_MAP = 34,0,0,0 %; literal DSSI$S_SUB_MAP = 8; macro DSSI$B_UNUSEDID = 42,0,0,0 %; literal DSSI$S_UNUSEDID = 8; macro DSSI$L_XCT_LEN = 10,0,32,0 %; macro DSSI$L_SND_NAME = 14,0,32,0 %; macro DSSI$L_SND_BOFF = 18,0,32,0 %; macro DSSI$Q_SND_BUFF = 14,0,0,0 %; literal DSSI$S_SND_BUFF = 8; macro DSSI$L_REC_NAME = 22,0,32,0 %; macro DSSI$L_REC_BOFF = 26,0,32,0 %; macro DSSI$Q_REC_BUFF = 22,0,0,0 %; literal DSSI$S_REC_BUFF = 8; macro DSSI$Q_BUFF = 10,0,0,0 %; literal DSSI$S_BUFF = 8; macro DSSI$B_DATA = 18,0,8,0 %; macro DSSI$L_ST_ADDR = 10,0,32,1 %; !*** MODULE $PLDEF *** ! ! Definitions for IPF Privilege Levels ! literal PL$C_KERNEL = 0; ! Kernel literal PL$C_EXEC = 1; ! Executive literal PL$C_SUPER = 2; ! Supervisor literal PL$C_USER = 3; ! User !*** MODULE $PLVDEF *** ! + ! PRIVILEGED LIBRARY VECTOR DEFINITION ! - ! ! ********* NOTE WELL ********* ! ! The following masks must EXACTLY EQUAL the SSFLAG masks defined in ! [LIB]VECTORS.SDL. The system service dispatcher assumes, for example, that ! PLV$M_WAIT_CALLERS_MODE equals SSFLAG_K_WCM. Ensure that any additions to ! the PLVFLG structure are reflected in [LIB]VECTORS.SDL (and vice versa). ! ! Also note that although PLVFLG is defined to be a quadword, the dispatcher ! treats the array of kernel flags and exec flags as an array of LONGWORD ! flags. Another interesting point is that the flags value for regular ! system services is limited to a byte. ! ! ********* END NOTE WELL ********* ! literal PLV$M_WAIT_CALLERS_MODE = %X'1'; literal PLV$M_WAIT_CALLERS_NO_REEXEC = %X'2'; literal PLV$M_CLRREG = %X'4'; literal PLV$M_RETURN_ANY = %X'8'; literal PLV$M_WCM_NO_SAVE = %X'10'; literal PLV$M_STACK_ARGS = %X'20'; literal PLV$M_THREAD_SAFE = %X'40'; literal PLV$M_64_BIT_ARGS = %X'80'; literal PLV$M_CHECK_UPCALL = %X'100'; literal PLV$M_EXCLUSIVE = %X'200'; literal PLV$M_TOLERANT = %X'400'; literal PLV$M_IMSEM_RELEASE = %X'800'; literal PLV$M_RESET_ASTEN = %X'1000'; literal PLV$S_FILL_912_ = 8; macro PLV$Q_PLVFLG = 0,0,0,1 %; literal PLV$S_PLVFLG = 8; macro PLV$V_WAIT_CALLERS_MODE = 0,0,1,0 %; ! equals SSFLAG_K_WCM macro PLV$V_WAIT_CALLERS_NO_REEXEC = 0,1,1,0 %; ! equals SSFLAG_K_WCM_NO_REEXEC macro PLV$V_CLRREG = 0,2,1,0 %; ! equals SSFLAG_K_CLRREG macro PLV$V_RETURN_ANY = 0,3,1,0 %; ! equals SSFLAG_K_RETURN_ANY macro PLV$V_WCM_NO_SAVE = 0,4,1,0 %; ! equals SSFLAG_K_WCM_NO_SAVE macro PLV$V_STACK_ARGS = 0,5,1,0 %; ! equals SSFLAG_K_STACK_ARGS macro PLV$V_THREAD_SAFE = 0,6,1,0 %; ! equals SSFLAG_K_THREAD_SAFE macro PLV$V_64_BIT_ARGS = 0,7,1,0 %; ! equals SSFLAG_K_64_BIT_ARGS macro PLV$V_CHECK_UPCALL = 0,8,1,0 %; ! equals SSFLAG_K_CHECK_UPCALL macro PLV$V_EXCLUSIVE = 0,9,1,0 %; ! equals SSFLAG_K_EXCLUSIVE macro PLV$V_TOLERANT = 0,10,1,0 %; ! equals SSFLAG_K_TOLERANT macro PLV$V_IMSEM_RELEASE = 0,11,1,0 %; ! equals SSFLAG_K_IMSEM_RELEASE macro PLV$V_RESET_ASTEN = 0,12,1,0 %; ! equals SSFLAG_K_RESET_ASTEN literal PLV$C_LENGTH = 44; ! Size of fixed portion literal PLV$S_PLVDEF = 44; literal PLV$S_PLV = 44; macro PLV$L_TYPE = 0,0,32,0 %; ! TYPE CODE FOR VECTOR FORMAT macro PLV$L_VERSION = 4,0,32,0 %; ! SYSTEM VERSION NUMBER macro PLV$L_KERNEL_ROUTINE_COUNT = 8,0,32,0 %; ! # of kernel routines macro PLV$L_EXEC_ROUTINE_COUNT = 12,0,32,0 %; ! # of exec routines macro PLV$PS_KERNEL_ROUTINE_LIST = 16,0,32,1 %; ! addr of kernel list macro PLV$PS_EXEC_ROUTINE_LIST = 20,0,32,1 %; ! addr of exec list macro PLV$PS_KERNEL_RUNDOWN_HANDLER = 24,0,32,1 %; ! kern rundown routine macro PLV$PS_EXEC_RUNDOWN_HANDLER = 28,0,32,1 %; ! exec rundown routine macro PLV$PS_RMS_DISPATCHER = 32,0,32,1 %; ! RMS dispatch routine macro PLV$PS_KERNEL_ROUTINE_FLAGS = 36,0,32,1 %; ! flags vector macro PLV$PS_EXEC_ROUTINE_FLAGS = 40,0,32,1 %; ! flags vector macro PLV$L_MSGDSP = 8,0,32,1 %; ! self-rel ptr to message dispatcher macro PLV$L_MSG_ENTRY = 12,0,32,0 %; ! message dispatcher code macro PLV$L_MSG_SECTION = 16,0,32,1 %; ! self-rel ptr to msg section macro PLV$L_FLAGS = 8,0,32,0 %; macro PLV$V_MAIN_IMAGE = 8,0,1,0 %; ! Closest to system service macro PLV$L_SSI_ROUTINE_COUNT = 12,0,32,0 %; ! Count of SSI symbol vectors macro PLV$PS_VECTOR_ADDRESS = 16,0,32,1 %; ! Private symbol vector address ! + ! TYPE CODES FOR PRIVILEGE VECTORS ! - literal PLV$C_TYP_CMOD = 1; ! CHANGE MODE VECTOR TYPE literal PLV$C_TYP_MSG = 2; ! MESSAGE VECTOR TYPE literal PLV$C_TYP_SSI = 3; ! SYSTEM SERVICE INTERCEPT TYPE !*** MODULE $PLVECDEF *** ! + ! PLVEC - SCS PORT LOAD VECTOR ! ! THIS DATA STRUCTURE CONTAINS A VECTOR LISTING THE ACTIVE CONNECTIONS BY ! TYPE ON A PORT. THE INDEX IS CONTAINED IN THE SBNB (SCS LOAD SHARE ! NAME BLOCK and in the CDT$L_ ! ! - literal PLVEC$C_MAX_INDEX = 10; literal PLVEC$K_LENGTH = 60; ! (TYC 15-Feb-89) literal PLVEC$C_LENGTH = 60; literal PLVEC$S_PLVECDEF = 16; literal PLVEC$S_PLVEC = 16; macro PLVEC$L_FLINK = -12,0,32,1 %; ! FWD LINK macro PLVEC$L_BLINK = -8,0,32,1 %; ! BCK LINK macro PLVEC$W_SIZE = -4,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro PLVEC$B_TYPE = -2,0,8,0 %; ! SCS STRUCTURE TYPE macro PLVEC$B_SUBTYP = -1,0,8,0 %; ! SCS STRUCTURE SUBTYPE FOR PLVEC macro PLVEC$L_TOT_CONNECT = 0,0,32,0 %; ! TOTAL NUMBER OF CONNECTIONS ON ! THIS PORT !*** MODULE $PMBDEF *** ! + ! PAGE FAULT MONITOR CONTROL BLOCK ! - literal PMB$M_MODE = %X'1'; literal PMB$K_SUBPROC = 0; ! Subprocess mode literal PMB$K_IMAGE = 1; ! Image mode literal PMB$M_ASTIP = %X'2'; literal PMB$M_QAST = %X'4'; literal PMB$K_LENGTH = 76; ! Length of PMB literal PMB$C_LENGTH = 76; ! Length of PMB literal PMB$S_PMBDEF = 76; ! Old size name - synonym literal PMB$S_PMB = 76; macro PMB$L_CURBUF = 0,0,32,1 %; ! Current buffer pointer macro PMB$L_BUFBASE = 4,0,32,1 %; ! Current buffer base address macro PMB$W_SIZE = 8,0,16,0 %; ! Block size field macro PMB$B_TYPE = 10,0,8,0 %; ! Dynamic structure type (PMB) macro PMB$B_FLAGS = 11,0,8,0 %; ! Processing flags macro PMB$V_MODE = 11,0,1,0 %; ! Mode of operation macro PMB$V_ASTIP = 11,1,1,0 %; ! AST in progress flag macro PMB$V_QAST = 11,2,1,0 %; ! Imbedded ACB is enqueued on the PCB macro PMB$L_LASTCPU = 12,0,32,0 %; ! Last recorded CPU time macro PMB$L_OVERFLOW = 16,0,32,0 %; ! Buffer overflow counter (both modes) macro PMB$Q_HDR = 24,0,0,0 %; literal PMB$S_HDR = 8; ! Free buffer queue header macro PMB$Q_SBPHDR = 32,0,0,0 %; literal PMB$S_SBPHDR = 8; ! Filled buffer queue header macro PMB$L_ASTQFL = 40,0,32,1 %; ! ACB flink macro PMB$L_ASTQBL = 44,0,32,1 %; ! ACB blink macro PMB$B_ACMODE = 50,0,8,0 %; ! Owner access mode macro PMB$B_RMOD = 51,0,8,0 %; ! AST delivery mode/flags macro PMB$L_PID = 52,0,32,0 %; ! PID for AST delivery macro PMB$L_AST = 56,0,32,1 %; ! AST routine address macro PMB$L_ASTPRM = 60,0,32,0 %; ! AST parameter macro PMB$L_KAST = 72,0,32,1 %; ! Address of piggy-back kernel AST routine macro PMB$W_MBXCHN = 48,0,16,0 %; ! Subprocess mailbox channel macro PMB$B_OACMODE = 50,0,8,0 %; ! Owner access mode (Synonym for ACMODE) macro PMB$L_IPID = 52,0,32,0 %; ! IPID of subprocess (Synonym for PID) macro PMB$L_EPID = 56,0,32,0 %; ! EPID of subprocess !*** MODULE $POOLCHECKDEF *** ! + ! POOLCHECK - Poolcheck SYSGEN parameter layout ! - literal PCHECK$M_POISON = %X'1'; literal PCHECK$M_CHECK = %X'2'; literal PCHECK$M_SRP_FREE = %X'4'; literal PCHECK$M_IRP_FREE = %X'8'; literal PCHECK$M_LRP_FREE = %X'10'; literal PCHECK$M_XRP_ALIGN = %X'20'; literal PCHECK$M_DEALLO_SIZE = %X'40'; literal PCHECK$M_P1 = %X'80'; literal PCHECK$S_POOLCHECKDEF = 4; literal PCHECK$S_POOLCHECK = 4; macro PCHECK$L_POOLCHECK = 0,0,32,1 %; macro PCHECK$B_FLAGS = 0,0,8,0 %; ! Flag bits macro PCHECK$V_POISON = 0,0,1,0 %; ! Poison on deallocation ! Enable other features macro PCHECK$V_CHECK = 0,1,1,0 %; ! Check poisoning on allocation ! and poison with allo pattern macro PCHECK$V_SRP_FREE = 0,2,1,0 %; ! Poison SRPs on deallocation (obsolete) macro PCHECK$V_IRP_FREE = 0,3,1,0 %; ! Poison IRPs on deallocation (obsolete) macro PCHECK$V_LRP_FREE = 0,4,1,0 %; ! Poison LRPs on deallocation (obsolete) macro PCHECK$V_XRP_ALIGN = 0,5,1,0 %; ! Check xRP alignment on deallocation (obs) macro PCHECK$V_DEALLO_SIZE = 0,6,1,0 %; ! Check deallocation length against allocation length macro PCHECK$V_P1 = 0,7,1,0 %; ! Do poisoning/checking on P1 space macro PCHECK$B_SIZE_TO_CHECK = 1,0,8,0 %; ! What deallo size to check if DEALO_LENGTH is set macro PCHECK$B_FREE = 2,0,8,0 %; ! Free pattern macro PCHECK$B_ALLO = 3,0,8,0 %; ! Allocated pattern ! + ! PCHK_REASON - Poolcheck bugcheck reason codes ! ! This defines the poolcheck bugcheck codes pushed on the stack when a ! poolcheck bugcheck is declared. ! ! - literal PCHK_REASON$_CORRUPT = 0; ! Corrupted packet literal PCHK_REASON$_ALIGN = 1; ! Bad alignment (obsolete) literal PCHK_REASON$_XRP_ALIGN = 2; ! Bad alignment of xRP packet (obsolete) literal PCHK_REASON$_PAGED = 3; ! Paged block is partially outside literal PCHK_REASON$_NPAGED = 4; ! Npaged block is partially outside literal PCHK_REASON$_IPL = 5; ! Called P1 routines with IPL too high literal PCHK_REASON$_AGGLOM = 6; ! Agglomeration not done literal PCHK_REASON$_UNBALANCED = 7; ! Deallocation and allocation were not the same size !*** MODULE $POSIXDEF *** literal PSXHDR$M_SID = %X'1'; literal PSXHDR$M_PGID = %X'2'; literal PSXHDR$M_INITIAL_ALLOC = %X'80000000'; literal PSXHDR$K_HEADER_LENGTH = 28; literal PSXHDR$S_PSXHDR = 32; macro PSXHDR$L_FLINK = 0,0,32,1 %; ! Standard listhead forward link macro PSXHDR$L_BLINK = 4,0,32,1 %; ! Standard listhead backward link macro PSXHDR$W_SIZE = 8,0,16,0 %; ! Standard structure size, in bytes macro PSXHDR$B_TYPE = 10,0,8,0 %; ! Standard type code for POSIXID (DYN$C_PSX) macro PSXHDR$B_SUBTYPE = 11,0,8,0 %; ! Standard subtype code (DYN$C_PSX_ID_HEADER) macro PSXHDR$L_FLAGS = 12,0,32,0 %; ! Generic FLAGS longword macro PSXHDR$V_SID = 12,0,1,0 %; ! Header for Session_ID structure macro PSXHDR$V_PGID = 12,1,1,0 %; ! Header for Process_Group_ID structure macro PSXHDR$V_INITIAL_ALLOC = 12,31,1,0 %; ! Initial member structure macro PSXHDR$L_LEADER = 16,0,32,0 %; ! Leader of this Session or Group macro PSXHDR$L_PARENT_LINK = 20,0,32,1 %; ! Pointer back to owner parent (SESSION) macro PSXHDR$L_MEMBER_PTR = 24,0,32,1 %; ! Pointer to a PSXMEM structure literal PSXMEM$M_SID = %X'1'; literal PSXMEM$M_PGID = %X'2'; literal PSXMEM$M_INITIAL_ALLOC = %X'80000000'; literal PSXMEM$K_HEADER_LENGTH = 36; literal PSXMEM$S_PSXMEM = 40; macro PSXMEM$L_FLINK = 0,0,32,1 %; ! Standard listhead forward link macro PSXMEM$L_BLINK = 4,0,32,1 %; ! Standard listhead backward link macro PSXMEM$W_SIZE = 8,0,16,0 %; ! Standard structure size, in bytes macro PSXMEM$B_TYPE = 10,0,8,0 %; ! Standard type code for POSIXID (DYN$C_PSX) macro PSXMEM$B_SUBTYPE = 11,0,8,0 %; ! Standard subtype code (DYN$C_PSX_ID_MEMBER) macro PSXMEM$L_FLAGS = 12,0,32,0 %; ! Generic FLAGS longword macro PSXMEM$V_SID = 12,0,1,0 %; ! Member for Session_ID structure macro PSXMEM$V_PGID = 12,1,1,0 %; ! Member for Process_Group_ID structure macro PSXMEM$V_INITIAL_ALLOC = 12,31,1,0 %; ! Initial member structure macro PSXMEM$L_HEADER_PTR = 16,0,32,1 %; ! Pointer back to header structure macro PSXMEM$L_CAPACITY = 28,0,32,0 %; ! Number of array slots in this structure macro PSXMEM$L_USED = 32,0,32,0 %; ! Number of array slots in use macro PSXMEM$T_MEMBERS = 36,0,0,0 %; ! Offset of Member list literal PSXCTL$M_ADD_MEMBER = %X'1'; literal PSXCTL$M_REMOVE_MEMBER = %X'2'; literal PSXCTL$M_SID_STRUCTURE = %X'4'; literal PSXCTL$M_PGID_STRUCTURE = %X'8'; literal PSXCTL$M_MEMBER_ONLY = %X'10'; literal PSXCTL$S_PSXCTL = 8; macro PSXCTL$L_CONTROL = 0,0,32,0 %; ! Define the control bits for SET_POSIX_MEMBER macro PSXCTL$V_ADD_MEMBER = 0,0,1,0 %; ! Add to exsiting or newly created group macro PSXCTL$V_REMOVE_MEMBER = 0,1,1,0 %; ! Remove from existing group macro PSXCTL$V_SID_STRUCTURE = 0,2,1,0 %; ! Group is a collection of SESSION IDs macro PSXCTL$V_PGID_STRUCTURE = 0,3,1,0 %; ! Group is a collection of Process IDs macro PSXCTL$V_MEMBER_ONLY = 0,4,1,0 %; ! Create only the member structure literal LEADERLESS$S_LEADERLESS = 8; macro LEADERLESS$L_FLINK = 0,0,32,1 %; macro LEADERLESS$L_BLINK = 4,0,32,1 %; literal SESSION_ID$S_SESSION_ID = 8; macro SESSION_ID$L_FLINK = 0,0,32,1 %; macro SESSION_ID$L_BLINK = 4,0,32,1 %; literal PSXMEM$S_MEMBER_SIZE = 4; literal PSXMEM$K_EXPAND_COUNT = 16; literal POSIX$_SET_RUID = 512; ! Set Real UserID literal POSIX$_SET_EUID = 513; ! Set Effective UserID literal POSIX$_SET_RGID = 514; ! Set Real GroupID literal POSIX$_SET_EGID = 515; ! Set Effective GroupID literal POSIX$_SET_MODE = 516; ! Mode of resulting personae !*** MODULE $PQBDEF *** ! + ! PROCESS QUOTA BLOCK DEFINITION ! - literal PQB$M_IMGDMP = %X'1'; literal PQB$M_DEBUG = %X'2'; literal PQB$M_DBGTRU = %X'4'; literal PQB$M_PARSE_EXTENDED = %X'8'; literal PQB$M_CASE_SENSITIVE = %X'10'; literal PQB$M_MEDDLE_ENABLE = %X'20'; literal PQB$M_MEDDLE = %X'40'; literal PQB$M_SEARCH_SYMLINK = %X'180'; literal PQB$K_LENGTH = 2276; ! LENGTH OF PROCESS QUOTA BLOCK literal PQB$C_LENGTH = 2276; ! LENGTH OF PROCESS QUOTA BLOCK literal PQB$S_PQBDEF = 2276; ! Old size name - synonym literal PQB$S_PQB = 2276; macro PQB$Q_PRVMSK = 0,0,0,0 %; literal PQB$S_PRVMSK = 8; ! PRIVILEGE MASK macro PQB$W_SIZE = 8,0,16,0 %; ! SIZE OF PQB IN BYTES macro PQB$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE CODE macro PQB$B_STS = 11,0,8,0 %; ! STATUS FLAGS macro PQB$L_ASTLM = 12,0,32,0 %; ! AST LIMIT macro PQB$L_BIOLM = 16,0,32,0 %; ! BUFFERED I/O LIMIT macro PQB$L_BYTLM = 20,0,32,0 %; ! BUFFERED I/O LIMIT macro PQB$L_CPULM = 24,0,32,0 %; ! CPU TIME LIMIT macro PQB$L_DIOLM = 28,0,32,0 %; ! DIRECT I/O LIMIT macro PQB$L_FILLM = 32,0,32,0 %; ! OPEN FILE LIMIT macro PQB$L_PGFLQUOTA = 36,0,32,0 %; ! PAGING FILE QUOTA macro PQB$L_PRCLM = 40,0,32,0 %; ! SUB-PROCESS LIMIT macro PQB$L_TQELM = 44,0,32,0 %; ! TIMER QUEUE ENTRY LIMIT macro PQB$L_WSQUOTA = 48,0,32,0 %; ! WORKING SET QUOTA macro PQB$L_WSDEFAULT = 52,0,32,0 %; ! WORKING SET DEFAULT macro PQB$L_ENQLM = 56,0,32,0 %; ! ENQUEUE LIMIT macro PQB$L_WSEXTENT = 60,0,32,0 %; ! MAXIMUM WORKING SET SIZE macro PQB$L_JTQUOTA = 64,0,32,0 %; ! JOB-WIDE LOGICAL NAME TABLE CREATION QUOTA macro PQB$W_FLAGS = 68,0,16,0 %; ! MISC FLAGS macro PQB$V_IMGDMP = 68,0,1,0 %; ! TAKE IMAGE DUMP ON SERIOUS ERROR macro PQB$V_DEBUG = 68,1,1,0 %; ! /DEBUG startup desired macro PQB$V_DBGTRU = 68,2,1,0 %; ! debugger present macro PQB$V_PARSE_EXTENDED = 68,3,1,0 %; ! Set if process is to be parse_style extended macro PQB$V_CASE_SENSITIVE = 68,4,1,0 %; ! set process CASE_LOOKUP = SENSITIVE macro PQB$V_MEDDLE_ENABLE = 68,5,1,0 %; ! Record fact of process logical name & symbol alterations macro PQB$V_MEDDLE = 68,6,1,0 %; ! Process logical names or symbols have been altered macro PQB$V_SEARCH_SYMLINK = 68,7,2,0 %; literal PQB$S_SEARCH_SYMLINK = 2; ! Process symlink search mode macro PQB$B_MSGMASK = 70,0,8,0 %; ! MESSAGE FLAGS macro PQB$L_UAF_FLAGS = 72,0,32,0 %; ! FLAGS FROM UAF RECORD macro PQB$L_CREPRC_FLAGS = 76,0,32,0 %; ! FLAGS FROM $CREPRC ARGUMENT LIST macro PQB$R_MIN_CLASS = 80,0,0,0 %; literal PQB$S_MIN_CLASS = 20; ! MINIMUM AUTHORIZED SECURITY CLEARANCE macro PQB$R_MAX_CLASS = 100,0,0,0 %; literal PQB$S_MAX_CLASS = 20; ! MAXIMUM AUTHORIZED SECURITY CLEARANCE macro PQB$L_INPUT_ATT = 120,0,32,0 %; ! SYS$INPUT attributes macro PQB$L_OUTPUT_ATT = 124,0,32,0 %; ! SYS$OUTPUT attributes macro PQB$L_ERROR_ATT = 128,0,32,0 %; ! SYS$ERROR attributes macro PQB$L_DISK_ATT = 132,0,32,0 %; ! SYS$DISK attributes macro PQB$T_CLI_NAME = 136,0,0,0 %; literal PQB$S_CLI_NAME = 32; ! CLI name macro PQB$T_CLI_TABLE = 168,0,0,0 %; literal PQB$S_CLI_TABLE = 256; ! CLI table name macro PQB$T_SPAWN_CLI = 424,0,0,0 %; literal PQB$S_SPAWN_CLI = 32; ! Spawn CLI name macro PQB$T_SPAWN_TABLE = 456,0,0,0 %; literal PQB$S_SPAWN_TABLE = 256; ! Spawn CLI table name macro PQB$T_INPUT = 712,0,0,0 %; literal PQB$S_INPUT = 256; ! LOGICAL NAME FOR INPUT macro PQB$T_OUTPUT = 968,0,0,0 %; literal PQB$S_OUTPUT = 256; ! LOGICAL NAME FOR OUTPUT macro PQB$T_ERROR = 1224,0,0,0 %; literal PQB$S_ERROR = 256; ! LOGICAL NAME FOR ERROR OUTPUT macro PQB$T_DISK = 1480,0,0,0 %; literal PQB$S_DISK = 256; ! LOGICAL NAME FOR SYS$DISK macro PQB$T_DDSTRING = 1736,0,0,0 %; literal PQB$S_DDSTRING = 256; ! DEFAULT DIRECTORY STRING macro PQB$T_IMAGE = 1992,0,0,0 %; literal PQB$S_IMAGE = 256; ! IMAGE NAME FOR NEW PROCESS macro PQB$T_ACCOUNT = 2248,0,0,0 %; literal PQB$S_ACCOUNT = 8; ! ACCOUNT NAME FOR NEW PROCESS macro PQB$L_ARB_SUPPORT = 2256,0,32,0 %; ! ARB SUPPORT BACKWARD COMPATIBILITY FLAG macro PQB$L_RMS_LCS = 2260,0,32,0 %; ! LOCAL CODE-SET FOR RMS FILENAME macro PQB$L_SSLOG_FLAGS = 2264,0,32,0 %; ! Flags for system service logging macro PQB$L_SSLOG_BUFSIZE = 2268,0,32,0 %; ! Size of system service log buffer macro PQB$L_SSLOG_BUFCNT = 2272,0,32,0 %; ! Number of system service log buffers !*** MODULE $PRBDEF *** ! + ! ! Protection block definition. The protection block is used to specify ! protection on objects internal to the system (e.g., devices, logical ! name tables, etc.) It is used as input to the EXE$CHECKACCESS routine. ! ! - literal PRB$M_UIC = %X'1'; literal PRB$M_ACL = %X'2'; literal PRB$M_CLASS = %X'4'; literal PRB$M_CLASSMAX = %X'8'; literal PRB$S_PRBDEF = 8; ! literal PRB$S_PRB = 8; macro PRB$W_FLAGS = 0,0,16,0 %; ! Presence flag bits macro PRB$V_UIC = 0,0,1,0 %; ! Set for simple UIC protection macro PRB$V_ACL = 0,1,1,0 %; ! Set for access control list macro PRB$V_CLASS = 0,2,1,0 %; ! Set for security classification macro PRB$V_CLASSMAX = 0,3,1,0 %; ! Set for security class range macro PRB$W_PROTECTION = 2,0,16,0 %; ! SOGW protection mask macro PRB$L_OWNER = 4,0,32,0 %; ! Owner UIC ! The remaining items in the protection block are optional and therefore ! do not have fixed offsets. The description given below is for a ! hypothetical fully configured protection block. ! ! ACL quadword; /* ACL listhead ! CLASS structure; /* Classification mask ! FILL_1 long dimension 5 fill; ! end CLASS; ! CLASSMAX structure; /* Maximum class mask for range ! FILL_2 long dimension 5 fill; ! end CLASSMAX; ! !*** MODULE $PRCEVTDEF *** ! ! PRCEVTDEF ! ! This module defines the Process Event constants and structure ! offsets. ! literal PRCEVT$K_LENGTH = 16; ! Length of PRCEVT literal PRCEVT$C_LENGTH = 16; ! Length of PRCEVT literal PRCEVT$S_PRCEVTDEF = 16; ! Old size name - synonym literal PRCEVT$S_PRCEVT = 16; macro PRCEVT$L_FLINK = 0,0,32,1 %; ! Foward link macro PRCEVT$L_BLINK = 4,0,32,1 %; ! Backward link macro PRCEVT$W_SIZE = 8,0,16,0 %; ! Size, in bytes macro PRCEVT$B_TYPE = 10,0,8,0 %; ! Structure type code macro PRCEVT$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro PRCEVT$L_HANDLER = 12,0,32,1 %; ! Handler address literal PRCEVT$C_USRUNDWN_EXEC = 0; ! Exec mode image rundown literal PRCEVT$C_USRUNDWN = 1; ! Image rundown literal PRCEVT$C_DELPRC_RUNDWN = 2; ! Process rundown literal PRCEVT$C_DELPRC_DELTVA = 3; ! Process address space deletion literal PRCEVT$C_CRE_MIN_PROCESS = 4; ! Minimal process creation literal PRCEVT$C_FORK_PROCSTRT = 5; ! Child's fork() procstrt literal PRCEVT$C_MAX_EVENT = 6; ! Maximum number of process events !*** MODULE $PRCPOLDEF *** ! + ! PROCESS POLLER MAILBOX MESSAGE DEFINITIONS ! - literal PRCPOL$C_SIZ = 56; ! SIZE OF MESSAGE literal PRCPOL$S_PRCPOLDEF = 56; literal PRCPOL$S_PRCPOL = 56; macro PRCPOL$L_SYSIDL = 0,0,32,0 %; ! LOW ORDER SYSTEM ID macro PRCPOL$W_SYSIDH = 4,0,16,0 %; ! HIGH ORDER SYSTEM ID macro PRCPOL$T_NODNAM = 8,0,0,0 %; literal PRCPOL$S_NODNAM = 16; ! SCA NODE NAME (COUNTED ASCII) macro PRCPOL$B_PRCNAM = 24,0,0,0 %; literal PRCPOL$S_PRCNAM = 16; ! PROCESS NAME macro PRCPOL$B_DIRINF = 40,0,0,0 %; literal PRCPOL$S_DIRINF = 16; ! DIRECTORY INFORMATION !*** MODULE $PRCSTRDEF *** ! ! PRCSTRDEF ! ! This module defines the alternate procstrt structure offsets. ! literal PRCSTR$K_LENGTH = 60; ! Length of PRCSTR literal PRCSTR$C_LENGTH = 60; ! Length of PRCSTR literal PRCSTR$S_PRCSTRDEF = 60; literal PRCSTR$S_PRCSTR = 60; macro PRCSTR$L_FLINK = 0,0,32,1 %; ! Foward link macro PRCSTR$L_BLINK = 4,0,32,1 %; ! Backward link macro PRCSTR$W_SIZE = 8,0,16,0 %; ! Size, in bytes macro PRCSTR$B_TYPE = 10,0,8,0 %; ! Structure type code macro PRCSTR$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro PRCSTR$L_PARENT_PCB = 12,0,32,1 %; ! Address of parent/creator's PCB macro PRCSTR$L_PROCSTRT = 16,0,32,1 %; ! Address of alternate procstrt routine macro PRCSTR$L_CTX_BUFFER = 20,0,32,1 %; ! Address of context buffer macro PRCSTR$L_PHD_BUFFER = 24,0,32,1 %; ! Address of PHD data buffer macro PRCSTR$L_P1POINTER_SVA = 28,0,32,1 %; ! System VA of P1 Pointer page macro PRCSTR$L_P1POINTER_SVAPTE = 32,0,32,1 %; ! SVAPTE of P1 Pointer page macro PRCSTR$L_PIO_SVA = 36,0,32,1 %; ! Syetem VA of PIO page macro PRCSTR$I_P1POINTER_PFN = 40,0,0,0 %; literal PRCSTR$S_P1POINTER_PFN = 8; ! macro PRCSTR$I_PIO_PFN = 48,0,0,0 %; literal PRCSTR$S_PIO_PFN = 8; ! macro PRCSTR$L_PIO_SVAPTE = 56,0,32,1 %; ! SVAPTE of PIO page !*** MODULE $PRIDEF *** ! + ! PRIORITY INCREMENT CLASS DEFINITIONS ! - literal PRI$_NULL = 0; ! NO PRIORITY INCREMENT (must be equal to 0) literal PRI$_IOCOM = 1; ! DIRECT I/O COMPLETION literal PRI$_RESAVL = 2; ! RESOURCE AVAIL literal PRI$_TOCOM = 3; ! TERMINAL OUTPUT COMPLETE literal PRI$_TICOM = 4; ! TERMINAL INPUT COMPLETE literal PRI$_TIMER = 5; ! TIMER INTERVAL COMPLETION literal PRI$_PINC_CNT = 6; ! No. of priority increment classes literal PRI$C_NUM_PRI = 64; literal PRI$C_NUM_NORMAL = 16; literal PRI$C_NUM_REALTIME = 48; ! Realtime threshold literal PRI$C_RT_THRESHOLD = 16; ! Priority interval for VMS native sched policy literal PRI$C_MIN_VMS_PRIO = 0; literal PRI$C_MAX_VMS_PRIO = 63; ! Priority interval for POSIX RT policies literal PRI$C_MIN_PSXRT_PRIO = 16; literal PRI$C_MAX_PSXRT_PRIO = 63; !*** MODULE $PRMDEF *** ! + ! DEFINE PARAMETER DESCRIPTOR BLOCK ! - literal PRM$M_DYNAMIC = %X'1'; literal PRM$M_STATIC = %X'2'; literal PRM$M_SYSGEN = %X'4'; literal PRM$M_ACP = %X'8'; literal PRM$M_JBC = %X'10'; literal PRM$M_RMS = %X'20'; literal PRM$M_SYS = %X'40'; literal PRM$M_SPECIAL = %X'80'; literal PRM$M_DISPLAY = %X'100'; literal PRM$M_CONTROL = %X'200'; literal PRM$M_MAJOR = %X'400'; literal PRM$M_PQL = %X'800'; literal PRM$M_NEG = %X'1000'; literal PRM$M_TTY = %X'2000'; literal PRM$M_SCS = %X'4000'; literal PRM$M_CLUSTER = %X'8000'; literal PRM$M_ASCII = %X'10000'; literal PRM$M_LGI = %X'20000'; literal PRM$M_MULTIPROCESSING = %X'40000'; literal PRM$M_CONVERT_PAGE = %X'80000'; literal PRM$M_MODIFIED = %X'100000'; literal PRM$M_GALAXY = %X'200000'; literal PRM$M_OBSOLETE = %X'400000'; literal PRM$M_BITMAP = %X'800000'; literal PRM$C_BYTE = 8; ! literal PRM$C_WORD = 16; ! literal PRM$C_LONG = 32; ! literal PRM$C_QUAD = 64; ! literal PRM$C_OCTA = 128; ! literal PRM$C_BIT1024 = 1024; ! literal PRM$C_MAXNAMLEN = 15; ! MAXIMUM LENGTH FOR PARAMETER NAME literal PRM$C_MAXUNILEN = 11; ! MAXIMUM LENGTH FOR UNIT NAME literal PRM$K_LENGTH = 64; ! SIZE OF DESCRIPTOR BLOCK literal PRM$C_LENGTH = 64; ! SIZE OF DESCRIPTOR BLOCK literal PRM$S_PRM_DEF = 64; ! Old size name - synonym literal PRM$S_PRM = 64; macro PRM$L_ADDR = 0,0,32,1 %; ! ADDRESS OF PARAMETER macro PRM$L_INT_ADDR = 4,0,32,1 %; ! ADDRESS OF INTERAL VAL macro PRM$L_DEFAULT = 8,0,32,0 %; ! DEFAULT VALUE macro PRM$L_MIN = 12,0,32,0 %; ! MINIMUM VALUE (-1)=>NONE macro PRM$L_MAX = 16,0,32,0 %; ! MAXIMUM VALUE (-1)=>NONE macro PRM$L_INT_MIN = 20,0,32,0 %; ! POST-CONVERSION MIN macro PRM$L_FLAGS = 24,0,32,0 %; ! TYPE FLAGS macro PRM$V_DYNAMIC = 24,0,1,0 %; ! DYNAMIC PARAMETER macro PRM$V_STATIC = 24,1,1,0 %; ! STATIC PARAMETER macro PRM$V_SYSGEN = 24,2,1,0 %; ! SYSGEN PARAMETER macro PRM$V_ACP = 24,3,1,0 %; ! ACP CONTROL PARAMETER macro PRM$V_JBC = 24,4,1,0 %; ! JOB CONTROL PARAMETER macro PRM$V_RMS = 24,5,1,0 %; ! RMS CONTROL PARAMETER macro PRM$V_SYS = 24,6,1,0 %; ! GENERAL SYSTEM PARAMETER macro PRM$V_SPECIAL = 24,7,1,0 %; ! SPECIAL PARAMETER macro PRM$V_DISPLAY = 24,8,1,0 %; ! DISPLAY ONLY (NO CHANGE) macro PRM$V_CONTROL = 24,9,1,0 %; ! CONTROL PARAMETER macro PRM$V_MAJOR = 24,10,1,0 %; ! MAJOR PARAMETER macro PRM$V_PQL = 24,11,1,0 %; ! PROCESS QUOTA LIST macro PRM$V_NEG = 24,12,1,0 %; ! NEGATIVE macro PRM$V_TTY = 24,13,1,0 %; ! TERMINAL CONTROL PARAMETER macro PRM$V_SCS = 24,14,1,0 %; ! SCS CONTROL PARAMETERS macro PRM$V_CLUSTER = 24,15,1,0 %; ! CLUSTER CONTROL PARAMETERS macro PRM$V_ASCII = 24,16,1,0 %; ! ASCII PARAMETER macro PRM$V_LGI = 24,17,1,0 %; ! LOGIN PARAMETER macro PRM$V_MULTIPROCESSING = 24,18,1,0 %; ! MULTIPROCESSING control macro PRM$V_CONVERT_PAGE = 24,19,1,0 %; ! Pagelets externally, pages internally macro PRM$V_MODIFIED = 24,20,1,0 %; ! Parameter modified (auditing) macro PRM$V_GALAXY = 24,21,1,0 %; ! GALAXY parameters macro PRM$V_OBSOLETE = 24,22,1,0 %; ! OBSOLETE parmeter macro PRM$V_BITMAP = 24,23,1,0 %; ! Parameter is a bitmap ( > 32 bits) macro PRM$L_SIZE = 28,0,32,0 %; ! SIZE CODE FOR DATUM macro PRM$L_POS = 32,0,32,0 %; ! BIT POSITION macro PRM$T_NAME = 36,0,0,0 %; literal PRM$S_NAME = 16; ! ASCIC NAME STRING macro PRM$T_UNIT = 52,0,0,0 %; literal PRM$S_UNIT = 12; ! ASCIC UNIT STRING literal PRM$K_BLOCKS = 22; ! PRM$K_BLOCKS is the length of ALPHAVMSSYS.PAR !*** MODULE proc_read_write *** ! ++ ! Facility: ! ! SYS ! ! Abstract: ! ! This module defines all the constants and data structures for ! PROC_READ_WRITE.BLI which are specific to that module. ! ! Environment: ! ! Kernel mode at IPL = 0 ! ! Author: Steve DiPirro , Creation date: 30-JAN-1991 ! ! Modified by: ! ! X-7 PM Pramod Mangalore 02-Feb-2010 ! PTR 75-13-2205/QXCM1000976519 ! Add a new constant EACB$K_PC_PSL. ! ! X-6 RAB Richard A. Bishop 11-Jun-2004 ! Add a cell for the actual size of the extended ACB. ! If it's over 65K, the size won't fit in the ACB$W_SIZE ! field. ! ! X-5 CAD Chip Dancy 20-Jun-2003 ! Increase IA64 memory pool size to 16384. ! ! X-4 CAD Chip Dancy 16-May-2003 ! Add IPF fields. ! ! X-3 RAB Richard A. Bishop 06-Dec-2002 ! Add IA64 register set ! ! X-2 RAB Richard A. Bishop 07-Feb-2000 ! Add new class of processor registers ! ! (fix audit trail - idents are out of step) ! ! X-2 RS00178 Richard Sayde 28-Oct-1991 ! Add definitions to be able to read and write registers. ! ! X-1 RS00175 Richard Sayde 22-Oct-1991 ! Put module into CMS - made some changes based on the ! way SDA solved the problem. ! --- ! ! ! ! ACB extensions to accommodate various additional pieces of information ! needed to complete process read/write operations. ! literal eacb$k_memory = 1; ! virtual memory literal eacb$k_general_register = 2; ! R0-R29,PC,PS literal eacb$k_float_register = 3; ! F0-F30 literal eacb$k_internal_register = 4; ! VIRBND,SYSPTBR etc literal eacb$k_invocation_context = 5; ! ICB literal eacb$k_pc_psl = 6; ! PC,PS literal eacb$k_gen_register_size = 8; ! Number of bytes in a general ! register literal eacb$k_r0 = 0; literal eacb$k_r1 = 1; literal eacb$k_r2 = 2; literal eacb$k_r3 = 3; literal eacb$k_r4 = 4; literal eacb$k_r5 = 5; literal eacb$k_r6 = 6; literal eacb$k_r7 = 7; literal eacb$k_r8 = 8; ! R0 - R29, PC, PS (address literal eacb$k_r9 = 9; literal eacb$k_r10 = 10; literal eacb$k_r11 = 11; literal eacb$k_r12 = 12; literal eacb$k_r13 = 13; literal eacb$k_r14 = 14; literal eacb$k_r15 = 15; ! map for registers literal eacb$k_r16 = 16; literal eacb$k_r17 = 17; literal eacb$k_r18 = 18; literal eacb$k_r19 = 19; literal eacb$k_r20 = 20; literal eacb$k_r21 = 21; literal eacb$k_r22 = 22; literal eacb$k_r23 = 23; literal eacb$k_r24 = 24; literal eacb$k_r25 = 25; literal eacb$k_r26 = 26; literal eacb$k_r27 = 27; literal eacb$k_r28 = 28; literal eacb$k_r29 = 29; literal eacb$k_r30 = 30; literal eacb$k_r31 = 31; literal eacb$k_pc = 32; literal eacb$k_psr = 33; literal eacb$k_isr = 34; literal eacb$k_gen_regs_length = 35; literal eacb$k_float_register_size = 8; literal eacb$k_fp0 = 0; literal eacb$k_fp1 = 1; literal eacb$k_fp2 = 2; literal eacb$k_fp3 = 3; literal eacb$k_fp4 = 4; literal eacb$k_fp5 = 5; literal eacb$k_fp6 = 6; ! FP0 - FP29 (address map for literal eacb$k_fp7 = 7; literal eacb$k_fp8 = 8; literal eacb$k_fp9 = 9; literal eacb$k_fp10 = 10; literal eacb$k_fp11 = 11; literal eacb$k_fp12 = 12; ! registers literal eacb$k_fp13 = 13; literal eacb$k_fp14 = 14; literal eacb$k_fp15 = 15; literal eacb$k_fp16 = 16; literal eacb$k_fp17 = 17; literal eacb$k_fp18 = 18; literal eacb$k_fp19 = 19; literal eacb$k_fp20 = 20; literal eacb$k_fp21 = 21; literal eacb$k_fp22 = 22; literal eacb$k_fp23 = 23; literal eacb$k_fp24 = 24; literal eacb$k_fp25 = 25; literal eacb$k_fp26 = 26; literal eacb$k_fp27 = 27; literal eacb$k_fp28 = 28; literal eacb$k_fp29 = 29; literal eacb$k_float_regs_length = 30; literal eacb$k_int_register_size = 8; literal eacb$k_virbnd = 0; literal eacb$k_sysptbr = 1; literal eacb$k_scc = 2; ! VIRBND,SYSPTBR etc literal eacb$k_int_regs_length = 3; ! Invocation Context size is in ICBDEF literal eacb$k_memory_pool_size = 16384; ! Memory pool size following EACB literal eacb$m_done = %X'1'; literal eacb$m_half_done = %X'2'; literal eacb$m_suspend = %X'4'; literal eacb$k_block_size = 68; ! Length of data block literal eacb$S_acb_extend = 68; macro eacb$q_local_adr = 0,0,0,0 %; literal eacb$s_local_adr = 8; ! Local process address macro eacb$q_target_adr_type = 8,0,0,0 %; literal eacb$s_target_adr_type = 8; ! target type, one of: macro eacb$q_target_adr = 16,0,0,0 %; literal eacb$s_target_adr = 8; ! Target process address macro eacb$q_status_adr = 24,0,0,0 %; literal eacb$s_status_adr = 8; ! Address of src process status longword macro eacb$q_memory_pool_addr = 32,0,0,0 %; literal eacb$s_memory_pool_addr = 8; ! Address of memory pool following EACB macro eacb$l_status_icb_alert_code = 40,0,32,0 %; ! ICB error status or zero macro eacb$l_status = 44,0,32,0 %; ! Operation completion status macro eacb$l_buffer_size = 48,0,32,0 %; ! Buffer size to transfer macro eacb$l_local_pid = 52,0,32,0 %; ! Local process PID macro eacb$l_image_count = 56,0,32,0 %; ! Process image count macro eacb$r_flags_field = 60,0,32,0 %; literal eacb$s_flags_field = 4; ! macro eacb$l_flags = 60,0,32,0 %; ! For references to whole thing macro eacb$r_flags_bits = 60,0,8,0 %; literal eacb$s_flags_bits = 1; ! For individual bits macro eacb$v_done = 60,0,1,0 %; ! Operation complete flag macro eacb$v_half_done = 60,1,1,0 %; ! Operation partly complete flag macro eacb$v_suspend = 60,2,1,0 %; ! Set if target process should suspend ! ! macro eacb$l_acb_extend_size = 64,0,32,0 %; ! Size of extended ACB actually allocated literal prcstk$k_nofp_save_size = 280; literal prcstk$S_proc_save_regs = 280; macro prcstk$q_regbase = 0,0,0,0 %; literal prcstk$s_regbase = 8; ! Not used macro prcstk$q_gp = 8,0,0,0 %; literal prcstk$s_gp = 8; ! Saved r1 macro prcstk$q_r2 = 16,0,0,0 %; literal prcstk$s_r2 = 8; ! Saved r2 macro prcstk$q_r3 = 24,0,0,0 %; literal prcstk$s_r3 = 8; ! Saved r3 macro prcstk$q_r4 = 32,0,0,0 %; literal prcstk$s_r4 = 8; ! Saved r4 macro prcstk$q_r5 = 40,0,0,0 %; literal prcstk$s_r5 = 8; ! Saved r5 macro prcstk$q_r6 = 48,0,0,0 %; literal prcstk$s_r6 = 8; ! Saved r6 macro prcstk$q_r7 = 56,0,0,0 %; literal prcstk$s_r7 = 8; ! Saved r7 macro prcstk$q_r8 = 64,0,0,0 %; literal prcstk$s_r8 = 8; ! Saved r8 macro prcstk$q_r9 = 72,0,0,0 %; literal prcstk$s_r9 = 8; ! Saved r9 macro prcstk$q_r10 = 80,0,0,0 %; literal prcstk$s_r10 = 8; ! Saved r10 macro prcstk$q_r11 = 88,0,0,0 %; literal prcstk$s_r11 = 8; ! Saved r11 macro prcstk$q_not_sp = 96,0,0,0 %; literal prcstk$s_not_sp = 8; ! Not used macro prcstk$q_r13 = 104,0,0,0 %; literal prcstk$s_r13 = 8; ! Saved r13 macro prcstk$q_r14 = 112,0,0,0 %; literal prcstk$s_r14 = 8; ! Saved r14 macro prcstk$q_r15 = 120,0,0,0 %; literal prcstk$s_r15 = 8; ! Saved r15 macro prcstk$q_r16 = 128,0,0,0 %; literal prcstk$s_r16 = 8; ! Saved r16 macro prcstk$q_r17 = 136,0,0,0 %; literal prcstk$s_r17 = 8; ! Saved r17 macro prcstk$q_r18 = 144,0,0,0 %; literal prcstk$s_r18 = 8; ! Saved r18 macro prcstk$q_r19 = 152,0,0,0 %; literal prcstk$s_r19 = 8; ! Saved r19 macro prcstk$q_r20 = 160,0,0,0 %; literal prcstk$s_r20 = 8; ! Saved r20 macro prcstk$q_r21 = 168,0,0,0 %; literal prcstk$s_r21 = 8; ! Saved r21 macro prcstk$q_r22 = 176,0,0,0 %; literal prcstk$s_r22 = 8; ! Saved r22 macro prcstk$q_r23 = 184,0,0,0 %; literal prcstk$s_r23 = 8; ! Saved r23 macro prcstk$q_r24 = 192,0,0,0 %; literal prcstk$s_r24 = 8; ! Saved r24 macro prcstk$q_r25 = 200,0,0,0 %; literal prcstk$s_r25 = 8; ! Saved r25 macro prcstk$q_r26 = 208,0,0,0 %; literal prcstk$s_r26 = 8; ! Saved r26 macro prcstk$q_r27 = 216,0,0,0 %; literal prcstk$s_r27 = 8; ! Saved r27 macro prcstk$q_r28 = 224,0,0,0 %; literal prcstk$s_r28 = 8; ! Saved r28 macro prcstk$q_r29 = 232,0,0,0 %; literal prcstk$s_r29 = 8; ! Saved r29 macro prcstk$q_r30 = 240,0,0,0 %; literal prcstk$s_r30 = 8; ! Saved r30 macro prcstk$q_r31 = 248,0,0,0 %; literal prcstk$s_r31 = 8; ! Saved r31 macro prcstk$q_pc = 256,0,0,0 %; literal prcstk$s_pc = 8; ! Saved ip+slot macro prcstk$q_psr = 264,0,0,0 %; literal prcstk$s_psr = 8; ! Saved psr macro prcstk$q_isr = 272,0,0,0 %; literal prcstk$s_isr = 8; ! Saved isr literal prcstk$k_intreg_save_size = 24; literal prcstk$S_proc_save_int_regs = 24; macro prcstk$q_virbnd = 0,0,0,0 %; literal prcstk$s_virbnd = 8; ! Saved VIRBND macro prcstk$q_sysptbr = 8,0,0,0 %; literal prcstk$s_sysptbr = 8; ! Saved SYSPTBR macro prcstk$q_scc = 16,0,0,0 %; literal prcstk$s_scc = 8; ! Saved SCC ! ! End of module proc_read_write ! !*** MODULE $PRQDEF *** ! + ! INTER-PROCESSOR REQUEST BLOCK DEFINITIONS ! ! THIS IS THE BASIC FORMAT FOR AN EXECUTIVE OR DRIVER REQUEST FROM ! ONE PROCESSOR TO ANOTHER PROCESSOR. ! - literal PRQ$C_EXEC = 0; ! EXECUTIVE REQUEST ID literal PRQ$C_MAILBOX = 1; ! MAILBOX REQUEST ID literal PRQ$C_REMDISK = 2; ! REMOTE DISK REQUEST ID literal PRQ$C_HSC50 = 3; ! HSC-50 REQUEST ID literal PRQ$C_SETEF = 0; ! COPY COMMON EVENT FLAG REQUEST ID literal PRQ$C_RESAVL = 1; ! REPORT RESOURCE AVAILABLE literal PRQ$C_MINLENGTH = 64; ! MINIMUM REQUEST BLOCK LENGTH literal PRQ$S_PRQDEF = 40; literal PRQ$S_PRQ = 40; macro PRQ$L_FLINK = 0,0,32,1 %; ! FORWARD LINK TO NEXT BLOCK macro PRQ$L_BLINK = 4,0,32,1 %; ! BACKWARD LINK TO PREVIOUS BLOCK macro PRQ$W_TO_PORT = 24,0,16,0 %; ! PORT NUMBER TO SEND REQUEST TO macro PRQ$W_FR_PORT = 26,0,16,0 %; ! PORT NUMBER REQUEST IS FROM macro PRQ$W_DISPATCH = 28,0,16,0 %; ! MESSAGE DISPATCHER ID ! MESSAGE DISPATCHER ID'S ! macro PRQ$W_REQTYPE = 32,0,16,0 %; ! REQUEST TYPE ! MESSAGE DISPATCHER REQUEST SUB-TYPES macro PRQ$W_UNIT = 34,0,16,0 %; ! UNIT NUMBER macro PRQ$L_PARAM = 36,0,32,0 %; ! FIRST PARAMETER !*** MODULE $PSCANCTXDEF *** ! ! The PSCANCTX$ structure is exchanged with remote nodes. Any updates to this ! structure must take mixed-version operation into account. ! literal pscanctx$m_super = %X'1'; literal pscanctx$m_csid_vec = %X'2'; literal pscanctx$m_locked = %X'4'; literal pscanctx$m_multi_node = %X'8'; literal pscanctx$m_busy = %X'10'; literal pscanctx$m_relock = %X'20'; literal pscanctx$m_thread = %X'40'; literal pscanctx$m_need_thread_cap = %X'80'; literal pscanctx$m_sched_class_cap = %X'100'; literal pscanctx$k_length = 64; ! length of data structure literal pscanctx$m_thread_item = 1073741824; ! item code references a node literal pscanctx$v_thread_item = 30; ! item code references a node literal pscanctx$m_node_item = -2147483648; ! item code references a node literal pscanctx$v_node_item = 31; ! item code references a node literal pscanctx$S_$pscanctxdef = 64; ! Old size name - synonym literal pscanctx$S_pscanctx = 64; macro pscanctx$l_flink = 0,0,32,1 %; ! forward link macro pscanctx$l_blink = 4,0,32,1 %; ! back link macro pscanctx$w_size = 8,0,16,0 %; ! size of structure macro pscanctx$b_type = 10,0,8,0 %; ! structure type code macro pscanctx$b_subtype = 11,0,8,0 %; ! structure subtype macro pscanctx$w_maj_vers = 12,0,16,0 %; ! incompatible level macro pscanctx$w_min_vers = 14,0,16,0 %; ! upwards-compatible level macro pscanctx$l_flags = 16,0,32,0 %; macro pscanctx$v_super = 16,0,1,0 %; ! allocated from supervisor mode macro pscanctx$v_csid_vec = 16,1,1,0 %; ! csid vector is present macro pscanctx$v_locked = 16,2,1,0 %; ! cell is locked in memory macro pscanctx$v_multi_node = 16,3,1,0 %; ! scan is for more than one node macro pscanctx$v_busy = 16,4,1,0 %; ! scan in progress on this block macro pscanctx$v_relock = 16,5,1,0 %; ! ignore BUSY flag, allow a "lock" macro pscanctx$v_thread = 16,6,1,0 %; ! PSCAN$M_THREAD specified - include threads macro pscanctx$v_need_thread_cap = 16,7,1,0 %; ! remote node needs kernel thread support macro pscanctx$v_sched_class_cap = 16,8,1,0 %; ! remote node needs class scheduling support macro pscanctx$l_cur_csid = 20,0,32,0 %; ! CSID for scan in progress macro pscanctx$l_cur_ipid = 24,0,32,0 %; ! initial IPID for scan in progress macro pscanctx$l_next_ipid = 28,0,32,0 %; ! updated IPID for scan in progress macro pscanctx$l_cur_epid = 32,0,32,0 %; ! EPID for scan in progress macro pscanctx$w_itmlstoff = 36,0,16,0 %; ! offset to item list macro pscanctx$w_bufferoff = 38,0,16,0 %; ! offset to buffer area macro pscanctx$w_csidoff = 40,0,16,0 %; ! offset to csid vector macro pscanctx$w_csididx = 42,0,16,0 %; ! index of current csid macro pscanctx$l_svapte = 44,0,32,0 %; ! sva of pte for this block macro pscanctx$l_cwpssrv = 48,0,32,1 %; ! address of CWPSSRV structure macro pscanctx$l_jpibufadr = 52,0,32,1 %; ! address of $GETJPI buffer macro pscanctx$w_seqnum = 56,0,16,0 %; ! sequence number macro pscanctx$b_acmode = 58,0,8,0 %; ! access mode of original call macro pscanctx$b_spare0 = 59,0,8,0 %; ! just a little extra macro pscanctx$l_spare1 = 60,0,32,0 %; ! just a little extra ! ! The PSCANBUF$ structure is exchanged with remote nodes. Any updates to this ! structure must take mixed-version operation into account. ! literal pscanbuf$m_spare0 = %X'1'; literal pscanbuf$k_length = 32; ! length of data structure literal pscanbuf$S_$pscanbufdef = 32; ! Old size name - synonym literal pscanbuf$S_pscanbuf = 32; macro pscanbuf$l_buflen = 0,0,32,0 %; ! length of data area macro pscanbuf$l_spare0 = 4,0,32,0 %; ! spare0 macro pscanbuf$w_size = 8,0,16,0 %; ! size of structure macro pscanbuf$b_type = 10,0,8,0 %; ! structure type code macro pscanbuf$b_subtype = 11,0,8,0 %; ! structure subtype macro pscanbuf$w_maj_vers = 12,0,16,0 %; ! incompatible level macro pscanbuf$w_min_vers = 14,0,16,0 %; ! upwards-compatible level macro pscanbuf$l_flags = 16,0,32,0 %; macro pscanbuf$v_spare0 = 16,0,1,0 %; ! filler macro pscanbuf$l_itmlstadr = 20,0,32,1 %; ! address of copy of JPI item list macro pscanbuf$l_buffer_offset = 24,0,32,0 %; ! offset to start of buffer macro pscanbuf$l_free_offset = 28,0,32,0 %; ! offset to next free byte ! ! The PSCANITM$ structure is a local structure. If modified, you do not need ! to take mixed-version operation into account, however you must be sure that ! all modules and images which reference the structure are updated together. ! literal pscanitm$k_length = 12; ! length of data structure literal pscanitm$S_$pscanitmdef = 13; ! Old size name - synonym literal pscanitm$S_pscanitm = 13; macro pscanitm$l_alloc_length = 0,0,32,0 %; ! allocated length macro pscanitm$l_itmlen = 4,0,32,0 %; ! length of item list macro pscanitm$w_size = 8,0,16,0 %; ! size of header macro pscanitm$b_type = 10,0,8,0 %; ! structure type code macro pscanitm$b_subtype = 11,0,8,0 %; ! structure subtype macro pscanitm$b_itmlst = 12,0,8,0 %; ! start of the item list !*** MODULE $PSMDEF *** ! Print symbiont definitions ! + ! Symbolic definitions for print symbionts. ! ! Public definition of various constants and data structures ! used by the standard VMS print symbiont, and by user modified ! print symbionts. ! ! - ! ! Service routine function codes ! ! ! IO functions ! literal PSM$K_CANCEL = 1; ! Cancel pending operations literal PSM$K_CLOSE = 2; ! Release resources literal PSM$K_FORMAT = 3; ! Format buffer literal PSM$K_OPEN = 4; ! Obtain resources literal PSM$K_READ = 5; ! Read literal PSM$K_GET_KEY = 6; ! Read record key literal PSM$K_POSITION_TO_KEY = 7; ! Read by record context literal PSM$K_REWIND = 8; ! Rewind file literal PSM$K_WRITE = 9; ! Write literal PSM$K_WRITE_NOFORMAT = 10; ! Write with driver formatting disabled literal PSM$K_WRITE_SUPPRESSED = 11; ! Write but suppress output ! ! Message notification functions ! literal PSM$K_PAUSE_TASK = 12; ! STOP /QUEUE literal PSM$K_RESET_STREAM = 13; ! STOP /QUEUE /RESET literal PSM$K_RESUME_TASK = 14; ! START /QUEUE (when paused) literal PSM$K_START_STREAM = 15; ! START /QUEUE (when stopped) literal PSM$K_START_TASK = 16; ! (ofiginated by job controller) literal PSM$K_STOP_TASK = 17; ! STOP /QUEUE /ABORT or /REQUEUE literal PSM$K_STOP_STREAM = 18; ! STOP /QUEUE /NEXT ! ! Replacement routines ! ! ! Task services -- where applicable the ordering of these literals ! determines the sequence of the corresponding service routines. ! ! ! Page services ! literal PSM$K_PAGE_SETUP = 1; ! Page setup - page setup modules literal PSM$K_PAGE_HEADER = 2; ! Page separation - page headers ! ! Library module service ! literal PSM$K_LIBRARY_INPUT = 3; ! Module services ! ! Filter services ! literal PSM$K_INPUT_FILTER = 4; ! Filter service - input literal PSM$K_MAIN_FORMAT = 5; ! Format service - carriage control literal PSM$K_OUTPUT_FILTER = 6; ! Filter service - output ! ! Output services ! literal PSM$K_OUTPUT = 7; ! Main output routine ! ! General input services ! literal PSM$K_JOB_SETUP = 8; ! Job setup - job reset modules literal PSM$K_FORM_SETUP = 9; ! Form setup - form setup modules literal PSM$K_JOB_FLAG = 10; ! Job separation - flag page literal PSM$K_JOB_BURST = 11; ! Job separation - burst page literal PSM$K_FILE_SETUP = 12; ! File setup - file setup modules literal PSM$K_FILE_FLAG = 13; ! File separation - flag page literal PSM$K_FILE_BURST = 14; ! File separation - burst page literal PSM$K_FILE_SETUP_2 = 15; ! File setup - top of form literal PSM$K_MAIN_INPUT = 16; ! File service - main routine literal PSM$K_FILE_INFORMATION = 17; ! Additional information print literal PSM$K_FILE_ERRORS = 18; ! Errors during task processing literal PSM$K_FILE_TRAILER = 19; ! File separation - trailer page literal PSM$K_JOB_RESET = 20; ! Job reset - job reset modules literal PSM$K_JOB_TRAILER = 21; ! Job separation - trailer page literal PSM$K_JOB_COMPLETION = 22; ! Job completion - top of form literal PSM$K_PAGE_FOOTER = 23; ! Page separation - page footers literal PSM$k_max = 24; ! MUST BE LAST ! ! Carriage control types ! literal PSM$K_CC_INTERNAL = 1; ! - imbedded literal PSM$K_CC_IMPLIED = 2; ! - implied literal PSM$K_CC_FORTRAN = 3; ! - fortran literal PSM$K_CC_PRINT = 4; ! - print file (PRN) literal PSM$K_CC_MAX = 5; ! MUST BE LAST literal PSM$M_LAT_PROTOCOL = %X'1'; literal PSM$S_P5_FLAGS = 4; ! PSM$PRINT PaRAMETER 5 macro PSM$L_FLAGS = 0,0,32,0 %; macro PSM$V_LAT_PROTOCOL = 0,0,1,0 %; ! !*** MODULE $PSRDEF *** ! ! Definitions for Processor Status Register ! literal PSR$M_USER_MASK = %X'3F'; literal PSR$M_SYSTEM_MASK = %X'FFFFFF'; literal PSR$M_RV0 = %X'1'; literal PSR$M_BE = %X'2'; literal PSR$M_UP = %X'4'; literal PSR$M_AC = %X'8'; literal PSR$M_MFL = %X'10'; literal PSR$M_MFH = %X'20'; literal PSR$M_MBZ0 = %X'1FC0'; literal PSR$M_IC = %X'2000'; literal PSR$M_I = %X'4000'; literal PSR$M_PK = %X'8000'; literal PSR$M_MBZ1 = %X'10000'; literal PSR$M_DT = %X'20000'; literal PSR$M_DFL = %X'40000'; literal PSR$M_DFH = %X'80000'; literal PSR$M_SP = %X'100000'; literal PSR$M_PP = %X'200000'; literal PSR$M_DI = %X'400000'; literal PSR$M_SI = %X'800000'; literal PSR$M_DB = %X'1000000'; literal PSR$M_LP = %X'2000000'; literal PSR$M_TB = %X'4000000'; literal PSR$M_RT = %X'8000000'; literal PSR$M_MBZ2 = %X'F0000000'; literal PSR$M_CPL = %X'300000000'; literal PSR$M_IS = %X'400000000'; literal PSR$M_MC = %X'800000000'; literal PSR$M_IT = %X'1000000000'; literal PSR$M_ID = %X'2000000000'; literal PSR$M_DA = %X'4000000000'; literal PSR$M_DD = %X'8000000000'; literal PSR$M_SS = %X'10000000000'; literal PSR$M_RI = %X'60000000000'; literal PSR$M_ED = %X'80000000000'; literal PSR$M_BN = %X'100000000000'; literal PSR$M_IA = %X'200000000000'; literal PSR$M_MBZ3 = %X'FFFFC00000000000'; literal PSR$S_PSR = 8; macro PSR$R_PSR_UNION = 0,0,0,0 %; literal PSR$S_PSR_UNION = 8; macro PSR$Q_PROCESSOR_STATUS = 0,0,0,0 %; literal PSR$S_PROCESSOR_STATUS = 8; ! Processor status register - entire 64-bits macro PSR$V_USER_MASK = 0,0,6,0 %; literal PSR$S_USER_MASK = 6; ! User mask bits PSR{5:0} macro PSR$V_SYSTEM_MASK = 0,0,24,0 %; literal PSR$S_SYSTEM_MASK = 24; ! System mask bits PSR{23:0} macro PSR$V_RV0 = 0,0,1,0 %; ! 0 Reserved bit PSR{0:0} macro PSR$V_BE = 0,1,1,0 %; ! 1 Big-Endian macro PSR$V_UP = 0,2,1,0 %; ! 2 User Performance monitor enabled macro PSR$V_AC = 0,3,1,0 %; ! 3 Alignment Check macro PSR$V_MFL = 0,4,1,0 %; ! 4 Lower (f2..f31) floating-point registers written macro PSR$V_MFH = 0,5,1,0 %; ! 5 Upper (f32..f127) floating-point registers written macro PSR$V_MBZ0 = 0,6,7,0 %; literal PSR$S_MBZ0 = 7; ! 6-12 Reserved bits PSR{12:6} (MBZ) macro PSR$V_IC = 0,13,1,0 %; ! 13 Interruption Collection macro PSR$V_I = 0,14,1,0 %; ! 14 Interrupt bit macro PSR$V_PK = 0,15,1,0 %; ! 15 Protection Key enable macro PSR$V_MBZ1 = 0,16,1,0 %; ! 16 Reserved bit PSR{16:16} (MBZ) macro PSR$V_DT = 0,17,1,0 %; ! 17 Data address Translation macro PSR$V_DFL = 0,18,1,0 %; ! 18 Disabled Floating-point Low register set macro PSR$V_DFH = 0,19,1,0 %; ! 19 Disabled Floating-point High register set macro PSR$V_SP = 0,20,1,0 %; ! 20 Secure Performance monitors macro PSR$V_PP = 0,21,1,0 %; ! 21 Privileged Performance monitor enable macro PSR$V_DI = 0,22,1,0 %; ! 22 Disable Instruction set transition macro PSR$V_SI = 0,23,1,0 %; ! 23 Secure Interval timer macro PSR$V_DB = 0,24,1,0 %; ! 24 Debug Breakpoint fault macro PSR$V_LP = 0,25,1,0 %; ! 25 Lower Privilege transfer trap macro PSR$V_TB = 0,26,1,0 %; ! 26 Taken Branch trap macro PSR$V_RT = 0,27,1,0 %; ! 27 Register stack Translation macro PSR$V_MBZ2 = 0,28,4,0 %; literal PSR$S_MBZ2 = 4; ! 28-31 Reserved bits PSR{31:28} (MBZ) macro PSR$V_CPL = 4,0,2,0 %; literal PSR$S_CPL = 2; ! 32-33 Current Privilege Level macro PSR$V_IS = 4,2,1,0 %; ! 34 Instruction Set macro PSR$V_MC = 4,3,1,0 %; ! 35 Machine Check abort mask macro PSR$V_IT = 4,4,1,0 %; ! 36 Instruction address Translation macro PSR$V_ID = 4,5,1,0 %; ! 37 Instruction Debug fault disable macro PSR$V_DA = 4,6,1,0 %; ! 38 Disable Data Access and Dirty-bit faults macro PSR$V_DD = 4,7,1,0 %; ! 39 Data Debug fault disable macro PSR$V_SS = 4,8,1,0 %; ! 40 Single Step enable macro PSR$V_RI = 4,9,2,0 %; literal PSR$S_RI = 2; ! 41-42 Restart Instruction macro PSR$V_ED = 4,11,1,0 %; ! 43 Exception Deferral macro PSR$V_BN = 4,12,1,0 %; ! 44 Register bank macro PSR$V_IA = 4,13,1,0 %; ! 45 Disable Instruction Access-bit faults macro PSR$V_MBZ3 = 4,14,18,0 %; literal PSR$S_MBZ3 = 18; ! 46-63 Reserved bits PSR{63:46} literal IS$C_IA64 = 0; ! IA64 literal IS$C_IA32 = 1; ! IA32 !*** MODULE $PROCSTATE *** literal PSTATE$K_LENGTH = 272; ! Length of process state literal PSTATE$S_PROCSTATE = 272; macro PSTATE$Q_R8 = 0,0,0,0 %; literal PSTATE$S_R8 = 8; ! register R8 macro PSTATE$Q_R9 = 8,0,0,0 %; literal PSTATE$S_R9 = 8; ! register R9 macro PSTATE$Q_R10 = 16,0,0,0 %; literal PSTATE$S_R10 = 8; ! register R10 macro PSTATE$Q_R11 = 24,0,0,0 %; literal PSTATE$S_R11 = 8; ! register R11 macro PSTATE$Q_R12 = 32,0,0,0 %; literal PSTATE$S_R12 = 8; ! register R12 macro PSTATE$Q_R13 = 40,0,0,0 %; literal PSTATE$S_R13 = 8; ! register R13 macro PSTATE$Q_R14 = 48,0,0,0 %; literal PSTATE$S_R14 = 8; ! register R14 macro PSTATE$Q_R15 = 56,0,0,0 %; literal PSTATE$S_R15 = 8; ! register R15 macro PSTATE$Q_R29 = 64,0,0,0 %; literal PSTATE$S_R29 = 8; ! register R29 macro PSTATE$Q_ALIGN_0 = 72,0,0,0 %; literal PSTATE$S_ALIGN_0 = 8; ! for alignment macro PSTATE$Q_R0 = 80,0,0,0 %; literal PSTATE$S_R0 = 8; ! register R0 macro PSTATE$Q_R1 = 88,0,0,0 %; literal PSTATE$S_R1 = 8; ! register R1 macro PSTATE$Q_R16 = 96,0,0,0 %; literal PSTATE$S_R16 = 8; ! register R16 macro PSTATE$Q_R17 = 104,0,0,0 %; literal PSTATE$S_R17 = 8; ! register R17 macro PSTATE$Q_R18 = 112,0,0,0 %; literal PSTATE$S_R18 = 8; ! register R18 macro PSTATE$Q_R19 = 120,0,0,0 %; literal PSTATE$S_R19 = 8; ! register R19 macro PSTATE$Q_R20 = 128,0,0,0 %; literal PSTATE$S_R20 = 8; ! register R20 macro PSTATE$Q_R21 = 136,0,0,0 %; literal PSTATE$S_R21 = 8; ! register R21 macro PSTATE$Q_R22 = 144,0,0,0 %; literal PSTATE$S_R22 = 8; ! register R22 macro PSTATE$Q_R23 = 152,0,0,0 %; literal PSTATE$S_R23 = 8; ! register R23 macro PSTATE$Q_R24 = 160,0,0,0 %; literal PSTATE$S_R24 = 8; ! register R24 macro PSTATE$Q_R25 = 168,0,0,0 %; literal PSTATE$S_R25 = 8; ! register R25 macro PSTATE$Q_R26 = 176,0,0,0 %; literal PSTATE$S_R26 = 8; ! register R26 macro PSTATE$Q_R27 = 184,0,0,0 %; literal PSTATE$S_R27 = 8; ! register R27 macro PSTATE$Q_R28 = 192,0,0,0 %; literal PSTATE$S_R28 = 8; ! register R28 macro PSTATE$Q_ALIGN_1 = 200,0,0,0 %; literal PSTATE$S_ALIGN_1 = 8; ! for alignment macro PSTATE$Q_R2 = 208,0,0,0 %; literal PSTATE$S_R2 = 8; ! register R2 macro PSTATE$Q_R3 = 216,0,0,0 %; literal PSTATE$S_R3 = 8; ! register R3 macro PSTATE$Q_R4 = 224,0,0,0 %; literal PSTATE$S_R4 = 8; ! register R4 macro PSTATE$Q_R5 = 232,0,0,0 %; literal PSTATE$S_R5 = 8; ! register R5 macro PSTATE$Q_R6 = 240,0,0,0 %; literal PSTATE$S_R6 = 8; ! register R6 macro PSTATE$Q_R7 = 248,0,0,0 %; literal PSTATE$S_R7 = 8; ! register R7 macro PSTATE$Q_PC = 256,0,0,0 %; literal PSTATE$S_PC = 8; ! register PC macro PSTATE$Q_PS = 264,0,0,0 %; literal PSTATE$S_PS = 8; ! register PS !*** MODULE $PSXFCBDEF *** ! amount of space reserved to save kernel stack ! during callbacks ! and the exec stack ! ! The following structure contains data about the process's use of fork ! callbacks. There is at most one of these per process and it is ! referenced through the P1 space cell CTL$GL_FORK_CONTROL_BLOCK ! literal PSXFCB$M_DISABLED = %X'1'; literal PSXFCB$C_KERN_SAVE_SIZE = 384; literal PSXFCB$K_KERN_SAVE_SIZE = 384; literal PSXFCB$C_EXEC_STACK_SAVE = 1280; literal PSXFCB$K_EXEC_STACK_SAVE = 1280; literal PSXFCB$S_PSXFCB = 6776; macro PSXFCB$L_FLINK = 0,0,32,1 %; ! forward link (unused) macro PSXFCB$L_BLINK = 4,0,32,1 %; ! backeard link (unused) macro PSXFCB$W_SIZE = 8,0,16,0 %; ! size allocated macro PSXFCB$B_TYPE = 10,0,8,0 %; ! block type macro PSXFCB$B_SUBTYPE = 11,0,8,0 %; ! sub type macro PSXFCB$R_FLAGS = 12,0,32,0 %; literal PSXFCB$S_FLAGS = 4; ! flags longword macro PSXFCB$V_DISABLED = 12,0,1,0 %; ! callbacks are diabled macro PSXFCB$V_SPARE = 12,1,31,0 %; literal PSXFCB$S_SPARE = 31; macro PSXFCB$L_BLOCK_COUNT = 16,0,0,1 %; literal PSXFCB$S_BLOCK_COUNT = 16; ! per-mode block counters macro PSXFCB$L_HANDLER_COUNT = 32,0,0,1 %; literal PSXFCB$S_HANDLER_COUNT = 16; ! count of handlers macro PSXFCB$L_WAIT = 48,0,0,1 %; literal PSXFCB$S_WAIT = 16; ! wait counters (unused macro PSXFCB$L_WHEN = 64,0,32,1 %; ! when callbacks are being call macro PSXFCB$L_FAILED_WHEN = 68,0,32,1 %; ! state of when bits on failure macro PSXFCB$L_CANCEL_STATE = 72,0,32,1 %; ! mode (+1) of failure macro PSXFCB$L_CALLBACK_STATE = 76,0,32,1 %; ! mode (+1) of current callbacks macro PSXFCB$L_PID = 80,0,32,0 %; ! pid of 'other' process macro PSXFCB$L_FAILING_DISP = 84,0,32,0 %; ! psxdisp address of failing cb macro PSXFCB$L_IMAGE_LIST = 88,0,32,1 %; ! pointer to first image fdb macro PSXFCB$L_PROCESS_LIST = 92,0,32,1 %; ! pointer to first process fdb macro PSXFCB$L_OUTER_STACK = 96,0,32,0 %; ! saved outer mode stack for cbs macro PSXFCB$L_SAVE_AP = 100,0,32,0 %; ! saved AP during callbacks macro PSXFCB$L_SAVE_FP = 104,0,32,0 %; ! saved FP during cbs macro PSXFCB$L_SAVE_SP = 108,0,32,0 %; ! saved sp during cbs macro PSXFCB$L_SAVE_PSL = 112,0,32,0 %; ! saved psl during cbs macro PSXFCB$L_SAVE_EXEC_SP = 116,0,32,0 %; ! saved exec stack pointer ! ! The area below is used to save the kernel mode stack contents while ! callbacks are being made ! macro PSXFCB$L_STACK_SAVE_AREA = 120,0,0,0 %; literal PSXFCB$S_STACK_SAVE_AREA = 1536; macro PSXFCB$L_EXEC_STACK_AREA = 1656,0,0,0 %; literal PSXFCB$S_EXEC_STACK_AREA = 5120; !*** MODULE $PSXFDBDEF *** ! ! PSXDISP is the format of a callback dispatch. there is an array of ! callback dispatched in each PSXFDB structure. ! literal PSXDISP$M_DISABLED = %X'1'; literal PSXDISP$S_PSXDISP = 20; macro PSXDISP$R_FLAGS = 0,0,32,0 %; literal PSXDISP$S_FLAGS = 4; ! flag word macro PSXDISP$V_DISABLED = 0,0,1,0 %; ! this callback is disabled macro PSXDISP$V_SPARE = 0,1,31,0 %; literal PSXDISP$S_SPARE = 31; ! fill out the longword ! macro PSXDISP$L_WHEN = 4,0,32,0 %; ! when the callback are to be made macro PSXDISP$L_ACMODE = 8,0,32,0 %; ! access mode of the callback macro PSXDISP$L_HANDLER = 12,0,32,1 %; ! address of the callback handler macro PSXDISP$L_ARG = 16,0,32,0 %; ! argument to pass to the handler ! stack ! ! This structure is used to make lists of callbacks routines ! ! literal PSXFDB$C_numcalls = 10; literal PSXFDB$K_numcalls = 10; literal PSXFDB$S_PSXFDB = 212; macro PSXFDB$L_SQFL = 0,0,32,1 %; ! link to next fdb macro PSXFDB$L_SQBL = 4,0,32,1 %; ! link to prev fdb macro PSXFDB$W_SIZE = 8,0,16,0 %; ! size macro PSXFDB$B_TYPE = 10,0,8,0 %; ! type macro PSXFDB$B_SUBTYPE = 11,0,8,0 %; macro PSXFDB$B_CALLS = 12,0,0,1 %; literal PSXFDB$S_CALLS = 200; ! array of dispatches !*** MODULE $PSXROODEF *** ! ! Definition of the structures for storing POSIX root ! information. Also used the the current working directory ! (CWD), which functions for relative pathnames much like the ! root does for absolute names. ! literal PSXROO$K_DVISIZ = 16; ! size of DVI literal PSXROO$C_BLN = 32; ! structure length (with C tag) literal PSXROO$K_BLN = 32; ! structure length (with K tag) literal PSXROO$S_PSXROO = 32; macro PSXROO$W_FID_NUM = 0,0,16,0 %; ! FID NUM macro PSXROO$W_FID_SEQ = 2,0,16,0 %; ! FID SEQ macro PSXROO$W_FID_RVN = 4,0,16,0 %; ! FID RVN macro PSXROO$Q_FID = 0,0,0,0 %; literal PSXROO$S_FID = 8; ! FID as a single field macro PSXROO$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro PSXROO$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE CODE macro PSXROO$B_SUBTYPE = 11,0,8,0 %; ! REQUEST ACCESS MODE macro PSXROO$W_CHAN = 12,0,16,0 %; ! for CWD, we keep a channel to the directory file. macro PSXROO$T_DVIBUF = 16,0,0,0 %; literal PSXROO$S_DVIBUF = 16; ! device (DVI) string buffer !*** MODULE $PTADEF *** ! ! Definitions for Page Table Address register (PTA - CR8) ! literal PTA$M_VE = %X'1'; literal PTA$M_MBZ0 = %X'2'; literal PTA$M_SIZE = %X'FC'; literal PTA$M_VF = %X'100'; literal PTA$M_MBZ1 = %X'7E00'; literal PTA$M_BASE_MASK = %X'7FFF'; literal PTA$M_BASE = %X'FFFFFFFFFFFF8000'; literal PTA$S_PTA = 8; macro PTA$R_PTA_UNION = 0,0,0,0 %; literal PTA$S_PTA_UNION = 8; macro PTA$Q_PAGE_TABLE_ADDR = 0,0,0,0 %; literal PTA$S_PAGE_TABLE_ADDR = 8; macro PTA$V_VE = 0,0,1,0 %; ! VHPT walker enabled macro PTA$V_MBZ0 = 0,1,1,0 %; ! Reserved - PTA{1:1} (MBZ) macro PTA$V_SIZE = 0,2,6,0 %; literal PTA$S_SIZE = 6; ! VHPT Size - power of 2 increments macro PTA$V_VF = 0,8,1,0 %; ! VHPT format, 0 = short, 1 = long macro PTA$V_MBZ1 = 0,9,6,0 %; literal PTA$S_MBZ1 = 6; ! Reserved - PTA{14:9} (MBZ) macro PTA$V_BASE_MASK = 0,0,15,0 %; literal PTA$S_BASE_MASK = 15; ! Mask for base VA macro PTA$V_BASE = 0,15,49,0 %; literal PTA$S_BASE = 49; ! VHPT base virtual address literal VHPT$C_SHORT = 0; ! VF = 0, Short VHPT format literal VHPT$C_LONG = 1; ! VF = 1, Long VHPT format literal VHPT$C_SHORT_SIZE = 8; ! VHPT short format structure size literal VHPT$C_LONG_SIZE = 32; ! VHPT long format structure size literal VHPT$C_MIN_TABLE_SIZE = 32768; ! Minimum VHPT table size !*** MODULE $PTRDEF *** ! + ! POINTER CONTROL BLOCK ! THIS IS A STRUCTURE OF POINTERS TO OTHER DYNAMIC STRUCTURES ! OF LIKE KIND. TYPICALLY THE STRUCTURES POINTED TO ARE KNOWN ! BY THEIR LONG WORD INDEX INTO THE TABLE AND TO FACILITATE FETCHING ! THESE, IT IS CONVENTIONAL TO KEEP A POINTER TO THE BASE OF THE ! STRUCTURE POINTERS RATHER THAN (OR IN ADDITION TO) THE POINTER ! TO THE FRONT OF THE POINTER CONTROL BLOCK. THE NUMBER OF POINTERS ! IN THE ARRAY PRECEEDS THE FIRST POINTER IN THE ARRAY. ! - literal PTR$K_LENGTH = 16; ! LENGTH OF FIXED PORTION literal PTR$C_LENGTH = 16; ! LENGTH OF FIXED PORTION literal PTR$S_PTRDEF = 20; literal PTR$S_PTR = 24; macro PTR$Q_INFO_QUAD = 0,0,0,0 %; literal PTR$S_INFO_QUAD = 8; macro PTR$L_INFO_LONG0 = 0,0,32,0 %; macro PTR$L_INFO_LONG1 = 4,0,32,0 %; macro PTR$W_SIZE = 8,0,16,0 %; ! SIZE OF DYNAMIC CONTROL BLOCK macro PTR$B_TYPE = 10,0,8,0 %; ! TYPE OF DYNAMIC CONTROL BLOCK macro PTR$B_PTRTYPE = 11,0,8,0 %; ! TYPE OF CONTROL BLOCK POINTED TO macro PTR$L_PTRCNT = 12,0,32,0 %; ! COUNT OF ENTRIES macro PTR$L_PTR0 = 16,0,32,1 %; ! PTR NUMBER 0 !*** MODULE $PWDHISDEF *** ! Password History Record - This structure defines the layout of the system ! password history file. This is a variable record length indexed file (keyed ! by username) where each record contains the last "n" quadword hash values for ! the user's last "n" passwords. literal PWDHIS$C_ENTRY_LENGTH = 16; ! size of one entry literal PWDHIS$K_ENTRY_LENGTH = 16; ! size of one entry literal PWDHIS$S_PWDENTDEF = 16; literal PWDHIS$S_PWDENT = 16; macro PWDHIS$Q_ENTRY = 0,0,0,1 %; literal PWDHIS$S_ENTRY = 8; ! the quadword hash macro PWDHIS$Q_CHANGE = 8,0,0,1 %; literal PWDHIS$S_CHANGE = 8; ! password change date literal PWDHIS$C_FIXED = 32; ! fixed part of record literal PWDHIS$K_FIXED = 32; ! fixed part of record literal PWDHIS$C_DEFAULT_LIFETIME = 365; ! default history lifetime (days) literal PWDHIS$K_DEFAULT_LIFETIME = 365; ! default history lifetime (days) literal PWDHIS$C_DEFAULT_LIMIT = 60; ! default # of history entries per user literal PWDHIS$K_DEFAULT_LIMIT = 60; ! default # of history entries per user literal PWDHIS$C_MAXIMUM_LIMIT = 2000; ! maximum # of history entries per user literal PWDHIS$K_MAXIMUM_LIMIT = 2000; ! maximum # of history entries per user literal PWDHIS$S_PWDHISDEF = 32032; literal PWDHIS$S_PWDHIS = 32032; macro PWDHIS$T_USERNAME = 0,0,0,0 %; literal PWDHIS$S_USERNAME = 32; ! username (KEY0) macro PWDHIS$R_HISTORY = 32,0,0,0 %; literal PWDHIS$S_HISTORY = 32000; ! offset to start of list macro PWDHIS$R_HISTORY_ENTRY = 32,0,0,0 %; literal PWDHIS$S_HISTORY_ENTRY = 16; !*** MODULE $PXBDEF *** literal PXB$S_PXB = 12; macro PXB$L_FLINK = 0,0,32,1 %; ! forward link macro PXB$L_BLINK = 4,0,32,1 %; ! backward link macro PXB$W_SIZE = 8,0,16,0 %; ! size macro PXB$B_TYPE = 10,0,8,0 %; ! type code macro PXB$B_SUBTYPE = 11,0,8,0 %; ! subtype code literal PXB$K_LENGTH = 12; ! Length of header ! ! PXB Array (Persona Extension Block Array) ! literal PXB_ARRAY_ELEMENTS = 16; literal PXB_ARRAY$K_PXB_ARRAY_HEADER = 12; literal PXB_ARRAY$S_PXB_ARRAY = 76; macro PXB_ARRAY$L_FLINK = 0,0,32,1 %; ! forward link macro PXB_ARRAY$L_BLINK = 4,0,32,1 %; ! backward link macro PXB_ARRAY$W_SIZE = 8,0,16,0 %; ! size macro PXB_ARRAY$B_TYPE = 10,0,8,0 %; ! type code macro PXB_ARRAY$B_SUBTYPE = 11,0,8,0 %; ! subtype code macro PXB_ARRAY$AR_ELEMENTS = 12,0,0,0 %; literal PXB_ARRAY$S_ELEMENTS = 64; ! The array cells ! ! delegate block ! literal DELBK$S_DELBK = 40; macro DELBK$L_FLINK = 0,0,32,1 %; ! forward link macro DELBK$L_BLINK = 4,0,32,1 %; ! backward link macro DELBK$W_SIZE = 8,0,16,0 %; ! size macro DELBK$B_TYPE = 10,0,8,0 %; ! type code macro DELBK$B_SUBTYPE = 11,0,8,0 %; ! subtype cod macro DELBK$L_PERSONA_ID = 12,0,32,0 %; ! Persona ID macro DELBK$L_PERSONA_ADDRESS = 16,0,32,0 %; ! Persona address macro DELBK$L_CLIENT_EPID = 20,0,32,0 %; ! Client's EPID macro DELBK$L_CLIENT_TPID = 24,0,32,0 %; ! Client's Thread PID macro DELBK$L_BYTCNT = 28,0,32,0 %; ! BYTCNT/BYTLM to be debited upon delegation macro DELBK$L_IMGCNT = 32,0,32,0 %; ! Value of PHD$L_IMGCNT when we started macro DELBK$L_STATUS = 36,0,32,0 %; ! status literal DELBK$C_DELEGATE_BLOCK_SIZE = 40; ! Length of DELBK struct ! ! Persona Security Extension Registration Block definitions ! literal PXRB$S_PXRB = 88; macro PXRB$L_FLINK = 0,0,32,1 %; ! forward link macro PXRB$L_BLINK = 4,0,32,1 %; ! backward link macro PXRB$W_SIZE = 8,0,16,0 %; ! size macro PXRB$B_TYPE = 10,0,8,0 %; ! type code macro PXRB$B_SUBTYPE = 11,0,8,0 %; ! subtype cod macro PXRB$L_FLAGS = 12,0,32,0 %; ! macro PXRB$L_EID = 16,0,32,0 %; ! Extension ID macro PXRB$L_NAME_DESC = 20,0,0,0 %; literal PXRB$S_NAME_DESC = 8; ! Extension name descriptor macro PXRB$AR_NAME = 28,0,0,0 %; literal PXRB$S_NAME = 32; ! Extension name string macro PXRB$A_CREATE = 60,0,32,0 %; ! Pointer to CREATE routine macro PXRB$A_CLONE = 64,0,32,0 %; ! Pointer to CLONE routine macro PXRB$A_DELEGATE = 68,0,32,0 %; ! Pointer to DELEGATE routine macro PXRB$A_DELETE = 72,0,32,0 %; ! Pointer to DELETE routine macro PXRB$A_MODIFY = 76,0,32,0 %; ! Pointer to MODIFY routine macro PXRB$A_QUERY = 80,0,32,0 %; ! Pointer to QUERY routine macro PXRB$A_MAKE_TLV = 84,0,32,0 %; ! Pointer to MAKE_TLV routine literal PXRB$K_LENGTH = 88; ! Length of PXRB struct ! ! Persona Security Extension Dispatch Vector Block definitions ! literal PXDV$K_version = 1; literal PXDV$K_min_version = 1; literal PXDV$K_max_version = 1; literal PXDV$S_PXDV = 40; macro PXDV$L_VERSION = 0,0,32,0 %; ! Version of dispatch vector macro PXDV$L_FLAGS = 4,0,32,0 %; ! macro PXDV$A_CREATE = 8,0,32,0 %; ! Address to CREATE routine macro PXDV$A_CLONE = 12,0,32,0 %; ! Address to CLONE routine macro PXDV$A_DELEGATE = 16,0,32,0 %; ! Address to DELEGATE routine macro PXDV$A_DELETE = 20,0,32,0 %; ! Address to DELETE routine macro PXDV$A_MODIFY = 24,0,32,0 %; ! Address to MODIFY routine macro PXDV$A_QUERY = 28,0,32,0 %; ! Address to QUERY routine macro PXDV$A_MAKE_TLV = 32,0,32,0 %; ! Address to MAKE_TLV routine ! ! Persona Security Extension Block definitions for NT ! literal PXBNT$K_VERSION_1 = 1; ! version number 1 literal PXBNT$K_CURRENT_VERSION = 1; ! current protocol literal PXBNT$M_CLONE = %X'1'; literal PXBNT$M_DELEGATE = %X'2'; literal PXBNT$M_FILL_3 = %X'4'; literal PXBNT$M_FILL_4 = %X'8'; literal PXBNT$M_FILL_5 = %X'10'; literal PXBNT$M_FILL_6 = %X'20'; literal PXBNT$M_FILL_7 = %X'40'; literal PXBNT$M_DEBIT = %X'80'; literal PXBNT$K_LENGTH = 88; ! Length of PXBNT structure literal PXBNT$S_PXBNT = 88; macro PXBNT$L_FLINK = 0,0,32,1 %; ! forward link macro PXBNT$L_BLINK = 4,0,32,1 %; ! backward link macro PXBNT$W_SIZE = 8,0,16,0 %; ! size, in bytes macro PXBNT$B_TYPE = 10,0,8,0 %; ! type code for PXBNT (DYN$C_SECURITY) macro PXBNT$B_SUBTYPE = 11,0,8,0 %; ! subtype code (DYN$C_SECURITY_PSB) macro PXBNT$L_VERSION = 12,0,32,0 %; ! version number macro PXBNT$L_FLAGS = 16,0,32,0 %; ! flags macro PXBNT$V_CLONE = 16,0,1,0 %; ! Clone operation macro PXBNT$V_DELEGATE = 16,1,1,0 %; ! Delegate operation macro PXBNT$V_FILL_3 = 16,2,1,0 %; macro PXBNT$V_FILL_4 = 16,3,1,0 %; macro PXBNT$V_FILL_5 = 16,4,1,0 %; macro PXBNT$V_FILL_6 = 16,5,1,0 %; macro PXBNT$V_FILL_7 = 16,6,1,0 %; macro PXBNT$V_DEBIT = 16,7,1,0 %; ! DEBIT ! This bit must be in ! synch with PSB flag. macro PXBNT$Q_DOI = 20,0,0,0 %; literal PXBNT$S_DOI = 8; macro PXBNT$L_DOI = 20,0,32,0 %; macro PXBNT$L_DOI_PID = 24,0,32,0 %; macro PXBNT$L_USER_REFCOUNT = 28,0,32,0 %; macro PXBNT$W_NT_OWF_PASSWORD_LENGTH = 32,0,16,0 %; macro PXBNT$W_LM_OWF_PASSWORD_LENGTH = 34,0,16,0 %; macro PXBNT$T_NT_OWF_PASSWORD = 36,0,0,0 %; literal PXBNT$S_NT_OWF_PASSWORD = 16; macro PXBNT$T_LM_OWF_PASSWORD = 52,0,0,0 %; literal PXBNT$S_LM_OWF_PASSWORD = 16; macro PXBNT$W_USERNAME_O = 68,0,16,0 %; macro PXBNT$W_USERNAME_S = 70,0,16,0 %; macro PXBNT$W_DOMAIN_O = 72,0,16,0 %; macro PXBNT$W_DOMAIN_S = 74,0,16,0 %; macro PXBNT$W_USER_SESSION_KEY_O = 76,0,16,0 %; macro PXBNT$W_USER_SESSION_KEY_S = 78,0,16,0 %; macro PXBNT$W_LM_SESSION_KEY_O = 80,0,16,0 %; macro PXBNT$W_LM_SESSION_KEY_S = 82,0,16,0 %; macro PXBNT$L_DATA_SIZE = 84,0,32,0 %; ! size of data area macro PXBNT$T_DATA = 88,0,0,0 %; ! start of data area ! ! PXB_FLAGS - These are generic PXB flags common to all Extensions. ! literal PXB$M_FILL_1 = %X'1'; literal PXB$M_FILL_2 = %X'2'; literal PXB$M_FILL_3 = %X'4'; literal PXB$M_FILL_4 = %X'8'; literal PXB$M_FILL_5 = %X'10'; literal PXB$M_FILL_6 = %X'20'; literal PXB$M_FILL_7 = %X'40'; literal PXB$M_DEBIT = %X'80'; literal PXB$S_PXB_FLAGS = 4; ! flags macro PXB$V_FILL_1 = 0,0,1,0 %; ! Clone operation macro PXB$V_FILL_2 = 0,1,1,0 %; ! Delegate operation macro PXB$V_FILL_3 = 0,2,1,0 %; macro PXB$V_FILL_4 = 0,3,1,0 %; macro PXB$V_FILL_5 = 0,4,1,0 %; macro PXB$V_FILL_6 = 0,5,1,0 %; macro PXB$V_FILL_7 = 0,6,1,0 %; macro PXB$V_DEBIT = 0,7,1,0 %; ! DEBIT ! This bit must be in ! synch with PSB flag. ! ! CREATE_FLAGS - Flags used for calls to CREATE_EXTENSION. ! literal PXB$M_PRIMARY_EXTENSION = %X'1'; literal PXB$S_CREATE_FLAGS = 4; ! flags macro PXB$V_PRIMARY_EXTENSION = 0,0,1,0 %; ! Clone operation ! ! define the offset and size for user session key and lm session key ! literal TOKEN$K_USERSESSIONKEY_OFFSET = 120; ! user session key offset literal TOKEN$K_USERSESSIONKEY_SIZE = 16; ! user session key size literal TOKEN$K_LMSESSIONKEY_OFFSET = 136; ! LM session key offset literal TOKEN$K_LMSESSIONKEY_SIZE = 8; ! LM session key offset !*** MODULE $PXDSRRDEF IDENT X-8 *** literal psx$_psx$spare_vms_1 = 0; literal psx$_psx$set_masks = 1; literal psx$_psx$same_session = 2; literal psx$_psx$vip_astexit_chmk = 3; literal psx$_psx$check_cpulim = 4; literal psx$_psx$get_cpulim = 5; literal psx$_psx$rdc_cpulim = 6; literal psx$_psx$alloc_p1_pages = 7; literal psx$_psx$time_mode = 8; literal psx$_psx$make_callbacks = 9; literal psx$_psx$system_callback_list = 10; literal psx$_psx$fork_check = 11; literal psx$_psx$callback_service = 12; literal psx$_psx$sendsegv = 13; literal psx$_psx$check_new_pid = 14; literal psx$_psx$spare_vms_16 = 15; literal psx$_psx$spare_vms_17 = 16; literal psx$_psx$spare_vms_18 = 17; literal psx$_psx$spare_vms_19 = 18; literal psx$_psx$spare_vms_20 = 19; literal psx$_psx$spare_vms_21 = 20; literal psx$_psx$spare_vms_22 = 21; literal psx$_psx$spare_vms_23 = 22; literal psx$_psx$spare_vms_24 = 23; literal psx$_psx$spare_vms_25 = 24; literal psx$_psx$spare_vms_26 = 25; literal psx$_psx$spare_vms_27 = 26; literal psx$_psx$spare_vms_28 = 27; literal psx$_psx$spare_vms_29 = 28; literal psx$_psx$spare_vms_30 = 29; literal psx$_psx$spare_vms_31 = 30; literal psx$_psx$spare_vms_32 = 31; literal psx$_psx$spare_vms_33 = 32; literal psx$_psx$spare_vms_34 = 33; literal psx$_psx$spare_vms_35 = 34; literal psx$_psx$spare_vms_36 = 35; literal psx$_psx$spare_vms_37 = 36; literal psx$_psx$spare_vms_38 = 37; literal psx$_psx$spare_vms_39 = 38; literal psx$_psx$spare_vms_40 = 39; literal psx$_psx$send_signal = 40; literal psx$_psx$send_signal_to_group = 41; literal psx$_psx$send_signal_to_session = 42; literal psx$_psx$rundown = 43; literal psx$_psx$rundown_exec = 44; literal psx$_psx$ga_cfs_base = 45; literal psx$_psx$gl_next_rndwn = 46; literal psx$_psx$gl_next_rndwn_exec = 47; literal psx$_psx$ga_spg_table = 48; literal psx$_psx$gl_spg_size = 49; literal psx$_psx$gl_spg_hash = 50; literal psx$_psx$gl_max_fork_in_prg = 51; literal psx$_psx$gl_max_fork_perproc = 52; literal psx$_psx$gl_max_sess_perproc = 53; literal psx$_psx$gl_exec_arg_size = 54; literal psx$_psx$gl_fs_buff_size = 55; literal psx$_psx$gl_fork_in_prg = 56; literal psx$_psx$gl_def_process_flags = 57; literal psx$_psx$lookup_spg_table = 58; literal psx$_psx$ga_default_termios = 59; literal psx$_psx$gl_max_sems_perprc = 60; literal psx$_psx$gl_max_sems_persys = 61; literal psx$_psx$spare_15 = 62; literal psx$_psx$spare_16 = 63; literal psx$_psx$spare_17 = 64; literal psx$_psx$spare_18 = 65; literal psx$_psx$spare_19 = 66; literal psx$_psx$spare_20 = 67; literal psx$_psx$spare_21 = 68; literal psx$_psx$spare_22 = 69; literal psx$_psx$spare_23 = 70; literal psx$_psx$spare_24 = 71; literal psx$_psx$spare_25 = 72; literal psx$_psx$spare_26 = 73; literal psx$_psx$spare_27 = 74; literal psx$_psx$spare_28 = 75; literal psx$_psx$spare_29 = 76; literal psx$_sub_total_number = 77; literal PXDSRR$K_LENGTH = 308; literal PXDSRR$C_LENGTH = 308; literal PXDSRR$S_PXDSRR = 308; macro PXDSRR$L_GLOBAL_CELLS = 0,0,0,0 %; literal PXDSRR$S_GLOBAL_CELLS = 308; literal PSXFRK$K_LENGTH = 248; ! LENGTH OF FORK CONTEXT BLOCK literal PSXFRK$C_LENGTH = 248; ! LENGTH OF FORK CONTEXT BLOCK literal PSXFRK$S_PSXFRK = 248; macro PSXFRK$Q_R2 = 0,0,0,1 %; literal PSXFRK$S_R2 = 8; ! R2 macro PSXFRK$Q_R3 = 8,0,0,1 %; literal PSXFRK$S_R3 = 8; ! R3 macro PSXFRK$Q_R4 = 16,0,0,1 %; literal PSXFRK$S_R4 = 8; ! R4 macro PSXFRK$Q_R5 = 24,0,0,1 %; literal PSXFRK$S_R5 = 8; ! R5 macro PSXFRK$Q_R6 = 32,0,0,1 %; literal PSXFRK$S_R6 = 8; ! R6 macro PSXFRK$Q_R7 = 40,0,0,1 %; literal PSXFRK$S_R7 = 8; ! R7 macro PSXFRK$Q_R8 = 48,0,0,1 %; literal PSXFRK$S_R8 = 8; ! R8 macro PSXFRK$Q_R9 = 56,0,0,1 %; literal PSXFRK$S_R9 = 8; ! R9 macro PSXFRK$Q_R10 = 64,0,0,1 %; literal PSXFRK$S_R10 = 8; ! R10 macro PSXFRK$Q_R11 = 72,0,0,1 %; literal PSXFRK$S_R11 = 8; ! R11 macro PSXFRK$Q_R12 = 80,0,0,1 %; literal PSXFRK$S_R12 = 8; ! R12 macro PSXFRK$Q_R13 = 88,0,0,1 %; literal PSXFRK$S_R13 = 8; ! R13 macro PSXFRK$Q_R14 = 96,0,0,1 %; literal PSXFRK$S_R14 = 8; ! R14 macro PSXFRK$Q_R15 = 104,0,0,1 %; literal PSXFRK$S_R15 = 8; ! R15 macro PSXFRK$Q_FP = 112,0,0,1 %; literal PSXFRK$S_FP = 8; ! FP macro PSXFRK$Q_RA = 120,0,0,1 %; literal PSXFRK$S_RA = 8; ! RA macro PSXFRK$Q_ESP = 128,0,0,1 %; literal PSXFRK$S_ESP = 8; ! ESP macro PSXFRK$Q_SSP = 136,0,0,1 %; literal PSXFRK$S_SSP = 8; ! SSP macro PSXFRK$Q_USP = 144,0,0,1 %; literal PSXFRK$S_USP = 8; ! USP macro PSXFRK$Q_UNQ = 152,0,0,1 %; literal PSXFRK$S_UNQ = 8; ! PROCESS UNQ macro PSXFRK$Q_ASTEN = 160,0,0,1 %; literal PSXFRK$S_ASTEN = 8; ! ASTEN macro PSXFRK$Q_FEN_DATFX = 168,0,0,1 %; literal PSXFRK$S_FEN_DATFX = 8; ! FEN & DATFX macro PSXFRK$Q_F2 = 176,0,0,1 %; literal PSXFRK$S_F2 = 8; ! F2 macro PSXFRK$Q_F3 = 184,0,0,1 %; literal PSXFRK$S_F3 = 8; ! F3 macro PSXFRK$Q_F4 = 192,0,0,1 %; literal PSXFRK$S_F4 = 8; ! F4 macro PSXFRK$Q_F5 = 200,0,0,1 %; literal PSXFRK$S_F5 = 8; ! F5 macro PSXFRK$Q_F6 = 208,0,0,1 %; literal PSXFRK$S_F6 = 8; ! F6 macro PSXFRK$Q_F7 = 216,0,0,1 %; literal PSXFRK$S_F7 = 8; ! F7 macro PSXFRK$Q_F8 = 224,0,0,1 %; literal PSXFRK$S_F8 = 8; ! F8 macro PSXFRK$Q_F9 = 232,0,0,1 %; literal PSXFRK$S_F9 = 8; ! F9 macro PSXFRK$Q_FPCR = 240,0,0,1 %; literal PSXFRK$S_FPCR = 8; ! FPCR !*** MODULE $PYXISDEF *** literal PYXIS$L_NODE_PA_H = 135; ! High order word literal PYXIS$L_PYXIS_CONTROL_L = 1073741824; literal PYXIS$L_PYXIS_ERROR_L = 1073774592; literal PYXIS$L_PYXIS_MEMORY_L = 1342177280; literal PYXIS$L_PYXIS_PCI_ADDR_L = 1610612736; literal PYXIS$L_PYXIS_CLOCK_RESET_L = -2147483648; literal PYXIS$L_PYXIS_SERVER_MGMT_L = -1879048192; literal PYXIS$L_PYXIS_INTERRUPT_L = -1610612736; literal PYXIS$L_CUSCO_L = -1072693248; literal PYXIS$K_PCI_REV = 128; ! PCI revision literal PYXIS$K_PCI_LAT = 192; ! PCI Latency literal PYXIS$K_PYXIS_CTRL = 256; ! PYXIS COntrol literal PYXIS$K_PYXIS_CTRL1 = 320; ! PYXIS COntrol literal PYXIS$K_PYXIS_FLASH_CTRL = 512; ! Flash COntrol literal PYXIS$K_HAE_MEM = 1024; ! HAE memory literal PYXIS$K_HAE_IO = 1088; ! HAE I/O literal PYXIS$K_HAE_CFG = 1152; ! COnfig literal PYXIS$K_PYXIS_DIAG = 8192; ! Diag control literal PYXIS$K_PYXIS_CHECK = 12288; ! Diag check literal PYXIS$K_PERF_MON = 16384; ! Perf monitor literal PYXIS$K_PERF_CNTR = 16448; ! Perf control literal PYXIS$K_PYXIS_ERR_REG = 512; ! PYXIS status literal PYXIS$K_PYXIS_STAT = 576; ! PYXIS status literal PYXIS$K_PYXIS_ERR_MSK = 640; ! PYXIS err mask literal PYXIS$K_PYXIS_SYN = 768; ! PYXIS syndrome literal PYXIS$K_PYXIS_ERR_DATA = 776; ! PYXIS error data literal PYXIS$K_CPU_MEAR = 1024; ! Mem Error Address literal PYXIS$K_CPU_MESR = 1088; ! Mem Error Status literal PYXIS$K_PCI_ERR0 = 2048; ! PCI Err 0 literal PYXIS$K_PCI_ERR1 = 2112; ! PCI Err 1 literal PYXIS$K_PCI_ERR2 = 2176; ! PCI Err 1 literal PYXIS$K_MEM_CONTROL = 0; ! Memory config literal PYXIS$K_MEM_CLOCK_MASK = 64; literal PYXIS$K_MEM_GTR = 512; literal PYXIS$K_MEM_RTR = 768; literal PYXIS$K_MEM_RHPR = 1024; literal PYXIS$K_MEM_MDR1 = 1280; literal PYXIS$K_MEM_MDR2 = 1344; literal PYXIS$K_MEM_BA0 = 1536; ! Mem base addr0 literal PYXIS$K_MEM_BA1 = 1600; ! Mem base addr2 literal PYXIS$K_MEM_BA2 = 1664; ! Mem base addr4 literal PYXIS$K_MEM_BA3 = 1728; ! Mem base addr6 literal PYXIS$K_MEM_BA4 = 1792; ! Mem base addr8 literal PYXIS$K_MEM_BA5 = 1856; ! Mem base addrA literal PYXIS$K_MEM_BA6 = 1920; ! Mem base addrC literal PYXIS$K_MEM_BA7 = 1984; ! Mem base addrE literal PYXIS$K_MEM_BC0 = 2048; ! Mem base contr0 literal PYXIS$K_MEM_BC1 = 2112; ! Mem base contr2 literal PYXIS$K_MEM_BC2 = 2176; ! Mem base contr4 literal PYXIS$K_MEM_BC3 = 2240; ! Mem base contr6 literal PYXIS$K_MEM_BC4 = 2304; ! Mem base contr8 literal PYXIS$K_MEM_BC5 = 2368; ! Mem base contrA literal PYXIS$K_MEM_BC6 = 2432; ! Mem base contrC literal PYXIS$K_MEM_BC7 = 2496; ! Mem base contrE literal PYXIS$K_MEM_BTR0 = 2560; ! Mem base timing0 literal PYXIS$K_MEM_BTR1 = 2624; ! Mem base timing2 literal PYXIS$K_MEM_BTR2 = 2688; ! Mem base timing4 literal PYXIS$K_MEM_BTR3 = 2752; ! Mem base timing6 literal PYXIS$K_MEM_BTR4 = 2816; ! Mem base timing8 literal PYXIS$K_MEM_BTR5 = 2880; ! Mem base timingA literal PYXIS$K_MEM_BTR6 = 2944; ! Mem base timingC literal PYXIS$K_MEM_BTR7 = 3008; ! Mem base timingE literal PYXIS$K_MEM_CVM = 3072; ! cache valid mask literal PYXIS$K_MEM_TBIA = 3072; ! cache valid mask literal PYXIS$K_MEM_TMG0 = 2816; ! Mem timing 0 literal PYXIS$K_MEM_TMG1 = 2880; ! Mem timing 1 literal PYXIS$K_MEM_TMG2 = 2944; ! Mem timing 2 literal PYXIS$K_PCI_TBIA = 256; ! SG TB inval literal PYXIS$K_PCI_W0_BASE = 1024; ! Window base0 literal PYXIS$K_PCI_W0_MASK = 1088; ! Window mask0 literal PYXIS$K_PCI_T0_BASE = 1152; ! Trans base0 literal PYXIS$K_PCI_W1_BASE = 1280; ! Window base1 literal PYXIS$K_PCI_W1_MASK = 1344; ! Window mask1 literal PYXIS$K_PCI_T1_BASE = 1408; ! Trans base1 literal PYXIS$K_PCI_W2_BASE = 1536; ! Window base2 literal PYXIS$K_PCI_W2_MASK = 1600; ! Window mask2 literal PYXIS$K_PCI_T2_BASE = 1664; ! Trans base2 literal PYXIS$K_PCI_W3_BASE = 1792; ! Window base3 literal PYXIS$K_PCI_W3_MASK = 1856; ! Window mask3 literal PYXIS$K_PCI_T3_BASE = 1920; ! Trans base3 literal PYXIS$K_PCI_DAC_BASE = 1984; ! DAC Base literal PYXIS$K_PCI_LTB_TAG0 = 2048; ! Lock TB tag0 literal PYXIS$K_PCI_LTB_TAG1 = 2112; ! Lock TB tag1 literal PYXIS$K_PCI_LTB_TAG2 = 2176; ! Lock TB tag2 literal PYXIS$K_PCI_LTB_TAG3 = 2240; ! Lock TB tag3 literal PYXIS$K_PCI_TB_TAG0 = 2304; ! TB tag0 literal PYXIS$K_PCI_TB_TAG1 = 2368; ! TB tag1 literal PYXIS$K_PCI_TB_TAG2 = 2432; ! TB tag2 literal PYXIS$K_PCI_TB_TAG3 = 2496; ! TB tag3 literal PYXIS$K_PCI_TB0_PAGE0 = 4096; ! TB0 page0 literal PYXIS$K_PCI_TB0_PAGE1 = 4160; ! TB0 page1 literal PYXIS$K_PCI_TB0_PAGE2 = 4224; ! TB0 page2 literal PYXIS$K_PCI_TB0_PAGE3 = 4288; ! TB0 page3 literal PYXIS$K_PCI_TB1_PAGE0 = 4352; ! TB1 page0 literal PYXIS$K_PCI_TB1_PAGE1 = 4416; ! TB1 page1 literal PYXIS$K_PCI_TB1_PAGE2 = 4480; ! TB1 page2 literal PYXIS$K_PCI_TB1_PAGE3 = 4544; ! TB1 page3 literal PYXIS$K_PCI_TB2_PAGE0 = 4608; ! TB2 page0 literal PYXIS$K_PCI_TB2_PAGE1 = 4672; ! TB2 page1 literal PYXIS$K_PCI_TB2_PAGE2 = 4736; ! TB2 page2 literal PYXIS$K_PCI_TB2_PAGE3 = 4800; ! TB2 page3 literal PYXIS$K_PCI_TB3_PAGE0 = 4864; ! TB3 page0 literal PYXIS$K_PCI_TB3_PAGE1 = 4928; ! TB3 page1 literal PYXIS$K_PCI_TB3_PAGE2 = 4992; ! TB3 page2 literal PYXIS$K_PCI_TB3_PAGE3 = 5056; ! TB3 page3 literal PYXIS$K_PCI_TB4_PAGE0 = 5120; ! TB4 page0 literal PYXIS$K_PCI_TB4_PAGE1 = 5184; ! TB4 page1 literal PYXIS$K_PCI_TB4_PAGE2 = 5248; ! TB4 page2 literal PYXIS$K_PCI_TB4_PAGE3 = 5312; ! TB4 page3 literal PYXIS$K_PCI_TB5_PAGE0 = 5376; ! TB5 page0 literal PYXIS$K_PCI_TB5_PAGE1 = 5440; ! TB5 page1 literal PYXIS$K_PCI_TB5_PAGE2 = 5504; ! TB5 page2 literal PYXIS$K_PCI_TB5_PAGE3 = 5568; ! TB5 page3 literal PYXIS$K_PCI_TB6_PAGE0 = 5632; ! TB6 page0 literal PYXIS$K_PCI_TB6_PAGE1 = 5696; ! TB6 page1 literal PYXIS$K_PCI_TB6_PAGE2 = 5760; ! TB6 page2 literal PYXIS$K_PCI_TB6_PAGE3 = 5824; ! TB6 page3 literal PYXIS$K_PCI_TB7_PAGE0 = 5888; ! TB7 page0 literal PYXIS$K_PCI_TB7_PAGE1 = 5952; ! TB7 page1 literal PYXIS$K_PCI_TB7_PAGE2 = 6016; ! TB7 page2 literal PYXIS$K_PCI_TB7_PAGE3 = 6080; ! TB7 page3 literal PYXIS$K_CLOCK_CONFIG = 0; literal PYXIS$K_RESET = 2304; literal PYXIS$K_FAN_ACCUM = 0; literal PYXIS$K_FAN_CTL = 64; literal PYXIS$K_FAN_THRESH = 128; literal PYXIS$K_POWER_CTL = 192; literal PYXIS$K_PWRDWN_TIM = 256; literal PYXIS$K_POWER_STATE = 320; literal PYXIS$K_INT_REQ = 0; literal PYXIS$K_INT_MASK = 64; literal PYXIS$K_INT_HILO = 192; literal PYXIS$K_INT_ROUTE = 320; literal PYXIS$K_GPO = 384; literal PYXIS$K_INT_CNFG = 448; literal PYXIS$K_RT_COUNT = 512; literal PYXIS$K_INT_TIME = 576; literal PYXIS$K_IIC_CTRL = 704; literal PYXIS$K_CLOCK_1286 = 64; literal PYXIS$K_COMMAND_1286 = 75; literal PYXIS$K_WDOG_1286 = 76; literal PYXIS$K_VDIVR = 128; literal PYXIS$K_V1ISR = 129; literal PYXIS$K_V2ISR = 130; literal PYXIS$K_V3ISR = 131; literal PYXIS$K_VDIER = 132; literal PYXIS$K_V1IER = 133; literal PYXIS$K_V2IER = 134; literal PYXIS$K_V3IER = 135; literal PYXIS$K_VMCSR = 136; literal PYXIS$K_VACSR = 138; literal PYXIS$K_BIDR = 139; literal PYXIS$K_VSICSR0 = 160; literal PYXIS$K_VSICSR1 = 161; literal PYXIS$K_VSICSR2 = 162; literal PYXIS$K_VSICSR3 = 163; literal PYXIS$K_VSICSR4 = 164; literal PYXIS$K_VSICSR5 = 165; literal PYXIS$K_VSICSR6 = 166; literal PYXIS$K_VSICSR9 = 169; literal PYXIS$K_VSICSRA = 170; literal PYXIS$K_VSICSRB = 171; literal PYXIS$K_VSICSRC = 172; literal PYXIS$K_VSICSR11 = 177; literal PYXIS$K_VSICSR12 = 178; literal PYXIS$K_VSICSR13 = 179; literal PYXIS$K_VSICSR14 = 180; literal PYXIS$K_VSICSR15 = 181; literal PYXIS$K_VSICSR16 = 182; literal PYXIS$K_VSICSR17 = 183; literal PYXIS$M_PYXIS_CTRL_PCI_EN = %X'1'; literal PYXIS$M_PYXIS_CTRL_PCI_LOCK_EN = %X'2'; literal PYXIS$M_PYXIS_CTRL_PCI_LOOP_EN = %X'4'; literal PYXIS$M_PYXIS_CTRL_FST_BB_EN = %X'8'; literal PYXIS$M_PYXIS_CTRL_MST_EN = %X'10'; literal PYXIS$M_PYXIS_CTRL_MEM_EN = %X'20'; literal PYXIS$M_PYXIS_CTRL_REQ64_EN = %X'40'; literal PYXIS$M_PYXIS_CTRL_ACK64_EN = %X'80'; literal PYXIS$M_PYXIS_CTRL_ADDR_PE_EN = %X'100'; literal PYXIS$M_PYXIS_CTRL_PERR_EN = %X'200'; literal PYXIS$M_PYXIS_CTRL_FILL_ERR_EN = %X'400'; literal PYXIS$M_PYXIS_CTRL_ECC_CHK_EN = %X'1000'; literal PYXIS$M_PYXIS_CTRL_CACK_EN_PE = %X'2000'; literal PYXIS$M_PYXIS_CTRL_CON_IDLE_BC = %X'4000'; literal PYXIS$M_PYXIS_CTRL_CSR_IOA_BYP = %X'8000'; literal PYXIS$M_PYXIS_CTRL_IO_FLUSH_REQ = %X'10000'; literal PYXIS$M_PYXIS_CTRL_CPU_FLUSH_REQ = %X'20000'; literal PYXIS$M_PYXIS_CTRL_ARB_EV5_EN = %X'40000'; literal PYXIS$M_PYXIS_CTRL_EN_ARB_LINK = %X'80000'; literal PYXIS$M_PYXIS_CTRL_RD_TYP = %X'300000'; literal PYXIS$M_PYXIS_CTRL_RL_TYP = %X'3000000'; literal PYXIS$M_PYXIS_CTRL_RM_TYP = %X'30000000'; literal PYXIS$M_PYXIS_CTRL1_IOA_BEN = %X'1'; literal PYXIS$M_PYXIS_CTRL1_PCI_MWIN_ENA = %X'10'; literal PYXIS$M_PYXIS_CTRL1_PCI_LINK_ENA = %X'100'; literal PYXIS$M_PYXIS_CTRL1_LW_PAR_MODE = %X'1000'; literal PYXIS$M_PYXIS_CNFG_PCI_WIDTH = %X'100'; literal PYXIS$M_PYXIS_CNFG_IOD_WIDTH = %X'10000'; literal PYXIS$M_HAE_MEM_REG_3 = %X'FC'; literal PYXIS$M_HAE_MEM_REG_2 = %X'F800'; literal PYXIS$M_HAE_MEM_REG_1 = %X'E0000000'; literal PYXIS$M_HAE_IO = %X'FE000000'; literal PYXIS$M_FROM_EN = %X'1'; literal PYXIS$M_USE_CHECK = %X'2'; literal PYXIS$M_FPE_PCI = %X'30000000'; literal PYXIS$M_FPE_TO_EV5 = %X'80000000'; literal PYXIS$M_ERR_CORR_ECC = %X'1'; literal PYXIS$M_ERR_UNC_ECC = %X'2'; literal PYXIS$M_ERR_CPU_PE = %X'4'; literal PYXIS$M_ERR_MEM_NEM = %X'8'; literal PYXIS$M_ERR_PCI_SERR = %X'10'; literal PYXIS$M_ERR_PCI_PERR = %X'20'; literal PYXIS$M_ERR_PCI_ADR_PE = %X'40'; literal PYXIS$M_ERR_M_ABORT = %X'80'; literal PYXIS$M_ERR_T_ABORT = %X'100'; literal PYXIS$M_ERR_PA_PTE_INV = %X'200'; literal PYXIS$M_ERR_IOA_TIMEOUT = %X'800'; literal PYXIS$M_ERR_LOST_CORR_ECC = %X'10000'; literal PYXIS$M_ERR_LOST_UNC_ECC = %X'20000'; literal PYXIS$M_ERR_LOST_CPU_PE = %X'40000'; literal PYXIS$M_ERR_LOST_MEM_NEM = %X'80000'; literal PYXIS$M_ERR_LOST_PCI_PERR = %X'200000'; literal PYXIS$M_ERR_LOST_PCI_ADR_PE = %X'400000'; literal PYXIS$M_ERR_LOST_M_ABORT = %X'800000'; literal PYXIS$M_ERR_LOST_T_ABORT = %X'1000000'; literal PYXIS$M_ERR_LOST_PA_PTE_INV = %X'2000000'; literal PYXIS$M_ERR_LOST_IOA_TIMEOUT = %X'8000000'; literal PYXIS$M_ERR_VALID = %X'80000000'; literal PYXIS$M_STAT_PCI_0 = %X'1'; literal PYXIS$M_STAT_PCI_1 = %X'2'; literal PYXIS$M_STAT_IOA_VALID = %X'F0'; literal PYXIS$M_STAT_TLB_MISS = %X'800'; literal PYXIS$M_MASK_CORR_ECC_ERR = %X'1'; literal PYXIS$M_MASK_UNC_ECC_ERR = %X'2'; literal PYXIS$M_MASK_CPU_PE = %X'4'; literal PYXIS$M_MASK_MEM_NEM = %X'8'; literal PYXIS$M_MASK_PCI_SERR = %X'10'; literal PYXIS$M_MASK_PCI_PERR = %X'20'; literal PYXIS$M_MASK_PCI_ADR_PE = %X'40'; literal PYXIS$M_MASK_M_ABORT = %X'80'; literal PYXIS$M_MASK_T_ABORT = %X'100'; literal PYXIS$M_MASK_PA_PTE_INV = %X'200'; literal PYXIS$M_MASK_IOA_TIMEOUT = %X'800'; literal PYXIS$M_PYXIS_SYNDROME0 = %X'FF'; literal PYXIS$M_PYXIS_SYNDROME1 = %X'FF00'; literal PYXIS$M_PYXIS_RAW_CHECK_BITS = %X'FF0000'; literal PYXIS$M_PYXIS_SYND_CE0 = %X'1000000'; literal PYXIS$M_PYXIS_SYND_CE1 = %X'2000000'; literal PYXIS$M_PYXIS_SYND_UCE0 = %X'4000000'; literal PYXIS$M_PYXIS_SYND_UCE1 = %X'8000000'; literal PYXIS$M_MEAR_ADDR_H = %X'FFFFFFF0'; literal PYXIS$M_MESR_ADDR_3932 = %X'FF'; literal PYXIS$M_MESR_DMA_RD_NXM = %X'100'; literal PYXIS$M_MESR_DMA_WR_NXM = %X'200'; literal PYXIS$M_MESR_CPU_RD_NXM = %X'400'; literal PYXIS$M_MESR_CPU_WR_NXM = %X'800'; literal PYXIS$M_MESR_IO_RD_NXM = %X'1000'; literal PYXIS$M_MESR_IO_WR_NXM = %X'2000'; literal PYXIS$M_MESR_VICTIM_NXM = %X'4000'; literal PYXIS$M_MESR_TLBFILL_NXM = %X'8000'; literal PYXIS$M_MESR_OWORD_INDEX = %X'30000'; literal PYXIS$M_MESR_DATA_CYCLE_TYP = %X'1F00000'; literal PYXIS$M_MESR_SEQ_ST = %X'FE000000'; literal PYXIS$M_PCIE_DMA_CMD = %X'F'; literal PYXIS$M_PCIE_DMA_DAC = %X'20'; literal PYXIS$M_PCIE_WINDOW = %X'F00'; literal PYXIS$M_PCIE_MSTR_STATE = %X'F0000'; literal PYXIS$M_PCIE_TRGT_STATE = %X'F00000'; literal PYXIS$M_PCIE_PCI_CMD = %X'F000000'; literal PYXIS$M_PCIE_PCI_DAC = %X'10000000'; literal PYXIS$M_MCR_MODE_REQ = %X'1'; literal PYXIS$M_MCR_SERVER_MODE = %X'100'; literal PYXIS$M_MCR_BCACHE_STAT = %X'200'; literal PYXIS$M_MCR_BCACHE_EN = %X'400'; literal PYXIS$M_MCR_PIPELINED_CACHE = %X'800'; literal PYXIS$M_MCR_OVERLAP_DIS = %X'1000'; literal PYXIS$M_MCR_SEQ_TRACE = %X'2000'; literal PYXIS$M_MCR_CKE_AUTO = %X'4000'; literal PYXIS$M_MCR_DRAM_CLK_AUTO = %X'8000'; literal PYXIS$M_MCR_DRAM_MODE = %X'3FFF0000'; literal PYXIS$M_MCMR_DRAM_CLOCK_MASK = %X'FFFF'; literal PYXIS$M_MGTR_MIN_RAS_PRE = %X'7'; literal PYXIS$M_MGTR_CAS_LAT = %X'30'; literal PYXIS$M_MGTR_IDLE_BC_WIDTH = %X'700'; literal PYXIS$M_MRTR_REF_WIDTH = %X'70'; literal PYXIS$M_MRTR_REF_INT = %X'1F80'; literal PYXIS$M_MRTR_FORCE_REF = %X'8000'; literal PYXIS$M_MRPHR_POLICY_MASK = %X'FFFF'; literal PYXIS$M_MDR1_SEL0 = %X'3F'; literal PYXIS$M_MDR1_SEL1 = %X'3F00'; literal PYXIS$M_MDR1_SEL2 = %X'3F0000'; literal PYXIS$M_MDR1_SEL3 = %X'3F000000'; literal PYXIS$M_MDR1_ENABLE = %X'80000000'; literal PYXIS$M_MDR2_SEL0 = %X'3F'; literal PYXIS$M_MDR2_SEL1 = %X'3F00'; literal PYXIS$M_MDR2_SEL2 = %X'3F0000'; literal PYXIS$M_MDR2_SEL3 = %X'3F000000'; literal PYXIS$M_MDR2_ENABLE = %X'80000000'; literal PYXIS$M_BBAR0_BASE_ADDR_3324 = %X'FFC0'; literal PYXIS$M_BBAR1_BASE_ADDR_3324 = %X'FFC0'; literal PYXIS$M_BBAR2_BASE_ADDR_3324 = %X'FFC0'; literal PYXIS$M_BBAR3_BASE_ADDR_3324 = %X'FFC0'; literal PYXIS$M_BBAR4_BASE_ADDR_3324 = %X'FFC0'; literal PYXIS$M_BBAR5_BASE_ADDR_3324 = %X'FFC0'; literal PYXIS$M_BBAR6_BASE_ADDR_3324 = %X'FFC0'; literal PYXIS$M_BBAR7_BASE_ADDR_3324 = %X'FFC0'; literal PYXIS$M_MBCR0_BANK_ENABLE = %X'1'; literal PYXIS$M_MBCR0_BANK_SIZE = %X'1E'; literal PYXIS$M_MBCR0_SUBBANK_ENABLE = %X'20'; literal PYXIS$M_MBCR0_COLSEL = %X'40'; literal PYXIS$M_MBCR0_4BANK = %X'80'; literal PYXIS$M_MBCR1_BANK_ENABLE = %X'1'; literal PYXIS$M_MBCR1_BANK_SIZE = %X'1E'; literal PYXIS$M_MBCR1_SUBBANK_ENABLE = %X'20'; literal PYXIS$M_MBCR1_COLSEL = %X'40'; literal PYXIS$M_MBCR1_4BANK = %X'80'; literal PYXIS$M_MBCR2_BANK_ENABLE = %X'1'; literal PYXIS$M_MBCR2_BANK_SIZE = %X'1E'; literal PYXIS$M_MBCR2_SUBBANK_ENABLE = %X'20'; literal PYXIS$M_MBCR2_COLSEL = %X'40'; literal PYXIS$M_MBCR2_4BANK = %X'80'; literal PYXIS$M_MBCR3_BANK_ENABLE = %X'1'; literal PYXIS$M_MBCR3_BANK_SIZE = %X'1E'; literal PYXIS$M_MBCR3_SUBBANK_ENABLE = %X'20'; literal PYXIS$M_MBCR3_COLSEL = %X'40'; literal PYXIS$M_MBCR3_4BANK = %X'80'; literal PYXIS$M_MBCR4_BANK_ENABLE = %X'1'; literal PYXIS$M_MBCR4_BANK_SIZE = %X'1E'; literal PYXIS$M_MBCR4_SUBBANK_ENABLE = %X'20'; literal PYXIS$M_MBCR4_COLSEL = %X'40'; literal PYXIS$M_MBCR4_4BANK = %X'80'; literal PYXIS$M_MBCR5_BANK_ENABLE = %X'1'; literal PYXIS$M_MBCR5_BANK_SIZE = %X'1E'; literal PYXIS$M_MBCR5_SUBBANK_ENABLE = %X'20'; literal PYXIS$M_MBCR5_COLSEL = %X'40'; literal PYXIS$M_MBCR5_4BANK = %X'80'; literal PYXIS$M_MBCR6_BANK_ENABLE = %X'1'; literal PYXIS$M_MBCR6_BANK_SIZE = %X'1E'; literal PYXIS$M_MBCR6_SUBBANK_ENABLE = %X'20'; literal PYXIS$M_MBCR6_COLSEL = %X'40'; literal PYXIS$M_MBCR6_4BANK = %X'80'; literal PYXIS$M_MBCR7_BANK_ENABLE = %X'1'; literal PYXIS$M_MBCR7_BANK_SIZE = %X'1E'; literal PYXIS$M_MBCR7_SUBBANK_ENABLE = %X'20'; literal PYXIS$M_MBCR7_COLSEL = %X'40'; literal PYXIS$M_MBCR7_4BANK = %X'80'; literal PYXIS$M_MBTR0_ROW_ADDR_HOLD = %X'7'; literal PYXIS$M_MBTR0_TOSHIBA = %X'10'; literal PYXIS$M_MBTR0_SLOW_CHARGE = %X'20'; literal PYXIS$M_MBTR1_ROW_ADDR_HOLD = %X'7'; literal PYXIS$M_MBTR1_TOSHIBA = %X'10'; literal PYXIS$M_MBTR1_SLOW_CHARGE = %X'20'; literal PYXIS$M_MBTR2_ROW_ADDR_HOLD = %X'7'; literal PYXIS$M_MBTR2_TOSHIBA = %X'10'; literal PYXIS$M_MBTR2_SLOW_CHARGE = %X'20'; literal PYXIS$M_MBTR3_ROW_ADDR_HOLD = %X'7'; literal PYXIS$M_MBTR3_TOSHIBA = %X'10'; literal PYXIS$M_MBTR3_SLOW_CHARGE = %X'20'; literal PYXIS$M_MBTR4_ROW_ADDR_HOLD = %X'7'; literal PYXIS$M_MBTR4_TOSHIBA = %X'10'; literal PYXIS$M_MBTR4_SLOW_CHARGE = %X'20'; literal PYXIS$M_MBTR5_ROW_ADDR_HOLD = %X'7'; literal PYXIS$M_MBTR5_TOSHIBA = %X'10'; literal PYXIS$M_MBTR5_SLOW_CHARGE = %X'20'; literal PYXIS$M_MBTR6_ROW_ADDR_HOLD = %X'7'; literal PYXIS$M_MBTR6_TOSHIBA = %X'10'; literal PYXIS$M_MBTR6_SLOW_CHARGE = %X'20'; literal PYXIS$M_MBTR7_ROW_ADDR_HOLD = %X'7'; literal PYXIS$M_MBTR7_TOSHIBA = %X'10'; literal PYXIS$M_MBTR7_SLOW_CHARGE = %X'20'; literal PYXIS$M_CVM_CACHE_VALID_MASK = %X'7FFFFFFF'; literal PYXIS$M_TBIA_CSR_WR_DATA = %X'3'; literal PYXIS$M_WBASE0_W_EN = %X'1'; literal PYXIS$M_WBASE0_SG_EN = %X'2'; literal PYXIS$M_WBASE0_MEMCS_EN = %X'4'; literal PYXIS$M_WBASE0_DAC_EN = %X'8'; literal PYXIS$M_WBASE0_BASE = %X'FFF00000'; literal PYXIS$M_WMASK0_MASK = %X'FFF00000'; literal PYXIS$M_TBASE0_BASE = %X'FFFFFF00'; literal PYXIS$M_WBASE1_W_EN = %X'1'; literal PYXIS$M_WBASE1_SG_EN = %X'2'; literal PYXIS$M_WBASE1_MEMCS_EN = %X'4'; literal PYXIS$M_WBASE1_DAC_EN = %X'8'; literal PYXIS$M_WBASE1_BASE = %X'FFF00000'; literal PYXIS$M_WMASK1_MASK = %X'FFF00000'; literal PYXIS$M_TBASE1_BASE = %X'FFFFFF00'; literal PYXIS$M_WBASE2_W_EN = %X'1'; literal PYXIS$M_WBASE2_SG_EN = %X'2'; literal PYXIS$M_WBASE2_MEMCS_EN = %X'4'; literal PYXIS$M_WBASE2_DAC_EN = %X'8'; literal PYXIS$M_WBASE2_BASE = %X'FFF00000'; literal PYXIS$M_WMASK2_MASK = %X'FFF00000'; literal PYXIS$M_TBASE2_BASE = %X'FFFFFF00'; literal PYXIS$M_WBASE3_W_EN = %X'1'; literal PYXIS$M_WBASE3_SG_EN = %X'2'; literal PYXIS$M_WBASE3_MEMCS_EN = %X'4'; literal PYXIS$M_WBASE3_DAC_EN = %X'8'; literal PYXIS$M_WBASE3_BASE = %X'FFF00000'; literal PYXIS$M_WMASK3_MASK = %X'FFF00000'; literal PYXIS$M_TBASE3_BASE = %X'FFFFFF00'; literal PYXIS$M_DAC_BASE = %X'FF'; literal PYXIS$M_LTB0_VALID = %X'1'; literal PYXIS$M_LTB0_LOCKED = %X'2'; literal PYXIS$M_LTB0_DAC = %X'4'; literal PYXIS$M_LTB0_TAG = %X'FFFF8000'; literal PYXIS$M_LTB1_VALID = %X'1'; literal PYXIS$M_LTB1_LOCKED = %X'2'; literal PYXIS$M_LTB1_DAC = %X'4'; literal PYXIS$M_LTB1_TAG = %X'FFFF8000'; literal PYXIS$M_LTB2_VALID = %X'1'; literal PYXIS$M_LTB2_LOCKED = %X'2'; literal PYXIS$M_LTB2_DAC = %X'4'; literal PYXIS$M_LTB2_TAG = %X'FFFF8000'; literal PYXIS$M_LTB3_VALID = %X'1'; literal PYXIS$M_LTB3_LOCKED = %X'2'; literal PYXIS$M_LTB3_DAC = %X'4'; literal PYXIS$M_LTB3_TAG = %X'FFFF8000'; literal PYXIS$M_TB0_VALID = %X'1'; literal PYXIS$M_TB0_DAC = %X'4'; literal PYXIS$M_TB0_TAG = %X'FFFF8000'; literal PYXIS$M_TB1_VALID = %X'1'; literal PYXIS$M_TB1_DAC = %X'4'; literal PYXIS$M_TB1_TAG = %X'FFFF8000'; literal PYXIS$M_TB2_VALID = %X'1'; literal PYXIS$M_TB2_DAC = %X'4'; literal PYXIS$M_TB2_TAG = %X'FFFF8000'; literal PYXIS$M_TB3_VALID = %X'1'; literal PYXIS$M_TB3_DAC = %X'4'; literal PYXIS$M_TB3_TAG = %X'FFFF8000'; literal PYXIS$M_TB0_PAGE0_VALID = %X'1'; literal PYXIS$M_TB0_PAGE0_ADDR = %X'3FFFFE'; literal PYXIS$M_TB0_PAGE1_VALID = %X'1'; literal PYXIS$M_TB0_PAGE1_ADDR = %X'3FFFFE'; literal PYXIS$M_TB0_PAGE2_VALID = %X'1'; literal PYXIS$M_TB0_PAGE2_ADDR = %X'3FFFFE'; literal PYXIS$M_TB0_PAGE3_VALID = %X'1'; literal PYXIS$M_TB0_PAGE3_ADDR = %X'3FFFFE'; literal PYXIS$M_TB1_PAGE0_VALID = %X'1'; literal PYXIS$M_TB1_PAGE0_ADDR = %X'3FFFFE'; literal PYXIS$M_TB1_PAGE1_VALID = %X'1'; literal PYXIS$M_TB1_PAGE1_ADDR = %X'3FFFFE'; literal PYXIS$M_TB1_PAGE2_VALID = %X'1'; literal PYXIS$M_TB1_PAGE2_ADDR = %X'3FFFFE'; literal PYXIS$M_TB1_PAGE3_VALID = %X'1'; literal PYXIS$M_TB1_PAGE3_ADDR = %X'3FFFFE'; literal PYXIS$M_TB2_PAGE0_VALID = %X'1'; literal PYXIS$M_TB2_PAGE0_ADDR = %X'3FFFFE'; literal PYXIS$M_TB2_PAGE1_VALID = %X'1'; literal PYXIS$M_TB2_PAGE1_ADDR = %X'3FFFFE'; literal PYXIS$M_TB2_PAGE2_VALID = %X'1'; literal PYXIS$M_TB2_PAGE2_ADDR = %X'3FFFFE'; literal PYXIS$M_TB2_PAGE3_VALID = %X'1'; literal PYXIS$M_TB2_PAGE3_ADDR = %X'3FFFFE'; literal PYXIS$M_TB3_PAGE0_VALID = %X'1'; literal PYXIS$M_TB3_PAGE0_ADDR = %X'3FFFFE'; literal PYXIS$M_TB3_PAGE1_VALID = %X'1'; literal PYXIS$M_TB3_PAGE1_ADDR = %X'3FFFFE'; literal PYXIS$M_TB3_PAGE2_VALID = %X'1'; literal PYXIS$M_TB3_PAGE2_ADDR = %X'3FFFFE'; literal PYXIS$M_TB3_PAGE3_VALID = %X'1'; literal PYXIS$M_TB3_PAGE3_ADDR = %X'3FFFFE'; literal PYXIS$M_TB4_PAGE0_VALID = %X'1'; literal PYXIS$M_TB4_PAGE0_ADDR = %X'3FFFFE'; literal PYXIS$M_TB4_PAGE1_VALID = %X'1'; literal PYXIS$M_TB4_PAGE1_ADDR = %X'3FFFFE'; literal PYXIS$M_TB4_PAGE2_VALID = %X'1'; literal PYXIS$M_TB4_PAGE2_ADDR = %X'3FFFFE'; literal PYXIS$M_TB4_PAGE3_VALID = %X'1'; literal PYXIS$M_TB4_PAGE3_ADDR = %X'3FFFFE'; literal PYXIS$M_TB5_PAGE0_VALID = %X'1'; literal PYXIS$M_TB5_PAGE0_ADDR = %X'3FFFFE'; literal PYXIS$M_TB5_PAGE1_VALID = %X'1'; literal PYXIS$M_TB5_PAGE1_ADDR = %X'3FFFFE'; literal PYXIS$M_TB5_PAGE2_VALID = %X'1'; literal PYXIS$M_TB5_PAGE2_ADDR = %X'3FFFFE'; literal PYXIS$M_TB5_PAGE3_VALID = %X'1'; literal PYXIS$M_TB5_PAGE3_ADDR = %X'3FFFFE'; literal PYXIS$M_TB6_PAGE0_VALID = %X'1'; literal PYXIS$M_TB6_PAGE0_ADDR = %X'3FFFFE'; literal PYXIS$M_TB6_PAGE1_VALID = %X'1'; literal PYXIS$M_TB6_PAGE1_ADDR = %X'3FFFFE'; literal PYXIS$M_TB6_PAGE2_VALID = %X'1'; literal PYXIS$M_TB6_PAGE2_ADDR = %X'3FFFFE'; literal PYXIS$M_TB6_PAGE3_VALID = %X'1'; literal PYXIS$M_TB6_PAGE3_ADDR = %X'3FFFFE'; literal PYXIS$M_TB7_PAGE0_VALID = %X'1'; literal PYXIS$M_TB7_PAGE0_ADDR = %X'3FFFFE'; literal PYXIS$M_TB7_PAGE1_VALID = %X'1'; literal PYXIS$M_TB7_PAGE1_ADDR = %X'3FFFFE'; literal PYXIS$M_TB7_PAGE2_VALID = %X'1'; literal PYXIS$M_TB7_PAGE2_ADDR = %X'3FFFFE'; literal PYXIS$M_TB7_PAGE3_VALID = %X'1'; literal PYXIS$M_TB7_PAGE3_ADDR = %X'3FFFFE'; literal PYXIS$M_CCR_CLOCK_DIVIDE = %X'3'; literal PYXIS$M_CCR_PCLK_DIVIDE = %X'380'; literal PYXIS$M_CCR_SEL_CFG = %X'800'; literal PYXIS$M_CCR_DCLK_INV = %X'8000'; literal PYXIS$M_CCR_DCLK_FORCE = %X'10000'; literal PYXIS$M_CCR_DCLK_DELAY = %X'FF000000'; literal PYXIS$M_FAR_HEAT = %X'FFFFFF'; literal PYXIS$M_FCR_ON_HEAT = %X'FF'; literal PYXIS$M_FCR_SAMPLE = %X'FF00'; literal PYXIS$M_FCR_OFF_DELAY = %X'FFF0000'; literal PYXIS$M_FCR_FORCE_FAN = %X'10000000'; literal PYXIS$M_FCR_FORCE_FAN_HI = %X'20000000'; literal PYXIS$M_FCR_FAN_ON = %X'40000000'; literal PYXIS$M_FCR_FAN_ON_HI = %X'80000000'; literal PYXIS$M_FTR_FAN_ON = %X'FF'; literal PYXIS$M_FTR_FAN_HI = %X'FF00'; literal PYXIS$M_FTR_FAN_HI_LO = %X'FF0000'; literal PYXIS$M_FTR_FAN_OFF = %X'FF000000'; literal PYXIS$M_PCR_POWER_DOWN = %X'1'; literal PYXIS$M_PCR_ABUS_DIS = %X'10'; literal PYXIS$M_PCR_IINT_DIS = %X'100'; literal PYXIS$M_PCR_DO_RESET = %X'1000'; literal PYXIS$M_PTR_PLL_DELAY = %X'FF'; literal PYXIS$M_PTR_OFF_DELAY = %X'FF00'; literal PYXIS$M_PTR_RESET_PULSE_WIDTH = %X'FF0000'; literal PYXIS$M_PTR_MIN_OFF_TIME = %X'FF000000'; literal PYXIS$M_INT_REQ_31_0 = %X'FFFFFFFF'; literal PYXIS$M_INT_REQ_61_32 = %X'3FFFFFFF00000000'; literal PYXIS$M_INT_REQ_CLK_PEND = %X'4000000000000000'; literal PYXIS$M_INT_REQ_ERR_INT = %X'8000000000000000'; literal PYXIS$M_INT_MASK_31_0 = %X'FFFFFFFF'; literal PYXIS$M_INT_MASK_61_32 = %X'3FFFFFFF00000000'; literal PYXIS$M_INT_HILO_BYTE = %X'FF'; literal PYXIS$M_INT_RTE = %X'7F'; literal PYXIS$M_ICNFG_CLK_DIV = %X'F'; literal PYXIS$M_ICNFG_IRQ_CNT = %X'70'; literal PYXIS$M_ICNFG_IRQ_CFG = %X'7F00'; literal PYXIS$M_ICNFG_DRIVE_IRQ = %X'10000'; literal PYXIS$M_IIC_READ_DATA = %X'1'; literal PYXIS$M_IIC_READ_CLK = %X'2'; literal PYXIS$M_IIC_DATA_EN = %X'4'; literal PYXIS$M_IIC_DATA = %X'8'; literal PYXIS$M_IIC_CLK_EN = %X'10'; literal PYXIS$M_IIC_CLK = %X'20'; literal PYXIS$M_SEC_01 = %X'F'; literal PYXIS$M_SEC_1 = %X'F0'; literal PYXIS$M_SECOND = %X'F'; literal PYXIS$M_SEC_10 = %X'70'; literal PYXIS$M_MINUTE = %X'F'; literal PYXIS$M_MIN_10 = %X'70'; literal PYXIS$M_ALARM_MIN = %X'F'; literal PYXIS$M_ALARM_MIN_10 = %X'70'; literal PYXIS$M_SET_MIN_ALARM = %X'80'; literal PYXIS$M_HOUR = %X'F'; literal PYXIS$M_HOUR_10 = %X'10'; literal PYXIS$M_AP_10HR = %X'20'; literal PYXIS$M_TWELVE = %X'40'; literal PYXIS$M_ALARM_HOUR = %X'F'; literal PYXIS$M_ALARM_HOUR_10 = %X'10'; literal PYXIS$M_ALARM_AP_10HR = %X'20'; literal PYXIS$M_ALARM_TWELVE = %X'40'; literal PYXIS$M_SET_HOUR_ALARM = %X'80'; literal PYXIS$M_DAY = %X'7'; literal PYXIS$M_DAY_ALARM = %X'7'; literal PYXIS$M_DAY_ALARM_MBZ = %X'78'; literal PYXIS$M_SET_DAY_ALARM = %X'80'; literal PYXIS$M_DATE = %X'F'; literal PYXIS$M_DATE_10 = %X'30'; literal PYXIS$M_MONTH = %X'F'; literal PYXIS$M_MONTH_10 = %X'10'; literal PYXIS$M_MONTH_MBZ = %X'20'; literal PYXIS$M_ESQW = %X'40'; literal PYXIS$M_EOSC = %X'80'; literal PYXIS$M_YEAR = %X'F'; literal PYXIS$M_YEAR_10 = %X'F0'; literal PYXIS$M_TDF = %X'1'; literal PYXIS$M_WAF = %X'2'; literal PYXIS$M_TDM = %X'4'; literal PYXIS$M_WAM = %X'8'; literal PYXIS$M_PU_LVL = %X'10'; literal PYXIS$M_IBH_LO = %X'20'; literal PYXIS$M_IPSW = %X'40'; literal PYXIS$M_TE = %X'80'; literal PYXIS$M_WDOG_01_SEC = %X'F'; literal PYXIS$M_WDOG_1_SEC = %X'F0'; literal PYXIS$M_WDOG_SEC = %X'F'; literal PYXIS$M_WDOG_10SEC = %X'F0'; literal PYXIS$S_PYXIS = 87784; ! PYXIS ASIC revision 8740000080 macro PYXIS$L_PCI_PYXIS_REV = 128,0,32,1 %; macro PYXIS$B_PYXIS_REV = 128,0,8,1 %; ! PYXIS revision ! PCI master latency timeout 87400000C0 macro PYXIS$L_PCI_LAT = 192,0,32,1 %; macro PYXIS$B_PCI_LATENCY = 193,0,8,1 %; ! PYXIS revision ! PYXIS Control register 8740000100 macro PYXIS$L_PYXIS_CTL = 256,0,32,1 %; macro PYXIS$V_PYXIS_CTRL_PCI_EN = 256,0,1,0 %; ! PYXIS disable/enable resets to PCI macro PYXIS$V_PYXIS_CTRL_PCI_LOCK_EN = 256,1,1,0 %; ! PYXIS locks from PCI enable macro PYXIS$V_PYXIS_CTRL_PCI_LOOP_EN = 256,2,1,0 %; ! PYXIS loopback enable macro PYXIS$V_PYXIS_CTRL_FST_BB_EN = 256,3,1,0 %; ! PYXIS fast back-to-back enable macro PYXIS$V_PYXIS_CTRL_MST_EN = 256,4,1,0 %; ! PYXIS is a PCI master enable macro PYXIS$V_PYXIS_CTRL_MEM_EN = 256,5,1,0 %; ! PYXIS is a PCI target enable macro PYXIS$V_PYXIS_CTRL_REQ64_EN = 256,6,1,0 %; ! PYXIS will request 64bit PCI txactions macro PYXIS$V_PYXIS_CTRL_ACK64_EN = 256,7,1,0 %; ! PYXIS will accept 64bit PCI txactions macro PYXIS$V_PYXIS_CTRL_ADDR_PE_EN = 256,8,1,0 %; ! PYXIS will check address parity enable macro PYXIS$V_PYXIS_CTRL_PERR_EN = 256,9,1,0 %; ! PYXIS will check PCI data enable macro PYXIS$V_PYXIS_CTRL_FILL_ERR_EN = 256,10,1,0 %; ! PYXIS will assert fill_err enable macro PYXIS$V_PYXIS_CTRL_ECC_CHK_EN = 256,12,1,0 %; ! PYXIS checks IOD data enable macro PYXIS$V_PYXIS_CTRL_CACK_EN_PE = 256,13,1,0 %; ! PYXIS checks c/a parity on CACK macro PYXIS$V_PYXIS_CTRL_CON_IDLE_BC = 256,14,1,0 %; ! PYXIS generated contig. IDLE_BC macro PYXIS$V_PYXIS_CTRL_CSR_IOA_BYP = 256,15,1,0 %; ! PYXIS bypasses I/O addr queue macro PYXIS$V_PYXIS_CTRL_IO_FLUSH_REQ = 256,16,1,0 %; ! Controls response to PCI FLUSH_REQ macro PYXIS$V_PYXIS_CTRL_CPU_FLUSH_REQ = 256,17,1,0 %; ! Controls response to PCI FLUSH_REQ macro PYXIS$V_PYXIS_CTRL_ARB_EV5_EN = 256,18,1,0 %; ! Enable bypass path ev5 to mem/io macro PYXIS$V_PYXIS_CTRL_EN_ARB_LINK = 256,19,1,0 %; macro PYXIS$V_PYXIS_CTRL_RD_TYP = 256,20,2,0 %; literal PYXIS$S_PYXIS_CTRL_RD_TYP = 2; ! Control prefetch algorithm RD macro PYXIS$V_PYXIS_CTRL_RL_TYP = 256,24,2,0 %; literal PYXIS$S_PYXIS_CTRL_RL_TYP = 2; ! Control prefetch algorithm RL macro PYXIS$V_PYXIS_CTRL_RM_TYP = 256,28,2,0 %; literal PYXIS$S_PYXIS_CTRL_RM_TYP = 2; ! Control prefetch algorithm RM ! PYXIS CTRL1 register 8740000140 macro PYXIS$L_PYXIS_CTL1 = 320,0,32,1 %; macro PYXIS$V_PYXIS_CTRL1_IOA_BEN = 320,0,1,0 %; ! PYXIS disable/enable macro PYXIS$V_PYXIS_CTRL1_PCI_MWIN_ENA = 320,4,1,0 %; ! PYXIS disable/enable Monster window macro PYXIS$V_PYXIS_CTRL1_PCI_LINK_ENA = 320,8,1,0 %; ! PYXIS disable/enable macro PYXIS$V_PYXIS_CTRL1_LW_PAR_MODE = 320,12,1,0 %; ! PYXIS ! PYXIS Config => Size information of the two busses 8740000200 macro PYXIS$L_PYXIS_CONFIG = 512,0,32,1 %; macro PYXIS$V_PYXIS_CNFG_PCI_WIDTH = 512,8,1,0 %; ! Bit is set -> 64bit PCI macro PYXIS$V_PYXIS_CNFG_IOD_WIDTH = 512,16,1,0 %; ! Bit is set -> 64bit IOD ! HAE MEM => Extends sparse space addr to full 32 bits 8740000400 macro PYXIS$L_HAE_MEM = 1024,0,32,1 %; macro PYXIS$V_HAE_MEM_REG_3 = 1024,2,6,0 %; literal PYXIS$S_HAE_MEM_REG_3 = 6; ! High order sparse bits macro PYXIS$V_HAE_MEM_REG_2 = 1024,11,5,0 %; literal PYXIS$S_HAE_MEM_REG_2 = 5; ! High order sparse bits macro PYXIS$V_HAE_MEM_REG_1 = 1024,29,3,0 %; literal PYXIS$S_HAE_MEM_REG_1 = 3; ! High order sparse bits ! HAE IO => Extends sparse space addr to full 32 bits 8740000440 macro PYXIS$L_HAE_IO = 1088,0,32,1 %; macro PYXIS$V_HAE_IO = 1088,25,7,0 %; literal PYXIS$S_HAE_IO = 7; ! High order sparse bits ! CFG => Low two address bits during access to PCI COnfig space 8740000480 macro PYXIS$L_CFG = 1152,0,32,1 %; macro PYXIS$V_CFG_BITS = 1152,0,2,0 %; ! Low order bits of config space ref ! PYXIS_DIAG Diagnostic control enable 840002000 macro PYXIS$L_PYXIS_DIAG = 8192,0,32,1 %; macro PYXIS$V_FROM_EN = 8192,0,1,0 %; ! FROM write enable macro PYXIS$V_USE_CHECK = 8192,1,1,0 %; ! USed with DIA_CHECK for ECC testing macro PYXIS$V_FPE_PCI = 8192,28,2,0 %; literal PYXIS$S_FPE_PCI = 2; ! Force bad parity on PCI macro PYXIS$V_FPE_TO_EV5 = 8192,31,1,0 %; ! Force parity error ! DIAG_CHECK Diagnostic used to write a known ECC pattern 840003000 macro PYXIS$L_DIAG_CHECK = 12288,0,32,1 %; macro PYXIS$B_DIAG_CHECK_ECC = 12288,0,8,1 %; ! ECC to be used ! Perf Monitor counts 8740004000 macro PYXIS$L_PERF_MONITOR = 16384,0,32,1 %; ! Perf Monitor control 8740004040 macro PYXIS$L_PERF_CONTROL = 16448,0,32,1 %; ! PYXIS Error register 8740008200 macro PYXIS$L_PYXIS_ERR = 25088,0,32,1 %; macro PYXIS$V_ERR_CORR_ECC = 25088,0,1,0 %; ! [0] macro PYXIS$V_ERR_UNC_ECC = 25088,1,1,0 %; ! [1] macro PYXIS$V_ERR_CPU_PE = 25088,2,1,0 %; ! [2] macro PYXIS$V_ERR_MEM_NEM = 25088,3,1,0 %; ! [3] macro PYXIS$V_ERR_PCI_SERR = 25088,4,1,0 %; ! [4] macro PYXIS$V_ERR_PCI_PERR = 25088,5,1,0 %; ! [5] macro PYXIS$V_ERR_PCI_ADR_PE = 25088,6,1,0 %; ! [6] macro PYXIS$V_ERR_M_ABORT = 25088,7,1,0 %; ! [7] macro PYXIS$V_ERR_T_ABORT = 25088,8,1,0 %; ! [8] macro PYXIS$V_ERR_PA_PTE_INV = 25088,9,1,0 %; ! [9] macro PYXIS$V_ERR_IOA_TIMEOUT = 25088,11,1,0 %; ! [11] macro PYXIS$V_ERR_LOST_CORR_ECC = 25088,16,1,0 %; macro PYXIS$V_ERR_LOST_UNC_ECC = 25088,17,1,0 %; macro PYXIS$V_ERR_LOST_CPU_PE = 25088,18,1,0 %; macro PYXIS$V_ERR_LOST_MEM_NEM = 25088,19,1,0 %; macro PYXIS$V_ERR_LOST_PCI_PERR = 25088,21,1,0 %; macro PYXIS$V_ERR_LOST_PCI_ADR_PE = 25088,22,1,0 %; macro PYXIS$V_ERR_LOST_M_ABORT = 25088,23,1,0 %; macro PYXIS$V_ERR_LOST_T_ABORT = 25088,24,1,0 %; macro PYXIS$V_ERR_LOST_PA_PTE_INV = 25088,25,1,0 %; macro PYXIS$V_ERR_LOST_IOA_TIMEOUT = 25088,27,1,0 %; macro PYXIS$V_ERR_VALID = 25088,31,1,0 %; ! ! PYXIS Error status register - 0x8740008240 ! macro PYXIS$L_PYXIS_STAT = 25152,0,32,1 %; macro PYXIS$V_STAT_PCI_0 = 25152,0,1,0 %; ! [0] macro PYXIS$V_STAT_PCI_1 = 25152,1,1,0 %; ! [1] macro PYXIS$V_STAT_IOA_VALID = 25152,4,4,0 %; literal PYXIS$S_STAT_IOA_VALID = 4; ! [7:4] macro PYXIS$V_STAT_TLB_MISS = 25152,11,1,0 %; ! [11] ! ! ! PYXIS Error mask register - 0x8740008280 ! macro PYXIS$L_PYXIS_ERROR_MASK = 25216,0,32,1 %; macro PYXIS$V_MASK_CORR_ECC_ERR = 25216,0,1,0 %; ! [0] macro PYXIS$V_MASK_UNC_ECC_ERR = 25216,1,1,0 %; ! [1] macro PYXIS$V_MASK_CPU_PE = 25216,2,1,0 %; ! [2] macro PYXIS$V_MASK_MEM_NEM = 25216,3,1,0 %; ! [3] macro PYXIS$V_MASK_PCI_SERR = 25216,4,1,0 %; ! [4] macro PYXIS$V_MASK_PCI_PERR = 25216,5,1,0 %; ! [5] macro PYXIS$V_MASK_PCI_ADR_PE = 25216,6,1,0 %; ! [6] macro PYXIS$V_MASK_M_ABORT = 25216,7,1,0 %; ! [7] macro PYXIS$V_MASK_T_ABORT = 25216,8,1,0 %; ! [8] macro PYXIS$V_MASK_PA_PTE_INV = 25216,9,1,0 %; ! [9] macro PYXIS$V_MASK_IOA_TIMEOUT = 25216,11,1,0 %; ! [11] ! ! PYXIS Error Syndrome register - 0x8740008300 ! macro PYXIS$L_PYXIS_SYND = 25344,0,32,1 %; macro PYXIS$R_PYXIS_SYND_BITS = 25344,0,32,0 %; macro PYXIS$V_PYXIS_SYNDROME0 = 25344,0,8,0 %; literal PYXIS$S_PYXIS_SYNDROME0 = 8; macro PYXIS$V_PYXIS_SYNDROME1 = 25344,8,8,0 %; literal PYXIS$S_PYXIS_SYNDROME1 = 8; macro PYXIS$V_PYXIS_RAW_CHECK_BITS = 25344,16,8,0 %; macro PYXIS$V_PYXIS_SYND_CE0 = 25344,24,1,0 %; ! [24] macro PYXIS$V_PYXIS_SYND_CE1 = 25344,25,1,0 %; ! [25] macro PYXIS$V_PYXIS_SYND_UCE0 = 25344,26,1,0 %; ! [26] macro PYXIS$V_PYXIS_SYND_UCE1 = 25344,27,1,0 %; ! [27] ! ! PYXIS Error data register - 0x8740008308 ! macro PYXIS$Q_PYXIS_ERRDATA = 25352,0,0,1 %; literal PYXIS$S_PYXIS_ERRDATA = 8; ! ! PYXIS Memory Error Address register 0 - 0x8740008400 ! macro PYXIS$L_PYXIS_MEAR = 25600,0,32,1 %; macro PYXIS$V_MEAR_ADDR_H = 25600,4,28,0 %; literal PYXIS$S_MEAR_ADDR_H = 28; ! ! PYXIS Memory Error status register 1 - 0x8740008440 ! macro PYXIS$L_PYXIS_MESR = 25664,0,32,1 %; macro PYXIS$V_MESR_ADDR_3932 = 25664,0,8,0 %; literal PYXIS$S_MESR_ADDR_3932 = 8; ! [7:0] macro PYXIS$V_MESR_DMA_RD_NXM = 25664,8,1,0 %; ! [8] macro PYXIS$V_MESR_DMA_WR_NXM = 25664,9,1,0 %; ! [9] macro PYXIS$V_MESR_CPU_RD_NXM = 25664,10,1,0 %; ! [10] macro PYXIS$V_MESR_CPU_WR_NXM = 25664,11,1,0 %; ! [11] macro PYXIS$V_MESR_IO_RD_NXM = 25664,12,1,0 %; ! [12] macro PYXIS$V_MESR_IO_WR_NXM = 25664,13,1,0 %; ! [13] macro PYXIS$V_MESR_VICTIM_NXM = 25664,14,1,0 %; ! [14] macro PYXIS$V_MESR_TLBFILL_NXM = 25664,15,1,0 %; ! [15] macro PYXIS$V_MESR_OWORD_INDEX = 25664,16,2,0 %; literal PYXIS$S_MESR_OWORD_INDEX = 2; ! [17:16] macro PYXIS$V_MESR_DATA_CYCLE_TYP = 25664,20,5,0 %; literal PYXIS$S_MESR_DATA_CYCLE_TYP = 5; ! [24:20] macro PYXIS$V_MESR_SEQ_ST = 25664,25,7,0 %; literal PYXIS$S_MESR_SEQ_ST = 7; ! [31:25] ! ! PCI Error register 0 - 0x8740008800 ! macro PYXIS$L_PYXIS_PCIE0 = 26624,0,32,1 %; macro PYXIS$V_PCIE_DMA_CMD = 26624,0,4,0 %; literal PYXIS$S_PCIE_DMA_CMD = 4; ! [3:0] macro PYXIS$V_PCIE_DMA_DAC = 26624,5,1,0 %; ! [5] macro PYXIS$V_PCIE_WINDOW = 26624,8,4,0 %; literal PYXIS$S_PCIE_WINDOW = 4; ! [11:8] macro PYXIS$V_PCIE_MSTR_STATE = 26624,16,4,0 %; literal PYXIS$S_PCIE_MSTR_STATE = 4; ! [19:16] macro PYXIS$V_PCIE_TRGT_STATE = 26624,20,4,0 %; literal PYXIS$S_PCIE_TRGT_STATE = 4; ! [23:20] macro PYXIS$V_PCIE_PCI_CMD = 26624,24,4,0 %; literal PYXIS$S_PCIE_PCI_CMD = 4; ! [27:24] macro PYXIS$V_PCIE_PCI_DAC = 26624,28,1,0 %; ! [28] ! ! PYXIS PCI error register 1 - 0x8740008840 ! macro PYXIS$L_PCIE1_DMA_ADDR_H = 26688,0,32,1 %; ! ! PYXIS PCI error register 2 - 0x8740008880 ! macro PYXIS$L_PCIE2_PCI_ADDR_H = 26752,0,32,1 %; ! ! Memory Configuration Register - 0x8750000000 ! macro PYXIS$L_MEM_MCR = 32768,0,32,1 %; macro PYXIS$V_MCR_MODE_REQ = 32768,0,1,0 %; ! 0 macro PYXIS$V_MCR_SERVER_MODE = 32768,8,1,0 %; ! 8 macro PYXIS$V_MCR_BCACHE_STAT = 32768,9,1,0 %; ! 9 macro PYXIS$V_MCR_BCACHE_EN = 32768,10,1,0 %; ! 10 macro PYXIS$V_MCR_PIPELINED_CACHE = 32768,11,1,0 %; ! 11 macro PYXIS$V_MCR_OVERLAP_DIS = 32768,12,1,0 %; ! 12 macro PYXIS$V_MCR_SEQ_TRACE = 32768,13,1,0 %; ! 13 macro PYXIS$V_MCR_CKE_AUTO = 32768,14,1,0 %; ! 14 macro PYXIS$V_MCR_DRAM_CLK_AUTO = 32768,15,1,0 %; ! 15 macro PYXIS$V_MCR_DRAM_MODE = 32768,16,14,0 %; literal PYXIS$S_MCR_DRAM_MODE = 14; ! 29:16 ! ! Memory Clock Mask Register - 0x8750000040 ! macro PYXIS$L_MEM_MCMR = 32832,0,32,1 %; macro PYXIS$V_MCMR_DRAM_CLOCK_MASK = 32832,0,16,0 %; literal PYXIS$S_MCMR_DRAM_CLOCK_MASK = 16; ! 15:0 ! ! Memory Global Timing Register - 0x8750000200 ! macro PYXIS$L_MEM_MGTR = 33280,0,32,1 %; macro PYXIS$V_MGTR_MIN_RAS_PRE = 33280,0,3,0 %; literal PYXIS$S_MGTR_MIN_RAS_PRE = 3; ! 2:0 macro PYXIS$V_MGTR_CAS_LAT = 33280,4,2,0 %; literal PYXIS$S_MGTR_CAS_LAT = 2; ! 5:4 macro PYXIS$V_MGTR_IDLE_BC_WIDTH = 33280,8,3,0 %; literal PYXIS$S_MGTR_IDLE_BC_WIDTH = 3; ! 10:8 ! ! Memory Refresh Timing Register - 0x8750000300 ! macro PYXIS$L_MEM_MRTR = 33536,0,32,1 %; macro PYXIS$V_MRTR_REF_WIDTH = 33536,4,3,0 %; literal PYXIS$S_MRTR_REF_WIDTH = 3; ! 6:4 macro PYXIS$V_MRTR_REF_INT = 33536,7,6,0 %; literal PYXIS$S_MRTR_REF_INT = 6; ! 12:7 macro PYXIS$V_MRTR_FORCE_REF = 33536,15,1,0 %; ! 15 ! ! Memory Row History Policy Register - 0x8750000400 ! macro PYXIS$L_MEM_MRPHR = 33792,0,32,1 %; macro PYXIS$V_MRPHR_POLICY_MASK = 33792,0,16,0 %; literal PYXIS$S_MRPHR_POLICY_MASK = 16; ! 15:0 ! ! Memory Debug Register 1 - 0x8750000500 ! macro PYXIS$L_MEM_MDR1 = 34048,0,32,1 %; macro PYXIS$V_MDR1_SEL0 = 34048,0,6,0 %; literal PYXIS$S_MDR1_SEL0 = 6; ! 5:0 macro PYXIS$V_MDR1_SEL1 = 34048,8,6,0 %; literal PYXIS$S_MDR1_SEL1 = 6; ! 13:8 macro PYXIS$V_MDR1_SEL2 = 34048,16,6,0 %; literal PYXIS$S_MDR1_SEL2 = 6; ! 21:16 macro PYXIS$V_MDR1_SEL3 = 34048,24,6,0 %; literal PYXIS$S_MDR1_SEL3 = 6; ! 29:24 macro PYXIS$V_MDR1_ENABLE = 34048,31,1,0 %; ! 31 ! ! Memory Debug Register 2 - 0x8750000540 ! macro PYXIS$L_MEM_MDR2 = 34112,0,32,1 %; macro PYXIS$V_MDR2_SEL0 = 34112,0,6,0 %; literal PYXIS$S_MDR2_SEL0 = 6; ! 5:0 macro PYXIS$V_MDR2_SEL1 = 34112,8,6,0 %; literal PYXIS$S_MDR2_SEL1 = 6; ! 13:8 macro PYXIS$V_MDR2_SEL2 = 34112,16,6,0 %; literal PYXIS$S_MDR2_SEL2 = 6; ! 21:16 macro PYXIS$V_MDR2_SEL3 = 34112,24,6,0 %; literal PYXIS$S_MDR2_SEL3 = 6; ! 29:24 macro PYXIS$V_MDR2_ENABLE = 34112,31,1,0 %; ! 31 ! ! Memory Base Address Register 0 - 0x8750000600 ! macro PYXIS$L_MEM_BBAR0 = 34304,0,32,1 %; macro PYXIS$V_BBAR0_BASE_ADDR_3324 = 34304,6,10,0 %; literal PYXIS$S_BBAR0_BASE_ADDR_3324 = 10; ! 15:6 ! ! Memory Base Address Register 1 - 0x8750000640 ! macro PYXIS$L_MEM_BBAR1 = 34368,0,32,1 %; macro PYXIS$V_BBAR1_BASE_ADDR_3324 = 34368,6,10,0 %; literal PYXIS$S_BBAR1_BASE_ADDR_3324 = 10; ! 15:6 ! ! Memory Base Address Register 2 - 0x8750000680 ! macro PYXIS$L_MEM_BBAR2 = 34432,0,32,1 %; macro PYXIS$V_BBAR2_BASE_ADDR_3324 = 34432,6,10,0 %; literal PYXIS$S_BBAR2_BASE_ADDR_3324 = 10; ! 15:6 ! ! Memory Base Address Register 3 - 0x87500006c0 ! macro PYXIS$L_MEM_BBAR3 = 34496,0,32,1 %; macro PYXIS$V_BBAR3_BASE_ADDR_3324 = 34496,6,10,0 %; literal PYXIS$S_BBAR3_BASE_ADDR_3324 = 10; ! 15:6 ! ! Memory Base Address Register 4 - 0x8750000700 ! macro PYXIS$L_MEM_BBAR4 = 34560,0,32,1 %; macro PYXIS$V_BBAR4_BASE_ADDR_3324 = 34560,6,10,0 %; literal PYXIS$S_BBAR4_BASE_ADDR_3324 = 10; ! 15:6 ! ! Memory Base Address Register 5 - 0x8750000740 ! macro PYXIS$L_MEM_BBAR5 = 34624,0,32,1 %; macro PYXIS$V_BBAR5_BASE_ADDR_3324 = 34624,6,10,0 %; literal PYXIS$S_BBAR5_BASE_ADDR_3324 = 10; ! 15:6 ! ! Memory Base Address Register 6 - 0x8750000780 ! macro PYXIS$L_MEM_BBAR6 = 34688,0,32,1 %; macro PYXIS$V_BBAR6_BASE_ADDR_3324 = 34688,6,10,0 %; literal PYXIS$S_BBAR6_BASE_ADDR_3324 = 10; ! 15:6 ! ! Memory Base Address Register 7 - 0x87500007c0 ! macro PYXIS$L_MEM_BBAR7 = 34752,0,32,1 %; macro PYXIS$V_BBAR7_BASE_ADDR_3324 = 34752,6,10,0 %; literal PYXIS$S_BBAR7_BASE_ADDR_3324 = 10; ! 15:6 ! ! Start of Bank Config ! ! Memory Bank Configuration Register 0 - 0x8750000800 ! macro PYXIS$L_MEM_MBCR0 = 34816,0,32,1 %; macro PYXIS$V_MBCR0_BANK_ENABLE = 34816,0,1,0 %; ! 0 macro PYXIS$V_MBCR0_BANK_SIZE = 34816,1,4,0 %; literal PYXIS$S_MBCR0_BANK_SIZE = 4; ! 4:1 macro PYXIS$V_MBCR0_SUBBANK_ENABLE = 34816,5,1,0 %; ! 5 macro PYXIS$V_MBCR0_COLSEL = 34816,6,1,0 %; ! 6 macro PYXIS$V_MBCR0_4BANK = 34816,7,1,0 %; ! 7 ! ! Memory Bank Configuration Register 1 - 0x8750000840 ! macro PYXIS$L_MEM_MBCR1 = 34880,0,32,1 %; macro PYXIS$V_MBCR1_BANK_ENABLE = 34880,0,1,0 %; ! 0 macro PYXIS$V_MBCR1_BANK_SIZE = 34880,1,4,0 %; literal PYXIS$S_MBCR1_BANK_SIZE = 4; ! 4:1 macro PYXIS$V_MBCR1_SUBBANK_ENABLE = 34880,5,1,0 %; ! 5 macro PYXIS$V_MBCR1_COLSEL = 34880,6,1,0 %; ! 6 macro PYXIS$V_MBCR1_4BANK = 34880,7,1,0 %; ! 7 ! ! Memory Bank Configuration Register 2 - 0x8750000880 ! macro PYXIS$L_MEM_MBCR2 = 34944,0,32,1 %; macro PYXIS$V_MBCR2_BANK_ENABLE = 34944,0,1,0 %; ! 0 macro PYXIS$V_MBCR2_BANK_SIZE = 34944,1,4,0 %; literal PYXIS$S_MBCR2_BANK_SIZE = 4; ! 4:1 macro PYXIS$V_MBCR2_SUBBANK_ENABLE = 34944,5,1,0 %; ! 5 macro PYXIS$V_MBCR2_COLSEL = 34944,6,1,0 %; ! 6 macro PYXIS$V_MBCR2_4BANK = 34944,7,1,0 %; ! 7 ! ! Memory Bank Configuration Register 3 - 0x87500008c0 ! macro PYXIS$L_MEM_MBCR3 = 35008,0,32,1 %; macro PYXIS$V_MBCR3_BANK_ENABLE = 35008,0,1,0 %; ! 0 macro PYXIS$V_MBCR3_BANK_SIZE = 35008,1,4,0 %; literal PYXIS$S_MBCR3_BANK_SIZE = 4; ! 4:1 macro PYXIS$V_MBCR3_SUBBANK_ENABLE = 35008,5,1,0 %; ! 5 macro PYXIS$V_MBCR3_COLSEL = 35008,6,1,0 %; ! 6 macro PYXIS$V_MBCR3_4BANK = 35008,7,1,0 %; ! 7 ! ! Memory Bank Configuration Register 4 - 0x8750000900 ! macro PYXIS$L_MEM_MBCR4 = 35072,0,32,1 %; macro PYXIS$V_MBCR4_BANK_ENABLE = 35072,0,1,0 %; ! 0 macro PYXIS$V_MBCR4_BANK_SIZE = 35072,1,4,0 %; literal PYXIS$S_MBCR4_BANK_SIZE = 4; ! 4:1 macro PYXIS$V_MBCR4_SUBBANK_ENABLE = 35072,5,1,0 %; ! 5 macro PYXIS$V_MBCR4_COLSEL = 35072,6,1,0 %; ! 6 macro PYXIS$V_MBCR4_4BANK = 35072,7,1,0 %; ! 7 ! ! Memory Bank Configuration Register 5 - 0x8750000940 ! macro PYXIS$L_MEM_MBCR5 = 35136,0,32,1 %; macro PYXIS$V_MBCR5_BANK_ENABLE = 35136,0,1,0 %; ! 0 macro PYXIS$V_MBCR5_BANK_SIZE = 35136,1,4,0 %; literal PYXIS$S_MBCR5_BANK_SIZE = 4; ! 4:1 macro PYXIS$V_MBCR5_SUBBANK_ENABLE = 35136,5,1,0 %; ! 5 macro PYXIS$V_MBCR5_COLSEL = 35136,6,1,0 %; ! 6 macro PYXIS$V_MBCR5_4BANK = 35136,7,1,0 %; ! 7 ! ! Memory Bank Configuration Register 6 - 0x8750000980 ! macro PYXIS$L_MEM_MBCR6 = 35200,0,32,1 %; macro PYXIS$V_MBCR6_BANK_ENABLE = 35200,0,1,0 %; ! 0 macro PYXIS$V_MBCR6_BANK_SIZE = 35200,1,4,0 %; literal PYXIS$S_MBCR6_BANK_SIZE = 4; ! 4:1 macro PYXIS$V_MBCR6_SUBBANK_ENABLE = 35200,5,1,0 %; ! 5 macro PYXIS$V_MBCR6_COLSEL = 35200,6,1,0 %; ! 6 macro PYXIS$V_MBCR6_4BANK = 35200,7,1,0 %; ! 7 ! ! Memory Bank Configuration Register 7 - 0x87500009c0 ! macro PYXIS$L_MEM_MBCR7 = 35264,0,32,1 %; macro PYXIS$V_MBCR7_BANK_ENABLE = 35264,0,1,0 %; ! 0 macro PYXIS$V_MBCR7_BANK_SIZE = 35264,1,4,0 %; literal PYXIS$S_MBCR7_BANK_SIZE = 4; ! 4:1 macro PYXIS$V_MBCR7_SUBBANK_ENABLE = 35264,5,1,0 %; ! 5 macro PYXIS$V_MBCR7_COLSEL = 35264,6,1,0 %; ! 6 macro PYXIS$V_MBCR7_4BANK = 35264,7,1,0 %; ! 7 ! ! Start of Bank TIming Registers ! Memory Bank TIming Register 0 - 0x8750000A00 ! macro PYXIS$L_MEM_MBTR0 = 35328,0,32,1 %; macro PYXIS$V_MBTR0_ROW_ADDR_HOLD = 35328,0,3,0 %; literal PYXIS$S_MBTR0_ROW_ADDR_HOLD = 3; ! 2:0 macro PYXIS$V_MBTR0_TOSHIBA = 35328,4,1,0 %; ! 4 macro PYXIS$V_MBTR0_SLOW_CHARGE = 35328,5,1,0 %; ! 5 ! ! Memory Bank TIming Register 1 - 0x8750000A40 ! macro PYXIS$L_MEM_MBTR1 = 35392,0,32,1 %; macro PYXIS$V_MBTR1_ROW_ADDR_HOLD = 35392,0,3,0 %; literal PYXIS$S_MBTR1_ROW_ADDR_HOLD = 3; ! 2:0 macro PYXIS$V_MBTR1_TOSHIBA = 35392,4,1,0 %; ! 4 macro PYXIS$V_MBTR1_SLOW_CHARGE = 35392,5,1,0 %; ! 5 ! ! Memory Bank TIming Register 2 - 0x8750000A80 ! macro PYXIS$L_MEM_MBTR2 = 35456,0,32,1 %; macro PYXIS$V_MBTR2_ROW_ADDR_HOLD = 35456,0,3,0 %; literal PYXIS$S_MBTR2_ROW_ADDR_HOLD = 3; ! 2:0 macro PYXIS$V_MBTR2_TOSHIBA = 35456,4,1,0 %; ! 4 macro PYXIS$V_MBTR2_SLOW_CHARGE = 35456,5,1,0 %; ! 5 ! ! Memory Bank TIming Register 3 - 0x8750000Ac0 ! macro PYXIS$L_MEM_MBTR3 = 35520,0,32,1 %; macro PYXIS$V_MBTR3_ROW_ADDR_HOLD = 35520,0,3,0 %; literal PYXIS$S_MBTR3_ROW_ADDR_HOLD = 3; ! 2:0 macro PYXIS$V_MBTR3_TOSHIBA = 35520,4,1,0 %; ! 4 macro PYXIS$V_MBTR3_SLOW_CHARGE = 35520,5,1,0 %; ! 5 ! ! Memory Bank TIming Register 4 - 0x8750000B00 ! macro PYXIS$L_MEM_MBTR4 = 35584,0,32,1 %; macro PYXIS$V_MBTR4_ROW_ADDR_HOLD = 35584,0,3,0 %; literal PYXIS$S_MBTR4_ROW_ADDR_HOLD = 3; ! 2:0 macro PYXIS$V_MBTR4_TOSHIBA = 35584,4,1,0 %; ! 4 macro PYXIS$V_MBTR4_SLOW_CHARGE = 35584,5,1,0 %; ! 5 ! ! Memory Bank TIming Register 5 - 0x8750000B40 ! macro PYXIS$L_MEM_MBTR5 = 35648,0,32,1 %; macro PYXIS$V_MBTR5_ROW_ADDR_HOLD = 35648,0,3,0 %; literal PYXIS$S_MBTR5_ROW_ADDR_HOLD = 3; ! 2:0 macro PYXIS$V_MBTR5_TOSHIBA = 35648,4,1,0 %; ! 4 macro PYXIS$V_MBTR5_SLOW_CHARGE = 35648,5,1,0 %; ! 5 ! ! Memory Bank TIming Register 6 - 0x8750000B80 ! macro PYXIS$L_MEM_MBTR6 = 35712,0,32,1 %; macro PYXIS$V_MBTR6_ROW_ADDR_HOLD = 35712,0,3,0 %; literal PYXIS$S_MBTR6_ROW_ADDR_HOLD = 3; ! 2:0 macro PYXIS$V_MBTR6_TOSHIBA = 35712,4,1,0 %; ! 4 macro PYXIS$V_MBTR6_SLOW_CHARGE = 35712,5,1,0 %; ! 5 ! ! Memory Bank TIming Register 7 - 0x8750000BC0 ! macro PYXIS$L_MEM_MBTR7 = 35776,0,32,1 %; macro PYXIS$V_MBTR7_ROW_ADDR_HOLD = 35776,0,3,0 %; literal PYXIS$S_MBTR7_ROW_ADDR_HOLD = 3; ! 2:0 macro PYXIS$V_MBTR7_TOSHIBA = 35776,4,1,0 %; ! 4 macro PYXIS$V_MBTR7_SLOW_CHARGE = 35776,5,1,0 %; ! 5 ! ! Memory Cache Valid Mask - 0x8750000C00 ! macro PYXIS$L_MEM_CVM = 35840,0,32,1 %; macro PYXIS$V_CVM_CACHE_VALID_MASK = 35840,0,31,0 %; literal PYXIS$S_CVM_CACHE_VALID_MASK = 31; ! 31:0 ! ! PCI Scatter/Gather TBIA - 0x8760000100 ! macro PYXIS$B_FILL345 = 40960,0,0,0 %; literal PYXIS$S_FILL345 = 256; macro PYXIS$L_PCI_TBIA = 41216,0,32,1 %; macro PYXIS$V_TBIA_CSR_WR_DATA = 41216,0,2,0 %; literal PYXIS$S_TBIA_CSR_WR_DATA = 2; ! ! ! PCI Window Base 0 - 0x8760000400 ! macro PYXIS$L_PCI_WBASE0 = 41984,0,32,1 %; macro PYXIS$V_WBASE0_W_EN = 41984,0,1,0 %; ! macro PYXIS$V_WBASE0_SG_EN = 41984,1,1,0 %; ! enable scatter/gather macro PYXIS$V_WBASE0_MEMCS_EN = 41984,2,1,0 %; ! enable MEMCS macro PYXIS$V_WBASE0_DAC_EN = 41984,3,1,0 %; ! enable 64BIT PCI macro PYXIS$V_WBASE0_BASE = 41984,20,12,0 %; literal PYXIS$S_WBASE0_BASE = 12; ! ! PCI Window Mask 0 - 0x8760000440 ! macro PYXIS$L_PCI_WMASK0 = 42048,0,32,1 %; macro PYXIS$V_WMASK0_MASK = 42048,20,12,0 %; literal PYXIS$S_WMASK0_MASK = 12; ! ! PCI Window Translated Base 0 - 0x8760000480 ! macro PYXIS$L_PCI_TBASE0 = 42112,0,32,1 %; macro PYXIS$V_TBASE0_BASE = 42112,8,24,0 %; literal PYXIS$S_TBASE0_BASE = 24; ! ***** ! ! PCI Window Base 1 - 0x8760000500 ! macro PYXIS$L_PCI_WBASE1 = 42240,0,32,1 %; macro PYXIS$V_WBASE1_W_EN = 42240,0,1,0 %; ! macro PYXIS$V_WBASE1_SG_EN = 42240,1,1,0 %; ! enable scatter/gather macro PYXIS$V_WBASE1_MEMCS_EN = 42240,2,1,0 %; ! enable MEMCS macro PYXIS$V_WBASE1_DAC_EN = 42240,3,1,0 %; ! enable 64BIT PCI macro PYXIS$V_WBASE1_BASE = 42240,20,12,0 %; literal PYXIS$S_WBASE1_BASE = 12; ! ! PCI Window Mask 1 - 0x8760000540 ! macro PYXIS$L_PCI_WMASK1 = 42304,0,32,1 %; macro PYXIS$V_WMASK1_MASK = 42304,20,12,0 %; literal PYXIS$S_WMASK1_MASK = 12; ! ! PCI Window Translated Base 1 - 0x8760000580 ! macro PYXIS$L_PCI_TBASE1 = 42368,0,32,1 %; macro PYXIS$V_TBASE1_BASE = 42368,8,24,0 %; literal PYXIS$S_TBASE1_BASE = 24; ! ! PCI Window Base 2 - 0x8760000600 ! macro PYXIS$L_PCI_WBASE2 = 42496,0,32,1 %; macro PYXIS$V_WBASE2_W_EN = 42496,0,1,0 %; ! macro PYXIS$V_WBASE2_SG_EN = 42496,1,1,0 %; ! enable scatter/gather macro PYXIS$V_WBASE2_MEMCS_EN = 42496,2,1,0 %; ! enable MEMCS macro PYXIS$V_WBASE2_DAC_EN = 42496,3,1,0 %; ! enable 64BIT PCI macro PYXIS$V_WBASE2_BASE = 42496,20,12,0 %; literal PYXIS$S_WBASE2_BASE = 12; ! ! PCI Window Mask 2 - 0x8760000640 ! macro PYXIS$L_PCI_WMASK2 = 42560,0,32,1 %; macro PYXIS$V_WMASK2_MASK = 42560,20,12,0 %; literal PYXIS$S_WMASK2_MASK = 12; ! ! PCI Window Translated Base 2 - 0x8760000680 ! macro PYXIS$L_PCI_TBASE2 = 42624,0,32,1 %; macro PYXIS$V_TBASE2_BASE = 42624,8,24,0 %; literal PYXIS$S_TBASE2_BASE = 24; ! ! PCI Window Base 3 - 0x8760000700 ! macro PYXIS$L_PCI_WBASE3 = 42752,0,32,1 %; macro PYXIS$V_WBASE3_W_EN = 42752,0,1,0 %; ! macro PYXIS$V_WBASE3_SG_EN = 42752,1,1,0 %; ! enable scatter/gather macro PYXIS$V_WBASE3_MEMCS_EN = 42752,2,1,0 %; ! enable MEMCS macro PYXIS$V_WBASE3_DAC_EN = 42752,3,1,0 %; ! enable 64BIT PCI macro PYXIS$V_WBASE3_BASE = 42752,20,12,0 %; literal PYXIS$S_WBASE3_BASE = 12; ! ! PCI Window Mask 3 - 0x8760000740 ! macro PYXIS$L_PCI_WMASK3 = 42816,0,32,1 %; macro PYXIS$V_WMASK3_MASK = 42816,20,12,0 %; literal PYXIS$S_WMASK3_MASK = 12; ! ! PCI Window Translated Base 3 - 0x8760000780 ! macro PYXIS$L_PCI_TBASE3 = 42880,0,32,1 %; macro PYXIS$V_TBASE3_BASE = 42880,8,24,0 %; literal PYXIS$S_TBASE3_BASE = 24; ! ! PCI DAC Base Register - 0x87600007C0 ! macro PYXIS$L_PCI_DAC = 42944,0,32,1 %; macro PYXIS$V_DAC_BASE = 42944,0,8,0 %; literal PYXIS$S_DAC_BASE = 8; ! ! PCI Lockable TB Tag 0- 0x8760000800 ! macro PYXIS$L_PCI_LTB0 = 43008,0,32,1 %; macro PYXIS$V_LTB0_VALID = 43008,0,1,0 %; ! macro PYXIS$V_LTB0_LOCKED = 43008,1,1,0 %; ! enable scatter/gather macro PYXIS$V_LTB0_DAC = 43008,2,1,0 %; ! enable 64BIT PCI macro PYXIS$V_LTB0_TAG = 43008,15,17,0 %; literal PYXIS$S_LTB0_TAG = 17; ! ! PCI Lockable TB Tag 1- 0x8760000840 ! macro PYXIS$L_PCI_LTB1 = 43072,0,32,1 %; macro PYXIS$V_LTB1_VALID = 43072,0,1,0 %; ! macro PYXIS$V_LTB1_LOCKED = 43072,1,1,0 %; ! enable scatter/gather macro PYXIS$V_LTB1_DAC = 43072,2,1,0 %; ! enable 64BIT PCI macro PYXIS$V_LTB1_TAG = 43072,15,17,0 %; literal PYXIS$S_LTB1_TAG = 17; ! ! PCI Lockable TB Tag 2- 0x8760000880 ! macro PYXIS$L_PCI_LTB2 = 43136,0,32,1 %; macro PYXIS$V_LTB2_VALID = 43136,0,1,0 %; ! macro PYXIS$V_LTB2_LOCKED = 43136,1,1,0 %; ! enable scatter/gather macro PYXIS$V_LTB2_DAC = 43136,2,1,0 %; ! enable 64BIT PCI macro PYXIS$V_LTB2_TAG = 43136,15,17,0 %; literal PYXIS$S_LTB2_TAG = 17; ! ! PCI Lockable TB Tag 3- 0x87600008C0 ! macro PYXIS$L_PCI_LTB3 = 43200,0,32,1 %; macro PYXIS$V_LTB3_VALID = 43200,0,1,0 %; ! macro PYXIS$V_LTB3_LOCKED = 43200,1,1,0 %; ! enable scatter/gather macro PYXIS$V_LTB3_DAC = 43200,2,1,0 %; ! enable 64BIT PCI macro PYXIS$V_LTB3_TAG = 43200,15,17,0 %; literal PYXIS$S_LTB3_TAG = 17; ! ! PCI TB Tag 0- 0x8760000900 ! macro PYXIS$L_PCI_TB0 = 43264,0,32,1 %; macro PYXIS$V_TB0_VALID = 43264,0,1,0 %; ! macro PYXIS$V_TB0_DAC = 43264,2,1,0 %; ! enable 64BIT PCI macro PYXIS$V_TB0_TAG = 43264,15,17,0 %; literal PYXIS$S_TB0_TAG = 17; ! ! PCI TB Tag 1 - 0x8760000940 ! macro PYXIS$L_PCI_TB1 = 43328,0,32,1 %; macro PYXIS$V_TB1_VALID = 43328,0,1,0 %; ! macro PYXIS$V_TB1_DAC = 43328,2,1,0 %; ! enable 64BIT PCI macro PYXIS$V_TB1_TAG = 43328,15,17,0 %; literal PYXIS$S_TB1_TAG = 17; ! ! PCI TB Tag 2 - 0x8760000980 ! macro PYXIS$L_PCI_TB2 = 43392,0,32,1 %; macro PYXIS$V_TB2_VALID = 43392,0,1,0 %; ! macro PYXIS$V_TB2_DAC = 43392,2,1,0 %; ! enable 64BIT PCI macro PYXIS$V_TB2_TAG = 43392,15,17,0 %; literal PYXIS$S_TB2_TAG = 17; ! ! PCI TB Tag 3- 0x87600009C0 ! macro PYXIS$L_PCI_TB3 = 43456,0,32,1 %; macro PYXIS$V_TB3_VALID = 43456,0,1,0 %; ! macro PYXIS$V_TB3_DAC = 43456,2,1,0 %; ! enable 64BIT PCI macro PYXIS$V_TB3_TAG = 43456,15,17,0 %; literal PYXIS$S_TB3_TAG = 17; ! ! PCI TB0 Page 0- 0x8760001000 ! macro PYXIS$L_PCI_TB0_PAGE0 = 45056,0,32,1 %; macro PYXIS$V_TB0_PAGE0_VALID = 45056,0,1,0 %; ! macro PYXIS$V_TB0_PAGE0_ADDR = 45056,1,21,0 %; literal PYXIS$S_TB0_PAGE0_ADDR = 21; ! ! PCI TB0 Page 1 - 0x8760001040 ! macro PYXIS$L_PCI_TB0_PAGE1 = 45120,0,32,1 %; macro PYXIS$V_TB0_PAGE1_VALID = 45120,0,1,0 %; ! macro PYXIS$V_TB0_PAGE1_ADDR = 45120,1,21,0 %; literal PYXIS$S_TB0_PAGE1_ADDR = 21; ! ! PCI TB0 Page 2 - 0x8760001080 ! macro PYXIS$L_PCI_TB0_PAGE2 = 45184,0,32,1 %; macro PYXIS$V_TB0_PAGE2_VALID = 45184,0,1,0 %; ! macro PYXIS$V_TB0_PAGE2_ADDR = 45184,1,21,0 %; literal PYXIS$S_TB0_PAGE2_ADDR = 21; ! ! PCI TB0 Page 3- 0x87600010C0 ! macro PYXIS$L_PCI_TB0_PAGE3 = 45248,0,32,1 %; macro PYXIS$V_TB0_PAGE3_VALID = 45248,0,1,0 %; ! macro PYXIS$V_TB0_PAGE3_ADDR = 45248,1,21,0 %; literal PYXIS$S_TB0_PAGE3_ADDR = 21; ! ! PCI TB1 Page 0- 0x8760001100 ! macro PYXIS$L_PCI_TB1_PAGE0 = 45312,0,32,1 %; macro PYXIS$V_TB1_PAGE0_VALID = 45312,0,1,0 %; ! macro PYXIS$V_TB1_PAGE0_ADDR = 45312,1,21,0 %; literal PYXIS$S_TB1_PAGE0_ADDR = 21; ! ! PCI TB1 Page 1 - 0x8760001140 ! macro PYXIS$L_PCI_TB1_PAGE1 = 45376,0,32,1 %; macro PYXIS$V_TB1_PAGE1_VALID = 45376,0,1,0 %; ! macro PYXIS$V_TB1_PAGE1_ADDR = 45376,1,21,0 %; literal PYXIS$S_TB1_PAGE1_ADDR = 21; ! ! PCI TB1 Page 2 - 0x8760001180 ! macro PYXIS$L_PCI_TB1_PAGE2 = 45440,0,32,1 %; macro PYXIS$V_TB1_PAGE2_VALID = 45440,0,1,0 %; ! macro PYXIS$V_TB1_PAGE2_ADDR = 45440,1,21,0 %; literal PYXIS$S_TB1_PAGE2_ADDR = 21; ! ! PCI TB1 Page 3- 0x87600011C0 ! macro PYXIS$L_PCI_TB1_PAGE3 = 45504,0,32,1 %; macro PYXIS$V_TB1_PAGE3_VALID = 45504,0,1,0 %; ! macro PYXIS$V_TB1_PAGE3_ADDR = 45504,1,21,0 %; literal PYXIS$S_TB1_PAGE3_ADDR = 21; ! ! PCI TB2 Page 0- 0x8760001200 ! macro PYXIS$L_PCI_TB2_PAGE0 = 45568,0,32,1 %; macro PYXIS$V_TB2_PAGE0_VALID = 45568,0,1,0 %; ! macro PYXIS$V_TB2_PAGE0_ADDR = 45568,1,21,0 %; literal PYXIS$S_TB2_PAGE0_ADDR = 21; ! ! PCI TB2 Page 1 - 0x8760001240 ! macro PYXIS$L_PCI_TB2_PAGE1 = 45632,0,32,1 %; macro PYXIS$V_TB2_PAGE1_VALID = 45632,0,1,0 %; ! macro PYXIS$V_TB2_PAGE1_ADDR = 45632,1,21,0 %; literal PYXIS$S_TB2_PAGE1_ADDR = 21; ! ! PCI TB2 Page 2 - 0x8760001280 ! macro PYXIS$L_PCI_TB2_PAGE2 = 45696,0,32,1 %; macro PYXIS$V_TB2_PAGE2_VALID = 45696,0,1,0 %; ! macro PYXIS$V_TB2_PAGE2_ADDR = 45696,1,21,0 %; literal PYXIS$S_TB2_PAGE2_ADDR = 21; ! ! PCI TB2 Page 3- 0x87600012C0 ! macro PYXIS$L_PCI_TB2_PAGE3 = 45760,0,32,1 %; macro PYXIS$V_TB2_PAGE3_VALID = 45760,0,1,0 %; ! macro PYXIS$V_TB2_PAGE3_ADDR = 45760,1,21,0 %; literal PYXIS$S_TB2_PAGE3_ADDR = 21; ! ! PCI TB3 Page 0- 0x8760001300 ! macro PYXIS$L_PCI_TB3_PAGE0 = 45824,0,32,1 %; macro PYXIS$V_TB3_PAGE0_VALID = 45824,0,1,0 %; ! macro PYXIS$V_TB3_PAGE0_ADDR = 45824,1,21,0 %; literal PYXIS$S_TB3_PAGE0_ADDR = 21; ! ! PCI TB3 Page 1 - 0x8760001340 ! macro PYXIS$L_PCI_TB3_PAGE1 = 45888,0,32,1 %; macro PYXIS$V_TB3_PAGE1_VALID = 45888,0,1,0 %; ! macro PYXIS$V_TB3_PAGE1_ADDR = 45888,1,21,0 %; literal PYXIS$S_TB3_PAGE1_ADDR = 21; ! ! PCI TB3 Page 2 - 0x8760001380 ! macro PYXIS$L_PCI_TB3_PAGE2 = 45952,0,32,1 %; macro PYXIS$V_TB3_PAGE2_VALID = 45952,0,1,0 %; ! macro PYXIS$V_TB3_PAGE2_ADDR = 45952,1,21,0 %; literal PYXIS$S_TB3_PAGE2_ADDR = 21; ! ! PCI TB3 Page 3- 0x87600013C0 ! macro PYXIS$L_PCI_TB3_PAGE3 = 46016,0,32,1 %; macro PYXIS$V_TB3_PAGE3_VALID = 46016,0,1,0 %; ! macro PYXIS$V_TB3_PAGE3_ADDR = 46016,1,21,0 %; literal PYXIS$S_TB3_PAGE3_ADDR = 21; ! ! PCI TB4 Page 0- 0x8760001400 ! macro PYXIS$L_PCI_TB4_PAGE0 = 46080,0,32,1 %; macro PYXIS$V_TB4_PAGE0_VALID = 46080,0,1,0 %; ! macro PYXIS$V_TB4_PAGE0_ADDR = 46080,1,21,0 %; literal PYXIS$S_TB4_PAGE0_ADDR = 21; ! ! PCI TB4 Page 1 - 0x8760001440 ! macro PYXIS$L_PCI_TB4_PAGE1 = 46144,0,32,1 %; macro PYXIS$V_TB4_PAGE1_VALID = 46144,0,1,0 %; ! macro PYXIS$V_TB4_PAGE1_ADDR = 46144,1,21,0 %; literal PYXIS$S_TB4_PAGE1_ADDR = 21; ! ! PCI TB4 Page 2 - 0x8760001480 ! macro PYXIS$L_PCI_TB4_PAGE2 = 46208,0,32,1 %; macro PYXIS$V_TB4_PAGE2_VALID = 46208,0,1,0 %; ! macro PYXIS$V_TB4_PAGE2_ADDR = 46208,1,21,0 %; literal PYXIS$S_TB4_PAGE2_ADDR = 21; ! ! PCI TB4 Page 3- 0x87600014C0 ! macro PYXIS$L_PCI_TB4_PAGE3 = 46272,0,32,1 %; macro PYXIS$V_TB4_PAGE3_VALID = 46272,0,1,0 %; ! macro PYXIS$V_TB4_PAGE3_ADDR = 46272,1,21,0 %; literal PYXIS$S_TB4_PAGE3_ADDR = 21; ! ! PCI TB5 Page 0- 0x8760001500 ! macro PYXIS$L_PCI_TB5_PAGE0 = 46336,0,32,1 %; macro PYXIS$V_TB5_PAGE0_VALID = 46336,0,1,0 %; ! macro PYXIS$V_TB5_PAGE0_ADDR = 46336,1,21,0 %; literal PYXIS$S_TB5_PAGE0_ADDR = 21; ! ! PCI TB5 Page 1 - 0x8760001540 ! macro PYXIS$L_PCI_TB5_PAGE1 = 46400,0,32,1 %; macro PYXIS$V_TB5_PAGE1_VALID = 46400,0,1,0 %; ! macro PYXIS$V_TB5_PAGE1_ADDR = 46400,1,21,0 %; literal PYXIS$S_TB5_PAGE1_ADDR = 21; ! ! PCI TB5 Page 2 - 0x8760001580 ! macro PYXIS$L_PCI_TB5_PAGE2 = 46464,0,32,1 %; macro PYXIS$V_TB5_PAGE2_VALID = 46464,0,1,0 %; ! macro PYXIS$V_TB5_PAGE2_ADDR = 46464,1,21,0 %; literal PYXIS$S_TB5_PAGE2_ADDR = 21; ! ! PCI TB5 Page 3- 0x87600015C0 ! macro PYXIS$L_PCI_TB5_PAGE3 = 46528,0,32,1 %; macro PYXIS$V_TB5_PAGE3_VALID = 46528,0,1,0 %; ! macro PYXIS$V_TB5_PAGE3_ADDR = 46528,1,21,0 %; literal PYXIS$S_TB5_PAGE3_ADDR = 21; ! ! PCI TB6 Page 0- 0x8760001600 ! macro PYXIS$L_PCI_TB6_PAGE0 = 46592,0,32,1 %; macro PYXIS$V_TB6_PAGE0_VALID = 46592,0,1,0 %; ! macro PYXIS$V_TB6_PAGE0_ADDR = 46592,1,21,0 %; literal PYXIS$S_TB6_PAGE0_ADDR = 21; ! ! PCI TB6 Page 1 - 0x8760001640 ! macro PYXIS$L_PCI_TB6_PAGE1 = 46656,0,32,1 %; macro PYXIS$V_TB6_PAGE1_VALID = 46656,0,1,0 %; ! macro PYXIS$V_TB6_PAGE1_ADDR = 46656,1,21,0 %; literal PYXIS$S_TB6_PAGE1_ADDR = 21; ! ! PCI TB6 Page 2 - 0x8760001680 ! macro PYXIS$L_PCI_TB6_PAGE2 = 46720,0,32,1 %; macro PYXIS$V_TB6_PAGE2_VALID = 46720,0,1,0 %; ! macro PYXIS$V_TB6_PAGE2_ADDR = 46720,1,21,0 %; literal PYXIS$S_TB6_PAGE2_ADDR = 21; ! ! PCI TB6 Page 3- 0x87600016C0 ! macro PYXIS$L_PCI_TB6_PAGE3 = 46784,0,32,1 %; macro PYXIS$V_TB6_PAGE3_VALID = 46784,0,1,0 %; ! macro PYXIS$V_TB6_PAGE3_ADDR = 46784,1,21,0 %; literal PYXIS$S_TB6_PAGE3_ADDR = 21; ! ! PCI TB7 Page 0- 0x8760001700 ! macro PYXIS$L_PCI_TB7_PAGE0 = 46848,0,32,1 %; macro PYXIS$V_TB7_PAGE0_VALID = 46848,0,1,0 %; ! macro PYXIS$V_TB7_PAGE0_ADDR = 46848,1,21,0 %; literal PYXIS$S_TB7_PAGE0_ADDR = 21; ! ! PCI TB7 Page 1 - 0x8760001740 ! macro PYXIS$L_PCI_TB7_PAGE1 = 46912,0,32,1 %; macro PYXIS$V_TB7_PAGE1_VALID = 46912,0,1,0 %; ! macro PYXIS$V_TB7_PAGE1_ADDR = 46912,1,21,0 %; literal PYXIS$S_TB7_PAGE1_ADDR = 21; ! ! PCI TB7 Page 2 - 0x8760001780 ! macro PYXIS$L_PCI_TB7_PAGE2 = 46976,0,32,1 %; macro PYXIS$V_TB7_PAGE2_VALID = 46976,0,1,0 %; ! macro PYXIS$V_TB7_PAGE2_ADDR = 46976,1,21,0 %; literal PYXIS$S_TB7_PAGE2_ADDR = 21; ! ! PCI TB7 Page 3- 0x87600017C0 ! macro PYXIS$L_PCI_TB7_PAGE3 = 47040,0,32,1 %; macro PYXIS$V_TB7_PAGE3_VALID = 47040,0,1,0 %; ! macro PYXIS$V_TB7_PAGE3_ADDR = 47040,1,21,0 %; literal PYXIS$S_TB7_PAGE3_ADDR = 21; ! ! Clock Configuration register - 0x8780000000 ! macro PYXIS$L_CLOCK_CONFIG = 49152,0,32,1 %; macro PYXIS$V_CCR_CLOCK_DIVIDE = 49152,0,2,0 %; literal PYXIS$S_CCR_CLOCK_DIVIDE = 2; ! 1:0 macro PYXIS$V_CCR_PCLK_DIVIDE = 49152,7,3,0 %; literal PYXIS$S_CCR_PCLK_DIVIDE = 3; ! 10:8 macro PYXIS$V_CCR_SEL_CFG = 49152,11,1,0 %; ! 12 macro PYXIS$V_CCR_DCLK_INV = 49152,15,1,0 %; ! 16 macro PYXIS$V_CCR_DCLK_FORCE = 49152,16,1,0 %; ! 17 macro PYXIS$V_CCR_DCLK_DELAY = 49152,24,8,0 %; literal PYXIS$S_CCR_DCLK_DELAY = 8; ! 31:24 ! ! RESET register - 0x8780000900 ! macro PYXIS$L_RESET = 51456,0,32,1 %; ! ! Fan Accumulation register - 0x8790000000 ! macro PYXIS$L_FAR_REG = 57344,0,32,1 %; macro PYXIS$V_FAR_HEAT = 57344,0,24,0 %; literal PYXIS$S_FAR_HEAT = 24; ! 23:0 ! ! Fan Control register - 0x8790000040 ! macro PYXIS$L_FCR_REG = 57408,0,32,1 %; macro PYXIS$V_FCR_ON_HEAT = 57408,0,8,0 %; literal PYXIS$S_FCR_ON_HEAT = 8; ! 7:0 macro PYXIS$V_FCR_SAMPLE = 57408,8,8,0 %; literal PYXIS$S_FCR_SAMPLE = 8; ! 15:8 macro PYXIS$V_FCR_OFF_DELAY = 57408,16,12,0 %; literal PYXIS$S_FCR_OFF_DELAY = 12; ! 27:16 macro PYXIS$V_FCR_FORCE_FAN = 57408,28,1,0 %; ! 28 macro PYXIS$V_FCR_FORCE_FAN_HI = 57408,29,1,0 %; ! 29 macro PYXIS$V_FCR_FAN_ON = 57408,30,1,0 %; ! 30 macro PYXIS$V_FCR_FAN_ON_HI = 57408,31,1,0 %; ! 31 ! ! Fan THRESHOLD register - 0x8790000080 ! macro PYXIS$L_FTR_REG = 57472,0,32,1 %; macro PYXIS$V_FTR_FAN_ON = 57472,0,8,0 %; literal PYXIS$S_FTR_FAN_ON = 8; ! 7:0 macro PYXIS$V_FTR_FAN_HI = 57472,8,8,0 %; literal PYXIS$S_FTR_FAN_HI = 8; ! 15:8 macro PYXIS$V_FTR_FAN_HI_LO = 57472,16,8,0 %; literal PYXIS$S_FTR_FAN_HI_LO = 8; ! 23:16 macro PYXIS$V_FTR_FAN_OFF = 57472,24,8,0 %; literal PYXIS$S_FTR_FAN_OFF = 8; ! 31:24 ! ! Power Control register - 0x87900000C0 ! macro PYXIS$L_PCR_REG = 57536,0,32,1 %; macro PYXIS$V_PCR_POWER_DOWN = 57536,0,1,0 %; ! 0 macro PYXIS$V_PCR_ABUS_DIS = 57536,4,1,0 %; ! 4 macro PYXIS$V_PCR_IINT_DIS = 57536,8,1,0 %; ! 8 macro PYXIS$V_PCR_DO_RESET = 57536,12,1,0 %; ! 12 ! ! Powerdown Timing register - 0x8790000100 ! macro PYXIS$L_PTR_REG = 57600,0,32,1 %; macro PYXIS$V_PTR_PLL_DELAY = 57600,0,8,0 %; literal PYXIS$S_PTR_PLL_DELAY = 8; ! 7:0 macro PYXIS$V_PTR_OFF_DELAY = 57600,8,8,0 %; literal PYXIS$S_PTR_OFF_DELAY = 8; ! 15:8 macro PYXIS$V_PTR_RESET_PULSE_WIDTH = 57600,16,8,0 %; literal PYXIS$S_PTR_RESET_PULSE_WIDTH = 8; ! 23:16 macro PYXIS$V_PTR_MIN_OFF_TIME = 57600,24,8,0 %; literal PYXIS$S_PTR_MIN_OFF_TIME = 8; ! 31:24 ! ! Power Management register - 0x8790000140 ! macro PYXIS$L_PSR_REG = 57664,0,32,1 %; ! ! Int Request Register - 0x87A0000000 ! macro PYXIS$Q_INT_REQ = 65536,0,0,1 %; literal PYXIS$S_INT_REQ = 8; macro PYXIS$V_INT_REQ_31_0 = 65536,0,32,0 %; literal PYXIS$S_INT_REQ_31_0 = 32; ! 31:0 macro PYXIS$V_INT_REQ_61_32 = 65540,0,30,0 %; literal PYXIS$S_INT_REQ_61_32 = 30; ! 61:32 macro PYXIS$V_INT_REQ_CLK_PEND = 65540,30,1,0 %; ! 62 macro PYXIS$V_INT_REQ_ERR_INT = 65540,31,1,0 %; ! 63 ! ! Int Mask Register - 0x87A0000040 ! macro PYXIS$Q_INT_MASK = 65600,0,0,1 %; literal PYXIS$S_INT_MASK = 8; macro PYXIS$V_INT_MASK_31_0 = 65600,0,32,0 %; literal PYXIS$S_INT_MASK_31_0 = 32; ! 31:0 macro PYXIS$V_INT_MASK_61_32 = 65604,0,30,0 %; literal PYXIS$S_INT_MASK_61_32 = 30; ! 61:32 ! ! Interrupt High/Low select register - 0x87A00000C0 ! macro PYXIS$L_INT_HILO = 65728,0,32,1 %; macro PYXIS$V_INT_HILO_BYTE = 65728,0,8,0 %; literal PYXIS$S_INT_HILO_BYTE = 8; ! ! Interrupt Routing register - 0x87A0000140 ! macro PYXIS$L_INT_ROUTE = 65856,0,32,1 %; macro PYXIS$V_INT_RTE = 65856,0,7,0 %; literal PYXIS$S_INT_RTE = 7; ! macro PYXIS$V_INT_RTE_FILL = 65856,7,24,0 %; literal PYXIS$S_INT_RTE_FILL = 24; ! ! General Purpose Output register - 0x87A0000180 ! macro PYXIS$Q_GPO_REGISTER = 65920,0,0,1 %; literal PYXIS$S_GPO_REGISTER = 8; ! ! Interrupt Config register - 0x87A00001C0 ! macro PYXIS$L_INT_CONFIG = 65984,0,32,1 %; macro PYXIS$V_ICNFG_CLK_DIV = 65984,0,4,0 %; literal PYXIS$S_ICNFG_CLK_DIV = 4; ! macro PYXIS$V_ICNFG_IRQ_CNT = 65984,4,3,0 %; literal PYXIS$S_ICNFG_IRQ_CNT = 3; ! macro PYXIS$V_ICNFG_FILL1 = 65984,7,1,0 %; macro PYXIS$V_ICNFG_IRQ_CFG = 65984,8,7,0 %; literal PYXIS$S_ICNFG_IRQ_CFG = 7; ! macro PYXIS$V_ICNFG_FILL2 = 65984,15,1,0 %; macro PYXIS$V_ICNFG_DRIVE_IRQ = 65984,16,1,0 %; ! macro PYXIS$B_FILLAB05 = 65988,0,0,0 %; literal PYXIS$S_FILLAB05 = 60; ! ! Real Time Counter - 0x87A0000200 ! macro PYXIS$Q_REAL_TIME_COUNTER = 66048,0,0,1 %; literal PYXIS$S_REAL_TIME_COUNTER = 8; ! ! Interrupt Timer - 0x87A0000240 ! macro PYXIS$Q_INTERRUPT_TIMER = 66112,0,0,1 %; literal PYXIS$S_INTERRUPT_TIMER = 8; ! ! IIC Control register - 0x87A00002C0 ! macro PYXIS$L_IIC_CONTROL = 66240,0,32,1 %; macro PYXIS$V_IIC_READ_DATA = 66240,0,1,0 %; ! macro PYXIS$V_IIC_READ_CLK = 66240,1,1,0 %; ! macro PYXIS$V_IIC_DATA_EN = 66240,2,1,0 %; ! macro PYXIS$V_IIC_DATA = 66240,3,1,0 %; ! macro PYXIS$V_IIC_CLK_EN = 66240,4,1,0 %; ! macro PYXIS$V_IIC_CLK = 66240,5,1,0 %; ! macro PYXIS$V_IIC_FILL = 66240,6,26,0 %; literal PYXIS$S_IIC_FILL = 26; ! ! CUSCO CPU CSR Registers 87C0100000 ! macro PYXIS$B_CPU_CSR0 = 73728,0,8,1 %; macro PYXIS$B_CPU_CSR1 = 73729,0,8,1 %; ! ! CUSCO Clock registers 87.C010.1000 ! macro PYXIS$B_FRACTION_SEC = 77824,0,8,1 %; macro PYXIS$V_SEC_01 = 77824,0,4,0 %; literal PYXIS$S_SEC_01 = 4; macro PYXIS$V_SEC_1 = 77824,4,4,0 %; literal PYXIS$S_SEC_1 = 4; macro PYXIS$B_SECOND_BYTE = 77825,0,8,1 %; macro PYXIS$V_SECOND = 77825,0,4,0 %; literal PYXIS$S_SECOND = 4; macro PYXIS$V_SEC_10 = 77825,4,3,0 %; literal PYXIS$S_SEC_10 = 3; macro PYXIS$B_MINUTE_BYTE = 77826,0,8,1 %; macro PYXIS$V_MINUTE = 77826,0,4,0 %; literal PYXIS$S_MINUTE = 4; macro PYXIS$V_MIN_10 = 77826,4,3,0 %; literal PYXIS$S_MIN_10 = 3; macro PYXIS$B_MIN_ALARM_BYTE = 77827,0,8,1 %; macro PYXIS$V_ALARM_MIN = 77827,0,4,0 %; literal PYXIS$S_ALARM_MIN = 4; macro PYXIS$V_ALARM_MIN_10 = 77827,4,3,0 %; literal PYXIS$S_ALARM_MIN_10 = 3; macro PYXIS$V_SET_MIN_ALARM = 77827,7,1,0 %; macro PYXIS$B_HOUR_BYTE = 77828,0,8,1 %; macro PYXIS$V_HOUR = 77828,0,4,0 %; literal PYXIS$S_HOUR = 4; macro PYXIS$V_HOUR_10 = 77828,4,1,0 %; macro PYXIS$V_AP_10HR = 77828,5,1,0 %; macro PYXIS$V_TWELVE = 77828,6,1,0 %; macro PYXIS$B_HOUR_ALARM_BYTE = 77829,0,8,1 %; macro PYXIS$V_ALARM_HOUR = 77829,0,4,0 %; literal PYXIS$S_ALARM_HOUR = 4; macro PYXIS$V_ALARM_HOUR_10 = 77829,4,1,0 %; macro PYXIS$V_ALARM_AP_10HR = 77829,5,1,0 %; macro PYXIS$V_ALARM_TWELVE = 77829,6,1,0 %; macro PYXIS$V_SET_HOUR_ALARM = 77829,7,1,0 %; macro PYXIS$B_DAY_BYTE = 77830,0,8,1 %; macro PYXIS$V_DAY = 77830,0,3,0 %; literal PYXIS$S_DAY = 3; macro PYXIS$B_DAY_ALARM_BYTE = 77831,0,8,1 %; macro PYXIS$V_DAY_ALARM = 77831,0,3,0 %; literal PYXIS$S_DAY_ALARM = 3; macro PYXIS$V_DAY_ALARM_MBZ = 77831,3,4,0 %; literal PYXIS$S_DAY_ALARM_MBZ = 4; macro PYXIS$V_SET_DAY_ALARM = 77831,7,1,0 %; macro PYXIS$B_DATE_BYTE = 77832,0,8,1 %; macro PYXIS$V_DATE = 77832,0,4,0 %; literal PYXIS$S_DATE = 4; macro PYXIS$V_DATE_10 = 77832,4,2,0 %; literal PYXIS$S_DATE_10 = 2; macro PYXIS$B_MONTH_BYTE = 77833,0,8,1 %; macro PYXIS$V_MONTH = 77833,0,4,0 %; literal PYXIS$S_MONTH = 4; macro PYXIS$V_MONTH_10 = 77833,4,1,0 %; macro PYXIS$V_MONTH_MBZ = 77833,5,1,0 %; macro PYXIS$V_ESQW = 77833,6,1,0 %; macro PYXIS$V_EOSC = 77833,7,1,0 %; macro PYXIS$B_YEAR_BYTE = 77834,0,8,1 %; macro PYXIS$V_YEAR = 77834,0,4,0 %; literal PYXIS$S_YEAR = 4; macro PYXIS$V_YEAR_10 = 77834,4,4,0 %; literal PYXIS$S_YEAR_10 = 4; ! ! The CUSCO Clock Command Register 87.C010.000B ! macro PYXIS$B_COMMAND_1286_BYTE = 77835,0,8,1 %; macro PYXIS$V_TDF = 77835,0,1,0 %; macro PYXIS$V_WAF = 77835,1,1,0 %; macro PYXIS$V_TDM = 77835,2,1,0 %; macro PYXIS$V_WAM = 77835,3,1,0 %; macro PYXIS$V_PU_LVL = 77835,4,1,0 %; macro PYXIS$V_IBH_LO = 77835,5,1,0 %; macro PYXIS$V_IPSW = 77835,6,1,0 %; macro PYXIS$V_TE = 77835,7,1,0 %; ! ! The CUSCO Watchdog Alarm Register 87.C010.000C ! macro PYXIS$B_WDOG_C_BYTE = 77836,0,8,1 %; macro PYXIS$V_WDOG_01_SEC = 77836,0,4,0 %; literal PYXIS$S_WDOG_01_SEC = 4; macro PYXIS$V_WDOG_1_SEC = 77836,4,4,0 %; literal PYXIS$S_WDOG_1_SEC = 4; macro PYXIS$B_WDOG_D_BYTE = 77837,0,8,1 %; macro PYXIS$V_WDOG_SEC = 77837,0,4,0 %; literal PYXIS$S_WDOG_SEC = 4; macro PYXIS$V_WDOG_10SEC = 77837,4,4,0 %; literal PYXIS$S_WDOG_10SEC = 4; ! ! 0x32 (50) unused User Registers ! ! ! A bunch more fill to get up to the PASS 2 base, ! 87.C010.2000 ! ! ! CUSCO Vintage Interrupt Registers 87.C010.2000 ! ! ! VDIVR - Device Interrupt Vector Register - 87.C010.2000 ! macro PYXIS$B_VDIVR = 86016,0,8,1 %; ! ! V1ISR - IPL 1 Interrupt Summary Register - 87.C010.2020 ! macro PYXIS$B_V1ISR = 86048,0,8,1 %; ! ! V2ISR - IPL 2 Interrupt Summary Register - 87.C010.2040 ! macro PYXIS$B_V2ISR = 86080,0,8,1 %; ! ! V3ISR - IPL 3 Interrupt Summary Register - 87.C010.2060 ! macro PYXIS$B_V3ISR = 86112,0,8,1 %; ! ! VDIER - Device Interrupt Enable Register - 87C010.2080 ! macro PYXIS$B_VDIER = 86144,0,8,1 %; ! ! V1IER - IPL1 Interrupt Enable Register - 87.C010.20A0 ! macro PYXIS$B_V1IER = 86176,0,8,1 %; ! ! V2IER - IPL2 Interrupt Enable Register - 87.C010.20C0 ! macro PYXIS$B_V2IER = 86208,0,8,1 %; ! ! V3IER - IPL3 Interrupt Enable Register - 87.C010.20E0 ! macro PYXIS$B_V3IER = 86240,0,8,1 %; ! ! VMCSR - Master Control and Status Register - 87.C010.2100 ! macro PYXIS$B_VMCSR = 86272,0,8,1 %; ! ! VACSR - Agent Control and Status Register - 87.C010.2140 ! macro PYXIS$B_VACSR = 86336,0,8,1 %; ! ! BIDR- Backplane ID - 87.C010.2160 ! macro PYXIS$B_BIDR = 86368,0,8,1 %; ! ! Following are the interrupt control and status registers. They ! all have the same format, except for VSICSR0 which only has one ! active control and one active status bit. That format is: ! ! bit <0> INTA# Enable ! bit <1> INTB# Enable ! bit <2> INTC# Enable ! bit <3> INTC# Enable ! bit <4> INTA# Status ! bit <5> INTB# Status ! bit <6> INTC# Status ! bit <7> INTD# Status ! 0: Disabled ! 1: Enabled ! ! I have not defined the bits for each register, since the code will ! not use them. The code simply sets the bit indicated by the int ! portion of the INT_LINE register. ! ! ! VSICSR0 - Bus 0 I/O Slot 0 Interrupt Control and Status Reg. - 87.C010.2400 ! macro PYXIS$B_VSICSR0 = 87040,0,8,1 %; ! ! VSICSR1 - Bus 0 I/O Slot 1 Interrupt Control and Status Reg. - 87.C010.2420 ! macro PYXIS$B_VSICSR1 = 87072,0,8,1 %; ! ! VSICSR2 - Bus 0 I/O Slot 2 Interrupt Control and Status Reg. - 87.C010.2440 ! macro PYXIS$B_VSICSR2 = 87104,0,8,1 %; ! ! VSICSR3 - Bus 0 I/O Slot 3 Interrupt Control and Status Reg. - 87.C010.2460 ! macro PYXIS$B_VSICSR3 = 87136,0,8,1 %; ! ! VSICSR4 - Bus 0 I/O Slot 4 Interrupt Control and Status Reg. - 87.C010.2480 ! macro PYXIS$B_VSICSR4 = 87168,0,8,1 %; ! ! VSICSR5 - Bus 0 I/O Slot 5 Interrupt Control and Status Reg. - 87.C010.24A0 ! macro PYXIS$B_VSICSR5 = 87200,0,8,1 %; ! ! VSICSR6 - Bus 0 I/O Slot 6 Interrupt Control and Status Reg. - 87.C010.24C0 ! macro PYXIS$B_VSICSR6 = 87232,0,8,1 %; ! ! VSICSR9 - Bus 1 I/O Slot 1 Interrupt Control and Status Reg. - 87.C010.2520 ! macro PYXIS$B_VSICSR9 = 87328,0,8,1 %; ! ! VSICSRA - Bus 1 I/O Slot 2 Interrupt Control and Status Reg. - 87.C010.2540 ! macro PYXIS$B_VSICSRA = 87360,0,8,1 %; ! ! VSICSRB - Bus 1 I/O Slot 3 Interrupt Control and Status Reg. - 87.C010.2560 ! macro PYXIS$B_VSICSRB = 87392,0,8,1 %; ! ! VSICSRC - Bus 1 I/O Slot 4 Interrupt Control and Status Reg. - 87.C010.2580 ! macro PYXIS$B_VSICSRC = 87424,0,8,1 %; ! ! VSICSR11 - Bus 2 I/O Slot 1 Interrupt Control and Status Reg. - 87.C010.2620 ! macro PYXIS$B_VSICSR11 = 87584,0,8,1 %; ! ! VSICSR12 - Bus 2 I/O Slot 2 Interrupt Control and Status Reg. - 87.C010.2640 ! macro PYXIS$B_VSICSR12 = 87616,0,8,1 %; ! ! VSICSR13 - Bus 2 I/O Slot 3 Interrupt Control and Status Reg. - 87.C010.2660 ! macro PYXIS$B_VSICSR13 = 87648,0,8,1 %; ! ! VSICSR14 - Bus 2 I/O Slot 4 Interrupt Control and Status Reg. - 87.C010.2680 ! macro PYXIS$B_VSICSR14 = 87680,0,8,1 %; ! ! VSICSR15 - Bus 2 I/O Slot 5 Interrupt Control and Status Reg. - 87.C010.26A0 ! macro PYXIS$B_VSICSR15 = 87712,0,8,1 %; ! ! VSICSR16 - Bus 2 I/O Slot 6 Interrupt Control and Status Reg. - 87.C010.26C0 ! macro PYXIS$B_VSICSR16 = 87744,0,8,1 %; ! ! VSICSR17 - Bus 2 I/O Slot 7 Interrupt Control and Status Reg. - 87.C010.26E0 ! macro PYXIS$B_VSICSR17 = 87776,0,8,1 %; ! ! DS1287A register definitions ! literal PYXIS_DS1287A$S_PYXIS_DS1287A = 3624; macro PYXIS_DS1287A$L_PORT_INDEX = 3584,0,32,0 %; macro PYXIS_DS1287A$L_PORT_DATA = 3616,0,32,0 %; !*** MODULE $PZDEF *** ! ! Structure definition for the poolzone header ! literal PZZON$S_PZ_ZONE = 96; macro PZZON$Q_ZONEPAGE_FLINK = 0,0,0,1 %; literal PZZON$S_ZONEPAGE_FLINK = 8; ! flink to next poolzone macro PZZON$Q_ZONEPAGE_BLINK = 8,0,0,1 %; literal PZZON$S_ZONEPAGE_BLINK = 8; ! blink to previous poolzone macro PZZON$Q_PACKET_SIZE = 16,0,0,0 %; literal PZZON$S_PACKET_SIZE = 8; ! size of packets in this poolzone macro PZZON$Q_PAGES = 24,0,0,0 %; literal PZZON$S_PAGES = 8; ! number of pages in this poolzone macro PZZON$Q_MAX_PAGES = 32,0,0,0 %; literal PZZON$S_MAX_PAGES = 8; ! maximum number of pages allowed macro PZZON$Q_FREE_COUNT = 40,0,0,0 %; literal PZZON$S_FREE_COUNT = 8; ! free page count macro PZZON$Q_HITS = 48,0,0,0 %; literal PZZON$S_HITS = 8; ! counts number of hits macro PZZON$Q_MISSES = 56,0,0,0 %; literal PZZON$S_MISSES = 8; ! count number of misses macro PZZON$Q_EXPANSIONS = 64,0,0,0 %; literal PZZON$S_EXPANSIONS = 8; ! count number of poolzone expansions macro PZZON$Q_FAILURES = 72,0,0,0 %; literal PZZON$S_FAILURES = 8; ! count allocation failures macro PZZON$Q_NOT1STPAGE = 80,0,0,0 %; literal PZZON$S_NOT1STPAGE = 8; ! count allocation not from first page macro PZZON$Q_EMPTY_PAGES = 88,0,0,0 %; literal PZZON$S_EMPTY_PAGES = 8; ! count empty pages ! ! Structure definition for the poolzone page header ! literal PZPAG$S_PZ_PAGE = 136; macro PZPAG$Q_ZONEPAGE_FLINK = 0,0,0,1 %; literal PZPAG$S_ZONEPAGE_FLINK = 8; ! flink to next poolzone page macro PZPAG$Q_ZONEPAGE_BLINK = 8,0,0,1 %; literal PZPAG$S_ZONEPAGE_BLINK = 8; ! blink to previous poolzone page macro PZPAG$Q_FREEQUEUE_FLINK = 16,0,0,1 %; literal PZPAG$S_FREEQUEUE_FLINK = 8; ! flink to next free packet macro PZPAG$Q_FREEQUEUE_BLINK = 24,0,0,1 %; literal PZPAG$S_FREEQUEUE_BLINK = 8; ! blink to previous free packet macro PZPAG$Q_ZONE = 32,0,0,1 %; literal PZPAG$S_ZONE = 8; ! pointer to poolzone macro PZPAG$Q_PACKET_SIZE = 40,0,0,0 %; literal PZPAG$S_PACKET_SIZE = 8; ! size of packets in this poolzone page macro PZPAG$Q_PACKET_COUNT = 48,0,0,0 %; literal PZPAG$S_PACKET_COUNT = 8; ! total number of packets in poolzone page macro PZPAG$Q_FREE_COUNT = 56,0,0,0 %; literal PZPAG$S_FREE_COUNT = 8; ! free packet counter macro PZPAG$Q_HITS = 64,0,0,0 %; literal PZPAG$S_HITS = 8; ! count number of hits macro PZPAG$Q_RELINKS = 72,0,0,0 %; literal PZPAG$S_RELINKS = 8; ! count number of page relinks macro PZPAG$Q_RESERVED1 = 80,0,0,0 %; literal PZPAG$S_RESERVED1 = 8; ! reserved fields macro PZPAG$Q_RESERVED2 = 88,0,0,0 %; literal PZPAG$S_RESERVED2 = 8; ! macro PZPAG$Q_RESERVED3 = 96,0,0,0 %; literal PZPAG$S_RESERVED3 = 8; ! macro PZPAG$Q_RESERVED4 = 104,0,0,0 %; literal PZPAG$S_RESERVED4 = 8; ! macro PZPAG$Q_RESERVED5 = 112,0,0,0 %; literal PZPAG$S_RESERVED5 = 8; ! macro PZPAG$Q_RESERVED6 = 120,0,0,0 %; literal PZPAG$S_RESERVED6 = 8; ! macro PZPAG$Q_FIRST_PACKET = 128,0,0,0 %; literal PZPAG$S_FIRST_PACKET = 8; ! address of first packet in poolzone page ! ! Structure definition for the poolzone region header ! literal PZREG$S_PZ_REGION = 176; macro PZREG$Q_FILL_1 = 0,0,0,0 %; literal PZREG$S_FILL_1 = 8; ! spare field macro PZREG$W_SIZE = 8,0,16,0 %; ! size of poolzone region structure macro PZREG$B_TYPE = 10,0,8,0 %; ! structure type macro PZREG$B_SUBTYPE = 11,0,8,0 %; ! structure subtype macro PZREG$L_FILL_2 = 12,0,32,0 %; ! spare field macro PZREG$Q_ALLOC_RTN = 16,0,0,1 %; literal PZREG$S_ALLOC_RTN = 8; ! pointer to allocation routine for poolzone macro PZREG$Q_DEALLOC_RTN = 24,0,0,1 %; literal PZREG$S_DEALLOC_RTN = 8; ! pointer to deallocation routine for poolzone macro PZREG$Q_ZONE_COUNT = 32,0,0,0 %; literal PZREG$S_ZONE_COUNT = 8; ! number of poolzones in this region macro PZREG$Q_FILL_3 = 40,0,0,0 %; literal PZREG$S_FILL_3 = 8; ! spare field macro PZREG$Q_RESERVED_1 = 48,0,0,0 %; literal PZREG$S_RESERVED_1 = 8; ! reserved fields macro PZREG$Q_RESERVED_2 = 56,0,0,0 %; literal PZREG$S_RESERVED_2 = 8; ! macro PZREG$Q_RESERVED_3 = 64,0,0,0 %; literal PZREG$S_RESERVED_3 = 8; ! macro PZREG$Q_RESERVED_4 = 72,0,0,0 %; literal PZREG$S_RESERVED_4 = 8; ! macro PZREG$R_ZONE = 80,0,0,0 %; literal PZREG$S_ZONE = 96; ! embedded first poolzone !*** MODULE $RADDEF *** ! + ! RAD Database - Structure containing information about a particular Resource Affinity Domain (RAD) ! within a system. This structure also serves as the base for other structures ! which are defined for each RAD. ! ! literal RAD$M_NO_MEMORY = %X'1'; literal RAD$M_NO_POOL = %X'2'; literal RAD$C_MAX_RADS = 32; ! Maximum number of RADs possible literal RAD$S_RAD = 120; macro RAD$L_RAD_ID = 0,0,32,0 %; ! The (0-based) RAD number represented by this structure macro RAD$L_FLAGS = 4,0,32,0 %; macro RAD$V_NO_MEMORY = 4,0,1,0 %; ! indicator if Rad has no memory macro RAD$V_NO_POOL = 4,1,1,0 %; ! indicator if Rad has no pool macro RAD$V_RESERVED = 4,2,30,0 %; literal RAD$S_RESERVED = 30; ! Reserved for future use macro RAD$W_MBO = 8,0,16,0 %; ! Part of 64-bit header. Must be 1 macro RAD$B_TYPE = 10,0,8,0 %; ! DYN$C_MISC macro RAD$B_SUBTYPE = 11,0,8,0 %; ! DYN$C_RAD macro RAD$L_CFG_HARD_ID = 12,0,32,1 %; ! "Hard" id of CFG node corresponding to or containing this RAD ! can go here. macro RAD$Q_SIZE = 16,0,0,0 %; literal RAD$S_SIZE = 8; ! Size of structure in bytes ! End of 64-bit header macro RAD$Q_CFG_HANDLE = 24,0,0,0 %; literal RAD$S_CFG_HANDLE = 8; ! Handle to find node corresponding to or ! containing this RAD. macro RAD$PQ_CPU_CBB = 32,0,0,1 %; literal RAD$S_CPU_CBB = 8; ! Pointer to bitmask of CPUs or 0 macro RAD$Q_CPU_MASK = 40,0,0,0 %; literal RAD$S_CPU_MASK = 8; ! Bitmask if CBB ptr is 0 macro RAD$PQ_DISTANCE_ARRAY = 48,0,0,1 %; literal RAD$S_DISTANCE_ARRAY = 8; ! Pointer to an array of "distances" to other RADs ! (Array length is RIH$L_MAX_RADS) macro RAD$PQ_PFN_ARRAY = 56,0,0,1 %; literal RAD$S_PFN_ARRAY = 8; ! Pointer to an array of PFN begin/end ! pairs on this RAD. 0 if n/a. (Use shift values from RIH) macro RAD$Q_PFN_ARRAY_LENGTH = 64,0,0,1 %; literal RAD$S_PFN_ARRAY_LENGTH = 8; ! How many PA pairs in the above list (in Wildfire, it would be 1) macro RAD$L_PCB_CACHE = 72,0,32,1 %; ! The per-RAD PCB cache macro RAD$L_SPARE1 = 76,0,32,1 %; ! Fill to quadword boundary macro RAD$Q_KPB_CACHE = 80,0,0,1 %; literal RAD$S_KPB_CACHE = 8; ! The per-RAD KPB cache macro RAD$PS_KPB_CACHE = 80,0,32,1 %; macro RAD$L_SEQUENCE = 84,0,32,0 %; macro RAD$Q_SPARE2 = 88,0,0,1 %; literal RAD$S_SPARE2 = 8; ! Extra space to debug with macro RAD$Q_SPARE3 = 96,0,0,1 %; literal RAD$S_SPARE3 = 8; macro RAD$L_ZEROED_LIST_COUNT = 104,0,32,1 %; ! Count of zeroed pages macro RAD$L_ZERO_LIST_HI_LIM = 108,0,32,1 %; ! Maxumum pages to zero for RAD macro RAD$L_BASE_RAD_1 = 112,0,32,1 %; ! Best ILM or CLM RAD to be used by this RAD macro RAD$L_BASE_RAD_2 = 116,0,32,1 %; ! Next best ILM or CLM RAD to be used by this RAD ! Add new pointers or info here literal RAD$C_LENGTH = 120; ! Length of RAD !*** MODULE $RBUNDEF *** ! + ! RBUN - SCS Resource bundle ! ! This structure contains a bundle of resources needed to do an I/O over ! a SCS port. There is a SCS port-independent resource portion that contains ! resources needed by all ports. There is also a port-dependent portion ! of the RBUN for port specific resources. ! - literal RBUN$C_MAX_SIZE = 65535; ! Maximum transfer supported by RBUNs is 64K-1 ! RBUN port extensions literal RBUN$C_NPORT_PAGES = 9; ! An unaligned 64K transfer can require the ! mapping of up to 9 Alpha 8KB port pages literal RBUN$C_TYP1_ARR_SIZE = 72; ! Size of Type 1 arrary given ! max transfer size literal RBUN$R_CRCTX = 64; ! CRCTX for this bundle literal RBUN$K_NPORT_LENGTH = 208; literal RBUN$C_NPORT_LENGTH = 208; literal RBUN$K_PEM_LENGTH = 52; literal RBUN$C_PEM_LENGTH = 52; literal RBUN$S_RBUN = 208; macro RBUN$L_LINK = 0,0,32,1 %; ! Singly linked list of RBUNs macro RBUN$L_RESERVED = 4,0,32,0 %; ! Unused longword macro RBUN$W_SIZE = 8,0,16,0 %; ! Size of RBUN in bytes macro RBUN$B_TYPE = 10,0,8,0 %; ! Structure Type for RBUN macro RBUN$B_SUBTYPE = 11,0,8,0 %; ! Structure Subtype for RBUN macro RBUN$L_RSPID = 12,0,32,0 %; ! RSPID macro RBUN$L_RDTE = 16,0,32,1 %; ! RDT entry address for the RSPID macro RBUN$L_RDT_SEQNUM = 20,0,32,0 %; ! RDT sequence number for this RSPID macro RBUN$L_MSG_BUF = 24,0,32,1 %; ! Message buffer macro RBUN$L_SCS_CREDITS = 28,0,32,0 %; ! SCS credits sent to remote system macro RBUN$L_BD_ADDR = 32,0,32,1 %; ! Buffer descriptor macro RBUN$L_PDT = 36,0,32,1 %; ! PDT of port this RBUN belongs to macro RBUN$L_RESERVED1 = 40,0,32,0 %; ! Unused macro RBUN$L_RESERVED2 = 44,0,32,0 %; ! Unused ! The Nport extension consists of two Type 1 pointer arrays big enough to support ! the maximum RBUN transfer size. The array is allocated twice as Type 1 arrays ! are not allowed to cross 8KB boundary. Note Type 1 arrays must be hex aligned as well. macro RBUN$L_TYP1_ADDR = 48,0,32,1 %; ! Virtual address of the Type 1 pointer array in TYP1_ARRAYS macro RBUN$L_FILL1 = 52,0,32,0 %; ! Keep quadword alignment macro RBUN$Q_TYP1_PHY_ADDR = 56,0,0,0 %; literal RBUN$S_TYP1_PHY_ADDR = 8; ! Physical address of the Type 1 pointer array in TYP1_ARRAYS ! NOTE: the following def for CRCTX assumes (CRCTX$K_LENGTH < RBUN$C_NPORT_PAGES*2*8) 96<144 ! this allows us to overlay a CRCTX structure when map registers are used instead of TYP1 arrays. macro RBUN$Q_TYP1_ARRAYS = 64,0,0,0 %; literal RBUN$S_TYP1_ARRAYS = 144; ! Two Type 1 pointer arrays ! PEDRIVER extensions to RBUN macro RBUN$L_VCRP = 48,0,32,1 %; !*** MODULE $RDIDEF *** ! ++ ! Rights Database Identifier Block definitions: This structure contains the ! RMS Internal File Identifiers (IFI's) and Internal Stream Identifiers ! (ISI's) for the rights database. This structure is allocated from the ! process allocation region pool. ! -- literal RDI$K_ISI_MAX = 10; ! Maximum number of concurrent record streams literal RDI$M_READ_CHECK = %X'1'; literal RDI$M_READ_ACCESS = %X'2'; literal RDI$S_RDIDEF = 64; literal RDI$S_RDI = 64; macro RDI$L_SIZE = 0,0,32,0 %; ! Size of allocated block macro RDI$L_IFI_READ = 4,0,32,0 %; ! Internal File Identifier for read operations macro RDI$L_IFI_WRITE = 8,0,32,0 %; ! Internal File Identifier for write operations macro RDI$L_READ_CHANNEL = 12,0,32,0 %; ! Holds channel used for reading RDB. macro RDI$L_FLAGS = 16,0,32,0 %; ! Flags longword macro RDI$V_READ_CHECK = 16,0,1,0 %; ! Set if read access checked macro RDI$V_READ_ACCESS = 16,1,1,0 %; ! Set if there is read access to RDB macro RDI$L_ISI_VEC = 20,0,0,0 %; literal RDI$S_ISI_VEC = 44; ! Internal Stream Identifier vector !*** MODULE $RDPDEF *** ! ! REMOTE DEVICE PROTOCOL DEFINITIONS ! literal RDP$K_HEADERLEN = 10; ! HEADER LENGTH literal RDP$C_HEADERLEN = 10; ! HEADER LENGTH literal RDP$S_RDPHDR = 10; macro RDP$W_OPCODE = 0,0,16,0 %; ! OPERATION CODE macro RDP$W_MOD = 2,0,16,0 %; ! OPERATION CODE MODIFIERS macro RDP$L_REFID = 4,0,32,0 %; ! REFERENCE ID macro RDP$W_UNIT = 8,0,16,0 %; ! DEVICE UNIT NUMBER macro RDP$W_SIZE = 8,0,16,0 %; ! SIZE OF MESSAGE (ACP/DRIVER USE ONLY) literal RDP$C_ATTN = -1; ! ATTENTION literal RDP$C_END = -2; ! I/O REQUEST COMPLETE literal RDP$C_LOG = -3; ! ERROR LOG literal RDP$S_RDPDEF = 34; ! Old size name - synonym literal RDP$S_RDP = 34; macro RDP$L_PARAM1 = 10,0,32,0 %; ! PARAMETER 1 macro RDP$L_PARAM2 = 14,0,32,0 %; ! PARAMETER 2 macro RDP$L_PARAM3 = 18,0,32,0 %; ! PARAMETER 3 macro RDP$L_PARAM4 = 22,0,32,0 %; ! PARAMETER 4 macro RDP$L_PARAM5 = 26,0,32,0 %; ! PARAMETER 5 macro RDP$L_PARAM6 = 30,0,32,0 %; ! PARAMETER 6 ! ! RESPONSE FROM REMOTE PACKET DEFINITIONS ! ! RESPONSE PACKET OPCODES literal RDP$S_RDPDEF1 = 18; ! Old size name - synonym literal RDP$S_RDP1 = 18; macro RDP$Q_STATUS = 10,0,0,0 %; literal RDP$S_STATUS = 8; ! END PACKET I/O STATUS ! ! TERMINAL SPECIFIC PARAMETER DEFINITIONS ! ! READ/WRITE REQUEST literal RDP$S_RDPDEF2 = 19; ! Old size name - synonym literal RDP$S_RDP2 = 19; macro RDP$L_TT_BCNT = 10,0,32,0 %; ! BYTE COUNT macro RDP$L_TT_CARCON = 14,0,32,0 %; ! WRITE CARRIAGE CONTROL macro RDP$L_TT_TIMOUT = 14,0,32,0 %; ! READ TIMEOUT macro RDP$T_TT_WDATA = 18,0,8,0 %; ! WRITE DATA macro RDP$T_TT_TERM = 18,0,8,0 %; ! BYTE OF SIZE + TERMINATOR MASK ! WORD OF SIZE + PROMPT STRING ! SET MODE/CHARACTERISTICS REQUEST literal RDP$S_RDPDEF3 = 34; ! Old size name - synonym literal RDP$S_RDP3 = 34; macro RDP$Q_TT_CHAR = 10,0,0,0 %; literal RDP$S_TT_CHAR = 8; ! CHARACTERISTICS macro RDP$L_TT_ASTPRM = 10,0,32,0 %; ! AST PARAMETER macro RDP$L_TT_SPEED = 18,0,32,0 %; ! LINE SPEED macro RDP$L_TT_FILL = 22,0,32,0 %; ! FILL SPECIFIER macro RDP$L_TT_PARITY = 26,0,32,0 %; ! PARITY FLAGS macro RDP$L_TT_CHAR2 = 30,0,32,0 %; ! Remaining longword of characters ! READ REQUEST END PACKET literal RDP$S_RDPDEF4 = 19; ! Old size name - synonym literal RDP$S_RDP4 = 19; macro RDP$T_TT_RDATA = 18,0,8,0 %; ! WORD OF SIZE + READ DATA ! SENSE MODE/CHARACTERISTICS END PACKET literal RDP$S_RDPDEF5 = 30; ! Old size name - synonym literal RDP$S_RDP5 = 30; macro RDP$Q_TT_SCHAR = 18,0,0,0 %; literal RDP$S_TT_SCHAR = 8; ! SENSED CHARACTERISTICS macro RDP$L_TT_SCHAR2 = 26,0,32,0 %; ! Additional longword of characters ! Broadcast message attention packet literal RDP$C_TT_BRDNAME = 16; ! Size of name field literal RDP$S_RDPDEF6 = 34; ! Old size name - synonym literal RDP$S_RDP6 = 34; macro RDP$W_TT_BRDTOTSIZE = 10,0,16,0 %; ! Total size of data macro RDP$W_TT_BRDMSG = 12,0,16,0 %; ! Message code macro RDP$W_TT_BRDUNIT = 14,0,16,0 %; ! Unit number macro RDP$T_TT_BRDNAME = 16,0,0,0 %; literal RDP$S_TT_BRDNAME = 16; ! Device name as counted string macro RDP$W_TT_BRDTXTSIZE = 32,0,16,0 %; ! Count for message text macro RDP$T_TT_BRDTEXT = 34,0,0,0 %; ! Message text start ! Out of band attention packet literal RDP$C_TT_UNSOL = 0; ! UNSOLICITED DATA literal RDP$C_TT_HANGUP = 1; ! MODEM HANGUP literal RDP$C_TT_CTRLC = 2; ! CONTROL/C literal RDP$C_TT_CTRLY = 3; ! CONTROL/Y literal RDP$C_TT_STARTRCV = 4; ! Start a receive to the net literal RDP$C_TT_BRDCST = 5; ! Broadcast message for mailbox literal RDP$C_TT_OUTBAND = 6; ! Out of band AST literal RDP$S_RDPDEF7 = 11; ! Old size name - synonym literal RDP$S_RDP7 = 11; macro RDP$B_TT_OUTBAND = 10,0,8,0 %; ! Out of band character ! ATTENTION PACKET MODIFIERS !*** MODULE $RBFDEF *** ! ! Remote buffer as stored in dynamic memory ! ! This structure must be identical to the above structure except ! for the header, which is the header for a buffered io buffer. ! ! ! Buffered io buffer header ! literal RBF$K_HEADERLEN = 24; ! HEADER LENGTH literal RBF$C_HEADERLEN = 24; ! HEADER LENGTH literal RBF$S_RBFHDR = 24; macro RBF$L_MSGDAT = 0,0,32,1 %; ! Address of message data macro RBF$L_USRBFR = 4,0,32,1 %; ! User buffer address macro RBF$W_SIZE = 8,0,16,0 %; ! Size of structure macro RBF$B_TYPE = 10,0,8,0 %; ! Type of structure, DYN$C_BUFIO macro RBF$B_SPARE = 11,0,8,0 %; ! Alignment macro RBF$W_DATSIZE = 12,0,16,0 %; ! Data size macro RBF$W_OPCODE = 14,0,16,0 %; ! OPERATION CODE macro RBF$W_MOD = 16,0,16,0 %; ! OPERATION CODE MODIFIERS macro RBF$L_REFID = 18,0,32,0 %; ! REFERENCE ID macro RBF$W_UNIT = 22,0,16,0 %; ! DEVICE UNIT NUMBER ! S SIZE,0,W /*SIZE OF MESSAGE (ACP/DRIVER USE ONLY) literal RBF$C_ATTN = -1; ! ATTENTION literal RBF$C_END = -2; ! I/O REQUEST COMPLETE literal RBF$C_LOG = -3; ! ERROR LOG literal RBF$S_RBFDEF = 48; ! Old size name - synonym literal RBF$S_RBF = 48; ! ! End of header ! macro RBF$L_PARAM1 = 24,0,32,0 %; ! PARAMETER 1 macro RBF$L_PARAM2 = 28,0,32,0 %; ! PARAMETER 2 macro RBF$L_PARAM3 = 32,0,32,0 %; ! PARAMETER 3 macro RBF$L_PARAM4 = 36,0,32,0 %; ! PARAMETER 4 macro RBF$L_PARAM5 = 40,0,32,0 %; ! PARAMETER 5 macro RBF$L_PARAM6 = 44,0,32,0 %; ! PARAMETER 6 ! ! RESPONSE FROM REMOTE PACKET DEFINITIONS ! ! RESPONSE PACKET OPCODES literal RBF$S_RBFDEF1 = 32; ! Old size name - synonym literal RBF$S_RBF1 = 32; macro RBF$Q_STATUS = 24,0,0,0 %; literal RBF$S_STATUS = 8; ! END PACKET I/O STATUS ! ! TERMINAL SPECIFIC PARAMETER DEFINITIONS ! ! READ/WRITE REQUEST literal RBF$S_RBFDEF2 = 33; ! Old size name - synonym literal RBF$S_RBF2 = 33; macro RBF$L_TT_BCNT = 24,0,32,0 %; ! BYTE COUNT macro RBF$L_TT_CARCON = 28,0,32,0 %; ! WRITE CARRIAGE CONTROL macro RBF$L_TT_TIMOUT = 28,0,32,0 %; ! READ TIMEOUT macro RBF$T_TT_WDATA = 32,0,8,0 %; ! WRITE DATA macro RBF$T_TT_TERM = 32,0,8,0 %; ! BYTE OF SIZE + TERMINATOR MASK ! WORD OF SIZE + PROMPT STRING ! SET MODE/CHARACTERISTICS REQUEST literal RBF$S_RBFDEF3 = 48; ! Old size name - synonym literal RBF$S_RBF3 = 48; macro RBF$Q_TT_CHAR = 24,0,0,0 %; literal RBF$S_TT_CHAR = 8; ! CHARACTERISTICS macro RBF$L_TT_ASTPRM = 24,0,32,0 %; ! AST PARAMETER macro RBF$L_TT_SPEED = 32,0,32,0 %; ! LINE SPEED macro RBF$L_TT_FILL = 36,0,32,0 %; ! FILL SPECIFIER macro RBF$L_TT_PARITY = 40,0,32,0 %; ! PARITY FLAGS macro RBF$L_TT_CHAR2 = 44,0,32,0 %; ! Another longword of characters ! READ REQUEST END PACKET literal RBF$S_RBFDEF4 = 33; ! Old size name - synonym literal RBF$S_RBF4 = 33; macro RBF$T_TT_RDATA = 32,0,8,0 %; ! WORD OF SIZE + READ DATA ! SENSE MODE/CHARACTERISTICS END PACKET literal RBF$S_RBFDEF5 = 44; ! Old size name - synonym literal RBF$S_RBF5 = 44; macro RBF$Q_TT_SCHAR = 32,0,0,0 %; literal RBF$S_TT_SCHAR = 8; ! SENSED CHARACTERISTICS macro RBF$L_TT_SCHAR2 = 40,0,32,0 %; ! Another longword of characters ! Broadcast message attention packet literal RBF$C_TT_BRDNAME = 16; ! Size of name field literal RBF$S_RBFDEF6 = 48; ! Old size name - synonym literal RBF$S_RBF6 = 48; macro RBF$W_TT_BRDTOTSIZE = 24,0,16,0 %; ! Total size of data macro RBF$W_TT_BRDMSG = 26,0,16,0 %; ! Message code macro RBF$W_TT_BRDUNIT = 28,0,16,0 %; ! Unit number macro RBF$T_TT_BRDNAME = 30,0,0,0 %; literal RBF$S_TT_BRDNAME = 16; ! Device name as counted string macro RBF$W_TT_BRDTXTSIZE = 46,0,16,0 %; ! Count for message text macro RBF$T_TT_BRDTEXT = 48,0,0,0 %; ! Message text start ! Out of band attention packet literal RBF$C_TT_UNSOL = 0; ! UNSOLICITED DATA literal RBF$C_TT_HANGUP = 1; ! MODEM HANGUP literal RBF$C_TT_CTRLC = 2; ! CONTROL/C literal RBF$C_TT_CTRLY = 3; ! CONTROL/Y literal RBF$C_TT_STARTRCV = 4; ! Start a receive to the net literal RBF$C_TT_BRDCST = 5; ! Broadcast message for mailbox literal RBF$C_TT_OUTBAND = 6; ! Out of band AST literal RBF$S_RBFDEF7 = 25; ! Old size name - synonym literal RBF$S_RBF7 = 25; macro RBF$B_TT_OUTBAND = 24,0,8,0 %; ! Out of band character ! ATTENTION PACKET MODIFIERS !*** MODULE $RCTDEF *** ! + ! RCT - Replacement and Caching Table sector !0 layout. ! The RCT is a structure residing on disks controlled by MSCP ! speaking disk controllers. The RCT is maintained by the intelligent ! controllers and the disk class driver. The disk class driver mainly ! gets involved in RCT manipulations during host initiated bad ! block replacement. literal RCT$M_WB = %X'1'; literal RCT$M_FE = %X'80'; literal RCT$M_BR = %X'2000'; literal RCT$M_RP2 = %X'4000'; literal RCT$M_RP1 = %X'8000'; literal RCT$M_LBN = %X'FFFFFFF'; literal RCT$M_CODE = %X'F0000000'; literal RCT$M_NONPRIME = %X'10000000'; literal RCT$M_ALLOCATED = %X'20000000'; literal RCT$M_UNUSABLE = %X'40000000'; literal RCT$M_NULL = %X'80000000'; literal RCT$K_EMPTY = 0; ! Unallocated (empty) replacement block literal RCT$K_ALOCPRIME = 2; ! Allocated replace blk - primary RBN literal RCT$K_ALOCNONP = 3; ! Allocated replace blk - non-primary RBN literal RCT$K_UNUSABLE = 4; ! Unusable replacement block literal RCT$K_ALTUNUSE = 5; ! Alternate unusable replacement block literal RCT$K_NULL = 8; ! Null entry - no corresponding RBN sector literal RCT$S_RCTDEF = 44; ! Old size name - synonym literal RCT$S_RCT = 44; macro RCT$Q_VOLSER = 0,0,0,0 %; literal RCT$S_VOLSER = 8; ! Volume serial number macro RCT$W_FLAGS = 8,0,16,0 %; ! Flags word macro RCT$V_WB = 8,0,1,0 %; ! Write back caching in use macro RCT$V_FE = 8,7,1,0 %; ! Forced Error flag for block being replaced macro RCT$V_BR = 8,13,1,0 %; ! Replacement caused by Bad RBN macro RCT$V_RP2 = 8,14,1,0 %; ! Replacement in Progress phase 2 macro RCT$V_RP1 = 8,15,1,0 %; ! Replacement in Progress phase 1 macro RCT$L_LBN = 12,0,32,0 %; ! LBN curently being replaced. macro RCT$L_RBN = 16,0,32,0 %; ! RBN allocated to replace LBN macro RCT$L_BAD_RBN = 20,0,32,0 %; ! If BR flag, RBN of bad replacement block macro RCT$Q_WB_CTRL = 24,0,0,0 %; literal RCT$S_WB_CTRL = 8; ! Serial ! of last controller doing Write back macro RCT$L_WB_INCAR = 32,0,32,0 %; ! Write back incarnation ! macro RCT$Q_INCARTIME = 36,0,0,0 %; literal RCT$S_INCARTIME = 8; ! Date-time of last update of incarnation no. ! ! Structure of a Replacement Block Descriptor ! macro RCT$V_LBN = 36,0,28,0 %; literal RCT$S_LBN = 28; ! Space for LBN replaced by this RBN macro RCT$V_CODE = 36,28,4,0 %; literal RCT$S_CODE = 4; ! Describes how this descriptor being used macro RCT$V_NONPRIME = 36,28,1,0 %; ! Set implies allocated, but not prime RBN macro RCT$V_ALLOCATED = 36,29,1,0 %; ! This RBN allocated macro RCT$V_UNUSABLE = 36,30,1,0 %; ! This RBN unusable macro RCT$V_NULL = 36,31,1,0 %; ! This marks a NULL entry ! Values of CODE !*** MODULE $RDABDEF *** literal RDAB$M_DEFAULT = %X'8'; literal RDAB$K_LENGTH = 24; ! Length of RDAB literal RDAB$C_LENGTH = 24; ! Length of RDAB literal RDAB$S_RDABDEF = 24; literal RDAB$S_RDAB = 24; macro RDAB$L_RDDB = 0,0,32,1 %; ! pointer to the RDDB macro RDAB$L_MAC = 4,0,32,0 %; ! spare longword macro RDAB$L_SEQ = 8,0,32,0 %; ! RDAB sequence number macro RDAB$L_ACCESS = 12,0,32,0 %; ! access mask macro RDAB$V_DEFAULT = 12,3,1,0 %; ! RADB created as default macro RDAB$L_ACMODE = 16,0,32,0 %; ! access mode (RSDM_ID) macro RDAB$L_DOM_ACMODE = 20,0,32,0 %; ! domain access mode !*** MODULE $RDDBDEF *** literal RDDB$M_KEEP = %X'1'; literal RDDB$M_NO_PROFILE = %X'2'; literal RDDB$K_LENGTH = 36; ! Length of RDDB literal RDDB$C_LENGTH = 36; ! Length of RDDB literal RDDB$S_RDDBDEF = 36; literal RDDB$S_RDDB = 36; macro RDDB$L_FLINK = 0,0,32,1 %; ! RDDB queue forward link macro RDDB$L_BLINK = 4,0,32,1 %; ! RDDB queue backward link macro RDDB$L_SIZE = 8,0,32,0 %; ! Size in bytes macro RDDB$L_TYPE = 12,0,32,0 %; ! Structure type code for RDDB macro RDDB$L_FLAGS = 16,0,32,0 %; macro RDDB$V_KEEP = 16,0,1,0 %; ! Domain block is deallocated if ! refcnt goes to 0 and KEEP not set ! KEEP is set on successful access. macro RDDB$V_NO_PROFILE = 16,1,1,0 %; ! Domain profile being instantiated macro RDDB$L_GROUP = 20,0,32,0 %; ! domain number macro RDDB$L_ORB = 24,0,32,1 %; ! Pointer to the ORB macro RDDB$L_LOCKID = 28,0,32,0 %; ! Lock id value (MAC) macro RDDB$L_REFCNT = 32,0,32,0 %; ! Count of RDs + root locks !*** MODULE $RDEDEF *** ! ! Region Descriptor Definitions. The region descriptor entry contains ! memory management data for a region of virtual address space. ! ! *** WARNING *** ! Region Descriptor Entries are embedded into the PHD. Any modification ! to this definition file may cause an update in PHDDEF.SDL as well. ! *************** literal REGPRT$M_OWNER_MODE = %X'F'; literal REGPRT$M_CREATE_MODE = %X'F0'; literal REGPRT$M_RESERVED_PROT_BITS = %X'FFFFFF00'; literal REGPRT$S_REGION_PROT = 4; macro REGPRT$L_REGION_PROT = 0,0,32,1 %; macro REGPRT$V_OWNER_MODE = 0,0,4,0 %; literal REGPRT$S_OWNER_MODE = 4; ! Region owner mode macro REGPRT$V_CREATE_MODE = 0,4,4,0 %; literal REGPRT$S_CREATE_MODE = 4; ! Region create mode macro REGPRT$V_RESERVED_PROT_BITS = 0,8,24,0 %; literal RDE$M_DESCEND = %X'1'; literal RDE$M_P0_SPACE = %X'2'; literal RDE$M_P1_SPACE = %X'4'; literal RDE$M_PERMANENT = %X'8'; literal RDE$M_EXPAND_ON_ACCVIO = %X'10'; literal RDE$M_NO_CLONE = %X'20'; literal RDE$M_SHARED_PTS = %X'40'; literal RDE$M_RESERVED_FLAGS = %X'FFFFFF80'; literal RDE$C_LENGTH = 56; ! Length of RDE literal RDE$S_RDE = 56; macro RDE$PS_VA_LIST_FLINK = 0,0,32,1 %; ! Flink for VA list of RDEs macro RDE$PS_VA_LIST_BLINK = 4,0,32,1 %; ! Blink for VA list of RDEs macro RDE$W_SIZE = 8,0,16,0 %; ! Structure size (including RDE) macro RDE$B_TYPE = 10,0,8,0 %; ! Dynamic structure type macro RDE$B_SUBTYPE = 11,0,8,0 %; ! Dynamic structore subtype macro RDE$PS_TABLE_LINK = 12,0,32,1 %; ! Pointer to next RDE in table macro RDE$L_FLAGS = 16,0,32,0 %; ! FLAGS longword macro RDE$V_DESCEND = 16,0,1,0 %; ! Region is descending macro RDE$V_P0_SPACE = 16,1,1,0 %; ! Region is in P0 space macro RDE$V_P1_SPACE = 16,2,1,0 %; ! Region is in P1 space macro RDE$V_PERMANENT = 16,3,1,0 %; ! Region is permanent macro RDE$V_EXPAND_ON_ACCVIO = 16,4,1,0 %; ! Expand within region on accvio macro RDE$V_NO_CLONE = 16,5,1,0 %; ! Do not clone this region macro RDE$V_SHARED_PTS = 16,6,1,0 %; ! Region is a shared PT region macro RDE$V_RESERVED_FLAGS = 16,7,25,0 %; literal RDE$S_RESERVED_FLAGS = 25; macro RDE$R_REGPROT = 20,0,32,0 %; literal RDE$S_REGPROT = 4; ! Region protection macro RDE$Q_REGION_ID = 24,0,0,0 %; literal RDE$S_REGION_ID = 8; ! Id of region macro RDE$PQ_START_VA = 32,0,0,1 %; literal RDE$S_START_VA = 8; ! Lowest address in region macro RDE$PS_START_VA = 32,0,32,1 %; ! Lowest address in 32-bit region macro RDE$Q_REGION_SIZE = 40,0,0,0 %; literal RDE$S_REGION_SIZE = 8; ! Size of region macro RDE$L_REGION_SIZE = 40,0,32,0 %; ! Size of 32-bit region macro RDE$PQ_FIRST_FREE_VA = 48,0,0,1 %; literal RDE$S_FIRST_FREE_VA = 8; ! First free VA in region macro RDE$PS_FIRST_FREE_VA = 48,0,32,1 %; ! First free VA in 32-bit region literal RDE$C_MIN_USER_ID = 16; ! Minimum region id for user defined regions literal RDE$C_REGION_TABLE_SIZE = 16; ! Number of list headers in region table ! Internal functions values for $lookup_rde_va function literal __LOOKUP_RDE_EXACT = 0; literal __LOOKUP_RDE_HIGHER = 1; !*** MODULE $RDPBDEF *** literal RDPB$K_LENGTH = 172; ! Length of RDPB literal RDPB$C_LENGTH = 172; ! Length of RDPB literal RDPB$C_NUM = 6; ! # of RDABs/RDPB literal RDPB$S_RDPBDEF = 172; literal RDPB$S_RDPB = 172; macro RDPB$L_FLINK = 0,0,32,1 %; ! RDPB queue forward link macro RDPB$L_BLINK = 4,0,32,1 %; ! RDPB queue backward link macro RDPB$W_SIZE = 8,0,16,0 %; ! Size in bytes macro RDPB$B_TYPE = 10,0,8,0 %; ! Structure type code for RDPB macro RDPB$L_NUM = 12,0,32,0 %; ! Number of RDABs per RDPB macro RDPB$L_DEFAULT_RDAB = 16,0,32,1 %; ! address of RDAB for default domain macro RDPB$L_DEFAULT_DOMAIN = 20,0,32,0 %; ! domain number for default domain macro RDPB$L_DEFAULT_ID = 24,0,32,0 %; ! RDAB index for default domain ! + ! Next 24*6 bytes are for the 6 RDAB fields contained in the RDPB ! - macro RDPB$L_RDAB = 28,0,0,1 %; literal RDPB$S_RDAB = 144; ! space for 6 RDABs !*** MODULE $RDTDEF *** ! + ! RDT - SCS RESPONSE DESCRIPTOR TABLE ! ! ONE RESPONSE DESCRIPTOR (RD) IS ALLOCATED FOR EACH SCS MESSAGE ! SENT FOR WHICH THE SENDER EXPECTS A MATCHING RESPONSE. ! - literal RDT$C_LENGTH = 40; ! LENGTH OF NEG PORTION OF STRUCTURE ! literal RDT$S_RDTDEF = 41; literal RDT$S_RDT = 41; macro RDT$B_SCS_MAINT_BLOCK = -40,0,0,0 %; literal RDT$S_SCS_MAINT_BLOCK = 16; ! Add a Maintenance block to the CDT ! which must be quadword aligned macro RDT$L_WAITFL = -24,0,32,1 %; ! RD WAIT QUEUE FWD LINK macro RDT$L_WAITBL = -20,0,32,1 %; ! RD WAIT QUEUE BACK LINK macro RDT$W_SIZE = -16,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro RDT$B_TYPE = -14,0,8,0 %; ! SCS STURCTURE TYPE macro RDT$B_SUBTYP = -13,0,8,0 %; ! SCS STRUCT SUBTYPE FOR RDT macro RDT$L_FREERD = -12,0,32,1 %; ! ADDR OF 1ST FREE RD macro RDT$L_MAXRDIDX = -8,0,32,0 %; ! MAXIMUM ! OF DESCRIPTORS macro RDT$L_QRDT_CNT = -4,0,32,0 %; ! Count of stalls because of no response ID's literal CRDT$S_CRDTDEF = 40; literal CRDT$S_CRDT = 40; macro CRDT$B_SCS_MAINT_BLOCK = 0,0,0,0 %; literal CRDT$S_SCS_MAINT_BLOCK = 16; ! Add a Maintenance block to the CDT ! which must be quadword aligned macro CRDT$L_WAITFL = 16,0,32,1 %; ! RD WAIT QUEUE FWD LINK macro CRDT$L_WAITBL = 20,0,32,1 %; ! RD WAIT QUEUE BACK LINK macro CRDT$W_SIZE = 24,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro CRDT$B_TYPE = 26,0,8,0 %; ! SCS STURCTURE TYPE macro CRDT$B_SUBTYP = 27,0,8,0 %; ! SCS STRUCT SUBTYPE FOR RDT macro CRDT$L_FREERD = 28,0,32,1 %; ! ADDR OF 1ST FREE RD macro CRDT$L_MAXRDIDX = 32,0,32,0 %; ! MAXIMUM ! OF DESCRIPTORS macro CRDT$L_QRDT_CNT = 36,0,32,0 %; ! Count of stalls because of no response ID's !*** MODULE $RDDEF *** ! + ! RD - SCS RESPONSE DESCRIPTOR FORMAT ! - literal RD$K_LENGTH = 8; ! LENGTH OF RD literal RD$C_LENGTH = 8; ! LENGTH OF RD literal RD$S_RDDEF = 8; literal RD$S_SCS_RD = 8; macro RD$L_CDRP = 0,0,32,1 %; ! ADDR OF ASSOC CDRP OR ! OR OTHER CONTEXT BLOCK macro RD$L_LINK = 0,0,32,1 %; ! OR LINK TO NEXT FREE RD macro RD$W_STATE = 4,0,16,0 %; ! RD STATE FLAGS macro RD$V_BUSY = 4,0,1,0 %; ! ALLOCATED IF SET macro RD$V_PERM = 4,1,1,0 %; ! PERMANENTLY ALLOCATED RD IF SET macro RD$W_SEQNUM = 6,0,16,0 %; ! SEQUENCE NUMBER OF RD !*** MODULE $RELDEF *** ! ! DEFINE FIXUP RECORD ! literal REL$K_BITMAP = 8; ! OFFSET TO BITMAP literal REL$S_RELREC = 8; macro REL$L_COUNT = 0,0,32,0 %; ! SIZE OF BITMAP macro REL$L_ADDR = 4,0,32,0 %; ! ADDRESS IF IMAGE SECTION macro REL$T_BITMAP = 8,0,0,0 %; ! THE BITMAP !*** MODULE $RGBDEF *** ! + ! RGB - Range Block ! ! Range Block is a user defined structure passed by reference to the Lock ! Manager $enq, $enqw and $deq system system services via the optional [RANGE] ! argument. ! The Range Block specifies a relative start and length of a resource range ! to be locked, converted or unlocked. ! - literal RGB$C_LENGTH = 16; ! LENGTH OF FIXED PART literal RGB$K_LENGTH = 16; ! LENGTH OF FIXED PART literal RGB$K_MAXRANGE = -1; ! Maximum range of resource literal RGB$S_RGBDEF = 16; literal RGB$S_RGB = 16; macro RGB$Q_START = 0,0,0,0 %; literal RGB$S_START = 8; ! relative start of range to lock macro RGB$Q_LENGTH = 8,0,0,0 %; literal RGB$S_LENGTH = 8; ! length of range to lock !*** MODULE $RIGHTSDEF *** ! ! RightsList structure definitions ! literal ID$K_LENGTH = 8; ! Length of ID$ structure literal ID$S_ID = 8; macro ID$L_VALUE = 0,0,32,0 %; ! Binary identifier value macro ID$L_FLAGS = 4,0,32,0 %; ! Flags associated with identifier literal RIGHTS$S_RIGHTS = 48; macro RIGHTS$L_FLINK = 0,0,32,1 %; ! Standard listhead forward link macro RIGHTS$L_BLINK = 4,0,32,1 %; ! Standard listhead backward link macro RIGHTS$W_SIZE = 8,0,16,0 %; ! Standard structure size, in bytes macro RIGHTS$B_TYPE = 10,0,8,0 %; ! Standard type code for RIGHTS (DYN$C_SECURITY) macro RIGHTS$B_SUBTYPE = 11,0,8,0 %; ! Standard subtype code (DYN$C_SECURITY_RIGHTS) macro RIGHTS$L_DEBUG_FLINK = 12,0,32,1 %; ! Forward link to next Rightslist in system (DEBUG) macro RIGHTS$L_DEBUG_BLINK = 16,0,32,1 %; ! Backward link to next Rightslist in system (DEBUG) macro RIGHTS$L_DEBUG_PID = 20,0,32,0 %; ! PID of process which allocated this PCB (DEBUG) macro RIGHTS$L_REFCOUNT = 24,0,32,0 %; ! macro RIGHTS$L_ID_COUNT = 28,0,32,0 %; ! Number of identifiers that array can hold macro RIGHTS$L_ID_USED = 32,0,32,0 %; ! Number of identifiers currently stored in array ! ! The following two locations must be kept adjacent, as they are ! treated as a descriptor that points at the rights data ! macro RIGHTS$L_ID_LENGTH = 36,0,32,0 %; ! Number of bytes taken up by ID_USED macro RIGHTS$A_ID_ARRAY = 40,0,32,1 %; ! Address of identifier array macro RIGHTS$T_IDENTIFIERS = 44,0,0,0 %; ! Offset to first rights entry literal RIGHTS$K_LENGTH = 48; ! Length of RIGHTS$ structure ! ! The following constants are assigned values chosen for no ! reason other than they seemed appropriate at the time. ! literal RIGHTS$K_INITIAL_IDENTIFIERS = 16; ! Initial allocation literal RIGHTS$K_COUNT_IDENTIFIERS = 64; ! expantion allocation literal RIGHTS$K_MAX_IDENTIFIERS = 528; !*** MODULE $RIHDEF *** ! + ! RAD Information Header - Structure containing information about the Resource Affinity Domain (RAD) ! characteristics of the current system. This is used for NUMA support. ! ! literal RIH$M_RAD_ENABLE = %X'1'; literal RIH$M_AFFINITY = %X'2'; literal RIH$M_SYSTEM_REPL = %X'4'; literal RIH$M_COPY_SOFT_FAULT = %X'8'; literal RIH$M_SPECIAL = %X'10'; literal RIH$M_FORCE_RAD = %X'20'; literal RIH$M_RAD_POOL = %X'40'; literal RIH$M_PLATFORM_DECISION = %X'80'; literal RIH$M_PROCESS_ALLOC = %X'30000'; literal RIH$M_SWAPPER_ALLOC = %X'C0000'; literal RIH$M_GLOBAL_ALLOC = %X'300000'; literal RIH$M_SYSTEM_ALLOC = %X'C00000'; literal RIH$M_SKIP_COUNT = %X'F000000'; literal RIH$C_CPU_MASK_OFFSET = 64; literal RIH$C_CPU_MASK_BYTES = 128; ! CPU Mask size in bytes literal RIH$C_CPU_MASK_QUADS = 16; ! CPU Mask size in bytes literal RIH$C_CPU_MASK_SHIFT = 7; ! Shift value to index to a RAD's CPU Mask literal RIH$C_MAX_RAD_COUNT = 32; ! Maximum supported RADs literal RIH$S_RIH = 4160; macro RIH$L_MAX_RADS = 0,0,32,0 %; ! The maximum RADs possible on system macro RIH$L_FLAGS = 4,0,32,0 %; ! Copy of RAD_SUPPORT sysgen parameter macro RIH$V_RAD_ENABLE = 4,0,1,0 %; ! Enable RAD support macro RIH$V_AFFINITY = 4,1,1,0 %; ! Enable Soft RAD affinity support macro RIH$V_SYSTEM_REPL = 4,2,1,0 %; ! Enable read-only system space replication macro RIH$V_COPY_SOFT_FAULT = 4,3,1,0 %; ! Enable copy on soft fault macro RIH$V_SPECIAL = 4,4,1,0 %; ! Enable special allocation flags macro RIH$V_FORCE_RAD = 4,5,1,0 %; ! Debug: RAD support software on non-RAD machines macro RIH$V_RAD_POOL = 4,6,1,0 %; ! Enable per-RAD non-paged pool macro RIH$V_PLATFORM_DECISION = 4,7,1,0 %; ! if set platform code will decide if RAD is on/off macro RIH$V_RESERVED_2 = 4,8,8,0 %; literal RIH$S_RESERVED_2 = 8; ! Reserved for future use macro RIH$V_PROCESS_ALLOC = 4,16,2,0 %; literal RIH$S_PROCESS_ALLOC = 2; ! Process page allocation macro RIH$V_SWAPPER_ALLOC = 4,18,2,0 %; literal RIH$S_SWAPPER_ALLOC = 2; ! Swapper page allocation macro RIH$V_GLOBAL_ALLOC = 4,20,2,0 %; literal RIH$S_GLOBAL_ALLOC = 2; ! Global page allocation macro RIH$V_SYSTEM_ALLOC = 4,22,2,0 %; literal RIH$S_SYSTEM_ALLOC = 2; ! System space page allocation macro RIH$V_SKIP_COUNT = 4,24,4,0 %; literal RIH$S_SKIP_COUNT = 4; ! How many times scheduler skips a process before going off-RAD ! The actual count is 2**SKIP_COUNT macro RIH$V_RESERVED_3 = 4,28,4,0 %; literal RIH$S_RESERVED_3 = 4; ! Reserved for future use macro RIH$W_SIZE = 8,0,16,0 %; ! Size of structure in bytes macro RIH$B_TYPE = 10,0,8,0 %; ! DYN$C_MISC macro RIH$B_SUBTYPE = 11,0,8,0 %; ! DYN$C_RIH macro RIH$L_CPU_SHIFT_VALUE = 12,0,32,1 %; ! Shift from CPU ID to RAD, -1 if it does not work that way macro RIH$L_PFN_SHIFT_VALUE = 16,0,32,1 %; ! Shift from PFN to RAD, -1 if it does not work that way macro RIH$L_PA_SHIFT_VALUE = 20,0,32,1 %; ! Shift from PA to RAD, -1 if it does not work that way macro RIH$L_BASE_RAD = 24,0,32,0 %; ! The RAD that contains SYS$BASE_IMAGE et al macro RIH$L_CPU_MASK_OFFSET = 28,0,32,0 %; ! Offset from beginning of RIH to CPU_MASK macro RIH$PQ_GBLSEC_RADS = 32,0,0,1 %; literal RIH$S_GBLSEC_RADS = 8; ! Pointer to global section RAD hint array macro RIH$L_PA_TO_RAD = 40,0,32,1 %; ! pointer to routine converting PA to RAD id macro RIH$L_CPU_TO_RAD = 44,0,32,1 %; ! pointer to routine converting CPU id to RAD id macro RIH$L_RAD_TO_PA_RANGE = 48,0,32,1 %; ! pointer to routine returning a PA range for a given RAD id macro RIH$L_ALT_BASE_RAD = 52,0,32,1 %; ! Will contain a RAD of equal cost to the base RAD if present (IA64) macro RIH$R_CPU_ARRAY = 64,0,0,0 %; literal RIH$S_CPU_ARRAY = 4096; macro RIH$Q_CPU_MASK_ARRAY = 64,0,0,0 %; literal RIH$S_CPU_MASK_ARRAY = 128; ! array of CPU Masks literal RIH$C_LENGTH = 4160; ! Length of RAD info header literal RIH$C_CURRENT_RAD = 0; ! Allocate from the current CPU's RAD literal RIH$C_RANDOM_RAD = 1; ! Allocate randomly from all RADs literal RIH$C_BASE_RAD = 2; ! Allocate from the BASE RAD literal RIH$C_HOME_RAD = 3; ! Allocate from the home RAD literal RIH$C_DEFAULT_SKIP = 16; ! Skip count for soft RAD affinity literal RIH$C_DEFAULT_PROCESS_ALLOC = 3; ! Default process allocation algorithm literal RIH$C_DEFAULT_SWAPPER_ALLOC = 1; ! Default swapper allocation algorithm literal RIH$C_DEFAULT_GLOBAL_ALLOC = 1; ! Default global allocation algorithm literal RIH$C_DEFAULT_SYSTEM_ALLOC = 0; ! Default system allocation algorithm literal RHA$S_RHA = 32; macro RHA$Q_UNUSED1 = 0,0,0,0 %; literal RHA$S_UNUSED1 = 8; macro RHA$W_MBO = 8,0,16,0 %; ! Must Be One (if 65535 Global Sections, size too big) macro RHA$B_TYPE = 10,0,8,0 %; ! DYN$C_MISC macro RHA$B_SUBTYPE = 11,0,8,0 %; ! DYN$C_RHA macro RHA$L_UNUSED2 = 12,0,32,0 %; macro RHA$Q_SIZE = 16,0,0,0 %; literal RHA$S_SIZE = 8; ! Size of structure macro RHA$T_HINT_ARRAY = 24,0,8,1 %; literal RHA$S_HINT_ARRAY = 1; ! The actual RAD hint array !*** MODULE $RMDDEF *** ! ! Reserved Memory Descriptor Definitions. The reserved memory ! descriptor contains memory management data for a memory literal RMD$M_ALLOC = %X'1'; literal RMD$M_IN_USE = %X'2'; literal RMD$M_ZERO = %X'4'; literal RMD$M_ZERO_DONE = %X'8'; literal RMD$M_FREED = %X'10'; literal RMD$M_GROUP = %X'20'; literal RMD$M_PAGE_TABLES = %X'40'; literal RMD$M_GBLSEC = %X'80'; literal RMD$M_RESERVE_ERROR = %X'100'; literal RMD$M_RESERVED_FLAGS = %X'FFFFFE00'; literal RMD$C_LENGTH = 96; ! Length of RMD literal RMD$S_RMD = 96; macro RMD$PS_FLINK = 0,0,32,1 %; ! Flink for VA list of RMDs macro RMD$PS_BLINK = 4,0,32,1 %; ! Blink for VA list of RMDs macro RMD$W_SIZE = 8,0,16,0 %; ! Structure size (including RMD) macro RMD$B_TYPE = 10,0,8,0 %; ! Dynamic structure type macro RMD$B_SUBTYPE = 11,0,8,0 %; ! Dynamic structore subtype macro RMD$L_FLAGS = 12,0,32,0 %; ! FLAGS longword macro RMD$V_ALLOC = 12,0,1,0 %; ! Pages already allocated macro RMD$V_IN_USE = 12,1,1,0 %; ! Pages in use by section macro RMD$V_ZERO = 12,2,1,0 %; ! Pages should be zeroed macro RMD$V_ZERO_DONE = 12,3,1,0 %; ! Zeroing of pages finished macro RMD$V_FREED = 12,4,1,0 %; ! Pages for section freed macro RMD$V_GROUP = 12,5,1,0 %; ! For a group global section macro RMD$V_PAGE_TABLES = 12,6,1,0 %; ! For page tables macro RMD$V_GBLSEC = 12,7,1,0 %; ! Reservation is for (group or system) global section macro RMD$V_RESERVE_ERROR = 12,8,1,0 %; ! Reservation got an error during boot macro RMD$V_RESERVED_FLAGS = 12,9,23,0 %; literal RMD$S_RESERVED_FLAGS = 23; macro RMD$I_FIRST_PFN = 16,0,0,0 %; literal RMD$S_FIRST_PFN = 8; ! First PFN of a contiguous set, 0 if no alloc macro RMD$I_ZERO_PFN = 24,0,0,0 %; literal RMD$S_ZERO_PFN = 8; ! Next PFN to zero, meaningful during zeroing macro RMD$L_PFN_COUNT = 32,0,32,0 %; ! Count of PFNs in the section macro RMD$L_IN_USE_COUNT = 36,0,32,0 %; ! Number of PFNs in use macro RMD$L_ERROR_STATUS = 36,0,32,0 %; ! If RESERVE_ERROR flag set, error status macro RMD$L_GROUP = 40,0,32,0 %; ! UIC group number (octal value) macro RMD$L_RAD = 44,0,32,1 %; ! Resource Affinity Domain macro RMD$T_NAME = 52,0,0,0 %; literal RMD$S_NAME = 44; ! GS NAMES never more than 43 characters macro RMD$B_NAME_LEN = 52,0,8,0 %; ! Character count macro RMD$T_NAME_STR = 53,0,0,0 %; literal RMD$S_NAME_STR = 43; ! Character string !*** MODULE $RRDEF *** ! ! Definitions for Region Register ! literal RR$M_VE = %X'1'; literal RR$M_MBZ0 = %X'2'; literal RR$M_PS = %X'FC'; literal RR$M_RID = %X'FFFFFF00'; literal RR$M_MBZ1 = %X'FFFFFFFF00000000'; literal RR$S_RR = 8; macro RR$R_RR_UNION = 0,0,0,0 %; literal RR$S_RR_UNION = 8; macro RR$Q_REGION_REGISTER = 0,0,0,0 %; literal RR$S_REGION_REGISTER = 8; macro RR$V_VE = 0,0,1,0 %; ! VHPT walker enabled macro RR$V_MBZ0 = 0,1,1,0 %; ! Reserved bit RR{1:1} (MBZ) macro RR$V_PS = 0,2,6,0 %; literal RR$S_PS = 6; ! Preferred page size macro RR$V_RID = 0,8,24,0 %; literal RR$S_RID = 24; ! Region identifier macro RR$V_MBZ1 = 4,0,32,0 %; literal RR$S_MBZ1 = 32; ! Reserved RR{63:32} (MBZ) literal VRN$C_PROCESS = 0; ! Virtual Region Number 0 is for process space literal VRN$C_SYSTEM = 7; ! Virtual Region Number 7 is for system space literal VRN$C_REGION_COUNT = 8; ! Number of regions literal RR$C_SIZE = 8; ! Number of region registers !*** MODULE $RSBDEF *** ! + ! ! RSB - Resource Block ! ! Resource blocks represent resources for which there are locks outstanding. ! Each resource block may have one or more lock blocks (LKBs) queued to it. ! ! - literal RSB$M_DIRENTRY = %X'1'; literal RSB$M_VALINVLD = %X'2'; literal RSB$M_DIR_RQD = %X'4'; literal RSB$M_RM_PEND = %X'8'; literal RSB$M_RM_IP = %X'10'; literal RSB$M_RM_ACCEPT = %X'20'; literal RSB$M_RM_RBLD = %X'40'; literal RSB$M_RM_WAIT = %X'80'; literal RSB$M_RM_DEFLECT = %X'100'; literal RSB$M_DIR_IP = %X'200'; literal RSB$M_RBLD_IP = %X'400'; literal RSB$M_RBLD_RQD = %X'800'; literal RSB$M_RBLD_ACT = %X'1000'; literal RSB$M_CHK_BTR = %X'2000'; literal RSB$M_WTFULRNG = %X'4000'; literal RSB$M_WTSUBRNG = %X'8000'; literal RSB$M_BRL = %X'10000'; literal RSB$M_2PC_IP = %X'80000'; literal RSB$M_CVTFULRNG = %X'100000'; literal RSB$M_CVTSUBRNG = %X'200000'; literal RSB$M_VALCUR = %X'400000'; literal RSB$M_INVPEND = %X'800000'; literal RSB$M_DPC = %X'1000000'; literal RSB$M_GGMODE_VALID = %X'2000000'; literal RSB$M_XVAL_VALID = %X'4000000'; literal RSB$M_RM_FREEZE = %X'8000000'; literal RSB$M_RM_FORCE = %X'10000000'; literal RSB$M_RM_NO_INTEREST = %X'20000000'; literal RSB$K_MAXLEN = 31; ! Maximum length of Resource Name literal RSB$K_LENGTH = 320; ! Length of fixed part of RSB literal RSB$C_LENGTH = 320; ! Length of fixed part of RSB literal RSB$S_RSBDEF = 320; ! Old size name - synonym literal RSB$S_RSB = 320; macro RSB$Q_HSHCHN = 0,0,0,1 %; literal RSB$S_HSHCHN = 8; ! Hash Chain Pointer macro RSB$W_SIZE = 8,0,16,0 %; ! Size of RSB structure macro RSB$B_TYPE = 10,0,8,0 %; ! Structure type macro RSB$B_FGMODE = 11,0,8,0 %; ! Full-Range Grant Mode macro RSB$B_GGMODE = 12,0,8,0 %; ! Group Grant Mode macro RSB$B_CGMODE = 13,0,8,0 %; ! Conversion Grant Mode macro RSB$W_BLKASTCNT = 14,0,16,0 %; ! Blocking AST count macro RSB$L_STATUS = 16,0,32,0 %; ! Status longword macro RSB$V_DIRENTRY = 16,0,1,0 %; ! Directory Entry (director system for resource) macro RSB$V_VALINVLD = 16,1,1,0 %; ! Value Block Invalid macro RSB$V_DIR_RQD = 16,2,1,0 %; ! Directory Entry required macro RSB$V_RM_PEND = 16,3,1,0 %; ! Resource Remaster Operation Pending macro RSB$V_RM_IP = 16,4,1,0 %; ! Resource being Remastered macro RSB$V_RM_ACCEPT = 16,5,1,0 %; ! New Master accepts macro RSB$V_RM_RBLD = 16,6,1,0 %; ! Always rebuild tree macro RSB$V_RM_WAIT = 16,7,1,0 %; ! Block local activity macro RSB$V_RM_DEFLECT = 16,8,1,0 %; ! Deflect remote interest macro RSB$V_DIR_IP = 16,9,1,0 %; ! Directory Entry being created macro RSB$V_RBLD_IP = 16,10,1,0 %; ! Rebuild in progress macro RSB$V_RBLD_RQD = 16,11,1,0 %; ! Rebuild required for this tree macro RSB$V_RBLD_ACT = 16,12,1,0 %; ! Lock Rebuild active for tree macro RSB$V_CHK_BTR = 16,13,1,0 %; ! Check for better master (not used as of V8.3) macro RSB$V_WTFULRNG = 16,14,1,0 %; ! Full-Range REQs in wait queue macro RSB$V_WTSUBRNG = 16,15,1,0 %; ! Sub-Range REQs in wait queue macro RSB$V_BRL = 16,16,1,0 %; ! Indicates byte range resource macro RSB$V_2PC_IP = 16,19,1,0 %; ! Two Phase Convert in progress macro RSB$V_CVTFULRNG = 16,20,1,0 %; ! Full-Range REQs in convert queue macro RSB$V_CVTSUBRNG = 16,21,1,0 %; ! Sub-Range REQs in convert queue macro RSB$V_VALCUR = 16,22,1,0 %; ! Value Block is current macro RSB$V_INVPEND = 16,23,1,0 %; ! Do Value Block invalidation check macro RSB$V_DPC = 16,24,1,0 %; ! Delete pending cache macro RSB$V_GGMODE_VALID = 16,25,1,0 %; ! Group Grant Mode valid macro RSB$V_XVAL_VALID = 16,26,1,0 %; ! Last VALBLK was not short macro RSB$V_RM_FREEZE = 16,27,1,0 %; ! Freeze resource tree on this node macro RSB$V_RM_FORCE = 16,28,1,0 %; ! Forced tree move macro RSB$V_RM_NO_INTEREST = 16,29,1,0 %; ! Remaster due to master having no interest macro RSB$L_REFCNT = 20,0,32,0 %; ! Sub RSB reference count macro RSB$L_CSID = 24,0,32,0 %; ! System ID of master system macro RSB$L_RM_CSID = 28,0,32,0 %; ! Pending Remaster CSID macro RSB$Q_HSHCHNBK = 32,0,0,1 %; literal RSB$S_HSHCHNBK = 8; ! Hash Chain back pointer macro RSB$W_RQSEQNM = 40,0,16,0 %; ! Request sequence number macro RSB$Q_RQSEQNM = 40,0,0,0 %; literal RSB$S_RQSEQNM = 8; ! Request sequence number macro RSB$L_CLURCB = 48,0,32,1 %; ! Remaster Control Block macro RSB$W_ACTIVITY = 52,0,16,0 %; ! Resource activity counter macro RSB$W_LCKCNT = 54,0,16,0 %; ! Count of locks on resource macro RSB$W_NACT = 56,0,16,0 %; ! New activity macro RSB$W_OACT = 58,0,16,0 %; ! Old (historical) activity macro RSB$W_NMACT = 60,0,16,0 %; ! New master's activity macro RSB$B_LSTCSID_IDX = 62,0,8,0 %; ! Last CSID index macro RSB$B_SAME_CNT = 63,0,8,0 %; ! Same node counter macro RSB$Q_VALBLK = 64,0,0,0 %; literal RSB$S_VALBLK = 16; ! Short Value Block macro RSB$T_XVALBLK = 64,0,0,0 %; literal RSB$S_XVALBLK = 64; ! Long Value Block macro RSB$Q_GRQFL = 128,0,0,1 %; literal RSB$S_GRQFL = 8; ! Granted queue forward link macro RSB$Q_GRQBL = 136,0,0,1 %; literal RSB$S_GRQBL = 8; ! Granted queue backward link macro RSB$Q_CVTQFL = 144,0,0,1 %; literal RSB$S_CVTQFL = 8; ! Conversion queue forward link macro RSB$Q_CVTQBL = 152,0,0,1 %; literal RSB$S_CVTQBL = 8; ! Conversion queue backward link macro RSB$Q_WTQFL = 160,0,0,1 %; literal RSB$S_WTQFL = 8; ! Wait queue forward link macro RSB$Q_WTQBL = 168,0,0,1 %; literal RSB$S_WTQBL = 8; ! Wait queue backward link macro RSB$Q_2PCQFL = 176,0,0,0 %; literal RSB$S_2PCQFL = 8; ! Two Phase Converts forward link macro RSB$Q_2PCQBL = 184,0,0,0 %; literal RSB$S_2PCQBL = 8; ! Two Phase Converts backward link macro RSB$Q_RRSFL = 192,0,0,1 %; literal RSB$S_RRSFL = 8; ! Root list forward link macro RSB$Q_RRSBL = 200,0,0,1 %; literal RSB$S_RRSBL = 8; ! Root list backward link macro RSB$Q_SRSFL = 208,0,0,1 %; literal RSB$S_SRSFL = 8; ! Tree list forward link macro RSB$Q_SRSBL = 216,0,0,1 %; literal RSB$S_SRSBL = 8; ! Tree list backward link macro RSB$Q_RTRSB = 224,0,0,1 %; literal RSB$S_RTRSB = 8; ! Pointer to Root RSB macro RSB$L_DEPTH = 232,0,32,0 %; ! Depth in tree macro RSB$L_VALSEQNUM = 236,0,32,0 %; ! Value Block sequence number macro RSB$Q_LOCK = 240,0,0,0 %; literal RSB$S_LOCK = 16; ! RSB Synchronization Lock macro RSB$Q_PARENT = 256,0,0,1 %; literal RSB$S_PARENT = 8; ! Address of Parent RSB macro RSB$L_HASHVAL = 264,0,32,0 %; ! Hash Value (P26 32-bit value) macro RSB$W_DIRHASH = 266,0,16,0 %; ! Directory Hash (Pre-P26 16-bit Hash Value) macro RSB$W_GROUP = 268,0,16,0 %; ! Group number macro RSB$B_RMOD = 270,0,8,0 %; ! Access mode of resource macro RSB$B_RSNLEN = 271,0,8,0 %; ! Resource Name length macro RSB$T_RESNAM = 272,0,0,0 %; literal RSB$S_RESNAM = 32; ! Start of Resource Name macro RSB$Q_TOT_LCKCNT = 304,0,0,0 %; literal RSB$S_TOT_LCKCNT = 8; ! total locks on this tree macro RSB$Q_LOC_LCKCNT = 312,0,0,0 %; literal RSB$S_LOC_LCKCNT = 8; ! total local locks on this tree !*** MODULE $RSCDEF *** literal RSC$M_MODE = %X'3'; literal RSC$M_PL = %X'C'; literal RSC$M_BE = %X'10'; literal RSC$M_LOADRS = %X'3FFF0000'; literal RSC$S_RSC = 8; ! ! Register Stack Engine Control Register ! *************************************** macro RSC$IQ_RSE_CONTROL = 0,0,0,0 %; literal RSC$S_RSE_CONTROL = 8; macro RSC$V_MODE = 0,0,2,0 %; literal RSC$S_MODE = 2; ! RSE saving mode macro RSC$V_PL = 0,2,2,0 %; literal RSC$S_PL = 2; ! RSE privilege level macro RSC$V_BE = 0,4,1,0 %; ! RSE endian macro RSC$V_RV1 = 0,5,11,0 %; literal RSC$S_RV1 = 11; ! Reserved macro RSC$V_LOADRS = 0,16,14,0 %; literal RSC$S_LOADRS = 14; ! RSE load distance to tear point..used by loadrs instruction macro RSC$V_RV2 = 0,30,34,0 %; literal RSC$S_RV2 = 34; ! Reserved ! Constants for MODE field literal RSC$C_MODE_ENFORCED_LAZY = 0; ! disable eager load and eager store literal RSC$C_MODE_LOAD_INTENSIVE = 1; ! enable eager load, disable eager store literal RSC$C_MODE_STORE_INTENSIVE = 2; ! disable eager load, enable eager store literal RSC$C_MODE_EAGER = 3; ! enable eager load and eager store ! Constants for BE field literal RSC$C_ENDIAN_LITTLE = 0; literal RSC$C_ENDIAN_BIG = 1; !*** MODULE $RSNDEF *** ! + ! RESOURCE NAME DEFINITIONS ! - ! 0 ORIGIN IN INCREMENTS OF 1 literal RSN$_ASTWAIT = 1; ! WAIT FOR AST EVENT, CHANNEL INTERLOCK literal RSN$_MAILBOX = 2; ! MAILBOX SPACE literal RSN$_NPDYNMEM = 3; ! NON-PAGED DYNAMIC MEMORY literal RSN$_PGFILE = 4; ! PAGING FILE SPACE literal RSN$_PGDYNMEM = 5; ! PAGED DYNAMIC MEMORY literal RSN$_BRKTHRU = 6; ! TERMINAL BROADCAST literal RSN$_IACLOCK = 7; ! IMAGE ACTIVATION INTERLOCK literal RSN$_JQUOTA = 8; ! JOB POOLED QUOTA literal RSN$_LOCKID = 9; ! LOCKIDS literal RSN$_SWPFILE = 10; ! SWAPPING FILE SPACE literal RSN$_MPLEMPTY = 11; ! MODIFIED PAGE LIST EMPTY literal RSN$_MPWBUSY = 12; ! MODIFIED PAGE WRITER BUSY literal RSN$_SCS = 13; ! SYSTEM COMMUNICATION literal RSN$_CLUSTRAN = 14; ! CLUSTER STATE TRANSITION literal RSN$_CPUCAP = 15; ! CPU Capability literal RSN$_CLUSRV = 16; ! CLUSTER SERVER literal RSN$_SNAPSHOT = 17; ! literal RSN$_PSXFRK = 18; ! POSIX FORK WAIT literal RSN$_INNER_MODE = 19; ! Inner mode access for Kthreads literal RSN$_EXH = 20; ! Exit handler for Kthread literal RSN$_MMG = 21; ! MMG Contention literal RSN$_MAX = 22; ! MAXIMUM RESOURCE NUMBER !*** MODULE $RVTDEF *** ! + ! RVT - RELATIVE VOLUME TABLE ! ! A RELATIVE VOLUME MAPPING TABLE IS REQUIRED FOR EVERY MULTIVOLUME ! STRUCTURE THAT IS MOUNTED IN A SYSTEM. ! - literal RVT$K_LENGTH = 88; ! LENGTH OF STANDARD RVT literal RVT$C_LENGTH = 88; ! LENGTH OF STANDARD RVT literal RVT$C_UCB_POINTER = 0; ! ADDRESSES OF THE RESPECTIVE UCB'S literal RVT$C_PHYSICAL_VOLUME = 1; ! Physical volume number literal RVT$C_VOLUME_LOCK_ID = 2; ! Volume Lock ID literal RVT$C_VOLUME_IDENTIFIER = 3; ! Volume Identifier ! Number of overlay elements literal RVT$C_RVTVCB = 4; ! Number of elements (0 based) literal RVT$C_MINSIZE = 18; ! MINIMUM NUMBER OF ENTRIES TO ALLOCATE literal RVT$S_RVTDEF = 88; ! Old size name - synonym literal RVT$S_RVT = 88; macro RVT$L_STRUCLKID = 0,0,32,0 %; ! LOCK ID OF VOLUME SET LOCK. macro RVT$L_REFC = 4,0,32,0 %; ! REFERENCE COUNT macro RVT$W_SIZE = 8,0,16,0 %; ! SIZE OF RVT IN BYTES macro RVT$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE OF RVT macro RVT$B_NVOLS = 11,0,8,0 %; ! NUMBER OF VOLUMES IN SET macro RVT$T_STRUCNAME = 12,0,0,0 %; literal RVT$S_STRUCNAME = 12; ! STRUCTURE (VOLUME SET) NAME macro RVT$T_VLSLCKNAM = 24,0,0,0 %; literal RVT$S_VLSLCKNAM = 12; ! Volume set lock name. macro RVT$L_BLOCKID = 36,0,32,0 %; ! Blocking lock id. macro RVT$B_ACB = 40,0,0,0 %; literal RVT$S_ACB = 36; ! ACB for blocking ast. macro RVT$L_TRANS = 76,0,32,0 %; ! Transaction count for volume sets macro RVT$L_ACTIVITY = 80,0,32,0 %; ! ACTIVITY COUNT/FLAG macro RVT$L_UCBLST = 84,0,32,0 %; ! Addresses of the respective UCB'S macro RVT$A_RVTVCB = 84,0,32,0 %; ! Start of RVT/VCB fields for Files-11 C/D ! Files-11 C/D RVT/VCB datums !*** MODULE $SASDEVDEF IDENT X-8 *** ! Definitions used by both PKMDRIVER and IOGEN. literal SAS_TARG$M_SAS_DEVICE_TYPE = %X'F'; literal SAS_TARG$M_VALID = %X'10'; literal SAS_TARG$M_CONNECTED = %X'20'; literal SAS_TARG$M_UDID_CAPABLE = %X'40'; literal SAS_TARG$M_NVRAM_UDID_CAPABLE = %X'80'; literal SAS_TARG$M_DIRECT_ATTACHED = %X'100'; literal SAS_TARG$M_TARGET_RESET = %X'200'; literal SAS_TARG$M_DA_WITH_ENCL_MGMT = %X'400'; literal SAS_TARG$C_SATA_WWNAME_SIZE = 60; ! Specified max bytes, minus leading invariant bytes literal SAS_TARG$C_NO_DEVICE = 0; ! No device literal SAS_TARG$C_SAS_END_DEVICE = 1; ! SAS end device literal SAS_TARG$C_SATA_END_DEVICE = 2; ! SATA end device literal SAS_TARG$C_ATAPI_END_DEVICE = 3; ! ATAPI end device literal SAS_TARG$C_SEP_END_DEVICE = 4; ! SEP end device literal SAS_TARG$C_SAS_SATA_DEVICE = 13; ! SAS/SATA device literal SAS_TARG$C_RAID_PHYS_DISK = 14; ! Integrated RAID physical disk literal SAS_TARG$C_RAID_VOLUME = 15; ! Integrated RAID volume literal SAS_TARG$S_SAS_TARGET_DEVICE_BLOCK = 104; macro SAS_TARG$R_SAS_ADDRESS_UNION = 0,0,0,0 %; literal SAS_TARG$S_SAS_ADDRESS_UNION = 8; macro SAS_TARG$Q_SAS_ADDRESS = 0,0,0,0 %; literal SAS_TARG$S_SAS_ADDRESS = 8; ! 00h 00 macro SAS_TARG$R_SAS_ADDRESS_LONGWORDS = 0,0,0,0 %; literal SAS_TARG$S_SAS_ADDRESS_LONGWORDS = 8; macro SAS_TARG$L_SAS_ADDRESS_LO = 0,0,32,0 %; ! 00h 00 macro SAS_TARG$L_SAS_ADDRESS_HI = 4,0,32,0 %; ! 04h 04 macro SAS_TARG$R_UDID_UNION = 8,0,0,0 %; literal SAS_TARG$S_UDID_UNION = 8; macro SAS_TARG$Q_UDID = 8,0,0,0 %; literal SAS_TARG$S_UDID = 8; ! 08h 08 macro SAS_TARG$R_UDID_LONGWORDS = 8,0,0,0 %; literal SAS_TARG$S_UDID_LONGWORDS = 8; macro SAS_TARG$L_UDID_LO = 8,0,32,0 %; ! 08h 08 macro SAS_TARG$L_UDID_HI = 12,0,32,0 %; ! 0Ch 12 macro SAS_TARG$Q_HIGHEST_LBN = 16,0,0,0 %; literal SAS_TARG$S_HIGHEST_LBN = 8; ! 10h 16 macro SAS_TARG$B_WWNAME = 24,0,0,0 %; literal SAS_TARG$S_WWNAME = 60; ! 18h 24 macro SAS_TARG$B_WWNAME_LEN = 84,0,8,0 %; ! 54h 84 macro SAS_TARG$B_PORT = 85,0,8,0 %; ! 55h 85 macro SAS_TARG$B_TARGET_ID = 86,0,8,0 %; ! 56h 86 macro SAS_TARG$B_PERIPHERAL_DEV_TYPE = 87,0,8,0 %; ! 57h 87 macro SAS_TARG$V_SAS_DEVICE_TYPE = 88,0,4,0 %; literal SAS_TARG$S_SAS_DEVICE_TYPE = 4; ! 0 macro SAS_TARG$V_VALID = 88,4,1,0 %; ! 4 macro SAS_TARG$V_CONNECTED = 88,5,1,0 %; ! 5 macro SAS_TARG$V_UDID_CAPABLE = 88,6,1,0 %; ! 6 macro SAS_TARG$V_NVRAM_UDID_CAPABLE = 88,7,1,0 %; ! 7 macro SAS_TARG$V_DIRECT_ATTACHED = 88,8,1,0 %; ! 8 macro SAS_TARG$V_TARGET_RESET = 88,9,1,0 %; ! 9 macro SAS_TARG$V_DA_WITH_ENCL_MGMT = 88,10,1,0 %; ! 10 macro SAS_TARG$R_BITFIELD_CONTAINER = 88,0,32,0 %; literal SAS_TARG$S_BITFIELD_CONTAINER = 4; macro SAS_TARG$W_INFO_BITFIELD = 88,0,16,0 %; ! 58h 88 macro SAS_TARG$W_RESERVED1 = 90,0,16,0 %; ! 5Ah 90 macro SAS_TARG$W_PARENT = 92,0,16,0 %; ! 5Ch 92 macro SAS_TARG$W_ENCLOSURE = 94,0,16,0 %; ! 5Eh 94 macro SAS_TARG$W_SLOT = 96,0,16,0 %; ! 60h 96 macro SAS_TARG$W_START_SLOT = 98,0,16,0 %; ! 62h 98 macro SAS_TARG$L_RESERVED2 = 100,0,32,0 %; ! 64h 100 ! Definitions used by both PKMDRIVER and EFI. !*** MODULE S0PAGINGDEF *** literal S0PAGING$M_EXEC = %X'1'; literal S0PAGING$M_RMS = %X'2'; literal S0PAGING$S_S0PAGINGDEF = 4; ! Old size name - synonym literal S0PAGING$S_S0PAGING = 4; macro S0PAGING$V_EXEC = 0,0,1,0 %; ! exec paging (most loadable pieces) macro S0PAGING$V_RMS = 0,1,1,0 %; ! RMS paging !*** MODULE $SBDEF *** ! + ! SB - SCS SYSTEM BLOCK ! ! THE SB HAS INFORMATION ABOUT KNOWN SYSTEMS IN A CPU CLUSTER. ! - literal SB$M_LOCAL = %X'1'; literal SB$M_LOCAL_DIRECTORY = %X'2'; literal SB$S_SB = 120; macro SB$L_FLINK = 0,0,32,1 %; ! FWD LINK TO NEXT SB macro SB$L_BLINK = 4,0,32,1 %; ! BACK LINK TO PREVIOUS SB macro SB$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro SB$B_TYPE = 10,0,8,0 %; ! SCS STRUCTURE TYPE macro SB$B_SUBTYP = 11,0,8,0 %; ! SCS STRUCT SUBTYPE FOR SB macro SB$L_PBFL = 12,0,32,1 %; ! LINK TO NEXT PATH BLOCK macro SB$L_PBBL = 16,0,32,1 %; ! LINK TO PREVIOUS PATH BLOCK macro SB$L_PBCONNX = 20,0,32,1 %; ! ADDR OF NEXT PB TO USE FOR ! A CONNECTION macro SB$B_SYSTEMID = 28,0,0,0 %; literal SB$S_SYSTEMID = 6; ! SYSTEM ID macro SB$W_MAXDG = 36,0,16,0 %; ! MAXIMUM DATAGRAM SIZE macro SB$W_MAXMSG = 38,0,16,0 %; ! MAXIMUM MESSAGE SIZE macro SB$T_SWTYPE = 40,0,32,0 %; literal SB$S_SWTYPE = 4; ! SOFTWARE TYPE, 1-4 CHAR macro SB$T_SWVERS = 44,0,32,0 %; literal SB$S_SWVERS = 4; ! SOFTWARE VERSION, 1-4 CHAR macro SB$Q_SWINCARN = 48,0,0,0 %; literal SB$S_SWINCARN = 8; ! SOFTWARE INCARNATION # macro SB$T_HWTYPE = 56,0,32,0 %; literal SB$S_HWTYPE = 4; ! HW TYPE; 1-4 CHAR, BLANK FILL macro SB$B_HWVERS = 60,0,0,0 %; literal SB$S_HWVERS = 12; ! HW VERSION # macro SB$T_NODENAME = 72,0,0,0 %; literal SB$S_NODENAME = 16; ! SCS NODENAME, COUNTED ASCII STRING macro SB$L_DDB = 88,0,32,1 %; ! DDB LIST HEAD macro SB$W_TIMEOUT = 92,0,16,1 %; ! SCA PROCESS POLLER, WAITING TIME REMAINING macro SB$B_ENBMSK = 94,0,16,0 %; literal SB$S_ENBMSK = 2; ! SCA PROCESS POLLER, PROCESS ENABLE MASK macro SB$L_CSB = 96,0,32,1 %; ! LINK TO NEWEST CLUSTER SYSTEM BLOCK macro SB$L_PORT_MAP = 100,0,32,0 %; ! (TYC 13-Feb-89) LOAD SHARING PORT BIT MAP macro SB$L_STATUS = 104,0,32,0 %; ! System block Status macro SB$V_LOCAL = 104,0,1,0 %; ! System is a Local port, (A BVP or PU port) macro SB$V_LOCAL_DIRECTORY = 104,1,1,0 %; ! System is a local port and supports local directory lookups. macro SB$PS_PROC_NAMES = 108,0,32,1 %; ! Pointer to list of SYSAP process names supported by a local port. macro SB$L_MOUNT_LKID = 112,0,32,0 %; ! Reserved macro SB$PS_ALLOCLS_LIST = 116,0,32,1 %; ! Reserved literal SB$K_LENGTH = 120; ! LENGTH OF SB literal SB$C_LENGTH = 120; ! LENGTH OF SB literal SB$S_SBDEF = 120; ! Old size name - synonym !*** MODULE $SBNBDEF *** ! + ! SBNB - SCA LOAD SHARING NAME BLOCK ! ! THIS DATA STRUCTURE DESCRIBES A PROCESS NAME KNOWN TO THE SCA ! DYNAMIC LOAD SHARING CODE. ! - literal SBNB$K_LENGTH = 36; literal SBNB$C_LENGTH = 36; literal SBNB$S_SBNBDEF = 36; literal SBNB$S_SBNB = 36; macro SBNB$L_FLINK = 0,0,32,1 %; ! FWD LINK macro SBNB$L_BLINK = 4,0,32,1 %; ! BCK LINK macro SBNB$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro SBNB$B_TYPE = 10,0,8,0 %; ! SCS STRUCTURE TYPE macro SBNB$B_SUBTYP = 11,0,8,0 %; ! SCS STRUCTURE SUBTYPE FOR SBNB macro SBNB$L_DISCON_COUNT = 12,0,32,0 %; ! # OF DISCONNECT ! DUE TO LOAD SHARING ACTIVITY macro SBNB$B_PROCNAM = 16,0,0,0 %; literal SBNB$S_PROCNAM = 16; ! ASCII STRING FOR PROCESS NAME macro SBNB$W_LOCAL_INDEX = 32,0,16,0 %; ! BIT ASSIGNED TO THIS PROCESS NAME !*** MODULE $SBODEF *** ! + ! SBO - SCS CONFIG_SYS OUTPUT ARRAY FORMAT ! ! THE OUTPUT ARRAY RETURNED FROM CALL TO SCS$CONFIG_SYS. DATA IS MOSTLY COPIED FROM ! THE SYSTEM BLOCK (SB) BEING LOOKED UP. ! - literal SBO$C_VC1 = 60; ! START OF 12 BYTE SPECIFIER OF literal SBO$K_VC1 = 60; ! 1ST VC (PATH BLK) TO SYSTEM literal SBO$K_LENGTH = 80; ! LENGTH OF SBO ARRAY literal SBO$C_LENGTH = 80; ! LENGTH OF SBO ARRAY literal SBO$S_SBODEF = 80; ! Old size name - synonym literal SBO$S_SBO = 80; macro SBO$B_SYSTEMID = 0,0,0,0 %; literal SBO$S_SYSTEMID = 6; ! SYSTEM ID macro SBO$W_MAXDG = 8,0,16,0 %; ! MAXIMUM DG SIZE macro SBO$W_MAXMSG = 10,0,16,0 %; ! MAXIMUM MSG SIZE macro SBO$T_SWTYPE = 12,0,32,0 %; literal SBO$S_SWTYPE = 4; ! SW TYPE, 1-4 CHAR, BLNK FILL macro SBO$T_SWVERS = 16,0,32,0 %; literal SBO$S_SWVERS = 4; ! SW VERSION, 1-4 CHAR, BLNK FILL macro SBO$Q_SWINCARN = 20,0,0,0 %; literal SBO$S_SWINCARN = 8; ! SW INCARNATION # macro SBO$T_HWTYPE = 28,0,32,0 %; literal SBO$S_HWTYPE = 4; ! HW TYPE, 1-4 CHAR BLNK FILL macro SBO$B_HWVERS = 32,0,0,0 %; literal SBO$S_HWVERS = 12; ! HW VERSION, 1-4 CHAR BLNK FILL macro SBO$T_NODENAME = 44,0,0,0 %; literal SBO$S_NODENAME = 16; ! NODE NAME, COUNTED ASCII STRING macro SBO$B_RSTATION1 = 60,0,0,0 %; literal SBO$S_RSTATION1 = 6; ! REMOTE STATION OF 1ST VC macro SBO$T_LPORT1 = 68,0,32,0 %; literal SBO$S_LPORT1 = 4; ! LOCAL PORT NAME OF 1ST VC macro SBO$B_NXT_SYSID = 72,0,0,0 %; literal SBO$S_NXT_SYSID = 6; ! ID OF NEXT SYSTEM IN CONFIGURATION ! ! PEMGTDEF -- PEDRIVER Management Definitions. ! !*** MODULE $SCAMGTDEF *** ! ! Some common Response Status Codes. ! literal PEMGT$K_STS_NO_SUCH_PORT = 129; ! No such port (PE_PORT not found) literal PEMGT$K_STS_CONT_NOT_VALID = 130; ! Continuation data not valid literal PEMGT$K_STS_CONT_STALE = 131; ! Continuation data stale literal PEMGT$K_STS_CONT_WITH_HINT = 132; ! Continuation data supplied with non-zero hint literal PEMGT$K_STS_CONT_DISALLOWED = 133; ! Continuation data disallowed for request literal PEMGT$K_STS_CONT_LOST = 134; ! Continuation point not found literal PEMGT$K_STS_INCOMP_REQ = 135; ! Incomplete request (buffer contains partial request) literal PEMGT$K_STS_NAME_NOT_FOUND = 136; ! Name (VC, CH, BUS) not found literal PEMGT$K_STS_INVALID_NAME = 137; ! Invalid name (VC, CH, BUS)(partial name given) literal PEMGT$K_STS_PAR_REJECTED = 138; ! Parameter change rejected literal PEMGT$K_STS_PAR_NOT_IMP = 139; ! Parameter setting not implemented literal PEMGT$K_STS_NO_DATA_FOUND = 140; ! No data found literal PEMGT$K_STS_IP_NOT_INIT = 141; ! IP communication not intialized ! ! Common SCA driver codes ! Here we carve up the SCA object action code space. ! We will allow 64 SCA object specific codes and ! 64 common SCA codes. So we limit use of the code ! space to the first 128 action codes ! literal SCAMGT$K_PORT_GET = 65; ! Get PORT data literal SCAMGT$K_CIRC_GET = 66; ! Get CIRCUIT data literal SCAMGT$K_PORT_SET_PRIORITY = 67; ! Set PORT priority literal SCAMGT$K_CIRC_SET_PRIORITY = 68; ! Set CIRCUIT priority ! First SCA common action code literal SCAACT$K_SCA_FIRST_SCA_CODE = 64; ! Number of SCA common action codes literal SCAACT$K_SCA_NUM_SCA_CODES = 64; ! ! PORTNAM$ -- PORT name - Handle for a PORT structure ! literal PORTNAM$K_LENGTH = 16; ! PORTNAM$ length literal PORTNAM$S_PORTNAM = 16; macro PORTNAM$T_PORTNAME = 0,0,0,0 %; literal PORTNAM$S_PORTNAME = 8; ! ASCIC PORT device name macro PORTNAM$B_PORT_SEL = 8,0,8,0 %; ! Selection value: 0 - Include, 1 - Exclude ! ! CIRCNAM$ -- Circuit name - Handle for a Circuit (Path) structure ! literal CIRCNAM$K_LENGTH = 48; ! CIRCNAM$ length literal CIRCNAM$S_CIRCNAM = 48; macro CIRCNAM$T_NODENAME = 0,0,0,0 %; literal CIRCNAM$S_NODENAME = 16; ! ASCIC remote system name macro CIRCNAM$T_PORTNAME = 16,0,0,0 %; literal CIRCNAM$S_PORTNAME = 16; ! Handle for circuit port macro CIRCNAM$Q_RSTATION_NUM = 32,0,0,0 %; literal CIRCNAM$S_RSTATION_NUM = 8; ! Remote station ID disambiguator macro CIRCNAM$T_RSTATION_CHAR = 32,0,0,0 %; literal CIRCNAM$S_RSTATION_CHAR = 8; macro CIRCNAM$B_CIRC_SEL = 40,0,8,0 %; ! Selection value: 0 - Include, 1 - Exclude macro CIRCNAM$B_RSTATION_SET = 41,0,8,0 %; ! Flag: 0 - Rstation_num is not valid, ! 1 - RSTATION_NUM is valid. ! Needed because 0 is a valid remote station ! number. ! ! CIRCACT$ -- Circuit Management action structure ! literal CIRCACT$K_MAJOR = 1; ! CIRCACT$ minor version literal CIRCACT$K_MINOR = 1; ! CIRCACT$ major version literal CIRCACT$K_ACT_PARAMS_V1_1_LEN = 8; ! V1.1 CIRC ACT_PARAMS size literal CIRCACT$K_MIN_LEN = 8; ! CIRCACT$ length ! literal CIRCACT$R_SELCIRCS = 8; ! Start of the CIRC names literal CIRCACT$S_CIRCACT = 8; macro CIRCACT$R_ACT_PARAMS = 0,0,0,0 %; literal CIRCACT$S_ACT_PARAMS = 8; ! Parameters describing action to be performed macro CIRCACT$B_ACT_PAR_LEN = 0,0,8,0 %; ! Length of ACT_PARAMS record ! ! CIRC parameters. ! macro CIRCACT$L_PARAMS = 4,0,32,0 %; ! Force longword minimum size macro CIRCACT$B_NEW_MGT_PRIORITY = 4,0,8,0 %; ! Priority value to be assigned ! CIRC selection array. ! ! ! PORTACT$ -- Port management action structure ! literal PORTACT$K_MAJOR = 1; ! PORTACT$ minor version literal PORTACT$K_MINOR = 1; ! PORTACT$ major version literal PORTACT$K_ACT_PARAMS_V1_1_LEN = 8; ! V1.1 PORT ACT_PARAMS size literal PORTACT$K_MIN_LEN = 8; ! PORTACT$ length ! literal PORTACT$R_SELPORTS = 8; ! Start of the PORT identifier literal PORTACT$S_PORTACT = 8; macro PORTACT$R_ACT_PARAMS = 0,0,0,0 %; literal PORTACT$S_ACT_PARAMS = 8; ! Parameters describing action to be performed macro PORTACT$B_ACT_PAR_LEN = 0,0,8,0 %; ! Length of ACT_PARAMS record ! ! PORT parameters. ! macro PORTACT$L_PARAMS = 4,0,32,0 %; ! Force longword minimum size macro PORTACT$B_NEW_MGT_PRIORITY = 4,0,8,0 %; ! Priority value to be assigned ! PORT selection array. ! ! *********************************************************************** ! ! Responses to actions on port/path Circuits ! ! *********************************************************************** literal PORTDAT$K_MAJOR = 1; ! PORTDAT$ major version literal PORTDAT$K_MINOR = 1; ! PORTDAT$ minor version literal PORTDAT$K_V1_1_LEN = 72; ! PORTDAT$ length for: ! major version = 1 literal PORTDAT$K_LENGTH = 72; literal PORTDAT$S_PORTDAT = 72; macro PORTDAT$R_PORT_HANDLE = 0,0,0,0 %; literal PORTDAT$S_PORT_HANDLE = 16; macro PORTDAT$L_MGT_PRIORITY = 16,0,32,1 %; ! Current management priority setting macro PORTDAT$L_DG_XMT = 20,0,32,0 %; macro PORTDAT$L_DG_RCV = 24,0,32,0 %; macro PORTDAT$L_MSG_XMT = 28,0,32,0 %; macro PORTDAT$L_MSG_RCV = 32,0,32,0 %; macro PORTDAT$L_NUM_MAP = 36,0,32,0 %; macro PORTDAT$L_BYTES_MAPPED = 40,0,32,0 %; macro PORTDAT$L_PDT = 44,0,32,0 %; macro PORTDAT$L_LOAD_CLASS = 48,0,32,0 %; ! Port's Load Class macro PORTDAT$L_BYTES_DG_XMT_PEAK = 52,0,32,0 %; ! Peak value of total bytes xmitted ! by port for DG only macro PORTDAT$L_BYTES_DG_RCV_PEAK = 56,0,32,0 %; ! Peak value of total bytes rcv'd ! by port for DG only macro PORTDAT$L_BYTES_MSG_XMT_PEAK = 60,0,32,0 %; ! Peak value of total bytes xmitted ! by port for MSG only macro PORTDAT$L_BYTES_MSG_RCV_PEAK = 64,0,32,0 %; ! Peak value of total bytes rcv'd ! by port for MSG only macro PORTDAT$L_BYTES_MAPPED_PEAK = 68,0,32,0 %; ! Peak value of total bytes mapped ! by port for BT only ! minor version = 1 ! NOTE: When making additions to this structure you must do the following to ensure ! interoperability with prior AM & SCACP versions: ! - Additional cells must only be added at the end of the currently defined cells. ! ie: After the most recent 'constant Vn_n_LEN...' declaration, and ! immediately preceding this note. The VCDAT$K_MINOR must be ! incremented. Otherwise, the major version (VCDAT$K_MAJOR) must be ! incremented, and the minor version reset to 0. ! A constant defining the end of the cells contained in the new version must ! also be added. The constant's name must be defined using this template: ! VCDAT$K_V#major_#minor_LEN literal CIRCDAT$K_MAJOR = 1; ! CIRCDAT$ minor version literal CIRCDAT$K_MINOR = 1; ! CIRCDAT$ major version ! literal CIRCDAT$K_V1_1_LEN = 64; ! CIRCDAT$ length for: ! major version = 1 literal CIRCDAT$K_LENGTH = 64; literal CIRCDAT$S_CIRCDAT = 64; ! CIRCUIT name. ! macro CIRCDAT$T_NODENAME = 0,0,0,0 %; literal CIRCDAT$S_NODENAME = 16; ! ASCIC remote system name macro CIRCDAT$T_PORTNAME = 16,0,0,0 %; literal CIRCDAT$S_PORTNAME = 16; ! Handle for circuit port macro CIRCDAT$B_RSTATION = 32,0,0,0 %; literal CIRCDAT$S_RSTATION = 6; macro CIRCDAT$W_STATE = 40,0,16,0 %; macro CIRCDAT$L_REMOTE_TYPE = 44,0,32,0 %; macro CIRCDAT$L_PRIORITY = 48,0,32,1 %; macro CIRCDAT$L_MGT_PRIORITY = 52,0,32,1 %; ! Current management priority setting macro CIRCDAT$L_LOAD_CLASS = 56,0,32,0 %; ! Circuit's current load class. macro CIRCDAT$L_RSTATE = 60,0,32,0 %; ! Remote port's current state. ! minor version = 1 ! NOTE: When making additions to this structure you must do the following to ensure ! interoperability with prior AM & SCACP versions: ! - Additional cells must only be added at the end of the currently defined cells. ! ie: After the most recent 'constant Vn_n_LEN...' declaration, and ! immediately preceding this note. The VCDAT$K_MINOR must be ! incremented. Otherwise, the major version (VCDAT$K_MAJOR) must be ! incremented, and the minor version reset to 0. ! A constant defining the end of the cells contained in the new version must ! also be added. The constant's name must be defined using this template: ! VCDAT$K_V#major_#minor_LEN !*** MODULE $SCDRPDEF *** ! + ! SCDRP - SCSI Class Driver I/O Request Packet ! ! This structure contains SCSI class driver request packet, which is used ! to pass parameters between the SCSI class and port drivers. In addition, ! the drivers use it to save information temporarily during the execution ! of a SCSI command. ! ! Note: Unlike the class driver request packet (CDRP), this structure does ! NOT contain an IRP accessed at negative offsets from the base of the packet. ! Instead, several IRP fields used in the SCDRP are located at positive ! offsets from the base. ! ! ***NOTE1:**** New SCDRP fields must be entered at the end of the data structure. ! ! ***NOTE:**** If an INCOMPATIBLE CHANGE is made to this structure bump ! the version number of this structure. ! - literal SCDRP$C_VERSION = 7; ! Compatible version number. literal SCDRP$K_SCDRPBASE = 0; literal SCDRP$C_SCDRPBASE = 0; literal SCDRP$K_QCHAR_UNORDERED = 0; ! Device may reorder in queue literal SCDRP$K_QCHAR_ORDERED = 1; ! Queue barrier for device literal SCDRP$K_QCHAR_HEAD = 2; ! Move this I/O to the head of the queue literal SCDRP$K_QCHAR_NOT_QUEUED = 3; ! Sent untagged as in SCSI-1 literal SCDRP$K_QCHAR_ACA = 4; ! Automatic Contigent Allegiance literal SCDRP$M_FLAG_S0BUF = %X'1'; literal SCDRP$M_FLAG_BUFFER_MAPPED = %X'2'; literal SCDRP$M_FLAG_DISK_SPUN_UP = %X'4'; literal SCDRP$M_FLAG_LOCK = %X'8'; literal SCDRP$M_FLAG_QUEUED_IO = %X'10'; literal SCDRP$M_FLAG_ACA_IO = %X'20'; literal SCDRP$M_FLAG_CLEAR_ACA_MSG = %X'40'; literal SCDRP$M_FLAG_ASENSE_VALID = %X'80'; literal SCDRP$M_FLAG_ON_PORT_QUEUE = %X'100'; literal SCDRP$M_FLAG_ON_DEV_QUEUE = %X'200'; literal SCDRP$M_FLAG_ABORT_THIS_IO = %X'400'; literal SCDRP$M_FLAG_QUEUE_FULL_INIT = %X'800'; literal SCDRP$M_FLAG_QUEUE_FULL_SEEN = %X'1000'; literal SCDRP$M_FLAG_WAIT_FOR_IO = %X'2000'; literal SCDRP$M_FLAG_INTERNAL_REQUEST = %X'4000'; literal SCDRP$M_FLAG_SEND_MESSAGE_ONLY = %X'8000'; literal SCDRP$M_FLAG_SEND_DEVICE_RESET = %X'10000'; literal SCDRP$M_FLAG_MODE_SENSE = %X'60000'; literal SCDRP$M_FLAG_CL_PRIVATE_BUFF = %X'80000'; literal SCDRP$M_FLAG_TENBYTE = %X'100000'; literal SCDRP$M_FLAG_BUS_RESET = %X'200000'; literal SCDRP$M_FLAG_ON_SYS_QUEUE = %X'400000'; literal SCDRP$M_FLAG_ON_FP_QUEUE = %X'800000'; literal SCDRP$M_FLAG_RBUN_WANTED = %X'1000000'; literal SCDRP$M_FLAG_EXT_LUN = %X'2000000'; literal SCDRP$M_FLAG_MEDIUM_NOTPRESENT = %X'4000000'; literal SCDRP$M_FLAG_ON_CREDIT_QUEUE = %X'8000000'; literal SCDRP$M_FLAG_TIME_STAMP_RSCC = %X'10000000'; literal SCDRP$M_FLAG_READY = %X'20000000'; literal SCDRP$S_FP_SCDRP = 144; ! Moved for X-36c ! literal SCDRP$M_DSF_NOWAIT = %X'1'; literal SCDRP$M_DSF_RELEASE_SPDT_LOCK = %X'2'; literal SCDRP$M_DSF_DEVICE_WAS_RESET = %X'4'; literal SCDRP$M_DSF_REQUEST_ABORTED = %X'8'; literal SCDRP$M_DSF_REQUEST_FLUSHED = %X'10'; literal SCDRP$M_DSF_STALL_WFIKPCH_DIPL = %X'20'; literal SCDRP$M_MSGO_IDENTIFY = %X'1'; literal SCDRP$M_MSGO_QUEUE_TAG = %X'2'; literal SCDRP$M_MSGO_SYNC_OUT = %X'4'; literal SCDRP$M_MSGO_BUS_DEVICE_RESET = %X'8'; literal SCDRP$M_MSGO_MSG_PARITY_ERROR = %X'10'; literal SCDRP$M_MSGO_ID_ERROR = %X'20'; literal SCDRP$M_MSGO_ABORT = %X'40'; literal SCDRP$M_MSGO_NOP = %X'80'; literal SCDRP$M_MSGO_MESSAGE_REJECT = %X'100'; literal SCDRP$M_MSGO_CLEAR_ACA = %X'200'; literal SCDRP$M_MSGO_LAST_BIT = %X'400'; literal SCDRP$M_MSGI_SYNC_IN = %X'1'; literal SCDRP$M_EVENT_PARERR = %X'1'; literal SCDRP$M_EVENT_BSYERR = %X'2'; literal SCDRP$M_EVENT_MISPHS = %X'4'; literal SCDRP$M_EVENT_BADPHS = %X'8'; literal SCDRP$M_EVENT_RST = %X'10'; literal SCDRP$M_EVENT_CTLERR = %X'20'; literal SCDRP$M_EVENT_BUSERR = %X'40'; literal SCDRP$M_EVENT_ABORT = %X'80'; literal SCDRP$M_EVENT_MSGERR = %X'100'; literal SCDRP$M_CNX_ABORT_PND = %X'1'; literal SCDRP$M_CNX_ABORT_CMPL = %X'2'; literal SCDRP$M_CNX_ABORT_INPROG = %X'4'; literal SCDRP$M_CNX_ABORT_RESEL = %X'8'; literal SCDRP$M_CNX_PND_RESEL = %X'10'; literal SCDRP$M_CNX_DSCN = %X'20'; literal SCDRP$M_CNX_TMODSCN = %X'40'; literal SCDRP$M_PHASE_DATAOUT = %X'1'; literal SCDRP$M_PHASE_DATAIN = %X'2'; literal SCDRP$M_PHASE_CMD = %X'4'; literal SCDRP$M_PHASE_STS = %X'8'; literal SCDRP$M_PHASE_INV1 = %X'10'; literal SCDRP$M_PHASE_INV2 = %X'20'; literal SCDRP$M_PHASE_MSGOUT = %X'40'; literal SCDRP$M_PHASE_MSGIN = %X'80'; literal SCDRP$M_PHASE_ARB = %X'100'; literal SCDRP$M_PHASE_SEL = %X'200'; literal SCDRP$M_PHASE_RESEL = %X'400'; literal SCDRP$M_PHASE_DISCON = %X'800'; literal SCDRP$M_PHASE_CMD_CMPL = %X'1000'; literal SCDRP$M_PHASE_TMODISCON = %X'2000'; literal SCDRP$M_PHASE_FREE = %X'4000'; literal SCDRP$K_SCSI_LEN = 456; literal SCDRP$C_SCSI_LEN = 456; literal SCDRP$K_SCSI_V73 = 1; literal SCDRP$C_SCSI_V73 = 1; ! Define the structure length. literal SCDRP$K_LENGTH = 528; literal SCDRP$C_LENGTH = 528; literal SCDRP$S_SCDRP = 528; macro SCDRP$L_FQFL = 0,0,32,1 %; ! O Fork Queue FLINK macro SCDRP$L_FQBL = 4,0,32,1 %; ! O Fork Queue Blink macro SCDRP$W_SCDRPSIZE = 8,0,16,0 %; ! I Size field for positive section only macro SCDRP$B_CD_TYPE = 10,0,8,0 %; ! I Type, always of interest macro SCDRP$B_FLCK = 11,0,8,0 %; ! O Fork lock index macro SCDRP$L_FPC = 12,0,32,1 %; ! O Fork PC macro SCDRP$Q_FR3 = 16,0,0,1 %; literal SCDRP$S_FR3 = 8; ! O Fork R3 macro SCDRP$Q_FR4 = 24,0,0,1 %; literal SCDRP$S_FR4 = 8; ! O Fork R4 ! ! 10-Jul-01 X-29 ! ! This is the beginning of the abbreviated SCDRP which must be included ! in each port-specific Resource Bundle, currently only used by FastPath ! code; the goal is to minimize the size of the SCDRP required to perform ! a FastPath request ! macro SCDRP$L_IRP = 32,0,32,1 %; ! I/O Request Packet address macro SCDRP$PS_KPB = 36,0,32,1 %; ! Kernel Process Block address macro SCDRP$IS_STS = 40,0,32,0 %; ! Request status (not SCSI status) macro SCDRP$PS_CDB = 44,0,32,1 %; ! Pointer to SCSI Command Descriptor Block (CDB) macro SCDRP$PS_SPDT = 48,0,32,1 %; ! SCSI Port Descriptor Table address macro SCDRP$PS_PQFL = 52,0,32,1 %; ! Port or device queue forward link macro SCDRP$PS_PQBL = 56,0,32,1 %; ! Port or device queue backward link macro SCDRP$L_BCNT = 60,0,32,0 %; ! Requested transfer byte count macro SCDRP$L_STS_PTR = 64,0,32,1 %; ! SCSI status byte address (low byte of referenced longword) macro SCDRP$L_CMD_PTR = 68,0,32,0 %; ! Address of the SCSI command buffer (CBUF) macro SCDRP$L_PAD_BCNT = 72,0,32,0 %; ! Number of pad bytes macro SCDRP$L_TRANS_CNT = 76,0,32,0 %; ! Number of bytes of user data transfered macro SCDRP$IS_QUEUE_CHAR = 80,0,32,0 %; ! Queue characteristics for this command macro SCDRP$L_DMA_TIMEOUT = 84,0,32,0 %; ! DMA timeout in seconds macro SCDRP$L_CMD_BUF_LEN = 88,0,32,0 %; ! Number of valid bytes in SCSI CDB macro SCDRP$PS_SENSE_BUFFER = 92,0,32,1 %; ! Pointer to a buffer containing CHECK CONDITION sense data macro SCDRP$PS_COMPLETE_IO = 96,0,32,1 %; ! FastPath request completion routine address macro SCDRP$IS_REQUEST_STATUS = 100,0,32,0 %; ! Request completion status macro SCDRP$IS_SENSE_BUFFER_LEN = 104,0,32,0 %; ! Number of valid bytes in the sense data buffer ! These unions simply provide typed or untyped access to the same fields ! so the structures they point to can be referenced simply by code written ! in different languages - for instance, in C it allows us to avoid having ! to cast the pointer to keep the compiler happy (quiet) macro SCDRP$R_RBUN_OVERLAY = 108,0,32,0 %; macro SCDRP$PS_SCSI_RBUN = 108,0,32,1 %; ! Pointer to generic SCSI RBUN macro SCDRP$PS_FCP_RBUN = 108,0,32,1 %; ! Pointer to SCSI-over-FibreChannel Protocol RBUN macro SCDRP$PS_PKQ_RBUN = 108,0,32,1 %; ! Pointer to PKQ-specific RBUN macro SCDRP$PS_RBUN = 108,0,32,1 %; ! X-39 Pointer to generic RBUN macro SCDRP$R_CDT_SCDT_UNION = 112,0,32,0 %; literal SCDRP$S_CDT_SCDT_UNION = 4; macro SCDRP$L_CDT = 112,0,32,1 %; ! Leave in place for older drivers macro SCDRP$PS_SCDT = 112,0,32,1 %; ! SCSI Connection Descriptor Table address ! Constants valid for use in the QUEUE_CHAR field macro SCDRP$L_SCSI_FLAGS = 116,0,32,0 %; ! Byte 0 bits macro SCDRP$V_FLAG_S0BUF = 116,0,1,0 %; ! Buffer allocated by class driver from S0 space macro SCDRP$V_FLAG_BUFFER_MAPPED = 116,1,1,0 %; ! Buffer (S0 or user) has been mapped macro SCDRP$V_FLAG_DISK_SPUN_UP = 116,2,1,0 %; ! Start unit has been issued macro SCDRP$V_FLAG_LOCK = 116,3,1,0 %; ! Fork block in use flag macro SCDRP$V_FLAG_QUEUED_IO = 116,4,1,0 %; ! Optimize code for queued I/O macro SCDRP$V_FLAG_ACA_IO = 116,5,1,0 %; ! ACA command macro SCDRP$V_FLAG_CLEAR_ACA_MSG = 116,6,1,0 %; ! Send clear ACA message and terminate ACA processing when done macro SCDRP$V_FLAG_ASENSE_VALID = 116,7,1,0 %; ! Set to indicate valid data is in the sense buffer ! Byte 1 bits macro SCDRP$V_FLAG_ON_PORT_QUEUE = 116,8,1,0 %; ! Set while the SCDRP is queued to the PORT_QUEUE macro SCDRP$V_FLAG_ON_DEV_QUEUE = 116,9,1,0 %; ! Set while the SCDRP is queued to the IN_DEVICE_QUEUE macro SCDRP$V_FLAG_ABORT_THIS_IO = 116,10,1,0 %; ! Set to indicate that this I/O is actively being aborted macro SCDRP$V_FLAG_QUEUE_FULL_INIT = 116,11,1,0 %; ! Queue full processing should be initialized macro SCDRP$V_FLAG_QUEUE_FULL_SEEN = 116,12,1,0 %; ! Queue full message was seen macro SCDRP$V_FLAG_WAIT_FOR_IO = 116,13,1,0 %; ! Must wait for I/O completion macro SCDRP$V_FLAG_INTERNAL_REQUEST = 116,14,1,0 %; ! Internal (port generated) request, skip ACA processing macro SCDRP$V_FLAG_SEND_MESSAGE_ONLY = 116,15,1,0 %; ! Only send the message byte, there is no CDB to send ! Byte 2 bits macro SCDRP$V_FLAG_SEND_DEVICE_RESET = 116,16,1,0 %; ! Send a device reset message macro SCDRP$V_FLAG_MODE_SENSE = 116,17,2,0 %; literal SCDRP$S_FLAG_MODE_SENSE = 2; ! MODE_SENSE (private flags) macro SCDRP$V_FLAG_CL_PRIVATE_BUFF = 116,19,1,0 %; ! Class Driver Private Buffer macro SCDRP$V_FLAG_TENBYTE = 116,20,1,0 %; ! 10-byte mode sense commands supported macro SCDRP$V_FLAG_BUS_RESET = 116,21,1,0 %; ! SCDRP was on device queue during a bus reset macro SCDRP$V_FLAG_ON_SYS_QUEUE = 116,22,1,0 %; ! Set while the SCDRP is on a system queue (fork,timer,...) macro SCDRP$V_FLAG_ON_FP_QUEUE = 116,23,1,0 %; ! Set while the SCDRP is on the FastPath active queue ! Byte 3 bits macro SCDRP$V_FLAG_RBUN_WANTED = 116,24,1,0 %; ! Set when an RBUN is needed for FastPath macro SCDRP$V_FLAG_EXT_LUN = 116,25,1,0 %; ! F Use LUN from SCDRP, not SCDT macro SCDRP$V_FLAG_MEDIUM_NOTPRESENT = 116,26,1,0 %; ! Medium is not present macro SCDRP$V_FLAG_ON_CREDIT_QUEUE = 116,27,1,0 %; ! X-36a Request is on SCDT & STDT credit wait queues macro SCDRP$V_FLAG_TIME_STAMP_RSCC = 116,28,1,0 %; ! FibreChannel is using RSCC as a time stamp macro SCDRP$V_FLAG_READY = 116,29,1,0 %; ! X-38a SCDRP has been prep'd for issue by port macro SCDRP$IS_SEQUENCE = 120,0,32,0 %; ! O I/O sequence ID assigned by the port driver for error recovery. macro SCDRP$Q_TIME_STAMP = 128,0,0,1 %; literal SCDRP$S_TIME_STAMP = 8; ! O Time stamp for queue full processing. macro SCDRP$R_QUEUE_TAG_OVERLAY = 136,0,0,0 %; macro SCDRP$IS_QUEUE_TAG = 136,0,32,0 %; ! O Tag value allocated by port driver. Not used by - macro SCDRP$Q_QUEUE_TAG = 136,0,0,0 %; literal SCDRP$S_QUEUE_TAG = 8; ! O - intelligent ports ! O Overlay added for high SCSI ID's (wide devices) ! Make sure size is an integral number of quadwords ! 10-Jul-01 X-29 ! ! A comment associated with the following field says that it must appear right after ! the SCDRP fork block for use by MKDRIVER, but I don't see any evidence that this is ! other than a stale comment; it also referenced use of REQCHAN, but I don't see that ! in any of the drivers either. If any problems show up from breaking this field away ! from the fork block it will be restored to it's location immediately following the ! fork block ! macro SCDRP$L_PORT_UCB = 144,0,32,1 %; ! I Saved UCB address for REQCHAN ! Fields that came from IRP portion of the old SCDRP. macro SCDRP$L_UCB = 148,0,32,1 %; ! I Address of device (class driver) UCB macro SCDRP$L_FUNC = 152,0,32,0 %; ! O I/O function code and modifiers macro SCDRP$L_BOFF = 156,0,32,0 %; ! O Byte offset in first page macro SCDRP$L_SVAPTE = 160,0,32,1 %; ! O System Virtual Address of first PTE macro SCDRP$L_MEDIA = 164,0,32,1 %; ! O Media address macro SCDRP$L_ABCNT = 168,0,32,0 %; ! O Accumulated bytes transfered macro SCDRP$L_SAVD_RTN = 172,0,32,1 %; ! O Saved return address from level 1 JSB macro SCDRP$L_MSG_BUF = 176,0,32,1 %; ! O Address of allocated MSCP buffer macro SCDRP$L_RSPID = 180,0,32,0 %; ! O Allocated Request ID macro SCDRP$L_RWCPTR = 184,0,32,1 %; ! O RWAITCNT pointer ! SCDRP extensions ! SCSI port/class driver extension macro SCDRP$PS_PREV_SCDRP = 188,0,32,1 %; ! I Address of previous SCDRP macro SCDRP$L_SVA_USER = 192,0,32,1 %; ! O S0 address of double mapped user buffer macro SCDRP$L_CMD_BUF = 196,0,32,1 %; ! O Address of SCSI command buffer macro SCDRP$IS_DIPL_SCSI_FLAGS = 200,0,32,0 %; ! S SCSI flags modified at DIPL. macro SCDRP$V_DSF_NOWAIT = 200,0,1,0 %; ! S No wait is necessary in PK$WAIT_FOR_IO_COMPLETION. macro SCDRP$V_DSF_RELEASE_SPDT_LOCK = 200,1,1,0 %; ! S Device lock must be released in stall routine. macro SCDRP$V_DSF_DEVICE_WAS_RESET = 200,2,1,0 %; ! S Device was reset while request was active. macro SCDRP$V_DSF_REQUEST_ABORTED = 200,3,1,0 %; ! S Request aborted while active. macro SCDRP$V_DSF_REQUEST_FLUSHED = 200,4,1,0 %; ! S Request was flushed while active. macro SCDRP$V_DSF_STALL_WFIKPCH_DIPL = 200,5,1,0 %; ! S Request stalled, use KP_STALL_WFIKPCH_DIPL macro SCDRP$L_DATACHECK = 204,0,32,1 %; ! O Address of buffer for datacheck operations macro SCDRP$L_CL_RETRY = 208,0,32,0 %; ! O Retry count macro SCDRP$L_DISCON_TIMEOUT = 212,0,32,0 %; ! O Time in seconds for a disconnect to timeout. macro SCDRP$L_ADDNL_INFO = 216,0,32,0 %; ! O Additional extended sense info macro SCDRP$B_SENSE_KEY = 220,0,8,0 %; ! O Saved extended sense key ! SCSI PORT driver extension macro SCDRP$L_SVA_DMA = 224,0,32,1 %; ! O S0 address of chunk of 128KB DMA buffer macro SCDRP$IS_CMD_SLOT = 228,0,32,1 %; ! O Command slot information macro SCDRP$L_SVA_SPTE = 232,0,32,1 %; ! O SVA of SPTE mapping user buffer. macro SCDRP$PS_PORT_DMA_VA = 236,0,32,1 %; ! O VA of buffer for PORT macro SCDRP$L_PORT_SVAPTE = 240,0,32,1 %; ! O SVAPTE for *PORT* usage macro SCDRP$L_PORT_BOFF = 244,0,32,0 %; ! O BOFF for *PORT* usage macro SCDRP$PS_MODE_ARGS = 248,0,32,1 %; ! O Pointer to SCSI MODE_SENSE.C arguments macro SCDRP$L_SCSIMSGO_PTR = 252,0,32,1 %; ! O SCSI OUTPUT MSG PTR, required for the SII PORT macro SCDRP$L_SCSIMSGI_PTR = 256,0,32,1 %; ! O SCSI INPUT MSG PTR, required for the SII PORT macro SCDRP$B_SCSIMSGO_BUF = 260,0,0,1 %; literal SCDRP$S_SCSIMSGO_BUF = 8; ! O SCSI OUTPUT MSG buffer of port. macro SCDRP$B_SCSIMSGI_BUF = 268,0,0,1 %; literal SCDRP$S_SCSIMSGI_BUF = 8; ! O SCSI INPUT MSG buffer of port. macro SCDRP$L_MSGO_PENDING = 276,0,32,0 %; ! O Bit set if corresponding message is to be sent. macro SCDRP$V_MSGO_IDENTIFY = 276,0,1,0 %; ! O macro SCDRP$V_MSGO_QUEUE_TAG = 276,1,1,0 %; ! O macro SCDRP$V_MSGO_SYNC_OUT = 276,2,1,0 %; ! O macro SCDRP$V_MSGO_BUS_DEVICE_RESET = 276,3,1,0 %; ! O macro SCDRP$V_MSGO_MSG_PARITY_ERROR = 276,4,1,0 %; ! O macro SCDRP$V_MSGO_ID_ERROR = 276,5,1,0 %; ! O macro SCDRP$V_MSGO_ABORT = 276,6,1,0 %; ! O macro SCDRP$V_MSGO_NOP = 276,7,1,0 %; ! O macro SCDRP$V_MSGO_MESSAGE_REJECT = 276,8,1,0 %; ! O macro SCDRP$V_MSGO_CLEAR_ACA = 276,9,1,0 %; ! O macro SCDRP$V_MSGO_LAST_BIT = 276,10,1,0 %; ! O This must be last bit in this structure. macro SCDRP$L_MSGI_PENDING = 280,0,32,0 %; ! O Bit set if corresponding message is expected. macro SCDRP$V_MSGI_SYNC_IN = 280,0,1,0 %; ! O macro SCDRP$B_LAST_MSGO = 284,0,8,0 %; ! O Last message sent macro SCDRP$L_DATA_PTR = 288,0,32,1 %; ! O Current data pointer address. macro SCDRP$L_SAVE_DATA_CNT = 292,0,32,0 %; ! O Running 2's complement count of bytes to be transfered macro SCDRP$L_SAVE_DATA_PTR = 296,0,32,0 %; ! O Running data pointer. macro SCDRP$L_SDP_DATA_CNT = 300,0,32,0 %; ! O Storage for SDP macro SCDRP$L_SDP_DATA_PTR = 304,0,32,1 %; ! O Storage for SDP macro SCDRP$L_DUETIME = 308,0,32,0 %; ! O Timeout time for disconnected IO. macro SCDRP$IS_CMD_BCNT = 312,0,32,0 %; ! O temporary storage for cmd bytecnt macro SCDRP$IS_BUSY_RETRY_CNT = 316,0,32,0 %; ! O Number retries left, for bus busy. macro SCDRP$IS_ARB_RETRY_CNT = 320,0,32,0 %; ! O Number of retries left, for arbitration failures. macro SCDRP$IS_SEL_RETRY_CNT = 324,0,32,0 %; ! O Number of retries left, for selection failures. macro SCDRP$IS_CMD_RETRY_CNT = 328,0,32,0 %; ! O Number of times the port will retry a command. macro SCDRP$IS_SEL_TQE_RETRY_CNT = 332,0,32,0 %; ! O Number of TQE retries left, for selection failures. macro SCDRP$IS_DMA_LONG = 336,0,32,0 %; ! O DMA buffer for 1 byte transfers. macro SCDRP$IS_EVENTS_SEEN = 340,0,32,0 %; ! O Mask of events seen. macro SCDRP$V_EVENT_PARERR = 340,0,1,0 %; ! O Parity error occured. macro SCDRP$V_EVENT_BSYERR = 340,1,1,0 %; ! O Lost busy during command. macro SCDRP$V_EVENT_MISPHS = 340,2,1,0 %; ! O Missing bus phase detected. macro SCDRP$V_EVENT_BADPHS = 340,3,1,0 %; ! O A bad phase transition occured. macro SCDRP$V_EVENT_RST = 340,4,1,0 %; ! O The bus has been reset during this command. macro SCDRP$V_EVENT_CTLERR = 340,5,1,0 %; ! O A SCSI controller error has been detected. macro SCDRP$V_EVENT_BUSERR = 340,6,1,0 %; ! O A SCSI BUS ERROR HAS BEEN DETECTED macro SCDRP$V_EVENT_ABORT = 340,7,1,0 %; ! O This io has been aborted. macro SCDRP$V_EVENT_MSGERR = 340,8,1,0 %; ! O An error was detected during ??? macro SCDRP$IS_CNX_STS = 344,0,32,0 %; ! O Per I/O connection status. macro SCDRP$V_CNX_ABORT_PND = 344,0,1,0 %; ! O Abort pending on connection. macro SCDRP$V_CNX_ABORT_CMPL = 344,1,1,0 %; ! O Abort completed on connection. macro SCDRP$V_CNX_ABORT_INPROG = 344,2,1,0 %; ! O Abort is in progress. macro SCDRP$V_CNX_ABORT_RESEL = 344,3,1,0 %; ! O Port has been reselected while abort was in progress. macro SCDRP$V_CNX_PND_RESEL = 344,4,1,0 %; ! O Reselection interrupt pending. macro SCDRP$V_CNX_DSCN = 344,5,1,0 %; ! O Connection is disconnected. macro SCDRP$V_CNX_TMODSCN = 344,6,1,0 %; ! O Connection timed out. macro SCDRP$PS_CLASS_KPB = 348,0,32,1 %; ! O Field used by the queue manager to save KBP address. ! Bus phases for phase processing. macro SCDRP$IS_BUS_PHASE = 352,0,32,0 %; ! O Current SCSI bus phase. macro SCDRP$V_PHASE_DATAOUT = 352,0,1,0 %; ! O DATAIN Phase. macro SCDRP$V_PHASE_DATAIN = 352,1,1,0 %; ! O DATAIN Phase. macro SCDRP$V_PHASE_CMD = 352,2,1,0 %; ! O Command Phase. macro SCDRP$V_PHASE_STS = 352,3,1,0 %; ! O Status Phase. macro SCDRP$V_PHASE_INV1 = 352,4,1,0 %; ! O Invalid Phase 1. macro SCDRP$V_PHASE_INV2 = 352,5,1,0 %; ! O Invalid Phase 1. macro SCDRP$V_PHASE_MSGOUT = 352,6,1,0 %; ! O MESSAGEOUT Phase. macro SCDRP$V_PHASE_MSGIN = 352,7,1,0 %; ! O MESSAGEIN Phase. macro SCDRP$V_PHASE_ARB = 352,8,1,0 %; ! O Arbitration Phase. macro SCDRP$V_PHASE_SEL = 352,9,1,0 %; ! O Selection Phase. macro SCDRP$V_PHASE_RESEL = 352,10,1,0 %; ! O Reselection Phase. macro SCDRP$V_PHASE_DISCON = 352,11,1,0 %; ! O Disconnect seen. macro SCDRP$V_PHASE_CMD_CMPL = 352,12,1,0 %; ! O Command complete received. macro SCDRP$V_PHASE_TMODISCON = 352,13,1,0 %; ! O Disconnect operation timed out. macro SCDRP$V_PHASE_FREE = 352,14,1,0 %; ! O The bus went free. macro SCDRP$IS_OLD_PHASES = 356,0,32,0 %; ! O Used to track SCSI bus phases. ! Embeded CRCTX (Counted Resource ConTeXt block) ! Used in allocating/deallocating mapping resources macro SCDRP$R_CRCTX_BASE = 360,0,0,0 %; literal SCDRP$S_CRCTX_BASE = 96; macro SCDRP$IS_ITEM_CNT = 416,0,32,1 %; ! O Number of mapping resource units allocated macro SCDRP$IS_ITEM_NUM = 420,0,32,1 %; ! O Base mapping resource unit index allocated ! Define a pointer for DKMK to use during cancels macro SCDRP$PS_QIO_P6 = 456,0,32,1 %; ! Allocate some per-command space for the port driver macro SCDRP$Q_PORT_SPECIFIC = 464,0,0,0 %; literal SCDRP$S_PORT_SPECIFIC = 8; ! Reserve some space for future expansion. macro SCDRP$L_RSVD_LONG = 472,0,0,1 %; literal SCDRP$S_RSVD_LONG = 44; ! ; count of que full scsi status for SCSI2COMMON macro SCDRP$L_QFULL_STS_CNT = 516,0,32,1 %; macro SCDRP$Q_CREDIT_SEQUENCE = 520,0,0,0 %; literal SCDRP$S_CREDIT_SEQUENCE = 8; ! O X-38b Order in which credit was granted to this request ! Define SCSI FastPath defined constant !*** MODULE $SCDTDEF *** ! + ! SCDT - SCSI Connection Descriptor Table ! ! One SCDT is used per SCSI connection. A connection is a logical link ! between a class driver UCB and a device on the SCSI bus. The SCDT ! contains the entire context of a connection between a class driver ! (SYSAP) and a device on the SCSI bus. ! ! SCDT's are created by port drivers when class drivers call port driver's ! connect entry point. The class driver has no access to this data structure. ! The SCDT is used exclusively by the port driver. ! ! ***NOTE1:**** New SCDT fields must be entered at the end of the data structure. ! ! ***NOTE2:**** If an INCOMPATIBLE CHANGE is made to this structure bump ! the version number of this structure. ! - ! ! Performance Matrix (PM) ! ! Description ! ! We want to define a 2-dimensional array in which to count commands ! which complete successfully having transferred certain amounts of data ! in certain amounts of time. Because the C compiler must know a matrix's ! X dimension in order to reference the correct [X][Y] cell, this is most ! easily done with a fixed-sized array; since at this point we don't see ! a need for the time or LBC ranges to be variable, there's no reason we ! can't establish these values now - so the reference will be like this: ! ! matrix [time-range-index] [lbc-range-index] ! ! Time Slice Ranges (columns) ! =========================== ! ! We're interested in the range of times from 0 to 8 seconds. Because the ! time increments are small but the time spread is large (due to the fine ! granulatity of our basic unit, which is 1us) we're mapping a big number ! of potential time values into a small number of time range slots. The ! algorithm chosen to do this is one which we think the compiler can ! optimize fairly well, and will yield the following time slices: ! ! [X] Time >= [X] Time >= ! === ======= === ======= ! [000] 1.000000 us [012] 4.000000 ms ! [001] 2.000000 us [013] 8.000000 ms ! [002] 4.000000 us [014] 16.000000 ms ! [003] 8.000000 us [015] 32.000000 ms ! [004] 16.000000 us [016] 64.000000 ms ! [005] 32.000000 us [017] 128.000000 ms ! [006] 64.000000 us [018] 256.000000 ms ! [007] 128.000000 us [019] 512.000000 ms ! [008] 256.000000 us [020] 1.000000 sec ! [009] 512.000000 us [021] 2.000000 sec ! [010] 1.000000 ms [022] 4.000000 sec ! [011] 2.000000 ms ! ! Each I/O which is counted in a given column took no *less* than that ! column's amount of time to complete; for instance, an I/O counted in ! column 3 took at least 8 us to complete: 8us <= t < 16us. If we ever ! need to see sub-us times we'll have to change this algorithm. Note ! that because these are minimums we don't have to have an element for ! the highest value - it's implied that I/O counted in the last column ! all took between 4 s and our maximum (8 seconds) ! ! Logical Block Count Ranges (rows) ! ================================= ! ! We're interested in LBCs from 1 to 256. There's an assumption that no ! request which completes successfully will have a zero transfer count, ! so no special checking will be performed to ensure that we don't count ! such a completion. We'll ignore any request which completes with a ! transfer count of more than 256d blocks. We're making this maximum ! transfer size a constant based on but independent of a port's ! maximum I/O size. What we know about an I/O counted in any given row ! is that it transferred no more than the number of blocks shown. For ! instance, an I/O counted in row 5 transferred up to 32d blocks, ! inclusive: 16 < LBC <= 32. The difference in logic between this and ! the time dimension is that we're mapping a fairly small number of ! blocks to a smaller number of cells for LBCs, so they can be done ! quickly with a table lookup. However, we could adjust the table so ! the same logic as the time dimension holds for LBCs ! ! [Y] LBC <= [Y] LBC <= ! === ====== === ====== ! [0] 001 [5] 032 ! [1] 002 [6] 064 ! [2] 004 [7] 128 ! [3] 008 [8] 256 ! [4] 016 ! literal PM$C_MAX_TIME_100NS = 80000000; ! Maximum time logged, in unadjusted units literal PM$C_MAX_TIME_US = 8000000; ! Maximum byte count logged, including pad bytes literal PM$C_MAX_BCNT = 131072; ! Maximum block count logged - note assumed block size literal PM$C_MAX_LBC = 256; ! Number of columns in the matrix literal PM$C_TIME_X = 23; ! Number of rows in the matrix literal PM$C_LBC_Y = 9; ! Define columns first ... literal PM$S_PM = 832; ! 1s in EXE$GQ_SYSTIME (100ns) ticks ! Maximum time logged, in unadjusted units macro PM$R_TIME = 0,0,0,0 %; literal PM$S_TIME = 828; ! ... then define rows macro PM$L_LBC = 0,0,0,0 %; literal PM$S_LBC = 36; ! ! We use a pointer to the performance data so that we don't have multiple copies ! for a multipath disk. We just want to gather the performance data on a per lun basis. ! literal PM_DATA$S_PM_DATA = 1704; macro PM_DATA$Q_READ_TIME_ACC = 0,0,0,0 %; literal PM_DATA$S_READ_TIME_ACC = 8; ! F Read command execution time accumulator (us) macro PM_DATA$Q_WRITE_TIME_ACC = 8,0,0,0 %; literal PM_DATA$S_WRITE_TIME_ACC = 8; ! F Write command execution time accumulator (us) macro PM_DATA$L_READS = 16,0,32,0 %; ! F Number of 6- or 10-byte Read commands macro PM_DATA$L_WRITES = 20,0,32,0 %; ! F Number of 6- or 10-byte Write commands macro PM_DATA$L_BLOCKS_READ = 24,0,32,0 %; ! F Number of blocks read macro PM_DATA$L_BLOCKS_WRITTEN = 28,0,32,0 %; ! F Number of blocks written macro PM_DATA$L_USE_RSCC = 32,0,32,0 %; ! F Boolean true if RSCC timer is used, otherwise use systime macro PM_DATA$R_RD_PM = 36,0,0,0 %; literal PM_DATA$S_RD_PM = 832; ! F Performance Matrix for reads macro PM_DATA$R_WR_PM = 868,0,0,0 %; literal PM_DATA$S_WR_PM = 832; ! F Performance Matrix for writes literal SCDT$C_VERSION = 10; ! Compatible Version Number. literal SCDT$C_STATE_CLOSED = 0; ! O Closed literal SCDT$C_STATE_OPEN = 1; ! O Open literal SCDT$C_STATE_FAIL = 2; ! O Connect Failed literal SCDT$M_CAP_SCSI_2 = %X'1'; literal SCDT$M_CAP_SCSI_3 = %X'2'; literal SCDT$M_CAP_CMDQ = %X'4'; literal SCDT$M_CAP_FREEZEQ = %X'8'; literal SCDT$M_CAP_FLUSHQ = %X'10'; literal SCDT$M_CAP_CLASS_DRIVER_ACA = %X'20'; literal SCDT$S_FBLOCK = 48; ! Old FBLOCK size name ! literal SCDT$M_CFLG_ENA_DISCON = %X'1'; literal SCDT$M_CFLG_DIS_RETRY = %X'2'; literal SCDT$M_CFLG_TARGET_MODE = %X'4'; literal SCDT$M_ISTS_SDTR_SENT = %X'1'; literal SCDT$M_ISTS_DID_RESET_CALLBACK = %X'2'; literal SCDT$M_ISTS_PORT_GO_CREDITS = %X'4'; literal SCDT$M_ISTS_PORT_SPEC_3 = %X'8'; literal SCDT$M_ISTS_PORT_SPEC_4 = %X'10'; literal SCDT$M_ISTS_PORT_SPEC_5 = %X'20'; literal SCDT$M_QF_QUEUED_ACA = %X'1'; literal SCDT$M_QF_QUEUE_TIMER_RUNNING = %X'2'; literal SCDT$M_QF_NO_DEV_IO_CREDITS = %X'4'; literal SCDT$M_QF_NOT_QUEUED = %X'8'; literal SCDT$M_DQF_ACA_ACTIVE = %X'1'; literal SCDT$M_DQF_FLUSHING_QUEUE = %X'2'; literal SCDT$M_DQF_QUEUE_FULL = %X'4'; literal SCDT$M_DQF_QUEUE_FULL_INIT = %X'8'; literal SCDT$M_DQF_QUEUE_WAIT = %X'10'; literal SCDT$M_DQF_CLASS_DRVR_FREEZE_Q = %X'20'; literal SCDT$M_DQF_QUEUE_FLUSH_ACTIVE = %X'40'; literal SCDT$K_MAX_QUEUE_DEPTH = 160; ! Absolute maximum queue depth allowed. literal SCDT$K_MAX_TAG = 256; ! Number of tags in bit map. literal SCDT$C_LENGTH = 440; ! Length of SCDT literal SCDT$S_SCDTDEF = 440; ! Old size name, synonym for SCDT$S_SCDT literal SCDT$S_SCDT = 440; macro SCDT$W_SCDT_TYPE = 0,0,16,0 %; ! O Type of SCDT macro SCDT$W_STATE = 2,0,16,0 %; ! O Connection State macro SCDT$IS_CAPABILITY = 4,0,32,0 %; ! Connection Capability Mask macro SCDT$V_CAP_SCSI_2 = 4,0,1,0 %; ! Device reports SCSI-2 compliance. macro SCDT$V_CAP_SCSI_3 = 4,1,1,0 %; ! Device reports SCSI-3 compliance. macro SCDT$V_CAP_CMDQ = 4,2,1,0 %; ! Device supports command queuing. macro SCDT$V_CAP_FREEZEQ = 4,3,1,0 %; ! Class driver requests freeze_queue_on_error mode. macro SCDT$V_CAP_FLUSHQ = 4,4,1,0 %; ! Class driver requests flush_queue_on_error mode. macro SCDT$V_CAP_CLASS_DRIVER_ACA = 4,5,1,0 %; ! Class driver requests control of ACA operations. macro SCDT$W_SIZE = 8,0,16,0 %; ! I Structure size in bytes macro SCDT$B_TYPE = 10,0,8,0 %; ! I SCSI structure type macro SCDT$B_SUBTYP = 11,0,8,0 %; ! I SCSI structure subtype for SCDT ! ! Define the fork block. ! macro SCDT$R_FKB_OVERLAY = 16,0,0,0 %; macro SCDT$R_FKB = 16,0,0,0 %; literal SCDT$S_FKB = 48; ! O Embedded quadword aligned fork block macro SCDT$B_FLCK = 16,0,8,1 %; ! O For backward compatability with old Bliss/Macro code ! Define the structure references. ! macro SCDT$PS_SPDT = 64,0,32,1 %; ! I Address of associated PORT descriptor table macro SCDT$PS_STDT = 68,0,32,1 %; ! I Pointer to the STDT. macro SCDT$PS_HASH_FLINK = 72,0,32,1 %; ! F Forward link on SCDT hash list. macro SCDT$PS_SCDRP_MAP = 76,0,32,1 %; ! I List of SCDRPs indexed by tag value for reselection. ! ! Define the class driver callbacks. ! macro SCDT$L_SEL_CALLBACK = 80,0,32,1 %; ! I Address of Class driver callback. macro SCDT$L_SEL_CONTEXT = 84,0,32,0 %; ! I Context for Class driver callback. macro SCDT$PS_PORT_STATE_CALLBACK = 88,0,32,1 %; ! I Class driver call back for PORT_STATE specified with SPI$CONNECT. macro SCDT$L_PORT_STATE_CONTEXT = 92,0,32,0 %; ! I Context for Port State callback. ! ! ITL specific information. ! macro SCDT$R_SCSI_LUN_OVERLAY = 96,0,0,0 %; ! I macro SCDT$L_SCSI_LUN = 96,0,32,0 %; ! I Create quadword overlay for - macro SCDT$Q_SCSI_LUN = 96,0,0,0 %; literal SCDT$S_SCSI_LUN = 8; ! I wide devices or high SCSI ID's ! I macro SCDT$IQ_IN_NEX = 104,0,0,1 %; literal SCDT$S_IN_NEX = 8; ! I ITL Nexus Descriptor Table Entry contents macro SCDT$L_DMA_TIMEOUT = 112,0,32,0 %; ! I Time in seconds for a DMA timeout. macro SCDT$L_DISCON_TIMEOUT = 116,0,32,0 %; ! I Time in seconds for a disconnect to timeout. macro SCDT$IS_BUSY_RETRY_CNT = 120,0,32,0 %; ! I Number retries left, for bus busy. macro SCDT$IS_ARB_RETRY_CNT = 124,0,32,0 %; ! I Number of retries left, for arbitration failures. macro SCDT$IS_SEL_RETRY_CNT = 128,0,32,0 %; ! I Number of retries left, for selection failures. macro SCDT$IS_CMD_RETRY_CNT = 132,0,32,0 %; ! I Number of times the port will retry a command. ! ! Set Connection Characteristic Information ! macro SCDT$IS_CON_FLAGS = 136,0,32,0 %; ! I Connection Specific Flags. macro SCDT$V_CFLG_ENA_DISCON = 136,0,1,0 %; ! I Enable disconnect macro SCDT$V_CFLG_DIS_RETRY = 136,1,1,0 %; ! I Disable retry on command fail. macro SCDT$V_CFLG_TARGET_MODE = 136,2,1,0 %; ! I Target mode supported macro SCDT$IS_IMPL_STS = 140,0,32,0 %; ! F Implementation specific connection sts macro SCDT$V_ISTS_SDTR_SENT = 140,0,1,0 %; ! O If SDTR_SENT bit is set, it means for ! this target/LUN, we already sent SDTR ! message to negotiate sync. xfer mode macro SCDT$V_ISTS_DID_RESET_CALLBACK = 140,1,1,0 %; ! F Used by SCSI2COMMON to remember that we ! have already told the class driver that a ! reset is in progress. macro SCDT$V_ISTS_PORT_GO_CREDITS = 140,2,1,0 %; ! F Port restarting class driver for I/O credits macro SCDT$V_ISTS_PORT_SPEC_3 = 140,3,1,0 %; ! Define some bits for port-specific use and name macro SCDT$V_ISTS_PORT_SPEC_4 = 140,4,1,0 %; ! them so as to make this intention clear. The # macro SCDT$V_ISTS_PORT_SPEC_5 = 140,5,1,0 %; ! of each bit happens to be it's bit offset ! ! Queuing specific data. ! macro SCDT$IS_QUEUE_FLAGS = 144,0,32,0 %; ! F Bitmap of flags used to manage the port queue state. macro SCDT$V_QF_QUEUED_ACA = 144,0,1,0 %; ! F ACA I/O on head of queue. macro SCDT$V_QF_QUEUE_TIMER_RUNNING = 144,1,1,0 %; ! F Queue full timer is running. macro SCDT$V_QF_NO_DEV_IO_CREDITS = 144,2,1,0 %; ! F The port's device I/O queue has no remaining credits macro SCDT$V_QF_NOT_QUEUED = 144,3,1,0 %; ! F At least 1 Not-Queued request is pending or active macro SCDT$IS_DIPL_QUEUE_FLAGS = 148,0,32,0 %; ! S Bitmap of flags used to manage the port queue state. macro SCDT$V_DQF_ACA_ACTIVE = 148,0,1,0 %; ! S Queued command terminated with a check condition. macro SCDT$V_DQF_FLUSHING_QUEUE = 148,1,1,0 %; ! F The device and port queues are being flushed. macro SCDT$V_DQF_QUEUE_FULL = 148,2,1,0 %; ! S The device's queue is full. macro SCDT$V_DQF_QUEUE_FULL_INIT = 148,3,1,0 %; ! S Initialize queue full processing. macro SCDT$V_DQF_QUEUE_WAIT = 148,4,1,0 %; ! S Queue processing is waiting for device I/O completion. macro SCDT$V_DQF_CLASS_DRVR_FREEZE_Q = 148,5,1,0 %; ! S Class driver requested that the queue be frozen. macro SCDT$V_DQF_QUEUE_FLUSH_ACTIVE = 148,6,1,0 %; ! S Queue flush active is active macro SCDT$IS_SEQUENCE = 152,0,32,0 %; ! O Sequence ID assigned to a new I/O. macro SCDT$IS_NEXT_SEQUENCE = 156,0,32,0 %; ! O Next sequence ID expected to be sent by the port driver. ! ! SCSI-2 Congestion Control information. Used for queue full message processing. ! macro SCDT$IS_QUEUED_IO_COUNT = 160,0,32,0 %; ! F The number of SCSI commands queued following the command that ! received the queue full condition. macro SCDT$IS_MAX_QUEUE_DEPTH = 164,0,32,0 %; ! F Maximum queue depth for the port. macro SCDT$IS_CURRENT_QUEUE_DEPTH = 168,0,32,0 %; ! F Current queue depth for the port. ! Fast growth if CURRENT_QUEUE_DEPTH < QUEUE_DEPTH_THRESHOLD ! Slow growth if CURRENT_QUEUE_DEPTH > QUEUE_DEPTH_THRESHOLD macro SCDT$IS_QUEUE_DEPTH_THRESHOLD = 172,0,32,0 %; ! F Queue depth threshold. macro SCDT$Q_CMD_COMPLETE_TIME = 176,0,0,1 %; literal SCDT$S_CMD_COMPLETE_TIME = 8; ! F Average time to complete a command. macro SCDT$Q_CMD_COMPLETE_DEVIATION = 184,0,0,1 %; literal SCDT$S_CMD_COMPLETE_DEVIATION = 8; ! F Deviation in the time to complete a command. macro SCDT$Q_CMD_COMPLETE_DELAY = 192,0,0,1 %; literal SCDT$S_CMD_COMPLETE_DELAY = 8; ! F The delay required to ensure that an average command could complete. macro SCDT$IS_CMD_SUCCESS_COUNT = 200,0,32,0 %; ! F The number of commands that have successfully completed. ! if CMD_SUCCESS_COUNT >= CMD_SUCCESS_THRESHOLD ! Increment CURRENT_QUEUE_DEPTH; ! CMD_SUCCESS_COUNT = 0; macro SCDT$IS_CMD_SUCCESS_THRESHOLD = 204,0,32,0 %; ! F Threshold to be crossed before incrementing CURRENT_QUEUE_DEPTH. ! ! Queue Manager information. ! macro SCDT$PS_PORT_QFL = 208,0,32,1 %; ! F Forward link of queue of I/O sent to the port. macro SCDT$PS_PORT_QBL = 212,0,32,1 %; ! F Backward link of queue of I/O sent to the port. macro SCDT$PS_DEV_QFL = 216,0,32,1 %; ! F Forward link of queue of requests sent to the device. macro SCDT$PS_DEV_QBL = 220,0,32,1 %; ! F Backward link of queue of requests sent to the device. macro SCDT$IS_TOTAL_IO_COUNT = 224,0,32,0 %; ! F Total outstanding I/O count (port & device). macro SCDT$IS_PORT_IO_COUNT = 228,0,32,0 %; ! F Count of I/Os outstanding on the port. macro SCDT$IS_DEV_IO_COUNT = 232,0,32,0 %; ! F Count of I/Os outstanding on the device. macro SCDT$IS_HASH_INDEX = 236,0,32,0 %; ! F Index of this SCDT's root SCDT in the STDT hash table ! ! Port connection performance and error counters. ! macro SCDT$L_ARB_FAIL_CNT = 240,0,32,0 %; ! S Count of arbitration failures. macro SCDT$L_SEL_FAIL_CNT = 244,0,32,0 %; ! S Count of selection failures. macro SCDT$L_PARERR_CNT = 248,0,32,0 %; ! S Count of parity errors. macro SCDT$L_MISPHS_CNT = 252,0,32,0 %; ! S Count of missing phases errors. macro SCDT$L_BADPHS_CNT = 256,0,32,0 %; ! S Count of bad phase errors. macro SCDT$L_RETRY_CNT = 260,0,32,0 %; ! S Count of retries, this on connection. macro SCDT$L_CTLERR_CNT = 264,0,32,0 %; ! S Count of controller errors macro SCDT$L_BUSERR_CNT = 268,0,32,0 %; ! S Count of bus errors macro SCDT$L_CMDSENT = 272,0,32,0 %; ! S Number of commands sent macro SCDT$L_MSGSENT = 276,0,32,0 %; ! S Number of messages sent macro SCDT$L_BYTSENT = 280,0,32,0 %; ! S Number of bytes sent during dataout ! ! Allocation bit map for tag values, and associated values. ! macro SCDT$IS_WAIT_TAG = 284,0,32,0 %; ! F Tag value associated with a non-queued request. macro SCDT$IS_MAX_TAG_USED = 288,0,32,0 %; ! F Maximum tag value used, performance metric. ! Maximum tag value allowed: ( 0 - 255 ) ! Maximum longwords for the tag allocation bit map. macro SCDT$IS_TAG_MAP = 292,0,0,0 %; literal SCDT$S_TAG_MAP = 32; ! F Bitmap of allocated tag values. Bit set => value in use. macro SCDT$IS_LAST_TAG_INDEX = 324,0,32,0 %; ! F Last tag value allocated macro SCDT$PS_INQUIRY_DATA = 328,0,32,1 %; ! Pointer to Inquiry data macro SCDT$PS_CLASS_UCB = 332,0,32,1 %; ! Pointer to class driver UCB ! ! Save some space for future expansion. Reserved to Digital, ALPHA/VMS development. ! macro SCDT$L_RSVD_LONG = 336,0,0,1 %; literal SCDT$S_RSVD_LONG = 20; ! F Port specific space that may be used for any purpose. macro SCDT$PS_FP_DEV_QFL = 360,0,32,1 %; ! F FastPath device queue forward link /* FP macro SCDT$PS_FP_DEV_QBL = 364,0,32,1 %; ! F FastPath device queue backward link /* FP macro SCDT$IQ_FP_DEV_IO_COUNT = 368,0,0,1 %; literal SCDT$S_FP_DEV_IO_COUNT = 8; ! F Number of active FastPath requests /* FP ! ! Save some space for Port specific extensions. ! macro SCDT$R_PORT_SPECIFIC_OVERLAY = 376,0,0,0 %; macro SCDT$L_PORT_SPECIFIC = 376,0,0,1 %; literal SCDT$S_PORT_SPECIFIC = 20; ! F Port specific space that may be used for any purpose. macro SCDT$Q_IDENTITY = 376,0,0,1 %; literal SCDT$S_IDENTITY = 8; ! F Identity quadword ! ! These fields are first used in Ruby (V7.3-1). Since we do not have the ! option of forcing 3rd-party class driver recompiles in a dash release, ! these fields are being added to the tail of the structure. It would be ! a good idea to move them to before the port-specific overlays in the ! next dot release ! macro SCDT$PS_SCDT_LINK = 396,0,32,1 %; ! F Link to next SCDT connected to same STDT macro SCDT$L_SUSPENSIONS = 400,0,32,0 %; ! F Number of outstanding pauses/suspensions macro SCDT$PS_BUSY_TQE = 404,0,32,1 %; ! F Pointer to TQE used to implement a BUSY stall ! F X-27 macro SCDT$PS_PM_DATA = 408,0,32,1 %; ! F Pointer to common performance data for each LUN ! An HBA will sometimes require the LUN it uses to be formatted ! differently than is expected in the SCSI_LUN field by the OpenVMS ! Exec. For instance, the ISP23xx requires the LUN to be shifted ! down (right) 8 bits, while the ISP24xx requires the full quadword ! LUN but in big-endian order (LSB at high byte). To avoid having ! to reformat the LUN for every single SCSI command which is issued ! some drivers may choose to do the formatting once into this field ! when the device is initially configured ! X-28 macro SCDT$Q_LUN = 416,0,0,1 %; literal SCDT$S_LUN = 8; ! LUN as quadword macro SCDT$L_LUN = 416,0,32,1 %; ! LUN as longword macro SCDT$W_LUN = 420,0,16,1 %; ! LUN as word macro SCDT$B_LUN = 422,0,8,1 %; ! LUN as byte ! End union ! X-28 macro SCDT$Q_CREDIT_IO_COUNT = 424,0,0,1 %; literal SCDT$S_CREDIT_IO_COUNT = 8; ! Credit I/O count as quadword macro SCDT$IS_CREDIT_IO_COUNT = 424,0,32,1 %; ! Number of I/Os waiting for credit ! End union ! X-28 macro SCDT$R_CREDIT_WQ = 432,0,0,0 %; literal SCDT$S_CREDIT_WQ = 8; ! Credit wait queue macro SCDT$PS_CREDIT_WQFL = 432,0,32,1 %; ! Credit wait queue forward link macro SCDT$PS_CREDIT_WQBL = 436,0,32,1 %; ! Credit wait queue backward link ! ! Define the length of this structure. ! !*** MODULE $SCHDEF *** literal SCH$C_SWPPIX = 1; ! PIX for swapper process literal SCH$V_SIP = 0; ! SWAP IN PROGRESS FLAG literal SCH$M_SIP = 1; ! SWAP IN PROGRESS MASK literal SCH$V_TCD = 1; ! MPL threshold checking disabled literal SCH$M_TCD = 2; ! MPL threshold checking disabled mask literal SCH$V_MPW = 2; ! Modify page writer active literal SCH$M_MPW = 4; ! Modify page writer active mask literal SCH$V_REORD = 0; ! OSWPSCHED queue reordering occured literal SCH$C_RID_SYSTEM = 3; ! RID for system space literal SCH$C_ASN_MIN = 16; ! Minimum RID for process space literal SCH$M_DEFERRED_AST_OFF = %X'1'; literal SCH$M_QUEUE_OPT_OFF = %X'2'; literal SCH$S_SCHED_FLAGS = 4; macro SCH$L_SCHED_FLAGS = 0,0,32,0 %; ! SCHED Control Flags macro SCH$V_DEFERRED_AST_OFF = 0,0,1,0 %; ! Turn off AST Deferal optimizaton macro SCH$V_QUEUE_OPT_OFF = 0,1,1,0 %; ! Turn off AST queue optimization !*** MODULE $SCQDEF *** ! + ! $SCQDEF - SCSI Connect reQuest desciptor block ! ! The SCQ is passed by a SCSI class driver to a SCSI port driver as the ! sole argument in to the CONNECT service call. The SCQ contains all ! CONNECT service parameters, both input and output. ! +-------------------+ ! Buffer | 10 or 12 | argument count ! +-------------------+ ! 1 +04 | disconnects | 1 = supported, 0 = unsupported ! +-------------------+ ! 2 +08 | synchronous | Port controlled. ! +-------------------+ ! 3 +0C | Transfer_period | m * 4 nanoseconds ! +-------------------+ ! 4 +10 | Reqack_offset | ! +-------------------+ ! 5 +14 | Busy_retry_count | 0 = no retries ! +-------------------+ ! 6 +18 | Arb_retry_count | 0 = no retries ! +-------------------+ ! 7 +1C | Sel_retry_count | 0 = no retries ! +-------------------+ ! 8 +20 | Cmd_retry_count | 0 = no retries ! +-------------------+ ! 9 +24 | Dma_timeout | 0 = Phase/Dma Timeout ! +-------------------+ ! 10 +28 | Disconnect timeout| 0 = Disconnected IO timeout ! +-------------------+ ! 11 +2C | Flags | SCSI Flags ! +-------------------+ ! 12 +30 | Max Queue Depth | Maximum queue depth ! +-------------------+ ! ! The Flags field is defined as follows: ! ! Bit Description ! --- ----------- ! 0 CMDQ - Device supports command queuing if set ! 1 FLUSHQ - Flush queue on error ! 2 FREEZEQ - Freeze queue on error ! 3 SCSI-2 - Device is SCSI-2 conformant ! 31-4 Reserved MBZ ! - literal SCQ$C_VERSION = 1; ! Compatible Version Number. ! Inputs literal SCQ$K_CLSPOT_SP1 = 1; ! SP1$ protocol literal SCQ$K_CLSPOT_SP2 = 2; ! SP2$ protocol literal SCQ$S_SCQ = 60; macro SCQ$IS_CLSPOT_PROTOCOL = 0,0,32,0 %; ! Class/port protocol macro SCQ$IS_VERSION_NOS = 4,0,32,0 %; ! Data struc. version #s macro SCQ$IB_SCDRP_VNO = 4,0,8,0 %; ! SCDRP version macro SCQ$IB_SPDT_VNO = 5,0,8,0 %; ! SPDT version macro SCQ$IB_SCDT_VNO = 6,0,8,0 %; ! SCDT version macro SCQ$IB_STDT_VNO = 7,0,8,0 %; ! STDT version macro SCQ$PS_SCSIPATH = 8,0,32,1 %; ! Pointer to path info macro SCQ$IS_SCSI_IDS = 8,0,32,0 %; ! SCSI port/bus IDs macro SCQ$IW_SCSI_PORT_ID = 8,0,16,0 %; ! SCSI port ID macro SCQ$IW_SCSI_BUS_ID = 10,0,16,0 %; ! SCSI bus ID macro SCQ$IS_SCSI_LUN = 12,0,32,0 %; ! SCSI LUN (longword) macro SCQ$IW_SCSI_LUN = 14,0,16,0 %; ! SCSI_LUN (word) macro SCQ$PS_SEL_CALLBACK = 16,0,32,1 %; ! Target mode callback rout. macro SCQ$IS_SEL_CONTEXT = 20,0,32,0 %; ! Target mode context data macro SCQ$PS_AEN_CALLBACK = 24,0,32,1 %; ! AEN callback routine macro SCQ$IS_AEN_CONTEXT = 28,0,32,0 %; ! AEN context data macro SCQ$PS_PORT_STATE_CALLBACK = 32,0,32,1 %; ! Port State Callback Routine macro SCQ$IS_PORT_STATE_CONTEXT = 36,0,32,0 %; ! Port State Callback Context ! Outputs macro SCQ$PS_SPDT = 40,0,32,1 %; ! Port SPDT address macro SCQ$PS_SCDT = 44,0,32,1 %; ! SCDT address macro SCQ$PS_STDT = 48,0,32,1 %; ! STDT address macro SCQ$IS_MAX_BCNT = 52,0,32,0 %; ! Maximum BCNT supported macro SCQ$IS_PORT_SERV_FLAGS = 56,0,32,0 %; ! Port service flags literal SCQ$K_LENGTH = 60; ! Structure length literal SCQ$S_SCQDEF = 60; !*** MODULE $SCSDEF *** ! + ! SCS MESSAGE DEFINITIONS ! ! THIS STRUCTURE DEFINES OFFSETS AND FIELDS WITHIN THE SCS PORTION OF ! A CLUSTER MESSAGE. OFFSETS ARE DEFINED RELATIVE TO THE START OF THE ! APPLICATION DATA OR SCS CONTROL MESSAGE DATA. THE FULL MESSAGE FORMAT ! CONSISTS OF A PORT DRIVER LAYER HEADER (SEE STRUCTURE PPD) FOLLOWED ! BY THE SCS HEADER LAYER FOLLOWED BY THE APPLICATION DATA OR SCS CONTROL ! MESSAGE DATA. ! - literal SCS$C_OVHD = 14; ! SCS LAYER OVERHEAD literal SCS$C_CON_REQL = 66; ! CONNECT_REQ LENGTH literal SCS$C_CON_RSPL = 22; ! (TYC 20-apr-89) CONNECT_RSP LENGTH literal SCS$C_ACCP_REQL = 66; ! ACCEPT_REQ LENGTH literal SCS$C_ACCP_RSPL = 18; ! ACCEPT_RSP LENGTH literal SCS$C_REJ_REQL = 18; ! REJECT_REQ LENGTH literal SCS$C_REJ_RSPL = 14; ! REJECT_RSP LENGTH literal SCS$C_DISC_REQL = 18; ! DISCONNECT_REQ LENGTH literal SCS$C_DISC_RSPL = 14; ! DISCONNECT_RSP LENGTH literal SCS$C_CR_REQL = 14; ! CREDIT_REQ LENGTH literal SCS$C_CR_RSPL = 14; ! CREDIT_RSP LENGHT literal SCS$C_CON_REQ = 0; ! CONNECT_REQ literal SCS$C_CON_RSP = 1; ! CONNECT_RSP literal SCS$C_ACCP_REQ = 2; ! ACCEPT_REQ literal SCS$C_ACCP_RSP = 3; ! ACCEPT_RSP literal SCS$C_REJ_REQ = 4; ! REJECT_REQ literal SCS$C_REJ_RSP = 5; ! REJECT_RSP literal SCS$C_DISC_REQ = 6; ! DISCONNECT_REQ literal SCS$C_DISC_RSP = 7; ! DISCONNECT_RSP literal SCS$C_CR_REQ = 8; ! CREDIT_REQ literal SCS$C_CR_RSP = 9; ! CREDIT_RSP literal SCS$C_APPL_MSG = 10; ! APPLICATION MESSAGE literal SCS$C_APPL_DG = 11; ! APPLICATION DATAGRAM literal SCS$K_APPL_BASE = 0; ! BASE OF APPLICTION MESSAGE DATA literal SCS$C_APPL_BASE = 0; ! BASE OF APPLICTION MESSAGE DATA literal SCS$M_UAP = %X'1'; literal SCS$K_STNORMAL = 1; ! NORMAL, SUCCESS literal SCS$C_STNORMAL = 1; ! literal SCS$K_STNOMAT = 10; ! NO MATCHING LISTENER literal SCS$C_STNOMAT = 10; ! literal SCS$K_STNORS = 18; ! NO RESOURCES literal SCS$C_STNORS = 18; ! literal SCS$K_STDISC = 25; ! DISCONNECTED literal SCS$C_STDISC = 25; ! literal SCS$K_STINSFCR = 33; ! INSUFF CREDIT literal SCS$C_STINSFCR = 33; ! literal SCS$K_STBALANCE = 41; ! LOAD BALANCE literal SCS$C_STBALANCE = 41; ! DISCONNECT literal SCS$K_USE_ALTERNATE_PORT = 42; ! (TYC 13-Feb-89) Load Share literal SCS$C_USE_ALTERNATE_PORT = 42; ! Status code for using alternate port literal SCS$K_CON_BASE = 4; ! BASE OF CONNECT/ACCEPT INFO TO literal SCS$C_CON_BASE = 4; ! BASE OF CONNECT/ACCEPT INFO TO ! GIVE TO SYSAP'S literal SCS$S_SCSDEF = 84; ! Old size name - synonym literal SCS$S_SCS = 84; macro SCS$B_PPD = -32,0,0,0 %; literal SCS$S_PPD = 16; ! 16 BYTES OF PPD HEADER macro SCS$W_LENGTH = -16,0,16,0 %; ! MESSAGE LENGTH (INCLUDES ALL ! BYTES FROM SCS$W_LENGTH ON, ! NOT INCLUDING SCS$W_LENGTH) ! (FIELD SHARED BY PPD) ! DEFINE LENGTHS OF SCS CONTROL MSGS: macro SCS$W_MTYPE = -12,0,16,0 %; ! SCS MESSAGE TYPE ! SCS MESSAGE TYPE CODES: ! 0 ORIGIN, INCREMENTS OF 1 macro SCS$W_CREDIT = -10,0,16,0 %; ! CREDIT BEING EXTENDED macro SCS$L_DST_CONID = -8,0,32,0 %; ! DESTINATION (RECVING) CONNX ID macro SCS$L_SRC_CONID = -4,0,32,0 %; ! SOURCE (SENDING) CONNX ID macro SCS$W_MIN_CR = 0,0,16,0 %; ! MINIMUM SEND CREDIT macro SCS$W_STATUS = 2,0,16,0 %; ! STATUS/REASON macro SCS$V_UAP = 2,0,1,0 %; ! USE ALTERNATE PORT is supported ! DEFINE STATUS/REASON CODES: ! FORMAT OF CONNECT/ACCEPT_REQ MSGS: macro SCS$T_DST_PROC = 4,0,0,0 %; literal SCS$S_DST_PROC = 16; ! DESTINATION PROCESS NAME macro SCS$B_SUBNODE = 4,0,8,0 %; ! MUST BE ZERO FOR NOW macro SCS$B_PGRP = 5,0,8,0 %; ! ALTERNATE PORT'S PPD ADDR macro SCS$W_RSV = 6,0,16,0 %; ! RESERVED FIELD macro SCS$T_SRC_PROC = 20,0,0,0 %; literal SCS$S_SRC_PROC = 16; ! SOURCE PROCESS NAME macro SCS$B_CON_DAT = 36,0,0,0 %; literal SCS$S_CON_DAT = 16; ! CONNECT DATA ! ! DEFINITION OF THE REQUEST/SEND DATA OFFSETS ! literal SCS$S_SCSDEF1 = 28; ! Old size name - synonym literal SCS$S_SCS1 = 28; macro SCS$L_LCONID = -16,0,32,0 %; ! LOCAL CONNECTION ID macro SCS$L_RSPID = -12,0,32,0 %; ! LOCAL RESPONSE ID macro SCS$L_XCT_LEN = -8,0,32,0 %; ! TRANSACTION LENGTH macro SCS$L_SND_NAME = -4,0,32,0 %; ! SEND BUFFER NAME macro SCS$L_SND_BOFF = 0,0,32,0 %; ! AND OFFSET macro SCS$L_REC_NAME = 4,0,32,0 %; ! RECEIVE BUFFER NAME macro SCS$L_REC_BOFF = 8,0,32,0 %; ! AND OFFSET !*** MODULE $SCSCMGDEF *** ! + ! SCSCMG - SCS CONNECTION MANAGEMENT MESSAGE FORMAT ! ! THIS PORTION OF A CONNECT/ACCEPT MESSAGE IS SEEN BY A ! SYSTEM APPLICATION. ! - literal SCSCMG$S_SCSCMGDEF = 48; literal SCSCMG$S_SCSCMG = 48; macro SCSCMG$T_RECNAM = 0,0,0,0 %; literal SCSCMG$S_RECNAM = 16; ! RECEIVE PROCESS NAME macro SCSCMG$T_SNDNAM = 16,0,0,0 %; literal SCSCMG$S_SNDNAM = 16; ! SENDER PROCESS NAME macro SCSCMG$B_SNDDAT = 32,0,0,0 %; literal SCSCMG$S_SNDDAT = 16; ! SENDER CONNECT DATA !*** MODULE $SCSNETDEF *** ! + ! SCS CI PPD definitions ! ! This structure defines offsets and fields for SCS datagrams used in the ! datagram handshake between remote systems. The full format consists of ! a port heder (See Structure PPD) followed by these definitions. The origin ! of this field is the beginning of user data for a normal SCS datagram ! so that the PDT$L_DGHDRSZ may be used to determine the true origin of the ! packet. ! - literal SCSNET$C_START_LEN = 62; ! Start dg length literal SCSNET$C_STACK_LEN = 62; ! Stack dg length literal SCSNET$C_ACK_LEN = 2; ! Ack dg length literal SCSNET$C_HSHUT_LEN = 2; ! Host shutdown dg length literal SCSNET$C_CACHE_LEN = 2; ! Cache clear marker length literal SCSNET$C_START = 0; ! START DATAGRAM literal SCSNET$C_STACK = 1; ! STACK DATAGRAM literal SCSNET$C_ACK = 2; ! ACK DATAGRAM literal SCSNET$C_SCS_DG = 3; ! SCS DATAGRAM literal SCSNET$C_SCS_MSG = 4; ! SCS MESSAGE literal SCSNET$C_ELOG = 5; ! ERROR LOG DATAGRAM literal SCSNET$C_HOSTSHUT = 6; ! HOST SHUTDOWN DATAGRAM literal SCSNET$C_CACHECLR = 32768; ! CACHE CLEAR MARKER MSG ! (8000 hex) literal SCSNET$C_PRT_BASE = 0; ! 1st PPD Protocol Rev literal SCSNET$C_PRT_ELOG = 1; ! 2nd rev, supports error ! log dgs and host shutdown. literal SCSNET$C_MIN_DGSIZ = 48; ! Minimum allowed DG size, ! not including the SCS header. literal SCSNET$S_SCSNETDEF = 80; ! Old size name - synonym literal SCSNET$S_SCSNET = 80; macro SCSNET$B_PPD = -32,0,0,0 %; literal SCSNET$S_PPD = 16; ! 16 bytes of PPD header macro SCSNET$W_LENGTH = -16,0,16,0 %; ! message length (includes all ! bytes from scs$w_length on, ! not including SCS$W_LENGTH) ! (field shared by PPD) macro SCSNET$W_MTYPE = -14,0,16,0 %; macro SCSNET$B_SYSTEMID = -12,0,0,0 %; literal SCSNET$S_SYSTEMID = 6; ! Sending System ID macro SCSNET$B_PROTOCOL = -6,0,8,0 %; ! PPD Protocol Level macro SCSNET$W_MAXDG = -4,0,16,0 %; ! Max DG size macro SCSNET$W_MAXMSG = -2,0,16,0 %; ! Max MSG size macro SCSNET$T_SWTYPE = 0,0,32,0 %; literal SCSNET$S_SWTYPE = 4; ! Software type macro SCSNET$T_SWVERS = 4,0,32,0 %; literal SCSNET$S_SWVERS = 4; ! Software version macro SCSNET$Q_SWINCARN = 8,0,0,0 %; literal SCSNET$S_SWINCARN = 8; ! Software incarnation # macro SCSNET$T_HWTYPE = 16,0,32,0 %; literal SCSNET$S_HWTYPE = 4; ! Hardware type macro SCSNET$B_HWVERS = 20,0,0,0 %; literal SCSNET$S_HWVERS = 12; ! Hardware version macro SCSNET$Q_NODENAME = 32,0,0,0 %; literal SCSNET$S_NODENAME = 8; ! Node Name macro SCSNET$Q_CURTIME = 40,0,0,0 %; literal SCSNET$S_CURTIME = 8; ! Current system time measured ! in 100 nsec units !*** MODULE $SDA_OPTDEF *** literal SDA_OPT$M_QUEUE_SELF = %X'1'; literal SDA_OPT$M_QUEUE_QUADLINK = %X'2'; literal SDA_OPT$M_QUEUE_SINGLINK = %X'4'; literal SDA_OPT$M_QUEUE_LISTQUEUE = %X'8'; literal SDA_OPT$M_QUEUE_BACKLINK = %X'10'; literal SDA_OPT$M_QUEUE_MAX_VALIDATE = %X'20'; literal SDA_OPT$M_READ_FORCE = %X'1'; literal SDA_OPT$M_READ_IMAGE = %X'2'; literal SDA_OPT$M_READ_SYMVA = %X'4'; literal SDA_OPT$M_READ_RELO = %X'8'; literal SDA_OPT$M_READ_EXEC = %X'10'; literal SDA_OPT$M_READ_NOLOG = %X'20'; literal SDA_OPT$M_READ_FILESPEC = %X'40'; literal SDA_OPT$M_READ_NOSIGNAL = %X'80'; literal SDA_OPT$M_READ_MAX_SYMFILE = %X'100'; literal SDA_OPT$M_FORMAT_TYPE = %X'1'; literal SDA_OPT$M_SPARE1 = %X'FFFFFFF'; literal SDA_OPT$M_PHYSICAL = %X'10000000'; literal SDA_OPT$K_PARSE_SAVE = 0; ! save this command for recall literal SDA_OPT$K_PARSE_DONT_SAVE = 1; ! do not save this command literal SDA_OPT$S_OPTDEF = 4; macro SDA_OPT$V_QUEUE_SELF = 0,0,1,0 %; ! SELF RELATIVE QUEUE macro SDA_OPT$V_QUEUE_QUADLINK = 0,1,1,0 %; ! QUEUE with QUADWORD links macro SDA_OPT$V_QUEUE_SINGLINK = 0,2,1,0 %; ! Singly linked queue macro SDA_OPT$V_QUEUE_LISTQUEUE = 0,3,1,0 %; ! Display elements of queue macro SDA_OPT$V_QUEUE_BACKLINK = 0,4,1,0 %; ! Scan backwards macro SDA_OPT$V_QUEUE_MAX_VALIDATE = 0,5,1,0 %; macro SDA_OPT$V_READ_FORCE = 0,0,1,0 %; ! READ/FORCE macro SDA_OPT$V_READ_IMAGE = 0,1,1,0 %; ! READ/IMAGE macro SDA_OPT$V_READ_SYMVA = 0,2,1,0 %; ! READ/SYMVA macro SDA_OPT$V_READ_RELO = 0,3,1,0 %; ! READ/RELO macro SDA_OPT$V_READ_EXEC = 0,4,1,0 %; ! READ/EXEC [] macro SDA_OPT$V_READ_NOLOG = 0,5,1,0 %; ! /NOLOG macro SDA_OPT$V_READ_FILESPEC = 0,6,1,0 %; ! or given macro SDA_OPT$V_READ_NOSIGNAL = 0,7,1,0 %; ! just return status, don't signal errors macro SDA_OPT$V_READ_MAX_SYMFILE = 0,8,1,0 %; macro SDA_OPT$V_FORMAT_TYPE = 0,0,1,0 %; ! FORMAT/TYPE=name macro SDA_OPT$V_PHYSICAL = 0,28,1,0 %; ! Physical address !*** MODULE $SDA_CIODEF *** literal SDA_CIO$M_VALID = %X'1'; literal SDA_CIO$M_PROCESS = %X'2'; literal SDA_CIO$M_SLICED = %X'4'; literal SDA_CIO$M_COMPRESSED = %X'8'; literal SDA_CIO$M_ISD_INDEX = %X'FFF0'; literal SDA_CIO$K_FIX = 0; ! Dynamic (fixup) literal SDA_CIO$K_PROMO_CODE = 1; ! Promote (code) literal SDA_CIO$K_PROMO_DATA = 2; ! Promote (data) literal SDA_CIO$K_INIT_CODE = 3; ! Initialization (code) literal SDA_CIO$K_INIT_DATA = 4; ! Initialization (data) literal SDA_CIO$K_CODE = 5; ! Code literal SDA_CIO$K_SHORT_RW = 6; ! Short data (read/write) literal SDA_CIO$K_SHORT_RO = 7; ! Short data (read only) literal SDA_CIO$K_RW = 8; ! Data (read/write) literal SDA_CIO$K_RO = 9; ! Data (read only) literal SDA_CIO$K_SHORT_DZ = 10; ! Short data (dzero) literal SDA_CIO$K_SHORT_TDZ = 11; ! Short data (trail-dzero) literal SDA_CIO$K_DZERO = 12; ! Demand zero literal SDA_CIO$K_TR_DZERO = 13; ! Trailing demand zero literal SDA_CIO$K_UNKNOWN = 14; ! Insert new entries before this literal SDA_CIO$S_COMP_IMG_OFF = 2; macro SDA_CIO$V_VALID = 0,0,1,0 %; ! Set if found an image macro SDA_CIO$V_PROCESS = 0,1,1,0 %; ! Set if this is a process activated image macro SDA_CIO$V_SLICED = 0,2,1,0 %; ! Set if this image is sliced or installed/resident macro SDA_CIO$V_COMPRESSED = 0,3,1,0 %; ! Set if this section is a compressed data section macro SDA_CIO$V_ISD_INDEX = 0,4,12,0 %; literal SDA_CIO$S_ISD_INDEX = 12; ! index into ISD table !*** MODULE $SDA_FLAGSDEF *** literal SDA_FLAGS$M_OVERRIDE = %X'1'; literal SDA_FLAGS$M_CURRENT = %X'2'; literal SDA_FLAGS$M_TARGET = %X'4'; literal SDA_FLAGS$M_PROCESS = %X'8'; literal SDA_FLAGS$M_IA64 = %X'10'; literal SDA_FLAGS$M_REMOTE = %X'20'; literal SDA_FLAGS$K_VERSION = 2; ! SDA Extension interface version literal SDA_FLAGS$S_SDA_FLAGS = 1; macro SDA_FLAGS$V_OVERRIDE = 0,0,1,0 %; ! In override mode macro SDA_FLAGS$V_CURRENT = 0,1,1,0 %; ! Analyzing running system macro SDA_FLAGS$V_TARGET = 0,2,1,0 %; ! Using SCD/SDD macro SDA_FLAGS$V_PROCESS = 0,3,1,0 %; ! Analyzing a process dump macro SDA_FLAGS$V_IA64 = 0,4,1,0 %; ! Analyzing an IA64 dump macro SDA_FLAGS$V_REMOTE = 0,5,1,0 %; ! Analyzing a remote system ! ! Version of SDA extension interface that the extension must match up to. ! Platforms must have a different version so that extensions for one ! platform don't get activated under the cross-platform environment for ! the other platform. ! ! For now, this means Alpha is always an odd number; IA64 an even number. ! !*** MODULE $SDIRDEF *** ! + ! SDIR - SCS DIRECTORY ENTRY ! ! THIS DATA STRUCTURE IS ALLOCATED FOR EACH LOCAL PROCESS THAT WANTS ! TO BE KNOWN TO SCS. ! - literal SDIR$K_LENGTH = 48; literal SDIR$C_LENGTH = 48; literal SDIR$S_SDIRDEF = 48; literal SDIR$S_SDIR = 48; macro SDIR$L_FLINK = 0,0,32,1 %; ! FWD LINK macro SDIR$L_BLINK = 4,0,32,1 %; ! BCK LINK macro SDIR$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro SDIR$B_TYPE = 10,0,8,0 %; ! SCS STRUCTURE TYPE macro SDIR$B_SUBTYP = 11,0,8,0 %; ! SCS STRUCTURE SUBTYPE FOR SDIR macro SDIR$B_PROCNAM = 12,0,0,0 %; literal SDIR$S_PROCNAM = 16; ! ASCII STRING FOR PROCESS NAME macro SDIR$B_PROCINF = 28,0,0,0 %; literal SDIR$S_PROCINF = 16; ! ASCII STRING FOR PROCESS INFO macro SDIR$L_CONID = 44,0,32,0 %; ! CONNECTION ID !*** MODULE $SECLIBDEF *** ! + ! PROCESS OR GLOBAL SECTION DEFINITIONS ! - ! ! ***** L_VBN, L_WINDOW, and L_PFC must be the same offset values as the ! ***** equivalently named offsets in $PFLDEF. ! literal SEC$K_SECLIBDEF = 1; literal SEC$C_SECLIBDEF = 1; !*** MODULE $SDPDEF *** literal SDP$M_LENGTH = %X'7F'; literal SDP$M_WILDCARD = %X'80'; literal SDP$S_SDP_DATA = 20; macro SDP$L_UIC = 0,0,32,0 %; macro SDP$W_MEM = 0,0,16,0 %; macro SDP$W_GRP = 2,0,16,0 %; macro SDP$T_NAME = 4,0,0,0 %; literal SDP$S_NAME = 16; macro SDP$V_LENGTH = 4,0,7,0 %; literal SDP$S_LENGTH = 7; macro SDP$V_WILDCARD = 4,7,1,0 %; macro SDP$T_STRING = 5,0,0,0 %; literal SDP$S_STRING = 15; literal SDP$S_SDP = 32; macro SDP$L_COUNT = 0,0,32,0 %; macro SDP$L_CHECKSUM = 4,0,32,0 %; macro SDP$W_SIZE = 8,0,16,0 %; macro SDP$B_TYPE = 10,0,8,0 %; macro SDP$B_SUBTYPE = 11,0,8,0 %; macro SDP$R_PROCESS = 12,0,0,0 %; literal SDP$S_PROCESS = 20; !*** MODULE $SGNDEF *** ! + ! SYSGEN PARAMETER DEFINITIONS ! - ! literal SGN$C_BALSETCNT = 24; ! NUMBER OF PROCESSES IN BALANCE SET literal SGN$C_DFWSCNT = 100; ! DEFAULT WORKING SET COUNT literal SGN$C_DFWSQUOTA = 120; ! DEFAULT WORKING SET QUOTA literal SGN$C_GBLSECCNT = 40; ! GLOBAL SECTION COUNT literal SGN$C_MAXGPGCNT = 2048; ! GLOBAL PAGE COUNT (GPT SIZE) literal SGN$C_MAXPAGCNT = 16384; ! PHYSICAL MEMORY SIZE IN PAGES literal SGN$C_MAXPGFL = 4096; ! DEFAULT MAXIMUM PAGING FILE literal SGN$C_MAXPSTCNT = 5; ! MAX NUMBER OF PST ENTRIES literal SGN$C_MAXVPGCNT = 8192; ! MAX PROCESS VIRTUAL SIZE (PAGES) literal SGN$C_MAXWSCNT = 1024; ! MAX WORKING SET SIZE (PAGES) literal SGN$C_MINWSCNT = 10; ! MIN WORKING SET SIZE (PAGES) literal SGN$C_NPAGEDYN = 26624; ! NON-PAGED DYNAMIC POOL SIZE literal SGN$C_NPROCS = 64; ! MAX NUMBER OF PROCESSES literal SGN$C_PAGEDYN = 16384; ! PAGED DYNAMIC POOL SIZE IN BYTES literal SGN$C_PHYPAGCNT = 4096; ! ACTUAL PHYSICAL PAGE COUNT literal SGN$C_SYSDWSCNT = 40; ! DEFAULT SYSTEM WORKING SET COUNT literal SGN$C_SYSVECPGS = 5; ! NO. OF PAGES OF SYSTEM SERVICE VECTORS literal SGN$C_SYSWSCNT = 96; ! SYSTEM WORKING SET COUNT ! ! The preceeding may be obsolete as of 11-Nov-1999. I don't see them being used anywhere ! However, the following will be used in SYSPARAM.MAR and possibly other places ! literal SGN$C_NPAGEDYN_MIN = 163840; ! Minimum value for NPAGEDYN literal SGN$C_NPAGEVIR_MIN = 163840; ! Minimum value for NPAGEVIR !*** MODULE $SHADDEF IDENT X-72 *** ! ++ ! VOLUME SHADOWING STRUCTURE DEFINITIONS ! -- ! Minimum number of devices literal SHAD$K_MINDEVS = 1; literal SHAD$C_MINDEVS = 1; ! Minimum number of members literal SHAD$K_MINMBRS = 1; literal SHAD$C_MINMBRS = 1; ! Maximum number of members in this version literal SHAD$K_MAXMBRS = 3; literal SHAD$C_MAXMBRS = 3; ! Duplicate the above ! for SDL local purposes ! Maximum number of members in this version literal SHAD$K_XMAXMBRS = 16; literal SHAD$C_XMAXMBRS = 16; ! Duplicate the above ! for SDL local purposes ! literal SHAD$K_MBRSIZ = 16; literal SHAD$C_MBRSIZ = 16; ! Number of seconds to wait between identical messages literal SHAD$K_MSGWAIT = 60; literal SHAD$C_MSGWAIT = 60; ! Number of I/Os to wait before blasting out an UPDATE_THRESHOLD literal SHAD$K_UPDATE_IO = 10; literal SHAD$C_UPDATE_IO = 10; ! Number of seconds to wait before blasting out an UPDATE_THRESHOLD literal SHAD$K_UPDATE_S = 2; literal SHAD$C_UPDATE_S = 2; ! Number of seconds to retry merge signal locking protocol literal SHAD$K_MRGSIG_RETRY = 100; literal SHAD$C_MRGSIG_RETRY = 100; ! ! For SHD_INIT use. ! ! $SET specified value for V.U. and the the members literal SHADIO$K_TIMEOUT = 11181; literal SHADIO$C_TIMEOUT = 11181; ! $SET specified value for the Virtual Unit literal SHADIO$K_WLG_STATE = 43962; literal SHADIO$C_WLG_STATE = 43962; ! $SET specified value intended for the Fibre Channel devices literal SHADIO$K_SITE_VALUE = 44252; literal SHADIO$C_SITE_VALUE = 44252; ! $SET specified value for Read Bias literal SHADIO$K_READ_BIAS = 142; literal SHADIO$C_READ_BIAS = 142; ! N.B. 143 through 147 are in use, see SHD_INIT module. ! $SET specified value for ODS5 VU literal SHADIO$K_ODS5_VU = 242; literal SHADIO$C_ODS5_VU = 242; ! $SET specified value for Force Removal literal SHADIO$K_FORCE_REMOVE = 342; literal SHADIO$C_FORCE_REMOVE = 342; ! $SET specified value for making a mix of DECram and non-DECram - VOLATILE literal SHADIO$K_VOLATILE = 442; literal SHADIO$C_VOLATILE = 442; ! $SET specified value for forcing copy operation to use master or specific member for read I/O literal SHADIO$K_COPY_SOURCE = 542; literal SHADIO$C_COPY_SOURCE = 542; ! literal SHADIO$K_ABORT_VU = 642; literal SHADIO$C_ABORT_VU = 642; ! literal SHADIO$K_USE_NCA = 742; literal SHADIO$C_USE_NCA = 742; ! literal SHADIO$K_LOCAL_DCD = 842; literal SHADIO$C_LOCAL_DCD = 842; ! literal SHADIO$K_REMOTE_DCD = 942; literal SHADIO$C_REMOTE_DCD = 942; ! literal SHADIO$K_THRESHOLD_BIAS = 1042; literal SHADIO$C_THRESHOLD_BIAS = 1042; ! literal SHADIO$K_THRESHOLD_SECONDS = 1142; literal SHADIO$C_THRESHOLD_SECONDS = 1142; ! literal SHADIO$K_THRESHOLD_IO_COUNT = 1242; literal SHADIO$C_THRESHOLD_IO_COUNT = 1242; ! literal SHADIO$K_STOP_MERGE_AT_LBN = 1342; literal SHADIO$C_STOP_MERGE_AT_LBN = 1342; ! literal SHADIO$K_DEMAND_MERGE = 1442; literal SHADIO$C_DEMAND_MERGE = 1442; ! literal SHADIO$K_NOSTALL_WRITES = 1542; literal SHADIO$C_NOSTALL_WRITES = 1542; ! literal SHADIO$K_STALL_WRITES = 1642; literal SHADIO$C_STALL_WRITES = 1642; ! literal SHADIO$K_TOGGLE_SPLIT_READS = 1742; literal SHADIO$C_TOGGLE_SPLIT_READS = 1742; ! literal SHADIO$K_UPDATE_SCB_LBA = 1842; literal SHADIO$C_UPDATE_SCB_LBA = 1842; ! literal SHADIO$K_MOUNT_DONE = 1942; literal SHADIO$C_MOUNT_DONE = 1942; ! literal SHADIO$K_LOAD_TRPRINT = 2042; literal SHADIO$C_LOAD_TRPRINT = 2042; ! $SET specified value for V.U. and the the members literal SHADIO$K_FCODE_21 = 2142; literal SHADIO$C_FCODE_21 = 2142; ! literal SHADIO$K_QTV_TESTING = 2242; literal SHADIO$C_QTV_TESTING = 2242; ! literal SHADIO$K_DSA_TRPRINT = 2342; literal SHADIO$C_DSA_TRPRINT = 2342; ! literal SHADIO$K_VUCHAR_SL2_HBMM = 2442; literal SHADIO$C_VUCHAR_SL2_HBMM = 2442; ! literal SHADIO$K_FCODE_25 = 2542; literal SHADIO$C_FCODE_25 = 2542; ! literal SHADIO$K_VU_PRIORITY_LEVEL = 2642; literal SHADIO$C_VU_PRIORITY_LEVEL = 2642; ! literal SHADIO$K_VU_DELAY = 2742; literal SHADIO$C_VU_DELAY = 2742; ! literal SHADIO$K_EVALUATE_RESOURCES = 2842; literal SHADIO$C_EVALUATE_RESOURCES = 2842; ! literal SHADIO$K_SRVED_PATH_SSM_DLY = 2942; literal SHADIO$C_SRVED_PATH_SSM_DLY = 2942; ! literal SHADIO$K_SRVED_PATH_SSM_DLY_ALL = 3042; literal SHADIO$C_SRVED_PATH_SSM_DLY_ALL = 3042; ! literal SHADIO$K_VUCHAR_SL2_AMCVP = 3142; literal SHADIO$C_VUCHAR_SL2_AMCVP = 3142; literal SHADIO$K_RESET_COUNTERS = 3242; literal SHADIO$C_RESET_COUNTERS = 3242; literal SHADIO$K_FCODE_33 = 3342; literal SHADIO$C_FCODE_33 = 3342; literal SHADIO$K_VUCHAR_SL2_HBMM_DMT = 3442; literal SHADIO$C_VUCHAR_SL2_HBMM_DMT = 3442; literal SHADIO$K_VUCHAR_SL2_XMBRS = 3542; literal SHADIO$C_VUCHAR_SL2_XMBRS = 3542; literal SH$C_TRANSIENT_STATE_MIGRATION = 268435522; ! 10000042 literal SH$C_DSC_RECOVERY_PENDING = 66; ! 00000042 literal SH$C_SEARCH_FOR_MM_VU = 16962; ! 00004242 literal SH$C_SEARCH_FOR_ANY_VU = 4342338; ! 00424242 literal SH$C_PLAY_IT_AGAIN_SAM = 8; literal SH$C_PLAY_IT_ONCE_SAM = 16; ! literal SHADIO$K_Trace_1 = 4201; literal SHADIO$C_Trace_1 = 4201; ! literal SHADIO$K_Trace_2 = 4202; literal SHADIO$C_Trace_2 = 4202; ! literal SHADIO$K_Trace_3 = 4203; literal SHADIO$C_Trace_3 = 4203; ! literal SHADIO$K_Trace_4 = 4204; literal SHADIO$C_Trace_4 = 4204; ! literal SHADIO$K_Trace_5 = 4205; literal SHADIO$C_Trace_5 = 4205; ! literal SHADIO$K_Trace_6 = 4206; literal SHADIO$C_Trace_6 = 4206; ! literal SHADIO$K_Trace_7 = 4207; literal SHADIO$C_Trace_7 = 4207; ! literal SHADIO$K_Trace_8 = 4208; literal SHADIO$C_Trace_8 = 4208; ! literal SHADIO$K_Trace_9 = 4209; literal SHADIO$C_Trace_9 = 4209; ! Number of bits in the member status ! fields used to determine copy type ! CLU$C_MAX_NODES ! For Alpha literal LOCK$M_DEQUEUE = %X'1'; literal LOCK$M_WATCHER = %X'2'; literal LOCK$M_VALUE_UPDATE = %X'4'; literal LOCK$M_MBR_CHANGE_HERE = %X'8'; literal LOCK$M_COPY_ACTIVE = %X'10'; literal LOCK$M_STALL = %X'20'; literal LOCK$M_STALL_IP = %X'40'; literal LOCK$M_LOCAL = %X'80'; literal LOCK$M_RELEASE_COPIER_LOCK = %X'100'; literal LOCK$M_WATCHR_DONE = %X'200'; literal LOCK$M_SSM_EXPELLED = %X'400'; literal LOCK$M_BIT11 = %X'800'; literal LOCK$M_BIT12 = %X'1000'; literal LOCK$M_WLG_FINI_RTN_NORMAL = %X'2000'; literal LOCK$M_HBMM_FINI_RTN_NORMAL = %X'4000'; literal LOCK$M_SKIP = %X'8000'; literal LOCK$M_OPTIMAL_HBMM_DELAY_DUE = %X'1000000'; literal LOCK$M_BIT25 = %X'2000000'; literal LOCK$M_COPIER_LOCK_RELEASED = %X'4000000'; literal LOCK$M_DCL_DEMAND_MERGE = %X'8000000'; literal LOCK$M_REQUEST_VUCHAR_INQUIRY = %X'10000000'; literal LOCK$M_TRANSIENT_SET_DISMOUNTED = %X'20000000'; literal LOCK$M_EVALUATE_PRIORITY_QUEUE = %X'40000000'; literal LOCK$M_MERGE_SIGNAL_REQUEST = %X'80000000'; literal LOCK$K_LENGTH = 136; ! Length of Structure literal LOCK$C_LENGTH = 136; ! Length of Structure literal LOCK$S_LOCK = 136; ! Lock substructure macro LOCK$B_RESNAM_STR = 0,0,0,0 %; literal LOCK$S_RESNAM_STR = 32; ! Resource name string macro LOCK$Q_RESNAM = 32,0,0,0 %; literal LOCK$S_RESNAM = 8; ! Resource name descriptor macro LOCK$L_FLINK = 40,0,32,0 %; ! CDRP queue Forward link macro LOCK$L_BLINK = 44,0,32,0 %; ! CDRP Queue Backward link macro LOCK$L_BLKADR = 48,0,32,0 %; ! Blocking address for function macro LOCK$L_LKSB = 52,0,32,0 %; ! Lock status block base macro LOCK$L_LKID = 56,0,32,0 %; ! Lock ID macro LOCK$L_LKVALBLK = 60,0,0,0 %; literal LOCK$S_LKVALBLK = 64; ! Lock value block macro LOCK$L_LOCK_STATE = 124,0,32,0 %; ! macro LOCK$B_STATE = 124,0,8,0 %; ! Lock state semaphore macro LOCK$L_SHAD = 128,0,32,1 %; ! Points to the shad for this lock structure macro LOCK$L_CTXB = 132,0,32,1 %; ! Pointer to context block macro LOCK$V_DEQUEUE = 132,0,1,0 %; ! DEQUEUE in progress macro LOCK$V_WATCHER = 132,1,1,0 %; ! Watcher node macro LOCK$V_VALUE_UPDATE = 132,2,1,0 %; ! Watcher value update node macro LOCK$V_MBR_CHANGE_HERE = 132,3,1,0 %; ! Set change in progress macro LOCK$V_COPY_ACTIVE = 132,4,1,0 %; ! EX mode on copier lock macro LOCK$V_STALL = 132,5,1,0 %; ! Lock does stalls macro LOCK$V_STALL_IP = 132,6,1,0 %; ! Stall new requests until NL macro LOCK$V_LOCAL = 132,7,1,0 %; ! Local validation in progress ! macro LOCK$V_RELEASE_COPIER_LOCK = 132,8,1,0 %; ! Causes merge or copy thread to return _CANCEL to Shadow Server ! which will release the COPIER lock on this system macro LOCK$V_WATCHR_DONE = 132,9,1,0 %; ! macro LOCK$V_SSM_EXPELLED = 132,10,1,0 %; ! ( %X00000400 ) macro LOCK$V_BIT11 = 132,11,1,0 %; ! ( %X00000800 ) macro LOCK$V_BIT12 = 132,12,1,0 %; ! ( %X00001000 ) macro LOCK$V_WLG_FINI_RTN_NORMAL = 132,13,1,0 %; ! ( %X00002000 ) Causes thread to return mini merge state,,SS$_NORMAL to Shadow Ser ! which will release the _COPIER lock on this system macro LOCK$V_HBMM_FINI_RTN_NORMAL = 132,14,1,0 %; ! ( %X00004000 ) Causes thread to return mini merge state,,SS$_NORMAL to Shadow Se ! which will release the _COPIER lock on this system macro LOCK$V_SKIP = 132,15,1,0 %; ! ( %X00008000 ) Skip tracing this lock macro LOCK$V_OPTIMAL_HBMM_DELAY_DUE = 132,24,1,0 %; ! ( %X01000000 ) macro LOCK$V_BIT25 = 132,25,1,0 %; ! ( %X02000000 ) macro LOCK$V_COPIER_LOCK_RELEASED = 132,26,1,0 %; ! Tell other nodes copier lock has been released macro LOCK$V_DCL_DEMAND_MERGE = 132,27,1,0 %; ! User requests a demand merge be done on a shadowset macro LOCK$V_REQUEST_VUCHAR_INQUIRY = 132,28,1,0 %; ! See if requested characteristic is possible macro LOCK$V_TRANSIENT_SET_DISMOUNTED = 132,29,1,0 %; ! Used by a system that is managing a VU in a transient state to ! notify other systems that they are DISMOUNTing it macro LOCK$V_EVALUATE_PRIORITY_QUEUE = 132,30,1,0 %; ! Used by systems when they need to manage the priority queue macro LOCK$V_MERGE_SIGNAL_REQUEST = 132,31,1,0 %; ! Used by merge signal to request a VU be put into a merge ! transient state ... when they abort a VU ! For Alpha literal SH$M_SHADOW_SYSTEM_DISK = %X'1'; literal SH$M_MINI_MERGE_SYSTEM_DISK = %X'2'; literal SH$M_HOST_COMPARE_ALL_WRITES = %X'4'; literal SH$M_IF_3_IS_SET = %X'8'; literal SH$M_IF_4_IS_SET = %X'10'; literal SH$M_IF_5_IS_SET = %X'20'; literal SH$M_IF_6_IS_SET = %X'40'; literal SH$M_IF_7_IS_SET = %X'80'; literal SH$M_IF_8_IS_SET = %X'100'; literal SH$M_IF_9_IS_SET = %X'200'; literal SH$M_IF_10_IS_SET = %X'400'; literal SH$M_SYSGEN_DISABLE_WLG = %X'800'; literal SH$M_MINIMERGE_SYSTEM_DISK = %X'1000'; literal SH$M_NO_BAD_BLOCK_RECOVERY = %X'2000'; literal SH$M_ENABLE_LOG_IT = %X'4000'; literal SH$M_SET_INHIBIT_RETRY = %X'8000'; literal SH$M_ENFORCE_LOCAL_READ = %X'10000'; literal SH$M_DONOT_ENFORCE_MC = %X'20000'; literal SH$M_ENABLE_HBVSTrace_All = %X'40000'; literal SH$M_USE_VU_UNIT_NUMBER = %X'80000'; literal SH$M_BIT20 = %X'100000'; literal SH$M_BIT21 = %X'200000'; literal SH$M_BIT22 = %X'400000'; literal SH$M_BIT23 = %X'800000'; literal SH$M_IF_24_IS_SET = %X'1000000'; literal SH$M_IF_25_IS_SET = %X'2000000'; literal SH$M_BUGCHECK_ABORT = %X'4000000'; literal SH$M_BUGCHECK_INCSHAMEM = %X'8000000'; literal SH$M_BUGCHECK_IF_28_IS_SET = %X'10000000'; literal SH$M_BUGCHECK_IF_29_IS_SET = %X'20000000'; literal SH$M_BUGCHECK_ABORT_VP = %X'40000000'; literal SH$M_BUGCHECK_NEG_RWAIT = %X'80000000'; literal SH$S_SYSDISK = 4; ! SHADOW_SYS_DISK Bit Mask definitions macro SH$L_SYSTEM_DISK_MASK = 0,0,32,0 %; macro SH$V_SHADOW_SYSTEM_DISK = 0,0,1,0 %; ! ( %X00000001 ) The historical request macro SH$V_MINI_MERGE_SYSTEM_DISK = 0,1,1,0 %; ! ( %X00000002 ) DOSD makes this possible new bit macro SH$V_HOST_COMPARE_ALL_WRITES = 0,2,1,0 %; ! ( %X00000004 ) for the truly paranoid macro SH$V_IF_3_IS_SET = 0,3,1,0 %; ! ( %X00000008 ) macro SH$V_IF_4_IS_SET = 0,4,1,0 %; ! ( %X00000010 ) macro SH$V_IF_5_IS_SET = 0,5,1,0 %; ! ( %X00000020 ) macro SH$V_IF_6_IS_SET = 0,6,1,0 %; ! ( %X00000040 ) macro SH$V_IF_7_IS_SET = 0,7,1,0 %; ! ( %X00000080 ) macro SH$V_IF_8_IS_SET = 0,8,1,0 %; ! ( %X00000100 ) macro SH$V_IF_9_IS_SET = 0,9,1,0 %; ! ( %X00000200 ) macro SH$V_IF_10_IS_SET = 0,10,1,0 %; ! ( %X00000400 ) macro SH$V_SYSGEN_DISABLE_WLG = 0,11,1,0 %; ! ( %X00000800 ) Don't allow phase 1 write logging on this system ! The next three bits MUST maintain these positions ! to maintain historical definitions macro SH$V_MINIMERGE_SYSTEM_DISK = 0,12,1,0 %; ! ( %X00001000 ) DOSD makes this possible ... historical bit macro SH$V_NO_BAD_BLOCK_RECOVERY = 0,13,1,0 %; ! ( %X00002000 ) Aggressive member removal macro SH$V_ENABLE_LOG_IT = 0,14,1,0 %; ! ( %X00004000 ) Enable LOG_IT macro macro SH$V_SET_INHIBIT_RETRY = 0,15,1,0 %; ! ( %X00008000 ) For special application I/Os macro SH$V_ENFORCE_LOCAL_READ = 0,16,1,0 %; ! ( %X00010000 ) Force local reads, for FDDI clusters macro SH$V_DONOT_ENFORCE_MC = 0,17,1,0 %; ! ( %X00020000 ) macro SH$V_ENABLE_HBVSTrace_All = 0,18,1,0 %; ! ( %X00040000 ) macro SH$V_USE_VU_UNIT_NUMBER = 0,19,1,0 %; ! ( %X00080000 ) macro SH$V_BIT20 = 0,20,1,0 %; ! ( %X00100000 ) macro SH$V_BIT21 = 0,21,1,0 %; ! ( %X00200000 ) macro SH$V_BIT22 = 0,22,1,0 %; ! ( %X00400000 ) macro SH$V_BIT23 = 0,23,1,0 %; ! ( %X00800000 ) macro SH$V_IF_24_IS_SET = 0,24,1,0 %; ! ( %X01000000 ) macro SH$V_IF_25_IS_SET = 0,25,1,0 %; ! ( %X02000000 ) macro SH$V_BUGCHECK_ABORT = 0,26,1,0 %; ! ( %X04000000 ) On ss$_abort crash now macro SH$V_BUGCHECK_INCSHAMEM = 0,27,1,0 %; ! ( %X08000000 ) macro SH$V_BUGCHECK_IF_28_IS_SET = 0,28,1,0 %; ! ( %X10000000 ) macro SH$V_BUGCHECK_IF_29_IS_SET = 0,29,1,0 %; ! ( %X20000000 ) macro SH$V_BUGCHECK_ABORT_VP = 0,30,1,0 %; ! ( %X40000000 ) On ABORT_VP crash now macro SH$V_BUGCHECK_NEG_RWAIT = 0,31,1,0 %; ! ( %X80000000 ) If RWAITCNT goes negative, crash now ! ! Shadow set VU characteristics ($VUCHAR) lock value block definitions ! ! Each set bit represents a per-VU characteristic that is currently enabled ! on that VU. A cluster member is not allowed to MOUNT a VU unless it has ! support for all the currently enabled characteristics on that VU. ! The mask of characteristics that are supported by this node is in ! EXE$GQ_SHADOW_CAPABILITIES. ! ! Any change in the enabled VU characteristics on a mounted VU requires ! unanimous consent of all the nodes where the VU is mounted. This is obtained ! using the VU characteristics voting protocol. ! ! NOTE: Prior versions used the SHMASK$M_MINI_COPY, DVE_DDS, and HBMM bit ! masks to set the VU characteristics lock value block. Therefore, to maintain ! cluster compatibility, the definitions of each of the corresponding ! SHAD_VUCHAR$M_ bits must have the same value. ! literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT0 = %X'1'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT1 = %X'2'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT2 = %X'4'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT3 = %X'8'; literal SHAD_VUCHAR$M_MINI_COPY = %X'10'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT5 = %X'20'; literal SHAD_VUCHAR$M_DVE_DDS = %X'40'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT7 = %X'80'; literal SHAD_VUCHAR$M_HBMM = %X'100'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT9 = %X'200'; literal SHAD_VUCHAR$M_AMCVP = %X'400'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT11 = %X'800'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT12 = %X'1000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT13 = %X'2000'; literal SHAD_VUCHAR$M_HBMM_DMT = %X'4000'; literal SHAD_VUCHAR$M_VERIFY_NEW_MBR = %X'8000'; literal SHAD_VUCHAR$M_XMBRS = %X'10000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT17 = %X'20000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT18 = %X'40000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT19 = %X'80000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT20 = %X'100000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT21 = %X'200000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT22 = %X'400000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT23 = %X'800000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT24 = %X'1000000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT25 = %X'2000000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT26 = %X'4000000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT27 = %X'8000000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT28 = %X'10000000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT29 = %X'20000000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT30 = %X'40000000'; literal SHAD_VUCHAR$M_SHADOW_CHAR_BIT31 = %X'80000000'; literal SHAD_VUCHAR$S_SHAD_VUCHAR = 4; macro SHAD_VUCHAR$L_SHADOW_CHAR_MASK = 0,0,32,0 %; ! SHADOW_CHAR Bit Mask definitions macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT0 = 0,0,1,0 %; ! ( %X00000001 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT1 = 0,1,1,0 %; ! ( %X00000002 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT2 = 0,2,1,0 %; ! ( %X00000004 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT3 = 0,3,1,0 %; ! ( %X00000008 ) macro SHAD_VUCHAR$V_MINI_COPY = 0,4,1,0 %; ! ( %X00000010 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT5 = 0,5,1,0 %; ! ( %X00000020 ) macro SHAD_VUCHAR$V_DVE_DDS = 0,6,1,0 %; ! ( %X00000040 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT7 = 0,7,1,0 %; ! ( %X00000080 ) macro SHAD_VUCHAR$V_HBMM = 0,8,1,0 %; ! ( %X00000100 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT9 = 0,9,1,0 %; ! ( %X00000200 ) macro SHAD_VUCHAR$V_AMCVP = 0,10,1,0 %; ! ( %X00000400 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT11 = 0,11,1,0 %; ! ( %X00000800 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT12 = 0,12,1,0 %; ! ( %X00001000 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT13 = 0,13,1,0 %; ! ( %X00002000 ) macro SHAD_VUCHAR$V_HBMM_DMT = 0,14,1,0 %; ! ( %X00004000 ) macro SHAD_VUCHAR$V_VERIFY_NEW_MBR = 0,15,1,0 %; ! ( %X00008000 ) macro SHAD_VUCHAR$V_XMBRS = 0,16,1,0 %; ! ( %X00010000 ) ! ! All of the rest of the character bits may already be used by ! SHD_RELEASE_FLAG.MAR - so use these carefully! ! macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT17 = 0,17,1,0 %; ! ( %X00020000 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT18 = 0,18,1,0 %; ! ( %X00040000 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT19 = 0,19,1,0 %; ! ( %X00080000 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT20 = 0,20,1,0 %; ! ( %X00100000 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT21 = 0,21,1,0 %; ! ( %X00200000 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT22 = 0,22,1,0 %; ! ( %X00400000 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT23 = 0,23,1,0 %; ! ( %X00800000 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT24 = 0,24,1,0 %; ! ( %X01000000 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT25 = 0,25,1,0 %; ! ( %X02000000 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT26 = 0,26,1,0 %; ! ( %X04000000 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT27 = 0,27,1,0 %; ! ( %X08000000 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT28 = 0,28,1,0 %; ! ( %X10000000 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT29 = 0,29,1,0 %; ! ( %X20000000 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT30 = 0,30,1,0 %; ! ( %X40000000 ) macro SHAD_VUCHAR$V_SHADOW_CHAR_BIT31 = 0,31,1,0 %; ! ( %X80000000 ) ! For NotVAX literal SHADD1$M_BIT0 = %X'1'; literal SHADD1$M_BIT1 = %X'2'; literal SHADD1$M_BIT2 = %X'4'; literal SHADD1$M_BIT3 = %X'8'; literal SHADD1$M_BIT4 = %X'10'; literal SHADD1$M_BIT5 = %X'20'; literal SHADD1$M_BIT6 = %X'40'; literal SHADD1$M_BIT7 = %X'80'; literal SHADD1$M_BIT8 = %X'100'; literal SHADD1$M_BIT9 = %X'200'; literal SHADD1$M_BIT10 = %X'400'; literal SHADD1$M_BIT11 = %X'800'; literal SHADD1$M_BIT12 = %X'1000'; literal SHADD1$M_BIT13 = %X'2000'; literal SHADD1$M_BIT14 = %X'4000'; literal SHADD1$M_BIT15 = %X'8000'; literal SHADD1$M_IF_16_IS_CLEAR = %X'10000'; literal SHADD1$M_IF_17_IS_CLEAR = %X'20000'; literal SHADD1$M_IF_18_IS_CLEAR = %X'40000'; literal SHADD1$M_IF_19_IS_CLEAR = %X'80000'; literal SHADD1$M_IF_20_IS_CLEAR = %X'100000'; literal SHADD1$M_IF_21_IS_CLEAR = %X'200000'; literal SHADD1$M_IF_22_IS_CLEAR = %X'400000'; literal SHADD1$M_IF_23_IS_CLEAR = %X'800000'; literal SHADD1$M_IF_24_IS_SET = %X'1000000'; literal SHADD1$M_IF_25_IS_SET = %X'2000000'; literal SHADD1$M_IF_26_IS_SET = %X'4000000'; literal SHADD1$M_IF_27_IS_SET = %X'8000000'; literal SHADD1$M_IF_28_IS_SET = %X'10000000'; literal SHADD1$M_IF_29_IS_SET = %X'20000000'; literal SHADD1$M_IF_30_IS_SET = %X'40000000'; literal SHADD1$M_IF_31_IS_SET = %X'80000000'; literal SHADD1$S_SHADOWD1 = 4; ! SHADOW_D1 Bit Mask definitions macro SHADD1$L_SHADOW_D1_MASK = 0,0,32,0 %; macro SHADD1$V_BIT0 = 0,0,1,0 %; ! ( %X00000001 ) macro SHADD1$V_BIT1 = 0,1,1,0 %; ! ( %X00000002 ) macro SHADD1$V_BIT2 = 0,2,1,0 %; ! ( %X00000004 ) macro SHADD1$V_BIT3 = 0,3,1,0 %; ! ( %X00000008 ) macro SHADD1$V_BIT4 = 0,4,1,0 %; ! ( %X00000010 ) macro SHADD1$V_BIT5 = 0,5,1,0 %; ! ( %X00000020 ) macro SHADD1$V_BIT6 = 0,6,1,0 %; ! ( %X00000040 ) macro SHADD1$V_BIT7 = 0,7,1,0 %; ! ( %X00000080 ) macro SHADD1$V_BIT8 = 0,8,1,0 %; ! ( %X00000100 ) macro SHADD1$V_BIT9 = 0,9,1,0 %; ! ( %X00000200 ) macro SHADD1$V_BIT10 = 0,10,1,0 %; ! ( %X00000400 ) macro SHADD1$V_BIT11 = 0,11,1,0 %; ! ( %X00000800 ) macro SHADD1$V_BIT12 = 0,12,1,0 %; ! ( %X00001000 ) macro SHADD1$V_BIT13 = 0,13,1,0 %; ! ( %X00002000 ) macro SHADD1$V_BIT14 = 0,14,1,0 %; ! ( %X00004000 ) macro SHADD1$V_BIT15 = 0,15,1,0 %; ! ( %X00008000 ) macro SHADD1$V_IF_16_IS_CLEAR = 0,16,1,0 %; ! ( %X00010000 ) macro SHADD1$V_IF_17_IS_CLEAR = 0,17,1,0 %; ! ( %X00020000 ) macro SHADD1$V_IF_18_IS_CLEAR = 0,18,1,0 %; ! ( %X00040000 ) macro SHADD1$V_IF_19_IS_CLEAR = 0,19,1,0 %; ! ( %X00080000 ) macro SHADD1$V_IF_20_IS_CLEAR = 0,20,1,0 %; ! ( %X00100000 ) macro SHADD1$V_IF_21_IS_CLEAR = 0,21,1,0 %; ! ( %X00200000 ) macro SHADD1$V_IF_22_IS_CLEAR = 0,22,1,0 %; ! ( %X00400000 ) macro SHADD1$V_IF_23_IS_CLEAR = 0,23,1,0 %; ! ( %X00800000 ) macro SHADD1$V_IF_24_IS_SET = 0,24,1,0 %; ! ( %X01000000 ) macro SHADD1$V_IF_25_IS_SET = 0,25,1,0 %; ! ( %X02000000 ) macro SHADD1$V_IF_26_IS_SET = 0,26,1,0 %; ! ( %X04000000 ) macro SHADD1$V_IF_27_IS_SET = 0,27,1,0 %; ! ( %X08000000 ) macro SHADD1$V_IF_28_IS_SET = 0,28,1,0 %; ! ( %X10000000 ) macro SHADD1$V_IF_29_IS_SET = 0,29,1,0 %; ! ( %X20000000 ) macro SHADD1$V_IF_30_IS_SET = 0,30,1,0 %; ! ( %X40000000 ) macro SHADD1$V_IF_31_IS_SET = 0,31,1,0 %; ! ( %X80000000 ) literal SHADD5$M_ENABLE_TRACING_BIT0 = %X'1'; literal SHADD5$M_ENABLE_TRACING_BIT1 = %X'2'; literal SHADD5$M_ENABLE_TRACING_BIT2 = %X'4'; literal SHADD5$M_ENABLE_TRACING_BIT3 = %X'8'; literal SHADD5$M_ENABLE_TRACING_BIT4 = %X'10'; literal SHADD5$M_ENABLE_TRACING_BIT5 = %X'20'; literal SHADD5$M_ENABLE_TRACING_BIT6 = %X'40'; literal SHADD5$M_ENABLE_TRACING_BIT7 = %X'80'; literal SHADD5$M_BIT8 = %X'100'; literal SHADD5$M_BIT9 = %X'200'; literal SHADD5$M_BIT10 = %X'400'; literal SHADD5$M_BIT11 = %X'800'; literal SHADD5$M_BIT12 = %X'1000'; literal SHADD5$M_BIT13 = %X'2000'; literal SHADD5$M_BIT14 = %X'4000'; literal SHADD5$M_BIT15 = %X'8000'; literal SHADD5$M_IF_16_IS_CLEAR = %X'10000'; literal SHADD5$M_IF_17_IS_CLEAR = %X'20000'; literal SHADD5$M_IF_18_IS_CLEAR = %X'40000'; literal SHADD5$M_IF_19_IS_CLEAR = %X'80000'; literal SHADD5$M_IF_20_IS_CLEAR = %X'100000'; literal SHADD5$M_IF_21_IS_CLEAR = %X'200000'; literal SHADD5$M_IF_22_IS_CLEAR = %X'400000'; literal SHADD5$M_IF_23_IS_CLEAR = %X'800000'; literal SHADD5$M_IF_24_IS_SET = %X'1000000'; literal SHADD5$M_IF_25_IS_SET = %X'2000000'; literal SHADD5$M_IF_26_IS_SET = %X'4000000'; literal SHADD5$M_IF_27_IS_SET = %X'8000000'; literal SHADD5$M_IF_28_IS_SET = %X'10000000'; literal SHADD5$M_IF_29_IS_SET = %X'20000000'; literal SHADD5$M_IF_30_IS_SET = %X'40000000'; literal SHADD5$M_IF_31_IS_SET = %X'80000000'; literal SHADD5$S_SHADOWD5 = 4; ! SHADOW_D5 Bit Mask definitions macro SHADD5$L_SHADOW_D5_MASK = 0,0,32,0 %; macro SHADD5$V_ENABLE_TRACING_BIT0 = 0,0,1,0 %; ! ( %X00000001 ) macro SHADD5$V_ENABLE_TRACING_BIT1 = 0,1,1,0 %; ! ( %X00000002 ) macro SHADD5$V_ENABLE_TRACING_BIT2 = 0,2,1,0 %; ! ( %X00000004 ) macro SHADD5$V_ENABLE_TRACING_BIT3 = 0,3,1,0 %; ! ( %X00000008 ) macro SHADD5$V_ENABLE_TRACING_BIT4 = 0,4,1,0 %; ! ( %X00000010 ) macro SHADD5$V_ENABLE_TRACING_BIT5 = 0,5,1,0 %; ! ( %X00000020 ) macro SHADD5$V_ENABLE_TRACING_BIT6 = 0,6,1,0 %; ! ( %X00000040 ) macro SHADD5$V_ENABLE_TRACING_BIT7 = 0,7,1,0 %; ! ( %X00000080 ) macro SHADD5$V_BIT8 = 0,8,1,0 %; ! ( %X00000100 ) macro SHADD5$V_BIT9 = 0,9,1,0 %; ! ( %X00000200 ) macro SHADD5$V_BIT10 = 0,10,1,0 %; ! ( %X00000400 ) macro SHADD5$V_BIT11 = 0,11,1,0 %; ! ( %X00000800 ) macro SHADD5$V_BIT12 = 0,12,1,0 %; ! ( %X00001000 ) macro SHADD5$V_BIT13 = 0,13,1,0 %; ! ( %X00002000 ) macro SHADD5$V_BIT14 = 0,14,1,0 %; ! ( %X00004000 ) macro SHADD5$V_BIT15 = 0,15,1,0 %; ! ( %X00008000 ) macro SHADD5$V_IF_16_IS_CLEAR = 0,16,1,0 %; ! ( %X00010000 ) macro SHADD5$V_IF_17_IS_CLEAR = 0,17,1,0 %; ! ( %X00020000 ) macro SHADD5$V_IF_18_IS_CLEAR = 0,18,1,0 %; ! ( %X00040000 ) macro SHADD5$V_IF_19_IS_CLEAR = 0,19,1,0 %; ! ( %X00080000 ) macro SHADD5$V_IF_20_IS_CLEAR = 0,20,1,0 %; ! ( %X00100000 ) macro SHADD5$V_IF_21_IS_CLEAR = 0,21,1,0 %; ! ( %X00200000 ) macro SHADD5$V_IF_22_IS_CLEAR = 0,22,1,0 %; ! ( %X00400000 ) macro SHADD5$V_IF_23_IS_CLEAR = 0,23,1,0 %; ! ( %X00800000 ) macro SHADD5$V_IF_24_IS_SET = 0,24,1,0 %; ! ( %X01000000 ) macro SHADD5$V_IF_25_IS_SET = 0,25,1,0 %; ! ( %X02000000 ) macro SHADD5$V_IF_26_IS_SET = 0,26,1,0 %; ! ( %X04000000 ) macro SHADD5$V_IF_27_IS_SET = 0,27,1,0 %; ! ( %X08000000 ) macro SHADD5$V_IF_28_IS_SET = 0,28,1,0 %; ! ( %X10000000 ) macro SHADD5$V_IF_29_IS_SET = 0,29,1,0 %; ! ( %X20000000 ) macro SHADD5$V_IF_30_IS_SET = 0,30,1,0 %; ! ( %X40000000 ) macro SHADD5$V_IF_31_IS_SET = 0,31,1,0 %; ! ( %X80000000 ) literal SHADEN$M_NEW_WBM_NAMES_IN_USE = %X'1'; literal SHADEN$M_BIT1 = %X'2'; literal SHADEN$M_BIT2 = %X'4'; literal SHADEN$M_BIT3 = %X'8'; literal SHADEN$M_BIT4 = %X'10'; literal SHADEN$M_BIT5 = %X'20'; literal SHADEN$M_BIT6 = %X'40'; literal SHADEN$M_BIT7 = %X'80'; literal SHADEN$M_BIT8 = %X'100'; literal SHADEN$M_BIT9 = %X'200'; literal SHADEN$M_BIT10 = %X'400'; literal SHADEN$M_BIT11 = %X'800'; literal SHADEN$M_BIT12 = %X'1000'; literal SHADEN$M_BIT13 = %X'2000'; literal SHADEN$M_BIT14 = %X'4000'; literal SHADEN$M_BIT15 = %X'8000'; literal SHADEN$M_BIT16 = %X'10000'; literal SHADEN$M_BIT17 = %X'20000'; literal SHADEN$M_BIT18 = %X'40000'; literal SHADEN$M_BIT19 = %X'80000'; literal SHADEN$M_BIT20 = %X'100000'; literal SHADEN$M_BIT21 = %X'200000'; literal SHADEN$M_BIT22 = %X'400000'; literal SHADEN$M_BIT23 = %X'800000'; literal SHADEN$M_BIT24 = %X'1000000'; literal SHADEN$M_BIT25 = %X'2000000'; literal SHADEN$M_BIT26 = %X'4000000'; literal SHADEN$M_BIT27 = %X'8000000'; literal SHADEN$M_BIT28 = %X'10000000'; literal SHADEN$M_BIT29 = %X'20000000'; literal SHADEN$M_BIT30 = %X'40000000'; literal SHADEN$M_BIT31 = %X'80000000'; literal SHADEN$S_SHADOWEN = 4; ! SHADOW_ENABLE Bit Mask definitions macro SHADEN$L_SHADOW_EN_MASK = 0,0,32,0 %; macro SHADEN$V_NEW_WBM_NAMES_IN_USE = 0,0,1,0 %; ! ( %X00000001 ) macro SHADEN$V_BIT1 = 0,1,1,0 %; ! ( %X00000002 ) macro SHADEN$V_BIT2 = 0,2,1,0 %; ! ( %X00000004 ) macro SHADEN$V_BIT3 = 0,3,1,0 %; ! ( %X00000008 ) macro SHADEN$V_BIT4 = 0,4,1,0 %; ! ( %X00000010 ) macro SHADEN$V_BIT5 = 0,5,1,0 %; ! ( %X00000020 ) macro SHADEN$V_BIT6 = 0,6,1,0 %; ! ( %X00000040 ) macro SHADEN$V_BIT7 = 0,7,1,0 %; ! ( %X00000080 ) macro SHADEN$V_BIT8 = 0,8,1,0 %; ! ( %X00000100 ) macro SHADEN$V_BIT9 = 0,9,1,0 %; ! ( %X00000200 ) macro SHADEN$V_BIT10 = 0,10,1,0 %; ! ( %X00000400 ) macro SHADEN$V_BIT11 = 0,11,1,0 %; ! ( %X00000800 ) macro SHADEN$V_BIT12 = 0,12,1,0 %; ! ( %X00001000 ) macro SHADEN$V_BIT13 = 0,13,1,0 %; ! ( %X00002000 ) macro SHADEN$V_BIT14 = 0,14,1,0 %; ! ( %X00004000 ) macro SHADEN$V_BIT15 = 0,15,1,0 %; ! ( %X00008000 ) macro SHADEN$V_BIT16 = 0,16,1,0 %; ! ( %X00010000 ) macro SHADEN$V_BIT17 = 0,17,1,0 %; ! ( %X00020000 ) macro SHADEN$V_BIT18 = 0,18,1,0 %; ! ( %X00040000 ) macro SHADEN$V_BIT19 = 0,19,1,0 %; ! ( %X00080000 ) macro SHADEN$V_BIT20 = 0,20,1,0 %; ! ( %X00100000 ) macro SHADEN$V_BIT21 = 0,21,1,0 %; ! ( %X00200000 ) macro SHADEN$V_BIT22 = 0,22,1,0 %; ! ( %X00400000 ) macro SHADEN$V_BIT23 = 0,23,1,0 %; ! ( %X00800000 ) macro SHADEN$V_BIT24 = 0,24,1,0 %; ! ( %X01000000 ) macro SHADEN$V_BIT25 = 0,25,1,0 %; ! ( %X02000000 ) macro SHADEN$V_BIT26 = 0,26,1,0 %; ! ( %X04000000 ) macro SHADEN$V_BIT27 = 0,27,1,0 %; ! ( %X08000000 ) macro SHADEN$V_BIT28 = 0,28,1,0 %; ! ( %X10000000 ) macro SHADEN$V_BIT29 = 0,29,1,0 %; ! ( %X20000000 ) macro SHADEN$V_BIT30 = 0,30,1,0 %; ! ( %X40000000 ) macro SHADEN$V_BIT31 = 0,31,1,0 %; ! ( %X80000000 ) ! For Alpha literal MC_WBM$C_HEADER = 12; literal MC_WBM$C_DDS_SIZE = 27; literal MC_WBM$C_I_LIST_BFR = 128; literal MC_WBM$C_ConVert_Buffer = 256; literal MC_WBM$K_LENGTH = 512; ! Length of Structure literal MC_WBM$C_LENGTH = 512; ! Length of Structure literal MC_WBM$S_MCWBM = 512; macro MC_WBM$L_FLINK = 0,0,32,0 %; ! Forward link FIELD macro MC_WBM$L_BLINK = 4,0,32,0 %; ! Backward link FIELD macro MC_WBM$L_SIZE_TYPE = 8,0,32,0 %; ! Size/Type of structure ! ! Name of buffer as derived from the SCB meta data. ! macro MC_WBM$L_DDS = 12,0,32,0 %; ! Size of string passed here macro MC_WBM$L_ADDR_OF_STRING = 16,0,32,0 %; ! Address of the string passed here macro MC_WBM$B_THE_STRING = 20,0,8,0 %; ! macro MC_WBM$L_STRING_PREFIX = 21,0,32,0 %; ! macro MC_WBM$L_SCB_STRING = 25,0,32,0 %; ! ! ! Item List buffer. ! macro MC_WBM$L_FLINK1 = 128,0,32,0 %; ! Forward link FIELD macro MC_WBM$L_BLINK1 = 132,0,32,0 %; ! Backward link FIELD macro MC_WBM$L_SIZE_TYPE1 = 136,0,32,0 %; ! Size/Type of structure macro MC_WBM$W_ITEM_LIST_BFR_SIZE = 140,0,16,0 %; ! In number of Bytes macro MC_WBM$W_ITEM_LIST_ARG = 142,0,16,0 %; ! #3 returns the handle macro MC_WBM$L_ADDR_OF_ITEM_LIST = 144,0,32,0 %; ! Address of the buffer passed here macro MC_WBM$L_ADDR_OF_BCNT_RTN = 148,0,32,0 %; ! macro MC_WBM$L_END_OF_ITEM_LIST = 152,0,32,0 %; ! macro MC_WBM$L_ITEM_LIST_BCNT_RTN = 156,0,32,0 %; ! macro MC_WBM$L_ITEM_LIST = 160,0,32,0 %; ! ! ! Convert Device Name ! macro MC_WBM$L_FLINK2 = 256,0,32,0 %; ! Forward link FIELD macro MC_WBM$L_BLINK2 = 260,0,32,0 %; ! Backward link FIELD macro MC_WBM$L_SIZE_TYPE2 = 264,0,32,0 %; ! Size/Type of structure macro MC_WBM$W_ConVert_BFR_SIZE = 268,0,16,0 %; ! Descriptor data size in number of Bytes macro MC_WBM$W_ConVert_TYPE = 270,0,16,0 %; ! macro MC_WBM$L_ConVert_PTR = 272,0,32,0 %; ! macro MC_WBM$L_ConVert_BFR = 276,0,32,0 %; ! 24 Bytes ! For Alpha literal SHADIO$M_FCODE = %X'FFFF'; literal SHADIO$M_FMODIFIERS = %X'FFFF0000'; literal SHADIO$M_FCODE_WAS_SET = %X'10000'; literal SHADIO$S_SHADIO = 8; ! SETCHAR SHADOWING function code/modifiers structure macro SHADIO$V_FCODE = 0,0,16,0 %; literal SHADIO$S_FCODE = 16; ! Function Code Field macro SHADIO$V_FMODIFIERS = 0,16,16,0 %; literal SHADIO$S_FMODIFIERS = 16; ! Function Modifiers Field macro SHADIO$V_FCODE_WAS_SET = 4,16,1,0 %; ! ! For Alpha literal SHAD$M_SNAPSHOT_PENDING = %X'1'; literal SHAD$M_SNAPSHOT_COMPLETE = %X'2'; literal SHAD$M_READ_MASTER = %X'4'; literal SHAD$M_FLUSH_WLT = %X'8'; literal SHAD$M_ENFORCE_LOCAL_READ = %X'10'; literal SHAD$M_LOCAL_STATUS_BIT05 = %X'20'; literal SHAD$M_NO_SINGLE_DECRAM = %X'40'; literal SHAD$M_HBMM_RECOVERY_IP = %X'80'; literal SHAD$M_HBMM_EVAL_POLICY_ENABLED = %X'100'; literal SHAD$M_HBMM_NO_MASTER_BITMAPS = %X'200'; literal SHAD$M_CLEAR_SCB_WRITECNT = %X'400'; literal SHAD$M_HOST_COMPARE_ALL_WRITES = %X'10000'; literal SHAD$M_BUGCHECK_ON_DATACHECK = %X'20000'; literal SHAD$M_AVAILABLE_IN_PROGRESS = %X'40000'; literal SHAD$M_LOCAL_STATUS_BIT19 = %X'80000'; literal SHAD$M_WBM = %X'100000'; literal SHAD$M_WBM_WRTLCK = %X'200000'; literal SHAD$M_USE_MASTER_FOR_READ = %X'400000'; literal SHAD$M_ABORT_VU = %X'800000'; literal SHAD$M_SPLIT_READ_LBNS = %X'1000000'; literal SHAD$M_LOCAL_STATUS_BIT25 = %X'2000000'; literal SHAD$M_LOCAL_STATUS_BIT26 = %X'4000000'; literal SHAD$M_SCB_UPDATE_FAILED = %X'8000000'; literal SHAD$M_SKIP_IF_HBMM_IS_ENABLED = %X'40000000'; literal SHAD$M_MUST_BE_MERGED = %X'80000000'; literal SHAD$M_NORMAL = %X'1'; literal SHAD$M_NEW = %X'2'; literal SHAD$M_COPYING = %X'20'; literal SHAD$M_MERGING = %X'40'; literal SHAD$M_MINIMRG = %X'80'; literal SHAD$M_COPY_RESET = %X'100'; literal SHAD$M_BOOTING = %X'200'; literal SHAD$M_SCB_WLG = %X'400'; literal SHAD$M_MUST_MRG = %X'4000'; literal SHAD$M_FAILED = %X'8000'; literal SHAD$M_MBR_COPY = %X'1'; literal SHAD$M_MBR_MERGE = %X'2'; literal SHAD$M_MBR_CIP = %X'4'; literal SHAD$M_MBR_SRC = %X'20'; literal SHAD$M_MBR_MCPY = %X'40'; literal SHAD$M_MBR_VALID = %X'80'; literal SHAD$M_MBR_FCPY = %X'1'; literal SH$C_CIP_MASK = 263172; ! 00040404 literal SH$C_MCPY_MASK = 4210752; ! 00404040 literal SH$C_MBR_MCPY_MASK = 4210752; ! 00404040 literal SH$C_VALID_CIP_COPY_MBR0 = 133; ! 00000085 literal SH$C_VALID_CIP_COPY_MBR1 = 34048; ! 00008500 literal SH$C_VALID_CIP_COPY_MBR2 = 8716288; ! 00850000 literal SH$C_VALID_SRC_MBR0 = 160; ! 000000A0 literal SH$C_VALID_SRC_MBR1 = 40960; ! 0000A000 literal SH$C_VALID_SRC_MBR2 = 10485760; ! 00A00000 literal SHAD$M_CA_COPY_ACTIVATED = %X'1'; literal SHAD$M_CA_LOCAL_COPY = %X'2'; literal SHAD$M_CA_REMOTE_COPY = %X'4'; literal SHAD$M_CA_COPY_PATH_EST = %X'8'; literal SHAD$M_CA_COPY_RETRY = %X'10'; literal SHAD$M_CA_COPY_DISABLE = %X'20'; literal SHAD$M_CA_LDCD_DISABLED = %X'40'; literal SHAD$M_CA_RDCD_DISABLED = %X'80'; literal SHAD$M_CA_CHECK_BITMAP_ERR = %X'80000000'; literal SHAD$M_IN_PROG = %X'1'; literal SHAD$M_INITING = %X'2'; literal SHAD$M_MMB_VALID = %X'4'; literal SHAD$M_MMB_ALLOCATION_FAILED = %X'8'; literal SHAD$M_LOST_CNID = %X'10'; literal SHAD$M_TABLE_GENERATION = %X'20'; literal SHAD$M_SWITCHING = %X'40'; literal SHAD$M_FLUSH_RATE_EXCEEDED = %X'1'; literal SHAD$M_BOOT_DEVICE_GONE = %X'1'; literal SHAD$M_MASTER_EQL_BOOT_DEV = %X'2'; literal SHAD$M_ORIBOOTDEV_SRC_VALID = %X'8'; literal SHAD$M_MASTER_ON_BAD_ADP_PATH = %X'10'; literal SHAD$M_BOOTED_ON_EMULATED_PATH = %X'20'; literal SHAD$M_MASTER_ON_EMULATED_PATH = %X'40'; literal SHAD$M_DUMP_UNIT_NUMBER_WRITTEN = %X'80'; literal SHAD$M_NODMPDISK = %X'8000'; literal SHAD$M_EXTENDED_INVWLG = %X'1'; literal SHAD$M_EXTENDED_INVWLG_PENDING = %X'2'; literal SHAD$M_EXTENDED_RESTARTED_TRIGR = %X'4'; literal SHAD$M_EXTENDED_WLG_TO_ON = %X'8'; literal SHAD$M_EXTENDED_EP_INPROGRESS = %X'10'; literal SHAD$M_EXTENDED_EP_DONE = %X'20'; literal SHAD$M_EXTENDED_SHDCPY_GTLK_ACT = %X'40'; literal SHAD$M_EXTENDED_INVWLG_NEEDED = %X'80'; literal SHAD$M_EXTENDED_COPY_COLLISIONS = %X'200'; literal SHAD$M_EXTENDED_COPY_HOTBLOCKS = %X'400'; literal SHAD$M_EXTENDED_DO_PASSIVE_MV = %X'800'; literal SHAD$M_COPY_MERGE_COMPLETE_TIME = %X'1000'; literal SHAD$M_EXTENDED_MBR_CIP = %X'1'; literal SHAD$M_HOMEBLOCK_CHECKSUM_BAD = %X'4'; literal SHAD$M_ODSII_CHECK_BAD = %X'8'; literal SHAD$M_SCB_CHECKSUM_BAD = %X'10'; literal SHAD$M_SCB_WRONG_VU = %X'20'; literal SHAD$M_SCB_NOMATCH_MOUNTTIME = %X'40'; literal SHAD$M_SCB_BAD_VOL_LOCK_NAME = %X'80'; literal SHAD$M_BIT16 = %X'10000'; literal SHAD$M_COPY_FROM_MASTER = %X'20000'; literal SHAD$M_HANDLE_VALID = %X'40000'; literal SHAD$M_REMOVE_THIS_MBR = %X'80000'; literal SHAD$M_USE_ONE_SRC_MBR = %X'100000'; literal SHAD$M_DECram_mbr = %X'200000'; literal SHAD$M_INCOMPATIBLE_SCB = %X'400000'; literal SHAD$M_SHD_WAS_CLEAR = %X'800000'; literal SHAD$M_BIT24 = %X'1000000'; literal SHAD$M_BIT25 = %X'2000000'; literal SHAD$M_BIT26 = %X'4000000'; literal SHAD$M_BIT27 = %X'8000000'; literal SHAD$M_IOERROR = %X'10000000'; literal SHAD$M_USER_SUPPLIED_READ_BIAS = %X'20000000'; literal SHAD$M_SOURCE_DCD_MBR = %X'40000000'; literal SHAD$M_BIT31 = %X'80000000'; literal SHAD$C_ID_BIAS = 100000; ! literal SHAD$M_QUIESCENT_POINT_EVENT = %X'1'; literal SHAD$M_SEQUENTIAL_COMMAND = %X'2'; literal SHAD$M_MEMBERSHIP_CHANGE = %X'4'; literal SHAD$M_PREVENT_MBR_CHANGE = %X'8'; literal SHAD$M_LOCAL_QUIESCE = %X'10'; literal SHAD$M_TRIGGER_VALIDATE = %X'20'; literal SHAD$M_SEQUENTIAL_NOP = %X'40'; literal SHAD$M_LOCAL_WLG = %X'1'; literal SHAD$M_EVALUATION_THREAD_ACTIVE = %X'2'; literal SHAD$M_WLG_THRESHOLD_ACTIVE = %X'4'; literal SHAD$M_WHM_DEAL_TIMR_ACTIVE = %X'8'; literal SHAD$M_PENDING_WLG_OFF = %X'10'; literal SHAD$M_PENDING_WLG_ON = %X'20'; literal SHAD$M_PENDING_WLG_OFF_SCB = %X'40'; literal SHAD$M_PENDING_WLG_ON_SCB = %X'80'; literal SHAD$M_DELETE_ENTRIES = %X'100'; literal SHAD$M_NF_TMP_IN_USE = %X'10000'; literal SHAD$M_CONT_ID_CHECK_DISABLED = %X'20000'; literal SHAD$M_WLGPRM_BAD_STATUS = %X'40000'; literal SHAD$M_WLG100_BAD_STATUS = %X'80000'; literal SHAD$M_WLGLCK_BAD_STATUS = %X'100000'; literal SHAD$M_GET_LOCK_MAP_FAILED = %X'200000'; literal SHAD$M_DISABLE_WLG = %X'1'; literal SHAD$M_ENABLE_WLG = %X'2'; literal SHAD$M_DRAIN_IO_0 = %X'1'; literal SHAD$M_DRAIN_IO_1 = %X'2'; literal SHAD$M_DRAIN_IO_2 = %X'4'; literal SHAD$M_DRAIN_IO_3 = %X'8'; literal SHAD$M_DRAIN_IO_4 = %X'10'; literal SHAD$M_DRAIN_IO_5 = %X'20'; literal SHAD$M_DRAIN_IO_6 = %X'40'; literal SHAD$M_DRAIN_IO_7 = %X'80'; literal SHAD$M_DRAIN_IO_8 = %X'100'; literal SHAD$M_DRAIN_IO_9 = %X'200'; literal SHAD$M_DRAIN_IO_A = %X'400'; literal SHAD$M_DRAIN_IO_B = %X'800'; literal SHAD$M_DRAIN_IO_C = %X'1000'; literal SHAD$M_DRAIN_IO_D = %X'2000'; literal SHAD$M_DRAIN_IO_E = %X'4000'; literal SHAD$M_DRAIN_IO_F = %X'8000'; literal SHAD$K_VETO_NEW_CHAR = 11181; ! Value used to veto proposed NEW_CHAR change literal SHAD$M_SHADOWING_LEVEL_BIT0 = %X'1'; literal SHAD$M_SHADOWING_LEVEL_BIT1 = %X'2'; literal SHAD$M_SHADOWING_LEVEL_BIT2 = %X'4'; literal SHAD$M_SHADOWING_LEVEL_BIT3 = %X'8'; literal SHAD$K_LENGTH = 7424; ! Length of Structure literal SHAD$C_LENGTH = 7424; ! Length of Structure literal SHAD$S_SHAD = 7428; macro SHAD$L_FLINK = 0,0,32,1 %; ! Used for offset determination macro SHAD$L_PRIORITY_FL = 0,0,32,1 %; ! Priority Level Linked List macro SHAD$L_PRIORITY_BL = 4,0,32,1 %; ! Backward link macro SHAD$W_SIZE = 8,0,16,0 %; ! Size of this structure macro SHAD$B_TYPE = 10,0,8,0 %; ! Standard fields macro SHAD$B_SUBTYP = 11,0,8,0 %; ! ... macro SHAD$L_VU_UCB = 12,0,32,1 %; ! Unit Control Block for VU macro SHAD$L_VU_VCB = 16,0,32,1 %; ! Volume Control Block for VU macro SHAD$L_OLD_DRIVER_MODE = 20,0,32,0 %; ! macro SHAD$L_ACTIVE_IRPS = 20,0,32,1 %; ! Obsolete Active "Master" IRPs macro SHAD$L_PERM_IRP = 24,0,32,1 %; ! Volume Processing always needs one .... macro SHAD$L_NOTIFICATION_ID = 28,0,32,0 %; ! Notification ID macro SHAD$B_MEMBERSHIP_PERMISSION = 32,0,0,0 %; literal SHAD$S_MEMBERSHIP_PERMISSION = 136; ! ($MBRPRM) Shadow set membership change permission lock macro SHAD$B_MEMBERSHIP_LOCK = 168,0,0,0 %; literal SHAD$S_MEMBERSHIP_LOCK = 136; ! ($MBRSHP) Shadow set membership lock macro SHAD$B_MEMBER_OF_SET = 304,0,0,0 %; literal SHAD$S_MEMBER_OF_SET = 136; ! ($IN_SET) Shadow set guaranteed member lock macro SHAD$B_WATCHER_LOCK = 440,0,0,0 %; literal SHAD$S_WATCHER_LOCK = 136; ! ($WATCHR) Shadow set membership lock watcher lock macro SHAD$B_SEQ_CMD_PERMISSION = 576,0,0,0 %; literal SHAD$S_SEQ_CMD_PERMISSION = 136; ! ($SEQPRM) Shadow set sequential command permission lock ! ! The following definitions are to allow DPDRIVER to work correctly, on older versions. ! We do this by defining multiple locations to contain "GENERATION Numbers" ... the only item that ! the DPDriver was extracting. Older versions of SHD_RELEASE_FLAG.MAR have the specifics and the assume ! statements. Spares added to insure that the HOLE is in the correct location ! macro SHAD$L_LOOKAHEAD = 712,0,32,0 %; macro SHAD$L_MAX_MBRS = 716,0,32,0 %; macro SHAD$L_SPARE4 = 720,0,0,0 %; literal SHAD$S_SPARE4 = 12; macro SHAD$B_WBM_BITMAP_GROUP = 732,0,8,0 %; macro SHAD$B_SPARE1 = 733,0,8,0 %; macro SHAD$W_SPARE3 = 734,0,16,0 %; macro SHAD$B_HOLE = 736,0,0,0 %; literal SHAD$S_HOLE = 96; macro SHAD$L_TRACK_WBM = 736,0,32,0 %; ! Last WBM call locator macro SHAD$L_SCP_MERGE_REPAIR_COUNT = 740,0,32,0 %; macro SHAD$L_APP_MERGE_REPAIR_COUNT = 744,0,32,0 %; macro SHAD$Q_DPGEN1 = 748,0,0,0 %; literal SHAD$S_DPGEN1 = 8; macro SHAD$L_RECOVERABLE_ERR_CTR = 756,0,0,0 %; literal SHAD$S_RECOVERABLE_ERR_CTR = 64; macro SHAD$L_RECOVERABLE_ERR_TIME = 820,0,0,0 %; literal SHAD$S_RECOVERABLE_ERR_TIME = 64; macro SHAD$B_NODE_MAP2 = 884,0,0,0 %; literal SHAD$S_NODE_MAP2 = 32; macro SHAD$Q_DPGEN2 = 916,0,0,0 %; literal SHAD$S_DPGEN2 = 8; macro SHAD$L_STOP_MERGE_AT_LBN = 924,0,32,0 %; ! Suspend full merge after xyzzy lbn is passed macro SHAD$Q_DPGEN3 = 928,0,0,0 %; literal SHAD$S_DPGEN3 = 8; ! End of DPDRIVER specific change macro SHAD$B_SEQ_CMD_LOCK = 936,0,0,0 %; literal SHAD$S_SEQ_CMD_LOCK = 136; ! ($SEQCMD) Shadow set sequential command lock macro SHAD$B_COPIER_LOCK = 1072,0,0,0 %; literal SHAD$S_COPIER_LOCK = 136; ! ($COPIER) Shadow set copier lock macro SHAD$B_NODE_MAP = 1208,0,0,0 %; literal SHAD$S_NODE_MAP = 32; ! Mounted node bit map ! and create a status longword which isn't completely zeroed by certain ! state changes. macro SHAD$L_LOCAL_STATUS = 1240,0,32,0 %; ! Node specific status macro SHAD$V_SNAPSHOT_PENDING = 1240,0,1,0 %; ! Snapshot shutdown/restart initiated macro SHAD$V_SNAPSHOT_COMPLETE = 1240,1,1,0 %; ! Snapshot shutdown/restart complete macro SHAD$V_READ_MASTER = 1240,2,1,0 %; ! Read only from the master disk macro SHAD$V_FLUSH_WLT = 1240,3,1,0 %; ! Flush write log table macro SHAD$V_ENFORCE_LOCAL_READ = 1240,4,1,0 %; ! Bias the READ I/O to best local members macro SHAD$V_LOCAL_STATUS_BIT05 = 1240,5,1,0 %; ! macro SHAD$V_NO_SINGLE_DECRAM = 1240,6,1,0 %; ! Permanent Storage device required macro SHAD$V_HBMM_RECOVERY_IP = 1240,7,1,0 %; ! Host Based Mini Merge is actively calling WBM to determine which LBAs must be merge macro SHAD$V_HBMM_EVAL_POLICY_ENABLED = 1240,8,1,0 %; ! HBMM "evaluate policy" for master bitmap creation is enabled on server macro SHAD$V_HBMM_NO_MASTER_BITMAPS = 1240,9,1,0 %; ! HBMM the last Pending Write "evaluate policy" for master bitmap creation is e macro SHAD$V_CLEAR_SCB_WRITECNT = 1240,10,1,0 %; ! If the VU is _SWL and a full merge is completed ... do this. macro SHAD$V_HOST_COMPARE_ALL_WRITES = 1240,16,1,0 %; ! Force host compare every write I/O macro SHAD$V_BUGCHECK_ON_DATACHECK = 1240,17,1,0 %; ! If host compare on write I/O fails macro SHAD$V_AVAILABLE_IN_PROGRESS = 1240,18,1,0 %; ! macro SHAD$V_LOCAL_STATUS_BIT19 = 1240,19,1,0 %; ! macro SHAD$V_WBM = 1240,20,1,0 %; ! WBM call active for Mini Copy macro SHAD$V_WBM_WRTLCK = 1240,21,1,0 %; ! Mini Copy macro SHAD$V_USE_MASTER_FOR_READ = 1240,22,1,0 %; ! NCA Copy Read Source macro SHAD$V_ABORT_VU = 1240,23,1,0 %; ! Requested Via User Interface macro SHAD$V_SPLIT_READ_LBNS = 1240,24,1,0 %; ! macro SHAD$V_LOCAL_STATUS_BIT25 = 1240,25,1,0 %; ! macro SHAD$V_LOCAL_STATUS_BIT26 = 1240,26,1,0 %; ! macro SHAD$V_SCB_UPDATE_FAILED = 1240,27,1,0 %; ! macro SHAD$V_SKIP_IF_HBMM_IS_ENABLED = 1240,30,1,0 %; ! Used after VU successfully completes MV when scanning the priority queue fo macro SHAD$V_MUST_BE_MERGED = 1240,31,1,0 %; ! For NPW to require a merge operation macro SHAD$L_ACTIVE_FL = 1244,0,32,1 %; ! FL for Active Queue macro SHAD$L_ACTIVE_BL = 1248,0,32,1 %; ! BL for Active Queue macro SHAD$L_RESTART_FL = 1252,0,32,1 %; ! FL for restart wait queue macro SHAD$L_RESTART_BL = 1256,0,32,1 %; ! BL for restart wait queue macro SHAD$W_WASCLR_COUNT = 1260,0,16,0 %; ! Mini Copy counter macro SHAD$W_DELAY_START_OF_COPY = 1262,0,16,0 %; ! Copy startup delay count ! ! define the LAST_RINDX so that it can be used as a byte and yet maintain ! longword alignment. ! macro SHAD$L_LAST_RINDX = 1264,0,32,0 %; ! Index of last read SSM macro SHAD$B_LAST_RINDX = 1264,0,8,0 %; ! macro SHAD$R_VECTOR = 1268,0,0,0 %; literal SHAD$S_VECTOR = 20; macro SHAD$L_COPY_VECTOR = 1268,0,32,0 %; ! Address of COPY routine macro SHAD$L_MERGE_VECTOR = 1272,0,32,0 %; ! Address of full MERGE or HBMM routine macro SHAD$L_WRITE_VECTOR = 1276,0,32,0 %; ! Address of WRITE Startio routine macro SHAD$L_READ_VECTOR = 1280,0,32,0 %; ! Address of DSE Startio routine macro SHAD$L_SPARE_VECTOR = 1284,0,32,0 %; ! Spare macro SHAD$L_SPARE_ARRAY = 1288,0,0,0 %; literal SHAD$S_SPARE_ARRAY = 28; ! ! The following fields, up to the next comment are placed contiguously in ! this data structure so that they can be copied from the SCB in one ! instruction. ! macro SHAD$Q_GENERNUM = 1316,0,0,0 %; literal SHAD$S_GENERNUM = 8; ! Shadow Set generation number macro SHAD$Q_UNIT_ID = 1324,0,0,0 %; literal SHAD$S_UNIT_ID = 8; ! unique cluster-wide identifier macro SHAD$W_STATUS = 1332,0,16,0 %; ! Volume status: macro SHAD$V_NORMAL = 1332,0,1,0 %; ! Shadow set populated and online macro SHAD$V_NEW = 1332,1,1,0 %; ! Newly created, no members yet macro SHAD$V_COPYING = 1332,5,1,0 %; ! Copy State macro SHAD$V_MERGING = 1332,6,1,0 %; ! Merge State macro SHAD$V_MINIMRG = 1332,7,1,0 %; ! Mini Merge in progress macro SHAD$V_COPY_RESET = 1332,8,1,0 %; ! Reset Shadow Server Copy mode macro SHAD$V_BOOTING = 1332,9,1,0 %; ! Shadow set in booting state macro SHAD$V_SCB_WLG = 1332,10,1,0 %; ! Write Logging Phase 1 enabled macro SHAD$V_MUST_MRG = 1332,14,1,0 %; ! This set requires a full merge macro SHAD$V_FAILED = 1332,15,1,0 %; ! Shadow set not populated macro SHAD$B_MEMBER_STATUS = 1334,0,8,0 %; ! Member status bits macro SHAD$V_MBR_COPY = 1334,0,1,0 %; ! Member involved in copy macro SHAD$V_MBR_MERGE = 1334,1,1,0 %; ! Member being merged macro SHAD$V_MBR_CIP = 1334,2,1,0 %; ! Cluster wide copy in progress bit macro SHAD$V_MBR_SRC = 1334,5,1,0 %; ! Member can be used for source macro SHAD$V_MBR_MCPY = 1334,6,1,0 %; ! Mini Copy candidate macro SHAD$V_MBR_VALID = 1334,7,1,0 %; ! Status information is valid macro SHAD$V_MBR_FCPY = 1334,0,1,0 %; ! Member involved in copy macro SHAD$W_SCB_MBZ = 1350,0,16,0 %; ! Historically cleared by UPDATE_DISKS macro SHAD$L_SPARE7 = 1352,0,32,0 %; macro SHAD$Q_MEMBER_IDS = 1356,0,0,0 %; literal SHAD$S_MEMBER_IDS = 128; ! Unit ID for member macro SHAD$L_SCB_LBN = 1484,0,32,0 %; ! Unit Control Block for VU macro SHAD$B_DEVICES = 1488,0,8,0 %; ! Number of devices in SS macro SHAD$B_MEMBERS = 1489,0,8,0 %; ! Number of full members macro SHAD$B_MASTER_INDEX = 1490,0,8,0 %; ! Array index to master UCB macro SHAD$B_MAST_INDX = 1490,0,8,0 %; ! Array index to master UCB macro SHAD$B_MRG_TARGETS = 1491,0,8,0 %; ! Merge Copy Targets macro SHAD$B_FC_TARGETS = 1492,0,8,0 %; ! Full Copy Targets macro SHAD$B_COPY_TARGETS = 1492,0,8,0 %; ! Full or MINI Copy Targets macro SHAD$B_DECram_MBRS = 1493,0,8,0 %; ! Number of DECram devices ! ! Maintain the following array as the last part of this data structure ! in order to maintain the longword alignment of fields preceding it. ! macro SHAD$L_MEMBER_UCB = 1500,0,0,1 %; literal SHAD$S_MEMBER_UCB = 64; ! UCB for member macro SHAD$L_filler7 = 1564,0,0,1 %; literal SHAD$s_filler7 = 40; macro SHAD$L_WBMB = 1604,0,32,1 %; ! For Mini Copy macro SHAD$L_MEMBER_VCB = 1608,0,0,1 %; literal SHAD$S_MEMBER_VCB = 64; ! VCB for member macro SHAD$L_COPY_LBN = 1672,0,0,0 %; literal SHAD$S_COPY_LBN = 64; ! Last LBN Copied macro SHAD$L_COPY_OR_MERGE_LBN = 1672,0,0,0 %; literal SHAD$S_COPY_OR_MERGE_LBN = 64; ! Last or either LBN macro SHAD$L_MERGE_LBN = 1672,0,0,0 %; literal SHAD$S_MERGE_LBN = 64; ! Last LBN Merged macro SHAD$L_PERD_LCKID = 1736,0,0,0 %; literal SHAD$S_PERD_LCKID = 64; ! sublock id for ! perdisk licensing ! Command Assist Information is added at the end of the shad to be ! backward compatible. macro SHAD$L_VP_IRP = 1800,0,32,1 %; ! Volume processing master. macro SHAD$L_SPARE2 = 1804,0,32,0 %; macro SHAD$L_WLG = 1808,0,0,0 %; literal SHAD$S_WLG = 64; ! Array of table indicators. macro SHAD$L_SPARE5 = 1872,0,32,0 %; macro SHAD$B_COPIER_THRESHOLD = 1876,0,0,0 %; literal SHAD$S_COPIER_THRESHOLD = 136; ! ($THRHLD) Copier threshold lock macro SHAD$B_WLG_INV = 2012,0,0,0 %; literal SHAD$S_WLG_INV = 136; ! ($SHDINV) Invalidate WLG lock macro SHAD$L_CA_COPY_STATUS = 2148,0,32,0 %; ! Command Assisted Copy Status macro SHAD$V_CA_COPY_ACTIVATED = 2148,0,1,0 %; ! Copy activated. macro SHAD$V_CA_LOCAL_COPY = 2148,1,1,0 %; ! Local copy. macro SHAD$V_CA_REMOTE_COPY = 2148,2,1,0 %; ! Remote copy. macro SHAD$V_CA_COPY_PATH_EST = 2148,3,1,0 %; ! Communication path established. macro SHAD$V_CA_COPY_RETRY = 2148,4,1,0 %; ! Retrying last I/O on a diff disk macro SHAD$V_CA_COPY_DISABLE = 2148,5,1,0 %; ! Disable assisted copy. macro SHAD$V_CA_LDCD_DISABLED = 2148,6,1,0 %; ! Disable local assisted copy macro SHAD$V_CA_RDCD_DISABLED = 2148,7,1,0 %; ! Disable remote assisted copy macro SHAD$V_CA_CHECK_BITMAP_ERR = 2148,31,1,0 %; ! WBM CHECK BITMAP returned an error macro SHAD$L_CA_SOURCE_INDEX = 2152,0,32,0 %; ! Command Assisted Copy Source macro SHAD$L_CA_TARGET_INDEX = 2156,0,32,0 %; ! Command Assisted Copy Target macro SHAD$L_WLG_THRESHOLD_TQE = 2160,0,32,1 %; ! Pointer to [SHADOWING] TQE Phase I macro SHAD$W_FAILED_CNID = 2164,0,16,0 %; ! macro SHAD$W_REMOVE_MBR_ERR = 2166,0,16,0 %; ! macro SHAD$L_MMB = 2168,0,32,0 %; ! Pointer to Merge Management Block macro SHAD$L_SRVR_IRP = 2172,0,32,1 %; ! Shadow server I/O PTR macro SHAD$L_MM_STS = 2176,0,32,0 %; ! Longword boundary macro SHAD$V_IN_PROG = 2176,0,1,0 %; ! In-progress macro SHAD$V_INITING = 2176,1,1,0 %; ! Table generation phase macro SHAD$V_MMB_VALID = 2176,2,1,0 %; ! mmb valid macro SHAD$V_MMB_ALLOCATION_FAILED = 2176,3,1,0 %; ! allocation failed macro SHAD$V_LOST_CNID = 2176,4,1,0 %; ! lost one or more cnids macro SHAD$V_TABLE_GENERATION = 2176,5,1,0 %; ! mmb in use for table macro SHAD$V_SWITCHING = 2176,6,1,0 %; ! mini-merge to merge switch ! ! Additional count to track how many seqcmd threads are queued. ! macro SHAD$L_SEQCMD_THREAD_COUNT = 2180,0,32,0 %; ! Count concurrent seqcmd threads macro SHAD$B_WLGINV_MAP = 2184,0,0,0 %; literal SHAD$S_WLGINV_MAP = 32; ! Nodes with WLG Lock macro SHAD$L_FLUSH_COUNT = 2216,0,32,0 %; ! Flush count macro SHAD$L_FLUSH_TICK_COUNT = 2220,0,32,0 %; ! Heart beat counter. macro SHAD$L_FLUSH_STS = 2224,0,32,0 %; ! Longword boundary macro SHAD$V_FLUSH_RATE_EXCEEDED = 2224,0,1,0 %; ! Flush rate exceeded ! SNAPSHOT_IRP longword unsigned; /* Pointer to the fastboot IRP ! SNAPSHOT_EXT longword unsigned; /* Pointer to the shadow extension ! SNAPSHOT_UCB longword unsigned; /* Pointer to the master UCB ! SNAPSHOT_STS longword unsigned; /* Saved master UCB$L_STS macro SHAD$L_VIRTUAL_UNIT_TIMEOUT = 2228,0,32,0 %; ! ! Member array macro SHAD$L_SHADOW_MEMBER_TIMEOUT = 2232,0,0,0 %; literal SHAD$S_SHADOW_MEMBER_TIMEOUT = 64; macro SHAD$W_RwaitcntCtr = 2296,0,16,0 %; ! Count of negative decrements macro SHAD$B_RwaitcntLog = 2298,0,8,0 %; ! Number of error log entries to write macro SHAD$B_RwaitcntBug = 2299,0,8,0 %; ! If sign bit is set, crash macro SHAD$L_WLG_PREFERENCE = 2300,0,32,0 %; ! Write Logging PREFERENCE Phase 1 ! ! DCD copy fence and some reserved longwords ! macro SHAD$L_DCD_COPY_LBN = 2304,0,32,0 %; ! DCD Copy Fence for Assisted Full Copy macro SHAD$L_DCD_MULTIPLIER = 2308,0,32,0 %; ! DCD Multiplier macro SHAD$L_DCD_WBM_TARGET_MBR = 2312,0,32,0 %; ! Mini Copy member using DCD macro SHAD$W_AbortVPCtr = 2316,0,16,0 %; ! Count of negative decrements macro SHAD$B_AbortVPLog = 2318,0,8,0 %; ! Number of error log entries to write macro SHAD$B_AbortVPBug = 2319,0,8,0 %; ! If sign bit is set, crash macro SHAD$L_ABORT_INCSHAMEM = 2320,0,32,0 %; ! macro SHAD$W_INCSHAMEMCtr = 2324,0,16,0 %; ! macro SHAD$B_INCSHAMEMLog = 2326,0,8,0 %; ! macro SHAD$B_INCSHAMEMBug = 2327,0,8,0 %; ! ! ! Warning : Must be quadword aligned ! macro SHAD$W_SDD_STATUS = 2328,0,16,0 %; ! Master switching status: macro SHAD$V_BOOT_DEVICE_GONE = 2328,0,1,0 %; ! macro SHAD$V_MASTER_EQL_BOOT_DEV = 2328,1,1,0 %; ! macro SHAD$V_ORIBOOTDEV_SRC_VALID = 2328,3,1,0 %; ! macro SHAD$V_MASTER_ON_BAD_ADP_PATH = 2328,4,1,0 %; ! macro SHAD$V_BOOTED_ON_EMULATED_PATH = 2328,5,1,0 %; ! macro SHAD$V_MASTER_ON_EMULATED_PATH = 2328,6,1,0 %; ! macro SHAD$V_DUMP_UNIT_NUMBER_WRITTEN = 2328,7,1,0 %; ! macro SHAD$V_NODMPDISK = 2328,15,1,0 %; ! macro SHAD$W_WBM_HAS_IO = 2330,0,16,0 %; ! For Mini Copy macro SHAD$L_VU_RECOVERABLE_ERR_CNT = 2332,0,32,0 %; macro SHAD$L_VU_RECOVERABLE_ERR_TIME = 2336,0,32,0 %; macro SHAD$B_WATCHER_MEMBER_OF_SET = 2340,0,0,0 %; literal SHAD$S_WATCHER_MEMBER_OF_SET = 136; ! ($IN_SET) Shadow set guaranteed member WATCHER lock macro SHAD$L_OLD_THRESHOLD_UPDATETIME = 2476,0,32,0 %; ! For UPDATE_THRESHOLD's use macro SHAD$L_EXTENDED_STATUS = 2480,0,32,0 %; ! Extended shadow volume status macro SHAD$V_EXTENDED_INVWLG = 2480,0,1,0 %; macro SHAD$V_EXTENDED_INVWLG_PENDING = 2480,1,1,0 %; macro SHAD$V_EXTENDED_RESTARTED_TRIGR = 2480,2,1,0 %; macro SHAD$V_EXTENDED_WLG_TO_ON = 2480,3,1,0 %; macro SHAD$V_EXTENDED_EP_INPROGRESS = 2480,4,1,0 %; macro SHAD$V_EXTENDED_EP_DONE = 2480,5,1,0 %; macro SHAD$V_EXTENDED_SHDCPY_GTLK_ACT = 2480,6,1,0 %; macro SHAD$V_EXTENDED_INVWLG_NEEDED = 2480,7,1,0 %; macro SHAD$V_EXTENDED_COPY_COLLISIONS = 2480,9,1,0 %; macro SHAD$V_EXTENDED_COPY_HOTBLOCKS = 2480,10,1,0 %; macro SHAD$V_EXTENDED_DO_PASSIVE_MV = 2480,11,1,0 %; macro SHAD$V_COPY_MERGE_COMPLETE_TIME = 2480,12,1,0 %; macro SHAD$W_DEVSTS_MSCP_MTVERIP_CNTR = 2484,0,16,0 %; macro SHAD$W_DEVSTS_SEQCMD_THERE_CNTR = 2486,0,16,0 %; macro SHAD$W_DEVSTS_PASSIVE_MV_CNTR = 2488,0,16,0 %; macro SHAD$W_DEVSTS_NODE_FAILURE_CNTR = 2490,0,16,0 %; macro SHAD$W_DEVSTS_WLGSTA_CHA_CNTR = 2492,0,16,0 %; macro SHAD$W_DEVSTS_WLG_INV_CNTR = 2494,0,16,0 %; macro SHAD$L_TRIGGER_VALIDATE_FLINK = 2496,0,32,1 %; macro SHAD$L_TRIGGER_VALIDATE_BLINK = 2500,0,32,1 %; macro SHAD$L_SEQ_CMD_FLINK = 2504,0,32,0 %; macro SHAD$L_SEQ_CMD_BLINK = 2508,0,32,0 %; macro SHAD$L_NODE_FAILURE_FLINK = 2512,0,32,0 %; macro SHAD$L_NODE_FAILURE_BLINK = 2516,0,32,0 %; macro SHAD$L_NODE_FAILURE_QUEUE = 2520,0,32,0 %; macro SHAD$W_NODE_FAILURE_STATUS1 = 2524,0,16,0 %; macro SHAD$W_NODE_FAILURE_STATUS2 = 2526,0,16,0 %; ! CONTROLLER_WLG longword unsigned dimension #XMAXMBRS; ! CONTROLLER_WLG_IOSB quadword unsigned; ! ! NOTE: The EXTENDED_MEMBER_STATUS byte is a local extension of the ! MEMBER_STATUS byte that resides in the SCB. Therefore, the ! MBR_VALID bit in MEMBER_STATUS is used to determine validity ! of the bits in EXTENDED_MEMBER_STATUS. ! macro SHAD$B_EXTENDED_MEMBER_STATUS = 2528,0,8,0 %; macro SHAD$V_EXTENDED_MBR_CIP = 2528,0,1,0 %; ! ( %X00000001 ) Local copy in progress bit macro SHAD$V_HOMEBLOCK_CHECKSUM_BAD = 2528,2,1,0 %; ! ( %X00000004 ) macro SHAD$V_ODSII_CHECK_BAD = 2528,3,1,0 %; ! ( %X00000008 ) macro SHAD$V_SCB_CHECKSUM_BAD = 2528,4,1,0 %; ! ( %X00000010 ) macro SHAD$V_SCB_WRONG_VU = 2528,5,1,0 %; ! ( %X00000020 ) macro SHAD$V_SCB_NOMATCH_MOUNTTIME = 2528,6,1,0 %; ! ( %X00000040 ) macro SHAD$V_SCB_BAD_VOL_LOCK_NAME = 2528,7,1,0 %; ! ( %X00000080 ) macro SHAD$L_MBR_STATUS = 2548,0,32,0 %; ! Do not use these bits ! Do not use these bits macro SHAD$V_BIT16 = 2548,16,1,0 %; ! ( %X00010000 ) macro SHAD$V_COPY_FROM_MASTER = 2548,17,1,0 %; ! ( %X00020000 ) for Write Bit Map macro SHAD$V_HANDLE_VALID = 2548,18,1,0 %; ! ( %X00040000 ) for " " " macro SHAD$V_REMOVE_THIS_MBR = 2548,19,1,0 %; ! ( %X00080000 ) macro SHAD$V_USE_ONE_SRC_MBR = 2548,20,1,0 %; ! ( %X00100000 ) as read source on full copy macro SHAD$V_DECram_mbr = 2548,21,1,0 %; ! ( %X00200000 ) DECram, a potentially volatile member macro SHAD$V_INCOMPATIBLE_SCB = 2548,22,1,0 %; ! ( %X00400000 ) macro SHAD$V_SHD_WAS_CLEAR = 2548,23,1,0 %; ! ( %X00800000 ) macro SHAD$V_BIT24 = 2548,24,1,0 %; ! ( %X01000000 ) macro SHAD$V_BIT25 = 2548,25,1,0 %; ! ( %X02000000 ) macro SHAD$V_BIT26 = 2548,26,1,0 %; ! ( %X04000000 ) macro SHAD$V_BIT27 = 2548,27,1,0 %; ! ( %X08000000 ) macro SHAD$V_IOERROR = 2548,28,1,0 %; ! ( %X10000000 ) macro SHAD$V_USER_SUPPLIED_READ_BIAS = 2548,29,1,0 %; ! ( %X20000000 ) macro SHAD$V_SOURCE_DCD_MBR = 2548,30,1,0 %; ! ( %X40000000 ) Assisted copy source member macro SHAD$V_BIT31 = 2548,31,1,0 %; ! ( %X80000000 ) ! The following are referenced in SHSB$MATCH_MASTER_SCB only. macro SHAD$L_VP_TIME = 2616,0,32,0 %; ! Time OUT Time macro SHAD$L_VP_MBRIDX = 2620,0,32,0 %; ! Member Index macro SHAD$L_VP_VALCNT = 2624,0,32,0 %; ! Count of Reads macro SHAD$L_VP_VALSCB = 2628,0,32,0 %; ! Count of Valid SCBs macro SHAD$L_VP_MTCH = 2632,0,32,0 %; ! Count matched macro SHAD$L_VP_CASE = 2636,0,32,0 %; ! SET_CASE case macro SHAD$L_VP_SETCASE = 2640,0,32,0 %; ! CHK_SET case macro SHAD$L_VP_SHADVAL = 2644,0,32,0 %; ! Valid SHAD Mbrs macro SHAD$L_VP_SCBMBR = 2648,0,32,0 %; ! Valid SCB Mbrs macro SHAD$L_VP_MBRM = 2652,0,32,0 %; ! Matched Mbrs macro SHAD$Q_VP_SCR1 = 2656,0,0,0 %; literal SHAD$S_VP_SCR1 = 8; ! Temp. space macro SHAD$L_VP_BUFARRAY = 2664,0,0,0 %; literal SHAD$S_VP_BUFARRAY = 64; ! SCB Buffer Array macro SHAD$L_VP_IRPARRAY = 2728,0,0,1 %; literal SHAD$S_VP_IRPARRAY = 64; ! IRP Array macro SHAD$L_VP_IDXARRAY = 2792,0,0,0 %; literal SHAD$S_VP_IDXARRAY = 64; ! Index Array ! The following are referenced in SHDR$START_ADDSHAD only. macro SHAD$Q_ADD_SCR1 = 2856,0,0,0 %; literal SHAD$S_ADD_SCR1 = 8; ! Temporary Space. ! The following are referenced in SHLK$NODE_FAILURE only. macro SHAD$L_NF_TMP1_01 = 2864,0,32,0 %; ! Temporary Space. macro SHAD$L_NF_TMP1_02 = 2868,0,32,0 %; ! Temporary Space ! The following constant is used by the SCSI Naming changes ! it is the bias used to ensure that an SCSSYTEMID cannot ! be mistaken for an allocation class. ! Added for threads package ! macro SHAD$L_ACTIVE_CTXB_FL = 2872,0,32,0 %; ! Thread active queue macro SHAD$L_ACTIVE_CTXB_BL = 2876,0,32,0 %; macro SHAD$L_STALLED_CTXB_FL = 2880,0,32,0 %; ! Thread stall queue macro SHAD$L_STALLED_CTXB_BL = 2884,0,32,0 %; macro SHAD$L_INTLIO_CTXB_FL = 2888,0,32,0 %; ! Internal I/O queue macro SHAD$L_INTLIO_CTXB_BL = 2892,0,32,0 %; macro SHAD$L_FORK_CTXB_FL = 2896,0,32,0 %; ! Forking queue macro SHAD$L_FORK_CTXB_BL = 2900,0,32,0 %; macro SHAD$L_LOCK_CTXB_FL = 2904,0,32,0 %; ! Locking queue macro SHAD$L_LOCK_CTXB_BL = 2908,0,32,0 %; macro SHAD$L_SPECIAL_EVENT_FL = 2912,0,32,0 %; ! Threads waiting to do special event macro SHAD$L_SPECIAL_EVENT_BL = 2916,0,32,0 %; macro SHAD$L_UNSTOPPABLE_CTXB_FL = 2920,0,32,0 %; ! Unstoppable threads macro SHAD$L_UNSTOPPABLE_CTXB_BL = 2924,0,32,0 %; macro SHAD$Q_SEQCMD_SEQNUM = 2928,0,0,0 %; literal SHAD$S_SEQCMD_SEQNUM = 8; ! Sequence number macro SHAD$L_SPECIAL_EVENTS = 2936,0,32,0 %; macro SHAD$V_QUIESCENT_POINT_EVENT = 2936,0,1,0 %; ! Quiescent Point active macro SHAD$V_SEQUENTIAL_COMMAND = 2936,1,1,0 %; ! Sequential command macro SHAD$V_MEMBERSHIP_CHANGE = 2936,2,1,0 %; ! Membership change macro SHAD$V_PREVENT_MBR_CHANGE = 2936,3,1,0 %; ! Prevent members change macro SHAD$V_LOCAL_QUIESCE = 2936,4,1,0 %; ! Local quiesce. macro SHAD$V_TRIGGER_VALIDATE = 2936,5,1,0 %; ! Trigger validate blocking ast macro SHAD$V_SEQUENTIAL_NOP = 2936,6,1,0 %; ! Emulation of sequential NOP's macro SHAD$L_EVALUATION_THREAD_TQE = 2940,0,32,1 %; macro SHAD$L_WHM_DEAL_TIMR_TQE = 2944,0,32,1 %; macro SHAD$L_WLG_STATUS = 2948,0,32,0 %; ! macro SHAD$V_LOCAL_WLG = 2948,0,1,0 %; ! macro SHAD$V_EVALUATION_THREAD_ACTIVE = 2948,1,1,0 %; ! macro SHAD$V_WLG_THRESHOLD_ACTIVE = 2948,2,1,0 %; ! macro SHAD$V_WHM_DEAL_TIMR_ACTIVE = 2948,3,1,0 %; ! macro SHAD$V_PENDING_WLG_OFF = 2948,4,1,0 %; ! macro SHAD$V_PENDING_WLG_ON = 2948,5,1,0 %; ! macro SHAD$V_PENDING_WLG_OFF_SCB = 2948,6,1,0 %; ! macro SHAD$V_PENDING_WLG_ON_SCB = 2948,7,1,0 %; ! macro SHAD$V_DELETE_ENTRIES = 2948,8,1,0 %; ! macro SHAD$V_NF_TMP_IN_USE = 2948,16,1,0 %; ! macro SHAD$V_CONT_ID_CHECK_DISABLED = 2948,17,1,0 %; ! macro SHAD$V_WLGPRM_BAD_STATUS = 2948,18,1,0 %; ! macro SHAD$V_WLG100_BAD_STATUS = 2948,19,1,0 %; ! macro SHAD$V_WLGLCK_BAD_STATUS = 2948,20,1,0 %; ! macro SHAD$V_GET_LOCK_MAP_FAILED = 2948,21,1,0 %; ! macro SHAD$W_WLG_CONTROL = 2952,0,16,0 %; macro SHAD$V_DISABLE_WLG = 2952,0,1,0 %; macro SHAD$V_ENABLE_WLG = 2952,1,1,0 %; macro SHAD$W_DRAIN_IO_FLAG = 2954,0,16,0 %; ! RWAITCNT Bump flags Reserved for alignment macro SHAD$V_DRAIN_IO_0 = 2954,0,1,0 %; macro SHAD$V_DRAIN_IO_1 = 2954,1,1,0 %; macro SHAD$V_DRAIN_IO_2 = 2954,2,1,0 %; macro SHAD$V_DRAIN_IO_3 = 2954,3,1,0 %; macro SHAD$V_DRAIN_IO_4 = 2954,4,1,0 %; macro SHAD$V_DRAIN_IO_5 = 2954,5,1,0 %; macro SHAD$V_DRAIN_IO_6 = 2954,6,1,0 %; macro SHAD$V_DRAIN_IO_7 = 2954,7,1,0 %; macro SHAD$V_DRAIN_IO_8 = 2954,8,1,0 %; macro SHAD$V_DRAIN_IO_9 = 2954,9,1,0 %; macro SHAD$V_DRAIN_IO_A = 2954,10,1,0 %; macro SHAD$V_DRAIN_IO_B = 2954,11,1,0 %; macro SHAD$V_DRAIN_IO_C = 2954,12,1,0 %; macro SHAD$V_DRAIN_IO_D = 2954,13,1,0 %; macro SHAD$V_DRAIN_IO_E = 2954,14,1,0 %; macro SHAD$V_DRAIN_IO_F = 2954,15,1,0 %; macro SHAD$L_CA_WASSET_CTR = 2956,0,32,0 %; ! Count these macro SHAD$L_SPARE6 = 2960,0,0,0 %; literal SHAD$S_SPARE6 = 104; macro SHAD$B_VU_CHAR = 3064,0,0,0 %; literal SHAD$S_VU_CHAR = 136; ! ($VUCHAR) VU Characteristics macro SHAD$B_WLG_INV_PERMISSION = 3200,0,0,0 %; literal SHAD$S_WLG_INV_PERMISSION = 136; ! ($WLGPRM) Invalidate WLG permission lock macro SHAD$B_COPIER_THRHLD_PERMISSION = 3336,0,0,0 %; literal SHAD$S_COPIER_THRHLD_PERMISSION = 136; ! ($THRPRM) Copier threshold permission lock macro SHAD$L_THRESHOLD_BIAS = 3472,0,32,0 %; ! Both referenced macro SHAD$W_THRESHOLD_IO_COUNT = 3472,0,16,0 %; ! macro SHAD$W_THRESHOLD_SECONDS = 3474,0,16,0 %; ! macro SHAD$L_NOCTX_RESTRT_FL = 3476,0,32,0 %; ! User IRPs queued for macro SHAD$L_NOCTX_RESTRT_BL = 3480,0,32,0 %; ! Retry. macro SHAD$L_WBM_HANDLE = 3484,0,0,0 %; literal SHAD$S_WBM_HANDLE = 64; ! Per Member Mini Copy Storage macro SHAD$L_SPARE8 = 3548,0,32,0 %; macro SHAD$Q_RESERVED_1 = 3552,0,0,0 %; literal SHAD$S_RESERVED_1 = 8; macro SHAD$Q_RESERVED_2 = 3560,0,0,0 %; literal SHAD$S_RESERVED_2 = 8; macro SHAD$L_THRESHOLD_UPDATE_TIME = 3568,0,32,0 %; ! For UPDATE_THRESHOLD's use macro SHAD$L_THRESHOLD_UPDATE_COUNT = 3572,0,32,0 %; ! For UPDATE_THRESHOLD's use macro SHAD$L_THRESHOLD_UPDATESECONDS = 3576,0,32,0 %; ! For UPDATE_THRESHOLD's use macro SHAD$L_THRESHOLD_UPDATE_IO = 3580,0,32,0 %; ! For UPDATE_THRESHOLD's use macro SHAD$Q_VU_VOLSIZE = 3584,0,0,0 %; literal SHAD$S_VU_VOLSIZE = 8; macro SHAD$Q_RESERVED_3 = 3592,0,0,0 %; literal SHAD$S_RESERVED_3 = 8; macro SHAD$L_HBMM_PREFERENCE = 3600,0,32,0 %; ! ! ! For Fibre Channel locally remote device determination ! KEEP this QUADWORD Aligned ! macro SHAD$L_VU_SITE_VALUE = 3604,0,32,0 %; ! macro SHAD$L_MEMBER_SITE_VALUE = 3608,0,0,0 %; literal SHAD$S_MEMBER_SITE_VALUE = 64; macro SHAD$L_BITMAP_SIZE = 3672,0,32,0 %; ! ! Merge Signal Stuff ! macro SHAD$B_MRGPRM = 3676,0,0,0 %; literal SHAD$S_MRGPRM = 136; ! ($MRGPRM) macro SHAD$B_MRGSIG = 3812,0,0,0 %; literal SHAD$S_MRGSIG = 136; ! ($MRGSIG) macro SHAD$B_MRGVAL = 3948,0,0,0 %; literal SHAD$S_MRGVAL = 136; ! ($MRGVAL) macro SHAD$L_TRACE1 = 4084,0,32,0 %; ! SHAD$L_EXTENDED_STATUS macro SHAD$L_TRACE2 = 4088,0,32,0 %; ! SHAD$W_STATUS, R0 (low word) macro SHAD$L_TRACE3 = 4092,0,32,0 %; ! Trace Number macro SHAD$L_TRACE4 = 4096,0,32,0 %; ! Trace Number macro SHAD$L_LOG_CMDREF = 4100,0,32,0 %; ! Tmp Storage for LOG_IT macro SHAD$L_NOLOG_CNT = 4104,0,32,0 %; ! Count of LOG_IT calls that failed. macro SHAD$L_POOL_ADDR = 4108,0,32,0 %; ! Location for Chaining Allocated POOL. ! ! N.B. The high word for each member in this array MUST remain unused ! to optimize the selection login in find_read_ucb. ! ! Read Bias - Setup by SHSB$SET_BIAS A.K.A. Read Cost ! Referenced by FIND_READ_UCB macro SHAD$L_READ_BIAS = 4112,0,0,0 %; literal SHAD$S_READ_BIAS = 64; ! ! DDS SHAD Support ! macro SHAD$B_RECEIVED_VU_CHAR = 4176,0,0,0 %; literal SHAD$S_RECEIVED_VU_CHAR = 136; ! ($RCVUCH) All received resultant VU characteristics after vote macro SHAD$B_NEW_CHAR = 4312,0,0,0 %; literal SHAD$S_NEW_CHAR = 136; ! ($NEWCHR) Proposed change to VU characterics macro SHAD$L_MOS_VALBLK_OFFSET = 4448,0,32,0 %; ! Offset into MOS value block macro SHAD$V_SHADOWING_LEVEL_BIT0 = 4452,0,1,0 %; ! Prevents older versions from mounting the shadow set macro SHAD$V_SHADOWING_LEVEL_BIT1 = 4452,1,1,0 %; ! Prevents older versions from mounting the shadow set macro SHAD$V_SHADOWING_LEVEL_BIT2 = 4452,2,1,0 %; ! Prevents older versions from mounting the shadow set macro SHAD$V_SHADOWING_LEVEL_BIT3 = 4452,3,1,0 %; ! Prevents older versions from mounting the shadow set macro SHAD$L_REQ_VU_CHAR_MASK_1 = 4456,0,32,0 %; macro SHAD$L_REQ_VU_CHAR_MASK_2 = 4460,0,32,0 %; macro SHAD$L_NEW_VU_CHAR_MASK_1 = 4464,0,32,0 %; macro SHAD$L_NEW_VU_CHAR_MASK_2 = 4468,0,32,0 %; macro SHAD$L_ASM_EXISTS_ENTRY = 4472,0,32,0 %; ! For use of Mount Done macro SHAD$L_SPARE10 = 4476,0,32,0 %; ! macro SHAD$L_LIMIT_LBN = 4480,0,0,0 %; literal SHAD$S_LIMIT_LBN = 64; ! ! Last generation number written to a specific SSM. ! macro SHAD$B_INDEX0_ID_GEN_NUM = 4544,0,0,0 %; literal SHAD$S_INDEX0_ID_GEN_NUM = 136; ! ($LGNIN0) Last GN for Index 0 macro SHAD$B_INDEX1_ID_GEN_NUM = 4680,0,0,0 %; literal SHAD$S_INDEX1_ID_GEN_NUM = 136; ! ($LGNIN1) Last GN for Index 1 macro SHAD$B_INDEX2_ID_GEN_NUM = 4816,0,0,0 %; literal SHAD$S_INDEX2_ID_GEN_NUM = 136; ! ($LGNIN2) Last GN for Index 2 macro SHAD$B_INDEX3_ID_GEN_NUM = 4952,0,0,0 %; literal SHAD$S_INDEX3_ID_GEN_NUM = 136; ! ($LGNIN3) Last GN for Index 0 macro SHAD$B_INDEX4_ID_GEN_NUM = 5088,0,0,0 %; literal SHAD$S_INDEX4_ID_GEN_NUM = 136; ! ($LGNIN4) Last GN for Index 1 macro SHAD$B_INDEX5_ID_GEN_NUM = 5224,0,0,0 %; literal SHAD$S_INDEX5_ID_GEN_NUM = 136; ! ($LGNIN5) Last GN for Index 2 macro SHAD$B_INDEX6_ID_GEN_NUM = 5360,0,0,0 %; literal SHAD$S_INDEX6_ID_GEN_NUM = 136; ! ($LGNIN6) Last GN for Index 0 macro SHAD$B_INDEX7_ID_GEN_NUM = 5496,0,0,0 %; literal SHAD$S_INDEX7_ID_GEN_NUM = 136; ! ($LGNIN7) Last GN for Index 1 macro SHAD$B_INDEX8_ID_GEN_NUM = 5632,0,0,0 %; literal SHAD$S_INDEX8_ID_GEN_NUM = 136; ! ($LGNIN8) Last GN for Index 2 macro SHAD$B_INDEX9_ID_GEN_NUM = 5768,0,0,0 %; literal SHAD$S_INDEX9_ID_GEN_NUM = 136; ! ($LGNIN9) Last GN for Index 0 macro SHAD$B_INDEX10_ID_GEN_NUM = 5904,0,0,0 %; literal SHAD$S_INDEX10_ID_GEN_NUM = 136; ! ($LGNIN10) Last GN for Index 1 macro SHAD$B_INDEX11_ID_GEN_NUM = 6040,0,0,0 %; literal SHAD$S_INDEX11_ID_GEN_NUM = 136; ! ($LGNIN11) Last GN for Index 2 macro SHAD$B_INDEX12_ID_GEN_NUM = 6176,0,0,0 %; literal SHAD$S_INDEX12_ID_GEN_NUM = 136; ! ($LGNIN12) Last GN for Index 0 macro SHAD$B_INDEX13_ID_GEN_NUM = 6312,0,0,0 %; literal SHAD$S_INDEX13_ID_GEN_NUM = 136; ! ($LGNIN13) Last GN for Index 1 macro SHAD$B_INDEX14_ID_GEN_NUM = 6448,0,0,0 %; literal SHAD$S_INDEX14_ID_GEN_NUM = 136; ! ($LGNIN14) Last GN for Index 2 macro SHAD$B_INDEX15_ID_GEN_NUM = 6584,0,0,0 %; literal SHAD$S_INDEX15_ID_GEN_NUM = 136; ! ($LGNIN15) Last GN for Index 0 macro SHAD$L_COPY_MERGE_PRIORITY = 6720,0,32,0 %; ! For HBMM macro SHAD$L_DO_SHADOW_COPIES_ACTIVE = 6724,0,32,0 %; ! For priority level thread macro SHAD$L_HBMM_WBM_MST_HNDL = 6728,0,32,0 %; ! HBMM master bitmap handle for VU on this node (if nonzero) macro SHAD$L_HBMM_WBM_MASTER_HANDLE = 6728,0,32,0 %; ! HBMM master bitmap handle for VU on this node (if nonzero) macro SHAD$PS_HBMM_EP = 6732,0,32,1 %; ! If nonzero, pointer to HBMM_EP structure used to trigger "evaluate policy" macro SHAD$Q_HBMM_RESET_TIME_OF = 6736,0,0,0 %; literal SHAD$S_HBMM_RESET_TIME_OF = 8; ! Time of most recent HBMM bitmap reset for VU macro SHAD$L_MINI_COPY_IP_CNID = 6744,0,32,0 %; ! This contains the CNID of the system that WAS doing it macro SHAD$L_HBMM_RESET_COUNT = 6748,0,32,0 %; ! Count of times HBMM bitmaps reset for VU macro SHAD$L_HBMM_LBNS_MERGED = 6752,0,32,0 %; ! This contains count of LBNs merged while HBMM is running macro SHAD$L_HBMM_LBNS_NOT_MERGED = 6756,0,32,0 %; ! This contains count of LBNs not merged while HBMM is running macro SHAD$L_REC_DLY_PER_SRV_SSM = 6760,0,32,0 %; ! This contains the seconds of delay per SSM before this system attempts to obtai ! the copier lock macro SHAD$L_SERVED_PATH_DELAY_DUE = 6764,0,32,0 %; ! This contains aggregate due time for the served SSMs macro SHAD$Q_CONSISTENCY_TIMESTAMP = 6768,0,0,0 %; literal SHAD$S_CONSISTENCY_TIMESTAMP = 8; ! Copy of time stamp from SCB read of a MBR_SRC SSM contains systime ! when last transient state completed that left the VU in that state macro SHAD$L_SCB_SHADOWING_STATUS = 6776,0,32,0 %; ! Contains SCB$w_SHADOWING_STATUS from SCB read of a MBR_SRC SSM macro SHAD$L_SPARE9 = 6780,0,32,0 %; macro SHAD$Q_TRACE1 = 6784,0,0,0 %; literal SHAD$S_TRACE1 = 8; ! macro SHAD$Q_TRACE2 = 6792,0,0,0 %; literal SHAD$S_TRACE2 = 8; ! macro SHAD$Q_TRACE3 = 6800,0,0,0 %; literal SHAD$S_TRACE3 = 8; ! macro SHAD$Q_TRACE4 = 6808,0,0,0 %; literal SHAD$S_TRACE4 = 8; ! macro SHAD$Q_TRACE5 = 6816,0,0,0 %; literal SHAD$S_TRACE5 = 8; ! macro SHAD$Q_TRACE6 = 6824,0,0,0 %; literal SHAD$S_TRACE6 = 8; ! macro SHAD$Q_TRACE7 = 6832,0,0,0 %; literal SHAD$S_TRACE7 = 8; ! macro SHAD$Q_TRACE8 = 6840,0,0,0 %; literal SHAD$S_TRACE8 = 8; ! macro SHAD$Q_TRACE9 = 6848,0,0,0 %; literal SHAD$S_TRACE9 = 8; ! macro SHAD$L_COPY_HOTBLOCKS = 6856,0,32,0 %; ! macro SHAD$W_COPY_HOTBLOCKS = 6856,0,16,0 %; ! macro SHAD$L_COPY_COLLISIONS = 6860,0,32,0 %; ! macro SHAD$W_COPY_COLLISIONS = 6860,0,16,0 %; ! macro SHAD$L_HBMC_LBNS_UPDATED = 6864,0,32,0 %; ! Contains count of LBNs updated while mini copy is used macro SHAD$L_OPTIMAL_HBMM_DELAY_DUE = 6868,0,32,0 %; ! Delay to allow systems that have a "pure" HBMM bitmap to obtain the _COPIER macro SHAD$Q_SSM_GN_VALUE = 6872,0,0,0 %; literal SHAD$S_SSM_GN_VALUE = 128; macro SHAD$Q_MOUNTTIME = 7000,0,0,0 %; literal SHAD$S_MOUNTTIME = 8; ! Virtual Units current value, needed for Mini Copy Restart validation macro SHAD$L_GN_UPDATE_ACTIVE = 7008,0,32,0 %; ! Count number of blossomed generation numbers that ware waiting to be updated macro SHAD$B_ADD_MEMBER = 7016,0,0,0 %; literal SHAD$S_ADD_MEMBER = 136; ! ($ADDMBR) VU Characteristics macro SHAD$B_NEW_MEMBER = 7152,0,0,0 %; literal SHAD$S_NEW_MEMBER = 136; ! ($NEWMBR) VU Characteristics macro SHAD$B_ADD_RESULT = 7288,0,0,0 %; literal SHAD$S_ADD_RESULT = 136; ! ($ADDRES) VU Characteristics ! ! Preserve quadword alignment for IRP ! macro SHAD$L_IRP = 7424,0,32,1 %; ! Pointer to shadow IRP macro SHAD$L_SHADEND_PLUS = 7424,0,32,0 %; ! Reserved Storage ! ++ ! Volume Shadowing Host-Based Mini Merge "Evaluate Policy" structure. ! ! The HBMM_EP is used to trigger a cluster-wide "evaluate policy" event for a ! specific VU. This structure is allocated and deallocate by SHDRIVER as ! its needed. When it exists, SHAD$PS_HBMM_EP contains a pointer to it. ! ! -- literal HBMM_EP$K_LENGTH = 424; ! Length of Structure literal HBMM_EP$C_LENGTH = 424; ! Length of Structure literal HBMM_EP$S_HBMM_EP = 424; macro HBMM_EP$PS_VU_UCB = 0,0,32,1 %; ! Unit Control Block for VU macro HBMM_EP$PS_SHAD = 4,0,32,1 %; ! SHAD for the VU macro HBMM_EP$W_SIZE = 8,0,16,0 %; ! Size of this structure, bytes macro HBMM_EP$B_TYPE = 10,0,8,0 %; ! Structure type: DYN$C_MISC macro HBMM_EP$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype: DYN$C_HBMM_EP macro HBMM_EP$L_FLAGS = 12,0,32,0 %; ! Miscellaneous flags macro HBMM_EP$R_PC_LOCK = 16,0,0,0 %; literal HBMM_EP$S_PC_LOCK = 136; ! ($HBMMpc) Policy Change mutex lock macro HBMM_EP$R_SC_LOCK = 152,0,0,0 %; literal HBMM_EP$S_SC_LOCK = 136; ! ($HBMMsc) Serialize Create lock, summary status in valblk macro HBMM_EP$R_EP_LOCK = 288,0,0,0 %; literal HBMM_EP$S_EP_LOCK = 136; ! ($HBMMep) Evaluate Policy doorbell lock literal ANLSHAD$M_BRIEF = %X'1'; literal ANLSHAD$M_STATISTICS = %X'2'; literal ANLSHAD$M_IGNORE = %X'4'; literal ANLSHAD$M_FILE_SYSTEM = %X'8'; literal ANLSHAD$M_ALL = %X'10'; literal ANLSHAD$M_SCB = %X'20'; literal ANLSHAD$M_NOT_CONSISTENT = %X'40'; literal ANLSHAD$S_ANLFLAGS = 4; macro ANLSHAD$V_BRIEF = 0,0,1,0 %; ! /Brief macro ANLSHAD$V_STATISTICS = 0,1,1,0 %; ! /Statistics macro ANLSHAD$V_IGNORE = 0,2,1,0 %; ! /Ignore macro ANLSHAD$V_FILE_SYSTEM = 0,3,1,0 %; ! /BLOCK=FILE macro ANLSHAD$V_ALL = 0,4,1,0 %; ! /BLOCK=ALL macro ANLSHAD$V_SCB = 0,5,1,0 %; ! Block is an SCB macro ANLSHAD$V_NOT_CONSISTENT = 0,6,1,0 %; ! Set may not be consistent ! ! This is the end of the SDL file. ! !*** MODULE $SHLDEF *** ! + ! SHL - SHAREABLE IMAGE LIST ! ! THIS LIST IS CREATED IN THE IMAGE FIXUP SECTION BY THE LINKER AND ! USED BY THE IMAGE ACTIVATOR FOR DOING SHAREABLE IMAGE FIXUPS. ! - literal SHL$M_FIXUP = %X'1'; literal SHL$C_OLD_SHL_SIZE = 56; ! Size of "old" SHL literal SHL$C_MAXNAMLNG = 39; ! Maximum length of image name literal SHL$K_LENGTH = 64; ! Length of shareable image list element literal SHL$C_LENGTH = 64; ! Length of shareable image list element literal SHL$S_SHLDEF = 64; literal SHL$S_SHL = 64; macro SHL$L_BASEVA = 0,0,32,1 %; ! Base address of this shareable image macro SHL$L_SHLPTR = 4,0,32,1 %; ! Pointer from SHL in shareable image ! to associated SHL in executable image macro SHL$L_IDENT = 8,0,32,0 %; ! GSMATCH macro SHL$L_PERMCTX = 12,0,32,1 %; ! Permanent sharable image context macro SHL$B_SHL_SIZE = 16,0,8,1 %; ! Size of SHL elements macro SHL$B_FLAGS = 19,0,8,0 %; ! Flags macro SHL$V_FIXUP = 19,0,1,0 %; ! Fixups against this shareable have been done macro SHL$L_ICB = 20,0,32,1 %; ! Address of the image control block macro SHL$T_IMGNAM = 24,0,0,0 %; literal SHL$S_IMGNAM = 40; ! Shareable image name (ASCIC string) macro SHL$B_NAMLNG = 24,0,8,1 %; ! Synonym for name count !*** MODULE $SHM_IDDEF *** ! ! Shared Memory ID Definition. The shared memory region ID is the ! handle used to identify a shared memory region. ! literal SHM_ID$S_SHM_ID = 8; macro SHM_ID$L_SHORT_ID = 0,0,32,0 %; ! Index and extent only macro SHM_ID$W_INDEX = 0,0,16,0 %; ! Index into SHM_REG array macro SHM_ID$W_EXTENT = 2,0,16,0 %; ! Unused for V1.0 macro SHM_ID$L_SEQ_NUM = 4,0,32,0 %; ! Sequence number macro SHM_ID$Q_IDENT = 0,0,0,0 %; literal SHM_ID$S_IDENT = 8; !*** MODULE $SLUSHRDEF *** ! SLU - Shared Data Structures for the serial line unit. ! ! SLUshr is the data structure used to bind the ! OpenVMS YR Driver and the X.25 ZR Driver. ! ! Define some types so we can get the C function prototypes to return ! the correct types. ! ! ! Vectors for the SCC interrupts generated by the SIR ! literal SIRVEC$K_SIZE = 20; literal SIRVEC$S_SIRvector = 20; macro SIRVEC$A_RxOverrun = 0,0,32,0 %; macro SIRVEC$A_RxHalfPage = 4,0,32,0 %; macro SIRVEC$A_TxReadError = 8,0,32,0 %; macro SIRVEC$A_TxPageEnd = 12,0,32,0 %; macro SIRVEC$A_SCC = 16,0,32,0 %; ! ! Vectors describing the SCC Specific ISRs ! literal SCCVEC$K_SIZE = 12; literal SCCVEC$S_SCCvector = 12; macro SCCVEC$A_RxSpecCond = 0,0,32,0 %; macro SCCVEC$A_Transmit = 4,0,32,0 %; macro SCCVEC$A_ExtStatus = 8,0,32,0 %; ! ! Saved state of the SCC registers ! literal SCCSAV$K_SIZE = 64; literal SCCSAV$S_SCCsaveReg = 64; macro SCCSAV$L_RR0 = 0,0,32,1 %; ! RR0 is saved, as WR0 is stateless macro SCCSAV$L_WR1 = 4,0,32,1 %; macro SCCSAV$L_WR2 = 8,0,32,1 %; macro SCCSAV$L_WR3 = 12,0,32,1 %; macro SCCSAV$L_WR4 = 16,0,32,1 %; macro SCCSAV$L_WR5 = 20,0,32,1 %; macro SCCSAV$L_WR6 = 24,0,32,1 %; macro SCCSAV$L_WR7 = 28,0,32,1 %; macro SCCSAV$L_WR8 = 32,0,32,1 %; macro SCCSAV$L_WR9 = 36,0,32,1 %; macro SCCSAV$L_WR10 = 40,0,32,1 %; macro SCCSAV$L_WR11 = 44,0,32,1 %; macro SCCSAV$L_WR12 = 48,0,32,1 %; macro SCCSAV$L_WR13 = 52,0,32,1 %; macro SCCSAV$L_WR14 = 56,0,32,1 %; macro SCCSAV$L_WR15 = 60,0,32,1 %; ! ! This structure is shared between the YR- and ZR-Drivers ! literal SLUSHR$K_SIZE = 172; literal SLUSHR$S_SLUshr = 172; macro SLUSHR$R_SIRvec = 0,0,0,0 %; literal SLUSHR$S_SIRvec = 20; ! SIR interrupt vectors macro SLUSHR$R_SCCvec = 20,0,0,0 %; literal SLUSHR$S_SCCvec = 24; ! SCC interupt vectors macro SLUSHR$R_SCCsav = 44,0,0,0 %; literal SLUSHR$S_SCCsav = 128; ! Save SCC registers macro SLUshrPtr = 0,0,32,0 %; ! ! PROTOTYPE ! %if not %declared(%quote SDL$$SLUSHRDEF_REQ) %then ! MACRO to emit warning and default to 0 if required argument is missing ! macro SDL$$SLUSHRDEF_REQ(ARG1, arg2) = %IF not %NULL(ARG1) %THEN ARG1 %else %warn(%string('REQUIRED ARGUMENT ', %NAME(ARG2), ' MISSING')) 0 %FI %; %fi %if not %declared(%quote SDL$$SLUSHRDEF_OPT) %then ! Defaults omitted arguments to 0 if followed by additional arguments ! macro SDL$$SLUSHRDEF_OPT[ARG] = %IF %NULL(ARG) %THEN %IF NOT %NULL(%REMAINING) %THEN 0 %FI %ELSE ARG %FI %; %fi %if not %declared(%quote SDL$$SLUSHRDEF_LIST_0_REQ) %then ! Handles LIST parameters that are also OPTIONAL ! macro SDL$$SLUSHRDEF_LIST_0_REQ(ARG) = %IF NOT %NULL(ARG) %THEN %REMOVE(ARG) %FI %; %fi %if not %declared(%quote SDL$$SLUSHRDEF_LIST_1_REQ) %then ! Handles LIST parameters that are not OPTIONAL ! Emits warning and defaults to 0 if required argument is missing ! macro SDL$$SLUSHRDEF_LIST_1_REQ(ARG, ARG2) = %IF %NULL(ARG) %THEN %warn(%string('REQUIRED ARGUMENT ', %NAME(ARG2), ' MISSING')) 0 %ELSE SDL$$SLUSHRDEF_LIST_0_REQ(ARG) %FI %; %fi %if not %declared(%quote SDL$$SLUSHRDEF_CONCAT) %then ! Eliminates trailing null arguments ! macro SDL$$SLUSHRDEF_CONCAT[ARG] = %IF NOT %NULL(ARG) %THEN ARG %FI %; %fi ! *********************************** KEYWORDMACRO $ATTACH_TTA1 (ShrTablePtr) = BEGIN EXTERNAL ROUTINE ZR$ATTACH_TTA1 : BLISS ADDRESSING_MODE (GENERAL); ZR$ATTACH_TTA1 (SDL$$SLUSHRDEF_CONCAT( SDL$$SLUSHRDEF_REQ(ShrTablePtr, %QUOTE ShrTablePtr) )) END %; ! VAX/DEC CMS REPLACEMENT HISTORY, Element SLUSHRDEF.SDL ! *3 6-JUL-1993 14:27:06 MUGGERIDGE "Cosmetic change." ! *2 5-JUL-1993 17:39:07 MUGGERIDGE " Added entry point description for zr$attach_tta1()." ! *1 23-JUN-1993 09:57:58 MUGGERIDGE "Shared data structures for the YR and ZR drivers" ! VAX/DEC CMS REPLACEMENT HISTORY, Element SLUSHRDEF.SDL !*** MODULE $SLVDEF *** ! ! ! Define symbolic offsets for System Loadable Vectors. These symbols ! are used by the various pieces of the loadable EXEC, notably SCSVEC, ! to create a list of vectors in system space and a corresponding image ! that will be loaded into pool and connected to the system vectors. ! ! literal SLV$K_LENGTH = 676; ! SLV$K_LENGTH literal SLV$S_SLV = 676; macro SLV$L_CODESIZE = 0,0,32,0 %; ! Loadable image size (in bytes) macro SLV$L_INITRTN = 4,0,32,0 %; ! Offset to init. routine macro SLV$W_SIZE = 8,0,16,0 %; ! Same as SLV$L_CODESIZE macro SLV$B_TYPE = 10,0,8,0 %; ! Structure type (DYN$C_LOADCODE) macro SLV$B_SUBTYP = 11,0,8,0 %; ! Sturcture Subtype macro SLV$B_PROT_R = 12,0,8,0 %; ! writeable protection for image macro SLV$B_PROT_W = 13,0,8,0 %; ! read-only protection for image macro SLV$W_SPARE = 14,0,16,0 %; ! spare field for future use macro SLV$A_SYSVECS = 16,0,32,0 %; ! address of vectors in SYS.EXE macro SLV$T_FACILITY = 20,0,0,0 %; literal SLV$S_FACILITY = 16; ! facility name (.ASCIC) macro SLV$T_LIST = 36,0,0,0 %; literal SLV$S_LIST = 640; ! Start of vector list (MAXVEC*5) ! ! ! Define vector type codes. The codes LODUMMY and HIDUMMY are ! used as placeholders, to make the definition of the upper and ! lower bound vector type symbols automatic. New vector type codes ! should be added at the end of the list, but before HIDUMMY. ! ! literal SLV$K_LODUMMY = 0; ! literal SLV$K_LDATA = 1; ! Longword pointer to data literal SLV$K_AJUMP = 2; ! Aligned jump literal SLV$K_UJUMP = 3; ! Unaligned jump literal SLV$K_SDATA = 4; ! Specified data literal SLV$K_SJUMP = 5; ! Specified jump literal SLV$K_HIDUMMY = 6; ! literal SLV$K_MINTYPE = 1; ! Lower bound of vector type codes literal SLV$K_MAXTYPE = 5; ! Upper bount of vector type codes literal SLV$K_MAXVEC = 128; ! Max. # of vectors in list. !*** MODULE $SMBDEF *** ! Symbiont interface definitions ! + ! Symbolic definitions for the symbiont to job controller interface. ! ! Public definitions of message types, item codes, and ! other constants utilied by the symbiont to job controller ! interface facility. ! ! - ! ! Structure level ! literal SMBMSG$K_STRUCTURE_LEVEL = 1; ! Current structure level literal SMBMSG$K_STRUCTURE_LEVEL_1 = 1; ! Structure level 1 literal SMBMSG$K_ARCH_MAX_STREAMS = 32; ! Architected maximum streams per symbiont ! ! Request header ! literal SMBMSG$K_PAUSE_TASK = 1; ! - STOP /QUEUE literal SMBMSG$K_RESET_STREAM = 2; ! - STOP /QUEUE /RESET literal SMBMSG$K_RESUME_TASK = 3; ! - START /QUEUE (when paused) literal SMBMSG$K_START_STREAM = 4; ! - START /QUEUE (when stopped) literal SMBMSG$K_START_TASK = 5; ! - task available literal SMBMSG$K_STOP_STREAM = 6; ! - STOP /QUEUE /NEXT literal SMBMSG$K_STOP_TASK = 7; ! - STOP /QUEUE /ABORT or /REQUEUE literal SMBMSG$K_TASK_COMPLETE = 8; ! - stream is idle literal SMBMSG$K_TASK_STATUS = 9; ! - asynchronous status update literal SMBMSG$K_START_SYMBIONT = 10; ! - symbiont creation confirmation literal SMBMSG$K_JOB_REQUEST = 11; ! - request a job to be executed literal SMBMSG$K_MAX_REQUEST_CODE = 12; ! MUST BE LAST literal SMBMSG$S_REQUEST_HEADER = 12; macro SMBMSG$W_REQUEST_CODE = 0,0,16,0 %; ! Request code ! Define request codes macro SMBMSG$B_STRUCTURE_LEVEL = 2,0,8,0 %; ! Message structure level macro SMBMSG$B_STREAM_INDEX = 3,0,8,0 %; ! Stream index macro SMBMSG$L_SYMBIONT_ID = 4,0,32,0 %; ! Symbiont identification macro SMBMSG$L_JOB_ID = 8,0,32,0 %; ! Job number (or 0 if a queue-oriented request) ! ! Item header ! literal SMBMSG$K_ACCOUNTING_DATA = 1; ! - accounting information literal SMBMSG$K_ACCOUNT_NAME = 2; ! - account name literal SMBMSG$K_AFTER_TIME = 3; ! - /AFTER value literal SMBMSG$K_ALIGNMENT_PAGES = 4; ! - /ALIGN count literal SMBMSG$K_BOTTOM_MARGIN = 5; ! - trailing blank lines literal SMBMSG$K_CHARACTERISTICS = 6; ! - /CHARACTERISTICS value literal SMBMSG$K_CHECKPOINT_DATA = 7; ! - checkpoint information literal SMBMSG$K_CONDITION_VECTOR = 8; ! - task error messages literal SMBMSG$K_DEVICE_NAME = 9; ! - /ON value literal SMBMSG$K_DEVICE_STATUS = 10; ! - device status literal SMBMSG$K_ENTRY_NUMBER = 11; ! - job entry number literal SMBMSG$K_EXECUTOR_QUEUE = 12; ! - this output queue literal SMBMSG$K_FILE_COPIES = 13; ! - /COPIES value literal SMBMSG$K_FILE_COUNT = 14; ! - current file copy number literal SMBMSG$K_FILE_SETUP_MODULES = 15; ! - file setup module list literal SMBMSG$K_FIRST_PAGE = 16; ! - first page to print literal SMBMSG$K_FORM_LENGTH = 17; ! - lines per page literal SMBMSG$K_FORM_NAME = 18; ! - name of physical form literal SMBMSG$K_FORM_SETUP_MODULES = 19; ! - form setup module list literal SMBMSG$K_FORM_WIDTH = 20; ! - columns per line literal SMBMSG$K_FILE_IDENTIFICATION = 21; ! - device, fid, and did literal SMBMSG$K_FILE_SPECIFICATION = 22; ! - file name literal SMBMSG$K_JOB_COPIES = 23; ! - /JOB_COUNT value literal SMBMSG$K_JOB_COUNT = 24; ! - current job copy number literal SMBMSG$K_JOB_NAME = 25; ! - /NAME value literal SMBMSG$K_JOB_RESET_MODULES = 26; ! - job reset module list literal SMBMSG$K_LAST_PAGE = 27; ! - last page to print literal SMBMSG$K_LEFT_MARGIN = 28; ! - leading blank columns literal SMBMSG$K_LIBRARY_SPECIFICATION = 29; ! - library name literal SMBMSG$K_MAXIMUM_STREAMS = 30; ! - maximum supported symbiont literal SMBMSG$K_MESSAGE_VECTOR = 31; ! - error messages to print literal SMBMSG$K_NOTE = 32; ! - /NOTE value literal SMBMSG$K_PAGE_SETUP_MODULES = 33; ! - page setup module list literal SMBMSG$K_PARAMETER_1 = 34; ! - user parameter 1 literal SMBMSG$K_PARAMETER_2 = 35; ! - user parameter 2 literal SMBMSG$K_PARAMETER_3 = 36; ! - user parameter 3 literal SMBMSG$K_PARAMETER_4 = 37; ! - user parameter 4 literal SMBMSG$K_PARAMETER_5 = 38; ! - user parameter 5 literal SMBMSG$K_PARAMETER_6 = 39; ! - user parameter 6 literal SMBMSG$K_PARAMETER_7 = 40; ! - user parameter 7 literal SMBMSG$K_PARAMETER_8 = 41; ! - user parameter 8 literal SMBMSG$K_PRINT_CONTROL = 42; ! - printing control literal SMBMSG$K_PRIORITY = 43; ! - queue priority literal SMBMSG$K_QUEUE = 44; ! - generic queue name literal SMBMSG$K_REFUSE_REASON = 45; ! - reason task refused literal SMBMSG$K_RELATIVE_PAGE = 46; ! - /BACKWARD, /FORWARD values literal SMBMSG$K_REQUEST_CONTROL = 47; ! - request control literal SMBMSG$K_REQUEST_RESPONSE = 48; ! - request code being responded to literal SMBMSG$K_RIGHT_MARGIN = 49; ! - trailing blank columns literal SMBMSG$K_SEARCH_STRING = 50; ! - /SEARCH value literal SMBMSG$K_SEPARATION_CONTROL = 51; ! - separation control literal SMBMSG$K_STOP_CONDITION = 52; ! - reason for print abort literal SMBMSG$K_TIME_QUEUED = 53; ! - time queued literal SMBMSG$K_TOP_MARGIN = 54; ! - leading blank lines literal SMBMSG$K_UIC = 55; ! - UIC of submittor literal SMBMSG$K_USER_NAME = 56; ! - username literal SMBMSG$K_CHECKPOINT_FREQUENCY = 57; ! - pages per checkpoint literal SMBMSG$K_QUEUING_CONTROL = 58; ! - queuing control literal SMBMSG$K_RETRY_TIME = 59; ! - delta time at which symbiont should retry job literal SMBMSG$K_DEVICE_CONDITION = 60; ! - device error messages literal SMBMSG$K_MESSAGE_FILE = 61; ! - symbiont's message file literal SMBMSG$K_AGENT_PROFILE = 62; ! - security info literal SMBMSG$K_CPU_LIMIT = 63; literal SMBMSG$K_FILE_SEPARATION = 64; literal SMBMSG$K_LOG_QUEUE = 65; literal SMBMSG$K_LOG_SPECIFICATION = 66; literal SMBMSG$K_LOG_SPOOL = 67; literal SMBMSG$K_OPERATOR_REQUEST = 68; literal SMBMSG$K_WSDEFAULT = 69; literal SMBMSG$K_WSEXTENT = 70; literal SMBMSG$K_WSQUOTA = 71; literal SMBMSG$K_FILE_ATTRIBUTES = 72; literal SMBMSG$K_FILE_ATTRIBUTES_SIZE = 73; literal SMBMSG$K_JOB_ATTRIBUTES = 74; literal SMBMSG$K_JOB_ATTRIBUTES_SIZE = 75; literal SMBMSG$K_QUEUE_ATTRIBUTES = 76; literal SMBMSG$K_QUEUE_ATTRIBUTES_SIZE = 77; literal SMBMSG$K_SUBMITTER_EPID = 78; ! literal SMBMSG$K_MAX_ITEM_CODE = 79; ! MUST BE LAST literal SMBMSG$S_SMBMSG_ITEM_HEADER = 4; macro SMBMSG$W_ITEM_SIZE = 0,0,16,0 %; ! Item size macro SMBMSG$W_ITEM_CODE = 2,0,16,0 %; ! Item code ! Define item codes literal SMBMSG$S_ITEM_HEADER = 4; ! Size (using prior aggregate name) ! ! ACCOUNTING_DATA item ! literal SMBMSG$S_ACCOUNTING_DATA = 16; macro SMBMSG$L_PAGES_PRINTED = 0,0,32,0 %; ! Pages printed macro SMBMSG$l_qio_puts = 4,0,32,0 %; ! Lines printed macro SMBMSG$l_rms_gets = 8,0,32,0 %; ! File reads macro SMBMSG$L_CPU_TIME = 12,0,32,0 %; ! Processor time ! ! CHECKPOINT_DATA item ! literal SMBMSG$S_CHECKPOINT_DATA = 24; macro SMBMSG$B_FILLER = 0,0,8,0 %; ! Reserved macro SMBMSG$B_CHECKPOINT_LEVEL = 1,0,8,0 %; ! Checkpoint structure level macro SMBMSG$W_OFFSET = 2,0,16,0 %; ! Offset into record macro SMBMSG$L_CARCON = 4,0,32,0 %; ! Carriage control macro SMBMSG$L_PAGE = 8,0,32,0 %; ! Page number macro SMBMSG$L_RECORD_NUMBER = 12,0,32,0 %; ! Record number macro SMBMSG$Q_USER_KEY = 16,0,0,1 %; literal SMBMSG$S_USER_KEY = 8; ! User positioning key ! ! DEVICE_STATUS item ! literal SMBMSG$M_LOWERCASE = %X'1'; literal SMBMSG$M_PAUSE_TASK = %X'2'; literal SMBMSG$M_REMOTE = %X'4'; literal SMBMSG$M_SERVER = %X'8'; literal SMBMSG$M_STALLED = %X'10'; literal SMBMSG$M_STOP_STREAM = %X'20'; literal SMBMSG$M_TERMINAL = %X'40'; literal SMBMSG$M_UNAVAILABLE = %X'80'; literal SMBMSG$M_SYM_NOTIFIES = %X'100'; literal SMBMSG$M_SYM_REQUESTS_OPER = %X'200'; literal SMBMSG$M_SYM_COPIES_FILE = %X'400'; literal SMBMSG$M_SYM_COPIES_JOB = %X'800'; literal SMBMSG$M_SYM_ACCEPTS_ALL_FORMS = %X'1000'; literal SMBMSG$M_SYM_NO_JOB_CHECKPOINT = %X'2000'; literal SMBMSG$M_SYM_ALL_CHARACTERISTIC = %X'4000'; literal SMBMSG$M_NOTIFY_ON_INTERRUPT = %X'8000'; literal SMBMSG$S_DEVICE_STATUS = 4; macro SMBMSG$L_DEVICE_FLAGS = 0,0,32,0 %; ! Device flags macro SMBMSG$V_LOWERCASE = 0,0,1,0 %; ! - supports lowercase macro SMBMSG$V_PAUSE_TASK = 0,1,1,0 %; ! - symbiont initiated pause macro SMBMSG$V_REMOTE = 0,2,1,0 %; ! - device is remote macro SMBMSG$V_SERVER = 0,3,1,0 %; ! - server symbiont macro SMBMSG$V_STALLED = 0,4,1,0 %; ! - task stalled macro SMBMSG$V_STOP_STREAM = 0,5,1,0 %; ! - symbiont requesting stop stream macro SMBMSG$V_TERMINAL = 0,6,1,0 %; ! - device is a terminal macro SMBMSG$V_UNAVAILABLE = 0,7,1,0 %; ! - device unavailable macro SMBMSG$V_SYM_NOTIFIES = 0,8,1,0 %; ! - Symbiont notifies for job completions macro SMBMSG$V_SYM_REQUESTS_OPER = 0,9,1,0 %; ! - Symbiont generates operator messages macro SMBMSG$V_SYM_COPIES_FILE = 0,10,1,0 %; ! - Symbiont generates multiple file copies macro SMBMSG$V_SYM_COPIES_JOB = 0,11,1,0 %; ! - Symbiont generates multiple job copies macro SMBMSG$V_SYM_ACCEPTS_ALL_FORMS = 0,12,1,0 %; ! - Symbiont processes all form types macro SMBMSG$V_SYM_NO_JOB_CHECKPOINT = 0,13,1,0 %; ! - Always reprocess full job on a restart macro SMBMSG$V_SYM_ALL_CHARACTERISTIC = 0,14,1,0 %; ! - Symbiont processes all characteristics macro SMBMSG$V_NOTIFY_ON_INTERRUPT = 0,15,1,0 %; ! - Symbiont notifies user on job interrupt ! ! PRINT_CONTROL item ! literal SMBMSG$M_DOUBLE_SPACE = %X'1'; literal SMBMSG$M_PAGE_HEADER = %X'2'; literal SMBMSG$M_PAGINATE = %X'4'; literal SMBMSG$M_PASSALL = %X'8'; literal SMBMSG$M_SEQUENCED = %X'10'; literal SMBMSG$M_SHEET_FEED = %X'20'; literal SMBMSG$M_TRUNCATE = %X'40'; literal SMBMSG$M_WRAP = %X'80'; literal SMBMSG$M_RECORD_BLOCKING = %X'100'; literal SMBMSG$M_PAGE_FOOTER = %X'200'; literal SMBMSG$M_DELETE_FILE = %X'400'; literal SMBMSG$M_LOWERCASE_EXPLICIT = %X'800'; literal SMBMSG$M_NOTIFY = %X'1000'; literal SMBMSG$M_RESTART = %X'2000'; literal SMBMSG$M_JOB_RETAIN = %X'4000'; literal SMBMSG$M_JOB_ERROR_RETAIN = %X'8000'; literal SMBMSG$M_NO_INITIAL_FF = %X'10000'; literal SMBMSG$S_PRINT_CONTROL = 4; macro SMBMSG$L_PRINT_FLAGS = 0,0,32,0 %; ! Print flags macro SMBMSG$V_DOUBLE_SPACE = 0,0,1,0 %; ! - double space macro SMBMSG$V_PAGE_HEADER = 0,1,1,0 %; ! - print page headers macro SMBMSG$V_PAGINATE = 0,2,1,0 %; ! - insert 's macro SMBMSG$V_PASSALL = 0,3,1,0 %; ! - binary print file macro SMBMSG$V_SEQUENCED = 0,4,1,0 %; ! - print sequence numbers macro SMBMSG$V_SHEET_FEED = 0,5,1,0 %; ! - pause at every TOF macro SMBMSG$V_TRUNCATE = 0,6,1,0 %; ! - truncate on overflow macro SMBMSG$V_WRAP = 0,7,1,0 %; ! - wrap on overflow macro SMBMSG$V_RECORD_BLOCKING = 0,8,1,0 %; ! - block records in output buffer macro SMBMSG$V_PAGE_FOOTER = 0,9,1,0 %; ! - print page footers macro SMBMSG$V_DELETE_FILE = 0,10,1,0 %; ! - delete file after printing macro SMBMSG$V_LOWERCASE_EXPLICIT = 0,11,1,0 %; ! - job for printer that supports lowercase macro SMBMSG$V_NOTIFY = 0,12,1,0 %; ! - notify user when job completes macro SMBMSG$V_RESTART = 0,13,1,0 %; ! - restart job after crash or requeue macro SMBMSG$V_JOB_RETAIN = 0,14,1,0 %; ! - per job retain macro SMBMSG$V_JOB_ERROR_RETAIN = 0,15,1,0 %; ! - per job retain on error macro SMBMSG$V_NO_INITIAL_FF = 0,16,1,0 %; ! - output form feed on START/QUEUE ! ! REQUEST_CONTROL item ! literal SMBMSG$M_ALIGNMENT_MASK = %X'1'; literal SMBMSG$M_PAUSE_COMPLETE = %X'2'; literal SMBMSG$M_RESTARTING = %X'4'; literal SMBMSG$M_TOP_OF_FILE = %X'8'; literal SMBMSG$S_REQUEST = 4; macro SMBMSG$L_REQUEST_FLAGS = 0,0,32,0 %; ! Print flags macro SMBMSG$V_ALIGNMENT_MASK = 0,0,1,0 %; ! - print A's and 9's macro SMBMSG$V_PAUSE_COMPLETE = 0,1,1,0 %; ! - pause when request complete macro SMBMSG$V_RESTARTING = 0,2,1,0 %; ! - job is restarting macro SMBMSG$V_TOP_OF_FILE = 0,3,1,0 %; ! - rewind before resume ! ! SEPARATION_CONTROL item ! literal SMBMSG$M_FILE_BURST = %X'1'; literal SMBMSG$M_FILE_FLAG = %X'2'; literal SMBMSG$M_FILE_TRAILER = %X'4'; literal SMBMSG$M_FILE_TRAILER_ABORT = %X'8'; literal SMBMSG$M_JOB_FLAG = %X'10'; literal SMBMSG$M_JOB_BURST = %X'20'; literal SMBMSG$M_JOB_RESET = %X'40'; literal SMBMSG$M_JOB_RESET_ABORT = %X'80'; literal SMBMSG$M_JOB_TRAILER = %X'100'; literal SMBMSG$M_JOB_TRAILER_ABORT = %X'200'; literal SMBMSG$M_FIRST_FILE_OF_JOB = %X'400'; literal SMBMSG$M_LAST_FILE_OF_JOB = %X'800'; literal SMBMSG$S_SEPARATION_CONTROL = 4; macro SMBMSG$L_SEPARATION_FLAGS = 0,0,32,0 %; ! Print flags macro SMBMSG$V_FILE_BURST = 0,0,1,0 %; ! - print file burst page macro SMBMSG$V_FILE_FLAG = 0,1,1,0 %; ! - print file flag page macro SMBMSG$V_FILE_TRAILER = 0,2,1,0 %; ! - print file trailer page macro SMBMSG$V_FILE_TRAILER_ABORT = 0,3,1,0 %; ! - print file trailer page macro SMBMSG$V_JOB_FLAG = 0,4,1,0 %; ! - print job flag page macro SMBMSG$V_JOB_BURST = 0,5,1,0 %; ! - print job burst page macro SMBMSG$V_JOB_RESET = 0,6,1,0 %; ! - execute job reset sequence macro SMBMSG$V_JOB_RESET_ABORT = 0,7,1,0 %; ! - execute job reset sequence macro SMBMSG$V_JOB_TRAILER = 0,8,1,0 %; ! - print job trailer page macro SMBMSG$V_JOB_TRAILER_ABORT = 0,9,1,0 %; ! - print job trailer page macro SMBMSG$V_FIRST_FILE_OF_JOB = 0,10,1,0 %; ! - this is the first file of the current job macro SMBMSG$V_LAST_FILE_OF_JOB = 0,11,1,0 %; ! - this is the last file of the current job ! ! QUEUING_CONTROL item ! literal SMBMSG$M_RETAIN_JOB = %X'1'; literal SMBMSG$S_QUEUING_CONTROL = 4; macro SMBMSG$L_QUEUING_FLAGS = 0,0,32,0 %; ! Queuing flags macro SMBMSG$V_RETAIN_JOB = 0,0,1,0 %; ! - symbiont retained job on "fixable" error !*** MODULE SNAPFKVECDEF *** literal SNAPFKVEC$K_TIMEOUT = 15; ! MAXIMUM DELAY TIME literal SNAPFKVEC$K_LENGTH = 32; ! LENGTH OF OVERHEAD AREA literal SNAPFKVEC$C_LENGTH = 32; ! LENGTH OF OVERHEAD AREA literal SNAPFKVEC$S_SNAPFKVECDEF = 32; literal SNAPFKVEC$S_SNAPFKVEC = 32; macro SNAPFKVEC$L_FQFL = 0,0,32,1 %; ! FORK QUEUE FORWARD LINK macro SNAPFKVEC$L_FQBL = 4,0,32,1 %; ! FORK QUEUE BACKWARD LINK macro SNAPFKVEC$W_SIZE = 8,0,16,0 %; ! SIZE OF BLOCK IN BYTES macro SNAPFKVEC$W_TYPE = 10,0,16,0 %; ! STRUCTURE TYPE macro SNAPFKVEC$L_REFCNT = 12,0,32,0 %; ! REFERENCE COUNT macro SNAPFKVEC$L_COUNT = 16,0,32,0 %; ! MAXIMUM VECTOR INDEX macro SNAPFKVEC$W_EVENT = 20,0,16,0 %; ! CURRENT EVENT CODE macro SNAPFKVEC$W_SEED = 22,0,16,0 %; ! SEQUENCE SEED macro SNAPFKVEC$L_STATUS = 24,0,32,0 %; ! ABORT STATUS macro SNAPFKVEC$L_VECTOR = 28,0,32,1 %; ! BEGINNING OF VECTOR AREA ! THE VECTOR AREA SIZE IS "COUNT" LONGWORDS !*** MODULE SNAPSTATEDEF *** literal SNAPSTATE$M_ACTIVE = %X'1'; literal SNAPSTATE$M_NORETURN = %X'2'; literal SNAPSTATE$M_ABORT = %X'4'; literal SNAPSTATE$M_RESUME = %X'8'; literal SNAPSTATE$M_POWER = %X'10'; literal SNAPSTATE$M_WATCHDOG = %X'20'; literal SNAPSTATE$M_ENABLEWATCH = %X'40'; literal SNAPSTATE$M_DEBUG = %X'80'; literal SNAPSTATE$M_CLEANUP = %X'100'; literal SNAPSTATE$S_SNAPSTATEDEF = 4; literal SNAPSTATE$S_SNAPSTATE = 4; macro SNAPSTATE$V_ACTIVE = 0,0,1,0 %; ! Snapshot process is active macro SNAPSTATE$V_NORETURN = 0,1,1,0 %; ! Snapshot is committed and an abort is not possible macro SNAPSTATE$V_ABORT = 0,2,1,0 %; ! Snapshot being aborted macro SNAPSTATE$V_RESUME = 0,3,1,0 %; ! O.K. to resume other processes. macro SNAPSTATE$V_POWER = 0,4,1,0 %; ! Powerfail exception in progress macro SNAPSTATE$V_WATCHDOG = 0,5,1,0 %; ! Snapshot watchdog is active (set by the watchdog process) macro SNAPSTATE$V_ENABLEWATCH = 0,6,1,0 %; ! Snapshot watchdog is enabled (set by the snapshot process) macro SNAPSTATE$V_DEBUG = 0,7,1,0 %; ! Snapshot watchdog may detect erroneous timeouts caused by the debugger macro SNAPSTATE$V_CLEANUP = 0,8,1,0 %; ! Snapshot cleanup process has been started !*** MODULE $SPIDEF *** ! + ! $SPIDEF - SCSI CLASS/PORT DRIVER INTERFACE DEFINITIONS. ! - literal SPI$K_PBCB_STOP_BUSY = -1; ! Port is busy literal SPI$K_PBCB_STOP_CHECK_CONDITION = -2; ! Port has seen a check condition event. literal SPI$K_PBCB_STOP_QUEUE_FULL_EVNT = -3; ! Port has seen a queue full event. literal SPI$K_PBCB_STOP_BUS_RESET = -4; ! Port has seen a bus reset literal SPI$K_PBCB_STOP_NO_SEND_CREDITS = -5; ! Port has run out of send credits. literal SPI$K_PBCB_STOP_NO_CMD_BITS = -6; ! Port has run out of cmd bits literal SPI$K_PBCB_STOP_LINK = -7; ! FibreChannel link is unavailable literal SPI$K_PBCB_GO_READY = 0; ! Port is no longer busy literal SPI$K_PBCB_GO_ACA_COMPLETE = 1; ! Port has finished the ACA processing. literal SPI$K_PBCB_GO_QUEUE_STARTING = 2; ! Port is attempting to restart the queue following the queue full event. literal SPI$K_PBCB_GO_BUS_FREE = 3; ! Port has finished bus reset, bus is free literal SPI$K_PBCB_GO_SEND_CREDITS = 4; ! Port has send credits available literal SPI$K_PBCB_GO_CMD_BITS = 5; ! Port has cmd bits available literal SPI$K_PBCB_GO_LINK = 6; ! FibreChannel link is available ! ! SPI$K_PCB_CHANGE_AFFINITY has a value of 127, make sure ! that the entry you're adding does't conflict with that! ! literal SPI$K_PCB_AFFINITY = 127; ! Port has set affinity to a new CPU ! Structure used by SPI$GET_CONNECTION_CHAR and SPI$SET_CONNECTION_CHAR literal SPI$K_CC_NUM_ARGS = 10; ! Current required count literal SPI$K_CC_QNUM_ARGS = 12; ! TCQ adds 2 longword arguments literal SPI$M_CC_ENA_DISCON = %X'1'; literal SPI$M_CC_DIS_RETRY = %X'2'; literal SPI$M_CC_CLASS_REQ_SDTR = %X'8'; literal SPI$M_CC_SUPPRESS_SDTR = %X'10'; literal SPI$K_CC_DEF_FLAGS = 0; ! Default connection flags literal SPI$K_CC_DEF_SYNCH = 0; ! Default synch xfer support literal SPI$K_CC_DEF_XFERPERIOD = 64; ! Default REQ/ACK tick count literal SPI$K_CC_DEF_REQACKOFF = 3; ! Default REQs before ACK literal SPI$K_CC_DEF_BSYRTY = 2000; ! Default bus free retry cnt literal SPI$K_CC_DEF_ARBRTY = 5; ! Default arb retry count literal SPI$K_CC_DEF_SELRTY = 3; ! Default sel retry count literal SPI$K_CC_DEF_CMDRTY = 3; ! Default cmd retry count literal SPI$K_CC_DEF_DMATMO = 4; ! Default DMA/Phase timeout literal SPI$K_CC_DEF_DISCTMO = 4; ! Default Disconnect timeout literal SPI$M_CC_CMDQ = %X'1'; literal SPI$M_CC_FLUSHQ = %X'2'; literal SPI$M_CC_FREEZEQ = %X'4'; literal SPI$M_CC_SCSI_2 = %X'8'; literal SPI$M_CC_SCSI_3 = %X'10'; literal SPI$M_CC_CLS_DRVR_ACA = %X'20'; literal SPI$K_CC_DEF_MAX_QDEPTH = 1; ! Default maximum queue depth literal SPI$K_CC_LENGTH = 52; ! Length of SPI_CC structure literal SPI$S_SPI_CC_DEF = 52; ! Old size name, synonym for SPI$S_SPI literal SPI$S_SPI = 56; macro SPI$IL_CC_COUNT = 0,0,32,1 %; ! Count of longword arguments macro SPI$IL_CC_CON_FLAGS = 4,0,32,0 %; ! Connection flags macro SPI$V_CC_ENA_DISCON = 4,0,1,0 %; ! Discon/Resel enabled macro SPI$V_CC_DIS_RETRY = 4,1,1,0 %; ! Disable command retry macro SPI$V_CC_CLASS_REQ_SDTR = 4,3,1,0 %; ! Class driver is requesting SDTR macro SPI$V_CC_SUPPRESS_SDTR = 4,4,1,0 %; ! Class driver is suppressing SDTR macro SPI$IL_CC_SYNCHRONOUS = 8,0,32,1 %; ! Sychronous transfer support macro SPI$IL_CC_TRANSFER_PERIOD = 12,0,32,1 %; ! Ticks between REQ & ACK macro SPI$IL_CC_REQACK_OFFSET = 16,0,32,1 %; ! REQs before ACK macro SPI$IL_CC_BUSY_RETRY_CNT = 20,0,32,1 %; ! Retries before bus free macro SPI$IL_CC_ARB_RETRY_CNT = 24,0,32,1 %; ! Retries before arbitration macro SPI$IL_CC_SEL_RETRY_CNT = 28,0,32,1 %; ! Retries on selections macro SPI$IL_CC_CMD_RETRY_CNT = 32,0,32,1 %; ! Retries on command send macro SPI$IL_CC_DMA_TIMEOUT = 36,0,32,1 %; ! DMA/Phase timeout macro SPI$IL_CC_DISC_TIMEOUT = 40,0,32,1 %; ! Disconnect timeout macro SPI$IL_CC_SCSI_FLAGS = 44,0,32,0 %; ! SCSI flags, including TCQ macro SPI$V_CC_CMDQ = 44,0,1,0 %; ! Device supports TCQ macro SPI$V_CC_FLUSHQ = 44,1,1,0 %; ! Flush queue on error ! MBZ, reserved for SCSI-3 macro SPI$V_CC_FREEZEQ = 44,2,1,0 %; ! Freeze queue on error ! MBZ, reserved for SCSI-3 macro SPI$V_CC_SCSI_2 = 44,3,1,0 %; ! Device is SCSI-2 conformant macro SPI$V_CC_SCSI_3 = 44,4,1,0 %; ! Device is SCSI-3 conformant macro SPI$V_CC_CLS_DRVR_ACA = 44,5,1,0 %; ! Class Driver needs ACA macro SPI$IL_CC_MAX_QDEPTH = 48,0,32,1 %; ! Maximum queue depth if TCQ !*** MODULE $SPLCODDEF *** ! + ! ! SPINLOCK INDEX DEFINITIONS ! ! - ! ! DEFINE THE HARDWARE LEVEL LOCKS (INDICES 0-F) ! literal SPL$C_EMB = 32; ! EMB spinlock index literal SPL$C_MCHECK = 33; ! Machine Check spinlock index literal SPL$C_MEGA = 34; ! Kitchen sink of spinlocks literal SPL$C_HWCLK = 36; ! HWCLK spinlock index literal SPL$C_INVALIDATE = 38; ! INVALIDATE spinlock index literal SPL$C_PERFMON = 40; ! PERFMON spinlock index literal SPL$C_POOL = 42; ! POOL spinlock index literal SPL$C_MAILBOX = 44; ! MAILBOX spinlock index literal SPL$C_IOLOCK11 = 46; ! IPL 11 I/O spinlock index literal SPL$C_IOLOCK10 = 47; ! IPL 10 I/O spinlock index literal SPL$C_IOLOCK9 = 48; ! IPL 9 I/O spinlock index literal SPL$C_SCHED = 50; ! SCHED spinlock index literal SPL$C_MMG = 52; ! Memory management spinlock index literal SPL$C_IO_MISC = 54; ! Miscellaneous short time I/O spinlock index literal SPL$C_PORT = 55; ! Multiple device ports index literal SPL$C_TIMER = 56; ! TIMER spinlock index literal SPL$C_TX_SYNCH = 57; ! Transaction processing lock literal SPL$C_IOLOCK8 = 58; ! IPL 8 I/O spinlock index literal SPL$C_LCKMGR = 59; ! Lock Manager lock literal SPL$C_FILSYS = 60; ! File system spinlock index literal SPL$C_QUEUEAST = 62; ! QUEUEAST spinlock index literal SPL$C_SCS = 58; ! SCS spinlock index ! Define dynamic spinlock symbol literal SPL$C_DYNAMIC = 255; ! DYNAMIC spinlock non-index literal SPL$_MIN_INDEX = 32; ! Min spinlock index literal SPL$_MAX_INDEX = 62; ! Max spinlock index literal SPL$_NUM_LOCKS = 31; ! Max number of spinlocks (ever) ! ! Define some system-wide multiprocessing control flags ! literal SMP$M_ENABLED = %X'1'; literal SMP$M_START_CPU = %X'2'; literal SMP$M_CRASH_CPU = %X'4'; literal SMP$M_TODR = %X'8'; literal SMP$M_UNMOD_DRIVER = %X'10'; literal SMP$M_TODR_ACK = %X'20'; literal SMP$M_SYNCH = %X'40'; literal SMP$M_BENIGN = %X'80'; literal SMP$M_MINIMUM_ACQUIRE = %X'100'; literal SMP$M_READ_SCC = %X'200'; literal SMP$M_READ_SCC_ACK = %X'400'; literal SMP$M_CLOCKS_SYNCH = %X'800'; literal SMP$M_DISPLAY_TRANSITIONS = %X'1000'; literal SMP$M_FW_STATE_CHECK = %X'2000'; literal SMP$M_MULTIQUAD_NMSP = %X'4000'; literal SMP$M_OVERRIDE = %X'1'; literal SMP$M_FOREVER = %X'2'; literal SMP$M_FKB_FRU_CHANGE = %X'1'; literal SMP$M_FKB_DOORBELL = %X'2'; literal SMP$S_SMPDEF = 4; ! Old size name, synonym for SMP$S_SMP literal SMP$M_PORTLOCK = %X'1'; literal SMP$M_INIT_ONLY = %X'2'; literal SMP$M_KNOWN_BY_SDA = %X'4'; literal SMP$S_SMP = 5; macro SMP$V_ENABLED = 0,0,1,0 %; ! SMP operation is enabled macro SMP$V_START_CPU = 0,1,1,0 %; ! PRIMARY CPU has finished INIT macro SMP$V_CRASH_CPU = 0,2,1,0 %; ! A CPU is initiating BUGCHECK macro SMP$V_TODR = 0,3,1,0 %; ! SMP$GL_PROPOSED_TODR in use macro SMP$V_UNMOD_DRIVER = 0,4,1,0 %; ! Unmodified driver is loaded macro SMP$V_TODR_ACK = 0,5,1,0 %; ! SMP TODR operation complete macro SMP$V_SYNCH = 0,6,1,0 %; ! SMP SYNCHRONIZATION IMAGE LOADED macro SMP$V_BENIGN = 0,7,1,0 %; ! BENIGN STATE REQUESTED macro SMP$V_MINIMUM_ACQUIRE = 0,8,1,0 %; ! Least overhead in acquisition macro SMP$V_READ_SCC = 0,9,1,0 %; ! Request PRIMARY CPU to read its SCC macro SMP$V_READ_SCC_ACK = 0,10,1,0 %; ! PRIMARY CPU has recorded its SCC value. macro SMP$V_CLOCKS_SYNCH = 0,11,1,0 %; ! Clocks are synchronized....therefore ! soft affinity is supported on this system. macro SMP$V_DISPLAY_TRANSITIONS = 0,12,1,0 %; ! Display verbose transition text macro SMP$V_FW_STATE_CHECK = 0,13,1,0 %; ! Toggle 1-second timer check for migrations macro SMP$V_MULTIQUAD_NMSP = 0,14,1,0 %; ! Bitmaps of more than 1 quadword needed for namespace macro SMP$V_OVERRIDE = 2,0,1,0 %; ! Skip checks before stopping CPU macro SMP$V_FOREVER = 2,1,1,0 %; ! FOREVER means remove from ! available set after stopping. macro SMP$V_FKB_FRU_CHANGE = 3,0,1,0 %; ! FKB to indicate config tree change in use macro SMP$V_FKB_DOORBELL = 3,1,1,0 %; ! FKB for doorbell console callback in use macro SMP$V_PORTLOCK = 4,0,1,0 %; ! set rank and subtype to portlock defaults macro SMP$V_INIT_ONLY = 4,1,1,0 %; ! initialize spinlocks only--don't allocate memory macro SMP$V_KNOWN_BY_SDA = 4,2,1,0 %; ! note that SDA already recognizes this spinlock !*** MODULE $SPNBDEF *** ! + ! SPNB - SCA POLLER NAME BLOCK ! ! THIS DATA STRUCTURE CONTAINS A LIST OF PROCESS NAMES WHICH WILL ! BE SEARCHED FOR ON THE GIVEN REMOTE NODE. ! - literal SPNB$C_HDRSIZ = 24; ! SIZE OF HEADER literal SPNB$S_SPNBDEF = 25; literal SPNB$S_SPNB = 25; macro SPNB$L_FLINK = 0,0,32,1 %; ! FWD LINK macro SPNB$L_BLINK = 4,0,32,1 %; ! BCK LINK macro SPNB$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro SPNB$B_TYPE = 10,0,8,0 %; ! SCS STRUCTURE TYPE macro SPNB$B_SUBTYP = 11,0,8,0 %; ! SCS STRUCTURE SUBTYPE FOR SPNB macro SPNB$L_SB = 12,0,32,0 %; ! SYSTEM BLOCK OF REMOTE NOTE macro SPNB$L_ROUTINE = 16,0,32,1 %; ! ADDRESS OF ROUTINE TO BE CALLED WHEN PROCESS FOUND macro SPNB$B_INDEX = 20,0,8,0 %; ! INDEX INTO PROCESS LIST OF NEXT PROCESS TO SEARCH FOR macro SPNB$W_REFC = 21,0,16,0 %; ! NUMBER OF REFERENCES TO SPNB macro SPNB$B_FREE = 23,0,8,0 %; literal SPNB$S_FREE = 1; ! FREE BYTE macro SPNB$B_NAMLST = 24,0,8,0 %; ! START OF VARIABLE LENGTH LIST OF ADDRESSES OF PROCESS NAMES ! LIST IS ZERO TERMINATED !*** MODULE $SPPADEF *** literal PDIR$M_VINDEX = %X'FF'; literal PDIR$M_SV = %X'800'; literal PDIR$M_V = %X'8000000000000000'; literal PDIR$S_SPPA_IO_PDIR = 8; macro PDIR$V_VINDEX = 0,0,8,0 %; literal PDIR$S_VINDEX = 8; ! Virtual index 0xFF on Itanium macro PDIR$V_SV = 0,11,1,0 %; ! Swap control field is valid macro PDIR$V_PPN = 0,12,43,0 %; literal PDIR$S_PPN = 43; ! Physical Page number (PFN) macro PDIR$V_SWAP_CTRL = 4,23,8,0 %; literal PDIR$S_SWAP_CTRL = 8; ! Swap control field (documentation?) macro PDIR$V_V = 4,31,1,0 %; ! Valid PDIR entry literal SPPA$S_SPPA_FUNC_HDR = 16; macro SPPA$Q_FUNC_ID = 0,0,0,0 %; literal SPPA$S_FUNC_ID = 8; ! 000 Function Id macro SPPA$W_VENDOR_ID = 0,0,16,0 %; ! 00 HP is 103C macro SPPA$W_FUNCTION_ID = 2,0,16,0 %; ! 02 Unique w/in Vendor macro SPPA$W_CONTROL = 4,0,16,0 %; ! 04 See PCI Spec macro SPPA$W_STATUS = 6,0,16,0 %; ! 06 See PCI spec macro SPPA$Q_FUNC_CLASS = 8,0,0,0 %; literal SPPA$S_FUNC_CLASS = 8; ! 008 Function Class macro SPPA$B_REVISION = 8,0,8,0 %; ! 08 Rev w/in Function ID macro SPPA$B_INTERFACE = 9,0,8,0 %; ! 09 Class Code - Interface macro SPPA$B_SUB_CLASS = 10,0,8,0 %; ! 0A Class Code - Subclass macro SPPA$B_BASE_CLASS = 11,0,8,0 %; ! 0B Class Code - Base Class literal SPPA$M_IM = %X'8000'; literal SPPA$M_CONTROL_RF = %X'1'; literal SPPA$M_CONTROL_FF = %X'2'; literal SPPA$M_CONTROL_RV = %X'4'; literal SPPA$M_CONTROL_CL = %X'8'; literal SPPA$M_CONTROL_CE = %X'10'; literal SPPA$M_CONTROL_HF = %X'20'; literal SPPA$M_STATUS_RC = %X'80000000'; literal SPPA$S_SPPA_MOD_STATUS = 16; macro SPPA$Q_MOD_INFO = 0,0,0,0 %; literal SPPA$S_MOD_INFO = 8; ! 100 Module Information macro SPPA$V_PHYSICAL_ID = 0,0,15,0 %; literal SPPA$S_PHYSICAL_ID = 15; ! Unique Module ID macro SPPA$V_IM = 0,15,1,0 %; ! Implementation-dependent macro SPPA$W_FUNCTIONS_PRESENT = 2,0,16,0 %; ! Functions present mask; F0 MBO macro SPPA$Q_STATUS_CONTROL = 8,0,0,0 %; literal SPPA$S_STATUS_CONTROL = 8; ! 108 Status/Control Info macro SPPA$V_CONTROL_RF = 8,0,1,0 %; ! Resets Function macro SPPA$V_CONTROL_FF = 8,1,1,0 %; ! Forwards Firmware Xactions (?) macro SPPA$V_CONTROL_RV = 8,2,1,0 %; ! Reserved macro SPPA$V_CONTROL_CL = 8,3,1,0 %; ! Clear Error Logging macro SPPA$V_CONTROL_CE = 8,4,1,0 %; ! Enable Error Log Clearing macro SPPA$V_CONTROL_HF = 8,5,1,0 %; ! Hard Fail Enable macro SPPA$V_STATUS_RC = 8,31,1,0 %; ! Reset-in-progress if set literal SBA$S_SPPA_SBA_MAP = 4096; macro SBA$R_SBA_HDR = 0,0,0,0 %; literal SBA$S_SBA_HDR = 16; macro SBA$R_SBA_MOD = 256,0,0,0 %; literal SBA$S_SBA_MOD = 16; literal SPPA$S_SPPA_SBA_MAP_LENGTH = 4096; literal IOC$M_RE = %X'1'; literal IOC$K_TS_4K = 0; ! 4K Page Size literal IOC$K_TS_8K = 1; ! 8K Page Size literal IOC$K_TS_16K = 2; ! 16K Page Size literal IOC$K_TS_64K = 3; ! 64K Page Size literal IOC$M_CTRL_FLUSH_CACHE = %X'400'; literal IOC$M_CTRL_IOCB_EMPTY = %X'800'; literal IOC$M_FLUSH_CACHE = %X'1'; literal IOC$M_FLUSH_2_CLEAN = %X'2'; literal IOC$M_FLUSH_ALL_CURRENT = %X'4'; literal IOC$M_PR_PLUNGE = %X'8'; literal IOC$M_FIP_SNAP = %X'10'; literal IOC$S_SPPA_IOC_MAP = 4096; macro IOC$Q_FUNC_ID = 0,0,0,0 %; literal IOC$S_FUNC_ID = 8; macro IOC$Q_MOD_INFO = 256,0,0,0 %; literal IOC$S_MOD_INFO = 8; macro IOC$Q_LBA_PORT0_CNTRL = 512,0,0,0 %; literal IOC$S_LBA_PORT0_CNTRL = 8; ! 200 LBA 0 Port Control macro IOC$Q_LBA_PORT1_CNTRL = 520,0,0,0 %; literal IOC$S_LBA_PORT1_CNTRL = 8; ! 208 LBA 1 Port Control macro IOC$Q_LBA_PORT2_CNTRL = 528,0,0,0 %; literal IOC$S_LBA_PORT2_CNTRL = 8; ! 210 LBA 2 Port Control macro IOC$Q_LBA_PORT3_CNTRL = 536,0,0,0 %; literal IOC$S_LBA_PORT3_CNTRL = 8; ! 218 LBA 3 Port Control macro IOC$Q_LBA_PORT4_CNTRL = 544,0,0,0 %; literal IOC$S_LBA_PORT4_CNTRL = 8; ! 220 LBA 4 Port Control macro IOC$Q_LBA_PORT5_CNTRL = 552,0,0,0 %; literal IOC$S_LBA_PORT5_CNTRL = 8; ! 228 LBA 5 Port Control macro IOC$Q_LBA_PORT6_CNTRL = 560,0,0,0 %; literal IOC$S_LBA_PORT6_CNTRL = 8; ! 230 LBA 6 Port Control macro IOC$Q_LBA_PORT7_CNTRL = 568,0,0,0 %; literal IOC$S_LBA_PORT7_CNTRL = 8; ! 238 LBA 7 Port Control macro IOC$Q_IBASE = 768,0,0,0 %; literal IOC$S_IBASE = 8; ! 300 Base of IOV Space macro IOC$V_RE = 768,0,1,0 %; ! Enable Mapping on Range macro IOC$Q_IMASK = 776,0,0,0 %; literal IOC$S_IMASK = 8; ! 308 Mask/Size of IOV Space macro IOC$Q_PCOM = 784,0,0,0 %; literal IOC$S_PCOM = 8; ! 310 Purge Command macro IOC$V_SIZE = 784,0,5,0 %; literal IOC$S_SIZE = 5; ! Naturally Aligned Purge Size macro IOC$V_PURGE_ADDR = 784,12,20,0 %; literal IOC$S_PURGE_ADDR = 20; ! Address Range to be Purged macro IOC$Q_TCNFG = 792,0,0,0 %; literal IOC$S_TCNFG = 8; ! 318 IOTLB Configuration macro IOC$V_TS = 792,0,2,0 %; literal IOC$S_TS = 2; ! TLB Page Size Code macro IOC$Q_PDIR = 800,0,0,0 %; literal IOC$S_PDIR = 8; ! 320 Physical Addr of IOTLB macro IOC$V_PDIR_BASE = 800,12,32,0 %; literal IOC$S_PDIR_BASE = 32; ! IOTLB PA bit extent macro IOC$Q_FLUSH_CTRL = 1024,0,0,0 %; literal IOC$S_FLUSH_CTRL = 8; ! 400 Flush/IKE compatibility macro IOC$V_CTRL_FLUSH_CACHE = 1024,10,1,0 %; ! Flush entire cache, then reset macro IOC$V_CTRL_IOCB_EMPTY = 1024,11,1,0 %; ! Set when IOC buffer is empty macro IOC$Q_FLUSH_COMMAND = 1064,0,0,0 %; literal IOC$S_FLUSH_COMMAND = 8; ! 428 Flush Command macro IOC$V_FLUSH_CACHE = 1064,0,1,0 %; ! Flush entire cache, then reset macro IOC$V_FLUSH_2_CLEAN = 1064,1,1,0 %; ! Flush dirty cache lines, then reset macro IOC$V_FLUSH_ALL_CURRENT = 1064,2,1,0 %; ! Flush all read_current lines, then reset macro IOC$V_PR_PLUNGE = 1064,3,1,0 %; ! Kinky macro IOC$V_FIP_SNAP = 1064,4,1,0 %; ! Snapshot macro IOC$q_cache_fip_snap = 1112,0,0,0 %; literal IOC$s_cache_fip_snap = 8; ! 458 Fetch-In-Progress Mask macro IOC$Q_LBA_PORT8_CNTRL = 2640,0,0,0 %; literal IOC$S_LBA_PORT8_CNTRL = 8; ! A50 LBA 8 Port Control macro IOC$Q_LBA_PORT9_CNTRL = 2648,0,0,0 %; literal IOC$S_LBA_PORT9_CNTRL = 8; ! A58 LBA 9 Port Control macro IOC$Q_LBA_PORT10_CNTRL = 2656,0,0,0 %; literal IOC$S_LBA_PORT10_CNTRL = 8; ! A60 LBA 10 Port Control macro IOC$Q_LBA_PORT11_CNTRL = 2664,0,0,0 %; literal IOC$S_LBA_PORT11_CNTRL = 8; ! A68 LBA 11 Port Control macro IOC$Q_LBA_PORT12_CNTRL = 2672,0,0,0 %; literal IOC$S_LBA_PORT12_CNTRL = 8; ! A70 LBA 12 Port Control macro IOC$Q_LBA_PORT13_CNTRL = 2680,0,0,0 %; literal IOC$S_LBA_PORT13_CNTRL = 8; ! A78 LBA 13 Port Control macro IOC$Q_LBA_PORT14_CNTRL = 2688,0,0,0 %; literal IOC$S_LBA_PORT14_CNTRL = 8; ! A80 LBA 14 Port Control macro IOC$Q_LBA_PORT15_CNTRL = 2696,0,0,0 %; literal IOC$S_LBA_PORT15_CNTRL = 8; ! A88 LBA 15 Port Control literal SPPA$S_SPPA_IOC_MAP_LENGTH = 4096; literal SPPA$M_ENABLE_ARB = %X'1'; literal SPPA$M_MASK_A = %X'2'; literal SPPA$M_MASK_B = %X'4'; literal SPPA$M_MASK_C = %X'8'; literal SPPA$M_MASK_D = %X'10'; literal SPPA$M_MASK_E = %X'20'; literal SPPA$M_MASK_F = %X'40'; literal SPPA$M_MASK_G = %X'80'; literal SPPA$M_RE = %X'1'; literal SPPA$M_ERR_CONFIG_CM = %X'10'; literal SPPA$M_ERR_CONFIG_S = %X'20'; literal SPPA$M_ERR_CONFIG_FS = %X'40'; literal SPPA$M_ERR_CONFIG_CT = %X'400'; literal SPPA$M_ERR_CONFIG_IM = %X'800'; literal SPPA$M_ERR_CONFIG_IT = %X'1000'; literal SPPA$S_SPPA_LBA_MAP = 4096; macro SPPA$R_LBA_HDR = 0,0,0,0 %; literal SPPA$S_LBA_HDR = 16; macro SPPA$Q_BUS_NUMBER = 88,0,0,0 %; literal SPPA$S_BUS_NUMBER = 8; ! 058 LBA Bus Number Range macro SPPA$B_LOWEST = 88,0,8,0 %; ! Lowest bus number in LBA macro SPPA$B_HIGHEST = 89,0,8,0 %; ! HIghest bus number in LBA macro SPPA$Q_ARB_MASK = 128,0,0,0 %; literal SPPA$S_ARB_MASK = 8; ! 080 Arbitration Mask macro SPPA$V_ENABLE_ARB = 128,0,1,0 %; ! Disable all requests if 0 macro SPPA$V_MASK_A = 128,1,1,0 %; ! Enable arbitration on device A macro SPPA$V_MASK_B = 128,2,1,0 %; ! Enable arbitration on device B macro SPPA$V_MASK_C = 128,3,1,0 %; ! Enable arbitration on device C macro SPPA$V_MASK_D = 128,4,1,0 %; ! Enable arbitration on device D macro SPPA$V_MASK_E = 128,5,1,0 %; ! Enable arbitration on device E macro SPPA$V_MASK_F = 128,6,1,0 %; ! Enable arbitration on device F macro SPPA$V_MASK_G = 128,7,1,0 %; ! Enable arbitration on device G macro SPPA$R_LBA_MOD = 256,0,0,0 %; literal SPPA$S_LBA_MOD = 16; macro SPPA$Q_IBASE = 768,0,0,0 %; literal SPPA$S_IBASE = 8; ! 300 Base of IOV Space macro SPPA$V_RE = 768,0,1,0 %; ! Enable Mapping on Range macro SPPA$Q_IMASK = 776,0,0,0 %; literal SPPA$S_IMASK = 8; ! 308 Mask/Size of IOV Space macro SPPA$Q_ERR_CONFIG = 1664,0,0,0 %; literal SPPA$S_ERR_CONFIG = 8; ! 680 Define handling of various errors macro SPPA$V_ERR_CONFIG_IP_1 = 1664,0,4,0 %; literal SPPA$S_ERR_CONFIG_IP_1 = 4; ! Implementation dependent macro SPPA$V_ERR_CONFIG_CM = 1664,4,1,0 %; ! Config: master abort fatal if set macro SPPA$V_ERR_CONFIG_S = 1664,5,1,0 %; ! Smart bus if set macro SPPA$V_ERR_CONFIG_FS = 1664,6,1,0 %; ! SERR# fatal if set macro SPPA$V_ERR_CONFIG_IP_2 = 1664,7,3,0 %; literal SPPA$S_ERR_CONFIG_IP_2 = 3; ! Implementation dependent macro SPPA$V_ERR_CONFIG_CT = 1664,10,1,0 %; ! Config: target abort fatal if set macro SPPA$V_ERR_CONFIG_IM = 1664,11,1,0 %; ! I/O port: master abort fatal if set macro SPPA$V_ERR_CONFIG_IT = 1664,12,1,0 %; ! I/O port: target abort fatal if set macro SPPA$V_ERR_CONFIG_IP_3 = 1664,13,19,0 %; literal SPPA$S_ERR_CONFIG_IP_3 = 19; ! Implementation dependent macro SPPA$V_RESERVED_LBA_7 = 1668,0,32,0 %; literal SPPA$S_RESERVED_LBA_7 = 32; ! Reserved literal SPPA$S_SPPA_LBA_MAP_LENGTH = 4096; !*** MODULE $SPPBDEF *** ! + ! SPPB - SCA POLLER PROCESS BLOCK ! ! THIS DATA STRUCTURE DESCRIBES A PROCESS NAME KNOWN ! TO THE SCA DIRECTORY POLLER. ! - literal SPPB$K_LENGTH = 40; literal SPPB$C_LENGTH = 40; literal SPPB$S_SPPBDEF = 40; literal SPPB$S_SPPB = 40; macro SPPB$L_FLINK = 0,0,32,1 %; ! FWD LINK macro SPPB$L_BLINK = 4,0,32,1 %; ! BCK LINK macro SPPB$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro SPPB$B_TYPE = 10,0,8,0 %; ! SCS STRUCTURE TYPE macro SPPB$B_SUBTYP = 11,0,8,0 %; ! SCS STRUCTURE SUBTYPE FOR SPPB macro SPPB$B_PROCNAM = 12,0,0,0 %; literal SPPB$S_PROCNAM = 16; ! ASCII STRING FOR PROCESS NAME macro SPPB$L_RTN = 28,0,32,1 %; ! ADDRESS OF NOTIFICATION ROUTINE macro SPPB$L_CTX = 32,0,32,0 %; ! CONTEXT FOR NOTIFICATION ROUTINE macro SPPB$W_BIT = 36,0,16,0 %; ! BIT ASSIGNED TO THIS PROCESS NAME !*** MODULE $SQEDEF *** ! + ! Serialisation Queue Element Definitions ! ! SQEs are put on the extent/FID cache serialisation queues within ! the XQP. ! ! - literal SQE$K_ACB = 16; ! OFFSET INTO ACB AREA literal SQE$C_ACB = 16; literal SQE$K_LENGTH = 44; ! LENGTH OF BLOCK literal SQE$C_LENGTH = 44; ! LENGTH OF BLOCK literal SQE$S_SQEDEF = 44; literal SQE$S_SQE = 44; macro SQE$L_SQEQFL = 0,0,32,1 %; ! SQE QUEUE FORWARD LINK macro SQE$L_SQEQBL = 4,0,32,1 %; ! SQE QUEUE BACKWARD LINK macro SQE$W_SQESIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro SQE$B_SQETYPE = 10,0,8,0 %; ! STRUCTURE TYPE CODE macro SQE$B_SQESUBTYPE = 11,0,8,0 %; ! STRUCTURE SUBTYPE CODE macro SQE$L_SQEPID = 12,0,32,0 %; ! PID OWNER OF SQE ! DONT ADD ANYTHING HERE - ACB IS QUAD ALIGNED macro SQE$L_ASTQFL = 16,0,32,1 %; ! AST QUEUE FORWARD LINK macro SQE$L_ASTQBL = 20,0,32,1 %; ! AST QUEUE BACKWARD LINK macro SQE$W_SIZE = 24,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro SQE$B_TYPE = 26,0,8,0 %; ! STRUCTURE TYPE CODE macro SQE$B_RMOD = 27,0,8,0 %; ! REQUEST ACCESS MODE macro SQE$L_PID = 28,0,32,0 %; ! PROCESS ID OF REQUEST macro SQE$L_AST = 32,0,32,1 %; ! AST ROUTINE ADDRESS macro SQE$L_ASTPRM = 36,0,32,0 %; ! AST PARAMETER macro SQE$L_KAST = 40,0,32,0 %; ! INTERNAL KERNEL MODE XFER ADDRESS !*** MODULE $SRVBUFDEF *** ! + ! SRVBUF Definitions -- MSCP Server local buffer ! ! This module defines the fields used in the data structure ! that keeps track of the local buffer pool. This local pool ! is used for buffering data between the client host and the ! local disk driver. The size field is stored after the type ! and subtype fields so that it can be larger and still retain ! the type and subtype convention. ! - literal SRVBUF$S_SRVBUFDEF = 24; ! Old size name - synonym literal SRVBUF$S_SRVBUF = 24; macro SRVBUF$L_FLINK = 0,0,32,1 %; ! Field maintained for macro SRVBUF$L_BLINK = 4,0,32,1 %; ! compatability macro SRVBUF$W_DEBITS = 8,0,16,0 %; ! Number of requestors memory has been lent to macro SRVBUF$B_TYPE = 10,0,8,0 %; ! MSCP type structure macro SRVBUF$B_SUBTYPE = 11,0,8,0 %; ! with a SRVBUF subtype (4) macro SRVBUF$L_SIZE = 12,0,32,0 %; ! Total buffer area size macro SRVBUF$L_BUFF_START = 16,0,32,1 %; ! List head for buffer free list macro SRVBUF$L_FREE_SIZE = 20,0,32,0 %; ! Buffer size for free list !*** MODULE $SSCDEF *** ! ++ ! SSC definitions ! -- ! The BASE register is at physical address %X2014000. It is loaded with ! a value at which to locate all the other registers. All other registers ! are at @BASE+offset. literal SSC$AL_BASE = 538181632; ! Base address literal SSC$L_CONFIG = 16; ! Configuration literal SSC$L_TODR = 108; ! Time-of-year literal SSC$L_TCR0 = 256; ! Timer 0 control literal SSC$L_TIR0 = 260; ! Timer 0 interval literal SSC$L_TNIR0 = 264; ! Timer 0 next interval literal SSC$L_TIVR0 = 268; ! Timer 0 interrupt vector literal SSC$L_TCR1 = 272; ! Timer 1 control literal SSC$L_TIR1 = 276; ! Timer 1 interval literal SSC$L_TNIR1 = 264; ! Timer 1 next interval literal SSC$L_TIVR1 = 268; ! Timer 1 interrupt vector literal SSC$B_RAM_START = 1024; ! Start of SSC RAM literal SSC$B_RAM_END = 2047; ! End of SSC RAM literal SSC$M_TCR_RUN = %X'1'; literal SSC$M_TCR_STP = %X'4'; literal SSC$M_TCR_XFR = %X'10'; literal SSC$M_TCR_SGL = %X'20'; literal SSC$M_TCR_IE = %X'40'; literal SSC$M_TCR_INT = %X'80'; literal SSC$M_TCR_ERR = %X'80000000'; literal SSC$S_TCR = 4; macro SSC$V_TCR_RUN = 0,0,1,0 %; macro SSC$V_TCR_MBZ_0 = 0,1,1,0 %; macro SSC$V_TCR_STP = 0,2,1,0 %; macro SSC$V_TCR_MBZ_1 = 0,3,1,0 %; macro SSC$V_TCR_XFR = 0,4,1,0 %; macro SSC$V_TCR_SGL = 0,5,1,0 %; macro SSC$V_TCR_IE = 0,6,1,0 %; macro SSC$V_TCR_INT = 0,7,1,0 %; macro SSC$V_TCR_MBZ_2 = 0,8,23,0 %; literal SSC$S_TCR_MBZ_2 = 23; macro SSC$V_TCR_ERR = 0,31,1,0 %; !*** MODULE $SSCTDEF *** ! + ! This file contains offset definitions for SSC timer registers accessible ! through XMI private space on the XMI-based processors. ! - literal SSCT_TCR0$M_RUN = %X'1'; literal SSCT_TCR0$M_STP = %X'4'; literal SSCT_TCR0$M_XFR = %X'10'; literal SSCT_TCR0$M_SGL = %X'20'; literal SSCT_TCR0$M_IE = %X'40'; literal SSCT_TCR0$M_INT = %X'80'; literal SSCT_TCR0$M_ERR = %X'80000000'; literal SSCT_TIVR0$M_VECTOR = %X'3FC'; literal SSCT_TCR1$M_RUN = %X'1'; literal SSCT_TCR1$M_STP = %X'4'; literal SSCT_TCR1$M_XFR = %X'10'; literal SSCT_TCR1$M_SGL = %X'20'; literal SSCT_TCR1$M_IE = %X'40'; literal SSCT_TCR1$M_INT = %X'80'; literal SSCT_TCR1$M_ERR = %X'80000000'; literal SSCT_TIVR1$M_VECTOR = %X'3FC'; literal SSCT$S_SSCTDEF = 32; literal SSCT$S_SSCT = 32; macro SSCT$L_TCR0 = 0,0,32,0 %; macro SSCT_TCR0$V_RUN = 0,0,1,0 %; ! Enables timer macro SSCT_TCR0$V_STP = 0,2,1,0 %; ! Stop on overflow macro SSCT_TCR0$V_XFR = 0,4,1,0 %; ! 1=copy TNIRn to TIRn macro SSCT_TCR0$V_SGL = 0,5,1,0 %; ! Increment counter by one macro SSCT_TCR0$V_IE = 0,6,1,0 %; ! Interrupt Enable macro SSCT_TCR0$V_INT = 0,7,1,0 %; ! Set on timer overflow macro SSCT_TCR0$V_ERR = 0,31,1,0 %; ! Indicates missed overflow macro SSCT$L_TIR0 = 4,0,32,0 %; ! Timer Interval Register 0 macro SSCT$L_TNIR0 = 8,0,32,0 %; ! Timer Next Interval Reg. 0 macro SSCT$L_TIVR0 = 12,0,32,0 %; macro SSCT_TIVR0$V_VECTOR = 12,2,8,0 %; literal SSCT_TIVR0$S_VECTOR = 8; ! Longword aligned SCB vector macro SSCT$L_TCR1 = 16,0,32,0 %; macro SSCT_TCR1$V_RUN = 16,0,1,0 %; ! Enables timer macro SSCT_TCR1$V_STP = 16,2,1,0 %; ! Stop on overflow macro SSCT_TCR1$V_XFR = 16,4,1,0 %; ! 1=copy TNIRn to TIRn macro SSCT_TCR1$V_SGL = 16,5,1,0 %; ! Increment counter by one macro SSCT_TCR1$V_IE = 16,6,1,0 %; ! Interrupt Enable macro SSCT_TCR1$V_INT = 16,7,1,0 %; ! Set on timer overflow macro SSCT_TCR1$V_ERR = 16,31,1,0 %; ! Indicates missed overflow macro SSCT$L_TIR1 = 20,0,32,0 %; ! Timer Interval Register 1 macro SSCT$L_TNIR1 = 24,0,32,0 %; ! Timer Next Interval Reg. 1 macro SSCT$L_TIVR1 = 28,0,32,0 %; macro SSCT_TIVR1$V_VECTOR = 28,2,8,0 %; literal SSCT_TIVR1$S_VECTOR = 8; ! Longword aligned SCB vector !*** MODULE $SSIDEF *** ! ! System Service Intercept Control Block Definitions ! literal SSID$M_DOUBLE_MAP_FAILED = %X'1'; literal SSID$M_PROMOTE_COPIED = %X'2'; literal SSID$S_SSI_DATA = 8; ! Definitions for flags in ! CTL$GQ_SSI_DATA macro SSID$V_DOUBLE_MAP_FAILED = 0,0,1,0 %; ! Attempt to doublemap ! S2 promote area failed macro SSID$V_PROMOTE_COPIED = 0,1,1,0 %; ! Process has a private copy ! of the promote area literal SSI$M_CLOSEST = %X'1'; literal SSI$C_LENGTH = 28; ! Length of SSI_BLOCK literal SSI$S_SSI_BLOCK = 28; macro SSI$R_FLINK_OVERLAY = 0,0,32,0 %; macro SSI$PS_FLINK = 0,0,32,1 %; ! Forward link macro SSI$PS_PRE_NEXT = 0,0,32,1 %; ! Pointer to next pre-processing routine macro SSI$R_BLINK_OVERLAY = 4,0,32,0 %; macro SSI$PS_BLINK = 4,0,32,1 %; ! Backward link macro SSI$PS_POST_NEXT = 4,0,32,1 %; ! Pointer to next post-processing routine macro SSI$W_SIZE = 8,0,16,0 %; ! Size, in bytes macro SSI$B_TYPE = 10,0,8,0 %; ! Structure type code for SSI_BLOCK macro SSI$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype code macro SSI$L_VERSION = 12,0,32,0 %; ! Version number macro SSI$L_FLAGS = 16,0,32,0 %; ! Flags longword macro SSI$V_CLOSEST = 16,0,1,0 %; ! Closest to system service macro SSI$PS_PRE_ROUTINE = 20,0,32,1 %; ! Address of pre-processing routine macro SSI$PS_POST_ROUTINE = 24,0,32,1 %; ! Address of post-processing routine ! ! Definition for System Service Intercept Specific Service Control Block ! literal SSISP$M_NOT_AVAIL = %X'1'; literal SSISP$C_LENGTH = 48; ! Length of SSI_SPEC_BLOCK literal SSISP$S_SSI_SPEC_BLOCK = 48; macro SSISP$PS_PRE_NEXT = 0,0,32,1 %; ! Forward link macro SSISP$L_PRE_PROC_COUNT = 4,0,32,1 %; ! Number of SSIs on list macro SSISP$PS_POST_NEXT = 8,0,32,1 %; ! Forward link macro SSISP$L_POST_PROC_COUNT = 12,0,32,1 %; ! Number of SSIs on list macro SSISP$O_ORIGINAL_BUNDLE = 16,0,0,0 %; literal SSISP$S_ORIGINAL_BUNDLE = 16; ! On I64, orig. bundle contents ! before replacement macro SSISP$PQ_REPLACEMENT = 32,0,0,1 %; literal SSISP$S_REPLACEMENT = 8; ! On I64, code entry of ! replacement routine macro SSISP$L_FLAGS = 40,0,32,0 %; ! Service-specific flags longword macro SSISP$V_NOT_AVAIL = 40,0,1,0 %; ! Service may not be intercepted: ! e.g., SYS$SRCHANDLER, etc. ! ! Extensions to bound procedure descriptors for System Service Intercept ! literal SSI_PDSC$S_SSI_PDSC = 40; macro SSI_PDSC$q_fill_1 = 0,0,0,1 %; literal SSI_PDSC$s_fill_1 = 8; ! Quadword which contains flags macro SSI_PDSC$q_fill_2 = 8,0,0,1 %; literal SSI_PDSC$s_fill_2 = 8; ! Quadword which contains entry address macro SSI_PDSC$q_fill_3 = 16,0,0,1 %; literal SSI_PDSC$s_fill_3 = 8; ! Quadword which contains bound procedure value macro SSI_PDSC$Q_SS_SSADR = 24,0,0,1 %; literal SSI_PDSC$S_SS_SSADR = 8; ! Address of system service in system space macro SSI_PDSC$PS_SS_SSADR = 24,0,32,1 %; macro SSI_PDSC$Q_REPLACEMENT_ROUTINE = 32,0,0,1 %; literal SSI_PDSC$S_REPLACEMENT_ROUTINE = 8; ! Address of replacement routine macro SSI_PDSC$PS_REPLACEMENT_ROUTINE = 32,0,32,1 %; ! ! Function prototypes ! KEYWORDMACRO $SSI_GET_INTERCEPT_MAIN = BEGIN EXTERNAL ROUTINE SSI$GET_INTERCEPT_MAIN : BLISS ADDRESSING_MODE (GENERAL); SSI$GET_INTERCEPT_MAIN() END %; KEYWORDMACRO $SSI_DECLARE_INTERCEPT (SSI_BLOCK_PTR) = BEGIN EXTERNAL ROUTINE SSI$DECLARE_INTERCEPT : BLISS ADDRESSING_MODE (GENERAL); SSI$DECLARE_INTERCEPT (SDL$$SSIDEF_CONCAT( SDL$$SSIDEF_REQ(SSI_BLOCK_PTR, %QUOTE SSI_BLOCK_PTR) )) END %; KEYWORDMACRO $SSI_CANCEL_INTERCEPT (SSI_BLOCK_PTR) = BEGIN EXTERNAL ROUTINE SSI$CANCEL_INTERCEPT : BLISS ADDRESSING_MODE (GENERAL); SSI$CANCEL_INTERCEPT (SDL$$SSIDEF_CONCAT( SDL$$SSIDEF_REQ(SSI_BLOCK_PTR, %QUOTE SSI_BLOCK_PTR) )) END %; KEYWORDMACRO $SSI_DECLARE_REPLACEMENT (PS_SSADR,REPLACEMENT_ROUTINE) = BEGIN EXTERNAL ROUTINE SSI$DECLARE_REPLACEMENT : BLISS ADDRESSING_MODE (GENERAL); SSI$DECLARE_REPLACEMENT (SDL$$SSIDEF_CONCAT( SDL$$SSIDEF_REQ(PS_SSADR, %QUOTE PS_SSADR) , SDL$$SSIDEF_REQ(REPLACEMENT_ROUTINE, %QUOTE REPLACEMENT_ROUTINE) )) END %; KEYWORDMACRO $SSI_CANCEL_REPLACEMENT (PS_SSADR,REPLACEMENT_ROUTINE) = BEGIN EXTERNAL ROUTINE SSI$CANCEL_REPLACEMENT : BLISS ADDRESSING_MODE (GENERAL); SSI$CANCEL_REPLACEMENT (SDL$$SSIDEF_CONCAT( SDL$$SSIDEF_REQ(PS_SSADR, %QUOTE PS_SSADR) , SDL$$SSIDEF_REQ(REPLACEMENT_ROUTINE, %QUOTE REPLACEMENT_ROUTINE) )) END %; KEYWORDMACRO $SSI_DECLARE_SPEC_INTERCEPT (SSI_FD_PTR,SSI_BLOCK_PTR) = BEGIN EXTERNAL ROUTINE SSI$DECLARE_SPEC_INTERCEPT : BLISS ADDRESSING_MODE (GENERAL); SSI$DECLARE_SPEC_INTERCEPT (SDL$$SSIDEF_CONCAT( SDL$$SSIDEF_REQ(SSI_FD_PTR, %QUOTE SSI_FD_PTR) , SDL$$SSIDEF_REQ(SSI_BLOCK_PTR, %QUOTE SSI_BLOCK_PTR) )) END %; KEYWORDMACRO $SSI_CANCEL_SPEC_INTERCEPT (SSI_FD_PTR,SSI_BLOCK_PTR) = BEGIN EXTERNAL ROUTINE SSI$CANCEL_SPEC_INTERCEPT : BLISS ADDRESSING_MODE (GENERAL); SSI$CANCEL_SPEC_INTERCEPT (SDL$$SSIDEF_CONCAT( SDL$$SSIDEF_REQ(SSI_FD_PTR, %QUOTE SSI_FD_PTR) , SDL$$SSIDEF_REQ(SSI_BLOCK_PTR, %QUOTE SSI_BLOCK_PTR) )) END %; ! ! Define a constant to be placed in the SSI$L_VERSION field of the SSI block. ! SYS$SSISHR will verify that the contents of the SSI$L_VERSION field match ! the constant below. If for any reason a change in the SSI interface occurs ! (as it did because of the 64-Bit Project) the version number must change, as ! must the name of this constant. A change of the symbol name enables users ! of SSI to realize at compile-time that SSI has changed. If the value ! of the constant changed without an accompanying symbol name change, SSI ! cannot determine whether its callers are aware of an SSI interface change. ! literal SSI$C_VERSION_QUAD_LIST = 65536; literal SSI$K_VERSION_QUAD_LIST = 65536; !*** MODULE STATDEF *** literal STAT_M_INPOOL = %X'1'; literal STAT_M_NOIMGHDR = %X'2'; literal STAT_M_OPEN = %X'4'; literal STAT_M_NOLOAD_SA_APP = %X'8'; literal STAT_M_OPTIONAL_LOAD = %X'10'; literal STAT_M_INHIBIT_LOAD = %X'20'; literal STAT_C_SIZE = 16; ! Size of statistics block literal STAT_S_STATDEF = 16; literal STAT_S_STAT = 16; macro STAT_L_LENGTH = 0,0,32,0 %; ! Length of ASCII file name macro STAT_L_NAME = 4,0,32,1 %; ! Address of ASCII file name macro STAT_L_FLAGS = 8,0,32,0 %; ! Loading flags for INIT macro STAT_V_INPOOL = 8,0,1,0 %; macro STAT_V_NOIMGHDR = 8,1,1,0 %; macro STAT_V_OPEN = 8,2,1,0 %; macro STAT_V_NOLOAD_SA_APP = 8,3,1,0 %; ! Don't load image if SA_APP=1 macro STAT_V_OPTIONAL_LOAD = 8,4,1,0 %; ! Image may not be present macro STAT_V_INHIBIT_LOAD = 8,5,1,0 %; ! Don't load image if set macro STAT_L_LDR_FLAGS = 12,0,32,0 %; ! Flags passed to exec loader !*** MODULE $STATEDEF *** ! + ! SCHEDULING STATES ! - ! DEFINITIONS START AT 1 literal SCH$C_COLPG = 1; ! COLLIDED PAGE WAIT literal SCH$C_MWAIT = 2; ! MUTEX AND MISCELLANEOUS RESOURCE WAIT literal SCH$C_CEF = 3; ! COMMON EVENT FLAG WAIT STATE literal SCH$C_PFW = 4; ! PAGE FAULT WAIT literal SCH$C_LEF = 5; ! LOCAL EVENT FLAG WAIT literal SCH$C_LEFO = 6; ! LOCAL EVENT FLAG WAIT OUT OF BALANCE SET literal SCH$C_HIB = 7; ! HIBERNATE WAIT literal SCH$C_HIBO = 8; ! HIBERNATE WAIT OUT OF BALANCE SET literal SCH$C_SUSP = 9; ! SUSPENDED literal SCH$C_SUSPO = 10; ! SUSPENDED OUT OF THE BALANCE SET literal SCH$C_FPG = 11; ! FREEPAGE WAIT literal SCH$C_COM = 12; ! COMPUTE, IN BALANCE SET STATE literal SCH$C_COMO = 13; ! COMPUTE, OUT OF BALANCE SET STATE literal SCH$C_CUR = 14; ! CURRENT PROCESS STATE !*** MODULE $STDTDEF *** ! + ! STDT - SCSI Target Descriptor Table ! ! There is one STDT per target. The STDT contains the SCSI information ! for each SCSI target. STDT's are created during the configuration of ! the SCSI bus. ! ! This structure is read accessable to the class driver and readable and ! writeable by the PORT driver. ! ! ***NOTE1:**** New STDT fields must be entered at the end of the data structure. ! ! ***NOTE2:**** If an INCOMPATIBLE CHANGE is made to this structure bump ! the version number of this structure. ! - literal STDT$C_VERSION = 6; ! COMPATIBLE VERSION NUMBER. literal STDT$M_DFLG_RENEGOTIATE_SYNC = %X'1'; literal STDT$M_DFLG_CLASS_REQ_SDTR = %X'2'; literal STDT$M_DFLG_SUPPRESS_SDTR = %X'4'; literal STDT$K_SCDT_HASH_SIZE = 8; ! Size of SCDT_HASH_TABLE. literal STDT$K_SCDT_HASH_BITBASE = 0; ! Start bit of hash mask. literal STDT$K_SCDT_HASH_BITCNT = 3; ! Number of bits in hash mask. literal STDT$K_SCDT_HASH_BITMASK = 7; ! Bit mask for the hash value. literal STDT$M_CNF_PENDING = %X'1'; literal STDT$M_CLASS_UNITS_PAUSED = %X'2'; literal STDT$M_UNTESTED_PRLI = %X'4'; literal STDT$M_TARGET_RESET_IP = %X'8'; literal STDT$M_PRLO_IND_IP = %X'10'; literal STDT$M_KEEP_NO_LUNS = %X'20'; literal STDT$C_SPAREQ = 10; literal STDT$C_SPAREL = 20; literal STDT$C_SPAREW = 40; literal STDT$C_SPAREB = 80; literal STDT$C_LENGTH = 512; ! Length of STDT literal STDT$S_STDT = 512; macro STDT$PS_HASH_FLINK = 0,0,32,1 %; ! I STDT hash list forward link macro STDT$PS_HASH_BLINK = 4,0,32,1 %; ! I STDT hash list backward link macro STDT$W_SIZE = 8,0,16,0 %; ! I Standard pool header - data structure size. macro STDT$B_TYPE = 10,0,8,0 %; ! I Standard pool header - data structure type. macro STDT$B_SUBTYPE = 11,0,8,0 %; ! I Standard pool header - data structure subtype. ! ! Target Specific Information ! macro STDT$IS_TARGET_ID = 12,0,32,0 %; ! I ID (bit#) of this SCSI target. macro STDT$R_SCSI_ID_OVERLAY = 16,0,0,0 %; macro STDT$IS_SCSI_ID_NUM = 16,0,32,0 %; ! I ID (number) of this SCSI target. macro STDT$Q_SCSI_ID_NUM = 16,0,0,0 %; literal STDT$S_SCSI_ID_NUM = 8; ! I ID (number) of SCSI target for wide devices. ! I ! I macro STDT$IS_REQACK_OFFSET = 24,0,32,0 %; ! S reqack offset for sync IO macro STDT$IS_TRANSFER_PERIOD = 28,0,32,0 %; ! S m*4 nanoseconds macro STDT$IS_XFERPD_DATA = 32,0,32,0 %; ! S Port transfer period data macro STDT$IS_FAST_DATA = 36,0,32,0 %; ! S Port fast SCSI data (port specific) macro STDT$IS_WIDE = 40,0,32,0 %; ! S Flag set enables WIDE data transfer mode. macro STDT$IS_BUS_WIDTH = 44,0,32,0 %; ! S Width of WIDE bus (8, 16, 32). macro STDT$IS_DIPL_FLAGS = 48,0,32,0 %; ! S Flags manipulated at DIPL. macro STDT$V_DFLG_RENEGOTIATE_SYNC = 48,0,1,0 %; ! Re-negotiate asynchronous/synchronous operation. macro STDT$V_DFLG_CLASS_REQ_SDTR = 48,1,1,0 %; ! Class driver has requested SDTR. macro STDT$V_DFLG_SUPPRESS_SDTR = 48,2,1,0 %; ! Class driver is suppressing SDTR. macro STDT$IS_REQUESTED_REQACK_OFFSET = 52,0,32,0 %; ! S ack offset requested by class driver for sync IO macro STDT$IS_REQUESTED_XFER_PERIOD = 56,0,32,0 %; ! S transfer period requested by class driver for synch IO ! ! Performance and sanity counters ! macro STDT$IS_SCDT_COUNT = 60,0,32,0 %; ! F Count of SCDTs associated with this STDT. macro STDT$IS_DEV_IO_COUNT = 64,0,32,0 %; ! F Outstanding device queue I/O count for the target macro STDT$IS_PORT_IO_COUNT = 68,0,32,0 %; ! F Outstanding port queue I/O count for the target macro STDT$IS_TOTAL_IO_COUNT = 72,0,32,0 %; ! F Outstanding total I/O count for the target macro STDT$IS_RESET_CNT = 76,0,32,0 %; ! S Count of bus resets. ! ! Hash table for the SCDTs ! ! Number of bits in the hash value. ! Starting position of those bits. macro STDT$PS_SCDT_HASH_TABLE = 80,0,0,1 %; literal STDT$S_SCDT_HASH_TABLE = 32; ! F SCDT hash table. macro STDT$Q_IDENTITY = 112,0,0,1 %; literal STDT$S_IDENTITY = 8; ! F Identity quadword macro STDT$L_STATUS = 120,0,32,0 %; ! F Target/ID/FC-LA status macro STDT$L_HASH_INDEX = 124,0,32,0 %; ! F Hash index of this STDT's root STDT ! F in the SPDT's STDT hash table ! ! PGADRIVER needs more room in the STDT than the stock structure allowed. I've ! overlaid the port-specific extension which was already here with PGADRIVER ! specific data and created a symbol to define the number of long ! macro STDT$R_PORT_SPECIFIC_OVERLAY = 128,0,0,0 %; ! F Port specific space that may be used for any purpose. ! Save starting port-specific offset macro STDT$R_PGA_PORT_SPECIFIC = 128,0,0,0 %; literal STDT$S_PGA_PORT_SPECIFIC = 48; macro STDT$Q_SUSPENDED_TIME = 128,0,0,0 %; literal STDT$S_SUSPENDED_TIME = 8; ! F Low longword of time when suspended ! F High longword of time when suspended macro STDT$L_PRLI_STATUS = 136,0,32,1 %; ! F PRLI status of this FC-LA macro STDT$L_PRLI_RETRIES = 140,0,32,1 %; ! F PRLI retries left macro STDT$PS_PRLI_RSP_MBD = 144,0,32,1 %; ! F Pointer to PRLI response MBD macro STDT$PS_PRLI_FCCD = 148,0,32,1 %; ! F Pointer to PRLI FCCD macro STDT$L_SUSPENSIONS = 152,0,32,1 %; ! F Number of reasons to stay suspended macro STDT$L_SUSPENDED_COMMANDS = 156,0,32,1 %; ! F Number of suspensions due to command status macro STDT$L_TARGET_RESETS = 160,0,32,1 %; ! F Number of Target Resets issued macro STDT$PS_QUEUE_FULL_TQE = 164,0,32,1 %; ! F Pointer to TQE used for QUEUE FULL recovery macro STDT$L_FLAGS = 168,0,32,1 %; macro STDT$V_CNF_PENDING = 168,0,1,0 %; ! F Boolean: pending an ELS confirmation? macro STDT$V_CLASS_UNITS_PAUSED = 168,1,1,0 %; ! F Boolean: class driver units paused? macro STDT$V_UNTESTED_PRLI = 168,2,1,0 %; ! F Boolean: PRLI issued but untested? macro STDT$V_TARGET_RESET_IP = 168,3,1,0 %; ! F Boolean: Target Reset in progress? macro STDT$V_PRLO_IND_IP = 168,4,1,0 %; ! F Boolean: PRLO Indication in progress? macro STDT$V_KEEP_NO_LUNS = 168,5,1,0 %; ! F Boolean: Keep even if LUN count goes to 0 ! Save ending port-specific offset macro STDT$R_PORT_SPECIFIC_ARRAYS = 128,0,0,0 %; literal STDT$S_PORT_SPECIFIC_ARRAYS = 48; ! Bliss complains about the duplicate definitions of size symbols for ! each of the following arrays. Until I can figure out how to work ! around that we'll get by with the one symbol which is actually ! referenced in checked-in code. There's no way that I know of to ! get SDL to skip some of it's input stream for specific languages, ! ("iflanguage" doesn't seem to work within an aggregate) ! PORT_SPECIFIC byte dimension #PORT_SPECIFIC_BYTES; ! PORT_SPECIFIC word dimension #PORT_SPECIFIC_WORDS; macro STDT$IS_PORT_SPECIFIC = 128,0,0,1 %; literal STDT$S_PORT_SPECIFIC = 48; ! PORT_SPECIFIC longword dimension #PORT_SPECIFIC_LONGS; ! PORT_SPECIFIC quadword dimension #PORT_SPECIFIC_QUADS; ! F End of port specific space that may be used for any purpose ! ! The following fields are reserved to Digital OpenVMS/Alpha development. ! They are not normally used in released code, so are available for test ! and debug code - however, the developer assumes responsibility for ! ensuring that the fields are available to the port driver being worked ! on at the time of use ! macro STDT$IS_RSVD_LONG = 176,0,0,1 %; literal STDT$S_RSVD_LONG = 20; ! F Port-independent symbols ! These fields are newly defined in Ruby (V7.3-1). Since we don't have ! the option of forcing 3rd-party class driver recompiles in a dash ! release, they are being added to the tail of the structure; it would ! be a good idea to move them to before the port-specific overlays in ! the next dot release macro STDT$PS_SPDT = 196,0,32,1 %; ! F Pointer to this STDT's SPDT macro STDT$PS_FIRST_SCDT = 200,0,32,1 %; ! F First SCDT on which to to try to start I/O macro STDT$PS_STDT_LINK = 204,0,32,1 %; ! F Link to next STDT connected to same SPDT ! Note that the following fields are not marked with "F" to indicate that they are ! synchronized with the fork spinlock - this is because they are synchronized with ! the credit semaphore independent of spinlock context; however, there is an implicit ! assumption that the credit semaphore is acquired & released at fork IPL macro STDT$PS_CREDIT_WQFL = 208,0,32,1 %; ! First SCDRP on credit wait queue macro STDT$PS_CREDIT_WQBL = 212,0,32,1 %; ! Last SCDRP on credit wait queue macro STDT$Q_CREDIT_IO_COUNT = 216,0,0,1 %; literal STDT$S_CREDIT_IO_COUNT = 8; ! Number of SCDRPs on credit wait queue macro STDT$Q_DRAIN_TO_DIVISOR = 224,0,0,1 %; literal STDT$S_DRAIN_TO_DIVISOR = 8; ! Divisor used to calculate the number of ! active requests to drain to after seeing ! a new Queue Full macro STDT$Q_CREDIT_LOCK = 232,0,0,0 %; literal STDT$S_CREDIT_LOCK = 8; ! Queue Full field semaphore macro STDT$Q_LOW_DEPTH_RECOVERY = 240,0,0,1 %; literal STDT$S_LOW_DEPTH_RECOVERY = 8; ! Number of active requests below which the ! driver will perform a time, rather than load, ! based Queue Full recovery macro STDT$Q_LOCK_CPU = 248,0,0,0 %; literal STDT$S_LOCK_CPU = 8; ! CPU which currently owns semaphore macro STDT$Q_PROBATION = 256,0,0,1 %; literal STDT$S_PROBATION = 8; ! Boolean telling whether or not the active ! queue depth is currently being tested with a ! probationary I/O macro STDT$Q_CREDIT_LIMIT = 264,0,0,1 %; literal STDT$S_CREDIT_LIMIT = 8; ! Maximum number of I/Os which will be issued ! without waiting for a request to complete macro STDT$Q_CREDIT_AVAILABLE = 272,0,0,1 %; literal STDT$S_CREDIT_AVAILABLE = 8; ! Number of credits currently available macro STDT$Q_QUEUE_FULLS = 280,0,0,1 %; literal STDT$S_QUEUE_FULLS = 8; ! New (non-latent) Queue Fulls seen on this target macro STDT$R_SEQUENCE_OVERLAY = 288,0,0,0 %; ! F Target-specific sequence used to order requests on retry macro STDT$L_SEQUENCE = 288,0,32,0 %; ! F Longword (but quadword aligned) sequence (treat as read-only) macro STDT$Q_SEQUENCE = 288,0,0,0 %; literal STDT$S_SEQUENCE = 8; ! F Quadword sequence, always the one which is incremented ! F End overlay macro STDT$Q_FP_DEV_IO_COUNT = 296,0,0,1 %; literal STDT$S_FP_DEV_IO_COUNT = 8; ! P Number of FastPath requests active on the target macro STDT$Q_FP_CREDITS = 304,0,0,1 %; literal STDT$S_FP_CREDITS = 8; ! P Number of credits to be freed by the FastPath fork thread macro STDT$PS_FP_CREDIT_FKB = 312,0,32,1 %; ! F Pointer to FKB used by successful FastPath requests to free credits macro STDT$L_ILLEGAL_FRAMES = 316,0,32,1 %; ! F Illegal Frame error counter macro STDT$L_SEQUENCE_TIMEOUTS = 320,0,32,1 %; ! F Sequence Timeout counter macro STDT$L_PAUSE_FC_LA = 324,0,32,0 %; ! F Incremented on all calls to pga$pause_fc_la and decremented in ! F in pga$resume_fc_la if it is nonzero. If pga$resume_fc_la see ! F that it is non-zero, it decrements it and resumes the stdt. ! Port WWID (X-19) macro STDT$Q_PORT_WWID = 328,0,0,0 %; literal STDT$S_PORT_WWID = 8; ! Node WWID (X-19) macro STDT$Q_NODE_WWID = 336,0,0,0 %; literal STDT$S_NODE_WWID = 8; ! Pointer to initialization WWID_TID (X-19) macro STDT$PS_INITIAL_WWID_TID = 344,0,32,1 %; ! Pointer to associated WWID_TID (X-19) macro STDT$PS_WWID_TID = 348,0,32,1 %; ! Pointer to the next STDT associated with this STDT's WTID (X-19) macro STDT$PS_NEXT_WTID_STDT = 352,0,32,1 %; ! Number of STDT/WTID configuration failures (X-19) macro STDT$Q_WTID_STAT_FAIL_CNT = 356,0,0,0 %; literal STDT$S_WTID_STAT_FAIL_CNT = 8; ! Last STDT/WTID configuration failure status code (X-19) macro STDT$Q_LAST_WTID_STAT = 364,0,0,0 %; literal STDT$S_LAST_WTID_STAT = 8; ! Number of times a NULL WTID was detected during IO processing (X-19) macro STDT$Q_WTID_NULL_CNT = 372,0,0,0 %; literal STDT$S_WTID_NULL_CNT = 8; ! WWID_TID allocation failure counter (X-19) macro STDT$Q_WTID_ALLOC_FAIL = 380,0,0,1 %; literal STDT$S_WTID_ALLOC_FAIL = 8; ! Pointer to Inquiry Server KPB - FibreChannel only (X-20) macro STDT$PS_INQUIRY_KPB = 388,0,32,1 %; ! Normal Path IO approved but not yet in-flight (X-20) macro STDT$Q_IO_APPROVED = 392,0,0,1 %; literal STDT$S_IO_APPROVED = 8; ! Fast Path IO approved but not yet in-flight (X-20) macro STDT$Q_FP_IO_APPROVED = 400,0,0,1 %; literal STDT$S_FP_IO_APPROVED = 8; ! Initial sequence timeout timestamp (X-20) macro STDT$Q_INIT_SEQ_TIMEOUT_TIME = 408,0,0,1 %; literal STDT$S_INIT_SEQ_TIMEOUT_TIME = 8; ! Last sequence timeout timestamp (X-20) macro STDT$Q_LAST_SEQ_TIMEOUT_TIME = 416,0,0,1 %; literal STDT$S_LAST_SEQ_TIMEOUT_TIME = 8; ! Sequence timeouts in the monitored sequence timeout window (X-20) macro STDT$L_SEQ_TIMEOUTS_IN_WINDOW = 424,0,32,1 %; ! Spares fields for future growth (X-20/X-21) ! Number of spare quadwords macro STDT$R_RSVD1 = 432,0,0,0 %; literal STDT$S_RSVD1 = 80; macro STDT$Q_SPAREQ = 432,0,0,0 %; literal STDT$S_SPAREQ = 80; macro STDT$L_SPAREL = 432,0,0,0 %; literal STDT$S_SPAREL = 80; macro STDT$W_SPAREW = 432,0,0,0 %; literal STDT$S_SPAREW = 80; macro STDT$B_SPAREB = 432,0,0,0 %; literal STDT$S_SPAREB = 80; ! ! Define the length of this structure. ! !*** MODULE $SYSAPDEF *** ! + ! SYSAP - FLAGS USED IN THE SYSAP-SCS INTERFACE ! - ! OPTIONS FOR DISPOSING OF ! SENT DATAGRAM: ! 0 ORIGIN, INCR OF 1: literal SYSAP$C_DISPQ = 0; ! DISPOSE ON DG FREE QUEUE literal SYSAP$C_DISPRET = 1; ! DISPOSE BY RETURN TO SYSAP literal SYSAP$C_DISPPO = 2; ! DISPOSE BY RETURN TO POOL ! FLAGS SPECIFYING TYPE OF DG ! REC'D FROM REMOTE SYSAP: ! 0 ORIGIN, INCR OF 1: literal SYSAP$C_DGREC = 0; ! DG REC'D FROM REMOTE literal SYSAP$C_DGSNT = 1; ! DG SENT !*** MODULE $SYSGDEF *** literal SYSG$M_UCB_CONFIG_CONS = %X'1'; literal SYSG$M_UCB_CONFIG_PPORT = %X'2'; literal SYSG$M_UCB_CONFIG_KBIO = %X'4'; literal SYSG$M_WORKSTATION_PRESENT = %X'1'; literal SYSG$M_WIND_SYS_ACTIVE = %X'2'; literal SYSG$M_ALT_CONSOLE = %X'4'; literal SYSG$M_WIND_SYS_CONSOLE = %X'8'; literal SYSG$M_UNIT0_TX = %X'1'; literal SYSG$M_UNIT0_RX = %X'2'; literal SYSG$M_UNIT1_TX = %X'4'; literal SYSG$M_UNIT1_RX = %X'8'; literal SYSG$M_UNIT2_TX = %X'10'; literal SYSG$M_UNIT2_RX = %X'20'; literal SYSG$M_UNIT3_TX = %X'40'; literal SYSG$M_UNIT3_RX = %X'80'; literal SYSG$M_UNIT4_TX = %X'100'; literal SYSG$M_UNIT4_RX = %X'200'; literal SYSG$M_IPF_CONSOLE_POLLED = %X'1'; literal SYSG$M_IPF_CON_POLLED_INPUT = %X'2'; literal SYSG$M_IPF_CON_POLLED_OUTPUT = %X'4'; literal SYSG$M_IPF_SETCHAR_SUPPORTED = %X'8'; literal SYSG$M_IPF_INTERRUPTS_ALLOWED = %X'10'; literal SYSG$M_IPF_VGA_CONSOLE = %X'20'; literal SYSG$S_SYSG = 240; macro SYSG$IQ_KB_UCB = 0,0,0,0 %; literal SYSG$S_KB_UCB = 8; ! Address of UCB for the workstation KB macro SYSG$IL_KB_UCB_L = 0,0,32,1 %; macro SYSG$IL_KB_UCB_H = 4,0,32,0 %; macro SYSG$IQ_MOUSE_UCB = 8,0,0,0 %; literal SYSG$S_MOUSE_UCB = 8; ! Address of UCB for the workstation mouse macro SYSG$IL_MOUSE_UCB_L = 8,0,32,1 %; macro SYSG$IL_MOUSE_UCB_H = 12,0,32,0 %; macro SYSG$IL_SYSG_SIZE = 16,0,32,0 %; ! Length of structure. macro SYSG$IL_SPARE1 = 20,0,32,0 %; ! Spare use macro SYSG$PQ_CTB_PTR = 24,0,0,1 %; literal SYSG$S_CTB_PTR = 8; ! Console Terminal Block pointer. macro SYSG$PL_CTB_PTR_L = 24,0,32,1 %; macro SYSG$IL_CTB_PTR_H = 28,0,32,0 %; macro SYSG$IL_UCB_CONFIG = 32,0,32,0 %; ! Tells autoconfig which opa lines should be configured macro SYSG$V_UCB_CONFIG_CONS = 32,0,1,0 %; ! OPA0 (always configured) macro SYSG$V_UCB_CONFIG_PPORT = 32,1,1,0 %; ! Printer port (unit 1) macro SYSG$V_UCB_CONFIG_KBIO = 32,2,1,0 %; ! KB I/O for windows (unit 2) macro SYSG$IL_FLAGS = 36,0,32,0 %; ! Flags for the window system macro SYSG$V_WORKSTATION_PRESENT = 36,0,1,0 %; ! System is a workstation ! macro SYSG$V_WIND_SYS_ACTIVE = 36,1,1,0 %; ! Windowing system has been activated ! (Bit set by server) macro SYSG$V_ALT_CONSOLE = 36,2,1,0 %; ! alternate console in use. macro SYSG$V_WIND_SYS_CONSOLE = 36,3,1,0 %; ! Use windowing system console ! (Bit set by server) macro SYSG$IQ_OPWIN_UPDOWN_PD = 40,0,0,0 %; literal SYSG$S_OPWIN_UPDOWN_PD = 8; ! Console Visibility Toggle macro SYSG$IQ_OPWIN_UP_PD = 40,0,0,0 %; literal SYSG$S_OPWIN_UP_PD = 8; macro SYSG$IL_OPWIN_UP_PD_L = 40,0,32,0 %; macro SYSG$IL_OPWIN_UP_PD_H = 44,0,32,0 %; macro SYSG$IQ_OPWIN_RESIZE_PD = 48,0,0,0 %; literal SYSG$S_OPWIN_RESIZE_PD = 8; ! Console Window Resize macro SYSG$IQ_OPWIN_DOWN_PD = 48,0,0,0 %; literal SYSG$S_OPWIN_DOWN_PD = 8; macro SYSG$IL_OPWIN_DOWN_PD_L = 48,0,32,0 %; macro SYSG$IL_OPWIN_DOWN_PD_H = 52,0,32,0 %; macro SYSG$IQ_UNIT_INT = 56,0,0,0 %; literal SYSG$S_UNIT_INT = 8; ! Unit interrupt bits macro SYSG$V_UNIT0_TX = 56,0,1,0 %; macro SYSG$V_UNIT0_RX = 56,1,1,0 %; macro SYSG$V_UNIT1_TX = 56,2,1,0 %; macro SYSG$V_UNIT1_RX = 56,3,1,0 %; macro SYSG$V_UNIT2_TX = 56,4,1,0 %; macro SYSG$V_UNIT2_RX = 56,5,1,0 %; macro SYSG$V_UNIT3_TX = 56,6,1,0 %; macro SYSG$V_UNIT3_RX = 56,7,1,0 %; macro SYSG$V_UNIT4_TX = 56,8,1,0 %; macro SYSG$V_UNIT4_RX = 56,9,1,0 %; macro SYSG$IQ_OPWIN_RESET_PD = 64,0,0,0 %; literal SYSG$S_OPWIN_RESET_PD = 8; ! Reset console macro SYSG$IL_OPWIN_RESET_PD_L = 64,0,32,0 %; macro SYSG$IL_OPWIN_RESET_PD_H = 68,0,32,0 %; macro SYSG$IQ_OPWIN_PUTS_PD = 72,0,0,0 %; literal SYSG$S_OPWIN_PUTS_PD = 8; ! Put string to console macro SYSG$IL_OPWIN_PUTS_PD_L = 72,0,32,0 %; macro SYSG$IL_OPWIN_PUTS_PD_H = 76,0,32,0 %; macro SYSG$IQ_OPWIN_VISIBLE_PD = 80,0,0,0 %; literal SYSG$S_OPWIN_VISIBLE_PD = 8; ! Test visibility macro SYSG$IL_OPWIN_VISIBLE_PD_L = 80,0,32,0 %; macro SYSG$IL_OPWIN_VISIBLE_PD_H = 84,0,32,0 %; macro SYSG$IQ_OPWIN_HALT_PD = 88,0,0,0 %; literal SYSG$S_OPWIN_HALT_PD = 8; ! Handle HALT macro SYSG$IL_OPWIN_HALT_PD_L = 88,0,32,0 %; macro SYSG$IL_OPWIN_HALT_PD_H = 92,0,32,0 %; macro SYSG$IQ_OPWIN_CONTINUE_PD = 96,0,0,0 %; literal SYSG$S_OPWIN_CONTINUE_PD = 8; ! Handle CONTINUE macro SYSG$IL_OPWIN_COMTINUE_PD_L = 96,0,32,0 %; macro SYSG$IL_OPWIN_CONTINUE_PD_H = 100,0,32,0 %; macro SYSG$IQ_CONSOLE_LANGUAGE_PD = 104,0,0,0 %; literal SYSG$S_CONSOLE_LANGUAGE_PD = 8; ! Get console language macro SYSG$IL_CONSOLE_LANGUAGE_PD_L = 104,0,32,0 %; macro SYSG$IL_CONSOLE_LANGUAGE_PD_H = 108,0,32,0 %; macro SYSG$IQ_SPARE_1_PD = 112,0,0,0 %; literal SYSG$S_SPARE_1_PD = 8; ! Reserved macro SYSG$IQ_SPARE_2_PD = 120,0,0,0 %; literal SYSG$S_SPARE_2_PD = 8; ! Reserved macro SYSG$IQ_SPARE_3_PD = 128,0,0,0 %; literal SYSG$S_SPARE_3_PD = 8; ! Reserved macro SYSG$IQ_SPARE_4_PD = 136,0,0,0 %; literal SYSG$S_SPARE_4_PD = 8; ! Reserved macro SYSG$IQ_KBD_GETC_PD = 144,0,0,0 %; literal SYSG$S_KBD_GETC_PD = 8; macro SYSG$IL_KBD_GETC_PD_L = 144,0,32,1 %; macro SYSG$IL_KBD_GETC_PD_H = 148,0,32,0 %; macro SYSG$L_IPF_CONSOLE_flags = 152,0,32,0 %; macro SYSG$V_IPF_CONSOLE_POLLED = 152,0,1,0 %; ! Polled mode requested macro SYSG$V_IPF_CON_POLLED_INPUT = 152,1,1,0 %; ! Polled input supported macro SYSG$V_IPF_CON_POLLED_OUTPUT = 152,2,1,0 %; ! Polled output supported macro SYSG$V_IPF_SETCHAR_SUPPORTED = 152,3,1,0 %; ! Can change line characteristics macro SYSG$V_IPF_INTERRUPTS_ALLOWED = 152,4,1,0 %; ! System now capable of taking interrupts macro SYSG$V_IPF_VGA_CONSOLE = 152,5,1,0 %; ! Indicates VGA Console macro SYSG$IQ_IPF_CONIN_UCB = 156,0,0,0 %; literal SYSG$S_IPF_CONIN_UCB = 8; ! Address of UCB for the console input device macro SYSG$IL_IPF_CONIN_UCB_L = 156,0,32,1 %; macro SYSG$IL_IPF_CONIN_UCB_H = 160,0,32,0 %; macro SYSG$IQ_IPF_CONOUT_UCB = 164,0,0,0 %; literal SYSG$S_IPF_CONOUT_UCB = 8; ! Address of UCB for the console input device macro SYSG$IL_IPF_CONOUT_UCB_L = 164,0,32,1 %; macro SYSG$IL_IPF_CONOUT_UCB_H = 168,0,32,0 %; macro SYSG$IQ_IPF_SETCHAR_UCB = 172,0,0,0 %; literal SYSG$S_IPF_SETCHAR_UCB = 8; ! Address of UCB for the console device that supports characteristics changing macro SYSG$IL_IPF_SETCHAR_UCB_L = 172,0,32,1 %; macro SYSG$IL_IPF_SETCHAR_UCB_H = 176,0,32,0 %; macro SYSG$IQ_IPF_CON_INTIN = 180,0,0,0 %; literal SYSG$S_IPF_CON_INTIN = 8; ! routine. macro SYSG$IL_IPF_CON_INTIN_L = 180,0,32,1 %; macro SYSG$IL_IPF_CON_INTIN_H = 184,0,32,0 %; macro SYSG$IQ_IPF_CON_INTOUT = 188,0,0,0 %; literal SYSG$S_IPF_CON_INTOUT = 8; ! routine. macro SYSG$IL_IPF_CON_INTOUT_L = 188,0,32,1 %; macro SYSG$IL_IPF_CON_INTOUT_H = 192,0,32,0 %; macro SYSG$IQ_IPF_CON_GETCHAR = 196,0,0,0 %; literal SYSG$S_IPF_CON_GETCHAR = 8; ! characters from the console macro SYSG$IL_IPF_CON_GETCHAR_L = 196,0,32,1 %; macro SYSG$IL_IPF_CON_GETCHAR_H = 200,0,32,0 %; macro SYSG$IQ_IPF_CON_OUTCHAR = 204,0,0,0 %; literal SYSG$S_IPF_CON_OUTCHAR = 8; ! characters to the console macro SYSG$IL_IPF_CON_PUTCHAR_L = 204,0,32,1 %; macro SYSG$IL_IPF_CON_PUTCHAR_H = 208,0,32,0 %; macro SYSG$IQ_IPF_CON_SETCHAR = 212,0,0,0 %; literal SYSG$S_IPF_CON_SETCHAR = 8; ! change console line speed macro SYSG$IL_IPF_CON_SETCHAR_L = 212,0,32,1 %; ! consoles macro SYSG$IL_IPF_CON_SETCHAR_H = 216,0,32,0 %; macro SYSG$IQ_IPF_SET_INTIN_STATE = 220,0,0,0 %; literal SYSG$S_IPF_SET_INTIN_STATE = 8; ! change console input macro SYSG$IL_IPF_SET_INTIN_STATE_L = 220,0,32,1 %; macro SYSG$IL_IPF_SET_INTIN_STATE_H = 224,0,32,0 %; macro SYSG$IQ_IPF_SET_INTOUT_STATE = 228,0,0,0 %; literal SYSG$S_IPF_SET_INTOUT_STATE = 8; ! change console output macro SYSG$IL_IPF_SET_INTOUT_STATE_L = 228,0,32,1 %; macro SYSG$IL_IPF_SET_INTOUT_STATE_H = 232,0,32,0 %; literal SYSG$K_LENGTH = 240; ! Length literal SYSG$C_LENGTH = 240; ! Length (with a C!) literal S_SYSG$ = 240; ! Old size name - synonym !*** MODULE $SYSPARDEF *** literal ACP$S_DATACHK = 1; ! Old size name, synonym for ACP$S_SYS_DATACHK literal ACP$S_SYS_DATACHK = 1; ! Definition for ACP$GB_DATACHK macro ACP$V_READCHK = 0,0,1,0 %; ! do datachecks on reads macro ACP$V_WRITECHK = 0,1,1,0 %; ! do datachecks on writes literal ACP$S_SWAPFLAGS = 1; ! Old size name, synonym for ACP$S_SYS_SWAPFLAGS literal ACP$S_SYS_SWAPFLAGS = 1; ! Definition for ACP$GB_SWAPFLGS macro ACP$V_SWAPSYS = 0,0,1,0 %; ! /SYSTEM macro ACP$V_SWAPGRP = 0,1,1,0 %; ! /GROUP macro ACP$V_SWAPPRV = 0,2,1,0 %; ! other (private mount) macro ACP$V_SWAPMAG = 0,3,1,0 %; ! magtape literal CLU$S_SGN_FLAGS = 4; ! Old size name, synonym for CLU$S_SYS_SGN_FLAGS literal CLU$S_SYS_SGN_FLAGS = 4; ! Definition for CLU$GL_SGN_FLAGS macro CLU$V_NISCS_LOAD_PEA0 = 0,0,1,0 %; ! <0> Load PEA0 for NISCS macro CLU$V_NISCS_CONV_BOOT = 0,1,1,0 %; ! <1> Allow remote conversational boot macro CLU$V_NISCS_USE_LAN = 0,2,1,0 %; ! <2> Allow NISCS use of LAN macro CLU$V_NISCS_USE_UDP = 0,3,1,0 %; ! <3> Allow NISCS use of UDP literal EXE$M_FATAL_BUG = %X'100'; literal EXE$S_FLAGS = 4; ! Old size name, synonym for EXE$S_SYS_FLAGS literal EXE$S_SYS_FLAGS = 4; ! DEFINITION FOR EXE$GL_FLAGS macro EXE$V_SYSWRTABL = 0,0,1,0 %; ! LEAVE SYSTEM READ ONLY CODE WRITABLE macro EXE$V_NOAUTOCNF = 0,1,1,0 %; ! NO AUTOMATIC CONFIGURATION OF UBA macro EXE$V_POOLPGING = 0,2,1,0 %; ! ENABLE DYNAMIC POOL PAGING macro EXE$V_SIMULATOR = 0,3,1,0 %; ! RUNNING ON SIMULATOR macro EXE$V_CRDENABL = 0,4,1,0 %; ! ENABLE CRD ERROR DETECTION macro EXE$V_SBIERR = 0,5,1,0 %; ! ENABLE SBI ERROR INTERRUPT macro EXE$V_INIT = 0,6,1,0 %; ! RMS AND FILE SYSTEM INITIALIZED macro EXE$V_SETTIME = 0,7,1,0 %; ! FORCE SOLICITATION OF TIME macro EXE$V_FATAL_BUG = 0,8,1,0 %; ! FORCE ALL BUG CHECKS FATAL macro EXE$V_MULTACP = 0,9,1,0 %; ! USE MULTIPLE FILE ACP'S macro EXE$V_NOCLUSTER = 0,10,1,0 %; ! TURN OFF PAGE FAULT CLUSTERING macro EXE$V_BUGREBOOT = 0,11,1,0 %; ! AUTO REBOOT ON BUGCHECK macro EXE$V_SYSUAFALT = 0,12,1,0 %; ! ALTERNATE LOGICAL NAME FOR SYSUAF macro EXE$V_SHRF11ACP = 0,13,1,0 %; ! MAKE F11ACP SHARABLE AT BOOT TIME macro EXE$V_BUGDUMP = 0,14,1,0 %; ! TAKE SYSTEM DUMP ON BUGCHECK macro EXE$V_RESALLOC = 0,15,1,0 %; ! ENABLE RESOURCE ALLOCATION CHECKS macro EXE$V_CONCEALED = 0,16,1,0 %; ! ENABLE USE OF CONCEALED DEVICES macro EXE$V_SSINHIBIT = 0,17,1,0 %; ! INHIBIT SYSTEM SERVICES PER-PROCESS macro EXE$V_EXPLICITP = 0,18,1,0 %; ! IF SET TODAY IS CONSIDERED PRIMARY macro EXE$V_EXPLICITS = 0,19,1,0 %; ! IF SET TODAY IS CONSIDERED SECONDARY macro EXE$V_PGFLFRAG = 0,20,1,0 %; ! SET IF PAGE FILE FRAGMENTED MSG ISSUED macro EXE$V_PGFLCRIT = 0,21,1,0 %; ! SET IF PAGE FILE FULL MSG ISSUED macro EXE$V_TBCHK = 0,22,1,0 %; ! SET IF PROCESSOR REGISTER TBCHK PRESENT macro EXE$V_PAGFILDMP = 0,23,1,0 %; ! SET IF DUMP IS IN PAGE FILE macro EXE$V_SAVEDUMP = 0,24,1,0 %; ! SET TO SAVE DUMP UNTIL ANALYZED macro EXE$V_JOBQUEUES = 0,25,1,0 %; ! Set if JOBCTL to enable queues macro EXE$V_REINITQUE = 0,26,1,0 %; ! Set if JOBCTL to reinitialize JBCSYSQUE macro EXE$V_WLKSYSDSK = 0,27,1,0 %; ! Set if system disk is write locked macro EXE$V_POWEROFF = 0,28,1,0 %; ! Enable software power-off macro EXE$V_VIRTUAL_MACHINE = 0,29,1,0 %; ! Running on HPVM literal EXE$M_NOCLOCK = %X'1'; literal EXE$M_NOSMPSANITY = %X'2'; literal EXE$M_NOSPINWAIT = %X'4'; literal EXE$S_TIME_CONTROL = 4; ! Old size name, synonym for EXE$S_SYS_TIME_CONTROL literal EXE$S_SYS_TIME_CONTROL = 4; ! DEFINITION FOR EXE$GL_TIME_CONTROL macro EXE$V_NOCLOCK = 0,0,1,0 %; ! DO NOT TURN ON CLOCK macro EXE$V_NOSMPSANITY = 0,1,1,0 %; ! DISABLE SMP SANITY TIMER TIMEOUTS macro EXE$V_NOSPINWAIT = 0,2,1,0 %; ! DISABLE SMP SPIN/BUSYWAIT TIMEOUTS literal EXE$M_SYSSER_LOGGING = %X'80'; literal EXE$S_DYNAMIC_FLAGS = 4; ! Old size name, synonym for EXE$S_SYS_DYNAMIC_FLAGS literal EXE$S_SYS_DYNAMIC_FLAGS = 4; ! DEFINITION FOR EXE$GL_DYNAMIC_FLAGS macro EXE$V_CLASS_PROT = 0,0,1,0 %; ! Do non-discretionary classification check macro EXE$V_WRITESYSPARAMS = 0,1,1,0 %; ! Write the active parameters to the system .PAR file macro EXE$V_BRK_TERM = 0,2,1,0 %; ! Associate on terminal in breakin detection macro EXE$V_BRK_DISUSER = 0,3,1,0 %; ! Disable user account on breakin macro EXE$V_NOPGFLSWP = 0,4,1,0 %; ! Disallow swapping into page files macro EXE$V_LOAD_PWD_POLICY = 0,5,1,0 %; ! Load site-specific password change policy macro EXE$V_PERSISTENT_RES = 0,6,1,0 %; ! Enable Fibre SCSI Persistent reservations. macro EXE$V_SYSSER_LOGGING = 0,7,1,0 %; ! Enable system service logging literal EXE$M_SSI_ENABLE = %X'10'; literal EXE$S_STATIC_FLAGS = 4; ! Old size name, synonym for EXE$S_SYS_STATIC_FLAGS literal EXE$S_SYS_STATIC_FLAGS = 4; ! DEFINITION FOR EXE$GL_STATIC_FLAGS macro EXE$V_XQP_RESIDENT = 0,0,1,0 %; ! MEMORY RESIDENT XQP macro EXE$V_REBLDSYSD = 0,1,1,0 %; ! REBUILD SYSTEM DISK IN SYSMOUNT macro EXE$V_OBSSHAD = 0,2,1,0 %; ! Skip obsolete SHADOWING bit macro EXE$V_SA_APP = 0,3,1,0 %; ! Booting stand-alone application (SA-BACKUP) macro EXE$V_SSI_ENABLE = 0,4,1,0 %; ! Enable system service interception on I64 literal EXE$M_MOUNTMSG = %X'1'; literal EXE$M_DISMOUMSG = %X'2'; literal EXE$S_MSGFLAGS = 4; ! Old size name, synonym for EXE$S_SYS_MSGFLAGS literal EXE$S_SYS_MSGFLAGS = 4; ! DEFINITION FOR EXE$GL_MSGFLAGS macro EXE$V_MOUNTMSG = 0,0,1,0 %; ! ENABLE MOUNT NOTIFICATION macro EXE$V_DISMOUMSG = 0,1,1,0 %; ! ENABLE DISMOUNT NOTIFICATION literal EXE$S_WSFLAGS = 4; ! Old size name, synonym for EXE$S_SYS_WSFLAGS literal EXE$S_SYS_WSFLAGS = 4; ! DEFINITION FOR EXE$GL_WSFLAGS macro EXE$V_OPA0 = 0,0,1,0 %; ! Reserve a window for OPA0 literal SGN$S_LOADFLAGS = 4; ! Old size name, synonym for SGN$S_SYS_LOADFLAGS literal SGN$S_SYS_LOADFLAGS = 4; ! DEFINITION FOR SGN$GL_LOADFLAGS macro SGN$V_LOAD_SYS_IMAGES = 0,0,1,0 %; ! Alternate load system images macro SGN$V_EXEC_SLICING = 0,1,1,0 %; ! Slice system images macro SGN$V_RELEASE_PFNS = 0,2,1,0 %; ! Release PFNs in the huge page literal SGN$M_SDH = %X'1'; literal SGN$M_EVENT_MSG_MAJ = %X'2'; literal SGN$M_EVENT_MSG_ALL = %X'4'; literal SGN$M_UNI_V30 = %X'8'; literal SGN$M_UNI_V31 = %X'10'; literal SGN$M_DISABLE_GBE_AUTO = %X'20'; literal SGN$M_ENABLE_GBE_JUMBO = %X'40'; literal SGN$M_ENABLE_MORE_RCV = %X'80'; literal SGN$M_DISABLE_FLOW_CTL = %X'100'; literal SGN$M_RESERVED1 = %X'600'; literal SGN$M_DISABLE_ERRLOG = %X'800'; literal SGN$M_ENABLE_FAST_TIMER = %X'1000'; literal SGN$M_DEFAULT_XMT_ERROR = %X'2000'; literal SGN$M_PORT_USABLE_ALWAYS = %X'4000'; literal SGN$M_PORT_USABLE_UP = %X'8000'; literal SGN$M_RESERVED2 = %X'FF0000'; literal SGN$M_STOP_TRACE_FULL = %X'1000000'; literal SGN$M_ENABLE_ALT_FUNC2 = %X'2000000'; literal SGN$M_ENABLE_ALT_FUNC3 = %X'4000000'; literal SGN$M_DISABLE_MAP_REG = %X'8000000'; literal SGN$M_DISABLE_ALL_MSG = %X'10000000'; literal SGN$M_ENABLE_DEBUG_MODE = %X'20000000'; literal SGN$M_ENABLE_ALL_TRACE = %X'40000000'; literal SGN$M_ENABLE_ALL_MSG = %X'80000000'; literal SGN$S_LAN_FLAGS = 4; ! Old size name, synonym for SGN$S_SYS_LAN_FLAGS literal SGN$S_SGN_LAN_FLAGS = 4; ! Definition for SGN$GL_LAN_FLAGS macro SGN$V_SDH = 0,0,1,0 %; ! 00000001 0 ATM device is in SDH mode macro SGN$V_EVENT_MSG_MAJ = 0,1,1,0 %; ! 00000002 1 Enable a subset of the ATM/NIPG event messages macro SGN$V_EVENT_MSG_ALL = 0,2,1,0 %; ! 00000004 2 Enable all ATM/NIPG event messages macro SGN$V_UNI_V30 = 0,3,1,0 %; ! 00000008 3 Enable UNI version 3.0 macro SGN$V_UNI_V31 = 0,4,1,0 %; ! 00000010 4 Enable UNI version 3.1 (overrides 3.0) macro SGN$V_DISABLE_GBE_AUTO = 0,5,1,0 %; ! 00000020 5 Disable GBE autoconfiguration macro SGN$V_ENABLE_GBE_JUMBO = 0,6,1,0 %; ! 00000040 6 Enable GBE use of jumbo frames macro SGN$V_ENABLE_MORE_RCV = 0,7,1,0 %; ! 00000080 7 Enable more receive buffers macro SGN$V_DISABLE_FLOW_CTL = 0,8,1,0 %; ! 00000100 8 Disable flow control macro SGN$V_RESERVED1 = 0,9,2,0 %; literal SGN$S_RESERVED1 = 2; ! 00000600 9,10 Reserved FCLAN bits macro SGN$V_DISABLE_ERRLOG = 0,11,1,0 %; ! 00000800 11 Disable LAN error logging macro SGN$V_ENABLE_FAST_TIMER = 0,12,1,0 %; ! 00001000 12 Enable fast transmit timer macro SGN$V_DEFAULT_XMT_ERROR = 0,13,1,0 %; ! 00002000 13 Default to transmit error on aborted transmits macro SGN$V_PORT_USABLE_ALWAYS = 0,14,1,0 %; ! 00004000 14 Report port usable after enable_port macro SGN$V_PORT_USABLE_UP = 0,15,1,0 %; ! 00008000 15 Report port usable when link up macro SGN$V_RESERVED2 = 0,16,8,0 %; literal SGN$S_RESERVED2 = 8; ! 00FF0000 16..23 Unused bits macro SGN$V_STOP_TRACE_FULL = 0,24,1,0 %; ! 01000000 24 Stop tracing when buffer full macro SGN$V_ENABLE_ALT_FUNC2 = 0,25,1,0 %; ! 02000000 25 Enable alternate fucntionality #2 macro SGN$V_ENABLE_ALT_FUNC3 = 0,26,1,0 %; ! 04000000 26 Enable alternate fucntionality #3 macro SGN$V_DISABLE_MAP_REG = 0,27,1,0 %; ! 08000000 27 Disable use of map registers macro SGN$V_DISABLE_ALL_MSG = 0,28,1,0 %; ! 10000000 28 Disable all messages macro SGN$V_ENABLE_DEBUG_MODE = 0,29,1,0 %; ! 20000000 29 Enable debug mode macro SGN$V_ENABLE_ALL_TRACE = 0,30,1,0 %; ! 40000000 30 Enable all tracing macro SGN$V_ENABLE_ALL_MSG = 0,31,1,0 %; ! 80000000 31 Enable all messages ! ! values for sysgen parameter: SGN$GL_GALAXY ! literal GLX$C_NOJOIN = 0; literal GLX$C_JOIN_NOW = 1; literal GLX$C_JOIN_LATER = 2; literal EXE$M_CLASS_SCHED_ACTIVE = %X'1'; literal EXE$S_SYS_SCHED_FLAGS = 4; ! DEFINITION FOR EXE$GL_SCHED_FLAGS macro EXE$V_CLASS_SCHED_ACTIVE = 0,0,1,0 %; ! Class scheduling is active literal SGN$M_PKQ_FP_DISABLE = %X'1'; literal SGN$M_FGE_FP_DISABLE = %X'2'; literal SGN$M_PKA_FP_DISABLE = %X'4'; literal SGN$M_LAN_FP_DISABLE = %X'8'; literal SGN$M_PKR_FP_DISABLE = %X'10'; literal SGN$M_PKM_FP_DISABLE = %X'20'; literal SGN$M_PGQ_FP_DISABLE = %X'40'; literal SGN$M_DE_FP_DISABLE = %X'80'; literal SGN$S_FAST_PATH_PORTS = 4; ! Old size name, synonym for SGN$S_SYS_FAST_PATH_PORTS literal SGN$S_SGN_FAST_PATH_PORTS = 4; ! DEFINITION FOR SGN$GL_FAST_PATH_PORTS macro SGN$V_PKQ_FP_DISABLE = 0,0,1,0 %; ! Set = disable PKQ (QLogic) Fast Path macro SGN$V_FGE_FP_DISABLE = 0,1,1,0 %; ! Set = disable Emulex FiberChannel Fast Path macro SGN$V_PKA_FP_DISABLE = 0,2,1,0 %; ! Set = disable PKA Fast Path macro SGN$V_LAN_FP_DISABLE = 0,3,1,0 %; ! Set = disable LAN Fast Path macro SGN$V_PKR_FP_DISABLE = 0,4,1,0 %; ! Set = disable PKR Fast Path macro SGN$V_PKM_FP_DISABLE = 0,5,1,0 %; ! Set = disable PKM Fast Path macro SGN$V_PGQ_FP_DISABLE = 0,6,1,0 %; ! Set = disable PGQ (QLogic FC) Fast Path macro SGN$V_DE_FP_DISABLE = 0,7,1,0 %; ! X-33 Set = disable DE (iSCSI) Fast Path literal SGN$M_PAC_ENABLE = %X'1'; literal SGN$M_DEPTH_FIRST = %X'2'; literal SGN$M_MAX_UNITS = %X'C'; literal SGN$S_DEVICE_NAMING = 4; ! Old size name, synonym for SGN$S_DEVICE_NAMING literal SGN$S_SGN_DEVICE_NAMING = 4; ! DEFINITION FOR IOC$GL_NAMING macro SGN$V_PAC_ENABLE = 0,0,1,0 %; ! set to enable port allocation class naming scheme macro SGN$V_DEPTH_FIRST = 0,1,1,0 %; ! set to enable depth-first adapter enumeration scheme macro SGN$V_MAX_UNITS = 0,2,2,0 %; literal SGN$S_MAX_UNITS = 2; ! set to limit maximum device units to 9999 !*** MODULE $SWRPBDEF *** literal SWRPB_BOOT_FLAGS$M_CONV = %X'1'; literal SWRPB_BOOT_FLAGS$M_DEBUG = %X'2'; literal SWRPB_BOOT_FLAGS$M_INIBPT = %X'4'; literal SWRPB_BOOT_FLAGS$M_DIAG = %X'8'; literal SWRPB_BOOT_FLAGS$M_BOOBPT = %X'10'; literal SWRPB_BOOT_FLAGS$M_NOHEADER = %X'20'; literal SWRPB_BOOT_FLAGS$M_NOTEST = %X'40'; literal SWRPB_BOOT_FLAGS$M_SOLICIT = %X'80'; literal SWRPB_BOOT_FLAGS$M_HALT = %X'100'; literal SWRPB_BOOT_FLAGS$M_SHADOW = %X'200'; literal SWRPB_BOOT_FLAGS$M_ISL = %X'400'; literal SWRPB_BOOT_FLAGS$M_PALCHECK = %X'800'; literal SWRPB_BOOT_FLAGS$M_DEBUG_BOOT = %X'1000'; literal SWRPB_BOOT_FLAGS$M_CRDFAIL = %X'2000'; literal SWRPB_BOOT_FLAGS$M_ALIGN_FAULTS = %X'4000'; literal SWRPB_BOOT_FLAGS$M_REM_DEBUG = %X'8000'; literal SWRPB_BOOT_FLAGS$M_DBG_INIT = %X'10000'; literal SWRPB_BOOT_FLAGS$M_USER_MSGS = %X'20000'; literal SWRPB_BOOT_FLAGS$M_RSM = %X'40000'; literal SWRPB_BOOT_FLAGS$M_FOREIGN = %X'80000'; literal SWRPB_BOOT_FLAGS$M_QIOSERVER = %X'100000'; literal SWRPB_BOOT_FLAGS$M_MEMORY_DISK = %X'200000'; literal SWRPB_BOOT_FLAGS$M_HW_CONFIG = %X'400000'; literal SWRPB_BOOT_FLAGS$M_SIM_HINT = %X'800000'; literal SWRPB_BOOT_FLAGS$M_GRAPHIC_CONS = %X'1000000'; literal SWRPB_BOOT_FLAGS$M_ROOT = %X'FFFF0000'; literal SWRPB$M_LOAD_SCS = %X'1'; literal SWRPB$M_TAKENODMP = %X'2'; literal SWRPB$M_DUMP_DEV_OK = %X'4'; literal SWRPB$M_MCHECK = %X'8'; literal SWRPB$M_MEMTEST = %X'10'; literal SWRPB$M_SATELLITE_BOOT = %X'20'; literal SWRPB_LAVC_FLAGS$M_CONV_BOOT_OK = %X'1'; literal SWRPB$C_LENGTH = 180; ! Length of SWRPB literal SWRPB$K_LENGTH = 180; ! Length of SWRPB literal SWRPB$S_SWRPBDEF = 180; ! Old size name - synonym literal SWRPB$S_SWRPB = 180; macro SWRPB$PQ_IOVEC_FLINK = 0,0,0,1 %; literal SWRPB$S_IOVEC_FLINK = 8; ! IOVEC forward link macro SWRPB$PL_IOVEC_FLINK_L = 0,0,32,1 %; macro SWRPB$IL_IOVEC_FLINK_H = 4,0,32,0 %; macro SWRPB$PQ_IOVEC_BLINK = 8,0,0,1 %; literal SWRPB$S_IOVEC_BLINK = 8; ! IOVEC backward link macro SWRPB$PL_IOVEC_BLINK_L = 8,0,32,1 %; macro SWRPB$IL_IOVEC_BLINK_H = 12,0,32,0 %; macro SWRPB$IQ_BOOT_FLAGS = 16,0,0,0 %; literal SWRPB$S_BOOT_FLAGS = 8; ! System variation macro SWRPB$IL_BOOT_FLAGS_L = 16,0,32,0 %; macro SWRPB_BOOT_FLAGS$V_CONV = 16,0,1,0 %; ! Conversational bootstrap macro SWRPB_BOOT_FLAGS$V_DEBUG = 16,1,1,0 %; ! Map XDELTA to running system macro SWRPB_BOOT_FLAGS$V_INIBPT = 16,2,1,0 %; ! Stop at initial system BPT macro SWRPB_BOOT_FLAGS$V_DIAG = 16,3,1,0 %; ! Diagnostic bootstrap macro SWRPB_BOOT_FLAGS$V_BOOBPT = 16,4,1,0 %; ! Stop at bootstrap breakpoints macro SWRPB_BOOT_FLAGS$V_NOHEADER = 16,5,1,0 %; ! No header on 2nd bootstrap macro SWRPB_BOOT_FLAGS$V_NOTEST = 16,6,1,0 %; ! Inhibit memory test macro SWRPB_BOOT_FLAGS$V_SOLICIT = 16,7,1,0 %; ! Prompt for 2nd bootstrap file macro SWRPB_BOOT_FLAGS$V_HALT = 16,8,1,0 %; ! Halt before 2nd bootstrap macro SWRPB_BOOT_FLAGS$V_SHADOW = 16,9,1,0 %; ! Boot from shaddow set macro SWRPB_BOOT_FLAGS$V_ISL = 16,10,1,0 %; ! LAD/LAST bootstrap macro SWRPB_BOOT_FLAGS$V_PALCHECK = 16,11,1,0 %; ! Disable PAL rev check halt macro SWRPB_BOOT_FLAGS$V_DEBUG_BOOT = 16,12,1,0 %; ! Xfer to 2nd primary bootstrap macro SWRPB_BOOT_FLAGS$V_CRDFAIL = 16,13,1,0 %; ! Mark CRD pages bad macro SWRPB_BOOT_FLAGS$V_ALIGN_FAULTS = 16,14,1,0 %; ! Report bootstrap unaligned data traps macro SWRPB_BOOT_FLAGS$V_REM_DEBUG = 16,15,1,0 %; ! Allow remote high level lang sys debug macro SWRPB_BOOT_FLAGS$V_DBG_INIT = 16,16,1,0 %; ! Toggle verbose mode in EXEC_INIT macro SWRPB_BOOT_FLAGS$V_USER_MSGS = 16,17,1,0 %; ! user messages displayed (subset of verbose mode) macro SWRPB_BOOT_FLAGS$V_RSM = 16,18,1,0 %; ! Boot is controlled by Remote System Manager macro SWRPB_BOOT_FLAGS$V_FOREIGN = 16,19,1,0 %; ! Boot involves a foreign disk, either as system ! device or as installation target macro SWRPB_BOOT_FLAGS$V_QIOSERVER = 16,20,1,0 %; ! Boot device is QIOServer controlled macro SWRPB_BOOT_FLAGS$V_MEMORY_DISK = 16,21,1,0 %; ! Boot from memory disk macro SWRPB_BOOT_FLAGS$V_HW_CONFIG = 16,22,1,0 %; ! Dump and trace hw config during booting macro SWRPB_BOOT_FLAGS$V_SIM_HINT = 16,23,1,0 %; ! Enable simulator shortcuts macro SWRPB_BOOT_FLAGS$V_GRAPHIC_CONS = 16,24,1,0 %; ! Force Graphic console on IA64 systems with no PCDP support ! ! symbol names with the swrpb_boot_flags$m or swrpb_boot_flags$v prefix ! cannot exceed 31 characters total. ! macro SWRPB$IL_BOOT_FLAGS_H = 20,0,32,0 %; macro SWRPB_BOOT_FLAGS$V_ROOT = 20,16,16,0 %; literal SWRPB_BOOT_FLAGS$S_ROOT = 16; ! System root macro SWRPB$PQ_BTADP = 24,0,0,1 %; literal SWRPB$S_BTADP = 8; ! BOOT ADAPTER BLOCK macro SWRPB$PL_BTADP_L = 24,0,32,1 %; macro SWRPB$IL_BTADP_H = 28,0,32,0 %; macro SWRPB$PQ_BOOPARAM = 32,0,0,1 %; literal SWRPB$S_BOOPARAM = 8; ! EXEC_INIT Param block macro SWRPB$PL_BOOPARAM_L = 32,0,32,1 %; macro SWRPB$IL_BOOPARAM_H = 36,0,32,0 %; macro SWRPB$PQ_IOCHAN = 40,0,0,1 %; literal SWRPB$S_IOCHAN = 8; ! IOCHAN of boot driver macro SWRPB$PL_IOCHAN_L = 40,0,32,1 %; macro SWRPB$IL_IOCHAN_H = 44,0,32,0 %; macro SWRPB$IQ_BOOT_TIME = 48,0,0,0 %; literal SWRPB$S_BOOT_TIME = 8; ! Time that system was booted macro SWRPB$IL_BOOT_TIME_L = 48,0,32,0 %; macro SWRPB$IL_BOOT_TIME_H = 52,0,32,0 %; macro SWRPB$IQ_FLAGS = 56,0,0,0 %; literal SWRPB$S_FLAGS = 8; ! Other bootstrap flags macro SWRPB$IL_FLAGS_L = 56,0,32,0 %; macro SWRPB$V_LOAD_SCS = 56,0,1,0 %; ! Load SCS code macro SWRPB$V_TAKENODMP = 56,1,1,0 %; ! Do not take dump, master ! changed for shadowed system ! disk. Note: On VAX, ! TAKENODMP was added to RPB ! to pass to console reboot ! logic. macro SWRPB$V_DUMP_DEV_OK = 56,2,1,0 %; ! Take the dump device is ! under dump_dev E.V. control macro SWRPB$V_MCHECK = 56,3,1,0 %; ! Set when a hard memory error occurs. macro SWRPB$V_MEMTEST = 56,4,1,0 %; ! Set when memory testing is in progress macro SWRPB$V_SATELLITE_BOOT = 56,5,1,0 %; ! This is an IA64 satellite boot ! currently not set on Alpha macro SWRPB$IL_FLAGS_H = 60,0,32,0 %; macro SWRPB$PQ_PORT_CHAN = 64,0,0,1 %; literal SWRPB$S_PORT_CHAN = 8; ! PORT_CHAN of port boot driver macro SWRPB$PL_PORT_CHAN_L = 64,0,32,1 %; macro SWRPB$IL_PORT_CHAN_H = 68,0,32,0 %; macro SWRPB$IQ_SCB_SIZE = 72,0,0,0 %; literal SWRPB$S_SCB_SIZE = 8; ! Size of the runtime SCB macro SWRPB$IL_SCB_SIZE_L = 72,0,32,0 %; macro SWRPB$IL_SCB_SIZE_H = 76,0,32,0 %; ! The following fields are filled in by APB if a NISCA ! boot is being performed on a LAVc satellite. These ! fields are cluster specific fields. macro SWRPB$T_SCSNODE = 80,0,0,0 %; literal SWRPB$S_SCSNODE = 8; ! System's SCS node name. macro SWRPB$IQ_SCSSYSTEMID = 88,0,0,0 %; literal SWRPB$S_SCSSYSTEMID = 8; ! System's SCSSYSTEMID value. ! The following fields are filled in by APB if a NISCA ! boot is being performed on a LAVc satellite. macro SWRPB$IQ_LAVC_AUTH = 96,0,0,0 %; literal SWRPB$S_LAVC_AUTH = 8; ! LAVc authorization code. macro SWRPB$IL_LAVC_GROUP = 104,0,32,0 %; ! LAVc group number. macro SWRPB$IL_LAVC_PORT_SERVICES = 108,0,32,0 %; ! NISCA port services. macro SWRPB$IL_LAVC_FLAGS = 112,0,32,0 %; ! LAVc boot control flags. macro SWRPB_LAVC_FLAGS$V_CONV_BOOT_OK = 112,0,1,0 %; ! Allow converstational boot. ! End of fields used for LAVc satellite booting. ! Define the file system data. macro SWRPB$T_SYSROOT = 120,0,0,0 %; literal SWRPB$S_SYSROOT = 40; ! Root directory on the system disk. Counted string ! End of the file system data. macro SWRPB$PS_SVA_TO_PA = 160,0,32,1 %; ! Vector to routine converting SVA to PA ! ! These fields are filled in by IPB and are used by IPB, SYSBOOT to do ! console I/O ! macro SWRPB$PQ_CON_INPUT_CHAN = 164,0,0,1 %; literal SWRPB$S_CON_INPUT_CHAN = 8; ! Console terminals input channel macro SWRPB$PL_CON_INPUT_CHAN_L = 164,0,32,1 %; macro SWRPB$IL_CON_INPUT_CHAN_H = 168,0,32,0 %; macro SWRPB$PQ_CON_OUTPUT_CHAN = 172,0,0,1 %; literal SWRPB$S_CON_OUTPUT_CHAN = 8; ! Console terminals output channel macro SWRPB$PL_CON_OUTPUT_CHAN_L = 172,0,32,1 %; macro SWRPB$IL_CON_OUTPUT_CHAN_H = 176,0,32,0 %; !*** MODULE $T10DEF IDENT X-4 *** literal SCSI$C_OCRW = 15; literal SCSI$C_BE = 17; literal SCSI$C_OSD = 17; literal SCSI$C_ADI = 18; literal SCSI$C_WLU = 30; literal SCSI$C_MAXCDB = 16; literal SCSI$K_MAXCDB = 16; literal SCSI$S_SCSIDEF1 = 4; macro SCSI$L_SCSIDEF_SDL_PACIFIER = 0,0,32,0 %; literal DQ$K_DQ_OPCODE = 1; literal DQ$K_DQ_FLAGS = 0; literal DQ$M_DQ_READ = 1; literal DQ$S_DQCMD = 60; macro DQ$L_DQ_OPCODE = 0,0,32,0 %; macro DQ$L_DQ_FLAGS = 4,0,32,0 %; macro DQ$A_DQ_CMDADR = 8,0,32,0 %; macro DQ$L_DQ_CMDLEN = 12,0,32,0 %; macro DQ$A_DQ_DATADR = 16,0,32,0 %; macro DQ$L_DQ_DATLEN = 20,0,32,0 %; macro DQ$L_DQ_PADLEN = 24,0,32,0 %; macro DQ$L_DQ_PHASETMO = 28,0,32,0 %; macro DQ$L_DQ_DISCONTMO = 32,0,32,0 %; macro DQ$L_DQ_RES_1 = 36,0,32,0 %; macro DQ$L_DQ_RES_2 = 40,0,32,0 %; macro DQ$L_DQ_RES_3 = 44,0,32,0 %; macro DQ$L_DQ_RES_4 = 48,0,32,0 %; macro DQ$L_DQ_RES_5 = 52,0,32,0 %; macro DQ$L_DQ_RES_6 = 56,0,32,0 %; literal T10$S_TXC00 = 6; macro T10$B_TXC00_OPCODE = 0,0,8,0 %; macro T10$B_TXC00_CONTROL = 5,0,8,0 %; literal T10$S_TXC03 = 6; macro T10$B_TXC03_OPCODE = 0,0,8,0 %; macro T10$B_TXC03_LENGTH = 4,0,8,0 %; macro T10$B_TXC03_CONTROL = 5,0,8,0 %; literal T10$K_SKEY_NOSENS = 0; literal T10$K_SKEY_FIXERR = 1; literal T10$K_SKEY_NOTRDY = 2; literal T10$K_SKEY_MEDERR = 3; literal T10$K_SKEY_HDWERR = 4; literal T10$K_SKEY_ILLREQ = 5; literal T10$K_SKEY_UNITAT = 6; literal T10$K_SKEY_DATPRT = 7; literal T10$K_SKEY_BLKCHK = 8; literal T10$K_SKEY_VENDOR = 9; literal T10$K_SKEY_RSVD = 10; literal T10$K_SKEY_CMDABT = 11; literal T10$S_TXR03 = 18; macro T10$R_TXR03S_CODE = 0,0,8,0 %; literal T10$S_TXR03S_CODE = 1; macro T10$V_TXR03_CODE = 0,0,7,0 %; literal T10$S_TXR03_CODE = 7; macro T10$V_TXR03_VALID = 0,7,1,0 %; macro T10$R_TXR03S_SKEY = 2,0,8,0 %; literal T10$S_TXR03S_SKEY = 1; macro T10$V_TXR03_SKEY = 2,0,4,0 %; literal T10$S_TXR03_SKEY = 4; macro T10$V_TXR03_ILI = 2,5,1,0 %; macro T10$V_TXR03_EOM = 2,6,1,0 %; macro T10$V_TXR03_FILEMARK = 2,7,1,0 %; macro T10$L_TXR03_INFO = 3,0,32,0 %; macro T10$B_TXR03_ADDLEN = 7,0,8,0 %; macro T10$L_TXR03_CMDINFO = 8,0,32,0 %; macro T10$B_TXR03_ASC = 12,0,8,0 %; macro T10$B_TXR03_ASCQ = 13,0,8,0 %; macro T10$B_TXR03_FRU = 14,0,8,0 %; macro T10$B_TXR03_JUNQUE = 15,0,24,0 %; literal T10$S_TXR03_JUNQUE = 3; literal T10$K_TXC04_PLFMT_LEGACY = 7; literal T10$K_TXC04_PLFMT_CURRENT = 1; literal T10$S_TXC04 = 6; macro T10$B_TXC04_OPCODE = 0,0,8,0 %; macro T10$R_TXC04_FLAGS = 1,0,8,0 %; literal T10$S_TXC04_FLAGS = 1; macro T10$V_TXC04_FORMAT_CODE = 1,0,3,0 %; literal T10$S_TXC04_FORMAT_CODE = 3; macro T10$V_TXC04_CMPLST = 1,3,1,0 %; macro T10$V_TXC04_FMTDATA = 1,4,1,0 %; macro T10$W_TXC04_INTERLEAVE = 3,0,16,0 %; macro T10$B_TXC04_CONTROL = 5,0,8,0 %; literal T10$K_TXP04_FIXED = 4; literal T10$S_TXP04 = 4; macro T10$R_TXP04_FLAGS = 1,0,8,0 %; literal T10$S_TXP04_FLAGS = 1; macro T10$V_TXP04_VS = 1,0,1,0 %; macro T10$V_TXP04_IMMED = 1,1,1,0 %; macro T10$V_TXP04_TRYOUT = 1,2,1,0 %; macro T10$V_TXP04_IP = 1,3,1,0 %; macro T10$V_TXP04_STPF = 1,4,1,0 %; macro T10$V_TXP04_DCRT = 1,5,1,0 %; macro T10$V_TXP04_DPRY = 1,6,1,0 %; macro T10$V_TXP04_FOV = 1,7,1,0 %; macro T10$W_TXP04_LENGTH = 2,0,16,0 %; literal T10$K_TXP04IP_NO_HEADER = 0; literal T10$K_TXP04IP_LBA_LOG = 1; literal T10$K_TXP04IP_LBA_PHY = 2; literal T10$S_TXP04IP = 5; macro T10$R_TXP04IP_FLAGS = 0,0,8,0 %; literal T10$S_TXP04IP_FLAGS = 1; macro T10$V_TXP04IP_SI = 0,5,1,0 %; macro T10$V_TXP04IP_IP_MODIFIER = 0,6,2,0 %; literal T10$S_TXP04IP_IP_MODIFIER = 2; macro T10$B_TXP04IP_PATTERN_TYPE = 1,0,8,0 %; macro T10$W_TXP04IP_PATTERN_LENGTH = 2,0,16,0 %; macro T10$X_TXP04IP_PATTERN = 4,0,8,0 %; literal T10$K_TXP04FC111_FDLEN = 4; literal T10$K_TXP04FC111_LENGTH = 8; literal T10$K_TXP04FC001_MAXBLOCKS = -1; literal T10$K_TXP04FC001_RWFULL = 0; literal T10$K_TXP04FC001_MRWFULL = 16; literal T10$K_TXP04FC001_PRWFULL = 38; literal T10$K_TXP04FC001_FDLEN = 4; literal T10$K_TXP04FC001_LENGTH = 8; literal T10$S_TXP04FD = 8; macro T10$R_TXP04FC111 = 0,0,0,0 %; literal T10$S_TXP04FC111 = 8; macro T10$R_TXP04FC111_FLAGS = 0,0,8,0 %; literal T10$S_TXP04FC111_FLAGS = 1; macro T10$V_TXP04FC111_GROW = 0,6,1,0 %; macro T10$V_TXP04FC111_SESS = 0,7,1,0 %; macro T10$B_TXP04FC111_FILL1 = 1,0,8,0 %; macro T10$B_TXP04FC111_FILL2 = 2,0,8,0 %; macro T10$B_TXP04FC111_FILL3 = 3,0,8,0 %; macro T10$L_TXP04FC111_FORMAT_SIZE = 4,0,32,0 %; macro T10$R_TXP04FC001 = 0,0,0,0 %; literal T10$S_TXP04FC001 = 8; macro T10$L_TXP04FC001_BLOCKS = 0,0,32,0 %; macro T10$R_TXP04FC001_FLAGS = 4,0,8,0 %; literal T10$S_TXP04FC001_FLAGS = 1; macro T10$V_TXP04FC001_FMTTYP = 4,2,6,0 %; literal T10$S_TXP04FC001_FMTTYP = 6; macro T10$R_TXP04FC001FT00 = 5,0,24,0 %; literal T10$S_TXP04FC001FT00 = 3; macro T10$R_TXP04FC001FT26 = 5,0,24,0 %; literal T10$S_TXP04FC001FT26 = 3; macro T10$R_TXP04FC001FT26_FLAGS = 7,0,8,0 %; literal T10$S_TXP04FC001FT26_FLAGS = 1; macro T10$V_TXP04FC001FT26_RST = 7,0,1,0 %; macro T10$V_TXP04FC001FT26_QST = 7,1,1,0 %; literal T10$S_TXC08 = 6; macro T10$B_TXC08_OPCODE = 0,0,8,0 %; macro T10$R_TXC08_LBA = 1,0,8,0 %; literal T10$S_TXC08_LBA = 1; macro T10$V_TXC08_LBA1 = 1,0,5,0 %; literal T10$S_TXC08_LBA1 = 5; macro T10$W_TXC08_LBA = 2,0,16,0 %; macro T10$B_TXC08_BLOCKS = 4,0,8,0 %; macro T10$B_TXC08_CONTROL = 5,0,8,0 %; literal T10$K_VPD_SUPPORTED = 0; literal T10$K_VPD_SERIAL = 128; literal T10$S_TXC12 = 6; macro T10$B_TXC12_OPCODE = 0,0,8,0 %; macro T10$R_TXC12_FLAGS = 1,0,8,0 %; literal T10$S_TXC12_FLAGS = 1; macro T10$V_TXC12_EVPD = 1,0,1,0 %; macro T10$V_TXC12_CMDDT = 1,1,1,0 %; macro T10$B_TXC12_PAGE_OPCODE = 2,0,8,0 %; macro T10$W_TXC12_MAX_LENGTH = 3,0,16,0 %; macro T10$B_TXC12_CONTROL = 5,0,8,0 %; literal T10$K_DTYP_DIRATT = 0; literal T10$K_DTYP_SEQDEV = 1; literal T10$K_DTYP_PRINTER = 2; literal T10$K_DTYP_CPU = 3; literal T10$K_DTYP_WRTONCE = 4; literal T10$K_DTYP_CDROM = 5; literal T10$K_DTYP_SCANNER = 6; literal T10$K_DTYP_OPTICAL = 7; literal T10$K_DTYP_CHANGER = 8; literal T10$K_DTYP_COMMDEV = 9; literal T10$K_DTYP_ASCIT8A = 10; literal T10$K_DTYP_ASCIT8B = 11; literal T10$K_DTYP_STORARR = 12; literal T10$K_DTYP_ENCSERV = 13; literal T10$K_DTYP_SDIRATT = 14; literal T10$K_DTYP_CARDRDR = 15; literal T10$K_DTYP_OBJDEV = 16; literal T10$K_DTYP_AUTOMAT = 17; literal T10$K_DTYP_WELLKNOWN = 30; literal T10$K_DTYP_UNKNOWN = 31; literal T10$K_DEVQ_CONNECT = 0; literal T10$K_DEVQ_DISCONN = 1; literal T10$K_DEVQ_RSVD010 = 2; literal T10$K_DEVQ_NOPHYDEV = 3; literal T10$K_DEVQ_VENDOR = 4; literal T10$K_SPCVA_NOCLAIMS = 0; literal T10$K_SPCVA_OBS1 = 1; literal T10$K_SPCVA_SCSI2 = 2; literal T10$K_SPCVA_SPC = 3; literal T10$K_SPCVA_SPC2 = 4; literal T10$K_SPCVA_SPC3 = 5; literal T10$K_ATAPI_UNK0 = 0; literal T10$K_ATAPI_UNK1 = 1; literal T10$K_ATAPI_SFF8020 = 2; literal T10$K_ATAPI_SFF8090 = 3; literal T10$K_SPCVA_UNK4 = 4; literal T10$K_TXR12_BASE_LENGTH = 5; literal T10$K_TXR12_VERS_DESC = 8; literal T10$K_TXR12_VDSC_MMC1 = 348; literal T10$K_TXR12_VDSC_MMC1_10A = 347; literal T10$K_TXR12_VDSC_MMC2 = 576; literal T10$K_TXR12_VDSC_MMC2_2000 = 604; literal T10$K_TXR12_VDSC_MMC2_11A = 603; literal T10$K_TXR12_VDSC_MMC3 = 672; literal T10$K_TXR12_VDSC_MMC3_200X = 696; literal T10$K_TXR12_VDSC_MMC3_10G = 694; literal T10$K_TXR12_VDSC_MMC3_9 = 693; literal T10$K_TXR12_VDSC_MMC4 = 928; literal T10$K_TXR12_GENERIC_LENGTH = 255; literal T10$S_TXR12 = 255; macro T10$R_TXR12_PERIPHERAL = 0,0,8,0 %; literal T10$S_TXR12_PERIPHERAL = 1; macro T10$V_TXR12_DEVTYPE = 0,0,5,0 %; literal T10$S_TXR12_DEVTYPE = 5; macro T10$V_TXR12_DEVQUAL = 0,5,3,0 %; literal T10$S_TXR12_DEVQUAL = 3; macro T10$R_TXR12_REMOVABLE = 1,0,8,0 %; literal T10$S_TXR12_REMOVABLE = 1; macro T10$V_TXR12_REMOVABLE = 1,7,1,0 %; macro T10$R_TXR12_VERSION = 2,0,8,0 %; literal T10$S_TXR12_VERSION = 1; macro T10$V_TXR12_ANSI_VERSION = 2,0,3,0 %; literal T10$S_TXR12_ANSI_VERSION = 3; macro T10$V_TXR12_ECMA_VERSION = 2,3,3,0 %; literal T10$S_TXR12_ECMA_VERSION = 3; macro T10$V_TXR12_ISOIEC_VERSION = 2,6,2,0 %; literal T10$S_TXR12_ISOIEC_VERSION = 2; macro T10$R_TXR12_ADDROVERLAY = 3,0,8,0 %; literal T10$S_TXR12_ADDROVERLAY = 1; macro T10$R_TXR12_ADDRSCSI = 3,0,8,0 %; literal T10$S_TXR12_ADDRSCSI = 1; macro T10$V_TXR12_SCSI_RDF = 3,0,4,0 %; literal T10$S_TXR12_SCSI_RDF = 4; macro T10$V_TXR12_HISUP = 3,4,1,0 %; macro T10$V_TXR12_NORMACA = 3,5,1,0 %; macro T10$V_TXR12_AERC = 3,7,1,0 %; macro T10$R_TXR12_ADDRATAPI = 3,0,8,0 %; literal T10$S_TXR12_ADDRATAPI = 1; macro T10$V_TXR12_ATAPI_RDF = 3,0,4,0 %; literal T10$S_TXR12_ATAPI_RDF = 4; macro T10$V_TXR12_ATAPI_VERSION = 3,4,4,0 %; literal T10$S_TXR12_ATAPI_VERSION = 4; macro T10$B_TXR12_EXTRA_LENGTH = 4,0,8,0 %; macro T10$R_TXR12_FLAGS1 = 5,0,8,0 %; literal T10$S_TXR12_FLAGS1 = 1; macro T10$V_TXR12_3PC = 5,3,1,0 %; macro T10$V_TXR12_ALUA = 5,4,2,0 %; literal T10$S_TXR12_ALUA = 2; macro T10$V_TXR12_ACC = 5,6,1,0 %; macro T10$V_TXR12_SCCS = 5,7,1,0 %; macro T10$R_TXR12_FLAGS2 = 6,0,8,0 %; literal T10$S_TXR12_FLAGS2 = 1; macro T10$V_TXR12_ADDR16 = 6,0,1,0 %; macro T10$V_TXR12_MCHNGR = 6,3,1,0 %; macro T10$V_TXR12_MULTIP = 6,4,1,0 %; macro T10$V_TXR12_VS1 = 6,5,1,0 %; macro T10$V_TXR12_ENCSERV = 6,6,1,0 %; macro T10$V_TXR12_BQUE = 6,7,1,0 %; macro T10$R_TXR12_FLAGS3 = 7,0,8,0 %; literal T10$S_TXR12_FLAGS3 = 1; macro T10$V_TXR12_VS2 = 7,0,1,0 %; macro T10$V_TXR12_CMDQUE = 7,1,1,0 %; macro T10$V_TXR12_LINKED = 7,3,1,0 %; macro T10$V_TXR12_SYNC = 7,4,1,0 %; macro T10$V_TXR12_WBUS16 = 7,5,1,0 %; macro T10$V_TXR12_RELADR = 7,7,1,0 %; macro T10$T_TXR12_VENDNAME = 8,0,0,0 %; literal T10$S_TXR12_VENDNAME = 8; macro T10$T_TXR12_PRODNAME = 16,0,0,0 %; literal T10$S_TXR12_PRODNAME = 16; macro T10$T_TXR12_PRODREV = 32,0,32,0 %; literal T10$S_TXR12_PRODREV = 4; macro T10$X_TXR12_VENDOR_DATA = 36,0,0,0 %; literal T10$S_TXR12_VENDOR_DATA = 20; macro T10$R_TXR12_TX_FLAGS4 = 56,0,8,0 %; literal T10$S_TXR12_TX_FLAGS4 = 1; macro T10$V_TXR12_IUS = 56,0,1,0 %; macro T10$V_TXR12_QAS = 56,1,1,0 %; macro T10$V_TXR12_CLOCKING = 56,2,2,0 %; literal T10$S_TXR12_CLOCKING = 2; macro T10$W_TXR12_VERS_DESC = 58,0,0,0 %; literal T10$S_TXR12_VERS_DESC = 16; macro T10$B_TXR12_RESERVED75255 = 74,0,0,0 %; literal T10$S_TXR12_RESERVED75255 = 181; literal T10$K_VPD00_FIXED = 4; literal T10$S_VPD00 = 4; macro T10$R_VPD00_PERIPHERAL = 0,0,8,0 %; literal T10$S_VPD00_PERIPHERAL = 1; macro T10$V_VPD00_DEVTYPE = 0,0,5,0 %; literal T10$S_VPD00_DEVTYPE = 5; macro T10$V_VPD00_DEVQUAL = 0,5,3,0 %; literal T10$S_VPD00_DEVQUAL = 3; macro T10$B_VPD00_PAGE_CODE = 1,0,8,0 %; macro T10$B_VPD00_LENGTH = 3,0,8,0 %; literal T10$K_VPD80_FIXED = 4; literal T10$S_VPD80 = 4; macro T10$R_VPD80_PERIPHERAL = 0,0,8,0 %; literal T10$S_VPD80_PERIPHERAL = 1; macro T10$V_VPD80_DEVTYPE = 0,0,5,0 %; literal T10$S_VPD80_DEVTYPE = 5; macro T10$V_VPD80_DEVQUAL = 0,5,3,0 %; literal T10$S_VPD80_DEVQUAL = 3; macro T10$B_VPD80_PAGE_CODE = 1,0,8,0 %; macro T10$B_VPD80_LENGTH = 3,0,8,0 %; literal T10$S_TXC15 = 6; macro T10$B_TXC15_OPCODE = 0,0,8,0 %; macro T10$R_TXC15_FLAGS = 1,0,8,0 %; literal T10$S_TXC15_FLAGS = 1; macro T10$V_TXC15_SP = 1,0,1,0 %; macro T10$V_TXC15_PF = 1,4,1,0 %; macro T10$B_TXC15_LENGTH = 4,0,8,0 %; macro T10$B_TXC15_CONTROL = 5,0,8,0 %; literal T10$K_TXC1A_PC_CURR = 0; literal T10$K_TXC1A_PC_CHNG = 1; literal T10$K_TXC1A_PC_DFLT = 2; literal T10$K_TXC1A_PC_SAVE = 3; literal T10$S_TXC1A = 6; macro T10$B_TXC1A_OPCODE = 0,0,8,0 %; macro T10$R_TXC1A_FLAGS = 1,0,8,0 %; literal T10$S_TXC1A_FLAGS = 1; macro T10$V_TXC1A_DBD = 1,3,1,0 %; macro T10$V_TXC1A_FILL4 = 1,4,4,0 %; literal T10$S_TXC1A_FILL4 = 4; macro T10$R_TXC1A_PAGECTRL = 2,0,8,0 %; literal T10$S_TXC1A_PAGECTRL = 1; macro T10$V_TXC1A_PAGE = 2,0,6,0 %; literal T10$S_TXC1A_PAGE = 6; macro T10$V_TXC1A_CTRL = 2,6,2,0 %; literal T10$S_TXC1A_CTRL = 2; macro T10$B_TXC1A_SUBPAGE = 3,0,8,0 %; macro T10$B_TXC1A_LENGTH = 4,0,8,0 %; macro T10$B_TXC1A_CONTROL = 5,0,8,0 %; literal T10$K_OPC_STOPDISK = 0; literal T10$K_OPC_STARTDISK = 1; literal T10$K_OPC_EJECTDISK = 2; literal T10$K_OPC_LOADDISK = 3; literal T10$K_PWR_NOCHANGE = 0; literal T10$K_PWR_RSVD1 = 1; literal T10$K_PWR_IDLE = 2; literal T10$K_PWR_STANDBY = 3; literal T10$K_PWR_RSVD4 = 4; literal T10$K_PWR_SLEEP = 5; literal T10$K_PWR_RSVD6 = 6; literal T10$K_PWR_RSVD7 = 7; literal T10$K_PWR_RSVD8 = 8; literal T10$K_PWR_RSVD9 = 9; literal T10$K_PWR_RSVDA = 10; literal T10$K_PWR_RSVDB = 11; literal T10$K_PWR_RSVDC = 12; literal T10$K_PWR_RSVDD = 13; literal T10$K_PWR_RSVDE = 14; literal T10$K_PWR_RSVDF = 15; literal T10$S_TXC1B = 6; macro T10$B_TXC1B_OPCODE = 0,0,8,0 %; macro T10$R_TXC1B_FLAGS = 1,0,8,0 %; literal T10$S_TXC1B_FLAGS = 1; macro T10$V_TXC1B_IMMED = 1,0,1,0 %; macro T10$V_TXC1B_FILL11 = 1,1,7,0 %; literal T10$S_TXC1B_FILL11 = 7; macro T10$R_TXC1B_POWER = 4,0,8,0 %; literal T10$S_TXC1B_POWER = 1; macro T10$V_TXC1B_ACTION = 4,0,2,0 %; literal T10$S_TXC1B_ACTION = 2; macro T10$V_TXC1B_FILL42 = 4,2,2,0 %; literal T10$S_TXC1B_FILL42 = 2; macro T10$V_TXC1B_STATE = 4,4,4,0 %; literal T10$S_TXC1B_STATE = 4; macro T10$B_TXC1B_CONTROL = 5,0,8,0 %; literal T10$S_TXC23 = 10; macro T10$B_TXC23_OPCODE = 0,0,8,0 %; macro T10$W_TXC23_LENGTH = 7,0,16,0 %; macro T10$B_TXC23_CONTROL = 9,0,8,0 %; literal T10$K_TXR23FL_DT_RSVDMED = 0; literal T10$K_TXR23FL_DT_UNFMTMED = 1; literal T10$K_TXR23FL_DT_FMTMED = 2; literal T10$K_TXR23FL_DT_NOMEDIA = 3; literal T10$K_FMTTYP_WHOLE = 0; literal T10$K_FMTTYP_EXPAND = 1; literal T10$K_FMTTYP_RSVD02 = 2; literal T10$K_FMTTYP_RSVD03 = 3; literal T10$K_FMTTYP_ZONE = 4; literal T10$K_FMTTYP_HIZONE = 5; literal T10$K_FMTTYP_RSVD06 = 6; literal T10$K_FMTTYP_RSVD07 = 7; literal T10$K_FMTTYP_RSVD08 = 8; literal T10$K_FMTTYP_RSVD09 = 9; literal T10$K_FMTTYP_RSVD0A = 10; literal T10$K_FMTTYP_RSVD0B = 11; literal T10$K_FMTTYP_RSVD0C = 12; literal T10$K_FMTTYP_RSVD0D = 13; literal T10$K_FMTTYP_RSVD0E = 14; literal T10$K_FMTTYP_RSVD0F = 15; literal T10$K_FMTTYP_MAXRW = 16; literal T10$K_FMTTYP_GROWSESS = 17; literal T10$K_FMTTYP_ADDSESS = 18; literal T10$K_FMTTYP_GROWSESINT = 19; literal T10$K_FMTTYP_ADDSESSINT = 20; literal T10$K_FMTTYP_MAXRWINT = 21; literal T10$K_FMTTYP_RSVD16 = 22; literal T10$K_FMTTYP_RSVD17 = 23; literal T10$K_FMTTYP_RSVD18 = 24; literal T10$K_FMTTYP_RSVD19 = 25; literal T10$K_FMTTYP_RSVD1A = 26; literal T10$K_FMTTYP_RSVD1B = 27; literal T10$K_FMTTYP_RSVD1C = 28; literal T10$K_FMTTYP_RSVD1D = 29; literal T10$K_FMTTYP_RSVD1E = 30; literal T10$K_FMTTYP_RSVD1F = 31; literal T10$K_FMTTYP_RSVD20 = 32; literal T10$K_FMTTYP_RSVD21 = 33; literal T10$K_FMTTYP_RSVD22 = 34; literal T10$K_FMTTYP_RSVD23 = 35; literal T10$K_FMTTYP_MRWDMAADD = 36; literal T10$K_FMTTYP_RSVD25 = 37; literal T10$K_FMTTYP_PLUSRW = 38; literal T10$K_FMTTYP_RSVD27 = 39; literal T10$S_TXR23FL = 268; macro T10$B_TXR23FL_LENGTH = 3,0,8,0 %; macro T10$L_TXR23FL_BLOCKS = 4,0,32,0 %; macro T10$R_TXR23FL_FLAGS = 8,0,8,0 %; literal T10$S_TXR23FL_FLAGS = 1; macro T10$V_TXR23FL_DSCTYPE = 8,0,2,0 %; literal T10$S_TXR23FL_DSCTYPE = 2; macro T10$X_TXR23FL_BLOCK_SIZE = 9,0,24,0 %; literal T10$S_TXR23FL_BLOCK_SIZE = 3; macro T10$R_TXR23FLFC = 12,0,0,0 %; literal T10$S_TXR23FLFC = 256; macro T10$L_TXR23FLFC_BLOCKS = 12,0,32,0 %; macro T10$R_TXR23FLFC_FCFLAGS = 16,0,8,0 %; literal T10$S_TXR23FLFC_FCFLAGS = 1; macro T10$V_TXR23FLFC_RSVD = 16,0,2,0 %; literal T10$S_TXR23FLFC_RSVD = 2; macro T10$V_TXR23FLFC_FMTTYPE = 16,2,2,0 %; literal T10$S_TXR23FLFC_FMTTYPE = 2; macro T10$X_TXR23FLFC_TYPDEP = 17,0,24,0 %; literal T10$S_TXR23FLFC_TYPDEP = 3; literal T10$S_TXC25 = 10; macro T10$B_TXC25_OPCODE = 0,0,8,0 %; macro T10$R_TXC25_FLAGS = 1,0,8,0 %; literal T10$S_TXC25_FLAGS = 1; macro T10$V_TXC25_RELADR = 1,0,1,0 %; macro T10$L_TXC25_LBA = 2,0,32,0 %; macro T10$R_TXC25_FLAGS10 = 8,0,8,0 %; literal T10$S_TXC25_FLAGS10 = 1; macro T10$V_TXC25_PMI = 8,7,1,0 %; macro T10$B_TXC25_CONTROL = 9,0,8,0 %; literal T10$S_TXR25 = 8; macro T10$L_TXR25_MAX_LBA = 0,0,32,0 %; macro T10$L_TXR25_BLOCK_SIZE = 4,0,32,0 %; literal T10$S_TXC28 = 10; macro T10$B_TXC28_OPCODE = 0,0,8,0 %; macro T10$R_TXC28_FLAGS = 1,0,8,0 %; literal T10$S_TXC28_FLAGS = 1; macro T10$V_TXC28_RELADR = 1,0,1,0 %; macro T10$V_TXC28_FUA = 1,3,1,0 %; macro T10$V_TXC28_DPO = 1,4,1,0 %; macro T10$L_TXC28_LBA = 2,0,32,0 %; macro T10$W_TXC28_BLOCKS = 7,0,16,0 %; macro T10$B_TXC28_CONTROL = 9,0,8,0 %; literal T10$S_TXC2A = 10; macro T10$B_TXC2A_OPCODE = 0,0,8,0 %; macro T10$R_TXC2A_FLAGS = 1,0,8,0 %; literal T10$S_TXC2A_FLAGS = 1; macro T10$V_TXC2A_RELADR = 1,0,1,0 %; macro T10$V_TXC2A_EBP = 1,2,1,0 %; macro T10$V_TXC2A_FUA = 1,3,1,0 %; macro T10$V_TXC2A_DPO = 1,4,1,0 %; macro T10$L_TXC2A_LBA = 2,0,32,0 %; macro T10$W_TXC2A_BLOCKS = 7,0,16,0 %; macro T10$B_TXC2A_CONTROL = 9,0,8,0 %; literal T10$S_TXC2E = 10; macro T10$B_TXC2E_OPCODE = 0,0,8,0 %; macro T10$R_TXC2E_FLAGS = 1,0,8,0 %; literal T10$S_TXC2E_FLAGS = 1; macro T10$V_TXC2E_RELADR = 1,0,1,0 %; macro T10$V_TXC2E_BYTCHK = 1,1,1,0 %; macro T10$V_TXC2E_DPO = 1,4,1,0 %; macro T10$L_TXC2E_LBA = 2,0,32,0 %; macro T10$W_TXC2E_BLOCKS = 7,0,16,0 %; macro T10$B_TXC2E_CONTROL = 9,0,8,0 %; literal T10$S_TXC35 = 10; macro T10$B_TXC35_OPCODE = 0,0,8,0 %; macro T10$R_TXC35_FLAGS = 1,0,8,0 %; literal T10$S_TXC35_FLAGS = 1; macro T10$V_TXC35_RELADR = 1,0,1,0 %; macro T10$V_TXC35_IMMED = 1,1,1,0 %; macro T10$L_TXC35_LBA = 2,0,32,0 %; macro T10$W_TXC35_BLOCKS = 7,0,16,0 %; macro T10$B_TXC35_CONTROL = 9,0,8,0 %; literal T10$K_TXC43_FMT_ALLTRKS = 0; literal T10$K_TXC43_FMT_LASTTRK = 1; literal T10$K_TXC43_FMT_QSUBTOC = 2; literal T10$K_TXC43_FMT_QSUBPMA = 3; literal T10$K_TXC43_FMT_ATIP = 4; literal T10$K_TXC43_FMT_TEXT = 5; literal T10$S_TXC43 = 10; macro T10$B_TXC43_OPCODE = 0,0,8,0 %; macro T10$R_TXC43_FLAGS = 1,0,8,0 %; literal T10$S_TXC43_FLAGS = 1; macro T10$V_TXC43_TIME_OR_LBA = 1,1,1,0 %; macro T10$R_TXC43S_FORMAT = 2,0,8,0 %; literal T10$S_TXC43S_FORMAT = 1; macro T10$V_TXC43_FORMAT = 2,0,4,0 %; literal T10$S_TXC43_FORMAT = 4; macro T10$B_TXC43_TRKSESS = 6,0,8,0 %; macro T10$W_TXC43_LENGTH = 7,0,16,0 %; macro T10$B_TXC43_CONTROL = 9,0,8,0 %; literal T10$S_TXR43 = 4; macro T10$W_TXR43_DATA_LENGTH = 0,0,16,0 %; macro T10$B_TXR43_1ST_TRACK = 2,0,8,0 %; macro T10$B_TXR43_LAST_TRACK = 3,0,8,0 %; literal T10$K_TX43ADRTD_NO = 0; literal T10$K_TX43ADRTD_PS = 1; literal T10$K_TX43ADRTD_CT = 2; literal T10$K_TX43ADRTD_IS = 3; literal T10$S_TXR43TD = 8; macro T10$R_TXR43TD_FLAGS = 1,0,8,0 %; literal T10$S_TXR43TD_FLAGS = 1; macro T10$V_TXR43TD_CONTROL = 1,0,4,0 %; literal T10$S_TXR43TD_CONTROL = 4; macro T10$V_TXR43TD_ADR = 1,4,4,0 %; literal T10$S_TXR43TD_ADR = 4; macro T10$B_TXR43TD_TRACK = 2,0,8,0 %; macro T10$L_TXR43TD_TRACK_START = 4,0,32,0 %; literal T10$K_TXC46_RT_ALL = 0; literal T10$K_TXC46_RT_CURRENT = 1; literal T10$K_TXC46_RT_ONE = 2; literal T10$K_TXC46_RT_RESERVED = 3; literal T10$K_FCOD_LIST = 0; literal T10$K_FCOD_CORE = 1; literal T10$K_FCOD_MORPH = 2; literal T10$K_FCOD_REMOVABLE = 3; literal T10$K_FCOD_WRPROT = 4; literal T10$K_FCOD_RSVD05 = 5; literal T10$K_FCOD_RSVD06 = 6; literal T10$K_FCOD_RSVD07 = 7; literal T10$K_FCOD_RSVD08 = 8; literal T10$K_FCOD_RSVD09 = 9; literal T10$K_FCOD_RSVD0A = 10; literal T10$K_FCOD_RSVD0B = 11; literal T10$K_FCOD_RSVD0C = 12; literal T10$K_FCOD_RSVD0D = 13; literal T10$K_FCOD_RSVD0E = 14; literal T10$K_FCOD_RSVD0F = 15; literal T10$K_FCOD_RANDRD = 16; literal T10$K_FCOD_RSVD11 = 17; literal T10$K_FCOD_RSVD12 = 18; literal T10$K_FCOD_RSVD13 = 19; literal T10$K_FCOD_RSVD14 = 20; literal T10$K_FCOD_RSVD15 = 21; literal T10$K_FCOD_RSVD16 = 22; literal T10$K_FCOD_RSVD17 = 23; literal T10$K_FCOD_RSVD18 = 24; literal T10$K_FCOD_RSVD19 = 25; literal T10$K_FCOD_RSVD1A = 26; literal T10$K_FCOD_RSVD1B = 27; literal T10$K_FCOD_RSVD1C = 28; literal T10$K_FCOD_MULTIREAD = 29; literal T10$K_FCOD_CDREAD = 30; literal T10$K_FCOD_DVDREAD = 31; literal T10$K_FCOD_RANDWR = 32; literal T10$K_FCOD_INCSTRMWR = 33; literal T10$K_FCOD_SECTORERASE = 34; literal T10$K_FCOD_FORMATTABLE = 35; literal T10$K_FCOD_DEFECTMGMT1 = 36; literal T10$K_FCOD_WRITEONCE = 37; literal T10$K_FCOD_RESTROVRWR1 = 38; literal T10$K_FCOD_CDRWCAV = 39; literal T10$K_FCOD_MRW = 40; literal T10$K_FCOD_DEFECTMGMT2 = 41; literal T10$K_FCOD_DVDPLUSRW = 42; literal T10$K_FCOD_DVDPLUSR = 43; literal T10$K_FCOD_RESTOVRWR2 = 44; literal T10$K_FCOD_CDTAO = 45; literal T10$K_FCOD_CDMASTER = 46; literal T10$K_FCOD_DVDMINUSRW = 47; literal T10$K_FCOD_DDCD = 48; literal T10$K_FCOD_DDCDR = 49; literal T10$K_FCOD_DDCDRW = 50; literal T10$K_FCOD_LAYERJMP = 51; literal T10$K_FCOD_RSVD34 = 52; literal T10$K_FCOD_RSVD35 = 53; literal T10$K_FCOD_RSVD36 = 54; literal T10$K_FCOD_CDRWMEDRPT = 55; literal T10$K_FCOD_BDPOW = 56; literal T10$K_FCOD_RSVD39 = 57; literal T10$K_FCOD_DVDPLUSRWDL = 58; literal T10$K_FCOD_DVDPLUSRDL = 59; literal T10$K_FCOD_RSVD3C = 60; literal T10$K_FCOD_RSVD3D = 61; literal T10$K_FCOD_RSVD3E = 62; literal T10$K_FCOD_RSVD3F = 63; literal T10$K_FCOD_BDR = 64; literal T10$K_FCOD_BDW = 65; literal T10$K_FCOD_TSR = 66; literal T10$K_FCOD_RSVD43 = 67; literal T10$K_FCOD_RSVD44 = 68; literal T10$K_FCOD_RSVD45 = 69; literal T10$K_FCOD_RSVD46 = 70; literal T10$K_FCOD_RSVD47 = 71; literal T10$K_FCOD_RSVD48 = 72; literal T10$K_FCOD_RSVD49 = 73; literal T10$K_FCOD_RSVD4A = 74; literal T10$K_FCOD_RSVD4B = 75; literal T10$K_FCOD_RSVD4C = 76; literal T10$K_FCOD_RSVD4D = 77; literal T10$K_FCOD_RSVD4E = 78; literal T10$K_FCOD_RSVD4F = 79; literal T10$K_FCOD_HDR = 80; literal T10$K_FCOD_HDW = 81; literal T10$K_FCOD_PWRMGMT = 256; literal T10$K_FCOD_RSVD101 = 257; literal T10$K_FCOD_EMBCHNGR = 258; literal T10$K_FCOD_CDAUDIO = 259; literal T10$K_FCOD_FWUPGR = 260; literal T10$K_FCOD_TIMEOUT = 261; literal T10$K_FCOD_DVDCSS = 262; literal T10$K_FCOD_RTSTREAM = 263; literal T10$K_FCOD_SERIALNUM = 264; literal T10$K_FCOD_RSVD109 = 265; literal T10$K_FCOD_CNTLBLKS = 266; literal T10$K_FCOD_DVDCPRM = 267; literal T10$K_FCOD_FWINFO = 268; literal T10$K_FCOD_AACS = 269; literal T10$K_FCOD_RSVD10E = 270; literal T10$K_FCOD_RSVD10F = 271; literal T10$K_FCOD_VCPS = 272; literal T10$K_FCOD_FWDATE = 511; literal T10$S_TXC46 = 10; macro T10$B_TXC46_OPCODE = 0,0,8,0 %; macro T10$R_TXC46_FLAGS = 1,0,8,0 %; literal T10$S_TXC46_FLAGS = 1; macro T10$V_TXC46_REQTYP = 1,0,2,0 %; literal T10$S_TXC46_REQTYP = 2; macro T10$W_TXC46_1ST_FEAT = 2,0,16,0 %; macro T10$W_TXC46_RSP_LENGTH = 7,0,16,0 %; macro T10$B_TXC46_CONTROL = 9,0,8,0 %; literal T10$K_TXR46FH_LENGTH = 8; literal T10$S_TXR46FH = 8; macro T10$L_TXR46FH_LENGTH = 0,0,32,0 %; macro T10$W_TXR46FH_CURR_PROFILE = 6,0,16,0 %; literal T10$K_TXR46FD_MRW = 40; literal T10$K_TXR46FD_DVDPRW = 42; literal T10$K_TXR46FD_DVDPR = 43; literal T10$K_TXR46FD_LENGTH = 4; literal T10$K_TXR46FD00_SIZE = 64; literal T10$K_PROF_RSVD00 = 0; literal T10$K_PROF_FIXEDDISK = 1; literal T10$K_PROF_REMOVABLE = 2; literal T10$K_PROF_MOERASABLE = 3; literal T10$K_PROF_WORMDISK = 4; literal T10$K_PROF_ASMO = 5; literal T10$K_PROF_RSVD06 = 6; literal T10$K_PROF_RSVD07 = 7; literal T10$K_PROF_CDROM = 8; literal T10$K_PROF_CDR = 9; literal T10$K_PROF_CDRW = 10; literal T10$K_PROF_RSVD0B = 11; literal T10$K_PROF_RSVD0C = 12; literal T10$K_PROF_RSVD0D = 13; literal T10$K_PROF_RSVD0E = 14; literal T10$K_PROF_RSVD0F = 15; literal T10$K_PROF_DVDROM = 16; literal T10$K_PROF_DVDMINUSRSEQ = 17; literal T10$K_PROF_DVDRAM = 18; literal T10$K_PROF_DVDMINUSRWRO = 19; literal T10$K_PROF_DVDMINUSRWSEQ = 20; literal T10$K_PROF_DVDMINUSRDLSEQ = 21; literal T10$K_PROF_DVDMINUSRDLJMP = 22; literal T10$K_PROF_RSVD17 = 23; literal T10$K_PROF_RSVD18 = 24; literal T10$K_PROF_RSVD19 = 25; literal T10$K_PROF_DVDPLUSRW = 26; literal T10$K_PROF_DVDPLUSR = 27; literal T10$K_PROF_RSVD1C = 28; literal T10$K_PROF_RSVD1D = 29; literal T10$K_PROF_RSVD1E = 30; literal T10$K_PROF_RSVD1F = 31; literal T10$K_PROF_DDCDROM = 32; literal T10$K_PROF_DDCDR = 33; literal T10$K_PROF_DDCDRW = 34; literal T10$K_PROF_RSVD23 = 35; literal T10$K_PROF_RSVD24 = 36; literal T10$K_PROF_RSVD25 = 37; literal T10$K_PROF_RSVD26 = 38; literal T10$K_PROF_RSVD27 = 39; literal T10$K_PROF_RSVD28 = 40; literal T10$K_PROF_RSVD29 = 41; literal T10$K_PROF_DVDPLUSRWDL = 42; literal T10$K_PROF_DVDPLUSRDL = 43; literal T10$K_PROF_RSVD2C = 44; literal T10$K_PROF_RSVD2D = 45; literal T10$K_PROF_RSVD2E = 46; literal T10$K_PROF_RSVD2F = 47; literal T10$K_PROF_RSVD30 = 48; literal T10$K_PROF_RSVD31 = 49; literal T10$K_PROF_RSVD32 = 50; literal T10$K_PROF_RSVD33 = 51; literal T10$K_PROF_RSVD34 = 52; literal T10$K_PROF_RSVD35 = 53; literal T10$K_PROF_RSVD36 = 54; literal T10$K_PROF_RSVD37 = 55; literal T10$K_PROF_RSVD38 = 56; literal T10$K_PROF_RSVD39 = 57; literal T10$K_PROF_RSVD3A = 58; literal T10$K_PROF_RSVD3B = 59; literal T10$K_PROF_RSVD3C = 60; literal T10$K_PROF_RSVD3D = 61; literal T10$K_PROF_RSVD3E = 62; literal T10$K_PROF_RSVD3F = 63; literal T10$K_PROF_BDROM = 64; literal T10$K_PROF_BDRSRM = 65; literal T10$K_PROF_BDRRRM = 66; literal T10$K_PROF_BDRE = 67; literal T10$K_PROF_RSVD44 = 68; literal T10$K_PROF_RSVD45 = 69; literal T10$K_PROF_RSVD46 = 70; literal T10$K_PROF_RSVD47 = 71; literal T10$K_PROF_RSVD48 = 72; literal T10$K_PROF_RSVD49 = 73; literal T10$K_PROF_RSVD4A = 74; literal T10$K_PROF_RSVD4B = 75; literal T10$K_PROF_RSVD4C = 76; literal T10$K_PROF_RSVD4D = 77; literal T10$K_PROF_RSVD4E = 78; literal T10$K_PROF_RSVD4F = 79; literal T10$K_PROF_HDDVDROM = 80; literal T10$K_PROF_HDDVDR = 81; literal T10$K_PROF_HDDVDRW = 82; literal T10$K_PROF_RSVD53 = 83; literal T10$K_PROF_RSVD54 = 84; literal T10$K_PROF_RSVD55 = 85; literal T10$K_PROF_RSVD56 = 86; literal T10$K_PROF_RSVD57 = 87; literal T10$K_PROF_RSVD58 = 88; literal T10$K_PROF_RSVD59 = 89; literal T10$K_PROF_RSVD5A = 90; literal T10$K_PROF_RSVD5B = 91; literal T10$K_PROF_RSVD5C = 92; literal T10$K_PROF_RSVD5D = 93; literal T10$K_PROF_RSVD5E = 94; literal T10$K_PROF_RSVD5F = 95; literal T10$K_PROF_NONCONFORM = 65535; literal T10$M_TXR46_MEDV1 = 1; literal T10$M_TXR46_MEDV2 = 2; literal T10$M_TXR46_MEDV3 = 4; literal T10$M_TXR46_MEDVX = 248; literal T10$S_TXR46FD = 260; macro T10$W_TXR46FD_FEATURE_CODE = 0,0,16,0 %; macro T10$R_TXR46FD_FLAGS = 2,0,8,0 %; literal T10$S_TXR46FD_FLAGS = 1; macro T10$V_TXR46FD_CURRENT = 2,0,1,0 %; macro T10$V_TXR46FD_PERSISTENT = 2,1,1,0 %; macro T10$V_TXR46FD_VERSION = 2,2,4,0 %; literal T10$S_TXR46FD_VERSION = 4; macro T10$B_TXR46FD_EXTRA_LENGTH = 3,0,8,0 %; macro T10$R_TXR46FD00 = 4,0,0,0 %; literal T10$S_TXR46FD00 = 256; macro T10$W_TXR46FD00_FEATURE_CODE = 4,0,16,0 %; macro T10$R_TXR46FD00_FLAGS = 6,0,8,0 %; literal T10$S_TXR46FD00_FLAGS = 1; macro T10$V_TXR46FD00_CURRENT = 6,0,1,0 %; macro T10$V_TXR46FD00_PERSISTENT = 6,1,1,0 %; macro T10$V_TXR46FD00_VERSION = 6,2,4,0 %; literal T10$S_TXR46FD00_VERSION = 4; macro T10$B_TXR46FD00_EXTRA_LENGTH = 7,0,8,0 %; macro T10$R_TXR46FD2A = 4,0,0,0 %; literal T10$S_TXR46FD2A = 12; macro T10$R_TXR46FD2A_FLAGS = 4,0,16,0 %; literal T10$S_TXR46FD2A_FLAGS = 2; macro T10$V_TXR46FD2A_WRITE = 4,0,1,0 %; macro T10$V_TXR46FD2A_CLOSEONLY = 4,8,1,0 %; macro T10$V_TXR46FD2A_QUICKST = 4,9,1,0 %; macro T10$B_TXR46FD2A_SUPPMEDVERS = 8,0,8,0 %; macro T10$R_TXR46FD2A_SUPPMEDVERS = 8,0,8,0 %; literal T10$S_TXR46FD2A_SUPPMEDVERS = 1; macro T10$V_TXR46FD2A_SUPPVERS1 = 8,0,1,0 %; macro T10$V_TXR46FD2A_SUPPVERS2 = 8,1,1,0 %; macro T10$V_TXR46FD2A_SUPPVERS3 = 8,2,1,0 %; macro T10$V_TXR46FD2A_SUPPOTHER = 8,3,5,0 %; literal T10$S_TXR46FD2A_SUPPOTHER = 5; macro T10$B_TXR46FD2A_CURRMEDVERS = 12,0,8,0 %; macro T10$R_TXR46FD2A_CURRMEDVERS = 12,0,8,0 %; literal T10$S_TXR46FD2A_CURRMEDVERS = 1; macro T10$V_TXR46FD2A_CURRVERS1 = 12,0,1,0 %; macro T10$V_TXR46FD2A_CURRVERS2 = 12,1,1,0 %; macro T10$V_TXR46FD2A_CURRVERS3 = 12,2,1,0 %; macro T10$V_TXR46FD2A_CURROTHER = 12,3,5,0 %; literal T10$S_TXR46FD2A_CURROTHER = 5; macro T10$R_TXR46FD2B = 4,0,0,0 %; literal T10$S_TXR46FD2B = 12; macro T10$R_TXR46FD2B_FLAGS = 4,0,8,0 %; literal T10$S_TXR46FD2B_FLAGS = 1; macro T10$V_TXR46FD2B_WRITE = 4,0,1,0 %; macro T10$B_TXR46FD2B_SUPPMEDVERS = 8,0,8,0 %; macro T10$R_TXR46FD2B_SUPPMEDVERS = 8,0,8,0 %; literal T10$S_TXR46FD2B_SUPPMEDVERS = 1; macro T10$V_TXR46FD2B_SUPPVERS1 = 8,0,1,0 %; macro T10$V_TXR46FD2B_SUPPVERS2 = 8,1,1,0 %; macro T10$V_TXR46FD2B_SUPPVERS3 = 8,2,1,0 %; macro T10$B_TXR46FD2B_CURRMEDVERS = 12,0,8,0 %; macro T10$R_TXR46FD2B_CURRMEDVERS = 12,0,8,0 %; literal T10$S_TXR46FD2B_CURRMEDVERS = 1; macro T10$V_TXR46FD2B_CURRVERS1 = 12,0,1,0 %; macro T10$V_TXR46FD2B_CURRVERS2 = 12,1,1,0 %; macro T10$V_TXR46FD2B_CURRVERS3 = 12,2,1,0 %; macro T10$R_TXR46FD2F = 4,0,0,0 %; literal T10$S_TXR46FD2F = 5; macro T10$B_TXR46FD2F_ADDITIONAL_LEN = 4,0,8,0 %; macro T10$R_TXR46FD2F_FLAGS = 5,0,8,0 %; literal T10$S_TXR46FD2F_FLAGS = 1; macro T10$V_TXR46FD2F_RW = 5,1,1,0 %; macro T10$V_TXR46FD2F_TEST_WR = 5,2,1,0 %; macro T10$V_TXR46FD2F_BUF = 5,6,1,0 %; literal T10$S_TXR46FL = 262148; macro T10$W_TXR46FL_FEATURE_CODE = 0,0,16,0 %; macro T10$R_TXR46FL_FLAGS = 2,0,8,0 %; literal T10$S_TXR46FL_FLAGS = 1; macro T10$V_TXR46FL_CURRENT = 2,0,1,0 %; macro T10$V_TXR46FL_PERSISTENT = 2,1,1,0 %; macro T10$V_TXR46FL_VERSION = 2,2,4,0 %; literal T10$S_TXR46FL_VERSION = 4; macro T10$B_TXR46FL_ADDITIONAL_LEN = 3,0,8,0 %; macro T10$R_TXR46FLPD = 4,0,0,0 %; literal T10$S_TXR46FLPD = 262144; macro T10$W_TXR46FLPD_FEATURE_CODE = 4,0,16,0 %; macro T10$R_TXR46FLPD_FLAGS = 6,0,8,0 %; literal T10$S_TXR46FLPD_FLAGS = 1; macro T10$V_TXR46FLPD_CURRENT = 6,0,1,0 %; literal T10$K_TXR46PD_LENGTH = 4; literal T10$S_TXR46PD = 4; macro T10$W_TXR46PD_PROFILE = 0,0,16,0 %; macro T10$R_TXR46PD_FLAGS = 2,0,8,0 %; literal T10$S_TXR46PD_FLAGS = 1; macro T10$V_TXR46PD_CURRENT = 2,0,1,0 %; literal T10$S_TXC4A = 10; macro T10$B_TXC4A_OPCODE = 0,0,8,0 %; macro T10$R_TXC4A_FLAGS = 1,0,8,0 %; literal T10$S_TXC4A_FLAGS = 1; macro T10$V_TXC4A_POLLED = 1,0,1,0 %; macro T10$R_TXC4A_REQ_CLASSES = 4,0,8,0 %; literal T10$S_TXC4A_REQ_CLASSES = 1; macro T10$V_TXC4A_GESN_OPCHANGE = 4,1,1,0 %; macro T10$V_TXC4A_GESN_POWER = 4,2,1,0 %; macro T10$V_TXC4A_GESN_EXTREQ = 4,3,1,0 %; macro T10$V_TXC4A_GESN_MEDIA = 4,4,1,0 %; macro T10$V_TXC4A_GESN_MULTI = 4,5,1,0 %; macro T10$V_TXC4A_GESN_DEVBUSY = 4,6,1,0 %; macro T10$W_TXC4A_LENGTH = 7,0,16,0 %; macro T10$B_TXC4A_CONTROL = 9,0,8,0 %; literal T10$K_TXR4A_GESN_NONE = 0; literal T10$K_TXR4A_GESN_OPCHANGE = 1; literal T10$K_TXR4A_GESN_POWER = 2; literal T10$K_TXR4A_GESN_EXTREQ = 3; literal T10$K_TXR4A_GESN_MEDIA = 4; literal T10$K_TXR4A_GESN_MULTI = 5; literal T10$K_TXR4A_GESN_DEVBUSY = 272; literal T10$K_TXR4ANC001_EVT_NOCHG = 0; literal T10$K_TXR4ANC001_EVT_CHGING = 1; literal T10$K_TXR4ANC001_EVT_CHGED = 2; literal T10$K_TXR4ANC001_STS_AVAIL = 0; literal T10$K_TXR4ANC001_STS_BUSY = 1; literal T10$K_TXR4ANC001_STS_RSVD = 2; literal T10$K_TXR4ANC001_CHG_NOCHG = 0; literal T10$K_TXR4ANC001_CHG_CFEAT = 1; literal T10$K_TXR4ANC001_CHG_NFEAT = 2; literal T10$K_TXR4ANC001_CHG_RESET = 3; literal T10$K_TXR4ANC001_CHG_CFIRM = 4; literal T10$K_TXR4ANC001_CHG_CINQD = 5; literal T10$K_TXR4ANC010_EVT_NOCHG = 0; literal T10$K_TXR4ANC010_EVT_CHGOK = 1; literal T10$K_TXR4ANC010_EVT_CHGNG = 2; literal T10$K_TXR4ANC010_STS_RSVD = 0; literal T10$K_TXR4ANC010_STS_ACTIVE = 1; literal T10$K_TXR4ANC010_STS_IDLE = 2; literal T10$K_TXR4ANC010_STS_STNDBY = 3; literal T10$K_TXR4ANC010_STS_SLEEP = 4; literal T10$K_TXR4ANC011_EVT_NOCHG = 0; literal T10$K_TXR4ANC011_EVT_KEYDN = 1; literal T10$K_TXR4ANC011_EVT_KEYUP = 2; literal T10$K_TXR4ANC011_EVT_EXTREQ = 3; literal T10$K_TXR4ANC011_STS_READY = 0; literal T10$K_TXR4ANC011_STS_OTHPRV = 1; literal T10$K_TXR4ANC011_EXT_NOREQ = 0; literal T10$K_TXR4ANC011_EXT_OVRUN = 1; literal T10$K_TXR4ANC011_EXT_PLAY = 257; literal T10$K_TXR4ANC011_EXT_REW = 258; literal T10$K_TXR4ANC011_EXT_FFWD = 259; literal T10$K_TXR4ANC011_EXT_PAUS = 260; literal T10$K_TXR4ANC011_EXT_STOP = 262; literal T10$K_TXR4ANC011_EXT_ASCL = 512; literal T10$K_TXR4ANC011_EXT_ASCH = 767; literal T10$K_TXR4ANC011_EXT_VNDL = 61440; literal T10$K_TXR4ANC011_EXT_VNDH = 65535; literal T10$K_TXR4ANC100_MED_NOCHG = 0; literal T10$K_TXR4ANC100_MED_EJECT = 1; literal T10$K_TXR4ANC100_MED_NEW = 2; literal T10$K_TXR4ANC100_MED_REM = 3; literal T10$K_TXR4ANC100_MED_CHG = 4; literal T10$K_TXR4ANC100_MED_BGFDON = 5; literal T10$K_TXR4ANC100_MED_BGFRES = 6; literal T10$K_TXR4ANC110_BSY_NOCHG = 0; literal T10$K_TXR4ANC110_BSY_CHG = 1; literal T10$K_TXR4ANC110_BSY_NOT = 0; literal T10$K_TXR4ANC110_BSY_BUSY = 1; literal T10$S_TXR4A = 8; macro T10$W_TXR4A_DATA_LENGTH = 0,0,16,0 %; macro T10$R_TXR4A_FLAGS = 2,0,8,0 %; literal T10$S_TXR4A_FLAGS = 1; macro T10$V_TXR4A_GESN_CURR_EVENT = 2,0,3,0 %; literal T10$S_TXR4A_GESN_CURR_EVENT = 3; macro T10$V_TXR4A_NEA = 2,7,1,0 %; macro T10$R_TXR4A_SUPP_CLASSES = 3,0,8,0 %; literal T10$S_TXR4A_SUPP_CLASSES = 1; macro T10$V_TXR4A_GESN_OPCHANGE = 3,1,1,0 %; macro T10$V_TXR4A_GESN_POWER = 3,2,1,0 %; macro T10$V_TXR4A_GESN_EXTREQ = 3,3,1,0 %; macro T10$V_TXR4A_GESN_MEDIA = 3,4,1,0 %; macro T10$V_TXR4A_GESN_MULTI = 3,5,1,0 %; macro T10$V_TXR4A_GESN_DEVBUSY = 3,6,1,0 %; macro T10$R_TXR4ANC001 = 4,0,32,0 %; literal T10$S_TXR4ANC001 = 4; macro T10$R_TXR4ANC001_FLAGS = 4,0,8,0 %; literal T10$S_TXR4ANC001_FLAGS = 1; macro T10$V_TXR4ANC001_EVENT = 4,0,4,0 %; literal T10$S_TXR4ANC001_EVENT = 4; macro T10$R_TXR4ANC001_STATE = 5,0,8,0 %; literal T10$S_TXR4ANC001_STATE = 1; macro T10$V_TXR4ANC001_STATUS = 5,0,4,0 %; literal T10$S_TXR4ANC001_STATUS = 4; macro T10$V_TXR4ANC001_PERSPREV = 5,7,1,0 %; macro T10$W_TXR4ANC001_CHANGE = 6,0,16,0 %; macro T10$R_TXR4ANC010 = 4,0,32,0 %; literal T10$S_TXR4ANC010 = 4; macro T10$R_TXR4ANC010_FLAGS = 4,0,8,0 %; literal T10$S_TXR4ANC010_FLAGS = 1; macro T10$V_TXR4ANC010_EVENT = 4,0,4,0 %; literal T10$S_TXR4ANC010_EVENT = 4; macro T10$B_TXR4ANC010_STATUS = 5,0,8,0 %; macro T10$B_TXR4ANC010_RSVD2 = 6,0,8,0 %; macro T10$B_TXR4ANC010_RSVD3 = 7,0,8,0 %; macro T10$R_TXR4ANC011 = 4,0,32,0 %; literal T10$S_TXR4ANC011 = 4; macro T10$R_TXR4ANC011_FLAGS = 4,0,8,0 %; literal T10$S_TXR4ANC011_FLAGS = 1; macro T10$V_TXR4ANC011_EVENT = 4,0,4,0 %; literal T10$S_TXR4ANC011_EVENT = 4; macro T10$R_TXR4ANC011_STATE = 5,0,8,0 %; literal T10$S_TXR4ANC011_STATE = 1; macro T10$V_TXR4ANC011_STATUS = 5,0,4,0 %; literal T10$S_TXR4ANC011_STATUS = 4; macro T10$V_TXR4ANC011_PERSPREV = 5,7,1,0 %; macro T10$W_TXR4ANC011_EXTREQ = 6,0,16,0 %; macro T10$R_TXR4ANC100 = 4,0,32,0 %; literal T10$S_TXR4ANC100 = 4; macro T10$R_TXR4ANC100_FLAGS = 4,0,8,0 %; literal T10$S_TXR4ANC100_FLAGS = 1; macro T10$V_TXR4ANC100_EVENT = 4,0,4,0 %; literal T10$S_TXR4ANC100_EVENT = 4; macro T10$R_TXR4ANC100_STATUS = 5,0,8,0 %; literal T10$S_TXR4ANC100_STATUS = 1; macro T10$V_TXR4ANC100_DOOR_OPEN = 5,0,1,0 %; macro T10$V_TXR4ANC100_MEDIA_PRESENT = 5,1,1,0 %; macro T10$B_TXR4ANC100_RSVD2 = 6,0,8,0 %; macro T10$B_TXR4ANC100_RSVD3 = 7,0,8,0 %; macro T10$R_TXR4ANC110 = 4,0,32,0 %; literal T10$S_TXR4ANC110 = 4; macro T10$R_TXR4ANC110_FLAGS = 4,0,8,0 %; literal T10$S_TXR4ANC110_FLAGS = 1; macro T10$V_TXR4ANC110_EVENT = 4,0,4,0 %; literal T10$S_TXR4ANC110_EVENT = 4; macro T10$B_TXR4ANC110_BSY_STATUS = 5,0,8,0 %; macro T10$W_TXR4ANC110_TIME = 6,0,16,0 %; literal T10$S_TXC51 = 10; macro T10$B_TXC51_OPCODE = 0,0,8,0 %; macro T10$W_TXC51_LENGTH = 7,0,16,0 %; macro T10$B_TXC51_CONTROL = 9,0,8,0 %; literal T10$K_TXR51_DSTAT_EMP = 0; literal T10$K_TXR51_DSTAT_INC = 1; literal T10$K_TXR51_DSTAT_FIN = 2; literal T10$K_TXR51_DSTAT_OTH = 3; literal T10$K_TXR51_SSTAT_EMP = 0; literal T10$K_TXR51_SSTAT_INC = 1; literal T10$K_TXR51_SSTAT_RSV = 2; literal T10$K_TXR51_SSTAT_OK = 3; literal T10$K_TXR51_BGFS_UNF = 0; literal T10$K_TXR51_BGFS_PAUS = 1; literal T10$K_TXR51_BGFS_UNDW = 2; literal T10$K_TXR51_BGFS_FMTD = 3; literal T10$K_TXR51_CDTYP_CDROM = 0; literal T10$K_TXR51_CDTYP_CDI = 16; literal T10$K_TXR51_CDTYP_CDXA = 32; literal T10$K_TXR51_CDTYP_OTHER = 255; literal T10$S_TXR51 = 286; macro T10$W_TXR51_LENGTH = 0,0,16,0 %; macro T10$R_TXR51_STATE = 2,0,8,0 %; literal T10$S_TXR51_STATE = 1; macro T10$V_TXR51_DISK_STATUS = 2,0,2,0 %; literal T10$S_TXR51_DISK_STATUS = 2; macro T10$V_TXR51_SESS_STATUS = 2,2,2,0 %; literal T10$S_TXR51_SESS_STATUS = 2; macro T10$V_TXR51_ERASABLE = 2,4,1,0 %; macro T10$B_TXR51_1ST_TRACK = 3,0,8,0 %; macro T10$B_TXR51_SESS_LSB = 4,0,8,0 %; macro T10$B_TXR51_1ST_TRACK_LSB = 5,0,8,0 %; macro T10$B_TXR51_LAST_TRACK_LSB = 6,0,8,0 %; macro T10$R_TXR51_FORMAT = 7,0,8,0 %; literal T10$S_TXR51_FORMAT = 1; macro T10$V_TXR51_BGF_STATUS = 7,0,2,0 %; literal T10$S_TXR51_BGF_STATUS = 2; macro T10$V_TXR51_DBIT = 7,2,1,0 %; macro T10$V_TXR51_URU = 7,4,1,0 %; macro T10$V_TXR51_DBC_V = 7,5,1,0 %; macro T10$V_TXR51_DID_V = 7,6,1,0 %; macro T10$B_TXR51_DISKTYPE = 8,0,8,0 %; macro T10$B_TXR51_SESS_MSB = 9,0,8,0 %; macro T10$B_TXR51_1ST_TRACK_MSB = 10,0,8,0 %; macro T10$B_TXR51_LAST_TRACK_MSB = 11,0,8,0 %; macro T10$L_TXR51_DISK_ID = 12,0,32,0 %; macro T10$L_TXR51_LEADIN_ADDR = 16,0,32,0 %; macro T10$L_TXR51_LEADOUT_ADDR = 20,0,32,0 %; macro T10$L_TXR51_BARCODE = 24,0,32,0 %; macro T10$B_TXR51_RSVD32 = 28,0,8,0 %; macro T10$B_TXR51_OPC_TABLES = 29,0,8,0 %; macro T10$R_TXR51OPC = 30,0,0,0 %; literal T10$S_TXR51OPC = 256; macro T10$W_TXR51_SPEED = 30,0,16,0 %; macro T10$X_TXR51_OPC_VENDOR_DATA = 32,0,0,0 %; literal T10$S_TXR51_OPC_VENDOR_DATA = 6; literal T10$K_TXC52_LBA = 0; literal T10$K_TXC52_TRACK_RZONE = 1; literal T10$K_TXC52_SESSION = 2; literal T10$K_TXC52_RSVD = 3; literal T10$S_TXC52 = 10; macro T10$B_TXC52_OPCODE = 0,0,8,0 %; macro T10$R_TXC52_FLAGS = 1,0,8,0 %; literal T10$S_TXC52_FLAGS = 1; macro T10$V_TXC52_ADDR_NUM = 1,0,2,0 %; literal T10$S_TXC52_ADDR_NUM = 2; macro T10$L_TXC52_ADDRESS = 2,0,32,0 %; macro T10$W_TXC52_ALLOC_LEN = 7,0,16,0 %; macro T10$B_TXC52_CONTROL = 9,0,8,0 %; literal T10$M_QSUB_AUD_MASK = 13; literal T10$M_QSUB_DATA_MASK = 4; literal T10$M_QSUB_COPY_MASK = 2; literal T10$K_QSUB_00X0 = 0; literal T10$K_QSUB_00X1 = 1; literal T10$K_QSUB_10X0 = 8; literal T10$K_QSUB_10X1 = 9; literal T10$K_QSUB_01X0 = 4; literal T10$K_QSUB_01X1 = 5; literal T10$K_QSUB_DDCD = 4; literal T10$K_TX52_SESSION = 2; literal T10$K_TX52_RSVD = 3; literal T10$K_DATA_MODE1 = 1; literal T10$K_DATA_MODE2 = 2; literal T10$K_DATA_UNKNOWN = 15; literal T10$S_TXR52 = 36; macro T10$W_TXR52_DATA_LENGTH = 0,0,16,0 %; macro T10$B_TXR52_TRACK_LSB = 2,0,8,0 %; macro T10$B_TXR52_SESS_LSB = 3,0,8,0 %; macro T10$R_TXR52_FLAGS5 = 5,0,8,0 %; literal T10$S_TXR52_FLAGS5 = 1; macro T10$V_TXR52_TRK_MODE = 5,0,4,0 %; literal T10$S_TXR52_TRK_MODE = 4; macro T10$V_TXR52_COPY = 5,4,1,0 %; macro T10$V_TXR52_DAMAGE = 5,5,1,0 %; macro T10$R_TXR52_FLAGS6 = 6,0,8,0 %; literal T10$S_TXR52_FLAGS6 = 1; macro T10$V_TXR52_DATA_MODE = 6,0,4,0 %; literal T10$S_TXR52_DATA_MODE = 4; macro T10$V_TXR52_FP = 6,4,1,0 %; macro T10$V_TXR52_PCK_INC = 6,5,1,0 %; macro T10$V_TXR52_BLANK = 6,6,1,0 %; macro T10$V_TXR52_RT = 6,7,1,0 %; macro T10$R_TXR52_FLAGS7 = 7,0,8,0 %; literal T10$S_TXR52_FLAGS7 = 1; macro T10$V_TXR52_NWA_V = 7,0,1,0 %; macro T10$V_TXR52_LRA_V = 7,1,1,0 %; macro T10$L_TXR52_TRACK_START = 8,0,32,0 %; macro T10$L_TXR52_NEXT_WRITE = 12,0,32,0 %; macro T10$L_TXR52_FREE_BLOCKS = 16,0,32,0 %; macro T10$L_TXR52_BLOCK_FACTOR = 20,0,32,0 %; macro T10$L_TXR52_TRACK_SIZE = 24,0,32,0 %; macro T10$L_TXR52_LAST_ADDRESS = 28,0,32,0 %; macro T10$B_TXR52_TRACK_MSB = 32,0,8,0 %; macro T10$B_TXR52_SESS_MSB = 33,0,8,0 %; literal T10$S_TXC53 = 10; macro T10$B_TXC53_OPCODE = 0,0,8,0 %; macro T10$L_TXC53_SECTORS = 5,0,32,0 %; macro T10$B_TXC53_CONTROL = 9,0,8,0 %; literal T10$S_TXC55 = 10; macro T10$B_TXC55_OPCODE = 0,0,8,0 %; macro T10$R_TXC55_FLAGS = 1,0,8,0 %; literal T10$S_TXC55_FLAGS = 1; macro T10$V_TXC55_SP = 1,0,1,0 %; macro T10$V_TXC55_PF = 1,4,1,0 %; macro T10$W_TXC55_LENGTH = 7,0,16,0 %; macro T10$B_TXC55_CONTROL = 9,0,8,0 %; literal T10$K_TXC5B_FUNC_FMT = 0; literal T10$K_TXC5B_FUNC_TRK = 1; literal T10$K_TXC5B_FUNC_SES = 2; literal T10$K_TXC5B_FUNC_SPC = 3; literal T10$K_TXC5B_FUNC_SESFD = 5; literal T10$K_TXC5B_FINALIZE = 154; literal T10$S_TXC5B = 10; macro T10$B_TXC5B_OPCODE = 0,0,8,0 %; macro T10$R_TXC5B_FLAGS = 1,0,8,0 %; literal T10$S_TXC5B_FLAGS = 1; macro T10$V_TXC5B_FL_IMMED = 1,0,1,0 %; macro T10$R_TXC5B_FUNC = 2,0,8,0 %; literal T10$S_TXC5B_FUNC = 1; macro T10$V_TXC5B_FUNC_CLOSE = 2,0,3,0 %; literal T10$S_TXC5B_FUNC_CLOSE = 3; macro T10$W_TXC5B_TRACK = 4,0,16,0 %; macro T10$B_TXC5B_CONTROL = 9,0,8,0 %; literal T10$K_MP_MMCAP = 42; literal T10$K_MP_WRITEPARAM = 5; literal T10$K_MP_TMO_PROT = 5; literal T10$K_TXC5A_PC_CURR = 0; literal T10$K_TXC5A_PC_CHNG = 1; literal T10$K_TXC5A_PC_DFLT = 2; literal T10$K_TXC5A_PC_SAVE = 3; literal T10$S_TXC5A = 10; macro T10$B_TXC5A_OPCODE = 0,0,8,0 %; macro T10$R_TXC5A_FLAGS = 1,0,8,0 %; literal T10$S_TXC5A_FLAGS = 1; macro T10$V_TXC5A_DBD = 1,3,1,0 %; macro T10$V_TXC5A_LLBA = 1,4,1,0 %; macro T10$V_TXC5A_FILL15 = 1,5,3,0 %; literal T10$S_TXC5A_FILL15 = 3; macro T10$R_TXC5A_PAGECTRL = 2,0,8,0 %; literal T10$S_TXC5A_PAGECTRL = 1; macro T10$V_TXC5A_PAGE = 2,0,6,0 %; literal T10$S_TXC5A_PAGE = 6; macro T10$V_TXC5A_CTRL = 2,6,2,0 %; literal T10$S_TXC5A_CTRL = 2; macro T10$B_TXC5A_SUBPAGE = 3,0,8,0 %; macro T10$W_TXC5A_LENGTH = 7,0,16,0 %; macro T10$B_TXC5A_CONTROL = 9,0,8,0 %; literal T10$S_TXCA8 = 12; macro T10$B_TXCA8_OPCODE = 0,0,8,0 %; macro T10$R_TXCA8_FLAGS1 = 1,0,8,0 %; literal T10$S_TXCA8_FLAGS1 = 1; macro T10$V_TXCA8_RELADR = 1,0,1,0 %; macro T10$V_TXCA8_FUA = 1,3,1,0 %; macro T10$V_TXCA8_DPO = 1,4,1,0 %; macro T10$L_TXCA8_LBA = 2,0,32,0 %; macro T10$L_TXCA8_BLOCKS = 6,0,32,0 %; macro T10$R_TXCA8_FLAGS10 = 10,0,8,0 %; literal T10$S_TXCA8_FLAGS10 = 1; macro T10$V_TXCA8_STREAM = 10,7,1,0 %; macro T10$B_TXCA8_CONTROL = 11,0,8,0 %; literal T10$K_BT_FULL = 0; literal T10$K_BT_QUICK = 1; literal T10$K_BT_TRACK = 2; literal T10$K_BT_UNRES_TRACK = 3; literal T10$K_BT_TAIL_TRACK = 4; literal T10$K_BT_UNCLOSE_SESS = 5; literal T10$K_BT_ERASE_SESS = 6; literal T10$S_TXCA1 = 12; macro T10$B_TXCA1_OPCODE = 0,0,8,0 %; macro T10$R_TXCA1_FLAGS1 = 1,0,8,0 %; literal T10$S_TXCA1_FLAGS1 = 1; macro T10$V_TXCA1_BLANKTYPE = 1,0,3,0 %; literal T10$S_TXCA1_BLANKTYPE = 3; macro T10$V_TXCA1_IMMED = 1,4,1,0 %; macro T10$L_TXCA1_START = 2,0,32,0 %; macro T10$B_TXCA1_CONTROL = 11,0,8,0 %; literal T10$S_TXCAA = 12; macro T10$B_TXCAA_OPCODE = 0,0,8,0 %; macro T10$R_TXCAA_FLAGS = 1,0,8,0 %; literal T10$S_TXCAA_FLAGS = 1; macro T10$V_TXCAA_FUA = 1,3,1,0 %; macro T10$L_TXCAA_LBA = 2,0,32,0 %; macro T10$L_TXCAA_BLOCKS = 6,0,32,0 %; macro T10$R_TXCAA_FLAGS10 = 10,0,8,0 %; literal T10$S_TXCAA_FLAGS10 = 1; macro T10$V_TXCAA_STREAM = 10,7,1,0 %; macro T10$B_TXCAA_CONTROL = 11,0,8,0 %; literal T10$K_TXCAD_FMT_PHY = 0; literal T10$S_TXCAD = 12; macro T10$B_TXCAD_OPCODE = 0,0,8,0 %; macro T10$B_TXCAD_FILL1 = 1,0,8,0 %; macro T10$L_TXCAD_ADDR = 2,0,32,0 %; macro T10$B_TXCAD_LAYER = 6,0,8,0 %; macro T10$B_TXCAD_FORMAT = 7,0,8,0 %; macro T10$W_TXCAD_LENGTH = 8,0,16,0 %; macro T10$R_TXCAD_FLAGS = 10,0,8,0 %; literal T10$S_TXCAD_FLAGS = 1; macro T10$V_TXCAD_AGID = 10,6,2,0 %; literal T10$S_TXCAD_AGID = 2; macro T10$B_TXCAD_CONTROL = 11,0,8,0 %; literal T10$K_TXRAD_FIXED = 4; literal T10$K_BKT_DVDROM = 0; literal T10$K_BKT_DVDRAM = 1; literal T10$K_BKT_DVDMR = 2; literal T10$K_BKT_DVDMRW = 3; literal T10$K_BKT_DVDRW = 9; literal T10$K_BKT_DVDPR = 10; literal T10$K_MXR_1X = 0; literal T10$K_MXR_2X = 1; literal T10$K_MXR_4X = 2; literal T10$K_MXR_8X = 3; literal T10$K_MXR_NOTSPEC = 15; literal T10$K_DSZ_120MM = 0; literal T10$K_DSZ_80MM = 0; literal T10$K_TXRAD_LENGTH = 2052; literal T10$S_TXRAD = 2052; macro T10$W_TXRAD_DATA_LENGTH = 0,0,16,0 %; macro T10$R_TXRAD_FC00 = 4,0,0,0 %; literal T10$S_TXRAD_FC00 = 2048; macro T10$R_TXRAD_FC00_HDR = 4,0,32,0 %; literal T10$S_TXRAD_FC00_HDR = 4; macro T10$V_TXRAD_FC00_PARTVER = 4,0,4,0 %; literal T10$S_TXRAD_FC00_PARTVER = 4; macro T10$V_TXRAD_FC00_BKTYPE = 4,4,4,0 %; literal T10$S_TXRAD_FC00_BKTYPE = 4; macro T10$V_TXRAD_FC00_MAXRATE = 4,8,4,0 %; literal T10$S_TXRAD_FC00_MAXRATE = 4; macro T10$V_TXRAD_FC00_DVDSIZE = 4,12,4,0 %; literal T10$S_TXRAD_FC00_DVDSIZE = 4; macro T10$V_TXRAD_FC00_ROMLAYER = 4,16,1,0 %; macro T10$V_TXRAD_FC00_R_LAYER = 4,17,1,0 %; macro T10$V_TXRAD_FC00_RW_LAYER = 4,18,1,0 %; macro T10$V_TXRAD_FC00_UNKLAYER = 4,19,1,0 %; macro T10$V_TXRAD_FC00_TKPATH = 4,20,1,0 %; macro T10$V_TXRAD_FC00_LAYERS = 4,21,2,0 %; literal T10$S_TXRAD_FC00_LAYERS = 2; macro T10$V_TXRAD_FC00_TKDENS = 4,24,4,0 %; literal T10$S_TXRAD_FC00_TKDENS = 4; macro T10$V_TXRAD_FC00_LNDENSE = 4,28,4,0 %; literal T10$S_TXRAD_FC00_LNDENSE = 4; macro T10$L_TXRAD_FC00_DATALO = 8,0,32,0 %; macro T10$L_TXRAD_FC00_DATAHI = 12,0,32,0 %; macro T10$L_TXRAD_FC00_ZEROHI = 16,0,32,0 %; macro T10$R_TXRADS_FC00_BCA = 20,0,16,0 %; literal T10$S_TXRADS_FC00_BCA = 2; macro T10$V_TXRAD_FC00_BCA = 20,7,4,0 %; literal T10$S_TXRAD_FC00_BCA = 4; macro T10$B_TXRAD_FC00_JUNQUE = 22,0,0,0 %; literal T10$S_TXRAD_FC00_JUNQUE = 2030; literal T10$K_STRM_PERFORM = 0; literal T10$K_STRM_UNUSABLE = 1; literal T10$K_STRM_DEFECT = 2; literal T10$K_STRM_WRITE = 3; literal T10$K_STRM_DBI = 4; literal T10$K_STRM_DBI_CACHE = 5; literal T10$S_TXCB6 = 12; macro T10$B_TXCB6_OPCODE = 0,0,8,0 %; macro T10$B_TXCB6_TYPE = 8,0,8,0 %; macro T10$W_TXCB6_LENGTH = 9,0,16,0 %; macro T10$B_TXCB6_CONTROL = 11,0,8,0 %; literal T10$S_TXPB6 = 28; macro T10$R_TXPB6_FLAGS = 0,0,8,0 %; literal T10$S_TXPB6_FLAGS = 1; macro T10$V_TXPB6_RA = 0,0,1,0 %; macro T10$V_TXPB6_EXACT = 0,1,1,0 %; macro T10$V_TXPB6_RDD = 0,2,1,0 %; macro T10$V_TXPB6_WRC = 0,3,2,0 %; literal T10$S_TXPB6_WRC = 2; macro T10$L_TXPB6_START_LBA = 4,0,32,0 %; macro T10$L_TXPB6_END_LBA = 8,0,32,0 %; macro T10$L_TXPB6_READ_SIZE = 12,0,32,0 %; macro T10$L_TXPB6_READ_TIME = 16,0,32,0 %; macro T10$L_TXPB6_WRITE_SIZE = 20,0,32,0 %; macro T10$L_TXPB6_WRITE_TIME = 24,0,32,0 %; literal T10$K_TXCBB_RC_CLV = 0; literal T10$K_TXCBB_RC_CAV = 1; literal T10$S_TXCBB = 12; macro T10$B_TXCBB_OPCODE = 0,0,8,0 %; macro T10$R_TXCBB_FLAGS1 = 1,0,8,0 %; literal T10$S_TXCBB_FLAGS1 = 1; macro T10$V_TXCBB_ROTCON = 1,0,2,0 %; literal T10$S_TXCBB_ROTCON = 2; macro T10$V_TXCBB_LUN = 1,5,3,0 %; literal T10$S_TXCBB_LUN = 3; macro T10$W_TXCBB_READ_SPEED = 2,0,16,0 %; macro T10$W_TXCBB_WRITE_SPEED = 4,0,16,0 %; macro T10$B_TXCBB_CONTROL = 11,0,8,0 %; literal T13$S_DQIOSB = 8; macro T13$W_DQIO_STATUS = 0,0,16,0 %; macro T13$R_DQIO_TRANSFER = 2,0,0,0 %; literal T13$S_DQIO_TRANSFER = 6; macro T13$L_DQIO_BYTES = 2,0,32,0 %; macro T13$B_DQIO_RSVD_XFR = 6,0,8,0 %; macro T13$B_DQIO_SENSEKEY = 7,0,8,0 %; macro T13$R_DQIO_RESET = 2,0,0,0 %; literal T13$S_DQIO_RESET = 6; macro T13$W_DQIO_RSVD_RST = 2,0,16,0 %; macro T13$L_DQIO_RESETS = 4,0,32,0 %; literal T13$K_T13_NOP = 0; literal T13$K_T13_SOFT_RESET = 8; literal T13$K_T13_RECALIBRATE = 16; literal T13$K_T13_READ_SECS = 32; literal T13$K_T13_READ_SECS_WO_RET = 33; literal T13$K_T13_READ_LONG = 34; literal T13$K_T13_READ_LONG_WO_RET = 35; literal T13$K_T13_WRITE_SECS = 48; literal T13$K_T13_WRITE_SECS_WO_RET = 49; literal T13$K_T13_WRITE_LONG = 50; literal T13$K_T13_WRITE_LONG_WO_RET = 51; literal T13$K_T13_WRITE_VFY = 60; literal T13$K_T13_READ_VFY_SECS = 64; literal T13$K_T13_READ_VFY_SECS_WO_RET = 65; literal T13$K_T13_FORMAT_TRACK = 80; literal T13$K_T13_SEEK = 112; literal T13$K_T13_80 = 128; literal T13$K_T13_EXEC_DEV_DIAGS = 144; literal T13$K_T13_INIT_DEV_PARAMS = 145; literal T13$K_T13_DOWNLOAD_UCODE = 146; literal T13$K_T13_STANDBY_IMMED_94 = 148; literal T13$K_T13_IDLE_IMMED_95 = 149; literal T13$K_T13_STANDBY_96 = 150; literal T13$K_T13_IDLE_97 = 151; literal T13$K_T13_CHK_PWR_MODE_98 = 152; literal T13$K_T13_SLEEP_99 = 153; literal T13$K_T13_PACKET_CMD = 160; literal T13$K_T13_PACKET_IDENTIFY = 161; literal T13$K_T13_SMART_DSBL_OPS = 176; literal T13$K_T13_SMART_ATTR_AUTO = 176; literal T13$K_T13_SMART_ENBL_OPER = 176; literal T13$K_T13_SMART_ATTR_THRESH = 176; literal T13$K_T13_SMART_RETURN_STATUS = 176; literal T13$K_T13_SEC_SET_PSWD_OBS = 186; literal T13$K_T13_SEC_UNLOCK_OBS = 187; literal T13$K_T13_SEC_ERASE_PREP_OBS = 188; literal T13$K_T13_SEC_ERASE_UNIT_OBS = 189; literal T13$K_T13_SEC_FREEZE_LOCK_OBS = 190; literal T13$K_T13_SEC_DSBL_PSWD_OBS = 191; literal T13$K_T13_READ_MULTIPLE = 196; literal T13$K_T13_WRITE_MULTI = 197; literal T13$K_T13_SET_MULTI_MODE = 198; literal T13$K_T13_READ_DMA = 200; literal T13$K_T13_READ_DMA_WO_RET = 201; literal T13$K_T13_WRITE_DMA = 202; literal T13$K_T13_WRITE_DMA_WO_RET = 203; literal T13$K_T13_DOOR_LOCK = 222; literal T13$K_T13_DOOR_UNLOCK = 223; literal T13$K_T13_STANDBY_IMMED_E0 = 224; literal T13$K_T13_IDLE_IMMED_E1 = 225; literal T13$K_T13_STANDBY_E2 = 226; literal T13$K_T13_IDLE_E3 = 227; literal T13$K_T13_READ_BUFFER = 228; literal T13$K_T13_CHK_PWR_MODE_E5 = 229; literal T13$K_T13_SLEEP_E6 = 230; literal T13$K_T13_WRITE_BUFFER = 232; literal T13$K_T13_IDENTIFY_DEV = 236; literal T13$K_T13_MEDIA_EJECT = 237; literal T13$K_T13_IDENTIFY_DEV_DMA = 238; literal T13$K_T13_SET_FEATURES = 239; literal T13$K_T13_SECUR_SET_PSWD = 241; literal T13$K_T13_SECUR_UNLOCK = 242; literal T13$K_T13_SECUR_ERASE_PREPARE = 243; literal T13$K_T13_SECUR_ERASE_UNIT = 244; literal T13$K_T13_SECUR_FREEZE_LOCK = 245; literal T13$K_T13_SECUR_DSBL_PSWD = 246; literal T13$S_ATACMD = 7; macro T13$B_CMD_FEATURES = 0,0,8,0 %; macro T13$B_CMD_SECTOR_COUNT = 1,0,8,0 %; macro T13$B_CMD_SECTOR_NUMBER = 2,0,8,0 %; macro T13$W_CMD_CYLINDER = 3,0,16,0 %; macro T13$R_CMD_DEVICE_HEAD = 5,0,8,0 %; literal T13$S_CMD_DEVICE_HEAD = 1; macro T13$V_CMD_DEV = 5,4,1,0 %; macro T13$B_CMD_COMMAND = 6,0,8,0 %; literal T10$K_BLK_SIZE_512 = 512; literal T10$K_BLK_SIZE_2048 = 2048; literal T10$K_BLK_SIZE_2352 = 2352; literal T10$K_T10_TEST_UNIT_READY = 0; literal T10$K_T10_REQUEST_SENSE = 3; literal T10$K_T10_FORMAT_UNIT = 4; literal T10$K_T10_READ_6 = 8; literal T10$K_T10_WRITE_6 = 10; literal T10$K_T10_INQUIRY = 18; literal T10$K_T10_MODE_SELECT_6 = 21; literal T10$K_T10_MODE_SENSE_6 = 26; literal T10$K_T10_START_STOP_UNIT = 27; literal T10$K_T10_PREVENT_ALLOW = 30; literal T10$K_T10_READ_FORMAT_CAP = 35; literal T10$K_T10_READ_CAPACITY = 37; literal T10$K_T10_READ_10 = 40; literal T10$K_T10_WRITE_10 = 42; literal T10$K_T10_SEEK = 43; literal T10$K_T10_WRITE_VERIFY_10 = 46; literal T10$K_T10_SYNCHRONIZE_CACHE = 53; literal T10$K_T10_WRITE_BUFFER = 59; literal T10$K_T10_READ_SUBCHANNEL = 66; literal T10$K_T10_READ_TOC_PMA_ATIP = 67; literal T10$K_T10_READ_HEADER = 68; literal T10$K_T10_PLAY_AUDIO_10 = 69; literal T10$K_T10_GET_CONFIG = 70; literal T10$K_T10_PLAY_AUDIO_MSF = 71; literal T10$K_T10_GET_EVENT_STATUS = 74; literal T10$K_T10_PAUSE_RESUME = 75; literal T10$K_T10_STOP_PLAY_SCAN = 78; literal T10$K_T10_READ_DISK_INFO = 81; literal T10$K_T10_READ_TRACK_INFO = 82; literal T10$K_T10_RESERVE_TRACK = 83; literal T10$K_T10_SEND_OPC_INFO = 84; literal T10$K_T10_MODE_SELECT_10 = 85; literal T10$K_T10_REPAIR_TRACK = 88; literal T10$K_T10_READ_MASTER_CUE = 89; literal T10$K_T10_MODE_SENSE_10 = 90; literal T10$K_T10_CLOSE_TRACK = 91; literal T10$K_T10_READ_BUFFER_CAP = 92; literal T10$K_T10_SEND_CUE_SHEET = 93; literal T10$K_T10_60 = 96; literal T10$K_T10_70 = 112; literal T10$K_T10_80 = 128; literal T10$K_T10_90 = 144; literal T10$K_T10_BLANK = 161; literal T10$K_T10_SEND_KEY = 163; literal T10$K_T10_PLAY_AUDIO_12 = 165; literal T10$K_T10_LOAD_UNLOAD_CD = 166; literal T10$K_T10_READ_12 = 168; literal T10$K_T10_WRITE_12 = 170; literal T10$K_T10_READ_DVD_STRUCT = 173; literal T10$K_T10_SET_STREAMING = 182; literal T10$K_T10_READ_CD_MSF = 185; literal T10$K_T10_SCAN = 186; literal T10$K_T10_SET_CD_SPEED = 187; literal T10$K_T10_PLAY_CD = 188; literal T10$K_T10_MECHANISM_STATUS = 189; literal T10$K_T10_READ_CD = 190; literal T10$K_T10_SEND_DVD_STRUCT = 191; literal T10$K_T10_C0 = 192; literal T10$K_T10_D0 = 208; literal T10$K_T10_E0 = 224; literal T10$K_T10_F0 = 240; literal T10$S_ATAPICMD = 1; macro T10$B_SDL_PACIFIER = 0,0,8,0 %; literal T13$S_ATAR = 7; macro T13$B_ATAR_ERROR = 0,0,8,0 %; macro T13$B_ATAR_SECTOR_COUNT = 1,0,8,0 %; macro T13$B_ATAR_SECTOR_NUMBER = 2,0,8,0 %; macro T13$W_ATAR_CYLINDER = 3,0,16,0 %; macro T13$R_ATAR_DEVICE_HEAD = 5,0,8,0 %; literal T13$S_ATAR_DEVICE_HEAD = 1; macro T13$V_ATAR_DEV = 5,4,1,0 %; macro T13$R_ATAR_STATUS = 6,0,8,0 %; literal T13$S_ATAR_STATUS = 1; macro T13$V_ATAR_ERR = 6,0,1,0 %; macro T13$V_ATAR_DRQ = 6,3,1,0 %; macro T13$V_ATAR_DF = 6,5,1,0 %; macro T13$V_ATAR_DRDY = 6,6,1,0 %; macro T13$V_ATAR_BSY = 6,7,1,0 %; literal T13$K_IPDPS_12BYTE = 0; literal T13$K_IPDPS_16BYTE = 1; literal T13$K_IPDPS_RSVD10 = 2; literal T13$K_IPDPS_RSVD11 = 3; literal T13$K_IPDDRQ_3MS = 0; literal T13$K_IPDDRQ_RSVD01 = 1; literal T13$K_IPDDRQ_50US = 2; literal T13$K_IPDDRQ_RSVD11 = 3; literal T13$K_IPDA_RSVD00 = 0; literal T13$K_IPDA_RSVD01 = 1; literal T13$K_IPDA_ATAPI = 2; literal T13$K_IPDA_RSVD11 = 3; literal T13$K_SCFG_SETFSU_INC = 14280; literal T13$K_SCFG_SETFSU_CMP = 14220; literal T13$K_SCFG_AUTOSU_INC = 35955; literal T13$K_SCFG_AUTOSU_CMP = 51255; literal T13$V_MAJV_ATA3 = 3; literal T13$M_MAJV_ATA3 = 8; literal T13$V_MAJV_ATAPI4 = 4; literal T13$M_MAJV_ATAPI4 = 16; literal T13$V_MAJV_ATAPI5 = 5; literal T13$M_MAJV_ATAPI5 = 32; literal T13$V_MAJV_ATAPI6 = 6; literal T13$M_MAJV_ATAPI6 = 64; literal T13$V_MAJV_ATAPI7 = 7; literal T13$M_MAJV_ATAPI7 = 128; literal T13$V_MAJV_ATAPI8 = 8; literal T13$M_MAJV_ATAPI8 = 256; literal T13$V_MAJV_ATAPI9 = 9; literal T13$M_MAJV_ATAPI9 = 512; literal T13$V_MAJV_ATAPI10 = 10; literal T13$M_MAJV_ATAPI10 = 1024; literal T13$V_MAJV_ATAPI11 = 11; literal T13$M_MAJV_ATAPI11 = 2048; literal T13$V_MAJV_ATAPI12 = 12; literal T13$M_MAJV_ATAPI12 = 4096; literal T13$V_MAJV_ATAPI13 = 13; literal T13$M_MAJV_ATAPI13 = 8192; literal T13$V_MAJV_ATAPI14 = 14; literal T13$M_MAJV_ATAPI14 = 16384; literal T13$K_HRR_UNIT_RSVD = 0; literal T13$K_HRR_UNIT_PLUG = 1; literal T13$K_HRR_UNIT_CSEL = 2; literal T13$K_HRR_UNIT_OTHR = 3; literal T13$K_SIGNATURE = 165; literal T13$S_ATAPIRA1 = 524; macro T13$R_ID_GENERAL = 0,0,16,0 %; literal T13$S_ID_GENERAL = 2; macro T13$V_ID_INCOMPLETE = 0,2,1,0 %; macro T13$V_ID_REMOVABLE = 0,7,1,0 %; macro T13$V_ID_ATA = 0,15,1,0 %; macro T13$R_IPD_GENERAL = 0,0,16,0 %; literal T13$S_IPD_GENERAL = 2; macro T13$V_IPD_PACKET_SIZE = 0,0,2,0 %; literal T13$S_IPD_PACKET_SIZE = 2; macro T13$V_IPD_INCOMPLETE = 0,2,1,0 %; macro T13$V_IPD_RSVD34 = 0,3,2,0 %; literal T13$S_IPD_RSVD34 = 2; macro T13$V_IPD_DRQ = 0,5,2,0 %; literal T13$S_IPD_DRQ = 2; macro T13$V_IPD_REMOVABLE = 0,7,1,0 %; macro T13$V_IPD_CMDPKTSET = 0,8,5,0 %; literal T13$S_IPD_CMDPKTSET = 5; macro T13$V_IPD_ATAPI = 0,14,2,0 %; literal T13$S_IPD_ATAPI = 2; macro T13$W_CHS_CYLINDERS = 2,0,16,0 %; macro T13$W_CHS_HEADS = 6,0,16,0 %; macro T13$W_CHS_SECTORS_PER_TRACK = 12,0,16,0 %; macro T13$T_SERIAL_NUMBER = 20,0,0,0 %; literal T13$S_SERIAL_NUMBER = 20; macro T13$T_FIRMWARE_REVISION = 46,0,0,0 %; literal T13$S_FIRMWARE_REVISION = 20; macro T13$T_MODEL_NUMBER = 66,0,0,0 %; literal T13$S_MODEL_NUMBER = 40; macro T13$R_MULTIPLE47 = 106,0,16,0 %; literal T13$S_MULTIPLE47 = 2; macro T13$V_SECTOR_TRANSFER = 106,0,8,0 %; literal T13$S_SECTOR_TRANSFER = 8; macro T13$V_HEX80 = 106,8,8,0 %; literal T13$S_HEX80 = 8; macro T13$R_CAPABILITIES49 = 110,0,16,0 %; literal T13$S_CAPABILITIES49 = 2; macro T13$V_DMA_SUPPORTED = 110,8,1,0 %; macro T13$V_LBA_SUPPORTED = 110,9,1,0 %; macro T13$V_IORDY_SELECTABLE = 110,10,1,0 %; macro T13$V_IORDY_SUPPORTED = 110,11,1,0 %; macro T13$V_ATA_RESET = 110,12,1,0 %; macro T13$V_TIMER_COMPLIANT = 110,13,1,0 %; macro T13$V_COMMAND_QUEUING = 110,14,1,0 %; macro T13$V_INTERLEAVED_DMA = 110,15,1,0 %; macro T13$R_CAPABILITIES50 = 112,0,16,0 %; literal T13$S_CAPABILITIES50 = 2; macro T13$V_LOCAL_TIMER = 112,0,1,0 %; macro T13$V_C50_MB1 = 112,14,1,0 %; macro T13$V_C50_MB0 = 112,15,1,0 %; macro T13$R_FIELD_STATUS53 = 118,0,16,0 %; literal T13$S_FIELD_STATUS53 = 2; macro T13$V_VALID5458 = 118,0,1,0 %; macro T13$V_VALID6470 = 118,1,1,0 %; macro T13$V_VALID88 = 118,2,1,0 %; macro T13$R_INTERRUPT_SECTORS59 = 130,0,16,0 %; literal T13$S_INTERRUPT_SECTORS59 = 2; macro T13$V_SECTORS_PER_INTERRUPT = 130,0,8,0 %; literal T13$S_SECTORS_PER_INTERRUPT = 8; macro T13$V_VALID = 130,8,1,0 %; macro T13$L_USER_SECTORS = 132,0,32,0 %; macro T13$R_MW_DMA_MODE63 = 138,0,16,0 %; literal T13$S_MW_DMA_MODE63 = 2; macro T13$V_MW_DMA_MODE_0_OK = 138,0,1,0 %; macro T13$V_MW_DMA_MODE_1_OK = 138,1,1,0 %; macro T13$V_MW_DMA_MODE_2_OK = 138,2,1,0 %; macro T13$V_MW_DMA_MODE_0_ON = 138,8,1,0 %; macro T13$V_MW_DMA_MODE_1_ON = 138,9,1,0 %; macro T13$V_MW_DMA_MODE_2_ON = 138,10,1,0 %; macro T13$R_ADV_PIO_MODE64 = 140,0,16,0 %; literal T13$S_ADV_PIO_MODE64 = 2; macro T13$V_PIO_MODES_SUPP = 140,0,8,0 %; literal T13$S_PIO_MODES_SUPP = 8; macro T13$W_MIN_MW_DMA_CYCLE = 142,0,16,0 %; macro T13$W_REC_MW_DMA_CYCLE = 144,0,16,0 %; macro T13$W_MIN_PIO_CYCLE = 146,0,16,0 %; macro T13$W_MIN_PIO_IORDY_CYCLE = 148,0,16,0 %; macro T13$R_QUEUE_DEPTH75 = 162,0,16,0 %; literal T13$S_QUEUE_DEPTH75 = 2; macro T13$V_MAX_QUEUE_DEPTH = 162,0,5,0 %; literal T13$S_MAX_QUEUE_DEPTH = 5; macro T13$W_MAJOR_VERSION = 172,0,16,0 %; macro T13$W_MINOR_VERSION = 174,0,16,0 %; macro T13$R_COMMAND_SETS82 = 176,0,32,0 %; literal T13$S_COMMAND_SETS82 = 4; macro T13$V_SMART = 176,0,1,0 %; macro T13$V_SECURITY = 176,1,1,0 %; macro T13$V_REMOVABLE = 176,2,1,0 %; macro T13$V_POWER = 176,3,1,0 %; macro T13$V_PACKET = 176,4,1,0 %; macro T13$V_WRITE_CACHE = 176,5,1,0 %; macro T13$V_LOOKAHEAD = 176,6,1,0 %; macro T13$V_RELEASE_INT = 176,7,1,0 %; macro T13$V_SERVICE_INT = 176,8,1,0 %; macro T13$V_DEVICE_RESET = 176,9,1,0 %; macro T13$V_HOST_PROTECTED = 176,10,1,0 %; macro T13$V_WRITE_BUFFER = 176,12,1,0 %; macro T13$V_READ_BUFFER = 176,13,1,0 %; macro T13$V_NOP = 176,14,1,0 %; macro T13$V_MICROCODE = 176,16,1,0 %; macro T13$V_DMA_QUEUED = 176,17,1,0 %; macro T13$V_CFA = 176,18,1,0 %; macro T13$V_ADV_POWER = 176,19,1,0 %; macro T13$V_MEDIA_STATUS = 176,20,1,0 %; macro T13$V_PWRUP_STANDBY = 176,21,1,0 %; macro T13$V_HOST_SPINUP = 176,22,1,0 %; macro T13$V_RSVD_AREA_BOOT = 176,23,1,0 %; macro T13$V_SET_MAX_SECURITY = 176,24,1,0 %; macro T13$V_AUTO_ACCOUSTICS = 176,25,1,0 %; macro T13$V_48B_ADDRESSING = 176,26,1,0 %; macro T13$V_CONFIG_OVERLAY = 176,27,1,0 %; macro T13$V_FLUSH_CACHE = 176,28,1,0 %; macro T13$V_FLUSH_CACHE_EXT = 176,29,1,0 %; macro T13$V_FS82_MB1 = 176,30,1,0 %; macro T13$V_FS82_MB0 = 176,31,1,0 %; macro T13$R_FEATURE_SETS84 = 180,0,16,0 %; literal T13$S_FEATURE_SETS84 = 2; macro T13$V_FS84_MB1 = 180,14,1,0 %; macro T13$V_FS84_MB0 = 180,15,1,0 %; macro T13$R_COMMAND_SETS_ON85 = 182,0,32,0 %; literal T13$S_COMMAND_SETS_ON85 = 4; macro T13$V_SMART_ON = 182,0,1,0 %; macro T13$V_SECURITY_ON = 182,1,1,0 %; macro T13$V_REMOVABLE_ON = 182,2,1,0 %; macro T13$V_POWER_ON = 182,3,1,0 %; macro T13$V_PACKET_ON = 182,4,1,0 %; macro T13$V_WRITE_CACHE_ON = 182,5,1,0 %; macro T13$V_LOOKAHEAD_ON = 182,6,1,0 %; macro T13$V_RELEASE_INT_ON = 182,7,1,0 %; macro T13$V_SERVICE_INT_ON = 182,8,1,0 %; macro T13$V_DEVICE_RESET_ON = 182,9,1,0 %; macro T13$V_HOST_PROTECTED_ON = 182,10,1,0 %; macro T13$V_WRITE_BUFFER_ON = 182,12,1,0 %; macro T13$V_READ_BUFFER_ON = 182,13,1,0 %; macro T13$V_NOP_ON = 182,14,1,0 %; macro T13$V_MICROCODE_ON = 182,16,1,0 %; macro T13$V_DMA_QUEUED_ON = 182,17,1,0 %; macro T13$V_CFA_ON = 182,18,1,0 %; macro T13$V_ADV_POWER_ON = 182,19,1,0 %; macro T13$V_MEDIA_STATUS_ON = 182,20,1,0 %; macro T13$V_PWRUP_STANDBY_ON = 182,21,1,0 %; macro T13$V_HOST_SPINUP_ON = 182,22,1,0 %; macro T13$V_RSVD_AREA_BOOT_ON = 182,23,1,0 %; macro T13$V_SET_MAX_SECURITY_ON = 182,24,1,0 %; macro T13$V_AUTO_ACCOUSTICS_ON = 182,25,1,0 %; macro T13$V_48B_ADDRESSING_ON = 182,26,1,0 %; macro T13$V_CONFIG_OVERLAY_ON = 182,27,1,0 %; macro T13$V_FLUSH_CACHE_ON = 182,28,1,0 %; macro T13$V_FLUSH_CACHE_EXT_ON = 182,29,1,0 %; macro T13$V_CS85_MB1_ON = 182,30,1,0 %; macro T13$V_CS85_MB0_ON = 182,31,1,0 %; macro T13$R_FEATURE_SETS_ON87 = 186,0,16,0 %; literal T13$S_FEATURE_SETS_ON87 = 2; macro T13$V_FS87_MB1 = 186,14,1,0 %; macro T13$V_FS87_MB0 = 186,15,1,0 %; macro T13$R_UL_DMA_MODE88 = 188,0,16,0 %; literal T13$S_UL_DMA_MODE88 = 2; macro T13$V_UL_DMA_MODE_0_OK = 188,0,1,0 %; macro T13$V_UL_DMA_MODE_1_OK = 188,1,1,0 %; macro T13$V_UL_DMA_MODE_2_OK = 188,2,1,0 %; macro T13$V_UL_DMA_MODE_0_ON = 188,8,1,0 %; macro T13$V_UL_DMA_MODE_1_ON = 188,9,1,0 %; macro T13$V_UL_DMA_MODE_2_ON = 188,10,1,0 %; macro T13$W_ERASE_TIME = 190,0,16,0 %; macro T13$W_ADV_ERASE_TIME = 192,0,16,0 %; macro T13$W_ADV_POWER = 194,0,16,0 %; macro T13$W_PWD_REVISION = 196,0,16,0 %; macro T13$R_HW_RESET_RESULTS = 198,0,16,0 %; literal T13$S_HW_RESET_RESULTS = 2; macro T13$V_HRR_D0_MB1 = 198,0,1,0 %; macro T13$V_HRR_D0_UNIT = 198,1,2,0 %; literal T13$S_HRR_D0_UNIT = 2; macro T13$V_HRR_D0_DIAG_OK = 198,3,1,0 %; macro T13$V_HRR_D0_PDIAG_OK = 198,4,1,0 %; macro T13$V_HRR_D0_DASP_OK = 198,5,1,0 %; macro T13$V_HRR_D0_CONFUSED = 198,6,1,0 %; macro T13$V_HRR_D1_MB1 = 198,7,1,0 %; macro T13$V_HRR_D1_UNIT = 198,8,2,0 %; literal T13$S_HRR_D1_UNIT = 2; macro T13$V_HRR_D1_PDIAG_OK = 198,10,1,0 %; macro T13$V_HRR_D1_RSVD = 198,11,1,0 %; macro T13$V_HRR_CBLID_HI = 198,12,1,0 %; macro T13$V_HRR_MB1 = 198,13,1,0 %; macro T13$V_HRR_MB0 = 198,14,1,0 %; macro T13$R_ACCOUSTIC_LEVEL = 200,0,16,0 %; literal T13$S_ACCOUSTIC_LEVEL = 2; macro T13$V_AL_CURRENT = 200,0,8,0 %; literal T13$S_AL_CURRENT = 8; macro T13$V_AL_RECOMMENDED = 200,8,8,0 %; literal T13$S_AL_RECOMMENDED = 8; macro T13$Q_48B_ADDR_LIMIT = 212,0,0,0 %; literal T13$S_48B_ADDR_LIMIT = 8; macro T13$R_RMS_FEATURES127 = 266,0,16,0 %; literal T13$S_RMS_FEATURES127 = 2; macro T13$V_RMS_SUPPORTED = 266,0,2,0 %; literal T13$S_RMS_SUPPORTED = 2; macro T13$R_SECURITY_STATUS128 = 268,0,16,0 %; literal T13$S_SECURITY_STATUS128 = 2; macro T13$V_SECURITY_SUPPORT = 268,0,1,0 %; macro T13$V_SECURITY_ENABLED = 268,1,1,0 %; macro T13$V_SECURITY_LOCKED = 268,2,1,0 %; macro T13$V_SECURITY_FROZEN = 268,3,1,0 %; macro T13$V_SECURITY_EXPIRED = 268,4,1,0 %; macro T13$V_SECURITY_ADV_ERASE = 268,5,1,0 %; macro T13$V_SECURITY_MAXIMUM = 268,8,1,0 %; macro T13$R_INTEGRITY_WORD255 = 522,0,16,0 %; literal T13$S_INTEGRITY_WORD255 = 2; macro T13$V_SIGNATURE = 522,0,8,0 %; literal T13$S_SIGNATURE = 8; macro T13$V_CHECKSUM = 522,8,8,0 %; literal T13$S_CHECKSUM = 8; literal T10$S_MPHDR10 = 8; macro T10$W_MPHDR10_DATA_LENGTH = 0,0,16,0 %; macro T10$B_MPHDR10_MEDIUM_TYPE = 2,0,8,0 %; macro T10$W_MPHDR10_BLOCK_LENGTH = 6,0,16,0 %; literal T10$S_MPHDR6 = 4; macro T10$B_MPHDR6_DATA_LENGTH = 0,0,8,0 %; macro T10$B_MPHDR6_MEDIUM_TYPE = 1,0,8,0 %; macro T10$B_MPHDR6_DEVICE = 2,0,8,0 %; macro T10$B_MPHDR6_BLOCK_LENGTH = 3,0,8,0 %; literal T10$S_MPBDG = 8; macro T10$B_MPBDG_DENSITY = 0,0,8,0 %; macro T10$X_MPBDG_BLOCKS = 1,0,24,0 %; literal T10$S_MPBDG_BLOCKS = 3; macro T10$B_MPBDG_RSVD = 4,0,8,0 %; macro T10$X_MPBDG_BLOCK_SIZE = 5,0,24,0 %; literal T10$S_MPBDG_BLOCK_SIZE = 3; literal T10$S_MPBDDA = 8; macro T10$L_MPBDDA_BLOCKS = 0,0,32,0 %; macro T10$B_MPBDDA_DENSITY = 4,0,8,0 %; macro T10$X_MPBDDA_BLOCK_SIZE = 5,0,24,0 %; literal T10$S_MPBDDA_BLOCK_SIZE = 3; literal T10$K_WRT_PACKET = 0; literal T10$K_WRT_TAO = 1; literal T10$K_WRT_SAO = 2; literal T10$K_WRT_DAO = 2; literal T10$K_WRT_RAW = 3; literal T10$K_QTM_2AUD_PE0 = 2; literal T10$K_QTM_2AUD_PE0_NOCOPY = 0; literal T10$K_QTM_2AUD_PE5015 = 3; literal T10$K_QTM_2AUD_PE5015_NOCOPY = 1; literal T10$K_QTM_4AUD_PE0 = 10; literal T10$K_QTM_4AUD_PE0_NOCOPY = 8; literal T10$K_QTM_4AUD_PE5015 = 11; literal T10$K_QTM_4AUD_PE5015_NOCOPY = 9; literal T10$K_QTM_DATA_UNINT = 6; literal T10$K_QTM_DATA_UNINT_NOCOPY = 4; literal T10$K_QTM_DATA_INCRE = 7; literal T10$K_QTM_DATA_INCRE_NOCOPY = 5; literal T10$M_QTM_COPYALLOWED = 2; literal T10$K_MSC_NO_B0 = 0; literal T10$K_MSC_MAX_B0 = 1; literal T10$K_MSC_RSVD = 16; literal T10$K_MSC_OK = 17; literal T10$K_BT_RAW_2352 = 0; literal T10$K_BT_RAW_2368 = 1; literal T10$K_BT_RAW_2448 = 2; literal T10$K_BT_RAW_2448_RAW = 3; literal T10$K_BT_MODE_1 = 8; literal T10$K_BT_MODE_2_2336 = 9; literal T10$K_BT_MODE_2_2048 = 10; literal T10$K_BT_MODE_2_2056 = 11; literal T10$K_BT_MODE_2_2324 = 12; literal T10$K_BT_MODE_2_2332 = 13; literal T10$K_SF_CDDA_CDROM = 0; literal T10$K_SF_CDI = 16; literal T10$K_SF_CDROMXA_DDCD = 32; literal T10$K_MP05_BASE_LENGTH = 50; literal T10$K_MP05_MAX_LENGTH = 54; literal T10$S_MP05 = 54; macro T10$R_MP05_HDR_FLAGS = 0,0,8,0 %; literal T10$S_MP05_HDR_FLAGS = 1; macro T10$V_MP05_HDR_MPCODE = 0,0,6,0 %; literal T10$S_MP05_HDR_MPCODE = 6; macro T10$V_MP05_HDR_PS = 0,7,1,0 %; macro T10$B_MP05_LENGTH = 1,0,8,0 %; macro T10$R_MP05_2_FLAGS = 2,0,8,0 %; literal T10$S_MP05_2_FLAGS = 1; macro T10$V_MP05_2_WRT_TYPE = 2,0,4,0 %; literal T10$S_MP05_2_WRT_TYPE = 4; macro T10$V_MP05_2_TEST_WR = 2,4,1,0 %; macro T10$V_MP05_2_LS_V = 2,5,1,0 %; macro T10$V_MP05_2_BUFE = 2,6,1,0 %; macro T10$R_MP05_3_FLAGS = 3,0,8,0 %; literal T10$S_MP05_3_FLAGS = 1; macro T10$V_MP05_3_TRK_MODE = 3,0,4,0 %; literal T10$S_MP05_3_TRK_MODE = 4; macro T10$V_MP05_3_COPYPROT = 3,4,1,0 %; macro T10$V_MP05_3_FIXEDPKT = 3,5,1,0 %; macro T10$V_MP05_3_MULTISESS = 3,6,2,0 %; literal T10$S_MP05_3_MULTISESS = 2; macro T10$R_MP05_4_FLAGS = 4,0,8,0 %; literal T10$S_MP05_4_FLAGS = 1; macro T10$V_MP05_4_BT_TYPE = 4,0,4,0 %; literal T10$S_MP05_4_BT_TYPE = 4; macro T10$B_MP05_LINK_SIZE = 5,0,8,0 %; macro T10$R_MP05_7_FLAGS = 7,0,8,0 %; literal T10$S_MP05_7_FLAGS = 1; macro T10$V_MP05_7_CODE = 7,0,6,0 %; literal T10$S_MP05_7_CODE = 6; macro T10$B_MP05_SESS_FORMAT = 8,0,8,0 %; macro T10$L_MP05_PKT_SIZE = 10,0,32,0 %; macro T10$W_MP05_AUDIO_PAUSE = 14,0,16,0 %; macro T10$X_MP05_MEDIA_CAT_NUM = 16,0,0,0 %; literal T10$S_MP05_MEDIA_CAT_NUM = 16; macro T10$X_MP05_ISRC = 32,0,0,0 %; literal T10$S_MP05_ISRC = 14; macro T10$X_MP05_SUBHEADER = 46,0,32,0 %; literal T10$S_MP05_SUBHEADER = 4; macro T10$X_MP05_VENDOR_DATA = 50,0,32,0 %; literal T10$S_MP05_VENDOR_DATA = 4; literal T10$S_MP1D = 10; macro T10$R_MP1D_HDR_FLAGS = 0,0,8,0 %; literal T10$S_MP1D_HDR_FLAGS = 1; macro T10$V_MP1D_HDR_MPCODE = 0,0,6,0 %; literal T10$S_MP1D_HDR_MPCODE = 6; macro T10$V_MP1D_HDR_PS = 0,7,1,0 %; macro T10$B_MP1D_LENGTH = 1,0,8,0 %; macro T10$R_MP1D_4_FLAGS = 4,0,8,0 %; literal T10$S_MP1D_4_FLAGS = 1; macro T10$V_MP1D_4_SWPP = 4,0,1,0 %; macro T10$V_MP1D_4_DISP = 4,1,1,0 %; macro T10$V_MP1D_4_TMOE = 4,2,1,0 %; macro T10$V_MP1D_4_G3ENABLE = 4,3,1,0 %; macro T10$W_MP1D_G1TIMEOUT = 6,0,16,0 %; macro T10$W_MP1D_G2TIMEOUT = 8,0,16,0 %; literal T10$K_LMT_CADDY = 0; literal T10$K_LMT_TRAY = 1; literal T10$K_LMT_POPUP = 2; literal T10$K_LMT_RSVD011 = 3; literal T10$K_LMT_CHANGER = 4; literal T10$K_LMT_MAGAZINE = 5; literal T10$K_LMT_RSVD110 = 6; literal T10$K_LMT_RSVD111 = 7; literal T10$K_SPEED_X1 = 1723; literal T10$K_SPEED_XMAX = 65535; literal T10$K_MP2A_X0001 = 1722; literal T10$K_MP2A_X0002 = 3445; literal T10$K_MP2A_X0004 = 6890; literal T10$K_MP2A_X0008 = 13781; literal T10$K_MP2A_X0010 = 17226; literal T10$K_MP2A_X0012 = 20671; literal T10$K_MP2A_X0016 = 27562; literal T10$K_MP2A_X0020 = 34453; literal T10$K_MP2A_X0024 = 41343; literal T10$K_MP2A_X0032 = 55125; literal T10$K_MP2A_X0040 = 68906; literal T10$K_MP2A_X0048 = 82687; literal T10$K_MP2A_X0052 = 89578; literal T10$K_MP2A_X0056 = 96468; literal T10$K_MP2A_X0064 = 110250; literal T10$K_MP2A_RC_CLV = 0; literal T10$K_MP2A_RC_CAV = 1; literal T10$S_MP2A = 1056; macro T10$R_MP2A_HDR_FLAGS = 0,0,8,0 %; literal T10$S_MP2A_HDR_FLAGS = 1; macro T10$V_MP2A_HDR_MPCODE = 0,0,6,0 %; literal T10$S_MP2A_HDR_MPCODE = 6; macro T10$V_MP2A_HDR_PS = 0,7,1,0 %; macro T10$B_MP2A_LENGTH = 1,0,8,0 %; macro T10$R_MP2A_2_FLAGS = 2,0,8,0 %; literal T10$S_MP2A_2_FLAGS = 1; macro T10$V_MP2A_2_CDR_RD = 2,0,1,0 %; macro T10$V_MP2A_2_CDRW_RD = 2,1,1,0 %; macro T10$V_MP2A_2_METHOD_2 = 2,2,1,0 %; macro T10$V_MP2A_2_DVDROM_RD = 2,3,1,0 %; macro T10$V_MP2A_2_DVDR_RD = 2,4,1,0 %; macro T10$V_MP2A_2_DVDRAM_RD = 2,5,1,0 %; macro T10$R_MP2A_3_FLAGS = 3,0,8,0 %; literal T10$S_MP2A_3_FLAGS = 1; macro T10$V_MP2A_3_CDR_WR = 3,0,1,0 %; macro T10$V_MP2A_3_CDRW_WR = 3,1,1,0 %; macro T10$V_MP2A_3_TEST_WR = 3,2,1,0 %; macro T10$V_MP2A_3_DVDR_WR = 3,4,1,0 %; macro T10$V_MP2A_3_DVDRAM_WR = 3,5,1,0 %; macro T10$R_MP2A_4_FLAGS = 4,0,8,0 %; literal T10$S_MP2A_4_FLAGS = 1; macro T10$V_MP2A_4_PLAY = 4,0,1,0 %; macro T10$V_MP2A_4_COMPOSITE = 4,1,1,0 %; macro T10$V_MP2A_4_DIGITAL_1 = 4,2,1,0 %; macro T10$V_MP2A_4_DIGITAL_2 = 4,3,1,0 %; macro T10$V_MP2A_4_MODE2_FORM1 = 4,4,1,0 %; macro T10$V_MP2A_4_MODE2_FORM2 = 4,5,1,0 %; macro T10$V_MP2A_4_MULTISESSION = 4,6,1,0 %; macro T10$V_MP2A_4_BUF = 4,7,1,0 %; macro T10$R_MP2A_5_FLAGS = 5,0,8,0 %; literal T10$S_MP2A_5_FLAGS = 1; macro T10$V_MP2A_5_SUPPORTED = 5,0,1,0 %; macro T10$V_MP2A_5_ACCURATE = 5,1,1,0 %; macro T10$V_MP2A_5_RW = 5,2,1,0 %; macro T10$V_MP2A_5_CORRECTED = 5,3,1,0 %; macro T10$V_MP2A_5_C2POINTERS = 5,4,1,0 %; macro T10$V_MP2A_5_ISRC = 5,5,1,0 %; macro T10$V_MP2A_5_UPC = 5,6,1,0 %; macro T10$V_MP2A_5_BARCODE = 5,7,1,0 %; macro T10$R_MP2A_6_FLAGS = 6,0,8,0 %; literal T10$S_MP2A_6_FLAGS = 1; macro T10$V_MP2A_6_LOCK = 6,0,1,0 %; macro T10$V_MP2A_6_STATE = 6,1,1,0 %; macro T10$V_MP2A_6_PREVENT = 6,2,1,0 %; macro T10$V_MP2A_6_EJECT = 6,3,1,0 %; macro T10$V_MP2A_6_RSVD4 = 6,4,1,0 %; macro T10$V_MP2A_6_LOADMECHTYPE = 6,5,3,0 %; literal T10$S_MP2A_6_LOADMECHTYPE = 3; macro T10$R_MP2A_7_FLAGS = 7,0,8,0 %; literal T10$S_MP2A_7_FLAGS = 1; macro T10$V_MP2A_7_SEPVOL = 7,0,1,0 %; macro T10$V_MP2A_7_SEPMUTE = 7,1,1,0 %; macro T10$V_MP2A_7_PRESENT = 7,2,1,0 %; macro T10$V_MP2A_7_SSS = 7,3,1,0 %; macro T10$V_MP2A_7_SIDECHANGE = 7,4,1,0 %; macro T10$V_MP2A_7_RW_LEADIN = 7,5,1,0 %; macro T10$V_MP2A_7_RSVD6 = 7,6,2,0 %; literal T10$S_MP2A_7_RSVD6 = 2; macro T10$W_MP2A_MAX_READ = 8,0,16,0 %; macro T10$W_MP2A_VOLLEVELS = 10,0,16,0 %; macro T10$W_MP2A_BUFSIZE = 12,0,16,0 %; macro T10$W_MP2A_CURR_READ = 14,0,16,0 %; macro T10$B_MP2A_RSVD16 = 16,0,8,0 %; macro T10$R_MP2A_17_FLAGS = 17,0,8,0 %; literal T10$S_MP2A_17_FLAGS = 1; macro T10$V_MP2A_17_BCKF = 17,1,1,0 %; macro T10$V_MP2A_17_RCK = 17,2,1,0 %; macro T10$V_MP2A_17_LSBF = 17,3,1,0 %; macro T10$V_MP2A_17_LENGTH = 17,4,2,0 %; literal T10$S_MP2A_17_LENGTH = 2; macro T10$V_MP2A_17_RSVD6 = 17,6,2,0 %; literal T10$S_MP2A_17_RSVD6 = 2; macro T10$W_MP2A_MAX_WRITE = 18,0,16,0 %; macro T10$W_MP2A_CURR_WRITE = 20,0,16,0 %; macro T10$W_MP2A_COPYMGMT = 22,0,16,0 %; macro T10$B_MP2A_RSVD240 = 24,0,8,0 %; macro T10$B_MP2A_RSVD250 = 25,0,8,0 %; macro T10$B_MP2A_RSVD260 = 26,0,8,0 %; macro T10$R_MP2A_27_FLAGS = 27,0,8,0 %; literal T10$S_MP2A_27_FLAGS = 1; macro T10$V_MP2A_27_ROTCON = 27,0,2,0 %; literal T10$S_MP2A_27_ROTCON = 2; macro T10$W_MP2A_CURR_WRITE_UNIT = 28,0,16,0 %; macro T10$W_MP2A_WRTSPD_SIZE = 30,0,16,0 %; macro T10$R_MP2A_WRTSPD = 32,0,0,0 %; literal T10$S_MP2A_WRTSPD = 1024; macro T10$B_MP2A_WS_RSVD0 = 32,0,8,0 %; macro T10$R_MP2A_WS_ROTCTRL = 33,0,8,0 %; literal T10$S_MP2A_WS_ROTCTRL = 1; macro T10$V_MP2A_WS_ROTCON = 33,0,3,0 %; literal T10$S_MP2A_WS_ROTCON = 3; macro T10$W_MP2A_WRITE_SPEED = 34,0,16,0 %; literal T10$S_MP3F = 1; macro T10$R_MP3F_HDR_FLAGS = 0,0,8,0 %; literal T10$S_MP3F_HDR_FLAGS = 1; macro T10$V_MP3F_HDR_MPCODE = 0,0,6,0 %; literal T10$S_MP3F_HDR_MPCODE = 6; macro T10$V_MP3F_HDR_PS = 0,7,1,0 %; !*** MODULE $TASTDEF *** ! ! TERMINAL AST PACKET. THIS STRUCTURE IS USED BY TERMINAL SERVICES TO ! DELIVER OUT OF BAND CHARACTER ASTS. ! literal TAST$M_MASK_DSBL = %X'1'; literal TAST$M_INCLUDE = %X'2'; literal TAST$M_ONE_SHOT = %X'4'; literal TAST$M_BUSY = %X'8'; literal TAST$M_LOST = %X'10'; literal TAST$M_ABORT = %X'20'; literal TAST$K_LENGTH = 60; literal TAST$C_LENGTH = 60; literal TAST$M_ABO = %X'4000'; literal TAST$M_INC = %X'8000'; literal TAST$S_TAST = 64; macro TAST$L_FLINK = 36,0,32,1 %; ! FORWARD LINK macro TAST$L_AST = 40,0,32,1 %; ! SAVED AST ADDRESS macro TAST$L_ASTPRM = 44,0,32,0 %; ! SAVED AST PARAMETER macro TAST$L_PID = 48,0,32,0 %; ! SAVED PID macro TAST$B_RMOD = 52,0,8,0 %; ! SAVED RMOD macro TAST$B_CTRL = 53,0,8,0 %; ! CONTROL FIELD macro TAST$V_MASK_DSBL = 53,0,1,0 %; ! DISABLE MASK PROCESSING macro TAST$V_INCLUDE = 53,1,1,0 %; ! INCLUDE CHARACTER macro TAST$V_ONE_SHOT = 53,2,1,0 %; ! ONE SHOT AST macro TAST$V_BUSY = 53,3,1,0 %; ! BLOCK BUSY macro TAST$V_LOST = 53,4,1,0 %; ! AST LOST macro TAST$V_ABORT = 53,5,1,0 %; ! ABORT I/O macro TAST$W_CHAN = 54,0,16,0 %; ! CHANNEL macro TAST$L_MASK = 56,0,32,0 %; ! OUT OF BAND MASK macro TAST$R_STATUS_BITS = 60,0,16,0 %; macro TAST$V_FILL = 60,0,14,0 %; literal TAST$S_FILL = 14; ! First byte and spares macro TAST$V_ABO = 60,14,1,0 %; ! ABORT flag macro TAST$V_INC = 60,15,1,0 %; ! INCLUDE flag literal TAST$S_TASTDEF = 64; ! Old size name, synonym for TAST$S_TAST !*** MODULE $TIEDEF *** literal TIE$K_GSMATCH = 0; literal TIE$K_PROC_KIND = 1; literal TIE$K_CALL_PROC = 2; literal TIE$K_NATIVE_TO_TRANSLATED = 3; literal TIE$K_NATIVE_TO_TRANSLATED_BP = 4; literal TIE$K_LONGJMP_RESTORE = 5; literal TIE$K_GET_INVO_HANDLE_64 = 6; !*** MODULE $TITANDEF *** ! ! Version: 'X-6' ! ! ! ************************************************************************ ! * ! Copyright 2000 Compaq Computer Corporation * ! * ! COMPAQ Registered in U.S. Patent and Trademark Office. * ! * ! Confidential computer software. Valid license from Compaq or * ! authorized sublicensor required for possession, use or copying. * ! Consistent with FAR 12.211 and 12.212, Commercial Computer Software, * ! Computer Software Documentation, and Technical Data for Commercial * ! Items are licensed to the U.S. Government under vendor's standard * ! commercial license. * ! * ! Compaq shall not be liable for technical or editorial errors or * ! omissions contained herein. The information in this document is * ! subject to change without notice. * ! * ! ************************************************************************ ! ! FACILITY: OpenVMS AXP System Macro Libraries ! ! ABSTRACT: ! ! This file defines the control and status registers of the Titan Chip ! Set (an extemsion of Tsunami), designed for use in EV6-8 based platforms. ! ! Because of the disparities in the address spaces for the various chips ! in the Titan Chip Set, it structure is defined as three distinct data stuctures, ! C chip (TITAN_C), D chip (TITAN_D), and the P chip (TITAN_P). There is one C Chip ! (C4+ - up to four processors), as many as eight D Chips (D+) and as many as two P Chips, ! (the PA-chip [PCI + AGP] and the PP-chip [2 PCIs] - each of these P-Chips ! supports 2 busses) This simplifies the definition, but puts an extra burden on ! the programmer to use the correct base addresses for the three chips. ! ! The following table shows the regions for the Titan Chip Set address ! space. ! ! -------------------------------------------------------------------- ! C chip Address Space ! -------------------------------------------------------------------- ! 801 0000 0000 1 GB TIG Bus, addr<5:0> = 0, single byte valid in ! quadword access, 16 MB accessible ! 801 a000 0000 256 MB C chip CSRs, addr<5:0> = 0, quadword access ! -------------------------------------------------------------------- ! ! -------------------------------------------------------------------- ! D chip Address Space ! -------------------------------------------------------------------- ! 801 b000 0000 256 MB D chip CSRs, addr<5:0> = 0, all eight bytes in ! quadword access must be identical. ! -------------------------------------------------------------------- ! ! -------------------------------------------------------------------- ! P chip-0 Address Space ! -------------------------------------------------------------------- ! 801 8000 0000 256 MB P chip CSRs, addr<5:0> = 0, quadword access ! ! 800 0000 0000 4 GB GPCI Memory ! 801 f800 0000 64 MB GPCI IACK/Special ! 801 fc00 0000 32 MB GPCI IO ! 801 fe00 0000 16 MB GPCI config space ! ! 804 0000 0000 4 GB APCI Memory ! 805 f800 0000 64 MB APCI IACK/Special ! 805 fc00 0000 32 MB APCI IO ! 805 fe00 0000 16 MB APCI config space ! -------------------------------------------------------------------- ! ! -------------------------------------------------------------------- ! P chip-1 Address Space ! -------------------------------------------------------------------- ! 803 8000 0000 256 MB P chip CSRs, addr<5:0> = 0, quadword access ! ! 802 0000 0000 4 GB GPCI Memory ! 803 f800 0000 64 MB GPCI IACK/Special ! 803 fc00 0000 32 MB GPCI IO ! 803 fe00 0000 16 MB GPCI config space ! ! 806 0000 0000 4 MB APCI Memory ! 807 f800 0000 64 MB APCI IACK/Special ! 807 fc00 0000 32 MB APCI IO ! 807 fe00 0000 16 MB APCI config space ! ! ! -------------------------------------------------------------------- ! ! AUTHOR: ! ! Walt Arbo 03-Jan-2000 ! ! MODIFIED BY: ! ! X-6 GBH Gary Huff 26-Sep-2001 ! Add AGP bit definitions to apctl. ! ! X-5 TLC Tony Camuso 29-Aug-2001 ! Bug: without MCTL register at 801.A000.0500, as in Tsunami, ! displacement for for MPR3 register must be %xC0, not %x80. ! ! X-4 WDA W.D. Arbo 26-Apr-2001 ! Add overlays to the Pchip for AGPERROR, AGPERREN, ! AGPERRSET and AGPLASTWR. They mirror SERROR, SERREN, ! SERRSET and Reserved. It all depends on whether the Pchip ! definition maps Pchip's 0 and 1 (SERROR etc.) or 2 and 3 ! (AGPERROR etc). ! ! X-3 WDA W.D. Arbo 15-May-2000 ! When I put this file into LIB, it had duplicate ! symbol definitions with TSUNAMIDEF.SDL for things like ! C_CHIP (duh!). Put TITAN into all the names (TITAN_C ! for C_CHIP etc.) ! ! X-2 WDA W.D. Arbo 10-May-2000 ! A few fixes. ! ! X-1 WDA W.D. Arbo 03-Jan-2000 ! Based on Tony Camuso's work on Tsunami support ! (TSUNAMIDEF.SDL). ! ! -- ! The maximum number of CPUs supported by the Titan chipset ! literal TITAN$K_MAX_CPU = 4; literal TITAN$C_MAX_CPU = 4; ! ! Since SDL currently doesn't support constants greater 2**32, the high-order ! bits (%X80x) have their own constants defined. ! ! Titan Chip Set CSR base addresses <63:32> (High longword) ! =========================================================== ! literal TITAN$L_C_CHIP_H = 2049; literal TITAN$L_D_CHIP_H = 2049; ! literal TITAN$L_P0_CHIP_CSR_H = 2049; literal TITAN$L_P0_CHIP_GMEM_H = 2048; literal TITAN$L_P0_CHIP_GIO_H = 2049; literal TITAN$L_P0_CHIP_GCONFIG_H = 2049; literal TITAN$L_P0_CHIP_AMEM_H = 2052; literal TITAN$L_P0_CHIP_AIO_H = 2053; literal TITAN$L_P0_CHIP_ACONFIG_H = 2053; ! literal TITAN$L_P1_CHIP_CSR_H = 2051; literal TITAN$L_P1_CHIP_GMEM_H = 2050; literal TITAN$L_P1_CHIP_GIO_H = 2051; literal TITAN$L_P1_CHIP_GCONFIG_H = 2051; literal TITAN$L_P1_CHIP_AMEM_H = 2054; literal TITAN$L_P1_CHIP_AIO_H = 2055; literal TITAN$L_P1_CHIP_ACONFIG_H = 2055; ! ! ! Titan Chip Set CSR base addresses <31:0> (Low longword) ! ========================================================= ! literal TITAN$L_C_CHIP_L = -1610612736; ! Cchip literal TITAN$L_D_CHIP_L = -1342177280; ! Dchip ! ! ! P-Chip ! ------ literal TITAN$L_P_CHIP_CSR_0_L = -2147483648; literal TITAN$L_P_CHIP_CSR_1_L = -2147479552; literal TITAN$L_P_CHIP_MEM_L = 0; literal TITAN$L_P_CHIP_IO_L = -67108864; literal TITAN$L_P_CHIP_IACK_L = -134217728; literal TITAN$L_P_CHIP_CONFIG_L = -33554432; ! ! ! ************************************************************************** ! ! Titan Chip Set Structures ! ! ************************************************************************** ! ! ========================================================================== ! ! C-CHIP Structure ! ========================================================================== literal TITAN_C$S_TITAN_C = 8192; ! ! 801.A000.000 ! ! CSC - C-Chip System Configuration Register ! macro TITAN_C$IQ_CSC = 0,0,0,0 %; literal TITAN_C$S_CSC = 8; ! ! 801.A000.0040 ! ! MTR - C-Chip Memory Timing Register ! macro TITAN_C$IQ_MTR = 64,0,0,0 %; literal TITAN_C$S_MTR = 8; ! ! 801.A000.0080 ! ! MISC - C-Chip Miscellaneous Register ! macro TITAN_C$IQ_MISC = 128,0,0,0 %; literal TITAN_C$S_MISC = 8; ! ! 801.A000.00C0 ! ! MPD - C-Chip Memory Presence Detect ! macro TITAN_C$IQ_MPD = 192,0,0,0 %; literal TITAN_C$S_MPD = 8; ! ! 801.A000.0100 ! ! AAR0 - C-Chip Array Address Register 0 ! macro TITAN_C$IQ_AAR0 = 256,0,0,0 %; literal TITAN_C$S_AAR0 = 8; ! ! 801.A000.0140 ! ! AAR1 - C-Chip Array Address Register 1 ! macro TITAN_C$IQ_AAR1 = 320,0,0,0 %; literal TITAN_C$S_AAR1 = 8; ! ! 801.A000.0180 ! ! AAR2 - C-Chip Array Address Register 2 ! macro TITAN_C$IQ_AAR2 = 384,0,0,0 %; literal TITAN_C$S_AAR2 = 8; ! ! 801.A000.01C0 ! ! AAR3 - C-Chip Array Address Register 3 ! macro TITAN_C$IQ_AAR3 = 448,0,0,0 %; literal TITAN_C$S_AAR3 = 8; ! ! 801.A000.0200 ! ! DIM0 - C-Chip Device Interrupt Mask Register 0 ! macro TITAN_C$IQ_DIM0 = 512,0,0,0 %; literal TITAN_C$S_DIM0 = 8; ! ! 801.A000.0240 ! ! DIM1 - C-Chip Device Interrupt Mask Register 1 ! macro TITAN_C$IQ_DIM1 = 576,0,0,0 %; literal TITAN_C$S_DIM1 = 8; ! ! 801.A000.0280 ! ! DIR0 - C-Chip Device Interrupt Request Register ! macro TITAN_C$IQ_DIR0 = 640,0,0,0 %; literal TITAN_C$S_DIR0 = 8; ! ! 801.A000.02C0 ! ! DIR1 - C-Chip Device Interrupt Request Register ! macro TITAN_C$IQ_DIR1 = 704,0,0,0 %; literal TITAN_C$S_DIR1 = 8; ! ! 801.A000.0300 ! ! DRIR - C-Chip Raw Interrupt Request Register ! macro TITAN_C$IQ_DRIR = 768,0,0,0 %; literal TITAN_C$S_DRIR = 8; ! ! 801.A000.0340 ! ! PRBEN - C-Chip Probe Enable Register ! macro TITAN_C$IQ_PRBEN = 832,0,0,0 %; literal TITAN_C$S_PRBEN = 8; ! ! 801.A000.0380 ! ! IIC0 - C-Chip Interval Ignore Count Register 0 ! macro TITAN_C$IQ_IIC0 = 896,0,0,0 %; literal TITAN_C$S_IIC0 = 8; ! ! 801.A000.03C0 ! ! IIC1 - C-Chip Interval Ignore Count Register 1 ! macro TITAN_C$IQ_IIC1 = 960,0,0,0 %; literal TITAN_C$S_IIC1 = 8; ! ! 801.A000.0400 ! ! MPR0 - C-Chip Memory Programming Register 0 ! macro TITAN_C$IQ_MPR0 = 1024,0,0,0 %; literal TITAN_C$S_MPR0 = 8; ! ! 801.A000.0440 ! ! MPR1 - C-Chip Memory Programming Register 1 ! macro TITAN_C$IQ_MPR1 = 1088,0,0,0 %; literal TITAN_C$S_MPR1 = 8; ! ! 801.A000.0480 ! ! MPR2 - C-Chip Memory Programming Register 2 ! macro TITAN_C$IQ_MPR2 = 1152,0,0,0 %; literal TITAN_C$S_MPR2 = 8; ! ! 801.A000.04C0 ! ! MPR3 - C-Chip Memory Programming Register 3 ! macro TITAN_C$IQ_MPR3 = 1216,0,0,0 %; literal TITAN_C$S_MPR3 = 8; ! ! 801.A000.0580 ! ! TTR - C-Chip TIG Bus Timing Register ! macro TITAN_C$IQ_TTR = 1408,0,0,0 %; literal TITAN_C$S_TTR = 8; ! ! 801.A000.05C0 ! ! TDR - C-Chip TIG Bus Device Timing Register ! macro TITAN_C$IQ_TDR = 1472,0,0,0 %; literal TITAN_C$S_TDR = 8; ! ! 801.A000.0600 ! ! DIM2 - C-Chip Device Interrupt Mask Register 2 ! macro TITAN_C$IQ_DIM2 = 1536,0,0,0 %; literal TITAN_C$S_DIM2 = 8; ! ! 801.A000.0640 ! ! DIM3 - C-Chip Device Interrupt Mask Register 3 ! macro TITAN_C$IQ_DIM3 = 1600,0,0,0 %; literal TITAN_C$S_DIM3 = 8; ! ! 801.A000.0680 ! ! DIR2 - C-Chip Device Interrupt Request Register 2 ! macro TITAN_C$IQ_DIR2 = 1664,0,0,0 %; literal TITAN_C$S_DIR2 = 8; ! ! 801.A000.06C0 ! ! DIR3 - C-Chip Device Interrupt Request Register 3 ! macro TITAN_C$IQ_DIR3 = 1728,0,0,0 %; literal TITAN_C$S_DIR3 = 8; ! ! 801.A000.0700 ! ! IIC2 - C-Chip Interval Ignore Count Register 2 ! macro TITAN_C$IQ_IIC2 = 1792,0,0,0 %; literal TITAN_C$S_IIC2 = 8; ! ! 801.A000.0740 ! ! IIC3 - C-Chip Interval Ignore Count Register 3 ! macro TITAN_C$IQ_IIC3 = 1856,0,0,0 %; literal TITAN_C$S_IIC3 = 8; ! ! 801.A000.A780 ! ! PWR - C-Chip Power Management Control ! macro TITAN_C$IQ_PWR = 1920,0,0,0 %; literal TITAN_C$S_PWR = 8; ! ! 801.A000.0C00 ! ! CMONCTLA - C-Chip Monitor Control A ! macro TITAN_C$IQ_CMONCTLA = 3072,0,0,0 %; literal TITAN_C$S_CMONCTLA = 8; ! ! 801.A000.0C40 ! ! CMONCTLB - C-Chip Monitor Control B ! macro TITAN_C$IQ_CMONCTLB = 3136,0,0,0 %; literal TITAN_C$S_CMONCTLB = 8; ! ! 801.A000.0C80 ! ! CMONCNT01- C-Chip Monitor Counter 01 ! macro TITAN_C$IQ_CMONCNT01 = 3200,0,0,0 %; literal TITAN_C$S_CMONCNT01 = 8; ! ! 801.A000.0CC0 ! ! CMONCNT23- C-Chip Monitor Counter 23 ! macro TITAN_C$IQ_CMONCNT23 = 3264,0,0,0 %; literal TITAN_C$S_CMONCNT23 = 8; ! ! 801.A000.0D00 ! ! CPEN- C-Chip (Reserved for future use) ! macro TITAN_C$IQ_CPEN = 3328,0,0,0 %; literal TITAN_C$S_CPEN = 8; ! ! ! ! ========================================================================== ! ! D-CHIP Structure ! ! NOTE: All the registers in this structure are abstracted as 64-bit entities. ! Therefore, they MUST be accessed and manipulated as quadwords and with ! quadwords. ! ! ========================================================================== literal TITAN_D$S_TITAN_D = 256; ! ! 801.B000.0800 ! ! DSC - D-Chip System Configuration Register ! macro TITAN_D$IQ_DSC = 0,0,0,0 %; literal TITAN_D$S_DSC = 8; ! ! 801.B000.0840 ! ! STR - D-Chip System Timing Register ! macro TITAN_D$IQ_STR = 64,0,0,0 %; literal TITAN_D$S_STR = 8; ! ! 801.B000.0880 ! ! DREV - D-Chip System Configuration Register ! macro TITAN_D$IQ_DREV = 128,0,0,0 %; literal TITAN_D$S_DREV = 8; ! ! ! 801.B000.08C0 ! ! DSC2 - D-Chip (Reserved for future use) ! macro TITAN_D$IQ_DSC2 = 192,0,0,0 %; literal TITAN_D$S_DSC2 = 8; ! ! ! ! ! ========================================================================== ! ! P chip Structure - These are the common registers (G and A) of the ! two halves of a PAchip or a PPchip. Remember that hose 2 or hose 3 could ! be an AGP bus. ! ! The four PCI chips have base address as follows: ! PCI 0 Pchip 0 Hose 0 G-port 801.8000.0000 ! PCI 1 Pchip 1 Hose 1 G-port 803.8000.0000 ! PCI 2 Pchip 0 Hose 2 A-port 801.8000.1000 ! PCI 3 Pchip 1 Hose 3 A-port 803.8000.1000 ! ! ========================================================================== literal TITAN_P$S_TITAN_P = 2056; ! ! 80x.8000.0000 ! ! WSBA0 - P-CHip Window Space Base Address Register 0 ! macro TITAN_P$IQ_WSBA0 = 0,0,0,0 %; literal TITAN_P$S_WSBA0 = 8; ! ! 80x.8000.0040 ! ! WSBA1 - P-CHip Window Space Base Address Register 1 ! macro TITAN_P$IQ_WSBA1 = 64,0,0,0 %; literal TITAN_P$S_WSBA1 = 8; ! ! 80x.8000.0080 ! ! WSBA2 - P-CHip Window Space Base Address Register 2 ! macro TITAN_P$IQ_WSBA2 = 128,0,0,0 %; literal TITAN_P$S_WSBA2 = 8; ! ! 80x.8000.00C0 ! ! WSBA3 - P-CHip Window Space Base Address Register 3 ! macro TITAN_P$IQ_WSBA3 = 192,0,0,0 %; literal TITAN_P$S_WSBA3 = 8; ! ! 80x.8000.0100 ! ! WSM0 - P-Chip Window Space Mask Register 0 ! macro TITAN_P$IQ_WSM0 = 256,0,0,0 %; literal TITAN_P$S_WSM0 = 8; ! ! 80x.8000.0140 ! ! WSM1 - P-Chip Window Space Mask Register 1 ! macro TITAN_P$IQ_WSM1 = 320,0,0,0 %; literal TITAN_P$S_WSM1 = 8; ! ! 80x.8000.0180 ! ! WSM2 - P-Chip Window Space Mask Register 2 ! macro TITAN_P$IQ_WSM2 = 384,0,0,0 %; literal TITAN_P$S_WSM2 = 8; ! ! 80x.8000.01C0 ! ! WSM3 - P-Chip Window Space Mask Register 3 ! macro TITAN_P$IQ_WSM3 = 448,0,0,0 %; literal TITAN_P$S_WSM3 = 8; ! ! 80x.8000.0200 ! ! TBA0 - P-Chip Translated Base Address Register 0 ! macro TITAN_P$IQ_TBA0 = 512,0,0,0 %; literal TITAN_P$S_TBA0 = 8; ! ! 80x.8000.0240 ! ! TBA1 - P-Chip Translated Base Address Register 1 ! macro TITAN_P$IQ_TBA1 = 576,0,0,0 %; literal TITAN_P$S_TBA1 = 8; ! ! 80x.8000.0280 ! ! TBA2 - P-Chip Translated Base Address Register 2 ! macro TITAN_P$IQ_TBA2 = 640,0,0,0 %; literal TITAN_P$S_TBA2 = 8; ! ! 80x.8000.02C0 ! ! TBA3 - P-Chip Translated Base Address Register 3 ! macro TITAN_P$IQ_TBA3 = 704,0,0,0 %; literal TITAN_P$S_TBA3 = 8; ! ! 80x.8000.0300 ! ! PCTL - P-Chip Control Register ! macro TITAN_P$IQ_PCTL = 768,0,0,0 %; literal TITAN_P$S_PCTL = 8; ! ! 80x.8000.0340 ! ! PLAT - P-Chip Master Latency Register ! macro TITAN_P$IQ_PLAT = 832,0,0,0 %; literal TITAN_P$S_PLAT = 8; ! ! 80x.8000.0400 ! ! SERROR - P-Chip System Error Register ! macro TITAN_P$IQ_SERROR = 1024,0,0,0 %; literal TITAN_P$S_SERROR = 8; macro TITAN_P$IQ_AGPERROR = 1024,0,0,0 %; literal TITAN_P$S_AGPERROR = 8; ! ! 80x.8000.0440 ! ! SERREN - P-Chip System Error Enable Register ! macro TITAN_P$IQ_SERREN = 1088,0,0,0 %; literal TITAN_P$S_SERREN = 8; macro TITAN_P$IQ_AGPERREN = 1088,0,0,0 %; literal TITAN_P$S_AGPERREN = 8; ! ! 80x.8000.0480 ! ! SERRSET - P-Chip System Error Set Register ! macro TITAN_P$IQ_SERRSET = 1152,0,0,0 %; literal TITAN_P$S_SERRSET = 8; macro TITAN_P$IQ_AGPERRSET = 1152,0,0,0 %; literal TITAN_P$S_AGPERRSET = 8; ! ! 80x.8000.04C0 ! ! AGPLASTWR - P-Chip Last Write Register ! macro TITAN_P$IQ_AGPLASTWR = 1216,0,0,0 %; literal TITAN_P$S_AGPLASTWR = 8; ! ! 80x.8000.0500 ! ! PERROR - P-Chip Error Register ! macro TITAN_P$IQ_PERROR = 1280,0,0,0 %; literal TITAN_P$S_PERROR = 8; ! ! 80x.8000.0540 ! ! PERREN - P-Chip Error Enable Register ! macro TITAN_P$IQ_PERREN = 1344,0,0,0 %; literal TITAN_P$S_PERREN = 8; ! ! 80x.8000.0580 ! ! PERRSET - P-Chip Error Set Register ! macro TITAN_P$IQ_PERRSET = 1408,0,0,0 %; literal TITAN_P$S_PERRSET = 8; ! ! 80x.8000.0600 ! ! TLBIV - P-Chip Translation Buffer Invalidate Virtual Register ! macro TITAN_P$IQ_TLBIV = 1536,0,0,0 %; literal TITAN_P$S_TLBIV = 8; ! ! 80x.8000.0640 ! ! TLBIA - P-Chip Translation Buffer Invalidate all Register ! macro TITAN_P$IQ_TLBIA = 1600,0,0,0 %; literal TITAN_P$S_TLBIA = 8; ! ! 80x.8000.0700 ! ! SCTL - P-Chip System Control Register ! macro TITAN_P$IQ_SCTL = 1792,0,0,0 %; literal TITAN_P$S_SCTL = 8; ! ! 80x.8000.0800 ! ! SPRST - Software PCI Reset Register ! macro TITAN_P$IQ_SPRST = 2048,0,0,0 %; literal TITAN_P$S_SPRST = 8; ! ************************************************************************** ! ! Bit Definitions for the Titan Chip Set Registers. Since many of these definitions ! are not used, I deleted definitions for Tsunami-only registers and updated Titan ones, but ! did not add any new Titan ones. ! ! ************************************************************************** ! ========================================================================== ! ! C-Chip Registers ! ! ========================================================================== ! ! ! Titan CSC - C-Chip System Configuration Register ! literal TITAN_CSC$M_BC = %X'3'; literal TITAN_CSC$M_C0CFP = %X'4'; literal TITAN_CSC$M_C1CFP = %X'8'; literal TITAN_CSC$M_SED = %X'30'; literal TITAN_CSC$M_SFD = %X'40'; literal TITAN_CSC$M_FW = %X'80'; literal TITAN_CSC$M_AW = %X'100'; literal TITAN_CSC$M_IDDR = %X'E00'; literal TITAN_CSC$M_IDDW = %X'3000'; literal TITAN_CSC$M_P1P = %X'4000'; literal TITAN_CSC$M_RSVD_0 = %X'8000'; literal TITAN_CSC$M_DWTP = %X'30000'; literal TITAN_CSC$M_DWFP = %X'C0000'; literal TITAN_CSC$M_DRTP = %X'300000'; literal TITAN_CSC$M_RSVD_1 = %X'C00000'; literal TITAN_CSC$M_PME = %X'1000000'; literal TITAN_CSC$M_QPM = %X'2000000'; literal TITAN_CSC$M_FET = %X'C000000'; literal TITAN_CSC$M_QDI = %X'70000000'; literal TITAN_CSC$M_EFT = %X'80000000'; literal TITAN_CSC$M_FTI = %X'100000000'; literal TITAN_CSC$M_B1D = %X'200000000'; literal TITAN_CSC$M_B2D = %X'400000000'; literal TITAN_CSC$M_B3D = %X'800000000'; literal TITAN_CSC$M_TPQMMAX = %X'F000000000'; literal TITAN_CSC$M_FPQCMAX = %X'F0000000000'; literal TITAN_CSC$M_FPQPMAX = %X'F00000000000'; literal TITAN_CSC$M_PDTMAX = %X'7000000000000'; literal TITAN_CSC$M_AXD = %X'8000000000000'; literal TITAN_CSC$M_PRQMAX = %X'70000000000000'; literal TITAN_CSC$M_ADD4PTP = %X'80000000000000'; literal TITAN_CSC$M_PBQMAX = %X'700000000000000'; literal TITAN_CSC$M_RSVD_7 = %X'3800000000000000'; literal TITAN_CSC$M_NODQM = %X'4000000000000000'; literal TITAN_CSC$M_ISM = %X'8000000000000000'; literal TITAN_CSC$S_TITAN_CSC = 8; macro TITAN_CSC$IQ_DATA = 0,0,0,0 %; literal TITAN_CSC$S_DATA = 8; macro TITAN_CSC$IL_L = 0,0,32,0 %; macro TITAN_CSC$IL_H = 4,0,32,0 %; macro TITAN_CSC$V_BC = 0,0,2,0 %; literal TITAN_CSC$S_BC = 2; ! 1:0 Base Configuration macro TITAN_CSC$V_C0CFP = 0,2,1,0 %; ! 2 CPU 0 Clk Fwd Preset macro TITAN_CSC$V_C1CFP = 0,3,1,0 %; ! 3 CPU 1 Clk Fwd Preset macro TITAN_CSC$V_SED = 0,4,2,0 %; literal TITAN_CSC$S_SED = 2; ! 5:4 SysDC Extract Delay macro TITAN_CSC$V_SFD = 0,6,1,0 %; ! 6 SysDC Fill Delay macro TITAN_CSC$V_FW = 0,7,1,0 %; ! 7 available for firmware macro TITAN_CSC$V_AW = 0,8,1,0 %; ! 8 Array Width macro TITAN_CSC$V_IDDR = 0,9,3,0 %; literal TITAN_CSC$S_IDDR = 3; ! 11:9 Issue to Data Delay on read macro TITAN_CSC$V_IDDW = 0,12,2,0 %; literal TITAN_CSC$S_IDDW = 2; ! 13:12 Issue to Data Delay for all xactions macro TITAN_CSC$V_P1P = 0,14,1,0 %; ! 14 P-Chip 1 present macro TITAN_CSC$V_RSVD_0 = 0,15,1,0 %; ! 15 reserved macro TITAN_CSC$V_DWTP = 0,16,2,0 %; literal TITAN_CSC$S_DWTP = 2; ! 17:16 Min Dchip Delay from CPU to PAD bus macro TITAN_CSC$V_DWFP = 0,18,2,0 %; literal TITAN_CSC$S_DWFP = 2; ! 19:18 Min Dchip Delay from PADbus to CPU or Memory macro TITAN_CSC$V_DRTP = 0,20,2,0 %; literal TITAN_CSC$S_DRTP = 2; ! 21:20 Min Dchip Delay from Memory to PAD bus macro TITAN_CSC$V_RSVD_1 = 0,22,2,0 %; literal TITAN_CSC$S_RSVD_1 = 2; ! 23:22 reserved macro TITAN_CSC$V_PME = 0,24,1,0 %; ! 24 Page Mode Enable macro TITAN_CSC$V_QPM = 0,25,1,0 %; ! 25 Que Priority Mode macro TITAN_CSC$V_FET = 0,26,2,0 %; literal TITAN_CSC$S_FET = 2; ! 27:26 Fill to Extract Turnaround cycles macro TITAN_CSC$V_QDI = 0,28,3,0 %; literal TITAN_CSC$S_QDI = 3; ! 30:28 Que Drain Interval macro TITAN_CSC$V_EFT = 0,31,1,0 %; ! 31 Extract to Fill Turnaround cycles ! macro TITAN_CSC$V_FTI = 4,0,1,0 %; ! 32 Full Throttle Issue macro TITAN_CSC$V_B1D = 4,1,1,0 %; ! 33 Bypass 1 Issue Path Disable macro TITAN_CSC$V_B2D = 4,2,1,0 %; ! 34 Bypass 2 Issue Path Disable macro TITAN_CSC$V_B3D = 4,3,1,0 %; ! 35 Bypass 3 Issue Path Disable macro TITAN_CSC$V_TPQMMAX = 4,4,4,0 %; literal TITAN_CSC$S_TPQMMAX = 4; ! 39:36 Max entries in TPQM on D-Chips, mod 16 macro TITAN_CSC$V_FPQCMAX = 4,8,4,0 %; literal TITAN_CSC$S_FPQCMAX = 4; ! 43:40 Max entries in FQP, mod 16 macro TITAN_CSC$V_FPQPMAX = 4,12,4,0 %; literal TITAN_CSC$S_FPQPMAX = 4; ! 47:44 Max entries in FPQ, mod 8 macro TITAN_CSC$V_PDTMAX = 4,16,3,0 %; literal TITAN_CSC$S_PDTMAX = 3; ! 50:48 Max data xfers to one P-Chip until ack, mod 8 macro TITAN_CSC$V_AXD = 4,19,1,0 %; ! 51 Disable Memory Address XOR macro TITAN_CSC$V_PRQMAX = 4,20,3,0 %; literal TITAN_CSC$S_PRQMAX = 3; ! 54:52 max reqests to one P-Chip until ack, mod 8 macro TITAN_CSC$V_ADD4PTP = 4,23,1,0 %; ! 55 Additional 4 PTP macro TITAN_CSC$V_PBQMAX = 4,24,3,0 %; literal TITAN_CSC$S_PBQMAX = 3; ! 58:56 Max CPU probe queue macro TITAN_CSC$V_RSVD_7 = 4,27,3,0 %; literal TITAN_CSC$S_RSVD_7 = 3; ! 61:59 reserved macro TITAN_CSC$V_NODQM = 4,30,1,0 %; ! 62 Set to 1, DMA partial writes to memory use DQM macro TITAN_CSC$V_ISM = 4,31,1,0 %; ! 63 Interrupt Strobe Mode bit ! ! ! Titan MTR - C-Chip Memory Timing Register ! literal TITAN_MTR$M_RCD = %X'1'; literal TITAN_MTR$M_RSVD_0 = %X'2'; literal TITAN_MTR$M_CAT = %X'4'; literal TITAN_MTR$M_RSVD_1 = %X'8'; literal TITAN_MTR$M_IRD = %X'70'; literal TITAN_MTR$M_RSVD_2 = %X'80'; literal TITAN_MTR$M_RPW = %X'300'; literal TITAN_MTR$M_RSVD_3 = %X'C00'; literal TITAN_MTR$M_RPT = %X'3000'; literal TITAN_MTR$M_RSVD_4 = %X'C000'; literal TITAN_MTR$M_RRD = %X'10000'; literal TITAN_MTR$M_RSVD_5 = %X'E0000'; literal TITAN_MTR$M_MPD = %X'100000'; literal TITAN_MTR$M_RSVD_6 = %X'E00000'; literal TITAN_MTR$M_RI = %X'3F000000'; literal TITAN_MTR$M_RSVD_7 = %X'C0000000'; literal TITAN_MTR$M_PHCR = %X'F00000000'; literal TITAN_MTR$M_PHCW = %X'F000000000'; literal TITAN_MTR$M_MPH = %X'3F0000000000'; literal TITAN_MTR$M_RSVD_8 = %X'FFFFC00000000000'; literal TITAN_MTR$S_TITAN_MTR = 8; macro TITAN_MTR$IQ_DATA = 0,0,0,0 %; literal TITAN_MTR$S_DATA = 8; macro TITAN_MTR$IL_L = 0,0,32,0 %; macro TITAN_MTR$IL_H = 4,0,32,0 %; macro TITAN_MTR$V_RCD = 0,0,1,0 %; ! 0 RAS to CAS Delay macro TITAN_MTR$V_RSVD_0 = 0,1,1,0 %; ! 1 reserved macro TITAN_MTR$V_CAT = 0,2,1,0 %; ! 2 CAS Access Time macro TITAN_MTR$V_RSVD_1 = 0,3,1,0 %; ! 3 reserved macro TITAN_MTR$V_IRD = 0,4,3,0 %; literal TITAN_MTR$S_IRD = 3; ! 6:4 Issue to RAS Delay macro TITAN_MTR$V_RSVD_2 = 0,7,1,0 %; ! 7 reserved macro TITAN_MTR$V_RPW = 0,8,2,0 %; literal TITAN_MTR$S_RPW = 2; ! 9:8 Minimum RAS Pulse Width macro TITAN_MTR$V_RSVD_3 = 0,10,2,0 %; literal TITAN_MTR$S_RSVD_3 = 2; ! 11:10 reserved macro TITAN_MTR$V_RPT = 0,12,2,0 %; literal TITAN_MTR$S_RPT = 2; ! 13:12 Min RAS Precharge Time macro TITAN_MTR$V_RSVD_4 = 0,14,2,0 %; literal TITAN_MTR$S_RSVD_4 = 2; ! 15:14 reserved macro TITAN_MTR$V_RRD = 0,16,1,0 %; ! 16 Min Same-Array_Diff-Bank RAS-to-RAS Delay macro TITAN_MTR$V_RSVD_5 = 0,17,3,0 %; literal TITAN_MTR$S_RSVD_5 = 3; ! 19:17 reserved macro TITAN_MTR$V_MPD = 0,20,1,0 %; ! 20 Mask Pipeline Delay macro TITAN_MTR$V_RSVD_6 = 0,21,3,0 %; literal TITAN_MTR$S_RSVD_6 = 3; ! 23:21 reserved macro TITAN_MTR$V_RI = 0,24,6,0 %; literal TITAN_MTR$S_RI = 6; ! 29:24 Refresh Interval macro TITAN_MTR$V_RSVD_7 = 0,30,2,0 %; literal TITAN_MTR$S_RSVD_7 = 2; ! 31:30 reserved ! macro TITAN_MTR$V_PHCR = 4,0,4,0 %; literal TITAN_MTR$S_PHCR = 4; ! 35:32 Page Hit Cycles for Reads macro TITAN_MTR$V_PHCW = 4,4,4,0 %; literal TITAN_MTR$S_PHCW = 4; ! 39:36 Page Hit Cycles for Writes macro TITAN_MTR$V_MPH = 4,8,6,0 %; literal TITAN_MTR$S_MPH = 6; ! 45:40 Max Page Hits macro TITAN_MTR$V_RSVD_8 = 4,14,18,0 %; literal TITAN_MTR$S_RSVD_8 = 18; ! 63:46 reserved ! ! ! Titan MISC - C-Chip Miscellaneous Register ! literal TITAN_MISC$M_CPUID = %X'3'; literal TITAN_MISC$M_RSVD_0 = %X'C'; literal TITAN_MISC$M_ITINTR = %X'F0'; literal TITAN_MISC$M_IPINTR = %X'F00'; literal TITAN_MISC$M_IPREQ = %X'F000'; literal TITAN_MISC$M_ABW = %X'F0000'; literal TITAN_MISC$M_ABT = %X'F00000'; literal TITAN_MISC$M_ACL = %X'1000000'; literal TITAN_MISC$M_RSVD_6 = %X'E000000'; literal TITAN_MISC$M_NXM = %X'10000000'; literal TITAN_MISC$M_NXS = %X'E0000000'; literal TITAN_MISC$M_REV = %X'FF00000000'; literal TITAN_MISC$M_DEVSUP = %X'F0000000000'; literal TITAN_MISC$M_RSVD_7 = %X'FFFFF00000000000'; literal TITAN_MISC$S_TITAN_MISC = 8; macro TITAN_MISC$V_CPUID = 0,0,2,0 %; literal TITAN_MISC$S_CPUID = 2; ! 0:1 ID of CPU performing the read macro TITAN_MISC$V_RSVD_0 = 0,2,2,0 %; literal TITAN_MISC$S_RSVD_0 = 2; ! 3:2 reserved macro TITAN_MISC$V_ITINTR = 0,4,4,0 %; literal TITAN_MISC$S_ITINTR = 4; ! 7:4 Interval Timer Interrupt pending macro TITAN_MISC$V_IPINTR = 0,8,4,0 %; literal TITAN_MISC$S_IPINTR = 4; ! 11:8 Interprocessor Interrupt pending macro TITAN_MISC$V_IPREQ = 0,12,4,0 %; literal TITAN_MISC$S_IPREQ = 4; ! 15:12 Interprocessor Interrupt Request macro TITAN_MISC$V_ABW = 0,16,4,0 %; literal TITAN_MISC$S_ABW = 4; ! 19:16 Arbitration Won macro TITAN_MISC$V_ABT = 0,20,4,0 %; literal TITAN_MISC$S_ABT = 4; ! 23:20 Arbitration Try macro TITAN_MISC$V_ACL = 0,24,1,0 %; ! 24 Arbitration Clear macro TITAN_MISC$V_RSVD_6 = 0,25,3,0 %; literal TITAN_MISC$S_RSVD_6 = 3; ! 27:25 reserved macro TITAN_MISC$V_NXM = 0,28,1,0 %; ! 28 Non eXistent Memory macro TITAN_MISC$V_NXS = 0,29,3,0 %; literal TITAN_MISC$S_NXS = 3; ! 31:29 NXM Source ! macro TITAN_MISC$V_REV = 4,0,8,0 %; literal TITAN_MISC$S_REV = 8; ! 39:32 C-Chip Revision macro TITAN_MISC$V_DEVSUP = 4,8,4,0 %; literal TITAN_MISC$S_DEVSUP = 4; ! 43:40 Suppress IRQ[1] macro TITAN_MISC$V_RSVD_7 = 4,12,20,0 %; literal TITAN_MISC$S_RSVD_7 = 20; ! 63:44 reserved ! ! ! Titan MPD - C-Chip Memory Presence Detect ! literal TITAN_MPD$M_CKS = %X'1'; literal TITAN_MPD$M_DS = %X'2'; literal TITAN_MPD$M_CKR = %X'4'; literal TITAN_MPD$M_DR = %X'8'; literal TITAN_MPD$M_RSVD_0 = %X'FFFFFFF0'; literal TITAN_MPD$M_RSVD_1 = %X'FFFFFFFF00000000'; literal TITAN_MPD$S_TITAN_MPD = 8; macro TITAN_MPD$V_CKS = 0,0,1,0 %; ! 0 ClocK Send macro TITAN_MPD$V_DS = 0,1,1,0 %; ! 1 Data Send macro TITAN_MPD$V_CKR = 0,2,1,0 %; ! 2 ClocK Receive macro TITAN_MPD$V_DR = 0,3,1,0 %; ! 3 Data Receive macro TITAN_MPD$V_RSVD_0 = 0,4,28,0 %; literal TITAN_MPD$S_RSVD_0 = 28; ! 31:4 reserved ! macro TITAN_MPD$V_RSVD_1 = 4,0,32,0 %; literal TITAN_MPD$S_RSVD_1 = 32; ! 63:32 reserved ! ! ! Titan AAR - C-Chip Array Address Register ! literal TITAN_AAR$M_BNKS = %X'3'; literal TITAN_AAR$M_ROWS = %X'C'; literal TITAN_AAR$M_RSVD_1 = %X'F0'; literal TITAN_AAR$M_SA = %X'100'; literal TITAN_AAR$M_DSA = %X'200'; literal TITAN_AAR$M_RSVD_2 = %X'C00'; literal TITAN_AAR$M_ASIZ = %X'F000'; literal TITAN_AAR$M_DBG = %X'10000'; literal TITAN_AAR$M_RSVD_4 = %X'FE0000'; literal TITAN_AAR$M_ADDR = %X'7FF000000'; literal TITAN_AAR$M_RSVD_5 = %X'7FFFFFF800000000'; literal TITAN_AAR$S_TITAN_AAR = 8; macro TITAN_AAR$IQ_DATA = 0,0,0,0 %; literal TITAN_AAR$S_DATA = 8; macro TITAN_AAR$IL_L = 0,0,32,0 %; macro TITAN_AAR$IL_H = 4,0,32,0 %; macro TITAN_AAR$V_BNKS = 0,0,2,0 %; literal TITAN_AAR$S_BNKS = 2; ! 1:0 Number of Bank bits in SDRAMs macro TITAN_AAR$V_ROWS = 0,2,2,0 %; literal TITAN_AAR$S_ROWS = 2; ! 3:2 Number of Row bits in SDRAMS macro TITAN_AAR$V_RSVD_1 = 0,4,4,0 %; literal TITAN_AAR$S_RSVD_1 = 4; ! 7:4 reserved macro TITAN_AAR$V_SA = 0,8,1,0 %; ! 8 Split Array macro TITAN_AAR$V_DSA = 0,9,1,0 %; ! 9 Doubly (twice) Split Array macro TITAN_AAR$V_RSVD_2 = 0,10,2,0 %; literal TITAN_AAR$S_RSVD_2 = 2; ! 11:10 reserved macro TITAN_AAR$V_ASIZ = 0,12,4,0 %; literal TITAN_AAR$S_ASIZ = 4; ! 15:12 Array Size macro TITAN_AAR$V_DBG = 0,16,1,0 %; ! 16 Enables this memory port as a debug interface macro TITAN_AAR$V_RSVD_4 = 0,17,7,0 %; literal TITAN_AAR$S_RSVD_4 = 7; ! 23:17 reserved macro TITAN_AAR$V_ADDR = 0,24,11,0 %; literal TITAN_AAR$S_ADDR = 11; ! 34:24 Base Address macro TITAN_AAR$V_RSVD_5 = 4,3,28,0 %; literal TITAN_AAR$S_RSVD_5 = 28; ! 63:35 reserved ! ! ! Titan DIM - C-Chip Device Interrupt Mask Registers ! literal TITAN_DIM$S_TITAN_DIM = 8; macro TITAN_DIM$IQ_DATA = 0,0,0,0 %; literal TITAN_DIM$S_DATA = 8; macro TITAN_DIM$IL_L = 0,0,32,0 %; macro TITAN_DIM$IL_H = 4,0,32,0 %; ! ! ! Titan DIR - C-Chip Device Interrupt Request Registers ! literal TITAN_DIR$M_DEV_L = %X'FFFFFFFF'; literal TITAN_DIR$M_DEV_H = %X'FFFFFF00000000'; literal TITAN_DIR$M_RSVD_0 = %X'300000000000000'; literal TITAN_DIR$M_ERR = %X'FC00000000000000'; literal TITAN_DIR$S_TITAN_DIR = 8; macro TITAN_DIR$IQ_DATA = 0,0,0,0 %; literal TITAN_DIR$S_DATA = 8; macro TITAN_DIR$IL_L = 0,0,32,0 %; macro TITAN_DIR$IL_H = 4,0,32,0 %; macro TITAN_DIR$V_DEV_L = 0,0,32,0 %; literal TITAN_DIR$S_DEV_L = 32; ! 31:0 IRQ[1] PCI Interrupts Pending macro TITAN_DIR$V_DEV_H = 4,0,24,0 %; literal TITAN_DIR$S_DEV_H = 24; ! 55:32 IRQ[1] PCI Interrupts Pending macro TITAN_DIR$V_RSVD_0 = 4,24,2,0 %; literal TITAN_DIR$S_RSVD_0 = 2; ! 57:56 reserved macro TITAN_DIR$V_ERR = 4,26,6,0 %; literal TITAN_DIR$S_ERR = 6; ! 63:58 IRQ[0] Error Interrupts ! ! ! Titan DRIR - C-Chip Raw Interrupt Request Register ! literal TITAN_DRIR$S_TITAN_DRIR = 8; macro TITAN_DRIR$IQ_DATA = 0,0,0,0 %; literal TITAN_DRIR$S_DATA = 8; macro TITAN_DRIR$IL_L = 0,0,32,0 %; macro TITAN_DRIR$IL_H = 4,0,32,0 %; ! ! ! Titan PRBEN - C-Chip Probe Enable Register ! literal TITAN_PRBEN$M_PRBEN = %X'1'; literal TITAN_PRBEN$M_RSVD_0 = %X'FFFFFFFE'; literal TITAN_PRBEN$M_RSVD_1 = %X'FFFFFFFF00000000'; literal TITAN_PRBEN$S_TITAN_PRBEN = 8; macro TITAN_PRBEN$IQ_DATA = 0,0,0,0 %; literal TITAN_PRBEN$S_DATA = 8; macro TITAN_PRBEN$IL_L = 0,0,32,0 %; macro TITAN_PRBEN$IL_H = 4,0,32,0 %; macro TITAN_PRBEN$V_PRBEN = 0,0,1,0 %; ! 0 Probe Enable bit macro TITAN_PRBEN$V_RSVD_0 = 0,1,31,0 %; literal TITAN_PRBEN$S_RSVD_0 = 31; ! 31:1 Reserved macro TITAN_PRBEN$V_RSVD_1 = 4,0,32,0 %; literal TITAN_PRBEN$S_RSVD_1 = 32; ! 63:32 Reserved ! ! ! Titan IIC - C-Chip Interval Ignore Count Registers ! literal TITAN_IIC$M_ICNT = %X'FFFFFF'; literal TITAN_IIC$M_OF = %X'1000000'; literal TITAN_IIC$M_RSVD_0 = %X'FE000000'; literal TITAN_IIC$M_RSVD_1 = %X'FFFFFFFF00000000'; literal TITAN_IIC$S_TITAN_IIC = 8; macro TITAN_IIC$IQ_DATA = 0,0,0,0 %; literal TITAN_IIC$S_DATA = 8; macro TITAN_IIC$IL_L = 0,0,32,0 %; macro TITAN_IIC$IL_H = 4,0,32,0 %; macro TITAN_IIC$V_ICNT = 0,0,24,0 %; literal TITAN_IIC$S_ICNT = 24; ! 23:0 Count of remaining interrupts to ignore macro TITAN_IIC$V_OF = 0,24,1,0 %; ! 24 Overflow bit macro TITAN_IIC$V_RSVD_0 = 0,25,7,0 %; literal TITAN_IIC$S_RSVD_0 = 7; ! 31:25 reserved macro TITAN_IIC$V_RSVD_1 = 4,0,32,0 %; literal TITAN_IIC$S_RSVD_1 = 32; ! 63:32 reserved ! ! ! Titan MPR - C-Chip Memory Programming Registers ! literal TITAN_MPR$M_MPRDAT = %X'1FFF'; literal TITAN_MPR$M_RSVD_0 = %X'FFFFE000'; literal TITAN_MPR$M_RSVD_1 = %X'FFFFFFFF00000000'; literal TITAN_MPR$S_TITAN_MPR = 8; macro TITAN_MPR$IQ_DATA = 0,0,0,0 %; literal TITAN_MPR$S_DATA = 8; macro TITAN_MPR$IL_L = 0,0,32,0 %; macro TITAN_MPR$IL_H = 4,0,32,0 %; macro TITAN_MPR$V_MPRDAT = 0,0,13,0 %; literal TITAN_MPR$S_MPRDAT = 13; ! 12:0 Data to be written on address lines 12:0 macro TITAN_MPR$V_RSVD_0 = 0,13,19,0 %; literal TITAN_MPR$S_RSVD_0 = 19; ! 31:13 reserved macro TITAN_MPR$V_RSVD_1 = 4,0,32,0 %; literal TITAN_MPR$S_RSVD_1 = 32; ! 63:32 reserved ! ! ! Titan TTR - C-Chip TIG Bus Timing Register ! literal TITAN_TTR$M_AS = %X'3'; literal TITAN_TTR$M_AH = %X'C'; literal TITAN_TTR$M_IS = %X'F0'; literal TITAN_TTR$M_IRT = %X'F00'; literal TITAN_TTR$M_ID = %X'7000'; literal TITAN_TTR$M_RSVD_3 = %X'FFFF8000'; literal TITAN_TTR$M_RSVD_4 = %X'FFFFFFFF00000000'; literal TITAN_TTR$S_TITAN_TTR = 8; macro TITAN_TTR$V_AS = 0,0,2,0 %; literal TITAN_TTR$S_AS = 2; ! 1:0 Address Setup to the address latch before AS macro TITAN_TTR$V_AH = 0,2,2,0 %; literal TITAN_TTR$S_AH = 2; ! 3:2 Address Hold after AS before CS_L macro TITAN_TTR$V_IS = 0,4,4,0 %; literal TITAN_TTR$S_IS = 4; ! 7:4 Interrupt Setup time macro TITAN_TTR$V_IRT = 0,8,4,0 %; literal TITAN_TTR$S_IRT = 4; ! 11:8 Interrupt Read Time macro TITAN_TTR$V_ID = 0,12,3,0 %; literal TITAN_TTR$S_ID = 3; ! 14:12 Interrupt starting Device macro TITAN_TTR$V_RSVD_3 = 0,15,17,0 %; literal TITAN_TTR$S_RSVD_3 = 17; ! 31:15 reserved macro TITAN_TTR$V_RSVD_4 = 4,0,32,0 %; literal TITAN_TTR$S_RSVD_4 = 32; ! 63:32 reserved ! ! ! Titan TDR - C-Chip TIG Bus Device Timing Register ! literal TITAN_TDR$M_RA0 = %X'1F'; literal TITAN_TDR$M_RD0 = %X'E0'; literal TITAN_TDR$M_WS0 = %X'F00'; literal TITAN_TDR$M_WP0 = %X'7000'; literal TITAN_TDR$M_WH0 = %X'8000'; literal TITAN_TDR$M_RA1 = %X'1F0000'; literal TITAN_TDR$M_RD1 = %X'E00000'; literal TITAN_TDR$M_WS1 = %X'F000000'; literal TITAN_TDR$M_WP1 = %X'70000000'; literal TITAN_TDR$M_WH1 = %X'80000000'; literal TITAN_TDR$M_RA2 = %X'1F00000000'; literal TITAN_TDR$M_RD2 = %X'E000000000'; literal TITAN_TDR$M_WS2 = %X'F0000000000'; literal TITAN_TDR$M_WP2 = %X'700000000000'; literal TITAN_TDR$M_WH2 = %X'800000000000'; literal TITAN_TDR$M_RA3 = %X'1F000000000000'; literal TITAN_TDR$M_RD3 = %X'E0000000000000'; literal TITAN_TDR$M_WS3 = %X'F00000000000000'; literal TITAN_TDR$M_WP3 = %X'7000000000000000'; literal TITAN_TDR$M_WH3 = %X'8000000000000000'; literal TITAN_TDR$S_TITAN_TDR = 8; macro TITAN_TDR$IQ_DATA = 0,0,0,0 %; literal TITAN_TDR$S_DATA = 8; macro TITAN_TDR$IL_L = 0,0,32,0 %; macro TITAN_TDR$IL_H = 4,0,32,0 %; macro TITAN_TDR$V_RA0 = 0,0,5,0 %; literal TITAN_TDR$S_RA0 = 5; ! 4:0 Read Access time macro TITAN_TDR$V_RD0 = 0,5,3,0 %; literal TITAN_TDR$S_RD0 = 3; ! 7:5 Read output Disable time macro TITAN_TDR$V_WS0 = 0,8,4,0 %; literal TITAN_TDR$S_WS0 = 4; ! 11:8 Write Setup time macro TITAN_TDR$V_WP0 = 0,12,3,0 %; literal TITAN_TDR$S_WP0 = 3; ! 14:12 Write Pulse width macro TITAN_TDR$V_WH0 = 0,15,1,0 %; ! 15 Write Hold time ! macro TITAN_TDR$V_RA1 = 0,16,5,0 %; literal TITAN_TDR$S_RA1 = 5; ! 20:16 Read Access time macro TITAN_TDR$V_RD1 = 0,21,3,0 %; literal TITAN_TDR$S_RD1 = 3; ! 23:21 Read output Disable time macro TITAN_TDR$V_WS1 = 0,24,4,0 %; literal TITAN_TDR$S_WS1 = 4; ! 27:24 Write Setup time macro TITAN_TDR$V_WP1 = 0,28,3,0 %; literal TITAN_TDR$S_WP1 = 3; ! 30:28 Write Pulse width macro TITAN_TDR$V_WH1 = 0,31,1,0 %; ! 31 Write Hold time ! macro TITAN_TDR$V_RA2 = 4,0,5,0 %; literal TITAN_TDR$S_RA2 = 5; ! 36:32 Read Access time macro TITAN_TDR$V_RD2 = 4,5,3,0 %; literal TITAN_TDR$S_RD2 = 3; ! 39:37 Read output Disable time macro TITAN_TDR$V_WS2 = 4,8,4,0 %; literal TITAN_TDR$S_WS2 = 4; ! 43:40 Write Setup time macro TITAN_TDR$V_WP2 = 4,12,3,0 %; literal TITAN_TDR$S_WP2 = 3; ! 46:44 Write Pulse width macro TITAN_TDR$V_WH2 = 4,15,1,0 %; ! 47 Write Hold time ! macro TITAN_TDR$V_RA3 = 4,16,5,0 %; literal TITAN_TDR$S_RA3 = 5; ! 52:48 Read Access time macro TITAN_TDR$V_RD3 = 4,21,3,0 %; literal TITAN_TDR$S_RD3 = 3; ! 55:53 Read output Disable time macro TITAN_TDR$V_WS3 = 4,24,4,0 %; literal TITAN_TDR$S_WS3 = 4; ! 59:56 Write Setup time macro TITAN_TDR$V_WP3 = 4,28,3,0 %; literal TITAN_TDR$S_WP3 = 3; ! 62:60 Write Pulse width macro TITAN_TDR$V_WH3 = 4,31,1,0 %; ! 63 Write Hold time ! ========================================================================== ! ! D-Chip Registers ! ! ========================================================================== ! ! ! Titan DSC - D-Chip System Configuration Register ! literal TITAN_DSC$M_BC = %X'3'; literal TITAN_DSC$M_C0CFP = %X'4'; literal TITAN_DSC$M_C1CFP = %X'8'; literal TITAN_DSC$M_C2CFP = %X'10'; literal TITAN_DSC$M_C3CFP = %X'20'; literal TITAN_DSC$M_P1P = %X'40'; literal TITAN_DSC$M_RSVD_0 = %X'80'; literal TITAN_DSC$M_BC1 = %X'300'; literal TITAN_DSC$M_C0CFP1 = %X'400'; literal TITAN_DSC$M_C1CFP1 = %X'800'; literal TITAN_DSC$M_C2CFP1 = %X'1000'; literal TITAN_DSC$M_C3CFP1 = %X'2000'; literal TITAN_DSC$M_P1P1 = %X'4000'; literal TITAN_DSC$M_RSVD_1 = %X'8000'; literal TITAN_DSC$M_BC2 = %X'30000'; literal TITAN_DSC$M_C0CFP2 = %X'40000'; literal TITAN_DSC$M_C1CFP2 = %X'80000'; literal TITAN_DSC$M_C2CFP2 = %X'100000'; literal TITAN_DSC$M_C3CFP2 = %X'200000'; literal TITAN_DSC$M_P1P2 = %X'400000'; literal TITAN_DSC$M_RSVD_2 = %X'800000'; literal TITAN_DSC$M_BC3 = %X'3000000'; literal TITAN_DSC$M_C0CFP3 = %X'4000000'; literal TITAN_DSC$M_C1CFP3 = %X'8000000'; literal TITAN_DSC$M_C2CFP3 = %X'10000000'; literal TITAN_DSC$M_C3CFP3 = %X'20000000'; literal TITAN_DSC$M_P1P3 = %X'40000000'; literal TITAN_DSC$M_RSVD_3 = %X'80000000'; literal TITAN_DSC$M_BC4 = %X'300000000'; literal TITAN_DSC$M_C0CFP4 = %X'400000000'; literal TITAN_DSC$M_C1CFP4 = %X'800000000'; literal TITAN_DSC$M_C2CFP4 = %X'1000000000'; literal TITAN_DSC$M_C3CFP4 = %X'2000000000'; literal TITAN_DSC$M_P1P4 = %X'4000000000'; literal TITAN_DSC$M_RSVD_4 = %X'8000000000'; literal TITAN_DSC$M_BC15 = %X'30000000000'; literal TITAN_DSC$M_C0CFP5 = %X'40000000000'; literal TITAN_DSC$M_C1CFP5 = %X'80000000000'; literal TITAN_DSC$M_C2CFP5 = %X'100000000000'; literal TITAN_DSC$M_C3CFP5 = %X'200000000000'; literal TITAN_DSC$M_P1P5 = %X'400000000000'; literal TITAN_DSC$M_RSVD_5 = %X'800000000000'; literal TITAN_DSC$M_BC6 = %X'3000000000000'; literal TITAN_DSC$M_C0CFP6 = %X'4000000000000'; literal TITAN_DSC$M_C1CFP6 = %X'8000000000000'; literal TITAN_DSC$M_C2CFP6 = %X'10000000000000'; literal TITAN_DSC$M_C3CFP6 = %X'20000000000000'; literal TITAN_DSC$M_P1P6 = %X'40000000000000'; literal TITAN_DSC$M_RSVD_6 = %X'80000000000000'; literal TITAN_DSC$M_BC7 = %X'300000000000000'; literal TITAN_DSC$M_C0CFP7 = %X'400000000000000'; literal TITAN_DSC$M_C1CFP7 = %X'800000000000000'; literal TITAN_DSC$M_C2CFP7 = %X'1000000000000000'; literal TITAN_DSC$M_C3CFP7 = %X'2000000000000000'; literal TITAN_DSC$M_P1P7 = %X'4000000000000000'; literal TITAN_DSC$M_RSVD_7 = %X'8000000000000000'; literal TITAN_DSC$S_TITAN_DSC = 8; macro TITAN_DSC$IQ_DATA = 0,0,0,0 %; literal TITAN_DSC$S_DATA = 8; macro TITAN_DSC$IL_L = 0,0,32,0 %; macro TITAN_DSC$IL_H = 4,0,32,0 %; macro TITAN_DSC$V_BC = 0,0,2,0 %; literal TITAN_DSC$S_BC = 2; ! 1:0 Base Configuration macro TITAN_DSC$V_C0CFP = 0,2,1,0 %; ! 2 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C1CFP = 0,3,1,0 %; ! 3 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C2CFP = 0,4,1,0 %; ! 4 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C3CFP = 0,5,1,0 %; ! 5 CPU 0 Clock Forward Preset macro TITAN_DSC$V_P1P = 0,6,1,0 %; ! 6 P-Chip_1 Preset macro TITAN_DSC$V_RSVD_0 = 0,7,1,0 %; ! 7 reserved ! macro TITAN_DSC$V_BC1 = 0,8,2,0 %; literal TITAN_DSC$S_BC1 = 2; ! 9:8 Base Configuration macro TITAN_DSC$V_C0CFP1 = 0,10,1,0 %; ! 10 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C1CFP1 = 0,11,1,0 %; ! 11 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C2CFP1 = 0,12,1,0 %; ! 12 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C3CFP1 = 0,13,1,0 %; ! 13 CPU 0 Clock Forward Preset macro TITAN_DSC$V_P1P1 = 0,14,1,0 %; ! 14 P-Chip_1 Preset macro TITAN_DSC$V_RSVD_1 = 0,15,1,0 %; ! 15 reserved ! macro TITAN_DSC$V_BC2 = 0,16,2,0 %; literal TITAN_DSC$S_BC2 = 2; ! 17:16 Base Configuration macro TITAN_DSC$V_C0CFP2 = 0,18,1,0 %; ! 18 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C1CFP2 = 0,19,1,0 %; ! 19 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C2CFP2 = 0,20,1,0 %; ! 20 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C3CFP2 = 0,21,1,0 %; ! 21 CPU 0 Clock Forward Preset macro TITAN_DSC$V_P1P2 = 0,22,1,0 %; ! 22 P-Chip_1 Preset macro TITAN_DSC$V_RSVD_2 = 0,23,1,0 %; ! 23 reserved ! macro TITAN_DSC$V_BC3 = 0,24,2,0 %; literal TITAN_DSC$S_BC3 = 2; ! 25:24 Base Configuration macro TITAN_DSC$V_C0CFP3 = 0,26,1,0 %; ! 26 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C1CFP3 = 0,27,1,0 %; ! 27 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C2CFP3 = 0,28,1,0 %; ! 28 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C3CFP3 = 0,29,1,0 %; ! 29 CPU 0 Clock Forward Preset macro TITAN_DSC$V_P1P3 = 0,30,1,0 %; ! 30 P-Chip_1 Preset macro TITAN_DSC$V_RSVD_3 = 0,31,1,0 %; ! 31 reserved ! macro TITAN_DSC$V_BC4 = 4,0,2,0 %; literal TITAN_DSC$S_BC4 = 2; ! 33:32 Base Configuration macro TITAN_DSC$V_C0CFP4 = 4,2,1,0 %; ! 34 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C1CFP4 = 4,3,1,0 %; ! 35 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C2CFP4 = 4,4,1,0 %; ! 36 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C3CFP4 = 4,5,1,0 %; ! 37 CPU 0 Clock Forward Preset macro TITAN_DSC$V_P1P4 = 4,6,1,0 %; ! 38 P-Chip_1 Preset macro TITAN_DSC$V_RSVD_4 = 4,7,1,0 %; ! 39 reserved ! macro TITAN_DSC$V_BC15 = 4,8,2,0 %; literal TITAN_DSC$S_BC15 = 2; ! 41:40 Base Configuration macro TITAN_DSC$V_C0CFP5 = 4,10,1,0 %; ! 42 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C1CFP5 = 4,11,1,0 %; ! 43 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C2CFP5 = 4,12,1,0 %; ! 44 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C3CFP5 = 4,13,1,0 %; ! 45 CPU 0 Clock Forward Preset macro TITAN_DSC$V_P1P5 = 4,14,1,0 %; ! 46 P-Chip_1 Preset macro TITAN_DSC$V_RSVD_5 = 4,15,1,0 %; ! 47 reserved ! macro TITAN_DSC$V_BC6 = 4,16,2,0 %; literal TITAN_DSC$S_BC6 = 2; ! 49:48 Base Configuration macro TITAN_DSC$V_C0CFP6 = 4,18,1,0 %; ! 50 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C1CFP6 = 4,19,1,0 %; ! 51 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C2CFP6 = 4,20,1,0 %; ! 52 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C3CFP6 = 4,21,1,0 %; ! 53 CPU 0 Clock Forward Preset macro TITAN_DSC$V_P1P6 = 4,22,1,0 %; ! 54 P-Chip_1 Preset macro TITAN_DSC$V_RSVD_6 = 4,23,1,0 %; ! 55 reserved ! macro TITAN_DSC$V_BC7 = 4,24,2,0 %; literal TITAN_DSC$S_BC7 = 2; ! 57:56 Base Configuration macro TITAN_DSC$V_C0CFP7 = 4,26,1,0 %; ! 58 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C1CFP7 = 4,27,1,0 %; ! 59 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C2CFP7 = 4,28,1,0 %; ! 60 CPU 0 Clock Forward Preset macro TITAN_DSC$V_C3CFP7 = 4,29,1,0 %; ! 61 CPU 0 Clock Forward Preset macro TITAN_DSC$V_P1P7 = 4,30,1,0 %; ! 62 P-Chip_1 Preset macro TITAN_DSC$V_RSVD_7 = 4,31,1,0 %; ! 63 reserved ! ! ! Titan STR - D-Chip System Timing Register ! literal TITAN_STR$M_AW = %X'1'; literal TITAN_STR$M_IDDR = %X'E'; literal TITAN_STR$M_IDDW = %X'30'; literal TITAN_STR$M_RSVD_0 = %X'C0'; literal TITAN_STR$M_AW1 = %X'100'; literal TITAN_STR$M_IDDR1 = %X'E00'; literal TITAN_STR$M_IDDW1 = %X'3000'; literal TITAN_STR$M_RSVD_1 = %X'C000'; literal TITAN_STR$M_AW2 = %X'10000'; literal TITAN_STR$M_IDDR2 = %X'E0000'; literal TITAN_STR$M_IDDW2 = %X'300000'; literal TITAN_STR$M_RSVD_2 = %X'C00000'; literal TITAN_STR$M_AW3 = %X'1000000'; literal TITAN_STR$M_IDDR3 = %X'E000000'; literal TITAN_STR$M_IDDW3 = %X'30000000'; literal TITAN_STR$M_RSVD_3 = %X'C0000000'; literal TITAN_STR$M_AW4 = %X'100000000'; literal TITAN_STR$M_IDDR4 = %X'E00000000'; literal TITAN_STR$M_IDDW4 = %X'3000000000'; literal TITAN_STR$M_RSVD_4 = %X'C000000000'; literal TITAN_STR$M_AW5 = %X'10000000000'; literal TITAN_STR$M_IDDR5 = %X'E0000000000'; literal TITAN_STR$M_IDDW5 = %X'300000000000'; literal TITAN_STR$M_RSVD_5 = %X'C00000000000'; literal TITAN_STR$M_AW6 = %X'1000000000000'; literal TITAN_STR$M_IDDR6 = %X'E000000000000'; literal TITAN_STR$M_IDDW6 = %X'30000000000000'; literal TITAN_STR$M_RSVD_6 = %X'C0000000000000'; literal TITAN_STR$M_AW7 = %X'100000000000000'; literal TITAN_STR$M_IDDR7 = %X'E00000000000000'; literal TITAN_STR$M_IDDW7 = %X'3000000000000000'; literal TITAN_STR$M_RSVD_7 = %X'C000000000000000'; literal TITAN_STR$S_TITAN_STR = 8; macro TITAN_STR$IQ_DATA = 0,0,0,0 %; literal TITAN_STR$S_DATA = 8; macro TITAN_STR$IL_L = 0,0,32,0 %; macro TITAN_STR$IL_H = 4,0,32,0 %; macro TITAN_STR$V_AW = 0,0,1,0 %; ! 0 Array Width macro TITAN_STR$V_IDDR = 0,1,3,0 %; literal TITAN_STR$S_IDDR = 3; ! 3:1 Issue to Data Delay for memory reads macro TITAN_STR$V_IDDW = 0,4,2,0 %; literal TITAN_STR$S_IDDW = 2; ! 5:4 Issue to Data Delay for xactions other than memory reads macro TITAN_STR$V_RSVD_0 = 0,6,2,0 %; literal TITAN_STR$S_RSVD_0 = 2; ! 7:6 reserved ! macro TITAN_STR$V_AW1 = 0,8,1,0 %; ! 8 Array Width macro TITAN_STR$V_IDDR1 = 0,9,3,0 %; literal TITAN_STR$S_IDDR1 = 3; ! 11:9 Issue to Data Delay for memory reads macro TITAN_STR$V_IDDW1 = 0,12,2,0 %; literal TITAN_STR$S_IDDW1 = 2; ! 13:12 Issue to Data Delay for xactions other than memory reads macro TITAN_STR$V_RSVD_1 = 0,14,2,0 %; literal TITAN_STR$S_RSVD_1 = 2; ! 15:14 reserved ! macro TITAN_STR$V_AW2 = 0,16,1,0 %; ! 16 Array Width macro TITAN_STR$V_IDDR2 = 0,17,3,0 %; literal TITAN_STR$S_IDDR2 = 3; ! 19:17 Issue to Data Delay for memory reads macro TITAN_STR$V_IDDW2 = 0,20,2,0 %; literal TITAN_STR$S_IDDW2 = 2; ! 21:20 Issue to Data Delay for xactions other than memory reads macro TITAN_STR$V_RSVD_2 = 0,22,2,0 %; literal TITAN_STR$S_RSVD_2 = 2; ! 23:22 reserved ! macro TITAN_STR$V_AW3 = 0,24,1,0 %; ! 24 Array Width macro TITAN_STR$V_IDDR3 = 0,25,3,0 %; literal TITAN_STR$S_IDDR3 = 3; ! 27:25 Issue to Data Delay for memory reads macro TITAN_STR$V_IDDW3 = 0,28,2,0 %; literal TITAN_STR$S_IDDW3 = 2; ! 29:28 Issue to Data Delay for xactions other than memory reads macro TITAN_STR$V_RSVD_3 = 0,30,2,0 %; literal TITAN_STR$S_RSVD_3 = 2; ! 31:30 reserved ! macro TITAN_STR$V_AW4 = 4,0,1,0 %; ! 32 Array Width macro TITAN_STR$V_IDDR4 = 4,1,3,0 %; literal TITAN_STR$S_IDDR4 = 3; ! 35:33 Issue to Data Delay for memory reads macro TITAN_STR$V_IDDW4 = 4,4,2,0 %; literal TITAN_STR$S_IDDW4 = 2; ! 37:36 Issue to Data Delay for xactions other than memory reads macro TITAN_STR$V_RSVD_4 = 4,6,2,0 %; literal TITAN_STR$S_RSVD_4 = 2; ! 39:38 reserved ! macro TITAN_STR$V_AW5 = 4,8,1,0 %; ! 40 Array Width macro TITAN_STR$V_IDDR5 = 4,9,3,0 %; literal TITAN_STR$S_IDDR5 = 3; ! 43:41 Issue to Data Delay for memory reads macro TITAN_STR$V_IDDW5 = 4,12,2,0 %; literal TITAN_STR$S_IDDW5 = 2; ! 45:44 Issue to Data Delay for xactions other than memory reads macro TITAN_STR$V_RSVD_5 = 4,14,2,0 %; literal TITAN_STR$S_RSVD_5 = 2; ! 47:46 reserved ! macro TITAN_STR$V_AW6 = 4,16,1,0 %; ! 48 Array Width macro TITAN_STR$V_IDDR6 = 4,17,3,0 %; literal TITAN_STR$S_IDDR6 = 3; ! 51:49 Issue to Data Delay for memory reads macro TITAN_STR$V_IDDW6 = 4,20,2,0 %; literal TITAN_STR$S_IDDW6 = 2; ! 53:52 Issue to Data Delay for xactions other than memory reads macro TITAN_STR$V_RSVD_6 = 4,22,2,0 %; literal TITAN_STR$S_RSVD_6 = 2; ! 55:54 reserved ! macro TITAN_STR$V_AW7 = 4,24,1,0 %; ! 56 Array Width macro TITAN_STR$V_IDDR7 = 4,25,3,0 %; literal TITAN_STR$S_IDDR7 = 3; ! 59:57 Issue to Data Delay for memory reads macro TITAN_STR$V_IDDW7 = 4,28,2,0 %; literal TITAN_STR$S_IDDW7 = 2; ! 61:60 Issue to Data Delay for xactions other than memory reads macro TITAN_STR$V_RSVD_7 = 4,30,2,0 %; literal TITAN_STR$S_RSVD_7 = 2; ! 63:62 reserved ! ! ! Titan DREV - D-Chip System Configuration Register ! literal TITAN_DREV$M_REV0 = %X'F'; literal TITAN_DREV$M_RSVD_0 = %X'F0'; literal TITAN_DREV$M_REV1 = %X'F00'; literal TITAN_DREV$M_RSVD_1 = %X'F000'; literal TITAN_DREV$M_REV2 = %X'F0000'; literal TITAN_DREV$M_RSVD_2 = %X'F00000'; literal TITAN_DREV$M_REV3 = %X'F000000'; literal TITAN_DREV$M_RSVD_3 = %X'F0000000'; literal TITAN_DREV$M_REV4 = %X'F00000000'; literal TITAN_DREV$M_RSVD_4 = %X'F000000000'; literal TITAN_DREV$M_REV5 = %X'F0000000000'; literal TITAN_DREV$M_RSVD_5 = %X'F00000000000'; literal TITAN_DREV$M_REV6 = %X'F000000000000'; literal TITAN_DREV$M_RSVD_6 = %X'F0000000000000'; literal TITAN_DREV$M_REV7 = %X'F00000000000000'; literal TITAN_DREV$M_RSVD_7 = %X'F000000000000000'; literal TITAN_DREV$S_TITAN_DREV = 8; macro TITAN_DREV$IQ_DATA = 0,0,0,0 %; literal TITAN_DREV$S_DATA = 8; macro TITAN_DREV$IL_L = 0,0,32,0 %; macro TITAN_DREV$IL_H = 4,0,32,0 %; macro TITAN_DREV$V_REV0 = 0,0,4,0 %; literal TITAN_DREV$S_REV0 = 4; ! 3:0 D-Chip 0 Revision macro TITAN_DREV$V_RSVD_0 = 0,4,4,0 %; literal TITAN_DREV$S_RSVD_0 = 4; ! 7:4 CPU 0 Clk Fwd Preset ! macro TITAN_DREV$V_REV1 = 0,8,4,0 %; literal TITAN_DREV$S_REV1 = 4; ! 11:8 D-Chip 1 Revision macro TITAN_DREV$V_RSVD_1 = 0,12,4,0 %; literal TITAN_DREV$S_RSVD_1 = 4; ! 15:12 CPU 1 Clk Fwd Preset ! macro TITAN_DREV$V_REV2 = 0,16,4,0 %; literal TITAN_DREV$S_REV2 = 4; ! 19:16 D-Chip 2 Revision macro TITAN_DREV$V_RSVD_2 = 0,20,4,0 %; literal TITAN_DREV$S_RSVD_2 = 4; ! 23:20 CPU 2 Clk Fwd Preset ! macro TITAN_DREV$V_REV3 = 0,24,4,0 %; literal TITAN_DREV$S_REV3 = 4; ! 27:24 D-Chip 3 Revision macro TITAN_DREV$V_RSVD_3 = 0,28,4,0 %; literal TITAN_DREV$S_RSVD_3 = 4; ! 31:28 CPU 3 Clk Fwd Preset ! macro TITAN_DREV$V_REV4 = 4,0,4,0 %; literal TITAN_DREV$S_REV4 = 4; ! 35:32 D-Chip 4 Revision macro TITAN_DREV$V_RSVD_4 = 4,4,4,0 %; literal TITAN_DREV$S_RSVD_4 = 4; ! 39:36 CPU 4 Clk Fwd Preset ! macro TITAN_DREV$V_REV5 = 4,8,4,0 %; literal TITAN_DREV$S_REV5 = 4; ! 43:40 D-Chip 5 Revision macro TITAN_DREV$V_RSVD_5 = 4,12,4,0 %; literal TITAN_DREV$S_RSVD_5 = 4; ! 47:44 CPU 5 Clk Fwd Preset ! macro TITAN_DREV$V_REV6 = 4,16,4,0 %; literal TITAN_DREV$S_REV6 = 4; ! 51:48 D-Chip 6 Revision macro TITAN_DREV$V_RSVD_6 = 4,20,4,0 %; literal TITAN_DREV$S_RSVD_6 = 4; ! 55:52 CPU 6 Clk Fwd Preset ! macro TITAN_DREV$V_REV7 = 4,24,4,0 %; literal TITAN_DREV$S_REV7 = 4; ! 59:56 D-Chip 7 Revision macro TITAN_DREV$V_RSVD_7 = 4,28,4,0 %; literal TITAN_DREV$S_RSVD_7 = 4; ! 63:60 CPU 7 Clk Fwd Preset ! ========================================================================== ! ! P-Chip Registers ! ! ========================================================================== ! ! ! Titan WSBA - P-Chip Window Space Base Address Registers ! literal TITAN_WSBA$M_ENA = %X'1'; literal TITAN_WSBA$M_SG = %X'2'; literal TITAN_WSBA$M_RSVD_0 = %X'FFFFC'; literal TITAN_WSBA$M_ADDR = %X'FFF00000'; literal TITAN_WSBA$M_RSVD_1 = %X'FFFFFFFF00000000'; literal TITAN_WSBA$S_TITAN_WSBA = 8; macro TITAN_WSBA$IQ_DATA = 0,0,0,0 %; literal TITAN_WSBA$S_DATA = 8; macro TITAN_WSBA$IL_L = 0,0,32,0 %; macro TITAN_WSBA$IL_H = 4,0,32,0 %; macro TITAN_WSBA$V_ENA = 0,0,1,0 %; ! 0 Enable macro TITAN_WSBA$V_SG = 0,1,1,0 %; ! 1 Scatter/Gather macro TITAN_WSBA$V_RSVD_0 = 0,2,18,0 %; literal TITAN_WSBA$S_RSVD_0 = 18; ! 19:2 reserved macro TITAN_WSBA$V_ADDR = 0,20,12,0 %; literal TITAN_WSBA$S_ADDR = 12; ! 31:20 Base Address macro TITAN_WSBA$V_RSVD_1 = 4,0,32,0 %; literal TITAN_WSBA$S_RSVD_1 = 32; ! 63:32 Reserved ! ! ! Titan WSM - P-Chip Window Space Mask Registers ! literal TITAN_WSM$M_RSVD_0 = %X'FFFFF'; literal TITAN_WSM$M_AM = %X'FFF00000'; literal TITAN_WSM$M_RSVD_1 = %X'FFFFFFFF00000000'; literal TITAN_WSM$S_TITAN_WSM = 8; macro TITAN_WSM$IQ_DATA = 0,0,0,0 %; literal TITAN_WSM$S_DATA = 8; macro TITAN_WSM$IL_L = 0,0,32,0 %; macro TITAN_WSM$IL_H = 4,0,32,0 %; macro TITAN_WSM$V_RSVD_0 = 0,0,20,0 %; literal TITAN_WSM$S_RSVD_0 = 20; ! 19:0 reserved macro TITAN_WSM$V_AM = 0,20,12,0 %; literal TITAN_WSM$S_AM = 12; ! 31:20 Base Address macro TITAN_WSM$V_RSVD_1 = 4,0,32,0 %; literal TITAN_WSM$S_RSVD_1 = 32; ! 63:32 Reserved ! ! ! Titan TBA - P-Chip Translated Base Address Registers ! literal TITAN_TBA$M_RSVD_0 = %X'3FF'; literal TITAN_TBA$M_ADDR = %X'7FFFFFC00'; literal TITAN_TBA$M_RSVD_1 = %X'FFFFFFF800000000'; literal TITAN_TBA$S_TITAN_TBA = 8; macro TITAN_TBA$IQ_DATA = 0,0,0,0 %; literal TITAN_TBA$S_DATA = 8; macro TITAN_TBA$IL_L = 0,0,32,0 %; macro TITAN_TBA$IL_H = 4,0,32,0 %; macro TITAN_TBA$V_RSVD_0 = 0,0,10,0 %; literal TITAN_TBA$S_RSVD_0 = 10; ! 9:0 reserved macro TITAN_TBA$V_ADDR = 0,10,25,0 %; literal TITAN_TBA$S_ADDR = 25; ! 34:10 Translated Base Address macro TITAN_TBA$V_RSVD_1 = 4,3,29,0 %; literal TITAN_TBA$S_RSVD_1 = 29; ! 63:35 reserved ! ! ! Titan PCTL - P-Chip Gport Control Register ! literal TITAN_PCTL$M_FBTB = %X'1'; literal TITAN_PCTL$M_THDIS = %X'2'; literal TITAN_PCTL$M_CHAINDIS = %X'4'; literal TITAN_PCTL$M_TGTLAT = %X'18'; literal TITAN_PCTL$M_HOLE = %X'20'; literal TITAN_PCTL$M_MWIN = %X'40'; literal TITAN_PCTL$M_ARBENA = %X'80'; literal TITAN_PCTL$M_PRIGRP = %X'FF00'; literal TITAN_PCTL$M_PPRI = %X'10000'; literal TITAN_PCTL$M_PCISPD66 = %X'20000'; literal TITAN_PCTL$M_CNGSTLT = %X'3C0000'; literal TITAN_PCTL$M_PTPDESTEN = %X'3FC00000'; literal TITAN_PCTL$M_DPCEN = %X'40000000'; literal TITAN_PCTL$M_APCEN = %X'80000000'; literal TITAN_PCTL$M_DCRTV = %X'300000000'; literal TITAN_PCTL$M_EN_STEPPING = %X'400000000'; literal TITAN_PCTL$M_AGP_RATE = %X'30000000000000'; literal TITAN_PCTL$M_AGP_SBA_ENABLE = %X'40000000000000'; literal TITAN_PCTL$M_AGP_ENABLE = %X'80000000000000'; literal TITAN_PCTL$M_AGP_PRESENT = %X'200000000000000'; literal TITAN_PCTL$M_AGP_HP_RD = %X'1C00000000000000'; literal TITAN_PCTL$M_AGP_LP_RD = %X'E000000000000000'; literal TITAN_PCTL$S_TITAN_PCTL = 8; macro TITAN_PCTL$IQ_DATA = 0,0,0,0 %; literal TITAN_PCTL$S_DATA = 8; macro TITAN_PCTL$IL_L = 0,0,32,0 %; macro TITAN_PCTL$IL_H = 4,0,32,0 %; macro TITAN_PCTL$V_FBTB = 0,0,1,0 %; ! 0 Fast Back-To-Back enable macro TITAN_PCTL$V_THDIS = 0,1,1,0 %; ! 1 Disable anti-Thrash mechanism for TLB macro TITAN_PCTL$V_CHAINDIS = 0,2,1,0 %; ! 2 Disable Chaining macro TITAN_PCTL$V_TGTLAT = 0,3,2,0 %; literal TITAN_PCTL$S_TGTLAT = 2; ! 4:3 Target Latency Timers timers enable macro TITAN_PCTL$V_HOLE = 0,5,1,0 %; ! 5 512K to 1M window Hole enable macro TITAN_PCTL$V_MWIN = 0,6,1,0 %; ! 6 Monster Window enable macro TITAN_PCTL$V_ARBENA = 0,7,1,0 %; ! 7 internal Arbiter Enable macro TITAN_PCTL$V_PRIGRP = 0,8,8,0 %; literal TITAN_PCTL$S_PRIGRP = 8; ! 15:8 arbiter Priority Group macro TITAN_PCTL$V_PPRI = 0,16,1,0 %; ! 16 arbiter Priority Group for the Pchip itself macro TITAN_PCTL$V_PCISPD66 = 0,17,1,0 %; ! 17 A '1' indicates GPCI frequency is 66 MHz macro TITAN_PCTL$V_CNGSTLT = 0,18,4,0 %; literal TITAN_PCTL$S_CNGSTLT = 4; ! 21:18 GPCI congestion limit macro TITAN_PCTL$V_PTPDESTEN = 0,22,8,0 %; literal TITAN_PCTL$S_PTPDESTEN = 8; ! 29:22 Bit mask enables legal PTP transactions macro TITAN_PCTL$V_DPCEN = 0,30,1,0 %; ! 30 set to '1' enables checking parity on PCI data xfers macro TITAN_PCTL$V_APCEN = 0,31,1,0 %; ! 31 set to '1' enables checking parity during address command cycles ! macro TITAN_PCTL$V_DCRTV = 4,0,2,0 %; literal TITAN_PCTL$S_DCRTV = 2; ! 33:32 contols value of delayed completion retry timer macro TITAN_PCTL$V_EN_STEPPING = 4,2,1,0 %; ! 34 enables address stepping on the PCI during config cycles macro TITAN_PCTL$V_RSVD_1 = 4,3,17,0 %; literal TITAN_PCTL$S_RSVD_1 = 17; ! 51:35 Reserved macro TITAN_PCTL$V_AGP_RATE = 4,20,2,0 %; literal TITAN_PCTL$S_AGP_RATE = 2; ! AGP RATE 1X, 2X, 4X macro TITAN_PCTL$V_AGP_SBA_ENABLE = 4,22,1,0 %; ! AGP SBA ENABLE macro TITAN_PCTL$V_AGP_ENABLE = 4,23,1,0 %; ! AGP ENABLE macro TITAN_PCTL$V_RSVD_2 = 4,24,1,0 %; ! RESERVED FIELD macro TITAN_PCTL$V_AGP_PRESENT = 4,25,1,0 %; ! AGP PRESENT macro TITAN_PCTL$V_AGP_HP_RD = 4,26,3,0 %; literal TITAN_PCTL$S_AGP_HP_RD = 3; ! AGP HIGH PRIORITY READ DE macro TITAN_PCTL$V_AGP_LP_RD = 4,29,3,0 %; literal TITAN_PCTL$S_AGP_LP_RD = 3; ! AGP LOW PRIORITY READ DEP ! ! ! Titan PLAT - P-Chip Master Latency Register ! literal TITAN_PLAT$M_RSVD_0 = %X'FF'; literal TITAN_PLAT$M_LAT = %X'FF00'; literal TITAN_PLAT$M_RSVD_1 = %X'FFFF0000'; literal TITAN_PLAT$M_RSVD_2 = %X'FFFFFFFF00000000'; literal TITAN_PLAT$S_TITAN_PLAT = 8; macro TITAN_PLAT$IQ_DATA = 0,0,0,0 %; literal TITAN_PLAT$S_DATA = 8; macro TITAN_PLAT$IL_L = 0,0,32,0 %; macro TITAN_PLAT$IL_H = 4,0,32,0 %; macro TITAN_PLAT$V_RSVD_0 = 0,0,8,0 %; literal TITAN_PLAT$S_RSVD_0 = 8; ! 7:0 reserved macro TITAN_PLAT$V_LAT = 0,8,8,0 %; literal TITAN_PLAT$S_LAT = 8; ! 15:8 Master Latency Timer macro TITAN_PLAT$V_RSVD_1 = 0,16,16,0 %; literal TITAN_PLAT$S_RSVD_1 = 16; ! 31:16 reserved macro TITAN_PLAT$V_RSVD_2 = 4,0,32,0 %; literal TITAN_PLAT$S_RSVD_2 = 32; ! 63:32 reserved ! ! ! Titan PERROR - P-Chip Error Register ! literal TITAN_PERROR$M_LOST = %X'1'; literal TITAN_PERROR$M_SERR = %X'2'; literal TITAN_PERROR$M_PERR = %X'4'; literal TITAN_PERROR$M_DCRTO = %X'8'; literal TITAN_PERROR$M_SGE = %X'10'; literal TITAN_PERROR$M_APE = %X'20'; literal TITAN_PERROR$M_TA = %X'40'; literal TITAN_PERROR$M_DPE = %X'80'; literal TITAN_PERROR$M_NDS = %X'100'; literal TITAN_PERROR$M_IPTPR = %X'200'; literal TITAN_PERROR$M_IPTPW = %X'400'; literal TITAN_PERROR$M_RSVD_0 = %X'3800'; literal TITAN_PERROR$M_ADDR = %X'3FFFFFFFC000'; literal TITAN_PERROR$M_DAC = %X'400000000000'; literal TITAN_PERROR$M_MWIN = %X'800000000000'; literal TITAN_PERROR$M_RSVD_1 = %X'7000000000000'; literal TITAN_PERROR$M_CMD = %X'78000000000000'; literal TITAN_PERROR$M_RSVD_2 = %X'7F80000000000000'; literal TITAN_PERROR$S_TITAN_PERROR = 8; macro TITAN_PERROR$IQ_DATA = 0,0,0,0 %; literal TITAN_PERROR$S_DATA = 8; macro TITAN_PERROR$IL_L = 0,0,32,0 %; macro TITAN_PERROR$IL_H = 4,0,32,0 %; macro TITAN_PERROR$V_LOST = 0,0,1,0 %; ! 0 Lost an error macro TITAN_PERROR$V_SERR = 0,1,1,0 %; ! 1 SERR# sampled asserted macro TITAN_PERROR$V_PERR = 0,2,1,0 %; ! 2 PERR# sampled asserted as PCI master macro TITAN_PERROR$V_DCRTO = 0,3,1,0 %; ! 3 delayed completion retry timeout as PCI target macro TITAN_PERROR$V_SGE = 0,4,1,0 %; ! 4 Scatter/Gather had invalid PTE macro TITAN_PERROR$V_APE = 0,5,1,0 %; ! 5 Address Parity Error detected as potential PCI target macro TITAN_PERROR$V_TA = 0,6,1,0 %; ! 6 Targed Abort as PCI master macro TITAN_PERROR$V_DPE = 0,7,1,0 %; ! 7 PCI Read Data Parity Error as PCI master macro TITAN_PERROR$V_NDS = 0,8,1,0 %; ! 8 No DevSel as PCI master macro TITAN_PERROR$V_IPTPR = 0,9,1,0 %; ! 9 Invalid Peer-to-peer write macro TITAN_PERROR$V_IPTPW = 0,10,1,0 %; ! 10 Invalid Peep-to-peer read macro TITAN_PERROR$V_RSVD_0 = 0,11,3,0 %; literal TITAN_PERROR$S_RSVD_0 = 3; ! 13:11 reserved macro TITAN_PERROR$V_ADDR = 0,14,32,0 %; literal TITAN_PERROR$S_ADDR = 32; ! 46:14 contain longword PCI address macro TITAN_PERROR$V_DAC = 4,14,1,0 %; ! 47 Erroneous DAC macro TITAN_PERROR$V_MWIN = 4,15,1,0 %; ! 48 Erroneous access to Monster Window macro TITAN_PERROR$V_RSVD_1 = 4,16,3,0 %; literal TITAN_PERROR$S_RSVD_1 = 3; ! 51:49 Rreserved macro TITAN_PERROR$V_CMD = 4,19,4,0 %; literal TITAN_PERROR$S_CMD = 4; ! 55:52 PCI Command on error macro TITAN_PERROR$V_RSVD_2 = 4,23,8,0 %; literal TITAN_PERROR$S_RSVD_2 = 8; ! 63:56 Reserved ! ! ! Titan PERREN - P-Chip Error Enable Register ! literal TITAN_PERREN$M_RSVD_O = %X'1'; literal TITAN_PERREN$M_SERR = %X'2'; literal TITAN_PERREN$M_PERR = %X'4'; literal TITAN_PERREN$M_DCRTO = %X'8'; literal TITAN_PERREN$M_SGE = %X'10'; literal TITAN_PERREN$M_APE = %X'20'; literal TITAN_PERREN$M_TA = %X'40'; literal TITAN_PERREN$M_DPE = %X'80'; literal TITAN_PERREN$M_NDS = %X'100'; literal TITAN_PERREN$M_IPTPR = %X'200'; literal TITAN_PERREN$M_IPTPW = %X'400'; literal TITAN_PERREN$M_RSVD_1 = %X'FFFFF800'; literal TITAN_PERREN$M_RSVD_2 = %X'FFFFFFFF00000000'; literal TITAN_PERREN$S_TITAN_PERREN = 8; macro TITAN_PERREN$IQ_DATA = 0,0,0,0 %; literal TITAN_PERREN$S_DATA = 8; macro TITAN_PERREN$IL_L = 0,0,32,0 %; macro TITAN_PERREN$IL_H = 4,0,32,0 %; macro TITAN_PERREN$V_RSVD_O = 0,0,1,0 %; ! 0 Reserved macro TITAN_PERREN$V_SERR = 0,1,1,0 %; ! 1 Enable logging of SERR macro TITAN_PERREN$V_PERR = 0,2,1,0 %; ! 2 Enable logging of PERR macro TITAN_PERREN$V_DCRTO = 0,3,1,0 %; ! 3 Enable logging of DCRTO macro TITAN_PERREN$V_SGE = 0,4,1,0 %; ! 4 Scatter/Gather had invalid PTE macro TITAN_PERREN$V_APE = 0,5,1,0 %; ! 5 Enable detection of Address Parity Error macro TITAN_PERREN$V_TA = 0,6,1,0 %; ! 6 Enable logging of Targed Abort macro TITAN_PERREN$V_DPE = 0,7,1,0 %; ! 7 Enable detection of parity errors on the PCI macro TITAN_PERREN$V_NDS = 0,8,1,0 %; ! 8 Enable logging of "No DevSel as PCI master"' macro TITAN_PERREN$V_IPTPR = 0,9,1,0 %; ! 9 Enable logging of IPTPR if this bit set macro TITAN_PERREN$V_IPTPW = 0,10,1,0 %; ! 10 Enable logging of IPTPW if this bit set macro TITAN_PERREN$V_RSVD_1 = 0,11,21,0 %; literal TITAN_PERREN$S_RSVD_1 = 21; ! 31:11 reserved macro TITAN_PERREN$V_RSVD_2 = 4,0,32,0 %; literal TITAN_PERREN$S_RSVD_2 = 32; ! 63:32 Reserved ! ! ! Titan TLBIV - P-Chip Translation Buffer Invalidate Virtual Register ! literal TITAN_TLBIV$M_RSVD_0 = %X'F'; literal TITAN_TLBIV$M_ADDR = %X'FFFF0'; literal TITAN_TLBIV$M_RSVD_1 = %X'FFF00000'; literal TITAN_TLBIV$M_RSVD_2 = %X'FFFFFFFF00000000'; literal TITAN_TLBIV$S_TITAN_TLBIV = 8; macro TITAN_TLBIV$IQ_DATA = 0,0,0,0 %; literal TITAN_TLBIV$S_DATA = 8; macro TITAN_TLBIV$IL_L = 0,0,32,0 %; macro TITAN_TLBIV$IL_H = 4,0,32,0 %; macro TITAN_TLBIV$V_RSVD_0 = 0,0,4,0 %; literal TITAN_TLBIV$S_RSVD_0 = 4; ! 3:0 reserved macro TITAN_TLBIV$V_ADDR = 0,4,16,0 %; literal TITAN_TLBIV$S_ADDR = 16; ! 19:4 invalidate if matches PCI addr<31:16> macro TITAN_TLBIV$V_RSVD_1 = 0,20,12,0 %; literal TITAN_TLBIV$S_RSVD_1 = 12; ! 31:20 reserved macro TITAN_TLBIV$V_RSVD_2 = 4,0,32,0 %; literal TITAN_TLBIV$S_RSVD_2 = 32; ! 63:32 reserved ! ! ! Titan TLBIA - P-Chip Translation Buffer Invalidate all Register ! literal TITAN_TLBIA$S_TITAN_TLBIA = 8; macro TITAN_TLBIA$IQ_DATA = 0,0,0,0 %; literal TITAN_TLBIA$S_DATA = 8; macro TITAN_TLBIA$IL_L = 0,0,32,0 %; macro TITAN_TLBIA$IL_H = 4,0,32,0 %; !*** MODULE $TLBDEF *** ! ! Definitions for the first TLB insertion register and VHPT short format ! literal TLB$M_P = %X'1'; literal TLB$M_MBZ0 = %X'2'; literal TLB$M_MA = %X'1C'; literal TLB$M_A = %X'20'; literal TLB$M_D = %X'40'; literal TLB$M_PL = %X'180'; literal TLB$M_AR = %X'E00'; literal TLB$M_PPN = %X'3FFFFFFFFF000'; literal TLB$M_MBZ1 = %X'C000000000000'; literal TLB$M_ED = %X'10000000000000'; literal TLB$M_IGN0 = %X'FFE0000000000000'; literal TLB$M_ATTR = %X'7F'; literal TLB$M_PROT = %X'F80'; literal TLB$S_TLB = 8; macro TLB$R_TLB_UNION = 0,0,0,0 %; literal TLB$S_TLB_UNION = 8; macro TLB$Q_VHPT_SHORT = 0,0,0,0 %; literal TLB$S_VHPT_SHORT = 8; macro TLB$Q_PTE0 = 0,0,0,0 %; literal TLB$S_PTE0 = 8; macro TLB$V_P = 0,0,1,0 %; ! Present bit macro TLB$V_MBZ0 = 0,1,1,0 %; ! Reserved TLB{1:1} (MBZ) macro TLB$V_MA = 0,2,3,0 %; literal TLB$S_MA = 3; ! Memory Attribute macro TLB$V_A = 0,5,1,0 %; ! Accessed bit macro TLB$V_D = 0,6,1,0 %; ! Dirty bit macro TLB$V_PL = 0,7,2,0 %; literal TLB$S_PL = 2; ! Privilege level macro TLB$V_AR = 0,9,3,0 %; literal TLB$S_AR = 3; ! Access Rights macro TLB$V_PPN = 0,12,38,0 %; literal TLB$S_PPN = 38; ! Physical page number macro TLB$V_MBZ1 = 4,18,2,0 %; literal TLB$S_MBZ1 = 2; ! Reserved bits TLB{51:50} macro TLB$V_ED = 4,20,1,0 %; ! Exception deferral macro TLB$V_ATTR = 0,0,7,0 %; literal TLB$S_ATTR = 7; ! Attribute bits macro TLB$V_PROT = 0,7,5,0 %; literal TLB$S_PROT = 5; ! Protection bits !*** MODULE $TLVDEF *** ! Define the layout of a general purpose type-length-value structure which is ! used to pass a variety of data structures around the cluster. literal TLV$K_MAX_ORB_LENGTH = 13312; literal TLV$K_MAX_ARB_LENGTH = 8448; ! 8360 rounded up to %x2100 literal TLV$K_MAX_IDENTIFIERS = 1024; ! maximum number of rights IDs literal TLV$S_CHECKSUM = 8; ! header minus checksum literal TLV$K_MSG_HDR_LENGTH = 24; ! message header length literal TLV$K_VERSION_1 = 1; ! version number 1 literal TLV$K_VERSION_2 = 2; ! version number 2 (Blade) literal TLV$K_CURRENT_VERSION = 2; ! current protocol literal TLV$K_GRANULARITY = 7; ! allocation granularity literal TLV$S_HEADER = 24; macro TLV$L_CHECKSUM = 0,0,32,0 %; ! checksum (includes header) macro TLV$L_UNUSED_L1 = 4,0,32,0 %; ! start of checksum macro TLV$L_MSG_SIZE = 8,0,32,0 %; ! message size macro TLV$W_MSG_COUNT = 12,0,16,0 %; ! # of packets in message macro TLV$B_VERSION = 14,0,8,0 %; ! TLV protocol version number macro TLV$Q_SECURITY_DOMAIN = 16,0,0,0 %; literal TLV$S_SECURITY_DOMAIN = 8; ! security domain ($KGBDEF) literal TLV$K_PKT_HDR_LENGTH = 4; ! packet header length literal TLV$S_PACKET = 8; macro TLV$W_TYPE = 0,0,16,0 %; ! packet type macro TLV$W_LENGTH = 2,0,16,0 %; ! packet length (including packet header) macro TLV$R_VALUE = 4,0,32,0 %; ! offset to start of data !*** MODULE $TMCDEF *** literal TMC$K_SYNCH = 0; ! $SYNCH honor TM_ACTIVE literal TMC$K_SETEF = 1; ! Set event flag ignore TM_ACTIVE literal TMC$K_WFL = 2; ! $WFLAND and $WFLOR honor TM_ACTIVE literal TMC$K_SET_CTX = 3; ! Set synch context ignore TM_ACTIVE literal TMC$K_HIBER = 4; ! $HIBER honor TM_ACTIVE literal TMC$K_WAKE = 5; ! $WAKE ignore TM_ACTIVE literal TMC$K_PFW = 6; ! Pagefault wait honor TM_ACTIVE literal TMC$K_PFC = 7; ! Pagefault complete ignore TM_ACTIVE literal TMC$K_IMW = 8; ! Inner mode Semaphore wait honor TM_ACTIVE literal TMC$K_IMF = 9; ! Inner mode Semaphore free ignore TM_ACTIVE literal TMC$K_EXIT = 10; ! $EXIT honor TM_ACTIVE literal TMC$K_FORCEX = 11; ! $FORCEX ignore TM_ACTIVE literal TMC$K_SETAST = 12; ! $SETAST honor TM_ACTIVE literal TMC$K_UAST = 13; ! User mode AST ignore TM_ACTIVE literal TMC$K_SYNCH_CTX = 14; ! Synch with context honor TM_ACTIVE literal TMC$K_QUANTUM = 15; ! Thread quantum ignore TM_ACTIVE literal TMC$K_NUM_TYPES = 16; ! Number of callback types literal TMC$K_HIGHEST_TYPE = 15; literal TMC$K_WFLOR = 0; ! $WFLOR callback literal TMC$K_WFLAND = 1; ! $WFLAND callback literal TMC$S_TMC = 128; macro TMC$Q_SYNCH = 0,0,0,1 %; literal TMC$S_SYNCH = 8; ! $SYNCH macro TMC$Q_SETEF = 8,0,0,1 %; literal TMC$S_SETEF = 8; ! Set event flag macro TMC$Q_WFL = 16,0,0,1 %; literal TMC$S_WFL = 8; ! $WFLAND and $WFLOR macro TMC$Q_SET_CTX = 24,0,0,1 %; literal TMC$S_SET_CTX = 8; ! Set synch context macro TMC$Q_HIBER = 32,0,0,1 %; literal TMC$S_HIBER = 8; ! $HIBER macro TMC$Q_WAKE = 40,0,0,1 %; literal TMC$S_WAKE = 8; ! $WAKE macro TMC$Q_PFW = 48,0,0,1 %; literal TMC$S_PFW = 8; ! Pagefault wait macro TMC$Q_PFC = 56,0,0,1 %; literal TMC$S_PFC = 8; ! Pagefault complete macro TMC$Q_IMW = 64,0,0,1 %; literal TMC$S_IMW = 8; ! Inner mode Semaphore wait macro TMC$Q_IMF = 72,0,0,1 %; literal TMC$S_IMF = 8; ! Inner mode Semaphore free macro TMC$Q_EXIT = 80,0,0,1 %; literal TMC$S_EXIT = 8; ! $EXIT macro TMC$Q_FORCEX = 88,0,0,1 %; literal TMC$S_FORCEX = 8; ! $FORCEX macro TMC$Q_SETAST = 96,0,0,1 %; literal TMC$S_SETAST = 8; ! $SETAST macro TMC$Q_UAST = 104,0,0,1 %; literal TMC$S_UAST = 8; ! User mode AST macro TMC$Q_SYNCH_CTX = 112,0,0,1 %; literal TMC$S_SYNCH_CTX = 8; ! $SYNCH with context macro TMC$Q_QUANTUM = 120,0,0,1 %; literal TMC$S_QUANTUM = 8; ! Thread quantum literal TMC$C_LENGTH = 128; ! Length of TMC literal TMC$K_LENGTH = 128; ! Length of TMC literal TMC$S_TMCDEF = 128; ! Old size name - synonym !*** MODULE $TQEDEF *** ! + ! TQE - TIME QUEUE ENTRY ! ! TIME QUEUE ENTRIES ARE UTILIZED TO SET TIMERS, WAKE UP PROCESSES, AND ! FOR INTERNAL SYSTEM SUBROUTINES. ! - literal TQE$M_TQTYPE = %X'3'; literal TQE$M_REPEAT = %X'4'; literal TQE$M_ABSOLUTE = %X'8'; literal TQE$M_CHK_CPUTIM = %X'10'; literal TQE$M_EXTENDED_FORMAT = %X'20'; literal TQE$M_ASTNODEL = %X'40'; literal TQE$M_RSRVD_7 = %X'80'; literal TQE$C_TMSNGL = 0; ! TIMER ENTRY SINGLE SHOT REQUEST literal TQE$C_SSREPT = 5; ! SYSTEM SUBROUTINE REPEAT REQUEST literal TQE$C_SSSNGL = 1; ! SYSTEM SUBROUTINE SINGLE SHOT REQUEST literal TQE$C_WKREPT = 6; ! WAKE ENTRY REPEAT REQUEST literal TQE$C_WKSNGL = 2; ! WAKE ENTRY SINGLE SHOT REQUEST literal TQE$S_TQEDEF = 64; ! Old size name - synonym literal TQE$S_TQE = 64; macro TQE$L_TQFL = 0,0,32,1 %; ! TIME QUEUE FORWARD LINK macro TQE$L_TQBL = 4,0,32,1 %; ! TIME QUEUE BACKWARD LINK macro TQE$W_SIZE = 8,0,16,0 %; ! SIZE OF TQE IN BYTES macro TQE$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE FOR TQE macro TQE$B_RQTYPE = 11,0,8,0 %; ! TIME QUEUE ENTRY TYPE macro TQE$V_TQTYPE = 11,0,2,0 %; literal TQE$S_TQTYPE = 2; ! TQE type (timer, subroutine, wake) macro TQE$V_REPEAT = 11,2,1,0 %; ! REPEAT REQUEST (1=YES) macro TQE$V_ABSOLUTE = 11,3,1,0 %; ! Absolute expiration time specified macro TQE$V_CHK_CPUTIM = 11,4,1,0 %; ! Process CPU time constrained request macro TQE$V_EXTENDED_FORMAT = 11,5,1,0 %; ! Extended AST fields included in size macro TQE$V_ASTNODEL = 11,6,1,0 %; ! Don't deallocate TQE/ACB after AST delivery macro TQE$V_RSRVD_7 = 11,7,1,0 %; ! Unused bit macro TQE$L_PID = 12,0,32,0 %; ! TIMER OR WAKE REQUEST PROCESS ID macro TQE$L_FPC = 12,0,32,1 %; ! TIMER SUBROUTINE ADDRESS macro TQE$L_AST = 16,0,32,1 %; ! ADDRESS OF AST ROUTINE macro TQE$L_ASTPRM = 20,0,32,0 %; ! AST PARAMETER macro TQE$Q_FR3 = 16,0,0,1 %; literal TQE$S_FR3 = 8; ! TIMER SUBROUTINE SAVED R3 macro TQE$Q_FR4 = 24,0,0,1 %; literal TQE$S_FR4 = 8; ! TIMER SUBROUTINE SAVED R4 macro TQE$Q_TIME = 32,0,0,0 %; literal TQE$S_TIME = 8; ! ABSOLUTE EXPIRATION TIME macro TQE$Q_DELTA = 40,0,0,0 %; literal TQE$S_DELTA = 8; ! DELTA REPEAT TIME macro TQE$L_RMOD = 48,0,32,0 %; ! ACCESS MODE OF REQUEST macro TQE$L_EFN = 52,0,32,0 %; ! EVENT FLAG NUMBER AND EVENT GROUP macro TQE$L_RQPID = 56,0,32,0 %; ! REQUESTER PROCESS ID macro TQE$L_CPUTIM = 60,0,32,0 %; ! Process CPU time at which entry becomes due ! TIME QUEUE ENTRY REQUEST TYPE DEFINITIONS literal TQE$K_LENGTH = 64; ! LENGTH OF STANDARD TQE literal TQE$C_LENGTH = 64; ! LENGTH OF STANDARD TQE ! ! ! Extended version of TQE to support a 64-bit ACB if it is embedded in this ! structure. Basically, the original TQE format remains the same as before, ! but if the EXTENDED_FORMAT bit is set in RQTYPE, the extra ACB quadwords ! are included in the structure and the internal ACB is configured to look ! like the 64-bit extended version with a valid flags longword. ! literal TQE64$M_TQTYPE = %X'3'; literal TQE64$M_REPEAT = %X'4'; literal TQE64$M_ABSOLUTE = %X'8'; literal TQE64$M_CHK_CPUTIM = %X'10'; literal TQE64$M_EXTENDED_FORMAT = %X'20'; literal TQE64$M_ASTNODEL = %X'40'; literal TQE64$C_TMSNGL = 0; ! TIMER ENTRY SINGLE SHOT REQUEST literal TQE64$C_SSREPT = 5; ! SYSTEM SUBROUTINE REPEAT REQUEST literal TQE64$C_SSSNGL = 1; ! SYSTEM SUBROUTINE SINGLE SHOT REQUEST literal TQE64$C_WKREPT = 6; ! WAKE ENTRY REPEAT REQUEST literal TQE64$C_WKSNGL = 2; ! WAKE ENTRY SINGLE SHOT REQUEST literal TQE64$S_TQEDEF = 88; ! Size name - synonym literal TQE64$S_TQE64 = 88; macro TQE64$L_TQFL = 0,0,32,1 %; ! TIME QUEUE FORWARD LINK macro TQE64$L_TQBL = 4,0,32,1 %; ! TIME QUEUE BACKWARD LINK macro TQE64$W_SIZE = 8,0,16,0 %; ! SIZE OF TQE IN BYTES macro TQE64$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE FOR TQE macro TQE64$B_RQTYPE = 11,0,8,0 %; ! TIME QUEUE ENTRY TYPE macro TQE64$V_TQTYPE = 11,0,2,0 %; literal TQE64$S_TQTYPE = 2; ! TQE type (timer, subroutine, wake) macro TQE64$V_REPEAT = 11,2,1,0 %; ! REPEAT REQUEST (1=YES) macro TQE64$V_ABSOLUTE = 11,3,1,0 %; ! Absolute expiration time specified macro TQE64$V_CHK_CPUTIM = 11,4,1,0 %; ! Process CPU time constrained request macro TQE64$V_EXTENDED_FORMAT = 11,5,1,0 %; ! Extended AST fields included in size macro TQE64$V_ASTNODEL = 11,6,1,0 %; ! Don't deallocate TQE/ACB after AST delivery macro TQE64$L_PID = 12,0,32,0 %; ! TIMER OR WAKE REQUEST PROCESS ID macro TQE64$L_FPC = 12,0,32,1 %; ! TIMER SUBROUTINE ADDRESS macro TQE64$L_ACB64X = 16,0,32,0 %; ! OFFSET TO ACB64X STRUCTURE macro TQE64$Q_FR3 = 16,0,0,1 %; literal TQE64$S_FR3 = 8; ! TIMER SUBROUTINE SAVED R3 macro TQE64$Q_FR4 = 24,0,0,1 %; literal TQE64$S_FR4 = 8; ! TIMER SUBROUTINE SAVED R4 macro TQE64$Q_TIME = 32,0,0,0 %; literal TQE64$S_TIME = 8; ! ABSOLUTE EXPIRATION TIME macro TQE64$Q_DELTA = 40,0,0,0 %; literal TQE64$S_DELTA = 8; ! DELTA REPEAT TIME macro TQE64$L_RMOD = 48,0,32,0 %; ! ACCESS MODE OF REQUEST macro TQE64$L_EFN = 52,0,32,0 %; ! EVENT FLAG NUMBER AND EVENT GROUP macro TQE64$L_RQPID = 56,0,32,0 %; ! REQUESTER PROCESS ID macro TQE64$L_CPUTIM = 60,0,32,0 %; ! Process CPU time at which entry becomes due macro TQE64$PQ_AST = 64,0,0,1 %; literal TQE64$S_AST = 8; ! 64-bit AST address macro TQE64$Q_ASTPRM = 72,0,0,0 %; literal TQE64$S_ASTPRM = 8; ! 64-bit ASTPRM value macro TQE64$Q_USER_THREAD_ID = 80,0,0,0 %; literal TQE64$S_USER_THREAD_ID = 8; ! Unique thread-specific identifier ! TIME QUEUE ENTRY REQUEST TYPE DEFINITIONS literal TQE64$K_LENGTH = 88; ! Length of 64-bit TQE literal TQE64$C_LENGTH = 88; ! Length of 64-bit TQE !*** MODULE $TQEIDXDEF *** ! + ! TQEIDX - Timer queue entry index ! ! Timer queue entries are maintained in an index structure. ! - literal TQEIDX$K_MAP_WIDTH = 6; ! Width literal TQEIDX$C_MAP_WIDTH = 6; ! of bitmap literal TQEIDX$K_MAX_WIDTH = 6; ! Maximum width allowed by structure literal TQEIDX$C_MAX_WIDTH = 6; ! Maximum width allowed by structure literal TQEIDX$K_MAXIDX = 64; ! Number of pointers in one literal TQEIDX$C_MAXIDX = 64; ! index bucket (= bits in bitmap) literal TQEIDX$C_LENGTH = 800; ! Size literal TQEIDX$K_LENGTH = 800; ! Size literal TQEIDX$S_TQEDEF = 800; ! Size (synonym) literal TQEIDX$S_TQEIDX = 800; macro TQEIDX$L_FLINK = 0,0,32,1 %; ! Forward link to next bucket (zero terminated) macro TQEIDX$L_BLINK = 4,0,32,1 %; ! Back link to previous bucket (zero terminated) macro TQEIDX$W_SIZE = 8,0,16,0 %; ! Size of this structure macro TQEIDX$B_TYPE = 10,0,8,0 %; ! (misc) macro TQEIDX$B_SUBTYPE = 11,0,8,0 %; ! (tqeidx) macro TQEIDX$L_LEVEL = 12,0,32,1 %; ! Index level macro TQEIDX$L_FREECNT = 16,0,32,1 %; ! Number of free array entries macro TQEIDX$L_PARENT = 20,0,32,1 %; ! Pointer to parent bucket macro TQEIDX$Q_BITMAP = 24,0,0,0 %; literal TQEIDX$S_BITMAP = 8; ! Free space bitmap; ! Min: 2 (1@2 - 1 = 3 entries per bucket) ! Max: 6 (1@6 - 1 = 63 entries per bucket) ! Cannot exceed 64 (size of bitmap = 1 quad) macro TQEIDX$Q_KEY = 32,0,0,0 %; literal TQEIDX$S_KEY = 512; ! Array of ordered keys macro TQEIDX$PS_PTR = 544,0,0,1 %; literal TQEIDX$S_PTR = 256; ! Array of pointers to target element ! or next level bucket !*** MODULE $TRDDEF *** literal TRD$M_VALID = %X'1'; literal TRD$M_PL = %X'6'; literal TRD$M_AR = %X'38'; literal TRD$M_RESERVED_1 = %X'FFFFFFC0'; literal TRD$M_RESERVED_2 = %X'FFFFFFFF00000000'; literal TRD$C_LENGTH = 32; literal TRD$S_TRD = 32; macro TRD$R_TRD_UNION = 0,0,0,0 %; literal TRD$S_TRD_UNION = 8; macro TRD$Q_FLAGS = 0,0,0,0 %; literal TRD$S_FLAGS = 8; macro TRD$V_VALID = 0,0,1,0 %; ! Valid macro TRD$V_PL = 0,1,2,0 %; literal TRD$S_PL = 2; ! Privilege level macro TRD$V_AR = 0,3,3,0 %; literal TRD$S_AR = 3; ! Access Rights macro TRD$PQ_VA = 8,0,0,1 %; literal TRD$S_VA = 8; ! Virtual address macro TRD$Q_PA = 16,0,0,0 %; literal TRD$S_PA = 8; ! Physical address macro TRD$L_PS = 24,0,32,0 %; ! Page size bits ! ! These symbols are used to define which TRs are used for what purposes. ! Note: there are both instruction and data translation registers. So, ! we distinguish which TR the constant is for by putting ITR or DTR in ! the symbol name. ! literal TRD$C_DTR_VHPT1 = 0; ! 1st DTR used for the VHPT literal TRD$C_DTR_VHPT2 = 1; ! 2nd DTR used for the VHPT literal TRD$C_IVT_SWIS1 = 5; ! ITR used for the IVT and SWIS literal TRD$C_IVT_SWIS2 = 6; ! 2nd ITR used for the IVT and SWIS (if necessary) literal TRD$C_DTR_SLOT_VA = 7; ! DTR used for the slot virtual address literal TRD$C_ITR_PAL_CODE = 7; ! ITR used for PAL code literal TRD$C_DTR_SWIS_DATA = 8; ! DTR used for SWIS data ! ! Minimum number of TRs supported by the IA64 architecture ! literal TRD$C_MIN_TRS = 8; ! ! Page size for PAL's TR ! literal TRD$C_PAL_PS = 18; ! 256K !*** MODULE $TSRVDEF *** ! + ! TSRV ( ) Definitions ! ! This module defines the main data structure of the TMSCP ! server. This structure contains the values specified in ! the start up qualifiers when the server was loaded, the ! UQB vector table, and statistics that are kept for server ! performance measurements. ! ! This structure is being checked in with fields aligned ! to the MSCP structure DSRV. This is not a requirement ! and may be changed in the future if necessary. ! ! <<== !NOTICE! ==>> ! ! DO NOT change offsets of the top part of the data structure. ! If new fields have to be added please make them below the ! forward and backward links to the UQB. ! - ! Max number of served units literal TSRV$M_LOG_ENABLD = %X'1'; literal TSRV$M_LOG_PRESENT = %X'2'; literal TSRV$M_PKT_LOGGED = %X'4'; literal TSRV$M_PKT_LOST = %X'8'; literal TSRV$M_LBSTEP1 = %X'10'; literal TSRV$M_LBSTEP2 = %X'20'; literal TSRV$M_LBEVENT = %X'40'; literal TSRV$M_HULB_DEL = %X'80'; literal TSRV$M_MON_ACTIVE = %X'100'; literal TSRV$M_LB_REQ = %X'200'; literal TSRV$C_LENGTH = 1912; literal TSRV$K_LENGTH = 1912; literal TSRV$K_AR_ADD = 2; ! Action routine code literal TSRV$K_MAX_UNITS = 256; literal TSRV$S_TSRV = 1912; macro TSRV$L_FLINK = 0,0,32,1 %; ! Field maintained for macro TSRV$L_BLINK = 4,0,32,1 %; ! compatability macro TSRV$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro TSRV$B_TYPE = 10,0,8,0 %; ! MSCP type structure macro TSRV$B_SUBTYPE = 11,0,8,0 %; ! with a TSRV subtype (1) macro TSRV$W_STATE = 12,0,16,0 %; ! Current state of the server macro TSRV$V_LOG_ENABLD = 12,0,1,0 %; ! Logging is enabled macro TSRV$V_LOG_PRESENT = 12,1,1,0 %; ! Logging code is present macro TSRV$V_PKT_LOGGED = 12,2,1,0 %; ! A packet has been logged macro TSRV$V_PKT_LOST = 12,3,1,0 %; ! One or more packets over- ! written since last read macro TSRV$V_LBSTEP1 = 12,4,1,0 %; ! Load balancing step1 active macro TSRV$V_LBSTEP2 = 12,5,1,0 %; ! Load balancing step2 active macro TSRV$V_LBEVENT = 12,6,1,0 %; ! An event of interest to LB has ! occured while STEP1 was active macro TSRV$V_HULB_DEL = 12,7,1,0 %; ! One or more HULBs to be deleted macro TSRV$V_MON_ACTIVE = 12,8,1,0 %; ! The load monitor thread is active macro TSRV$V_LB_REQ = 12,9,1,0 %; ! A load balance request has been sent macro TSRV$W_BUFWAIT = 14,0,16,0 %; ! I/Os that had to wait macro TSRV$L_LOG_BUF_START = 16,0,32,1 %; ! Address of start of buffer macro TSRV$L_LOG_BUF_END = 20,0,32,1 %; ! Address of end of buffer macro TSRV$L_NEXT_READ = 24,0,32,1 %; ! Adrs of next packet to read macro TSRV$L_NEXT_WRITE = 28,0,32,1 %; ! Adrs of next packet to write macro TSRV$W_INC_LOLIM = 32,0,16,0 %; ! Low unit number to log macro TSRV$W_INC_HILIM = 34,0,16,0 %; ! High unit number to log macro TSRV$W_EXC_LOLIM = 36,0,16,0 %; ! Low unit number not to log macro TSRV$W_EXC_HILIM = 38,0,16,0 %; ! High unit number not to log macro TSRV$W_VERSION = 60,0,16,0 %; ! Server software version macro TSRV$W_CFLAGS = 62,0,16,0 %; ! Controller flags macro TSRV$W_CTIMO = 64,0,16,0 %; ! Controller timeout macro TSRV$Q_CTRL_ID = 68,0,0,0 %; literal TSRV$S_CTRL_ID = 8; ! Unique MSCP device identifier macro TSRV$W_NUM_HOST = 92,0,16,0 %; ! Count of hosts being served macro TSRV$W_NUM_UNIT = 94,0,16,0 %; ! Count of disks being served macro TSRV$L_HQB_FL = 96,0,32,1 %; ! Host queue block list head macro TSRV$L_HQB_BL = 100,0,32,1 %; ! macro TSRV$L_UQB_FL = 104,0,32,1 %; ! Unit queue block list head macro TSRV$L_UQB_BL = 108,0,32,1 %; ! macro TSRV$L_UNITS = 208,0,0,1 %; literal TSRV$S_UNITS = 1024; ! Table of UQB addresses ! ! new fields should be added here, after the UQB linkages ! ! ! Statistics gathering fields ! ! Two tables are maintained below. The first table is made up of the ! frequency count for each of the opcodes received since the server ! was loaded. The opcode is used as an index into the table to its own ! frequency count (the zeroeth element contains a total count). The ! second table is made up of the frequency counters for all the ! different sized block transfers. For this table, the size of the ! transfer is the index into the table. ! macro TSRV$L_OPCOUNT = 1232,0,32,0 %; ! Total operations count macro TSRV$L_ABORT_CNT = 1236,0,32,0 %; ! - 1 - macro TSRV$L_GET_CMD_CNT = 1240,0,32,0 %; ! - 2 - macro TSRV$L_GET_UNT_CNT = 1244,0,32,0 %; ! - 3 - macro TSRV$L_SET_CON_CNT = 1248,0,32,0 %; ! - 4 - macro TSRV$L_AVAIL_CNT = 1264,0,32,0 %; ! - 8 - macro TSRV$L_ONLIN_CNT = 1268,0,32,0 %; ! - 9 - macro TSRV$L_SET_UNT_CNT = 1272,0,32,0 %; ! - 10 - macro TSRV$L_DET_ACC_CNT = 1276,0,32,0 %; ! - 11 - macro TSRV$L_ACCES_CNT = 1296,0,32,0 %; ! - 16 - macro TSRV$L_CMP_CON_CNT = 1300,0,32,0 %; ! - 17 - macro TSRV$L_ERASE_CNT = 1304,0,32,0 %; ! - 18 - macro TSRV$L_FLUSH_CNT = 1308,0,32,0 %; ! - 19 - macro TSRV$L_REPLC_CNT = 1312,0,32,0 %; ! - 20 - macro TSRV$L_CMP_HST_CNT = 1360,0,32,0 %; ! - 32 - macro TSRV$L_READ_CNT = 1364,0,32,0 %; ! - 33 - macro TSRV$L_WRITE_CNT = 1368,0,32,0 %; ! - 34 - macro TSRV$L_VCFAIL_CNT = 1392,0,32,0 %; ! Count of VC failures macro TSRV$L_BLKCOUNT = 1396,0,0,0 %; literal TSRV$S_BLKCOUNT = 516; ! Counters for block xfer reqs !*** MODULE $TSUNAMIDEF *** ! ++ ! ! FACILITY: OpenVMS AXP System Macro Libraries ! ! ABSTRACT: ! ! This file defines the control and status registers of the Tsunami Chip ! Set (TCS), designed for use in EV6 based platforms. ! ! Because of the disparities in the address spaces for the various chips ! in the Tsunami Chip Set, and because there are one C-Chip, as many as ! eight D-Chips and as many as two P-Chips, the Tsunami Chip Set ! structure is defined as three distinct data stuctures, C_CHIP, D_CHIP, ! and P_CHIP. This simplifies the definition, but puts an extra burden on ! the programmer to use the correct base addresses for the three chips. ! ! The following table shows the regions for the Tsunami Chip Set address ! space. ! ! -------------------------------------------------------------------- ! Cchip Address Space ! -------------------------------------------------------------------- ! 801 0000 0000 1 GB TIG Bus, addr<5:0> = 0, single byte valid in ! quadword access, 16 MB accessible ! 801 a000 0000 256 MB Cchip CSRs, addr<5:0> = 0, quadword access ! -------------------------------------------------------------------- ! ! -------------------------------------------------------------------- ! Dchip Address Space ! -------------------------------------------------------------------- ! 801 b000 0000 256 MB Dchip CSRs, addr<5:0> = 0, all eight bytes in ! quadword access must be identical. ! -------------------------------------------------------------------- ! ! -------------------------------------------------------------------- ! Pchip-0 Address Space ! -------------------------------------------------------------------- ! 800 0000 0000 4 GB PCI Memory ! 801 8000 0000 256 MB CSRs, addr<5:0> = 0, quadword access ! 801 f800 0000 64 MB PCI IACK/Special ! 801 fc00 0000 32 MB PCI IO ! 801 fe00 0000 16 MB PCI config space ! -------------------------------------------------------------------- ! ! -------------------------------------------------------------------- ! Pchip-1 Address Space ! -------------------------------------------------------------------- ! 802 0000 0000 4 GB PCI Memory ! 803 8000 0000 256 MB CSRs, addr<5:0> = 0, quadword access ! 803 f800 0000 64 MB PCI IACK/Special ! 803 fc00 0000 32 MB PCI IO ! 803 fe00 0000 16 MB PCI config space ! -------------------------------------------------------------------- ! ! AUTHOR: ! ! Tony Camuso 14-Jan-1997 ! ! MODIFIED BY: ! ! X-3 TLC Tony Camuso 16-Dec-1998 ! Add constant for maximum supported CPUs ! ! X-2 PAJ1025 Paul A. Jacobi 12-Oct-1998 ! Rename DIR$ to CDIR$ to avoid conflict with other symbols. ! ! X-1 TLC Tony Camuso 14-Jan-1997 ! Initial entry. ! ! -- ! The maximum number of CPUs supported by the Tsunami chipset ! literal TSUNAMI$K_MAX_CPU = 4; literal TSUNAMI$C_MAX_CPU = 4; ! ! Since SDL currently doesn't support constants greater 2**32, the high-order ! bits (%X80x) have their own constants defined. ! ! Tsunami Chip Set CSR base addresses <63:32> (High longword) ! =========================================================== ! literal TSUNAMI$L_C_CHIP_H = 2049; literal TSUNAMI$L_D_CHIP_H = 2049; ! literal TSUNAMI$L_P0_CHIP_MEM_H = 2048; literal TSUNAMI$L_P0_CHIP_IO_H = 2049; literal TSUNAMI$L_P0_CHIP_CSR_H = 2049; ! literal TSUNAMI$L_P1_CHIP_MEM_H = 2050; literal TSUNAMI$L_P1_CHIP_IO_H = 2051; literal TSUNAMI$L_P1_CHIP_CSR_H = 2051; ! ! ! Tsunami Chip Set CSR base addresses <31:0> (Low longword) ! ========================================================= ! literal TSUNAMI$L_C_CHIP_L = -1610612736; ! Cchip literal TSUNAMI$L_D_CHIP_L = -1342177280; ! Dchip ! ! ! P-Chip ! ------ literal TSUNAMI$L_P_CHIP_MEM_L = 0; literal TSUNAMI$L_P_CHIP_IO_L = -67108864; literal TSUNAMI$L_P_CHIP_CSR_L = -2147483648; literal TSUNAMI$L_P_CHIP_IACK_L = -134217728; literal TSUNAMI$L_P_CHIP_CONFIG_L = -33554432; ! ! ! Tsunami Chip Set CSR offsets ! ================================================= ! ! ------------------------------------------------- ! C-Chip - base addr<63:32> = TSUNAMI$L_C_CHIP_H ! base addr<31:0> = TSUNAMI$L_C_CHIP_L ! ------------------------------------------------- literal TSUNAMI$L_CSC_L = 0; ! Cchip System Config literal TSUNAMI$L_MTR_L = 64; ! literal TSUNAMI$L_MISC_L = 128; ! literal TSUNAMI$L_MPD_L = 192; ! ! literal TSUNAMI$L_AAR0_L = 256; ! literal TSUNAMI$L_AAR1_L = 320; ! literal TSUNAMI$L_AAR2_L = 384; ! literal TSUNAMI$L_AAR3_L = 448; ! ! literal TSUNAMI$L_DIM0_L = 512; ! literal TSUNAMI$L_DIM1_L = 576; ! literal TSUNAMI$L_DIR0_L = 640; ! literal TSUNAMI$L_DIR1_L = 704; ! ! literal TSUNAMI$L_DRIR_L = 768; ! literal TSUNAMI$L_PRBEN_L = 832; ! literal TSUNAMI$L_IIC0_L = 896; ! literal TSUNAMI$L_IIC1_L = 960; ! ! literal TSUNAMI$L_MPR0_L = 1024; ! literal TSUNAMI$L_MPR1_L = 1088; ! literal TSUNAMI$L_MPR2_L = 1152; ! literal TSUNAMI$L_MPR3_L = 1216; ! ! literal TSUNAMI$L_MCTL_L = 1280; ! literal TSUNAMI$L_TTR_L = 1408; ! literal TSUNAMI$L_TDR_L = 1472; ! ! literal TSUNAMI$L_DIM2_L = 1536; ! literal TSUNAMI$L_DIM3_L = 1600; ! literal TSUNAMI$L_DIR2_L = 1664; ! literal TSUNAMI$L_DIR3_L = 1728; ! ! literal TSUNAMI$L_IIC2_L = 1792; ! literal TSUNAMI$L_IIC3_L = 1856; ! ! ! ! ----------------------------------------------------- ! D-Chip - base addr <63:32> = TSUNAMI$L_D_CHIP_H ! base addr <31:0> = TSUNAMI$L_D_CHIP_L ! ----------------------------------------------------- literal TSUNAMI$L_DSC_L = 2048; ! literal TSUNAMI$L_STR_L = 2112; ! literal TSUNAMI$L_DREV_L = 2176; ! ! ! ! ----------------------------------------------------- ! P-Chip - P0 base addr<63:32> = TSUNAMI$L_P0_CHIP_CSR_H ! P0 base addr<32:0> = TSUNAMI$L_P_CHIP_CSR_L ! ! P1 base addr<63:32> = TSUNAMI$L_P1_CHIP_CSR_H ! P1 base addr<32:0> = TSUNAMI$L_P_CHIP_CSR_L ! ----------------------------------------------------- literal TSUNAMI$L_WSBA0_L = 0; ! literal TSUNAMI$L_WSBA1_L = 64; ! literal TSUNAMI$L_WSBA2_L = 128; ! literal TSUNAMI$L_WSBA3_L = 192; ! ! literal TSUNAMI$L_WSMA0_L = 256; ! literal TSUNAMI$L_WSMA1_L = 320; ! literal TSUNAMI$L_WSMA2_L = 384; ! literal TSUNAMI$L_WSMA3_L = 448; ! ! literal TSUNAMI$L_TBA0_L = 512; ! literal TSUNAMI$L_TBA1_L = 576; ! literal TSUNAMI$L_TBA2_L = 640; ! literal TSUNAMI$L_TBA3_L = 704; ! ! literal TSUNAMI$L_PCTL_L = 768; ! literal TSUNAMI$L_PLAT_L = 832; ! ! literal TSUNAMI$L_P_RESERVED_1_L = 896; ! ! literal TSUNAMI$L_PERROR_L = 960; ! literal TSUNAMI$L_PERRMASK_L = 1024; ! literal TSUNAMI$L_PERRSET_L = 1088; ! ! literal TSUNAMI$L_TLBIV_L = 1152; ! literal TSUNAMI$L_TLBIA_L = 1216; ! ! literal TSUNAMI$L_PMONCTL_L = 1280; ! literal TSUNAMI$L_PMONCNT_L = 1344; ! ! ! ! ************************************************************************** ! ! Tsunami Chip Set Structures ! ! ************************************************************************** ! ! ========================================================================== ! ! C-CHIP Structure ! ========================================================================== literal C_CHIP$S_C_CHIP = 2048; ! ! 801.A000.000 ! ! CSC - C-Chip System Configuration Register ! macro C_CHIP$IQ_CSC = 0,0,0,0 %; literal C_CHIP$S_CSC = 8; ! ! 801.A000.0040 ! ! MTR - C-Chip Memory Timing Register ! macro C_CHIP$IQ_MTR = 64,0,0,0 %; literal C_CHIP$S_MTR = 8; ! ! 801.A000.0080 ! ! MISC - C-Chip Miscellaneous Register ! macro C_CHIP$IQ_MISC = 128,0,0,0 %; literal C_CHIP$S_MISC = 8; ! ! 801.A000.00C0 ! ! MPD - C-Chip Memory Presence Detect ! macro C_CHIP$IQ_MPD = 192,0,0,0 %; literal C_CHIP$S_MPD = 8; ! ! 801.A000.0100 ! ! AAR0 - C-Chip Array Address Register 0 ! macro C_CHIP$IQ_AAR0 = 256,0,0,0 %; literal C_CHIP$S_AAR0 = 8; ! ! 801.A000.0140 ! ! AAR1 - C-Chip Array Address Register 1 ! macro C_CHIP$IQ_AAR1 = 320,0,0,0 %; literal C_CHIP$S_AAR1 = 8; ! ! 801.A000.0180 ! ! AAR2 - C-Chip Array Address Register 2 ! macro C_CHIP$IQ_AAR2 = 384,0,0,0 %; literal C_CHIP$S_AAR2 = 8; ! ! 801.A000.01C0 ! ! AAR3 - C-Chip Array Address Register 3 ! macro C_CHIP$IQ_AAR3 = 448,0,0,0 %; literal C_CHIP$S_AAR3 = 8; ! ! 801.A000.0200 ! ! DIM0 - C-Chip Device Interrupt Mask Register 0 ! macro C_CHIP$IQ_DIM0 = 512,0,0,0 %; literal C_CHIP$S_DIM0 = 8; ! ! 801.A000.0240 ! ! DIM1 - C-Chip Device Interrupt Mask Register 1 ! macro C_CHIP$IQ_DIM1 = 576,0,0,0 %; literal C_CHIP$S_DIM1 = 8; ! ! 801.A000.0280 ! ! DIR0 - C-Chip Device Interrupt Request Register ! macro C_CHIP$IQ_DIR0 = 640,0,0,0 %; literal C_CHIP$S_DIR0 = 8; ! ! 801.A000.02C0 ! ! DIR1 - C-Chip Device Interrupt Request Register ! macro C_CHIP$IQ_DIR1 = 704,0,0,0 %; literal C_CHIP$S_DIR1 = 8; ! ! 801.A000.0300 ! ! DRIR - C-Chip Raw Interrupt Request Register ! macro C_CHIP$IQ_DRIR = 768,0,0,0 %; literal C_CHIP$S_DRIR = 8; ! ! 801.A000.0340 ! ! PRBEN - C-Chip Probe Enable Register ! macro C_CHIP$IQ_PRBEN = 832,0,0,0 %; literal C_CHIP$S_PRBEN = 8; ! ! 801.A000.0380 ! ! IIC0 - C-Chip Interval Ignore Count Register 0 ! macro C_CHIP$IQ_IIC0 = 896,0,0,0 %; literal C_CHIP$S_IIC0 = 8; ! ! 801.A000.03C0 ! ! IIC1 - C-Chip Interval Ignore Count Register 1 ! macro C_CHIP$IQ_IIC1 = 960,0,0,0 %; literal C_CHIP$S_IIC1 = 8; ! ! 801.A000.0400 ! ! MPR0 - C-Chip Memory Programming Register 0 ! macro C_CHIP$IQ_MPR0 = 1024,0,0,0 %; literal C_CHIP$S_MPR0 = 8; ! ! 801.A000.0440 ! ! MPR1 - C-Chip Memory Programming Register 1 ! macro C_CHIP$IQ_MPR1 = 1088,0,0,0 %; literal C_CHIP$S_MPR1 = 8; ! ! 801.A000.0480 ! ! MPR2 - C-Chip Memory Programming Register 2 ! macro C_CHIP$IQ_MPR2 = 1152,0,0,0 %; literal C_CHIP$S_MPR2 = 8; ! ! 801.A000.04C0 ! ! MPR3 - C-Chip Memory Programming Register 3 ! macro C_CHIP$IQ_MPR3 = 1216,0,0,0 %; literal C_CHIP$S_MPR3 = 8; ! ! 801.A000.0500 ! ! MCTL - C-Chip M-Port Control Register ! macro C_CHIP$IQ_MCTL = 1280,0,0,0 %; literal C_CHIP$S_MCTL = 8; ! ! 801.A000.0580 ! ! TTR - C-Chip TIG Bus Timing Register ! macro C_CHIP$IQ_TTR = 1408,0,0,0 %; literal C_CHIP$S_TTR = 8; ! ! 801.A000.05C0 ! ! TDR - C-Chip TIG Bus Device Timing Register ! macro C_CHIP$IQ_TDR = 1472,0,0,0 %; literal C_CHIP$S_TDR = 8; ! ! 801.A000.0600 ! ! DIM2 - C-Chip Device Interrupt Mask Register 2 ! macro C_CHIP$IQ_DIM2 = 1536,0,0,0 %; literal C_CHIP$S_DIM2 = 8; ! ! 801.A000.0640 ! ! DIM3 - C-Chip Device Interrupt Mask Register 3 ! macro C_CHIP$IQ_DIM3 = 1600,0,0,0 %; literal C_CHIP$S_DIM3 = 8; ! ! 801.A000.0680 ! ! DIR2 - C-Chip Device Interrupt Request Register 2 ! macro C_CHIP$IQ_DIR2 = 1664,0,0,0 %; literal C_CHIP$S_DIR2 = 8; ! ! 801.A000.06C0 ! ! DIR3 - C-Chip Device Interrupt Request Register 3 ! macro C_CHIP$IQ_DIR3 = 1728,0,0,0 %; literal C_CHIP$S_DIR3 = 8; ! ! 801.A000.0700 ! ! IIC2 - C-Chip Interval Ignore Count Register 2 ! macro C_CHIP$IQ_IIC2 = 1792,0,0,0 %; literal C_CHIP$S_IIC2 = 8; ! ! 801.A000.0740 ! ! IIC3 - C-Chip Interval Ignore Count Register 3 ! macro C_CHIP$IQ_IIC3 = 1856,0,0,0 %; literal C_CHIP$S_IIC3 = 8; ! ! ! ! ! ========================================================================== ! ! D-CHIP Structure ! ! NOTE: All the registers in this structure are abstracted as 64-bit entities. ! Therefore, they MUST be accessed and manipulated as quadwords and with ! quadwords. ! ! ========================================================================== literal D_CHIP$S_D_CHIP = 192; ! ! 801.B000.0800 ! ! DSC - D-Chip System Configuration Register ! macro D_CHIP$IQ_DSC = 0,0,0,0 %; literal D_CHIP$S_DSC = 8; ! ! 801.B000.0840 ! ! STR - D-Chip System Timing Register ! macro D_CHIP$IQ_STR = 64,0,0,0 %; literal D_CHIP$S_STR = 8; ! ! 801.B000.0880 ! ! DREV - D-Chip System Configuration Register ! macro D_CHIP$IQ_DREV = 128,0,0,0 %; literal D_CHIP$S_DREV = 8; ! ! ! ! ! ========================================================================== ! ! P-CHIP Structure ! ! In the addresses below, x = 1 for PChip-0 and x = 3 for PChip-1 ! ! ========================================================================== literal P_CHIP$S_P_CHIP = 1408; ! ! 80x.8000.0000 ! ! WSBA0 - P-CHip Window Space Base Address Register 0 ! macro P_CHIP$IQ_WSBA0 = 0,0,0,0 %; literal P_CHIP$S_WSBA0 = 8; ! ! 80x.8000.0040 ! ! WSBA1 - P-CHip Window Space Base Address Register 1 ! macro P_CHIP$IQ_WSBA1 = 64,0,0,0 %; literal P_CHIP$S_WSBA1 = 8; ! ! 80x.8000.0080 ! ! WSBA2 - P-CHip Window Space Base Address Register 2 ! macro P_CHIP$IQ_WSBA2 = 128,0,0,0 %; literal P_CHIP$S_WSBA2 = 8; ! ! 80x.8000.00C0 ! ! WSBA3 - P-CHip Window Space Base Address Register 3 ! macro P_CHIP$IQ_WSBA3 = 192,0,0,0 %; literal P_CHIP$S_WSBA3 = 8; ! ! 80x.8000.0100 ! ! WSM0 - P-Chip Window Space Mask Register 0 ! macro P_CHIP$IQ_WSM0 = 256,0,0,0 %; literal P_CHIP$S_WSM0 = 8; ! ! 80x.8000.0140 ! ! WSM1 - P-Chip Window Space Mask Register 1 ! macro P_CHIP$IQ_WSM1 = 320,0,0,0 %; literal P_CHIP$S_WSM1 = 8; ! ! 80x.8000.0180 ! ! WSM2 - P-Chip Window Space Mask Register 2 ! macro P_CHIP$IQ_WSM2 = 384,0,0,0 %; literal P_CHIP$S_WSM2 = 8; ! ! 80x.8000.01C0 ! ! WSM3 - P-Chip Window Space Mask Register 3 ! macro P_CHIP$IQ_WSM3 = 448,0,0,0 %; literal P_CHIP$S_WSM3 = 8; ! ! 80x.8000.0200 ! ! TBA0 - P-Chip Translated Base Address Register 0 ! macro P_CHIP$IQ_TBA0 = 512,0,0,0 %; literal P_CHIP$S_TBA0 = 8; ! ! 80x.8000.0240 ! ! TBA1 - P-Chip Translated Base Address Register 1 ! macro P_CHIP$IQ_TBA1 = 576,0,0,0 %; literal P_CHIP$S_TBA1 = 8; ! ! 80x.8000.0280 ! ! TBA2 - P-Chip Translated Base Address Register 2 ! macro P_CHIP$IQ_TBA2 = 640,0,0,0 %; literal P_CHIP$S_TBA2 = 8; ! ! 80x.8000.02C0 ! ! TBA3 - P-Chip Translated Base Address Register 3 ! macro P_CHIP$IQ_TBA3 = 704,0,0,0 %; literal P_CHIP$S_TBA3 = 8; ! ! 80x.8000.0300 ! ! PCTL - P-Chip Control Register ! macro P_CHIP$IQ_PCTL = 768,0,0,0 %; literal P_CHIP$S_PCTL = 8; ! ! 80x.8000.0340 ! ! PLAT - P-Chip Master Latency Register ! macro P_CHIP$IQ_PLAT = 832,0,0,0 %; literal P_CHIP$S_PLAT = 8; ! ! 80x.8000.0380 ! ! P_RESERVED_1 - P-Chip Reserved Register 1 ! macro P_CHIP$IQ_P_RESERVED_1 = 896,0,0,0 %; literal P_CHIP$S_P_RESERVED_1 = 8; ! ! 80x.8000.03C0 ! ! PERROR - P-Chip Error Register ! macro P_CHIP$IQ_PERROR = 960,0,0,0 %; literal P_CHIP$S_PERROR = 8; ! ! 80x.8000.0400 ! ! PERRMASK - P-Chip Error Mask Register ! macro P_CHIP$IQ_PERRMASK = 1024,0,0,0 %; literal P_CHIP$S_PERRMASK = 8; ! ! 80x.8000.0440 ! ! PERRSET - P-Chip Error Set Register ! macro P_CHIP$IQ_PERRSET = 1088,0,0,0 %; literal P_CHIP$S_PERRSET = 8; ! ! 80x.8000.0480 ! ! TLBIV - P-Chip Translation Buffer Invalidate Virtual Register ! macro P_CHIP$IQ_TLBIV = 1152,0,0,0 %; literal P_CHIP$S_TLBIV = 8; ! ! 80x.8000.04C0 ! ! TLBIA - P-Chip Translation Buffer Invalidate all Register ! macro P_CHIP$IQ_TLBIA = 1216,0,0,0 %; literal P_CHIP$S_TLBIA = 8; ! ! 80x.8000.0500 ! ! PMONCTL - P-Chip Monitor Control Register ! macro P_CHIP$IQ_PMONCTL = 1280,0,0,0 %; literal P_CHIP$S_PMONCTL = 8; ! ! 80x.8000.05C0 ! ! PMONCNT - P-Chip Monitor Counters Register ! macro P_CHIP$IQ_PMONCNT = 1344,0,0,0 %; literal P_CHIP$S_PMONCNT = 8; ! ************************************************************************** ! ! Bit Definitions for the Tsunami Chip Set Registers ! ! ************************************************************************** ! ========================================================================== ! ! C-Chip Registers ! ! ========================================================================== ! ! ! CSC - C-Chip System Configuration Register ! literal CSC$M_BC = %X'3'; literal CSC$M_C0CFP = %X'4'; literal CSC$M_C1CFP = %X'8'; literal CSC$M_SED = %X'30'; literal CSC$M_SFD = %X'40'; literal CSC$M_FW = %X'80'; literal CSC$M_AW = %X'100'; literal CSC$M_IDDR = %X'E00'; literal CSC$M_IDDW = %X'3000'; literal CSC$M_P1P = %X'4000'; literal CSC$M_RSVD_0 = %X'8000'; literal CSC$M_DWTP = %X'30000'; literal CSC$M_DWFP = %X'C0000'; literal CSC$M_DRTP = %X'300000'; literal CSC$M_RSVD_1 = %X'C00000'; literal CSC$M_PME = %X'1000000'; literal CSC$M_QPM = %X'2000000'; literal CSC$M_FET = %X'C000000'; literal CSC$M_QDI = %X'70000000'; literal CSC$M_EFT = %X'80000000'; literal CSC$M_FTI = %X'100000000'; literal CSC$M_B1D = %X'200000000'; literal CSC$M_B2D = %X'400000000'; literal CSC$M_B3D = %X'800000000'; literal CSC$M_TPQMMAX = %X'7000000000'; literal CSC$M_RSVD_2 = %X'8000000000'; literal CSC$M_FPQCMAX = %X'70000000000'; literal CSC$M_RSVD_3 = %X'80000000000'; literal CSC$M_FPQPMAX = %X'700000000000'; literal CSC$M_RSVD_4 = %X'800000000000'; literal CSC$M_PDTMAX = %X'7000000000000'; literal CSC$M_RSVD_5 = %X'8000000000000'; literal CSC$M_PRQMAX = %X'70000000000000'; literal CSC$M_RSVD_6 = %X'80000000000000'; literal CSC$M_PBQMAX = %X'700000000000000'; literal CSC$M_RSVD_7 = %X'F800000000000000'; literal CSC$S_CSC = 8; macro CSC$IQ_DATA = 0,0,0,0 %; literal CSC$S_DATA = 8; macro CSC$IL_L = 0,0,32,0 %; macro CSC$IL_H = 4,0,32,0 %; macro CSC$V_BC = 0,0,2,0 %; literal CSC$S_BC = 2; ! 1:0 Base Configuration macro CSC$V_C0CFP = 0,2,1,0 %; ! 2 CPU 0 Clk Fwd Preset macro CSC$V_C1CFP = 0,3,1,0 %; ! 3 CPU 1 Clk Fwd Preset macro CSC$V_SED = 0,4,2,0 %; literal CSC$S_SED = 2; ! 5:4 SysDC Extract Delay macro CSC$V_SFD = 0,6,1,0 %; ! 6 SysDC Fill Delay macro CSC$V_FW = 0,7,1,0 %; ! 7 available for firmware macro CSC$V_AW = 0,8,1,0 %; ! 8 Array Width macro CSC$V_IDDR = 0,9,3,0 %; literal CSC$S_IDDR = 3; ! 11:9 Issue to Data Delay on read macro CSC$V_IDDW = 0,12,2,0 %; literal CSC$S_IDDW = 2; ! 13:12 Issue to Data Delay for all xactions macro CSC$V_P1P = 0,14,1,0 %; ! 14 P-Chip 1 present macro CSC$V_RSVD_0 = 0,15,1,0 %; ! 15 reserved macro CSC$V_DWTP = 0,16,2,0 %; literal CSC$S_DWTP = 2; ! 17:16 Min Dchip Delay from CPU to PAD bus macro CSC$V_DWFP = 0,18,2,0 %; literal CSC$S_DWFP = 2; ! 19:18 Min Dchip Delay from PADbus to CPU or Memory macro CSC$V_DRTP = 0,20,2,0 %; literal CSC$S_DRTP = 2; ! 21:20 Min Dchip Delay from Memory to PAD bus macro CSC$V_RSVD_1 = 0,22,2,0 %; literal CSC$S_RSVD_1 = 2; ! 23:22 reserved macro CSC$V_PME = 0,24,1,0 %; ! 24 Page Mode Enable macro CSC$V_QPM = 0,25,1,0 %; ! 25 Que Priority Mode macro CSC$V_FET = 0,26,2,0 %; literal CSC$S_FET = 2; ! 27:26 Fill to Extract Turnaround cycles macro CSC$V_QDI = 0,28,3,0 %; literal CSC$S_QDI = 3; ! 30:28 Que Drain Interval macro CSC$V_EFT = 0,31,1,0 %; ! 31 Extract to Fill Turnaround cycles ! macro CSC$V_FTI = 4,0,1,0 %; ! 32 Full Throttle Issue macro CSC$V_B1D = 4,1,1,0 %; ! 33 Bypass 1 Issue Path Disable macro CSC$V_B2D = 4,2,1,0 %; ! 34 Bypass 2 Issue Path Disable macro CSC$V_B3D = 4,3,1,0 %; ! 35 Bypass 3 Issue Path Disable macro CSC$V_TPQMMAX = 4,4,3,0 %; literal CSC$S_TPQMMAX = 3; ! 38:36 Max entries in TPQM on D-Chips, mod 8 macro CSC$V_RSVD_2 = 4,7,1,0 %; ! 39 reserved macro CSC$V_FPQCMAX = 4,8,3,0 %; literal CSC$S_FPQCMAX = 3; ! 42:40 Max entries in FQP, mod 8 macro CSC$V_RSVD_3 = 4,11,1,0 %; ! 43 reserved macro CSC$V_FPQPMAX = 4,12,3,0 %; literal CSC$S_FPQPMAX = 3; ! 46:44 Max entries in FPQ, mod 8 macro CSC$V_RSVD_4 = 4,15,1,0 %; ! 47 reserved macro CSC$V_PDTMAX = 4,16,3,0 %; literal CSC$S_PDTMAX = 3; ! 50:48 Max data xfers to one P-Chip until ack, mod 8 macro CSC$V_RSVD_5 = 4,19,1,0 %; ! 51 reserved macro CSC$V_PRQMAX = 4,20,3,0 %; literal CSC$S_PRQMAX = 3; ! 54:52 max reqests to one P-Chip until ack, mod 8 macro CSC$V_RSVD_6 = 4,23,1,0 %; ! 55 reserved macro CSC$V_PBQMAX = 4,24,3,0 %; literal CSC$S_PBQMAX = 3; ! 58:56 Max CPU probe queue macro CSC$V_RSVD_7 = 4,27,5,0 %; literal CSC$S_RSVD_7 = 5; ! 63:59 reserved ! ! ! MTR - C-Chip Memory Timing Register ! literal MTR$M_RCD = %X'1'; literal MTR$M_RSVD_0 = %X'2'; literal MTR$M_CAT = %X'4'; literal MTR$M_RSVD_1 = %X'8'; literal MTR$M_IRD = %X'70'; literal MTR$M_RSVD_2 = %X'80'; literal MTR$M_RPW = %X'300'; literal MTR$M_RSVD_3 = %X'C00'; literal MTR$M_RPT = %X'3000'; literal MTR$M_RSVD_4 = %X'C000'; literal MTR$M_RRD = %X'10000'; literal MTR$M_RSVD_5 = %X'E0000'; literal MTR$M_MPD = %X'100000'; literal MTR$M_RSVD_6 = %X'E00000'; literal MTR$M_RI = %X'3F000000'; literal MTR$M_RSVD_7 = %X'C0000000'; literal MTR$M_PHCR = %X'F00000000'; literal MTR$M_PHCW = %X'F000000000'; literal MTR$M_MPH = %X'3F0000000000'; literal MTR$M_RSVD_8 = %X'FFFFC00000000000'; literal MTR$S_MTR = 8; macro MTR$IQ_DATA = 0,0,0,0 %; literal MTR$S_DATA = 8; macro MTR$IL_L = 0,0,32,0 %; macro MTR$IL_H = 4,0,32,0 %; macro MTR$V_RCD = 0,0,1,0 %; ! 0 RAS to CAS Delay macro MTR$V_RSVD_0 = 0,1,1,0 %; ! 1 reserved macro MTR$V_CAT = 0,2,1,0 %; ! 2 CAS Access Time macro MTR$V_RSVD_1 = 0,3,1,0 %; ! 3 reserved macro MTR$V_IRD = 0,4,3,0 %; literal MTR$S_IRD = 3; ! 6:4 Issue to RAS Delay macro MTR$V_RSVD_2 = 0,7,1,0 %; ! 7 reserved macro MTR$V_RPW = 0,8,2,0 %; literal MTR$S_RPW = 2; ! 9:8 Minimum RAS Pulse Width macro MTR$V_RSVD_3 = 0,10,2,0 %; literal MTR$S_RSVD_3 = 2; ! 11:10 reserved macro MTR$V_RPT = 0,12,2,0 %; literal MTR$S_RPT = 2; ! 13:12 Min RAS Precharge Time macro MTR$V_RSVD_4 = 0,14,2,0 %; literal MTR$S_RSVD_4 = 2; ! 15:14 reserved macro MTR$V_RRD = 0,16,1,0 %; ! 16 Min Same-Array_Diff-Bank RAS-to-RAS Delay macro MTR$V_RSVD_5 = 0,17,3,0 %; literal MTR$S_RSVD_5 = 3; ! 19:17 reserved macro MTR$V_MPD = 0,20,1,0 %; ! 20 Mask Pipeline Delay macro MTR$V_RSVD_6 = 0,21,3,0 %; literal MTR$S_RSVD_6 = 3; ! 23:21 reserved macro MTR$V_RI = 0,24,6,0 %; literal MTR$S_RI = 6; ! 29:24 Refresh Interval macro MTR$V_RSVD_7 = 0,30,2,0 %; literal MTR$S_RSVD_7 = 2; ! 31:30 reserved ! macro MTR$V_PHCR = 4,0,4,0 %; literal MTR$S_PHCR = 4; ! 35:32 Page Hit Cycles for Reads macro MTR$V_PHCW = 4,4,4,0 %; literal MTR$S_PHCW = 4; ! 39:36 Page Hit Cycles for Writes macro MTR$V_MPH = 4,8,6,0 %; literal MTR$S_MPH = 6; ! 45:40 Max Page Hits macro MTR$V_RSVD_8 = 4,14,18,0 %; literal MTR$S_RSVD_8 = 18; ! 63:46 reserved ! ! ! MISC - C-Chip Miscellaneous Register ! literal MISC$M_CPUID = %X'1'; literal MISC$M_RSVD_0 = %X'E'; literal MISC$M_ITINTR = %X'30'; literal MISC$M_RSVD_1 = %X'C0'; literal MISC$M_IPINTR = %X'300'; literal MISC$M_RSVD_2 = %X'C00'; literal MISC$M_IPREQ = %X'3000'; literal MISC$M_RSVD_3 = %X'C000'; literal MISC$M_ABW = %X'30000'; literal MISC$M_RSVD_4 = %X'C0000'; literal MISC$M_ABT = %X'300000'; literal MISC$M_RSVD_5 = %X'C00000'; literal MISC$M_ACL = %X'1000000'; literal MISC$M_RSVD_6 = %X'E000000'; literal MISC$M_NXM = %X'10000000'; literal MISC$M_NXS = %X'E0000000'; literal MISC$M_REV = %X'FF00000000'; literal MISC$M_DEVSUP = %X'30000000000'; literal MISC$M_RSVD_7 = %X'FFFFFC0000000000'; literal MISC$S_MISC = 8; macro MISC$V_CPUID = 0,0,1,0 %; ! 0 ID of CPU performing the read macro MISC$V_RSVD_0 = 0,1,3,0 %; literal MISC$S_RSVD_0 = 3; ! 3:1 reserved macro MISC$V_ITINTR = 0,4,2,0 %; literal MISC$S_ITINTR = 2; ! 5:4 Interval Timer Interrupt pending macro MISC$V_RSVD_1 = 0,6,2,0 %; literal MISC$S_RSVD_1 = 2; ! 7:6 reserved macro MISC$V_IPINTR = 0,8,2,0 %; literal MISC$S_IPINTR = 2; ! 9:8 Interprocessor Interrupt pending macro MISC$V_RSVD_2 = 0,10,2,0 %; literal MISC$S_RSVD_2 = 2; ! 11:10 reserved macro MISC$V_IPREQ = 0,12,2,0 %; literal MISC$S_IPREQ = 2; ! 13:12 Interprocessor Interrupt Request macro MISC$V_RSVD_3 = 0,14,2,0 %; literal MISC$S_RSVD_3 = 2; ! 15:14 reserved macro MISC$V_ABW = 0,16,2,0 %; literal MISC$S_ABW = 2; ! 17:16 Arbitration Won macro MISC$V_RSVD_4 = 0,18,2,0 %; literal MISC$S_RSVD_4 = 2; ! 19:18 reserved macro MISC$V_ABT = 0,20,2,0 %; literal MISC$S_ABT = 2; ! 21:20 Arbitration Try macro MISC$V_RSVD_5 = 0,22,2,0 %; literal MISC$S_RSVD_5 = 2; ! 23:22 reserved macro MISC$V_ACL = 0,24,1,0 %; ! 24 Arbitration Clear macro MISC$V_RSVD_6 = 0,25,3,0 %; literal MISC$S_RSVD_6 = 3; ! 27:25 reserved macro MISC$V_NXM = 0,28,1,0 %; ! 28 Non eXistent Memory macro MISC$V_NXS = 0,29,3,0 %; literal MISC$S_NXS = 3; ! 31:29 NXM Source ! macro MISC$V_REV = 4,0,8,0 %; literal MISC$S_REV = 8; ! 39:32 C-Chip Revision macro MISC$V_DEVSUP = 4,8,2,0 %; literal MISC$S_DEVSUP = 2; ! 41:40 Suppress IRQ[1] macro MISC$V_RSVD_7 = 4,10,22,0 %; literal MISC$S_RSVD_7 = 22; ! 63:42 reserved ! ! ! MPD - C-Chip Memory Presence Detect ! literal MPD$M_CKS = %X'1'; literal MPD$M_DS = %X'2'; literal MPD$M_CKR = %X'4'; literal MPD$M_DR = %X'8'; literal MPD$M_RSVD_0 = %X'FFFFFFF0'; literal MPD$M_RSVD_1 = %X'FFFFFFFF00000000'; literal MPD$S_MPD = 8; macro MPD$V_CKS = 0,0,1,0 %; ! 0 ClocK Send macro MPD$V_DS = 0,1,1,0 %; ! 1 Data Send macro MPD$V_CKR = 0,2,1,0 %; ! 2 ClocK Receive macro MPD$V_DR = 0,3,1,0 %; ! 3 Data Receive macro MPD$V_RSVD_0 = 0,4,28,0 %; literal MPD$S_RSVD_0 = 28; ! 31:4 reserved ! macro MPD$V_RSVD_1 = 4,0,32,0 %; literal MPD$S_RSVD_1 = 32; ! 63:32 reserved ! ! ! AAR - C-Chip Array Address Register ! literal AAR$M_BNKS = %X'1'; literal AAR$M_RSVD_0 = %X'2'; literal AAR$M_ROWS = %X'C'; literal AAR$M_RSVD_1 = %X'F0'; literal AAR$M_SA = %X'100'; literal AAR$M_RSVD_2 = %X'E00'; literal AAR$M_ASIZ = %X'7000'; literal AAR$M_RSVD_3 = %X'8000'; literal AAR$M_DBG = %X'10000'; literal AAR$M_RSVD_4 = %X'FE0000'; literal AAR$M_ADDR = %X'FF000000'; literal AAR$M_RSVD_5 = %X'FFFFFFFF00000000'; literal AAR$S_AAR = 8; macro AAR$IQ_DATA = 0,0,0,0 %; literal AAR$S_DATA = 8; macro AAR$IL_L = 0,0,32,0 %; macro AAR$IL_H = 4,0,32,0 %; macro AAR$V_BNKS = 0,0,1,0 %; ! 0 Number of Bank bits in DRAMs macro AAR$V_RSVD_0 = 0,1,1,0 %; ! 1 reserved macro AAR$V_ROWS = 0,2,2,0 %; literal AAR$S_ROWS = 2; ! 2 Number of Row bits in DRAMS macro AAR$V_RSVD_1 = 0,4,4,0 %; literal AAR$S_RSVD_1 = 4; ! 7:4 reserved macro AAR$V_SA = 0,8,1,0 %; ! 8 Split Array macro AAR$V_RSVD_2 = 0,9,3,0 %; literal AAR$S_RSVD_2 = 3; ! 11:9 reserved macro AAR$V_ASIZ = 0,12,3,0 %; literal AAR$S_ASIZ = 3; ! 14:12 Array Size macro AAR$V_RSVD_3 = 0,15,1,0 %; ! 15 reserved macro AAR$V_DBG = 0,16,1,0 %; ! 16 Enables this memory port as a debug interface macro AAR$V_RSVD_4 = 0,17,7,0 %; literal AAR$S_RSVD_4 = 7; ! 23:17 reserved macro AAR$V_ADDR = 0,24,8,0 %; literal AAR$S_ADDR = 8; ! 31:24 Base Address macro AAR$V_RSVD_5 = 4,0,32,0 %; literal AAR$S_RSVD_5 = 32; ! 63:32 reserved ! ! ! DIM - C-Chip Device Interrupt Mask Registers ! literal DIM$S_DIM = 8; macro DIM$IQ_DATA = 0,0,0,0 %; literal DIM$S_DATA = 8; macro DIM$IL_L = 0,0,32,0 %; macro DIM$IL_H = 4,0,32,0 %; ! ! ! DIR - C-Chip Device Interrupt Request Registers ! literal CDIR$M_DEV_L = %X'FFFFFFFF'; literal CDIR$M_DEV_H = %X'FFFFFF00000000'; literal CDIR$M_RSVD_0 = %X'300000000000000'; literal CDIR$M_ERR = %X'FC00000000000000'; literal CDIR$S_DIR = 8; macro CDIR$IQ_DATA = 0,0,0,0 %; literal CDIR$S_DATA = 8; macro CDIR$IL_L = 0,0,32,0 %; macro CDIR$IL_H = 4,0,32,0 %; macro CDIR$V_DEV_L = 0,0,32,0 %; literal CDIR$S_DEV_L = 32; ! 31:0 IRQ[1] PCI Interrupts Pending macro CDIR$V_DEV_H = 4,0,24,0 %; literal CDIR$S_DEV_H = 24; ! 55:32 IRQ[1] PCI Interrupts Pending macro CDIR$V_RSVD_0 = 4,24,2,0 %; literal CDIR$S_RSVD_0 = 2; ! 57:56 reserved macro CDIR$V_ERR = 4,26,6,0 %; literal CDIR$S_ERR = 6; ! 63:58 IRQ[0] Error Interrupts ! ! ! DRIR - C-Chip Raw Interrupt Request Register ! literal DRIR$S_DRIR = 8; macro DRIR$IQ_DATA = 0,0,0,0 %; literal DRIR$S_DATA = 8; macro DRIR$IL_L = 0,0,32,0 %; macro DRIR$IL_H = 4,0,32,0 %; ! ! ! PRBEN - C-Chip Probe Enable Register ! literal PRBEN$M_PRBEN = %X'1'; literal PRBEN$M_RSVD_0 = %X'FFFFFFFE'; literal PRBEN$M_RSVD_1 = %X'FFFFFFFF00000000'; literal PRBEN$S_PRBEN = 8; macro PRBEN$IQ_DATA = 0,0,0,0 %; literal PRBEN$S_DATA = 8; macro PRBEN$IL_L = 0,0,32,0 %; macro PRBEN$IL_H = 4,0,32,0 %; macro PRBEN$V_PRBEN = 0,0,1,0 %; ! 0 Probe Enable bit macro PRBEN$V_RSVD_0 = 0,1,31,0 %; literal PRBEN$S_RSVD_0 = 31; ! 31:1 Reserved macro PRBEN$V_RSVD_1 = 4,0,32,0 %; literal PRBEN$S_RSVD_1 = 32; ! 63:32 Reserved ! ! ! IIC - C-Chip Interval Ignore Count Registers ! literal IIC$M_ICNT = %X'FFFFFF'; literal IIC$M_OF = %X'1000000'; literal IIC$M_RSVD_0 = %X'FE000000'; literal IIC$M_RSVD_1 = %X'FFFFFFFF00000000'; literal IIC$S_IIC = 8; macro IIC$IQ_DATA = 0,0,0,0 %; literal IIC$S_DATA = 8; macro IIC$IL_L = 0,0,32,0 %; macro IIC$IL_H = 4,0,32,0 %; macro IIC$V_ICNT = 0,0,24,0 %; literal IIC$S_ICNT = 24; ! 23:0 Count of remaining interrupts to ignore macro IIC$V_OF = 0,24,1,0 %; ! 24 Overflow bit macro IIC$V_RSVD_0 = 0,25,7,0 %; literal IIC$S_RSVD_0 = 7; ! 31:25 reserved macro IIC$V_RSVD_1 = 4,0,32,0 %; literal IIC$S_RSVD_1 = 32; ! 63:32 reserved ! ! ! MPR - C-Chip Memory Programming Registers ! literal MPR$M_MPRDAT = %X'1FFF'; literal MPR$M_RSVD_0 = %X'FFFFE000'; literal MPR$M_RSVD_1 = %X'FFFFFFFF00000000'; literal MPR$S_MPR = 8; macro MPR$IQ_DATA = 0,0,0,0 %; literal MPR$S_DATA = 8; macro MPR$IL_L = 0,0,32,0 %; macro MPR$IL_H = 4,0,32,0 %; macro MPR$V_MPRDAT = 0,0,13,0 %; literal MPR$S_MPRDAT = 13; ! 12:0 Data to be written on address lines 12:0 macro MPR$V_RSVD_0 = 0,13,19,0 %; literal MPR$S_RSVD_0 = 19; ! 31:13 reserved macro MPR$V_RSVD_1 = 4,0,32,0 %; literal MPR$S_RSVD_1 = 32; ! 63:32 reserved ! ! ! MCTL - C-Chip M-Port Control Register ! literal MCTL$S_MCTL = 8; macro MCTL$IQ_DATA = 0,0,0,0 %; literal MCTL$S_DATA = 8; macro MCTL$IL_L = 0,0,32,0 %; macro MCTL$IL_H = 4,0,32,0 %; ! ! ! TTR - C-Chip TIG Bus Timing Register ! literal TTR$M_AS = %X'1'; literal TTR$M_AH = %X'2'; literal TTR$M_RSVD_0 = %X'C'; literal TTR$M_IS = %X'30'; literal TTR$M_RSVD_1 = %X'C0'; literal TTR$M_IRT = %X'300'; literal TTR$M_RSVD_2 = %X'C00'; literal TTR$M_ID = %X'7000'; literal TTR$M_RSVD_3 = %X'FFFF8000'; literal TTR$M_RSVD_4 = %X'FFFFFFFF00000000'; literal TTR$S_TTR = 8; macro TTR$V_AS = 0,0,1,0 %; ! 0 Address Setup to the address latch before AS macro TTR$V_AH = 0,1,1,0 %; ! 1 Address Hold after AS before CS_L macro TTR$V_RSVD_0 = 0,2,2,0 %; literal TTR$S_RSVD_0 = 2; ! 3:2 reserved macro TTR$V_IS = 0,4,2,0 %; literal TTR$S_IS = 2; ! 5:4 Interrupt Setup time macro TTR$V_RSVD_1 = 0,6,2,0 %; literal TTR$S_RSVD_1 = 2; ! 7:6 reserved macro TTR$V_IRT = 0,8,2,0 %; literal TTR$S_IRT = 2; ! 9:8 Interrupt Read Time macro TTR$V_RSVD_2 = 0,10,2,0 %; literal TTR$S_RSVD_2 = 2; ! 11:10 reserved macro TTR$V_ID = 0,12,3,0 %; literal TTR$S_ID = 3; ! 14:12 Interrupt starting Device macro TTR$V_RSVD_3 = 0,15,17,0 %; literal TTR$S_RSVD_3 = 17; ! 31:15 reserved macro TTR$V_RSVD_4 = 4,0,32,0 %; literal TTR$S_RSVD_4 = 32; ! 63:32 reserved ! ! ! TDR - C-Chip TIG Bus Device Timing Register ! literal TDR$M_RA0 = %X'F'; literal TDR$M_RD0 = %X'70'; literal TDR$M_RSVD_0 = %X'80'; literal TDR$M_WS0 = %X'300'; literal TDR$M_RSVD_1 = %X'C00'; literal TDR$M_WP0 = %X'7000'; literal TDR$M_WH0 = %X'8000'; literal TDR$M_RA1 = %X'F0000'; literal TDR$M_RD1 = %X'700000'; literal TDR$M_RSVD_2 = %X'800000'; literal TDR$M_WS1 = %X'3000000'; literal TDR$M_RSVD_3 = %X'C000000'; literal TDR$M_WP1 = %X'70000000'; literal TDR$M_WH1 = %X'80000000'; literal TDR$M_RA2 = %X'F00000000'; literal TDR$M_RD2 = %X'7000000000'; literal TDR$M_RSVD_4 = %X'8000000000'; literal TDR$M_WS2 = %X'30000000000'; literal TDR$M_RSVD_5 = %X'C0000000000'; literal TDR$M_WP2 = %X'700000000000'; literal TDR$M_WH2 = %X'800000000000'; literal TDR$M_RA3 = %X'F000000000000'; literal TDR$M_RD3 = %X'70000000000000'; literal TDR$M_RSVD_6 = %X'80000000000000'; literal TDR$M_WS3 = %X'300000000000000'; literal TDR$M_RSVD_7 = %X'C00000000000000'; literal TDR$M_WP3 = %X'7000000000000000'; literal TDR$M_WH3 = %X'8000000000000000'; literal TDR$S_TDR = 8; macro TDR$IQ_DATA = 0,0,0,0 %; literal TDR$S_DATA = 8; macro TDR$IL_L = 0,0,32,0 %; macro TDR$IL_H = 4,0,32,0 %; macro TDR$V_RA0 = 0,0,4,0 %; literal TDR$S_RA0 = 4; ! 3:0 Read Access time macro TDR$V_RD0 = 0,4,3,0 %; literal TDR$S_RD0 = 3; ! 6:4 Read output Disable time macro TDR$V_RSVD_0 = 0,7,1,0 %; ! 7 reserved macro TDR$V_WS0 = 0,8,2,0 %; literal TDR$S_WS0 = 2; ! 9:8 Write Setup time macro TDR$V_RSVD_1 = 0,10,2,0 %; literal TDR$S_RSVD_1 = 2; ! 11:10 reserved macro TDR$V_WP0 = 0,12,3,0 %; literal TDR$S_WP0 = 3; ! 14:12 Write Pulse width macro TDR$V_WH0 = 0,15,1,0 %; ! 15 Write Hold time ! macro TDR$V_RA1 = 0,16,4,0 %; literal TDR$S_RA1 = 4; ! 19:16 Read Access time macro TDR$V_RD1 = 0,20,3,0 %; literal TDR$S_RD1 = 3; ! 22:20 Read output Disable time macro TDR$V_RSVD_2 = 0,23,1,0 %; ! 23 reserved macro TDR$V_WS1 = 0,24,2,0 %; literal TDR$S_WS1 = 2; ! 25:24 Write Setup time macro TDR$V_RSVD_3 = 0,26,2,0 %; literal TDR$S_RSVD_3 = 2; ! 27:26 reserved macro TDR$V_WP1 = 0,28,3,0 %; literal TDR$S_WP1 = 3; ! 30:28 Write Pulse width macro TDR$V_WH1 = 0,31,1,0 %; ! 31 Write Hold time ! macro TDR$V_RA2 = 4,0,4,0 %; literal TDR$S_RA2 = 4; ! 35:32 Read Access time macro TDR$V_RD2 = 4,4,3,0 %; literal TDR$S_RD2 = 3; ! 38:36 Read output Disable time macro TDR$V_RSVD_4 = 4,7,1,0 %; ! 39 reserved macro TDR$V_WS2 = 4,8,2,0 %; literal TDR$S_WS2 = 2; ! 41:40 Write Setup time macro TDR$V_RSVD_5 = 4,10,2,0 %; literal TDR$S_RSVD_5 = 2; ! 43:42 reserved macro TDR$V_WP2 = 4,12,3,0 %; literal TDR$S_WP2 = 3; ! 46:44 Write Pulse width macro TDR$V_WH2 = 4,15,1,0 %; ! 47 Write Hold time ! macro TDR$V_RA3 = 4,16,4,0 %; literal TDR$S_RA3 = 4; ! 51:48 Read Access time macro TDR$V_RD3 = 4,20,3,0 %; literal TDR$S_RD3 = 3; ! 54:52 Read output Disable time macro TDR$V_RSVD_6 = 4,23,1,0 %; ! 55 reserved macro TDR$V_WS3 = 4,24,2,0 %; literal TDR$S_WS3 = 2; ! 57:56 Write Setup time macro TDR$V_RSVD_7 = 4,26,2,0 %; literal TDR$S_RSVD_7 = 2; ! 59:58 reserved macro TDR$V_WP3 = 4,28,3,0 %; literal TDR$S_WP3 = 3; ! 62:60 Write Pulse width macro TDR$V_WH3 = 4,31,1,0 %; ! 63 Write Hold time ! ========================================================================== ! ! D-Chip Registers ! ! ========================================================================== ! ! ! DSC - D-Chip System Configuration Register ! literal DSC$M_BC = %X'3'; literal DSC$M_C0CFP = %X'4'; literal DSC$M_C1CFP = %X'8'; literal DSC$M_C2CFP = %X'10'; literal DSC$M_C3CFP = %X'20'; literal DSC$M_P1P = %X'40'; literal DSC$M_RSVD_0 = %X'80'; literal DSC$M_BC1 = %X'300'; literal DSC$M_C0CFP1 = %X'400'; literal DSC$M_C1CFP1 = %X'800'; literal DSC$M_C2CFP1 = %X'1000'; literal DSC$M_C3CFP1 = %X'2000'; literal DSC$M_P1P1 = %X'4000'; literal DSC$M_RSVD_1 = %X'8000'; literal DSC$M_BC2 = %X'30000'; literal DSC$M_C0CFP2 = %X'40000'; literal DSC$M_C1CFP2 = %X'80000'; literal DSC$M_C2CFP2 = %X'100000'; literal DSC$M_C3CFP2 = %X'200000'; literal DSC$M_P1P2 = %X'400000'; literal DSC$M_RSVD_2 = %X'800000'; literal DSC$M_BC3 = %X'3000000'; literal DSC$M_C0CFP3 = %X'4000000'; literal DSC$M_C1CFP3 = %X'8000000'; literal DSC$M_C2CFP3 = %X'10000000'; literal DSC$M_C3CFP3 = %X'20000000'; literal DSC$M_P1P3 = %X'40000000'; literal DSC$M_RSVD_3 = %X'80000000'; literal DSC$M_BC4 = %X'300000000'; literal DSC$M_C0CFP4 = %X'400000000'; literal DSC$M_C1CFP4 = %X'800000000'; literal DSC$M_C2CFP4 = %X'1000000000'; literal DSC$M_C3CFP4 = %X'2000000000'; literal DSC$M_P1P4 = %X'4000000000'; literal DSC$M_RSVD_4 = %X'8000000000'; literal DSC$M_BC15 = %X'30000000000'; literal DSC$M_C0CFP5 = %X'40000000000'; literal DSC$M_C1CFP5 = %X'80000000000'; literal DSC$M_C2CFP5 = %X'100000000000'; literal DSC$M_C3CFP5 = %X'200000000000'; literal DSC$M_P1P5 = %X'400000000000'; literal DSC$M_RSVD_5 = %X'800000000000'; literal DSC$M_BC6 = %X'3000000000000'; literal DSC$M_C0CFP6 = %X'4000000000000'; literal DSC$M_C1CFP6 = %X'8000000000000'; literal DSC$M_C2CFP6 = %X'10000000000000'; literal DSC$M_C3CFP6 = %X'20000000000000'; literal DSC$M_P1P6 = %X'40000000000000'; literal DSC$M_RSVD_6 = %X'80000000000000'; literal DSC$M_BC7 = %X'300000000000000'; literal DSC$M_C0CFP7 = %X'400000000000000'; literal DSC$M_C1CFP7 = %X'800000000000000'; literal DSC$M_C2CFP7 = %X'1000000000000000'; literal DSC$M_C3CFP7 = %X'2000000000000000'; literal DSC$M_P1P7 = %X'4000000000000000'; literal DSC$M_RSVD_7 = %X'8000000000000000'; literal DSC$S_DSC = 8; macro DSC$IQ_DATA = 0,0,0,0 %; literal DSC$S_DATA = 8; macro DSC$IL_L = 0,0,32,0 %; macro DSC$IL_H = 4,0,32,0 %; macro DSC$V_BC = 0,0,2,0 %; literal DSC$S_BC = 2; ! 1:0 Base Configuration macro DSC$V_C0CFP = 0,2,1,0 %; ! 2 CPU 0 Clock Forward Preset macro DSC$V_C1CFP = 0,3,1,0 %; ! 3 CPU 0 Clock Forward Preset macro DSC$V_C2CFP = 0,4,1,0 %; ! 4 CPU 0 Clock Forward Preset macro DSC$V_C3CFP = 0,5,1,0 %; ! 5 CPU 0 Clock Forward Preset macro DSC$V_P1P = 0,6,1,0 %; ! 6 P-Chip_1 Preset macro DSC$V_RSVD_0 = 0,7,1,0 %; ! 7 reserved ! macro DSC$V_BC1 = 0,8,2,0 %; literal DSC$S_BC1 = 2; ! 9:8 Base Configuration macro DSC$V_C0CFP1 = 0,10,1,0 %; ! 10 CPU 0 Clock Forward Preset macro DSC$V_C1CFP1 = 0,11,1,0 %; ! 11 CPU 0 Clock Forward Preset macro DSC$V_C2CFP1 = 0,12,1,0 %; ! 12 CPU 0 Clock Forward Preset macro DSC$V_C3CFP1 = 0,13,1,0 %; ! 13 CPU 0 Clock Forward Preset macro DSC$V_P1P1 = 0,14,1,0 %; ! 14 P-Chip_1 Preset macro DSC$V_RSVD_1 = 0,15,1,0 %; ! 15 reserved ! macro DSC$V_BC2 = 0,16,2,0 %; literal DSC$S_BC2 = 2; ! 17:16 Base Configuration macro DSC$V_C0CFP2 = 0,18,1,0 %; ! 18 CPU 0 Clock Forward Preset macro DSC$V_C1CFP2 = 0,19,1,0 %; ! 19 CPU 0 Clock Forward Preset macro DSC$V_C2CFP2 = 0,20,1,0 %; ! 20 CPU 0 Clock Forward Preset macro DSC$V_C3CFP2 = 0,21,1,0 %; ! 21 CPU 0 Clock Forward Preset macro DSC$V_P1P2 = 0,22,1,0 %; ! 22 P-Chip_1 Preset macro DSC$V_RSVD_2 = 0,23,1,0 %; ! 23 reserved ! macro DSC$V_BC3 = 0,24,2,0 %; literal DSC$S_BC3 = 2; ! 25:24 Base Configuration macro DSC$V_C0CFP3 = 0,26,1,0 %; ! 26 CPU 0 Clock Forward Preset macro DSC$V_C1CFP3 = 0,27,1,0 %; ! 27 CPU 0 Clock Forward Preset macro DSC$V_C2CFP3 = 0,28,1,0 %; ! 28 CPU 0 Clock Forward Preset macro DSC$V_C3CFP3 = 0,29,1,0 %; ! 29 CPU 0 Clock Forward Preset macro DSC$V_P1P3 = 0,30,1,0 %; ! 30 P-Chip_1 Preset macro DSC$V_RSVD_3 = 0,31,1,0 %; ! 31 reserved ! macro DSC$V_BC4 = 4,0,2,0 %; literal DSC$S_BC4 = 2; ! 33:32 Base Configuration macro DSC$V_C0CFP4 = 4,2,1,0 %; ! 34 CPU 0 Clock Forward Preset macro DSC$V_C1CFP4 = 4,3,1,0 %; ! 35 CPU 0 Clock Forward Preset macro DSC$V_C2CFP4 = 4,4,1,0 %; ! 36 CPU 0 Clock Forward Preset macro DSC$V_C3CFP4 = 4,5,1,0 %; ! 37 CPU 0 Clock Forward Preset macro DSC$V_P1P4 = 4,6,1,0 %; ! 38 P-Chip_1 Preset macro DSC$V_RSVD_4 = 4,7,1,0 %; ! 39 reserved ! macro DSC$V_BC15 = 4,8,2,0 %; literal DSC$S_BC15 = 2; ! 41:40 Base Configuration macro DSC$V_C0CFP5 = 4,10,1,0 %; ! 42 CPU 0 Clock Forward Preset macro DSC$V_C1CFP5 = 4,11,1,0 %; ! 43 CPU 0 Clock Forward Preset macro DSC$V_C2CFP5 = 4,12,1,0 %; ! 44 CPU 0 Clock Forward Preset macro DSC$V_C3CFP5 = 4,13,1,0 %; ! 45 CPU 0 Clock Forward Preset macro DSC$V_P1P5 = 4,14,1,0 %; ! 46 P-Chip_1 Preset macro DSC$V_RSVD_5 = 4,15,1,0 %; ! 47 reserved ! macro DSC$V_BC6 = 4,16,2,0 %; literal DSC$S_BC6 = 2; ! 49:48 Base Configuration macro DSC$V_C0CFP6 = 4,18,1,0 %; ! 50 CPU 0 Clock Forward Preset macro DSC$V_C1CFP6 = 4,19,1,0 %; ! 51 CPU 0 Clock Forward Preset macro DSC$V_C2CFP6 = 4,20,1,0 %; ! 52 CPU 0 Clock Forward Preset macro DSC$V_C3CFP6 = 4,21,1,0 %; ! 53 CPU 0 Clock Forward Preset macro DSC$V_P1P6 = 4,22,1,0 %; ! 54 P-Chip_1 Preset macro DSC$V_RSVD_6 = 4,23,1,0 %; ! 55 reserved ! macro DSC$V_BC7 = 4,24,2,0 %; literal DSC$S_BC7 = 2; ! 57:56 Base Configuration macro DSC$V_C0CFP7 = 4,26,1,0 %; ! 58 CPU 0 Clock Forward Preset macro DSC$V_C1CFP7 = 4,27,1,0 %; ! 59 CPU 0 Clock Forward Preset macro DSC$V_C2CFP7 = 4,28,1,0 %; ! 60 CPU 0 Clock Forward Preset macro DSC$V_C3CFP7 = 4,29,1,0 %; ! 61 CPU 0 Clock Forward Preset macro DSC$V_P1P7 = 4,30,1,0 %; ! 62 P-Chip_1 Preset macro DSC$V_RSVD_7 = 4,31,1,0 %; ! 63 reserved ! ! ! STR - D-Chip System Timing Register ! literal STR$M_AW = %X'1'; literal STR$M_IDDR = %X'E'; literal STR$M_IDDW = %X'30'; literal STR$M_RSVD_0 = %X'C0'; literal STR$M_AW1 = %X'100'; literal STR$M_IDDR1 = %X'E00'; literal STR$M_IDDW1 = %X'3000'; literal STR$M_RSVD_1 = %X'C000'; literal STR$M_AW2 = %X'10000'; literal STR$M_IDDR2 = %X'E0000'; literal STR$M_IDDW2 = %X'300000'; literal STR$M_RSVD_2 = %X'C00000'; literal STR$M_AW3 = %X'1000000'; literal STR$M_IDDR3 = %X'E000000'; literal STR$M_IDDW3 = %X'30000000'; literal STR$M_RSVD_3 = %X'C0000000'; literal STR$M_AW4 = %X'100000000'; literal STR$M_IDDR4 = %X'E00000000'; literal STR$M_IDDW4 = %X'3000000000'; literal STR$M_RSVD_4 = %X'C000000000'; literal STR$M_AW5 = %X'10000000000'; literal STR$M_IDDR5 = %X'E0000000000'; literal STR$M_IDDW5 = %X'300000000000'; literal STR$M_RSVD_5 = %X'C00000000000'; literal STR$M_AW6 = %X'1000000000000'; literal STR$M_IDDR6 = %X'E000000000000'; literal STR$M_IDDW6 = %X'30000000000000'; literal STR$M_RSVD_6 = %X'C0000000000000'; literal STR$M_AW7 = %X'100000000000000'; literal STR$M_IDDR7 = %X'E00000000000000'; literal STR$M_IDDW7 = %X'3000000000000000'; literal STR$M_RSVD_7 = %X'C000000000000000'; literal STR$S_STR = 8; macro STR$IQ_DATA = 0,0,0,0 %; literal STR$S_DATA = 8; macro STR$IL_L = 0,0,32,0 %; macro STR$IL_H = 4,0,32,0 %; macro STR$V_AW = 0,0,1,0 %; ! 0 Array Width macro STR$V_IDDR = 0,1,3,0 %; literal STR$S_IDDR = 3; ! 3:1 Issue to Data Delay for memory reads macro STR$V_IDDW = 0,4,2,0 %; literal STR$S_IDDW = 2; ! 5:4 Issue to Data Delay for xactions other than memory reads macro STR$V_RSVD_0 = 0,6,2,0 %; literal STR$S_RSVD_0 = 2; ! 7:6 reserved ! macro STR$V_AW1 = 0,8,1,0 %; ! 8 Array Width macro STR$V_IDDR1 = 0,9,3,0 %; literal STR$S_IDDR1 = 3; ! 11:9 Issue to Data Delay for memory reads macro STR$V_IDDW1 = 0,12,2,0 %; literal STR$S_IDDW1 = 2; ! 13:12 Issue to Data Delay for xactions other than memory reads macro STR$V_RSVD_1 = 0,14,2,0 %; literal STR$S_RSVD_1 = 2; ! 15:14 reserved ! macro STR$V_AW2 = 0,16,1,0 %; ! 16 Array Width macro STR$V_IDDR2 = 0,17,3,0 %; literal STR$S_IDDR2 = 3; ! 19:17 Issue to Data Delay for memory reads macro STR$V_IDDW2 = 0,20,2,0 %; literal STR$S_IDDW2 = 2; ! 21:20 Issue to Data Delay for xactions other than memory reads macro STR$V_RSVD_2 = 0,22,2,0 %; literal STR$S_RSVD_2 = 2; ! 23:22 reserved ! macro STR$V_AW3 = 0,24,1,0 %; ! 24 Array Width macro STR$V_IDDR3 = 0,25,3,0 %; literal STR$S_IDDR3 = 3; ! 27:25 Issue to Data Delay for memory reads macro STR$V_IDDW3 = 0,28,2,0 %; literal STR$S_IDDW3 = 2; ! 29:28 Issue to Data Delay for xactions other than memory reads macro STR$V_RSVD_3 = 0,30,2,0 %; literal STR$S_RSVD_3 = 2; ! 31:30 reserved ! macro STR$V_AW4 = 4,0,1,0 %; ! 32 Array Width macro STR$V_IDDR4 = 4,1,3,0 %; literal STR$S_IDDR4 = 3; ! 35:33 Issue to Data Delay for memory reads macro STR$V_IDDW4 = 4,4,2,0 %; literal STR$S_IDDW4 = 2; ! 37:36 Issue to Data Delay for xactions other than memory reads macro STR$V_RSVD_4 = 4,6,2,0 %; literal STR$S_RSVD_4 = 2; ! 39:38 reserved ! macro STR$V_AW5 = 4,8,1,0 %; ! 40 Array Width macro STR$V_IDDR5 = 4,9,3,0 %; literal STR$S_IDDR5 = 3; ! 43:41 Issue to Data Delay for memory reads macro STR$V_IDDW5 = 4,12,2,0 %; literal STR$S_IDDW5 = 2; ! 45:44 Issue to Data Delay for xactions other than memory reads macro STR$V_RSVD_5 = 4,14,2,0 %; literal STR$S_RSVD_5 = 2; ! 47:46 reserved ! macro STR$V_AW6 = 4,16,1,0 %; ! 48 Array Width macro STR$V_IDDR6 = 4,17,3,0 %; literal STR$S_IDDR6 = 3; ! 51:49 Issue to Data Delay for memory reads macro STR$V_IDDW6 = 4,20,2,0 %; literal STR$S_IDDW6 = 2; ! 53:52 Issue to Data Delay for xactions other than memory reads macro STR$V_RSVD_6 = 4,22,2,0 %; literal STR$S_RSVD_6 = 2; ! 55:54 reserved ! macro STR$V_AW7 = 4,24,1,0 %; ! 56 Array Width macro STR$V_IDDR7 = 4,25,3,0 %; literal STR$S_IDDR7 = 3; ! 59:57 Issue to Data Delay for memory reads macro STR$V_IDDW7 = 4,28,2,0 %; literal STR$S_IDDW7 = 2; ! 61:60 Issue to Data Delay for xactions other than memory reads macro STR$V_RSVD_7 = 4,30,2,0 %; literal STR$S_RSVD_7 = 2; ! 63:62 reserved ! ! ! DREV - D-Chip System Configuration Register ! literal DREV$M_REV0 = %X'F'; literal DREV$M_RSVD_0 = %X'F0'; literal DREV$M_REV1 = %X'F00'; literal DREV$M_RSVD_1 = %X'F000'; literal DREV$M_REV2 = %X'F0000'; literal DREV$M_RSVD_2 = %X'F00000'; literal DREV$M_REV3 = %X'F000000'; literal DREV$M_RSVD_3 = %X'F0000000'; literal DREV$M_REV4 = %X'F00000000'; literal DREV$M_RSVD_4 = %X'F000000000'; literal DREV$M_REV5 = %X'F0000000000'; literal DREV$M_RSVD_5 = %X'F00000000000'; literal DREV$M_REV6 = %X'F000000000000'; literal DREV$M_RSVD_6 = %X'F0000000000000'; literal DREV$M_REV7 = %X'F00000000000000'; literal DREV$M_RSVD_7 = %X'F000000000000000'; literal DREV$S_DREV = 8; macro DREV$IQ_DATA = 0,0,0,0 %; literal DREV$S_DATA = 8; macro DREV$IL_L = 0,0,32,0 %; macro DREV$IL_H = 4,0,32,0 %; macro DREV$V_REV0 = 0,0,4,0 %; literal DREV$S_REV0 = 4; ! 3:0 D-Chip 0 Revision macro DREV$V_RSVD_0 = 0,4,4,0 %; literal DREV$S_RSVD_0 = 4; ! 7:4 CPU 0 Clk Fwd Preset ! macro DREV$V_REV1 = 0,8,4,0 %; literal DREV$S_REV1 = 4; ! 11:8 D-Chip 1 Revision macro DREV$V_RSVD_1 = 0,12,4,0 %; literal DREV$S_RSVD_1 = 4; ! 15:12 CPU 1 Clk Fwd Preset ! macro DREV$V_REV2 = 0,16,4,0 %; literal DREV$S_REV2 = 4; ! 19:16 D-Chip 2 Revision macro DREV$V_RSVD_2 = 0,20,4,0 %; literal DREV$S_RSVD_2 = 4; ! 23:20 CPU 2 Clk Fwd Preset ! macro DREV$V_REV3 = 0,24,4,0 %; literal DREV$S_REV3 = 4; ! 27:24 D-Chip 3 Revision macro DREV$V_RSVD_3 = 0,28,4,0 %; literal DREV$S_RSVD_3 = 4; ! 31:28 CPU 3 Clk Fwd Preset ! macro DREV$V_REV4 = 4,0,4,0 %; literal DREV$S_REV4 = 4; ! 35:32 D-Chip 4 Revision macro DREV$V_RSVD_4 = 4,4,4,0 %; literal DREV$S_RSVD_4 = 4; ! 39:36 CPU 4 Clk Fwd Preset ! macro DREV$V_REV5 = 4,8,4,0 %; literal DREV$S_REV5 = 4; ! 43:40 D-Chip 5 Revision macro DREV$V_RSVD_5 = 4,12,4,0 %; literal DREV$S_RSVD_5 = 4; ! 47:44 CPU 5 Clk Fwd Preset ! macro DREV$V_REV6 = 4,16,4,0 %; literal DREV$S_REV6 = 4; ! 51:48 D-Chip 6 Revision macro DREV$V_RSVD_6 = 4,20,4,0 %; literal DREV$S_RSVD_6 = 4; ! 55:52 CPU 6 Clk Fwd Preset ! macro DREV$V_REV7 = 4,24,4,0 %; literal DREV$S_REV7 = 4; ! 59:56 D-Chip 7 Revision macro DREV$V_RSVD_7 = 4,28,4,0 %; literal DREV$S_RSVD_7 = 4; ! 63:60 CPU 7 Clk Fwd Preset ! ========================================================================== ! ! P-Chip Registers ! ! ========================================================================== ! ! ! WSBA - P-Chip Window Space Base Address Registers ! literal WSBA$M_ENA = %X'1'; literal WSBA$M_SG = %X'2'; literal WSBA$M_PTP = %X'4'; literal WSBA$M_RSVD_0 = %X'FFFF8'; literal WSBA$M_ADDR = %X'FFF00000'; literal WSBA$M_RSVD_1 = %X'FFFFFFFF00000000'; literal WSBA$S_WSBA = 8; macro WSBA$IQ_DATA = 0,0,0,0 %; literal WSBA$S_DATA = 8; macro WSBA$IL_L = 0,0,32,0 %; macro WSBA$IL_H = 4,0,32,0 %; macro WSBA$V_ENA = 0,0,1,0 %; ! 0 Enable macro WSBA$V_SG = 0,1,1,0 %; ! 1 Scatter/Gather macro WSBA$V_PTP = 0,2,1,0 %; ! 2 Peer-to-Peer macro WSBA$V_RSVD_0 = 0,3,17,0 %; literal WSBA$S_RSVD_0 = 17; ! 19:3 reserved macro WSBA$V_ADDR = 0,20,12,0 %; literal WSBA$S_ADDR = 12; ! 31:20 Base Address macro WSBA$V_RSVD_1 = 4,0,32,0 %; literal WSBA$S_RSVD_1 = 32; ! 63:32 Reserved ! ! ! WSM - P-Chip Window Space Mask Registers ! literal WSM$M_RSVD_0 = %X'FFFFF'; literal WSM$M_AM = %X'FFF00000'; literal WSM$M_RSVD_1 = %X'FFFFFFFF00000000'; literal WSM$S_WSM = 8; macro WSM$IQ_DATA = 0,0,0,0 %; literal WSM$S_DATA = 8; macro WSM$IL_L = 0,0,32,0 %; macro WSM$IL_H = 4,0,32,0 %; macro WSM$V_RSVD_0 = 0,0,20,0 %; literal WSM$S_RSVD_0 = 20; ! 19:0 reserved macro WSM$V_AM = 0,20,12,0 %; literal WSM$S_AM = 12; ! 31:20 Base Address macro WSM$V_RSVD_1 = 4,0,32,0 %; literal WSM$S_RSVD_1 = 32; ! 63:32 Reserved ! ! ! TBA - P-Chip Translated Base Address Registers ! literal TBA$M_RSVD_0 = %X'3FF'; literal TBA$M_ADDR = %X'7FFFFFC00'; literal TBA$M_RSVD_1 = %X'FFFFFFF800000000'; literal TBA$S_TBA = 8; macro TBA$IQ_DATA = 0,0,0,0 %; literal TBA$S_DATA = 8; macro TBA$IL_L = 0,0,32,0 %; macro TBA$IL_H = 4,0,32,0 %; macro TBA$V_RSVD_0 = 0,0,10,0 %; literal TBA$S_RSVD_0 = 10; ! 9:0 reserved macro TBA$V_ADDR = 0,10,25,0 %; literal TBA$S_ADDR = 25; ! 34:10 Translated Base Address macro TBA$V_RSVD_1 = 4,3,29,0 %; literal TBA$S_RSVD_1 = 29; ! 63:35 reserved ! ! ! PCTL - P-Chip Control Register ! literal PCTL$M_FDSC = %X'1'; literal PCTL$M_FBTB = %X'2'; literal PCTL$M_THDIS = %X'4'; literal PCTL$M_CHAINDIS = %X'8'; literal PCTL$M_TGTLAT = %X'10'; literal PCTL$M_HOLE = %X'20'; literal PCTL$M_MWIN = %X'40'; literal PCTL$M_ARBENA = %X'80'; literal PCTL$M_PRIGRP = %X'7F00'; literal PCTL$M_PPRI = %X'8000'; literal PCTL$M_RSVD_0 = %X'30000'; literal PCTL$M_ECCEN = %X'40000'; literal PCTL$M_PADM = %X'80000'; literal PCTL$M_CDQMAX = %X'F00000'; literal PCTL$M_REV = %X'FF000000'; literal PCTL$M_CRQMAX = %X'F00000000'; literal PCTL$M_PTPMAX = %X'F000000000'; literal PCTL$M_PCLKX = %X'30000000000'; literal PCTL$M_FDSDIS = %X'40000000000'; literal PCTL$M_FDWDIS = %X'80000000000'; literal PCTL$M_PTEVRFY = %X'100000000000'; literal PCTL$M_RSVD_1 = %X'FFFFE00000000000'; literal PCTL$S_PCTL = 8; macro PCTL$IQ_DATA = 0,0,0,0 %; literal PCTL$S_DATA = 8; macro PCTL$IL_L = 0,0,32,0 %; macro PCTL$IL_H = 4,0,32,0 %; macro PCTL$V_FDSC = 0,0,1,0 %; ! 0 Fast Discard enable macro PCTL$V_FBTB = 0,1,1,0 %; ! 1 Fast Back-To-Back enable macro PCTL$V_THDIS = 0,2,1,0 %; ! 2 Disable anti-Thrash mechanism for TLB macro PCTL$V_CHAINDIS = 0,3,1,0 %; ! 3 Disable Chaining macro PCTL$V_TGTLAT = 0,4,1,0 %; ! 4 Target Latency Timers timers enable macro PCTL$V_HOLE = 0,5,1,0 %; ! 5 512K to 1M window Hole enable macro PCTL$V_MWIN = 0,6,1,0 %; ! 6 Monster Window enable macro PCTL$V_ARBENA = 0,7,1,0 %; ! 7 internal Arbiter Enable macro PCTL$V_PRIGRP = 0,8,7,0 %; literal PCTL$S_PRIGRP = 7; ! 14:8 arbiter Priority Group macro PCTL$V_PPRI = 0,15,1,0 %; ! 15 arbiter Priority Group for the Pchip itself macro PCTL$V_RSVD_0 = 0,16,2,0 %; literal PCTL$S_RSVD_0 = 2; ! 17:16 reserved macro PCTL$V_ECCEN = 0,18,1,0 %; ! 18 ECC Enable for DMA & SGTE accesses macro PCTL$V_PADM = 0,19,1,0 %; ! 19 PAD bus Mode macro PCTL$V_CDQMAX = 0,20,4,0 %; literal PCTL$S_CDQMAX = 4; ! 23:20 Max Data xfer to Dchips from both Pchips macro PCTL$V_REV = 0,24,8,0 %; literal PCTL$S_REV = 8; ! 31:24 Revision ! macro PCTL$V_CRQMAX = 4,0,4,0 %; literal PCTL$S_CRQMAX = 4; ! 35:32 Max requests to Cchip from both Pchips macro PCTL$V_PTPMAX = 4,4,4,0 %; literal PCTL$S_PTPMAX = 4; ! 39:36 Max PTP requests to Cchip from both Pchips macro PCTL$V_PCLKX = 4,8,2,0 %; literal PCTL$S_PCLKX = 2; ! 41:40 PCI Clock Freq Multiplier macro PCTL$V_FDSDIS = 4,10,1,0 %; ! 42 Fast DMA Start & SGTE request Disable macro PCTL$V_FDWDIS = 4,11,1,0 %; ! 43 Fast DMA read cache blk Wrap request Disable macro PCTL$V_PTEVRFY = 4,12,1,0 %; ! 44 PTE Verify for DMA read macro PCTL$V_RSVD_1 = 4,13,19,0 %; literal PCTL$S_RSVD_1 = 19; ! 63:45 reserved ! ! ! PLAT - P-Chip Master Latency Register ! literal PLAT$M_RSVD_0 = %X'FF'; literal PLAT$M_LAT = %X'FF00'; literal PLAT$M_RSVD_1 = %X'FFFF0000'; literal PLAT$M_RSVD_2 = %X'FFFFFFFF00000000'; literal PLAT$S_PLAT = 8; macro PLAT$IQ_DATA = 0,0,0,0 %; literal PLAT$S_DATA = 8; macro PLAT$IL_L = 0,0,32,0 %; macro PLAT$IL_H = 4,0,32,0 %; macro PLAT$V_RSVD_0 = 0,0,8,0 %; literal PLAT$S_RSVD_0 = 8; ! 7:0 reserved macro PLAT$V_LAT = 0,8,8,0 %; literal PLAT$S_LAT = 8; ! 15:8 Master Latency Timer macro PLAT$V_RSVD_1 = 0,16,16,0 %; literal PLAT$S_RSVD_1 = 16; ! 31:16 reserved macro PLAT$V_RSVD_2 = 4,0,32,0 %; literal PLAT$S_RSVD_2 = 32; ! 63:32 reserved ! ! ! PERROR - P-Chip Error Register ! literal PERROR$M_LOST = %X'1'; literal PERROR$M_SERR = %X'2'; literal PERROR$M_PERR = %X'4'; literal PERROR$M_DCRTO = %X'8'; literal PERROR$M_SGE = %X'10'; literal PERROR$M_APE = %X'20'; literal PERROR$M_TA = %X'40'; literal PERROR$M_RDPE = %X'80'; literal PERROR$M_NDS = %X'100'; literal PERROR$M_RTO = %X'200'; literal PERROR$M_UECC = %X'400'; literal PERROR$M_CRE = %X'800'; literal PERROR$M_RSVD_0 = %X'F000'; literal PERROR$M_ADDR = %X'FFFFFFFF0000'; literal PERROR$M_ADDR_H = %X'7000000000000'; literal PERROR$M_RSVD_1 = %X'8000000000000'; literal PERROR$M_CMD = %X'F0000000000000'; literal PERROR$M_SYN = %X'FF00000000000000'; literal PERROR$S_PERROR = 8; macro PERROR$IQ_DATA = 0,0,0,0 %; literal PERROR$S_DATA = 8; macro PERROR$IL_L = 0,0,32,0 %; macro PERROR$IL_H = 4,0,32,0 %; macro PERROR$V_LOST = 0,0,1,0 %; ! 0 Lost an error macro PERROR$V_SERR = 0,1,1,0 %; ! 1 SERR# sampled asserted macro PERROR$V_PERR = 0,2,1,0 %; ! 2 PERR# sampled asserted as PCI master macro PERROR$V_DCRTO = 0,3,1,0 %; ! 3 delayed completion retry timeout as PCI target macro PERROR$V_SGE = 0,4,1,0 %; ! 4 Scatter/Gather had invalid PTE macro PERROR$V_APE = 0,5,1,0 %; ! 5 Address Parity Error detected as potential PCI target macro PERROR$V_TA = 0,6,1,0 %; ! 6 Targed Abort as PCI master macro PERROR$V_RDPE = 0,7,1,0 %; ! 7 PCI Read Data Parity Error as PCI master macro PERROR$V_NDS = 0,8,1,0 %; ! 8 No DevSel as PCI master macro PERROR$V_RTO = 0,9,1,0 %; ! 9 Retry TimeOut as PCI master after 2^24 tries macro PERROR$V_UECC = 0,10,1,0 %; ! 10 Uncorrectable ECC error macro PERROR$V_CRE = 0,11,1,0 %; ! 11 Correctable ECC error macro PERROR$V_RSVD_0 = 0,12,4,0 %; literal PERROR$S_RSVD_0 = 4; ! 15:12 reserved macro PERROR$V_ADDR = 0,16,32,0 %; literal PERROR$S_ADDR = 32; ! 48:16 Addres of CRE or UECC macro PERROR$V_ADDR_H = 4,16,3,0 %; literal PERROR$S_ADDR_H = 3; ! 50:48 Addres of CRE or UECC macro PERROR$V_RSVD_1 = 4,19,1,0 %; ! 51 reserved macro PERROR$V_CMD = 4,20,4,0 %; literal PERROR$S_CMD = 4; ! 55:52 PCI Command on error macro PERROR$V_SYN = 4,24,8,0 %; literal PERROR$S_SYN = 8; ! 63:56 ECC Syndrome on CRE or UECC ! ! ! PERRMASK - P-Chip Error Mask Register ! literal PERRMASK$M_LOST = %X'1'; literal PERRMASK$M_SERR = %X'2'; literal PERRMASK$M_PERR = %X'4'; literal PERRMASK$M_DCRTO = %X'8'; literal PERRMASK$M_SGE = %X'10'; literal PERRMASK$M_APE = %X'20'; literal PERRMASK$M_TA = %X'40'; literal PERRMASK$M_RDPE = %X'80'; literal PERRMASK$M_NDS = %X'100'; literal PERRMASK$M_RTO = %X'200'; literal PERRMASK$M_UECC = %X'400'; literal PERRMASK$M_CRE = %X'800'; literal PERRMASK$M_RSVD_0 = %X'FFFFF000'; literal PERRMASK$M_RSVD_1 = %X'FFFFFFFF00000000'; literal PERRMASK$S_PERRMASK = 8; macro PERRMASK$IQ_DATA = 0,0,0,0 %; literal PERRMASK$S_DATA = 8; macro PERRMASK$IL_L = 0,0,32,0 %; macro PERRMASK$IL_H = 4,0,32,0 %; macro PERRMASK$V_LOST = 0,0,1,0 %; ! 0 Lost an error macro PERRMASK$V_SERR = 0,1,1,0 %; ! 1 SERR# sampled asserted macro PERRMASK$V_PERR = 0,2,1,0 %; ! 2 PERR# sampled asserted as PCI master macro PERRMASK$V_DCRTO = 0,3,1,0 %; ! 3 delayed completion retry timeout as PCI target macro PERRMASK$V_SGE = 0,4,1,0 %; ! 4 Scatter/Gather had invalid PTE macro PERRMASK$V_APE = 0,5,1,0 %; ! 5 Address Parity Error detected as potential PCI target macro PERRMASK$V_TA = 0,6,1,0 %; ! 6 Targed Abort as PCI master macro PERRMASK$V_RDPE = 0,7,1,0 %; ! 7 PCI Read Data Parity Error as PCI master macro PERRMASK$V_NDS = 0,8,1,0 %; ! 8 No DevSel as PCI master macro PERRMASK$V_RTO = 0,9,1,0 %; ! 9 Retry TimeOut as PCI master after 2^24 tries macro PERRMASK$V_UECC = 0,10,1,0 %; ! 10 Uncorrectable ECC error macro PERRMASK$V_CRE = 0,11,1,0 %; ! 11 Correctable ECC error macro PERRMASK$V_RSVD_0 = 0,12,20,0 %; literal PERRMASK$S_RSVD_0 = 20; ! 31:12 reserved macro PERRMASK$V_RSVD_1 = 4,0,32,0 %; literal PERRMASK$S_RSVD_1 = 32; ! 63:32 reserved ! ! ! PERRSET - P-Chip Error Set Register ! literal PERRSET$M_LOST = %X'1'; literal PERRSET$M_SERR = %X'2'; literal PERRSET$M_PERR = %X'4'; literal PERRSET$M_DCRTO = %X'8'; literal PERRSET$M_SGE = %X'10'; literal PERRSET$M_APE = %X'20'; literal PERRSET$M_TA = %X'40'; literal PERRSET$M_RDPE = %X'80'; literal PERRSET$M_NDS = %X'100'; literal PERRSET$M_RTO = %X'200'; literal PERRSET$M_UECC = %X'400'; literal PERRSET$M_CRE = %X'800'; literal PERRSET$M_RSVD_0 = %X'F000'; literal PERRSET$M_ADDR = %X'FFFFFFFF0000'; literal PERRSET$M_ADDR_H = %X'7000000000000'; literal PERRSET$M_RSVD_1 = %X'8000000000000'; literal PERRSET$M_CMD = %X'F0000000000000'; literal PERRSET$M_SYN = %X'FF00000000000000'; literal PERRSET$S_PERRSET = 8; macro PERRSET$IQ_DATA = 0,0,0,0 %; literal PERRSET$S_DATA = 8; macro PERRSET$IL_L = 0,0,32,0 %; macro PERRSET$IL_H = 4,0,32,0 %; macro PERRSET$V_LOST = 0,0,1,0 %; ! 0 Lost an error macro PERRSET$V_SERR = 0,1,1,0 %; ! 1 SERR# sampled asserted macro PERRSET$V_PERR = 0,2,1,0 %; ! 2 PERR# sampled asserted as PCI master macro PERRSET$V_DCRTO = 0,3,1,0 %; ! 3 delayed completion retry timeout as PCI target macro PERRSET$V_SGE = 0,4,1,0 %; ! 4 Scatter/Gather had invalid PTE macro PERRSET$V_APE = 0,5,1,0 %; ! 5 Address Parity Error detected as potential PCI target macro PERRSET$V_TA = 0,6,1,0 %; ! 6 Targed Abort as PCI master macro PERRSET$V_RDPE = 0,7,1,0 %; ! 7 PCI Read Data Parity Error as PCI master macro PERRSET$V_NDS = 0,8,1,0 %; ! 8 No DevSel as PCI master macro PERRSET$V_RTO = 0,9,1,0 %; ! 9 Retry TimeOut as PCI master after 2^24 tries macro PERRSET$V_UECC = 0,10,1,0 %; ! 10 Uncorrectable ECC error macro PERRSET$V_CRE = 0,11,1,0 %; ! 11 Correctable ECC error macro PERRSET$V_RSVD_0 = 0,12,4,0 %; literal PERRSET$S_RSVD_0 = 4; ! 15:12 reserved macro PERRSET$V_ADDR = 0,16,32,0 %; literal PERRSET$S_ADDR = 32; ! 47:16 Lo 32 Address bits of CRE or UECC macro PERRSET$V_ADDR_H = 4,16,3,0 %; literal PERRSET$S_ADDR_H = 3; ! 50:48 Hi 3 Address bits of CRE or UECC macro PERRSET$V_RSVD_1 = 4,19,1,0 %; ! 51 reserved macro PERRSET$V_CMD = 4,20,4,0 %; literal PERRSET$S_CMD = 4; ! 55:52 PCI Command on error macro PERRSET$V_SYN = 4,24,8,0 %; literal PERRSET$S_SYN = 8; ! 63:56 ECC Syndrome on CRE or UECC ! ! ! TLBIV - P-Chip Translation Buffer Invalidate Virtual Register ! literal TLBIV$M_RSVD_0 = %X'F'; literal TLBIV$M_ADDR = %X'FFFF0'; literal TLBIV$M_RSVD_1 = %X'FFF00000'; literal TLBIV$M_RSVD_2 = %X'FFFFFFFF00000000'; literal TLBIV$S_TLBIV = 8; macro TLBIV$IQ_DATA = 0,0,0,0 %; literal TLBIV$S_DATA = 8; macro TLBIV$IL_L = 0,0,32,0 %; macro TLBIV$IL_H = 4,0,32,0 %; macro TLBIV$V_RSVD_0 = 0,0,4,0 %; literal TLBIV$S_RSVD_0 = 4; ! 3:0 reserved macro TLBIV$V_ADDR = 0,4,16,0 %; literal TLBIV$S_ADDR = 16; ! 19:4 invalidate if matches PCI addr<31:16> macro TLBIV$V_RSVD_1 = 0,20,12,0 %; literal TLBIV$S_RSVD_1 = 12; ! 31:20 reserved macro TLBIV$V_RSVD_2 = 4,0,32,0 %; literal TLBIV$S_RSVD_2 = 32; ! 63:32 reserved ! ! ! TLBIA - P-Chip Translation Buffer Invalidate all Register ! literal TLBIA$S_TLBIA = 8; macro TLBIA$IQ_DATA = 0,0,0,0 %; literal TLBIA$S_DATA = 8; macro TLBIA$IL_L = 0,0,32,0 %; macro TLBIA$IL_H = 4,0,32,0 %; ! ! ! PMONCTL - P-Chip Monitor Control Register ! literal PMONCTL$M_SLCT0 = %X'FF'; literal PMONCTL$M_SLCT1 = %X'FF00'; literal PMONCTL$M_STKDIS0 = %X'10000'; literal PMONCTL$M_STKDIS1 = %X'20000'; literal PMONCTL$M_RSVD_0 = %X'FFFC0000'; literal PMONCTL$M_RSVD_1 = %X'FFFFFFFF00000000'; literal PMONCTL$S_PMONCTL = 8; macro PMONCTL$IQ_DATA = 0,0,0,0 %; literal PMONCTL$S_DATA = 8; macro PMONCTL$IL_L = 0,0,32,0 %; macro PMONCTL$IL_H = 4,0,32,0 %; macro PMONCTL$V_SLCT0 = 0,0,8,0 %; literal PMONCTL$S_SLCT0 = 8; ! 7:0 Select Monitor 0 macro PMONCTL$V_SLCT1 = 0,8,8,0 %; literal PMONCTL$S_SLCT1 = 8; ! 15:8 Select Monitor 1 macro PMONCTL$V_STKDIS0 = 0,16,1,0 %; ! 16 Sticky Count 0 Disable macro PMONCTL$V_STKDIS1 = 0,17,1,0 %; ! 17 Sticky Count 1 Disable macro PMONCTL$V_RSVD_0 = 0,18,14,0 %; literal PMONCTL$S_RSVD_0 = 14; ! 31:18 reserved macro PMONCTL$V_RSVD_1 = 4,0,32,0 %; literal PMONCTL$S_RSVD_1 = 32; ! 63:32 reserved ! ! ! PMONCNT - P-Chip Monitor Counters Register ! literal PMONCNT$S_PMONCNT = 8; macro PMONCNT$IQ_DATA = 0,0,0,0 %; literal PMONCNT$S_DATA = 8; macro PMONCNT$IL_CNT0 = 0,0,32,0 %; macro PMONCNT$IL_CNT1 = 4,0,32,0 %; !*** MODULE $UAFDEF *** ! ++ ! User authorization file format ! Note: With the exception of the username and account name, ! all strings are blank padded counted strings. Username and ! account name are uncounted, blank padded. ! -- literal UAF$C_USER_ID = 1; ! main user ID record literal UAF$C_VERSION1 = 1; ! this version literal UAF$C_KEYED_PART = 52; ! ISAM keys come this far literal UAF$C_MAX_PWD_LENGTH = 32; ! maximum plaintext password length literal UAF$K_MAX_PWD_LENGTH = 32; ! maximum plaintext password length literal UAF$C_AD_II = 0; ! AUTODIN-II 32 bit crc code literal UAF$C_PURDY = 1; ! Purdy polynomial over salted input literal UAF$C_PURDY_V = 2; ! Purdy polynomial + variable length username literal UAF$C_PURDY_S = 3; ! PURDY_V folded into password length literal UAF$K_CURRENT_ALGORITHM = 3; ! current DEC algorithm number literal UAF$C_CURRENT_ALGORITHM = 3; ! current DEC algorithm number literal UAF$C_PREFERED_ALGORITHM = 127; literal UAF$K_PREFERED_ALGORITHM = 127; literal UAF$C_PREFERRED_ALGORITHM = 127; ! preferred hash algorithm - use current literal UAF$K_PREFERRED_ALGORITHM = 127; ! preferred hash algorithm - use current literal UAF$C_CUST_ALGORITHM = 128; ! customer algorithm division literal UAF$K_CUST_ALGORITHM = 128; ! customer algorithm division literal UAF$K_FIXED = 644; ! length of fixed portion literal UAF$C_FIXED = 644; ! length of fixed portion literal UAF$K_LENGTH = 1412; literal UAF$C_LENGTH = 1412; literal UAF$S_UAFDEF = 1412; ! Old size name, synonym for UAF$S_UAF literal UAF$S_UAF = 1412; macro UAF$B_RTYPE = 0,0,8,0 %; ! UAF record type macro UAF$B_VERSION = 1,0,8,0 %; ! UAF format version macro UAF$W_USRDATOFF = 2,0,16,0 %; ! offset of counted string of user data macro UAF$T_USERNAME = 4,0,0,0 %; literal UAF$S_USERNAME = 32; ! username macro UAF$T_USERNAME_TAG = 35,0,8,0 %; ! tag to differentiate records macro UAF$L_UIC = 36,0,32,0 %; ! user ID code macro UAF$W_MEM = 36,0,16,0 %; ! member subfield macro UAF$W_GRP = 38,0,16,0 %; ! group subfield macro UAF$L_SUB_ID = 40,0,32,0 %; ! user sub-identifier macro UAF$Q_PARENT_ID = 44,0,0,0 %; literal UAF$S_PARENT_ID = 8; ! identifier of owner of this account macro UAF$T_ACCOUNT = 52,0,0,0 %; literal UAF$S_ACCOUNT = 32; ! account name macro UAF$T_OWNER = 84,0,0,0 %; literal UAF$S_OWNER = 32; ! owner's name macro UAF$T_DEFDEV = 116,0,0,0 %; literal UAF$S_DEFDEV = 32; ! default device macro UAF$T_DEFDIR = 148,0,0,0 %; literal UAF$S_DEFDIR = 64; ! default directory macro UAF$T_LGICMD = 212,0,0,0 %; literal UAF$S_LGICMD = 64; ! login command file macro UAF$T_DEFCLI = 276,0,0,0 %; literal UAF$S_DEFCLI = 32; ! default command interpreter macro UAF$T_CLITABLES = 308,0,0,0 %; literal UAF$S_CLITABLES = 32; ! user CLI tables macro UAF$Q_PWD = 340,0,0,0 %; literal UAF$S_PWD = 8; ! hashed password macro UAF$L_PWD = 340,0,32,0 %; ! 32 bit subfield macro UAF$Q_PWD2 = 348,0,0,0 %; literal UAF$S_PWD2 = 8; ! second password macro UAF$W_LOGFAILS = 356,0,16,0 %; ! count of login failures macro UAF$W_SALT = 358,0,16,0 %; ! random password salt macro UAF$B_ENCRYPT = 360,0,8,0 %; ! primary password hash algorithm ! known hash algorithm indices macro UAF$B_ENCRYPT2 = 361,0,8,0 %; ! secondary password hash algorithm macro UAF$B_PWD_LENGTH = 362,0,8,0 %; ! minimum password length macro UAF$Q_EXPIRATION = 364,0,0,0 %; literal UAF$S_EXPIRATION = 8; ! expiration date for account macro UAF$Q_PWD_LIFETIME = 372,0,0,0 %; literal UAF$S_PWD_LIFETIME = 8; ! password lifetime macro UAF$Q_PWD_DATE = 380,0,0,0 %; literal UAF$S_PWD_DATE = 8; ! date of password change macro UAF$Q_PWD2_DATE = 388,0,0,0 %; literal UAF$S_PWD2_DATE = 8; ! date of 2nd password change macro UAF$Q_LASTLOGIN_I = 396,0,0,0 %; literal UAF$S_LASTLOGIN_I = 8; ! date of last interactive login macro UAF$Q_LASTLOGIN_N = 404,0,0,0 %; literal UAF$S_LASTLOGIN_N = 8; ! date of last non-interactive login macro UAF$Q_PRIV = 412,0,0,0 %; literal UAF$S_PRIV = 8; ! process privilege vector macro UAF$Q_DEF_PRIV = 420,0,0,0 %; literal UAF$S_DEF_PRIV = 8; ! default process privileges macro UAF$R_MIN_CLASS = 428,0,0,0 %; literal UAF$S_MIN_CLASS = 20; ! minimum security class macro UAF$R_MAX_CLASS = 448,0,0,0 %; literal UAF$S_MAX_CLASS = 20; ! maximum security class macro UAF$L_FLAGS = 468,0,32,0 %; ! user flags longword macro UAF$V_DISCTLY = 468,0,1,0 %; ! no user control-y macro UAF$V_DEFCLI = 468,1,1,0 %; ! only allow user default CLI macro UAF$V_LOCKPWD = 468,2,1,0 %; ! disable SET PASSWORD command macro UAF$V_RESTRICTED = 468,3,1,0 %; ! restricted account (pre-V5.2 CAPTIVE) macro UAF$V_DISACNT = 468,4,1,0 %; ! no interactive login macro UAF$V_DISWELCOM = 468,5,1,0 %; ! skip welcome message macro UAF$V_DISMAIL = 468,6,1,0 %; ! skip new mail message macro UAF$V_NOMAIL = 468,7,1,0 %; ! disable mail delivery macro UAF$V_GENPWD = 468,8,1,0 %; ! passwords must be generated macro UAF$V_PWD_EXPIRED = 468,9,1,0 %; ! password has expired macro UAF$V_PWD2_EXPIRED = 468,10,1,0 %; ! 2nd password has expired macro UAF$V_AUDIT = 468,11,1,0 %; ! audit all actions macro UAF$V_DISREPORT = 468,12,1,0 %; ! skip last login messages macro UAF$V_DISRECONNECT = 468,13,1,0 %; ! inhibit reconnections macro UAF$V_AUTOLOGIN = 468,14,1,0 %; ! auto-login only macro UAF$V_DISFORCE_PWD_CHANGE = 468,15,1,0 %; ! disable forced password change macro UAF$V_CAPTIVE = 468,16,1,0 %; ! captive account (no overrides) macro UAF$V_DISIMAGE = 468,17,1,0 %; ! disable arbitrary image activation macro UAF$V_DISPWDDIC = 468,18,1,0 %; ! disable password dictionary search macro UAF$V_DISPWDHIS = 468,19,1,0 %; ! disable password history search macro UAF$V_DEFCLSVAL = 468,20,1,0 %; ! default classification is valid macro UAF$V_EXTAUTH = 468,21,1,0 %; ! external authentication enabled macro UAF$V_MIGRATEPWD = 468,22,1,0 %; ! migrate UAF pwd to external auth macro UAF$V_VMSAUTH = 468,23,1,0 %; ! VMS alternative is allowed macro UAF$V_DISPWDSYNCH = 468,24,1,0 %; ! no ACME password sharing macro UAF$V_PWDMIX = 468,25,1,0 %; ! enable mixed-case passwords macro UAF$B_NETWORK_ACCESS_P = 472,0,24,0 %; literal UAF$S_NETWORK_ACCESS_P = 3; ! hourly network access, primary macro UAF$B_NETWORK_ACCESS_S = 475,0,24,0 %; literal UAF$S_NETWORK_ACCESS_S = 3; ! hourly network access, secondary macro UAF$B_BATCH_ACCESS_P = 478,0,24,0 %; literal UAF$S_BATCH_ACCESS_P = 3; ! hourly batch access, primary macro UAF$B_BATCH_ACCESS_S = 481,0,24,0 %; literal UAF$S_BATCH_ACCESS_S = 3; ! hourly batch access, secondary macro UAF$B_LOCAL_ACCESS_P = 484,0,24,0 %; literal UAF$S_LOCAL_ACCESS_P = 3; ! hourly local access, primary macro UAF$B_LOCAL_ACCESS_S = 487,0,24,0 %; literal UAF$S_LOCAL_ACCESS_S = 3; ! hourly local access, secondary macro UAF$B_DIALUP_ACCESS_P = 490,0,24,0 %; literal UAF$S_DIALUP_ACCESS_P = 3; ! hourly dialup access, primary macro UAF$B_DIALUP_ACCESS_S = 493,0,24,0 %; literal UAF$S_DIALUP_ACCESS_S = 3; ! hourly dialup access, secondary macro UAF$B_REMOTE_ACCESS_P = 496,0,24,0 %; literal UAF$S_REMOTE_ACCESS_P = 3; ! hourly remote access, primary macro UAF$B_REMOTE_ACCESS_S = 499,0,24,0 %; literal UAF$S_REMOTE_ACCESS_S = 3; ! hourly remote access, secondary macro UAF$B_PRIMEDAYS = 514,0,8,0 %; ! bits representing primary days macro UAF$V_MONDAY = 514,0,1,0 %; ! bit clear means this is a primary day macro UAF$V_TUESDAY = 514,1,1,0 %; ! bit set means this is an off day macro UAF$V_WEDNESDAY = 514,2,1,0 %; macro UAF$V_THURSDAY = 514,3,1,0 %; macro UAF$V_FRIDAY = 514,4,1,0 %; macro UAF$V_SATURDAY = 514,5,1,0 %; macro UAF$V_SUNDAY = 514,6,1,0 %; macro UAF$B_PRI = 516,0,8,0 %; ! base process priority macro UAF$B_QUEPRI = 517,0,8,0 %; ! maximum job queuing priority macro UAF$W_MAXJOBS = 518,0,16,0 %; ! maximum jobs for UIC allowed ! 0 means no limit macro UAF$W_MAXACCTJOBS = 520,0,16,0 %; ! maximum jobs for account allowed ! 0 means no limit macro UAF$W_MAXDETACH = 522,0,16,0 %; ! maximum detached processes for UIC ! 0 means no limit macro UAF$W_PRCCNT = 524,0,16,0 %; ! subprocess creation limit macro UAF$W_BIOLM = 526,0,16,0 %; ! buffered I/O limit macro UAF$W_DIOLM = 528,0,16,0 %; ! direct I/O limit macro UAF$W_TQCNT = 530,0,16,0 %; ! timer queue entry limit macro UAF$W_ASTLM = 532,0,16,0 %; ! AST queue limit macro UAF$W_ENQLM = 534,0,16,0 %; ! enqueue limit macro UAF$W_FILLM = 536,0,16,0 %; ! open file limit macro UAF$W_SHRFILLM = 538,0,16,0 %; ! shared file limit macro UAF$L_WSQUOTA = 540,0,32,0 %; ! working set size quota macro UAF$L_DFWSCNT = 544,0,32,0 %; ! default working set size macro UAF$L_WSEXTENT = 548,0,32,0 %; ! working set size limit macro UAF$L_PGFLQUOTA = 552,0,32,0 %; ! page file quota macro UAF$L_CPUTIM = 556,0,32,0 %; ! CPU time quota macro UAF$L_BYTLM = 560,0,32,0 %; ! buffered I/O byte count limit macro UAF$L_PBYTLM = 564,0,32,0 %; ! paged buffer I/O byte count limit macro UAF$L_JTQUOTA = 568,0,32,0 %; ! job-wide logical name table creation quota macro UAF$W_PROXY_LIM = 572,0,16,0 %; ! number of proxies user can grant macro UAF$W_PROXIES = 574,0,16,0 %; ! number of proxies granted macro UAF$W_ACCOUNT_LIM = 576,0,16,0 %; ! number of sub-accounts allowed macro UAF$W_ACCOUNTS = 578,0,16,0 %; ! number of sub-accounts in use macro UAF$R_DEF_CLASS = 580,0,0,0 %; literal UAF$S_DEF_CLASS = 20; ! default security class !*** MODULE $UASDEF *** ! + ! UNIBUS ADDRESS SPACE REGISTER DEFINITIONS FOR DW750 ! (SECOND UNIBUS ADAPTER ON 11/750) ! - literal UAS$M_IP_CR1_PIE = %X'1000'; literal UAS$M_IP_CR1_PDN = %X'2000'; literal UAS$S_UASDEF = 5222; literal UAS$S_UAS = 5222; macro UAS$R_IP = 5216,0,0,0 %; literal UAS$S_IP = 6; ! INTER-PROCESSOR EXERCISER COMMUNICATOR macro UAS$W_IP_CR1 = 5220,0,16,0 %; ! THE THIRD IPEC REGISTER, CR1 macro UAS$V_IP_CR1_PIE = 5220,12,1,0 %; ! POWERFAIL INTERRUPT ENABLE macro UAS$V_IP_CR1_PDN = 5220,13,1,0 %; ! POWER DOWN STATUS BIT !*** MODULE $UBIDEF *** ! + ! UNIBUS INTERCONNECT (VAX 11/750 & 11/730) REGISTER OFFSETS AND FIELDS ! - literal UBI$M_DPR_PUR = %X'1'; literal UBI$M_DPR_UCE = %X'20000000'; literal UBI$M_DPR_NXM = %X'40000000'; literal UBI$M_DPR_ERROR = %X'80000000'; literal UBI$S_UBIDEF = 16; macro UBI$L_DPR = 0,0,0,0 %; literal UBI$S_DPR = 16; ! DATAPATH REGISTERS ! (DPR 0 NOT IMPLEMENTED) macro UBI$V_DPR_PUR = 0,0,1,0 %; ! DATAPATH PURGE macro UBI$V_DPR_UCE = 0,29,1,0 %; ! UNCORRECTABLE ERROR macro UBI$V_DPR_NXM = 0,30,1,0 %; ! NON-EXISTENT MEMORY macro UBI$V_DPR_ERROR = 0,31,1,0 %; ! ERROR (UCE!NXM) literal UBI$M_DSR_CD = %X'8000000'; literal UBI$S_UBIDEF1 = 32; macro UBI$L_DSR = 16,0,0,0 %; literal UBI$S_DSR = 16; ! DIAGNOSTIC STATUS REGISTERS ! (DSR 0 NOT IMPLEMENTED) macro UBI$V_DSR_CD = 16,27,1,0 %; ! ALL 4 BYTES IN BDP FULL macro UBI$V_DSR_BF = 16,28,4,0 %; literal UBI$S_DSR_BF = 4; ! BYTE 0,1,2,3 IN BDP HAS VALID DATA literal UBI$M_SR_UWE = %X'4000'; literal UBI$M_SR_MRPE = %X'8000'; literal UBI$M_SR_NXM = %X'10000'; literal UBI$M_SR_UCE = %X'80000000'; literal UBI$S_UBIDEF2 = 20; macro UBI$L_SR = 16,0,32,0 %; ! UB STATUS REGISTER: macro UBI$V_SR_UWE = 16,14,1,0 %; ! UNCORRECTED WRITE ERROR macro UBI$V_SR_MRPE = 16,15,1,0 %; ! MAP REGISTER PARITY ERROR macro UBI$V_SR_NXM = 16,16,1,0 %; ! NONEXISTENT MEMORY REF macro UBI$V_SR_UCE = 16,31,1,0 %; ! UNCORRECTED READ ERROR ! END OF CPU_SPECIFIC REGISTERS literal UBI$C_MAXDP = 3; ! MAXIMUM DATAPATH ! literal UBI$C_PURCNT = 10; ! MAX ! OF TESTS OF PURGE DONE literal UBI$S_UBIDEF3 = 4032; macro UBI$L_MAP = 2048,0,0,0 %; literal UBI$S_MAP = 1984; ! MAP REGISTERS, SAME FORMAT AS UBA !*** MODULE $UBMDDEF *** ! + ! UBMD - UNIBUS Map Descriptor used to record UNIBUS map registers ! and datapaths allocated. ! - literal UBMD$S_UBMDDEF = 4; literal UBMD$S_UBMD = 4; macro UBMD$W_MAPREG = 0,0,16,0 %; ! Starting map register macro UBMD$B_NUMREG = 2,0,8,0 %; ! Number of registers in extent macro UBMD$B_DATAPATH = 3,0,8,0 %; ! Associated Buffered datapath !*** MODULE $UNCDEF *** ! ! UNCHDRDEF - Universal Context Segment Header Definition ! literal UNC$C_JPI = 1; ! JPI context segment (not used) literal UNC$C_UAI = 2; ! UAI context segment literal UNC$C_AUDIT_EVENT = 3; ! AUDIT_EVENT context segment literal UNC$C_OBJECT = 4; ! Object management context segment literal UNC$C_ORB_FIXUP = 5; ! Writeback ORB after boot fixup literal UNC$C_OBJECT_SERVICE = 6; ! Object service request context literal UNC$C_HDR_LENGTH = 16; ! size of context segment header literal UNC$K_HDR_LENGTH = 16; ! size of context segment header literal UNC$C_LIST = 16; ! offset to first context block literal UNC$K_LIST = 16; ! offset to first context block literal UNC$S_UNCHDRDEF = 16; ! Old size name - synonym literal UNC$S_UNCHDR = 16; macro UNC$L_FLINK = 0,0,32,1 %; ! forward link to next context segment macro UNC$L_BLINK = 4,0,32,1 %; ! back link to previous context segment macro UNC$W_SIZE = 8,0,16,0 %; ! total size of context segment macro UNC$B_TYPE = 10,0,8,0 %; ! VMS type of block (DYN$C_UNC) macro UNC$B_SUBTYPE = 11,0,8,0 %; ! type of context segment macro UNC$W_COUNT = 12,0,16,0 %; ! number of context blocks in segment macro UNC$W_FREE_COUNT = 14,0,16,0 %; ! number of entries free for use macro UNC$R_LIST = 16,0,0,0 %; ! Start of context blocks ! ! Universal Context Block Definition (Go Heels!) ! literal UNC$M_ENTRY_INUSE = %X'1'; literal UNC$M_NEW_ENTRY = %X'2'; literal UNC$M_MBX_NORSWAIT = %X'4'; literal UNC$C_LENGTH = 84; ! size of largest context block literal UNC$K_LENGTH = 84; ! size of largest context block literal UNC$C_SEGMENTS = 5; ! natural number of segments/page literal UNC$K_SEGMENTS = 5; ! natural number of segments/page literal UNC$S_UNCDEF = 84; ! Old size name - synonym literal UNC$S_UNC = 84; macro UNC$W_FLAGS = 0,0,16,0 %; ! context cell flags macro UNC$V_ENTRY_INUSE = 0,0,1,0 %; ! context entry inuse macro UNC$V_NEW_ENTRY = 0,1,1,0 %; ! Newly created entry macro UNC$V_MBX_NORSWAIT = 0,2,1,0 %; ! Return on resource failure macro UNC$B_ACCESS_MODE = 2,0,8,0 %; ! access mode of context cell macro UNC$L_IMAGE_COUNT = 4,0,32,0 %; ! IMGCNT when context cell assigned macro UNC$W_UAI_IFI = 8,0,16,0 %; ! FAB$W_IFI macro UNC$W_UAI_ISI = 10,0,16,0 %; ! RAB$W_ISI macro UNC$W_UAI_CHANNEL = 12,0,16,0 %; ! UAF channel macro UNC$L_AE_IOSB = 8,0,32,1 %; ! IOSB address macro UNC$L_AE_ASTADR = 12,0,32,1 %; ! AST address macro UNC$L_AE_ASTPRM = 16,0,32,0 %; ! AST parameter macro UNC$W_AE_EFN = 20,0,16,0 %; ! EFN number macro UNC$W_AE_CHANNEL = 22,0,16,0 %; ! reply mailbox channel macro UNC$L_AE_FLAGS = 24,0,32,0 %; ! $AUDIT_EVENT flags macro UNC$L_AE_REPLY = 28,0,32,0 %; ! audit server reply status macro UNC$W_AE_QIO_STATUS = 32,0,16,0 %; ! status from $AUDIT_EVENT's $QIO to reply mailbox macro UNC$B_AE_PRVMOD = 40,0,8,0 %; ! mode to deliver completion AST macro UNC$L_SO_CONTEXT = 8,0,32,0 %; ! Value of this context block macro UNC$L_SO_CONTEXT_PTR = 12,0,32,1 %; ! Address of user's context cell macro UNC$L_SO_ACL_POSITION = 16,0,32,0 %; ! Position in the ACL macro UNC$L_SO_LOCKID = 20,0,32,0 %; ! Lock ID for write lock on ORB macro UNC$L_SO_PARENT_ID = 24,0,32,0 %; ! Parent lock ID for SO_LOCKID macro UNC$L_SO_OSR_FLAGS = 28,0,32,0 %; ! OSR processing flags (see $OSRDEF) macro UNC$L_SO_OCB = 32,0,32,1 %; ! Object Class Block address macro UNC$L_SO_ORB = 36,0,32,1 %; ! Address of the ORB macro UNC$L_SO_OBJECT_HANDLE = 40,0,32,1 %; ! Object handle address ! ! OBJNAM_LENGTH and OBJNAM ! must form an string ! descriptor ! macro UNC$W_SO_OBJNAM_LENGTH = 44,0,16,0 %; ! Size of object name macro UNC$W_SO_RESERVED_1 = 46,0,16,0 %; ! Reserved (MBZ) macro UNC$L_SO_OBJNAM = 48,0,32,1 %; ! Object name buffer address ! macro UNC$W_SO_OBJNAM_BUFSIZ = 52,0,16,0 %; ! Size of objnam buffer alloc macro UNC$B_SO_ACMODE = 54,0,8,0 %; ! Access mode macro UNC$B_SO_RESERVED_2 = 55,0,8,0 %; ! Reserved for digital use macro UNC$L_SO_ACLCTX_PTR = 56,0,32,1 %; ! Context return address macro UNC$L_SO_RESERVED_3 = 60,0,32,0 %; ! Reserved for digital use macro UNC$L_SO_RESERVED_4 = 64,0,32,0 %; ! Reserved for digital use macro UNC$T_SO_OSR_CONTEXT = 68,0,0,0 %; literal UNC$S_SO_OSR_CONTEXT = 16; ! Object Support Routine context area macro UNC$L_OF_ASTADR = 8,0,32,1 %; ! AST address macro UNC$L_OF_ASTPRM = 12,0,32,0 %; ! AST parameter macro UNC$L_OF_FLAGS = 16,0,32,0 %; ! flags (object specific) macro UNC$W_OF_STATUS = 20,0,16,0 %; ! completion status macro UNC$B_OF_PRVMOD = 28,0,8,0 %; ! mode to deliver completion AST macro UNC$L_OF_OBJECT = 32,0,32,0 %; ! context for locating the macro UNC$L_OF_OBJECT1 = 36,0,32,0 %; ! next object profile macro UNC$L_OF_OBJECT2 = 40,0,32,0 %; ! (object specific) macro UNC$L_OF_OBJECT3 = 44,0,32,0 %; ! macro UNC$L_OS_ASTADR = 8,0,32,1 %; ! AST address macro UNC$L_OS_ASTPRM = 12,0,32,0 %; ! AST parameter macro UNC$L_OS_FLAGS = 16,0,32,0 %; ! flags (object specific) macro UNC$W_OS_REPL_CHAN = 20,0,16,0 %; ! mailbox channel for reply macro UNC$W_OS_RQST_CHAN = 22,0,16,0 %; ! mailbox channel for request macro UNC$R_OS_IOSB = 24,0,0,0 %; literal UNC$S_OS_IOSB = 8; ! IOSB for $QIO macro UNC$W_OS_STATUS = 24,0,16,0 %; ! completion status macro UNC$B_OS_PRVMOD = 32,0,8,0 %; ! mode to deliver completion AST macro UNC$L_OS_OBJECT = 36,0,32,0 %; ! context for locating the macro UNC$L_OS_OBJECT1 = 40,0,32,0 %; ! next object profile macro UNC$L_OS_OBJECT2 = 44,0,32,0 %; ! (object specific) macro UNC$L_OS_OBJECT3 = 48,0,32,0 %; ! ! ! Object management Context cell layout ! literal OBJCTX$S_CTXDEF = 8; ! Old size name - synonym literal OBJCTX$S_OBJCTX = 8; macro OBJCTX$L_INDEX = 0,0,32,0 %; ! Index in table macro OBJCTX$L_SEQ = 4,0,32,0 %; ! Sequence number !*** MODULE $UTCDEF *** ! + ! ! $UTCDEF defines the storage format for UTC based times. ! ! - literal UTC$M_TDF = %X'FFF'; literal UTC$M_VER = %X'F000'; literal UTC$S_UTCDEF = 16; ! Old size name - synonym literal UTC$S_UTC = 16; macro UTC$A_WHOLE_TIME = 0,0,0,1 %; literal UTC$S_WHOLE_TIME = 16; ! Double quad to fetch entire time macro UTC$Q_ABSTIME = 0,0,0,0 %; literal UTC$S_ABSTIME = 8; ! 64 bit system time ! In units of 100ns ticks macro UTC$Q_TDF_ETC = 8,0,0,0 %; literal UTC$S_TDF_ETC = 8; ! Inaccuracy, TDF, and version macro UTC$L_ABS0 = 0,0,32,0 %; ! Least sig 4 bytes of binary time macro UTC$L_ABS1 = 4,0,32,0 %; ! Most sig 4 bytes of binary time macro UTC$L_INAC = 8,0,32,0 %; ! 4 least sig bytes of inaccuracy macro UTC$L_TDFV = 12,0,32,0 %; ! 4 bits vers, 12 bits TDF, 2 ! most sig bytes of inaccuracy macro UTC$A_INACCUR = 8,0,0,1 %; literal UTC$S_INACCUR = 6; ! Six bytes of inaccuracy ! In units of 100ns ticks macro UTC$W_TDFWRD = 14,0,16,0 %; ! Fetch the TDF and the version macro UTC$V_TDF = 14,0,12,0 %; literal UTC$S_TDF = 12; ! 12 bits of offset from UTC to local ! In units of minutes macro UTC$V_VER = 14,12,4,0 %; literal UTC$S_VER = 4; ! Unsigned version number !*** MODULE $TTYVECDEF *** ! ! ! ! literal CLASS_LENGTH = 40; ! must be at end. literal CLASSS_CLASS_DEF = 40; ! Old size name, synonym for CLASSS_TT_CLASS literal CLASSS_TT_CLASS = 40; macro CLASS_GETNXT = 0,0,32,1 %; ! macro CLASS_PUTNXT = 4,0,32,1 %; ! macro CLASS_SETUP_UCB = 8,0,32,1 %; ! macro CLASS_DS_TRAN = 12,0,32,1 %; ! macro CLASS_DDT = 16,0,32,1 %; ! macro CLASS_READERROR = 20,0,32,1 %; ! macro CLASS_DISCONNECT = 24,0,32,1 %; ! macro CLASS_FORK = 28,0,32,1 %; ! macro CLASS_POWERFAIL = 32,0,32,1 %; ! macro CLASS_TABLES = 36,0,32,1 %; ! literal TABLES_LENGTH = 100; ! must be at end. literal TABLESS_TABLES_DEF = 100; ! Old size name, synonym for TABLESS_TT_TABLES literal TABLESS_TT_TABLES = 100; macro TABLES_FILL1 = 0,0,32,0 %; ! macro TABLES_FILL2 = 4,0,32,0 %; ! macro TABLES_FILL3 = 8,0,32,0 %; ! macro TABLES_FILL4 = 12,0,32,0 %; ! macro TABLES_FILL5 = 16,0,32,0 %; ! macro TABLES_FILL6 = 20,0,32,0 %; ! macro TABLES_FILL7 = 24,0,32,0 %; ! macro TABLES_FILL8 = 28,0,32,0 %; ! macro TABLES_FILL9 = 32,0,32,0 %; ! macro TABLES_FILL10 = 36,0,32,0 %; ! macro TABLES_FILL11 = 40,0,32,0 %; ! macro TABLES_FILL12 = 44,0,32,0 %; ! macro TABLES_FILL13 = 48,0,32,0 %; ! macro TABLES_FILL14 = 52,0,32,0 %; ! macro TABLES_FILL15 = 56,0,32,0 %; ! macro TABLES_FILL16 = 60,0,32,0 %; ! macro TABLES_FILL17 = 64,0,32,0 %; ! macro TABLES_INIT_MID = 68,0,32,0 %; ! macro TABLES_FILL19 = 72,0,32,0 %; ! macro TABLES_POSIX = 76,0,32,0 %; ! macro TABLES_ASIAN = 80,0,32,0 %; ! macro TABLES_FILL22 = 84,0,32,0 %; ! macro TABLES_FILL23 = 88,0,32,0 %; ! macro TABLES_FILL24 = 92,0,32,0 %; ! macro TABLES_FIDRIVER = 96,0,32,0 %; ! literal PORT_LENGTH = 76; ! must be at end. literal PORTS_PORT_DEF = 76; ! Old size name, synonym for PORTS_TT_PORT literal PORTS_TT_PORT = 76; macro PORT_STARTIO = 0,0,32,1 %; ! macro PORT_DISCONNECT = 4,0,32,1 %; ! macro PORT_SET_LINE = 8,0,32,1 %; ! macro PORT_DS_SET = 12,0,32,1 %; ! macro PORT_XON = 16,0,32,1 %; ! macro PORT_XOFF = 20,0,32,1 %; ! macro PORT_STOP = 24,0,32,1 %; ! macro PORT_STOP2 = 28,0,32,1 %; ! macro PORT_ABORT = 32,0,32,1 %; ! macro PORT_RESUME = 36,0,32,1 %; ! macro PORT_SET_MODEM = 40,0,32,1 %; ! macro PORT_GLYPHLOAD = 44,0,32,1 %; ! Glyph loading (was _DMA) macro PORT_MAINT = 48,0,32,1 %; ! macro PORT_FORKRET = 52,0,32,1 %; ! macro PORT_FDT = 56,0,32,1 %; ! macro PORT_START_READ = 60,0,32,1 %; ! Start of PSI specific extensions macro PORT_MIDDLE_READ = 64,0,32,1 %; ! macro PORT_END_READ = 68,0,32,1 %; ! End of PSI specific extensions macro PORT_CANCEL = 72,0,32,1 %; ! Port driver cancel I/O routine for PORT FDT requests ! ! Asian terminal driver vectors ! literal ASIAN_LENGTH = 96; ! must be at end. literal ASIANS_ASIAN_DEF = 96; ! Old size name, synonym for ASIANS_TT_ASIAN literal ASIANS_TT_ASIAN = 96; macro ASIAN_FDTSENSEM = 0,0,32,1 %; ! FDT SENSEMODE macro ASIAN_FDTSENSEC = 4,0,32,1 %; ! FDT SENSECHAR macro ASIAN_FDT_SETM = 8,0,32,1 %; ! FDT SETMODE macro ASIAN_FDT_SETC = 12,0,32,1 %; ! FDT SETCHAR macro ASIAN_UPPER = 16,0,32,1 %; ! FDT upcasing macro ASIAN_JISCON = 20,0,32,1 %; ! JIS conversion macro ASIAN_START_READ = 24,0,32,1 %; ! Read QIO init macro ASIAN_DO_SETM = 28,0,32,1 %; ! Start I/O SETMODE macro ASIAN_DO_SETC = 32,0,32,1 %; ! Start I/O SETCHAR macro ASIAN_BEGIN_ECHO = 36,0,32,1 %; ! Start echo if needed macro ASIAN_CURSOROVERF = 40,0,32,1 %; ! Cursor overflow macro ASIAN_SETUP_UCB = 44,0,32,1 %; ! Set/reset UCB macro ASIAN_FONTFORK = 48,0,32,1 %; ! Fork ODL startup macro ASIAN_CRE_CONTROL = 52,0,32,1 %; ! macro ASIAN_FHPOINTER = 56,0,32,1 %; ! Pointer to FHDRIVER macro ASIAN_DELETE_ASC = 60,0,32,1 %; ! Delete ASC macro ASIAN_ABORT = 64,0,32,1 %; ! AS$ABORT macro ASIAN_FIND_BOL = 68,0,32,1 %; ! Find begin of line macro ASIAN_PRELOAD = 72,0,32,1 %; ! Preload handling macro ASIAN_PRELOAD_FORK = 76,0,32,1 %; ! Deliver preload req. macro ASIAN_DEL_CACHE_FORK = 80,0,32,1 %; ! Deliver del cache req. macro ASIAN_PRELOAD_CLEANUP = 84,0,32,1 %; ! Deliver preload req. macro ASIAN_ADJUST_CURSOR = 88,0,32,1 %; ! update cursor position macro ASIAN_CLONE_UCB = 92,0,32,1 %; ! Clone UCB fixup ! ! FI driver vectors ! literal FIDRIVER_LENGTH = 12; ! must be at end. literal FIDRIVERS_FIDRIVER_DEF = 12; ! Old size name, synonym for ASIANS_TT_ASIAN literal FIDRIVERS_TT_FIDRIVER = 12; macro FIDRIVER_TTREAD = 0,0,32,1 %; ! FDT READ macro FIDRIVER_TTCANCELIO = 4,0,32,1 %; ! CANCEL IO macro FIDRIVER_TTDISCONNECT = 8,0,32,1 %; ! DISCONNECT ! ! Tables pointed to by TTY$A_POSIX ! literal POSIX_TABLES_LENGTH = 16; ! must be at end. literal POSIX_TABLESS_POSIX_TABLES_DEF = 16; ! Old size name, synonym for POSIX_TABLESS_TT_POSIX_TABLES literal POSIX_TABLESS_TT_POSIX_TABLES = 16; macro POSIX_TABLES_PT_POINTER = 0,0,32,0 %; ! macro POSIX_TABLES_PT_PUTNXT = 4,0,32,0 %; ! macro POSIX_TABLES_PT_GETNXT = 8,0,32,0 %; ! macro POSIX_TABLES_PT_WRITING = 12,0,32,0 %; ! !*** MODULE $FTVECDEF *** literal PORT_FT_LENGTH = 100; literal PORTS_FTVECDEF = 100; literal PORTS_FT_VEC = 100; macro PORT_FT_CREATE = 76,0,32,1 %; macro PORT_FT_READ = 80,0,32,1 %; macro PORT_FT_WRITE = 84,0,32,1 %; macro PORT_FT_SET_EVENT = 88,0,32,1 %; macro PORT_FT_CANCEL = 92,0,32,1 %; macro PORT_FT_DECTERM_SET = 96,0,32,1 %; !*** MODULE $POSIXVECDEF *** ! ++ ! ! POSIX driver vectors ! These values are used by TTDRIVER to dispatch to Posix ! driver routines. The pointer to the Posix vector table is ! contained in TTY$A_POSIX in TTDRIVER. The Posix driver wil ! use the $VECINI and $VEC macros to generate its table based ! on these offsets. ! ! __ literal POSIX_LENGTH = 88; ! must be at end. literal POSIXS_POSIX_DEF = 88; ! Old size name, synonym for POSIX$S_POSIX_FDT literal POSIXS_POSIX_FDT = 88; macro POSIX_PUTNXT = 0,0,32,1 %; ! POSIX VECTORS macro POSIX_GETNXT = 4,0,32,1 %; ! macro POSIX_WRITING = 8,0,32,1 %; ! Getnxt entry for POSIXWRITE macro POSIX_DO_SETM = 12,0,32,1 %; ! Startio SET MODE macro POSIX_INTERRUPT = 16,0,32,1 %; ! Send SIGINT macro POSIX_BREAK = 20,0,32,1 %; ! Handle BREAK condition macro POSIX_PARITY = 24,0,32,1 %; ! Handle PARITY error macro POSIX_SIGHUP = 28,0,32,1 %; ! Send SIGHUP macro POSIX_FDT_READ = 32,0,32,1 %; ! macro POSIX_FDT_WRITE = 36,0,32,1 %; ! macro POSIX_FDT_SETM = 40,0,32,1 %; ! macro POSIX_FDT_SENSEM = 44,0,32,1 %; ! macro POSIX_INIT_PTC = 48,0,32,1 %; ! macro POSIX_DELETE_PTC = 52,0,32,1 %; ! macro POSIX_DO_SETC = 56,0,32,1 %; ! not in V1 of Posix macro POSIX_FDT_SETC = 60,0,32,1 %; ! not in V1 of Posix macro POSIX_FDT_SENSEC = 64,0,32,1 %; ! not in V1 of Posix macro POSIX_POWER = 68,0,32,1 %; ! powerfail macro POSIX_DO_READ = 72,0,32,1 %; ! Startio POSIXREAD macro POSIX_DO_WRITE = 76,0,32,1 %; ! Extra write entry point if n macro POSIX_READ_DONE = 80,0,32,1 %; ! Read is being completed macro POSIX_WRITE_DONE = 84,0,32,1 %; ! Write is being completed !*** MODULE $TTYSYMDEF *** ! ++ ! ! Miscellaneous symbols used by the terminal driver. ! ! -- ! ! FORK DISPATCHER BIT DEFINITIONS ! literal TTY$M_FD_UNSOL = %X'1'; literal TTY$M_FD_GETAHD = %X'2'; literal TTY$M_FD_DISCONNECT = %X'4'; literal TTY$M_FD_PORTFORK = %X'8'; literal TTY$M_FD_UNLINK = %X'10'; literal TTY$M_FD_LINK = %X'20'; literal TTY$M_FD_ASIAN_CTRL = %X'40'; literal TTY$M_FD_FONT = %X'80'; literal TTY$M_FD_PRELOAD = %X'100'; literal TTY$M_FD_DEL_CACHE = %X'200'; literal TTY$M_FD_BUSY = %X'400'; literal TTY$S_FORK = 2; ! Old size name, synonym for TTY$S_FORK literal TTY$S_TT_FORK = 2; macro TTY$V_FD_UNSOL = 0,0,1,0 %; ! SEND UNSOLISITED INPUT MESSAGE macro TTY$V_FD_GETAHD = 0,1,1,0 %; ! CREATE A TYPEAHEAD BUFFER macro TTY$V_FD_DISCONNECT = 0,2,1,0 %; ! DISCONNECT AND DELIVER HANGUPAST macro TTY$V_FD_PORTFORK = 0,3,1,0 %; ! FORK DISPATCH FOR THE PORT DRIVER macro TTY$V_FD_UNLINK = 0,4,1,0 %; ! UNLINK PUCB & LUCB (DETACH) macro TTY$V_FD_LINK = 0,5,1,0 %; ! LINK PUCB & LUCB (CONNECT) macro TTY$V_FD_ASIAN_CTRL = 0,6,1,0 %; ! Create Asian control block macro TTY$V_FD_FONT = 0,7,1,0 %; ! Font request delivery macro TTY$V_FD_PRELOAD = 0,8,1,0 %; ! Deliver preload request macro TTY$V_FD_DEL_CACHE = 0,9,1,0 %; ! request delete Soft-ODL cache macro TTY$V_FD_BUSY = 0,10,1,0 %; ! *** MUST REMAIN AT THE END ******** ! ! POSIX FDT RETURN VALUE DEFINITIONS ! literal TTY$M_PF_GETAHD = %X'1'; literal TTY$S_POSIX_FDT_RET = 1; macro TTY$V_PF_GETAHD = 0,0,1,0 %; ! CREATE A TYPEAHEAD BUFFER ! ! POSIX PUTNXT RETURN VALUE DEFINITIONS ! literal TTY$M_PP_XOFF = %X'1'; literal TTY$M_PP_XON = %X'2'; literal TTY$M_PP_CTRLY = %X'4'; literal TTY$M_PP_CTRLYFLUSH = %X'8'; literal TTY$M_PP_GETAHD = %X'10'; literal TTY$M_PP_START = %X'20'; literal TTY$M_PP_STOP = %X'40'; literal TTY$M_PP_ECHO = %X'80'; literal TTY$M_PP_FLUSHONLY = %X'100'; literal TTY$M_PP_MAX = %X'200'; literal TTY$S_POSIX_PUTNXT = 2; macro TTY$V_PP_XOFF = 0,0,1,0 %; ! SEND XOFF macro TTY$V_PP_XON = 0,1,1,0 %; ! SEND XON macro TTY$V_PP_CTRLY = 0,2,1,0 %; ! DELIVER CTRL-Y AST macro TTY$V_PP_CTRLYFLUSH = 0,3,1,0 %; ! CTRL-Y AST AND FLUSH QUEUES macro TTY$V_PP_GETAHD = 0,4,1,0 %; ! CREATE TYPEAHEAD macro TTY$V_PP_START = 0,5,1,0 %; ! CALL TTY$RESUME macro TTY$V_PP_STOP = 0,6,1,0 %; ! CALL TTY$STOP macro TTY$V_PP_ECHO = 0,7,1,0 %; ! ECHO (TTY$GETNEXTCHAR) macro TTY$V_PP_FLUSHONLY = 0,8,1,0 %; ! FLUSH I/O QUEUES macro TTY$V_PP_MAX = 0,9,1,0 %; ! ** MUST BE LAST *** ! ! POSIX GETNXT RETURN VALUE DEFINITIONS ! literal TTY$M_PG_XON = %X'1'; literal TTY$M_PG_LOOP = %X'2'; literal TTY$M_PG_WRITEDONE = %X'4'; literal TTY$S_POSIX_GETNXT = 1; macro TTY$V_PG_XON = 0,0,1,0 %; ! SEND XON macro TTY$V_PG_LOOP = 0,1,1,0 %; ! GO BACK TO GETNXT macro TTY$V_PG_WRITEDONE = 0,2,1,0 %; ! Finish current write ! ! POSIX READERROR RETURN VALUE DEFINITIONS ! literal TTY$M_PR_PURGEAHEAD = %X'1'; literal TTY$M_PR_FLUSH = %X'2'; literal TTY$S_POSIX_READERROR = 1; macro TTY$V_PR_PURGEAHEAD = 0,0,1,0 %; ! PURGE TYPEAHEAD macro TTY$V_PR_FLUSH = 0,1,1,0 %; ! FLUSH I/O QUEUES ! ! CHARACTER CONSTANTS ! literal TTY$C_CTRLA = 1; ! 1 literal TTY$C_CTRLB = 2; ! 2 literal TTY$C_CTRLC = 3; ! 3 literal TTY$C_CTRLD = 4; ! 4 literal TTY$C_CTRLE = 5; ! 5 literal TTY$C_CTRLF = 6; ! 6 literal TTY$C_BELL = 7; ! 7 literal TTY$C_BS = 8; ! 8 literal TTY$C_TAB = 9; ! 9 literal TTY$C_LF = 10; ! 10 literal TTY$C_VT = 11; ! 11 literal TTY$C_FF = 12; ! 12 literal TTY$C_CR = 13; ! 13 literal TTY$C_CTRLN = 14; ! 14 literal TTY$C_CTRLO = 15; ! 15 literal TTY$C_CTRLP = 16; ! 16 literal TTY$C_CTRLQ = 17; ! 17 (XON) literal TTY$C_CTRLR = 18; ! 18 literal TTY$C_CTRLS = 19; ! 19 (XOFF) literal TTY$C_CTRLT = 20; ! 20 literal TTY$C_CTRLU = 21; ! 21 literal TTY$C_CTRLV = 22; ! 22 literal TTY$C_CTRLW = 23; ! 23 literal TTY$C_CTRLX = 24; ! 24 literal TTY$C_CTRLY = 25; ! 25 literal TTY$C_CTRLZ = 26; ! 26 literal TTY$C_ESCAPE = 27; ! 27 literal TTY$C_XON = 17; literal TTY$C_XOFF = 19; literal TTY$C_BLANK = 32; literal TTY$C_DOLLAR = 36; literal TTY$C_PLUS = 43; literal TTY$C_ZERO = 48; literal TTY$C_ONE = 49; literal TTY$C_SCRIPT = 96; literal TTY$C_LOWA = 97; literal TTY$C_LOWZ = 123; literal TTY$C_LOWESC1 = 125; literal TTY$C_LOWESC2 = 126; literal TTY$C_DELETE = 127; literal TTY$C_NL = 128; literal TTY$C_CSI = 155; ! ! Miscellaneous values ! literal TTY$C_MAXPAGLEN = 255; literal TTY$C_MAXPAGWID = 511; literal TTY$C_HIGHIPL = 22; ! ! EDIT READ STATES (STORED IN THE MODE FIELD OF THE READ BUFFER) ! literal TTY$K_ER_NORMAL = 0; ! NORMAL CONTROL-R OR CONTROL-U literal TTY$K_ER_CLRECHO = 1; ! ECHO WITH TABS EXPANDED TO SPACES literal TTY$K_ER_ECHLINE = 2; ! ECHO FROM GIVEN STRING literal TTY$K_ER_UPDCURSOR = 3; ! UPDATE THE CURSOR POSITION THEN EXIT literal TTY$K_ER_EXITING = 4; ! EXIT NOW literal TTY$K_ER_MOVECURSOR = 5; ! MOVE THE CURSOR TO ITS FINAL PLACE literal TTY$K_ER_CLRREST = 6; ! CLEAR THE REST OF THE LINE literal TTY$K_ER_PRMECHO = 7; ! ECHO OUT A PROMPT literal TTY$K_ER_PRMECHO1 = 8; ! RETURN STATE FOR PROMPT ECHOING literal TTY$K_ER_AESECHO = 9; ! ECHO AES STRING ALONE literal TTY$K_ER_RVECHO = 10; ! ECHO READ VERIFY STRING literal TTY$K_ER_SIMCEOL = 11; ! SIMULATE CLEAR TO END OF LINE ! ! EDITING TOKENS ! literal TTY$K_ET_CTRLU = 1; ! CONTROL-U literal TTY$K_ET_CTRLR = 2; ! CONTROL-R literal TTY$K_ET_DELEFT = 3; ! DELETE CHARACTER LEFT literal TTY$K_ET_ESCAPE = 4; ! ESCAPE PREFIX CHARACTER ! ***** END OF THE NORMAL EDITING CHARACTERRSn literal TTY$K_ET_BACK_CHAR = 5; ! BACKUP 1 CHARACTER literal TTY$K_ET_FORWARD_CHAR = 6; ! MOVE FORWARD 1 CHARCTER literal TTY$K_ET_MOVE_EOL = 7; ! MOVE TO THE END OF LINE literal TTY$K_ET_MOVE_BOL = 8; ! MOVE TO THE BEGINNING OF THE LINE literal TTY$K_ET_DELETE_WORD = 9; ! DELETE WORD TO THE LEFT literal TTY$K_ET_QUOTING = 10; ! AND THE QUOTE CHARACTER literal TTY$K_ET_RECALL = 11; ! RECALL THE LAST Command literal TTY$K_ET_TOGGEL = 12; ! TOGGEL BETWEEN INSERT AND OVERSTRIKE MODES literal TTY$K_ET_UNUSED = 13; ! *** MUST REMAIN AT THE END *** literal TTY$K_ET_TERMINATE = 14; ! INDICATES CHARACTERS NOT ALLOWED IN EDITING INPUT LINE literal TTY$K_EDITNORMAL = 4; ! ! INTERNAL FUNCTION CODES ! literal TTY$C_FC_READ = 0; ! 0 READ FUNCTION literal TTY$C_FC_WRITE = 1; ! 1 WRITE FUNCTION literal TTY$C_FC_SETM = 2; ! 2 SET MODE literal TTY$C_FC_SETC = 3; ! 3 SET CHAR literal TTY$C_FC_HANGUP = 4; ! 4 HANGUP literal TTY$C_FC_MAINT = 5; ! 5 MAINTENCE FUNCTION literal TTY$C_FC_CTRL = 6; ! 6 CONTROL ENABLE literal TTY$C_FC_CONNECT = 7; ! 7 CONNECT TO DETACHED TERMINAL literal TTY$C_FC_DISCON = 8; ! 8 DISCONNECT FROM ATTACHED TERMINAL literal TTY$C_FC_POSIXREAD = 9; ! 9 POSIX READ literal TTY$C_FC_POSIXWRITE = 10; ! 10 POSIX WRITE - MAPS TO VMS WRITE literal TTY$C_FC_POSIXSETM = 11; ! 11 POSIX SET MODE literal TTY$C_FC_ASSETM = 12; ! 12 Asian set mode literal TTY$C_FC_ASSETC = 13; ! 13 Asian set characteristics ! ! CHARACTER CHARACTERISTICS ! literal TTY$M_CH_LOWER = %X'8'; literal TTY$M_CH_SPEC = %X'10'; literal TTY$M_CH_CTRL = %X'20'; literal TTY$M_CH_CTRL3 = %X'40'; literal TTY$M_CH_CTRL2 = %X'80'; literal TTY$S_CHAR_CHAR = 1; ! Old size name, synonym for TTY$S_TT_CHAR_CHAR literal TTY$S_TT_CHAR_CHAR = 1; macro TTY$V_CH_FILL = 0,0,3,0 %; literal TTY$S_CH_FILL = 3; macro TTY$V_CH_LOWER = 0,3,1,0 %; macro TTY$V_CH_SPEC = 0,4,1,0 %; macro TTY$V_CH_CTRL = 0,5,1,0 %; macro TTY$V_CH_CTRL3 = 0,6,1,0 %; macro TTY$V_CH_CTRL2 = 0,7,1,0 %; ! ++ ! ! ASDRIVER symbols ! ! -- !*** MODULE ASSYMDEF *** literal AS$M_MD_ODLPARSE = %X'1'; literal AS$M_MD_EDIT = %X'2'; literal AS$M_MD_NOUPCASE = %X'4'; literal AS$M_MD_INPUT = %X'8'; literal AS$M_MD_1978 = %X'10'; literal AS$M_MD_PRELOAD = %X'20'; literal AS$M_MD_4BYTE = %X'40'; literal AS$S_MODEDEF = 1; ! Old size name, synonym for AS$S_AS_MODE literal AS$S_AS_MODE = 1; macro AS$V_MD_ODLPARSE = 0,0,1,0 %; ! Parse ODL request sequence macro AS$V_MD_EDIT = 0,1,1,0 %; ! MOC line editing macro AS$V_MD_NOUPCASE = 0,2,1,0 %; ! Disable MOC upcasing macro AS$V_MD_INPUT = 0,3,1,0 %; ! Input (Kana or Kanji) macro AS$V_MD_1978 = 0,4,1,0 %; ! JIS 1978 code conversion macro AS$V_MD_PRELOAD = 0,5,1,0 %; ! Dynamic glyph preloading macro AS$V_MD_4BYTE = 0,6,1,0 %; ! 4-byte capability literal AS$M_ST_XPORT = %X'1'; literal AS$M_ST_NOTTYGET = %X'2'; literal AS$M_ST_GLOAD = %X'4'; literal AS$M_ST_GLOAD2 = %X'8'; literal AS$M_ST_NOJOBC = %X'10'; literal AS$M_ST_NOECHO = %X'20'; literal AS$M_ST_TIM = %X'40'; literal AS$S_ODLLOADDEF = 1; ! Old size name; synonym for AS$S_AS_ODLLOAD literal AS$S_AS_ODLLOAD = 1; macro AS$V_ST_XPORT = 0,0,1,0 %; ! Extended Port macro AS$V_ST_NOTTYGET = 0,1,1,0 %; ! No TTYGET macro AS$V_ST_GLOAD = 0,2,1,0 %; ! Glyph Load macro AS$V_ST_GLOAD2 = 0,3,1,0 %; ! Glyph Load 2 macro AS$V_ST_NOJOBC = 0,4,1,0 %; ! No JOBCONT macro AS$V_ST_NOECHO = 0,5,1,0 %; ! No Echo macro AS$V_ST_TIM = 0,6,1,0 %; ! Timer Active literal AS$M_PR_REQUEST = %X'F'; literal AS$M_PR_XAREA = %X'10'; literal AS$M_PR_XSEQ = %X'20'; literal AS$M_PR_SKIP = %X'40'; literal AS$S_ODLPARSEDEF = 1; ! Old size name; synonym for AS$S_AS_ODLPARSE literal AS$S_AS_ODLPARSE = 1; macro AS$V_PR_REQUEST = 0,0,4,0 %; literal AS$S_PR_REQUEST = 4; ! Req. seq. stat macro AS$V_PR_XAREA = 0,4,1,0 %; ! Extend Area macro AS$V_PR_XSEQ = 0,5,1,0 %; ! Extended request sequence macro AS$V_PR_SKIP = 0,6,1,0 %; ! Skip parsing in downloading literal AS$M_TR_ESCSEEN = %X'1'; literal AS$M_TR_1STOF2B = %X'2'; literal AS$M_TR_WAS_XA8 = %X'4'; literal AS$M_TR_KANAMODE = %X'8'; literal AS$M_TR_UPCASE = %X'10'; literal AS$M_TR_SS2 = %X'20'; literal AS$M_TR_SS3 = %X'40'; literal AS$S_JISTRANSDEF = 1; ! Old size name; synonym for AS$S_AS_JISTRANS literal AS$S_AS_JISTRANS = 1; macro AS$V_TR_ESCSEEN = 0,0,1,0 %; ! ESC seen macro AS$V_TR_1STOF2B = 0,1,1,0 %; ! 1st of 2Byte macro AS$V_TR_WAS_XA8 = 0,2,1,0 %; ! it was x'A8' macro AS$V_TR_KANAMODE = 0,3,1,0 %; ! Kana mode macro AS$V_TR_UPCASE = 0,4,1,0 %; ! Upper-case ASCII code macro AS$V_TR_SS2 = 0,5,1,0 %; ! SS2 seen macro AS$V_TR_SS3 = 0,6,1,0 %; ! SS3 seen literal AS$M_ED_EDIT = %X'1'; literal AS$M_ED_NOUPCASE = %X'2'; literal AS$M_ED_RETBYTE = %X'4'; literal AS$M_ED_GOTMOC = %X'8'; literal AS$M_ED_GOTMULTI = %X'10'; literal AS$M_ED_EXPNEXT = %X'20'; literal AS$M_ED_ECHOMOC = %X'40'; literal AS$M_ED_EDITMOC = %X'80'; literal AS$S_ASEDITDEF = 1; ! Old size name; synonym for AS$S_AS_EDIT literal AS$S_AS_EDIT = 1; macro AS$V_ED_EDIT = 0,0,1,0 %; ! MOC editing required macro AS$V_ED_NOUPCASE = 0,1,1,0 %; ! Disable MOC upcasing macro AS$V_ED_RETBYTE = 0,2,1,0 %; ! Can return incomplete MOC macro AS$V_ED_GOTMOC = 0,3,1,0 %; ! Got a MOC macro AS$V_ED_GOTMULTI = 0,4,1,0 %; ! Remove whole MOC from TA buffer macro AS$V_ED_EXPNEXT = 0,5,1,0 %; ! Expecting next byte of MOC macro AS$V_ED_ECHOMOC = 0,6,1,0 %; ! MOC echo in pregress macro AS$V_ED_EDITMOC = 0,7,1,0 %; ! MOC edit (e.g. del) literal AS$M_XE_EXP2ND = %X'1'; literal AS$M_XE_EXP3RD = %X'2'; literal AS$M_XE_EXP4TH = %X'4'; literal AS$S_ASXEDDEF = 1; ! Old size name; synonym for AS$S_AS_XED literal AS$S_AS_XED = 1; macro AS$V_XE_EXP2ND = 0,0,1,0 %; ! Expecting MOC 2nd byte macro AS$V_XE_EXP3RD = 0,1,1,0 %; ! Expecting MOC 3rd byte macro AS$V_XE_EXP4TH = 0,2,1,0 %; ! Expecting MOC 4th byte ! ++ ! VMS/Japanaese Multi Code Set Support bit ! -- literal AS$M_MCE_SS2 = %X'1'; literal AS$M_MCE_SS3 = %X'2'; literal AS$M_MCE_EXP2ND = %X'4'; literal AS$M_MCE_EXP3RD = %X'8'; literal AS$M_MCE_EXPSS2NXT = %X'10'; literal AS$S_MCEDEF = 1; macro AS$V_MCE_SS2 = 0,0,1,0 %; ! Handling SS2 bit macro AS$V_MCE_SS3 = 0,1,1,0 %; ! Handling SS3 bit macro AS$V_MCE_EXP2ND = 0,2,1,0 %; ! Expect 2nd byte of SS3 macro AS$V_MCE_EXP3RD = 0,3,1,0 %; ! Expect 3rd byte of SS3 macro AS$V_MCE_EXPSS2NXT = 0,4,1,0 %; ! Expect 2nd byte of SS2 ! ++ ! VMS/Japanaese Output Character State bit ! -- literal AS$M_OCS_MBCHAR = %X'8000'; literal AS$S_OCSDEF = 2; macro AS$V_OCS_FILL = 0,0,15,0 %; literal AS$S_OCS_FILL = 15; ! (reserved) macro AS$V_OCS_MBCHAR = 0,15,1,0 %; ! Expect a next byte of MB Char ! ++ ! ODL parse State ! -- literal AS$C_PR_DONE = 0; ! Whole sequence is parsed literal AS$C_PR_DCS = 1; ! Parsed DCS, expect 1st P1 literal AS$C_PR_PAR11 = 2; ! Parsed 1st P1 parameter, expect 2nd literal AS$C_PR_PARA = 3; ! Parsed all P1 parameters, expect 'x' literal AS$C_PR_TERM = 4; ! Parsed 'x', expect 1st byte of code literal AS$C_PR_1STB = 5; ! Parsed 1st byte of code, expect 2nd literal AS$C_PR_2NDB = 6; ! Parsed 2nd byte of code, expect ST ! ++ ! VMS/Japanaese Multi Code Set Support SS handling state ! -- literal AS$C_SS2 = 142; literal AS$C_SS3 = 143; ! ++ ! Dispatch code returned by AS$MOVEREADATA ! -- literal AS$C_GD_DISMISS = 0; ! 0 - DISMISS literal AS$C_GD_GETNXT = 1; ! 1 - TTY$GETNEXTCHAR literal AS$C_GD_FORMAT_CHAR = 2; ! 2 - FORMAT_CHAR literal AS$C_GD_FORMAT_LOCAL = 3; ! 3 - FORMAT_LOCAL literal AS$C_GD_STRTMULTI = 4; ! 4 - STRTMULTI literal AS$C_GD_STRTMULTI_1 = 5; ! 5 - STRTMULTI_1 literal AS$C_GD_EOLSEEN = 6; ! 6 - EOLSEEN literal AS$C_GD_XON = 7; ! 7 - XON literal AS$C_GD_MOVE_BOL = 8; ! 8 - MOVE_BOL literal AS$C_GD_MOVE_EOL = 9; ! 9 - MOVE_EOL literal AS$C_GD_BACKSPACING = 10; ! 10 - BACKSPACING literal AS$C_GD_EDITREAD = 11; ! 11 - EDITREAD literal AS$C_GD_UPDATE_CURSOR = 12; ! 12 - UPDATE_CURSOR literal AS$C_GD_OUTPUTANDWAIT = 13; ! 13 - OUTPUTANDWAIT ! ++ ! Miscellaneous symbols ! -- literal AS$C_MOC_MIN = 161; !*** MODULE $TTYRBDEF *** ! ++ ! Read buffer definitions ! ! This buffer is allocated everytime a read is issued. The ! buffer contains all the information necessary to perform this read. ! ! -- literal TTY$M_RS_WRAP = %X'1'; literal TTY$S_TTYRBDEF = 84; ! Old size name; synonym for TTY$S_TT_READBUF literal TTY$S_TT_READBUF = 84; macro TTY$L_RB_TXT = 0,0,32,1 %; ! Address of the first character of ! the read data. macro TTY$L_RB_UVA = 4,0,32,1 %; ! READ BUFFER - USER VIRTUAL ADDR macro TTY$W_RB_SIZE = 8,0,16,0 %; ! READ BUFFER - BLOCK SIZE macro TTY$W_RB_TYPE = 10,0,16,0 %; ! buffer type macro TTY$W_RB_ECHLEN = 12,0,16,0 %; ! NUMBER OF CHARACTERS TO ECHO ! WHEN OUTPUTTING FROM ECHSTR macro TTY$W_RB_NONFILL = 14,0,16,0 %; ! POSITION OF 1ST NONFILL CHAR macro TTY$Q_RB_ECHOAREA = 16,0,0,0 %; literal TTY$S_RB_ECHOAREA = 8; ! WORDS TO ECHO CHARACTERS FROM macro TTY$L_RB_ECHSTR = 24,0,32,1 %; ! ADDRESS OF THE FIRST CHARACTER ! TO OUTPUT DURING EDITECHOING. macro TTY$L_RB_PIC = 28,0,32,1 %; ! ADDRESS OF THE PICTURE STRING ! FOR READ VERIFY macro TTY$L_RB_TERM = 32,0,32,1 %; ! THE ADDRESS OF THE TERMINATOR BITMASK macro TTY$L_RB_MOD = 36,0,32,0 %; ! MODIFIER LONGWORD macro TTY$L_RB_AES = 40,0,32,1 %; ! ADDRESS OF THE AES STRING macro TTY$W_RB_AESLEN = 44,0,16,0 %; ! THE LENGTH OF THE AESSTRING macro TTY$W_RB_RDSTATE = 46,0,16,0 %; ! Read state information word macro TTY$V_RS_WRAP = 46,0,1,0 %; ! THE READ HAS WRAPPED EITHER IN THE PROMPT OR INITIAL STRING macro TTY$L_RB_LIN = 48,0,32,1 %; ! ADDRESS OF THE FIRST CHARACTER ON ! THIS LINE. macro TTY$W_RB_LINOFF = 52,0,16,0 %; ! OFFSET FROM THE BEGINNING OF THE ! LINE TO THE CURSOR POSITION. macro TTY$W_RB_LINREST = 54,0,16,0 %; ! NUMBER OF CHARACTERS TO THE RIGHT ! OF THE CURSOR POSITION, USED BY ! INPUT EDITING macro TTY$W_RB_PRMLEN = 56,0,16,0 %; ! LENGTH IN BYTES OF THE PROMPT STRING macro TTY$W_RB_TIMOS = 58,0,16,0 %; ! READ BUFFER - TIMEOUT SECONDS macro TTY$W_RB_CPZCUR = 60,0,16,0 %; ! CURRENT CURSOR POSITION macro TTY$W_RB_CPZORG = 62,0,16,0 %; ! READ BUFFER - ORIGONAL HORIZON macro TTY$W_RB_TXTOFF = 64,0,16,0 %; ! OFFSET FROM THE BEGINNING OF THE ! DATA TO THE LOCATION OF THE NEXT CHARACTER macro TTY$W_RB_PICLEN = 66,0,16,0 %; ! the length of the picture string macro TTY$W_RB_TXTSIZ = 68,0,16,0 %; ! THE LENGTH OF THE READ. macro TTY$W_RB_TXTECH = 70,0,16,0 %; ! AMOUNT OF INITIAL STRING TO ECHO macro TTY$W_RB_MODE = 72,0,16,0 %; ! VALUE INDICATING READ EDIT MODE macro TTY$B_RB_RVFCLR = 74,0,8,0 %; ! CLEAR CHARACTER FOR READ VERIFY macro TTY$B_RB_RVFFIL = 75,0,8,0 %; ! READ VERIFY FILL CHARACTER macro TTY$W_RB_ESCTKN = 76,0,16,0 %; ! ESCAPE TOKEN CHARACTER macro TTY$W_RB_TXTONLYSIZ = 78,0,16,0 %; ! SIZE OF TEXT W/OUT TERMINATOR macro TTY$A_RB_PRM = 80,0,32,0 %; ! ADDRESS OF BEGINNING OF THE PROMPT macro TTY$L_RB_DATA = 80,0,32,1 %; ! READ BUFFER - DATA !*** MODULE $TTYISDEF *** ! ++ ! ITEM LIST STACK STRUCTURE ! ! WARNING: STRUCTURE MUST ALWAYS BE FORCED TO A LONGWORD BOUNDARY. ! ! DESCRIPTION: ! THIS STRUCTURE IS ALLOCATED OFF THE STACK WHEN AN ITEM LIST QIO IS ! DETECTED. ! -- literal TTY$K_IS_LENGTH = 96; ! LENGTH literal TTY$S_TTYISDEF = 96; ! Old size name, synonym for TTY$S_TT_ITEM_STK literal TTY$S_TT_ITEM_STK = 96; macro TTY$L_IS_ACMODE = 0,0,32,0 %; ! ACCESS MODE MAXIMIZED WITH THE MODE OF THE CALLER macro TTY$L_IS_EDITMODE = 4,0,32,0 %; ! PLACE TO KEEP THE MODE macro TTY$L_IS_BUF = 8,0,32,1 %; ! THE USERS ADDRESS OF HIS BUFFER macro TTY$L_IS_BUFLEN = 12,0,32,0 %; ! THE LENGTH OF THE USERS BUFFER macro TTY$L_IS_INI = 16,0,32,1 %; ! USERS INITIAL STRING ADDRESS macro TTY$L_IS_INILEN = 20,0,32,0 %; ! LENGTH OF THE INITIAL STRING macro TTY$L_IS_INIBUF = 24,0,32,0 %; ! length of initial buffer for fallback use macro TTY$L_IS_ITMLST = 28,0,32,1 %; ! THE USERS ADDRESS OF THE ITEM LIST ! USED AS A POINTER TO THE NEXT ENTRY macro TTY$L_IS_LASTITM = 32,0,32,1 %; ! USERS ADDRESS OF THE LAST ITEM ! CALCULATED FROM BEGINNING ADDRESS AND LENGTH macro TTY$L_IS_MODIFY = 36,0,32,0 %; ! THE USERS MODIFIER BITS macro TTY$L_IS_PIC = 40,0,32,1 %; ! USERS ADDRESS OF THE PICTURE STRING macro TTY$L_IS_PICLEN = 44,0,32,0 %; ! THE LENGTH OF THE PICTURE STRING macro TTY$L_IS_PRM = 48,0,32,1 %; ! USERS ADDRESS OF THE PROMPT STRING macro TTY$L_IS_PRMLEN = 52,0,32,0 %; ! THE LENGTH OF THE PROMPT STRING macro TTY$L_IS_PRMBUF = 56,0,32,0 %; ! length of prompt for fallback use macro TTY$L_IS_SPECIFYED = 60,0,32,0 %; ! BITMASK OF SPECIFYED ITEM LIST ENTRIES macro TTY$L_IS_TERM = 64,0,32,1 %; ! THE ADDRESS OF THE USERS TERMINATOR MASK macro TTY$L_IS_TERMLEN = 68,0,32,1 %; ! THE LENGTH OF THE USERS TERMINATOR MASK macro TTY$L_IS_AES = 72,0,32,1 %; ! THE ADDRESS OF THE ALTERNATE ECHO STRING macro TTY$L_IS_AESLEN = 76,0,32,0 %; ! THE LENGTH OF THE ALTERNATE ECHO STRING macro TTY$L_IS_TIMEOUT = 80,0,32,0 %; ! TIMEOUT VALUE macro TTY$W_IS_FILLCHR = 84,0,16,0 %; ! TWO BYTES SPECIFYING FILL AND CLEAR CHARACTER macro TTY$W_IS_INIOFF = 86,0,16,0 %; ! OFFSET INTO INITIAL STRING FOR ECHOING macro TTY$W_IS_ESCTRMOVR = 88,0,16,0 %; ! ESCAPE TERMINATOR OVERFLOW SIZE macro TTY$W_IS_SPAREW = 90,0,16,0 %; ! round to longword macro TTY$L_IS_SPAREL = 92,0,32,0 %; ! round to quadword boundary !*** MODULE $TTYILDEF *** ! ++ ! Itemlist Descriptor ! ! Description: ! This set of definitions defines the locations of all the fields ! in the terminal QIO item list. ! -- literal TTY$K_IL_LENGTH = 12; ! LENGTH literal TTY$S_TTYILDEF = 12; ! Old size name, synonym for TTY$S_TT_ITEM_LIST literal TTY$S_TT_ITEM_LIST = 12; macro TTY$W_IL_LEN = 0,0,16,0 %; ! THE LENGTH OF THE BUFFER POINTED TO BY ADR macro TTY$W_IL_TYPE = 2,0,16,0 %; ! THE TYPE CODE OF THIS ITEM macro TTY$L_IL_ADR = 4,0,32,0 %; ! THE USER SPECIFYED ADDRESS macro TTY$L_IL_RETADR = 8,0,32,0 %; ! VALUE RETURNED ADDRESS !*** MODULE $TTYTADEF *** ! ++ ! TYPEAHEAD BUFFER ! ! DESCRIPTION: ! THIS BUFFER IS USED TO STORE CHARACTERS BEFORE PROCESSING AND ! MOVING THEM INTO THE USERS READ BUFFER. ! ALLOCATED ON UNSOLICITED DATA OR THE FIRST READ POSTED ON A TERMINAL ! LINE. ! -- literal TTY$K_TA_RCLLEN = 256; ! LENGTH OF RECALL literal TTY$S_TTYTADEF = 284; ! Old size name, synonym for TTY$S_TT_TYPE_AHD literal TTY$S_TT_TYPE_AHD = 284; ! THE LENGTH OF THE RECALL BUFFER macro TTY$L_TA_PUT = 0,0,32,1 %; ! PUT POINTER macro TTY$L_TA_GET = 4,0,32,1 %; ! GET POINTER macro TTY$W_TA_SIZE = 8,0,16,0 %; ! BLOCK SIZE macro TTY$B_TA_TYPE = 10,0,8,0 %; ! macro TTY$B_TA_SPARE1 = 11,0,8,0 %; macro TTY$W_TA_INAHD = 12,0,16,0 %; ! COUNT OF CHARS IN BUFFER macro TTY$W_TA_RCLOFF = 14,0,16,0 %; ! NUMBER OF CHARACTERS IN THE RECALL ! BUFFER USED. macro TTY$L_TA_END = 16,0,32,1 %; ! END ADDRESS macro TTY$W_TA_RCLSIZ = 20,0,16,0 %; ! THE SIZE OF THE RECALL STRING macro TTY$W_TA_SPARE2 = 22,0,16,0 %; macro TTY$A_TA_RCL = 24,0,0,0 %; literal TTY$S_TA_RCL = 256; ! TYPEAHEAD BUFFER - RECALL BUFFER macro TTY$L_TA_DATA = 280,0,32,1 %; ! TYPEAHEAD BUFFER - DATA START !*** MODULE $TTYMDMDEF *** ! aka $TTYMODEM via hack in TTYMACS.MAR ! ! Modem control state table definitions ! ! ! state entry definitions ! literal MODEM$C_ST_LENGTH = 8; ! LENGTH literal MODEM$S_MODEM_STATE = 8; ! Old size name, synonym for MODEM$S_TT_MODEM_STATE literal MODEM$S_TT_MODEM_STATE = 8; macro MODEM$B_ST_ONMASK = 0,0,8,0 %; ! output signals to activate macro MODEM$B_ST_OFFMASK = 1,0,8,0 %; ! output signals to disable macro MODEM$W_ST_TIMER = 2,0,16,0 %; ! timer amount to init macro MODEM$L_ST_ROUTINE = 4,0,32,1 %; ! action routine ADDRESS ! ! transition definitions ! literal MODEM$C_TRAN_LENGTH = 8; ! LENGTH literal MODEM$S_MODEM_TRANS = 8; ! Old size name, synonym for MODEM$S_TT_MODEM_TRANS literal MODEM$S_TT_MODEM_TRANS = 8; macro MODEM$B_TRAN_TYPE = 0,0,8,0 %; ! element type macro MODEM$B_TRAN_TYPE2 = 1,0,8,0 %; ! unused element type macro MODEM$B_TRAN_OFFMASK = 2,0,8,0 %; ! input signals test on macro MODEM$B_TRAN_ONMASK = 3,0,8,0 %; ! input signals test off macro MODEM$L_TRAN_NSTATE = 4,0,32,1 %; ! next state ADDRESS ! ! transition type codes ! literal MODEM$C_TRAN_DATASET = 0; ! dataset literal MODEM$C_TRAN_TIME = 1; ! timer literal MODEM$C_TRAN_END = 2; ! end of transition list literal MODEM$C_TRAN_DIALTYPE = 3; ! test for sysgen parameter literal MODEM$C_TRAN_DZ11 = 4; ! controller = DZ11 literal MODEM$C_TRAN_NOMODEM = 5; ! line not enabled for modem ! ! argument type codes ! literal MODEM$C_INIT = 0; ! init line literal MODEM$C_SHUTDWN = 1; ! hangup command literal MODEM$C_NULL = 2; ! null, for detecting preset conditions literal MODEM$C_DATASET = 3; ! dataset interrupt literal MODEM$C_TIMER = 4; ! timer expiration literal MODEM$C_INIT_NORESET = 5; ! init modem but not signals literal MODEM$C_SHUTDWN_NOHANGUP = 6; ! stop modem but not signals literal TIMCTRL$M_CANCEL = %X'1'; literal TIMCTRL$M_ACTIVE = %X'2'; literal TIMCTRL$S_MODEM_BITS = 1; ! Old size name, synonym for TIMCTRL$S_TT_MODEM_BITS literal TIMCTRL$S_TT_MODEM_BITS = 1; macro TIMCTRL$V_CANCEL = 0,0,1,0 %; ! CANCEL TIMER REQUEST macro TIMCTRL$V_ACTIVE = 0,1,1,0 %; ! TIMER CURRENTLY ACTIVE literal MODEM$M_ENABLE = 32768; ! mask enable !*** MODULE $TTYDEF *** ! ++ ! ! Terminal driver write packet (TWP) ! ! -- literal TTY$K_WB_LENGTH = 56; ! LENGTH literal TTY$C_WB_LENGTH = 56; ! LENGTH literal TTY$S_TTYWBDEF = 60; ! Old size name, synonym for TWP$S_TWP literal TTY$S_TWP = 60; macro TTY$L_WB_FLINK = 0,0,32,1 %; ! macro TTY$L_WB_BLINK = 4,0,32,1 %; ! macro TTY$W_WB_SIZE = 8,0,16,0 %; ! macro TTY$B_WB_TYPE = 10,0,8,0 %; ! macro TTY$B_WB_FLCK = 11,0,8,0 %; ! macro TTY$L_WB_FPC = 12,0,32,1 %; ! macro TTY$Q_WB_FR3 = 16,0,0,1 %; literal TTY$S_WB_FR3 = 8; ! macro TTY$Q_WB_FR4 = 24,0,0,1 %; literal TTY$S_WB_FR4 = 8; ! macro TTY$L_WB_MAP = 32,0,32,1 %; ! macro TTY$L_WB_NEXT = 36,0,32,1 %; ! macro TTY$L_WB_END = 40,0,32,1 %; ! macro TTY$L_WB_IRP = 44,0,32,1 %; ! macro TTY$W_WB_STATUS = 48,0,16,0 %; ! macro TTY$W_WB_BCNT = 50,0,16,0 %; ! macro TTY$L_WB_RETADDR = 52,0,32,1 %; ! macro TTY$L_WB_DATA = 56,0,32,1 %; ! !*** MODULE $TTYDIALTYP *** ! ! Assign meanings to bits in the TTY_DIALTYP SYSGEN parameter. ! literal TTY$M_RINGWAIT = %X'1'; literal TTY$M_FAST_SHUTDOWN = %X'2'; literal TTY$M_NO_REFC = %X'4'; literal TTY$M_A_SPEEDS = %X'8'; literal TTY$S_DIALTYP_BITS = 1; ! Old size name, synonym for TTY$S_TTY_DIALTYP literal TTY$S_TTY_DIALTYP = 1; macro TTY$V_RINGWAIT = 0,0,1,0 %; ! WAIT FOR RING BEFORE SET DTR macro TTY$V_FAST_SHUTDOWN = 0,1,1,0 %; ! SHUTDOWN IMMED. IF LOSE CARRIER macro TTY$V_NO_REFC = 0,2,1,0 %; ! SKIP CHECK FOR REFC macro TTY$V_A_SPEEDS = 0,3,1,0 %; ! IF SET, USE A SPEED TABLE ! last bit reserved for internal ! use !*** MODULE $UQBDEF *** ! + ! UQB (Unit Queue Block) Definitions -- MSCP Server, TMSCP Server ! ! This data structure has all the information pertaining ! to a unit that is currently being served. It is most used ! for the list head of all requests for this unit. ! - literal UQB$M_SEQ = %X'1'; literal UQB$M_WRTPH = %X'2'; literal UQB$M_WRTPS = %X'4'; literal UQB$M_ONLINE = %X'8'; literal UQB$M_FLUSH = %X'10'; literal UQB$M_DUNN = %X'20'; literal UQB$M_C = %X'1F'; literal UQB$M_D1 = %X'3E0'; literal UQB$M_D0 = %X'7C00'; literal UQB$K_ST_ONLINE = 2; ! Unit is online to some host literal UQB$K_ST_OFFLINE = 3; ! Unit is offline literal UQB$K_ST_AVAILABLE = 4; ! Unit is available literal UQB$S_UQB = 112; macro UQB$L_FLINK = 0,0,32,1 %; ! Used to link together all macro UQB$L_BLINK = 4,0,32,1 %; ! UQBs being served macro UQB$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro UQB$B_TYPE = 10,0,8,0 %; ! MSCP type structure macro UQB$B_SUBTYPE = 11,0,8,0 %; ! with a UQB subtype (5) macro UQB$W_STATE = 12,0,16,0 %; ! Current state of this unit macro UQB$W_FLAGS = 14,0,16,0 %; ! Unit usage macro UQB$V_SEQ = 14,0,1,0 %; ! Sequential command executing macro UQB$V_WRTPH = 14,1,1,0 %; ! Unit is writelocked macro UQB$V_WRTPS = 14,2,1,0 %; ! Unit was mounted /NOWRITE macro UQB$V_ONLINE = 14,3,1,0 %; ! Unit is ONLINE. macro UQB$V_FLUSH = 14,4,1,0 %; ! Per-unit cache is being flushed macro UQB$V_DUNN = 14,5,1,0 %; ! Device uses new naming macro UQB$W_OLD_UNIT = 16,0,16,0 %; ! "Old Style" unit number macro UQB$W_CURRENT = 18,0,16,0 %; ! Commands active on this unit macro UQB$W_MULT_UNIT = 20,0,16,0 %; ! This information is set up macro UQB$W_UNIT_FLAGS = 22,0,16,0 %; ! in ADDUNIT when the device macro UQB$Q_UNIT_ID = 24,0,0,0 %; literal UQB$S_UNIT_ID = 8; ! is set /SERVED. macro UQB$L_ALLOCLS = 24,0,32,0 %; ! The unit identifier is made up macro UQB$W_UNIT = 28,0,16,0 %; ! of the allocation class, the macro UQB$W_DEVNAME = 30,0,16,0 %; ! macro UQB$V_C = 30,0,5,0 %; literal UQB$S_C = 5; ! UCB unit number, the controller macro UQB$V_D1 = 30,5,5,0 %; literal UQB$S_D1 = 5; ! letter, and the D1 D0 fields macro UQB$V_D0 = 30,10,5,0 %; literal UQB$S_D0 = 5; ! from the media ID field macro UQB$l_reserved = 32,0,32,0 %; ! macro UQB$L_UCB = 36,0,32,1 %; ! UCB address for this unit macro UQB$W_NUM_QUE = 40,0,16,0 %; ! Host requests pending macro UQB$W_MAX_QUE = 42,0,16,0 %; ! Most requests ever pending macro UQB$L_BLOCKED_FL = 44,0,32,1 %; ! List head for HRBs pending macro UQB$L_BLOCKED_BL = 48,0,32,1 %; ! sequential cmd completion macro UQB$B_ONLINE = 52,0,0,0 %; literal UQB$S_ONLINE = 32; ! Array of hosts with unit online macro UQB$L_EXTRA_IO = 84,0,32,0 %; ! Splinter requests macro UQB$L_IOCNT = 88,0,32,0 %; ! Server contribution to total macro UQB$W_QLEN = 92,0,16,0 %; ! Server queue length for unit macro UQB$W_SLUN = 94,0,16,0 %; ! Server local unit number ! max chars in Cluster unique ! device name ( dependency in ! PEDRIVER's PEM_DEF.SDL) macro UQB$B_UNIQUE_DNAME_CNT = 96,0,8,0 %; ! .ASCIC string with macro UQB$T_UNIQUE_DNAME = 97,0,0,0 %; literal UQB$S_UNIQUE_DNAME = 15; ! Cluster unique name for disk ! unit (obtained VIA GETDVI ! ALLDEVNAM item) ! Unit state definitions literal UQB$M_ST_BOT = %X'1'; literal UQB$M_ST_DLS = %X'2'; literal UQB$M_ST_EOT = %X'4'; literal UQB$M_ST_LEOT = %X'8'; literal UQB$M_ST_PLS = %X'10'; literal UQB$M_ST_SEREX = %X'20'; literal UQB$M_ST_WRTPH = %X'40'; literal UQB$S_TSRV_EXTENSION = 208; macro UQB$L_ONLINE_HQB = 112,0,32,1 %; ! Unit is excl. onl. to this host. macro UQB$L_MEMW_TOT = 116,0,32,0 %; ! Number of I/Os that had to wait. macro UQB$L_MEMW_FL = 120,0,32,1 %; ! Queue listhead for requests macro UQB$L_MEMW_BL = 124,0,32,1 %; ! in memory wait state. macro UQB$W_MEMW_CNT = 128,0,16,0 %; ! Current memory stalls. macro UQB$W_MEMW_MAX = 130,0,16,0 %; ! Most requests ever in MEMWAIT macro UQB$L_CACHE_FL = 132,0,32,1 %; ! Queue listhead for requests macro UQB$L_CACHE_BL = 136,0,32,1 %; ! in server cache. macro UQB$W_NUM_CACHE = 140,0,16,0 %; ! Number of requests in cache. macro UQB$W_MAX_CACHE = 142,0,16,0 %; ! Max ever cached macro UQB$L_FREELIST_FL = 144,0,32,1 %; ! Queue listhead for available macro UQB$L_FREELIST_BL = 148,0,32,1 %; ! local buffers macro UQB$W_BUFF_AVAIL = 152,0,16,0 %; ! Number of free buffers macro UQB$W_MAX_BUFF_AVAIL = 154,0,16,0 %; ! Max ever of free buffers macro UQB$W_BUFF_ALLOC = 156,0,16,0 %; ! Number of allocated buffers macro UQB$W_MAX_BUFF_ALLOC = 158,0,16,0 %; ! Max number of buffers alloc. macro UQB$L_SERV_RSPID = 160,0,32,0 %; ! Last RSPID checked in GCS macro UQB$L_CLASS_RSPID = 164,0,32,0 %; ! Last class driver RSPID macro UQB$L_OLD_CLSSTS = 168,0,32,0 %; ! Class driver command status. macro UQB$W_TAPEM_SKIP = 172,0,16,0 %; ! Storage for REPOS. OBJECT macro UQB$W_RECORD_SKIP = 174,0,16,0 %; ! Storage for REPOS. OBJECT macro UQB$L_STARTSTOP = 176,0,32,0 %; ! Start/stop time for drive macro UQB$L_IO_TIME = 180,0,32,0 %; ! Cycle time of IO to local drive macro UQB$W_NUM_IO = 184,0,16,0 %; ! Number of IOs issued to drive macro UQB$W_MAX_IO = 186,0,16,0 %; ! Max num of IOs outstanding to ! to drive macro UQB$L_ARR_TIME = 188,0,32,0 %; ! Average time it takes the host ! to respond to a request and ! send the next request out. macro UQB$W_NUM_FLUSH = 192,0,16,0 %; ! Number of flush commands. macro UQB$W_MAX_NUM_FLUSH = 194,0,16,0 %; ! Max number of flush commands. macro UQB$L_POSITION = 196,0,32,0 %; ! Unit's current position macro UQB$W_ST_FLAGS = 200,0,16,0 %; ! Unit usage macro UQB$V_ST_BOT = 200,0,1,0 %; ! BOT macro UQB$V_ST_DLS = 200,1,1,0 %; ! Cached data lost macro UQB$V_ST_EOT = 200,2,1,0 %; ! End of tape macro UQB$V_ST_LEOT = 200,3,1,0 %; ! Logical end of tape macro UQB$V_ST_PLS = 200,4,1,0 %; ! Position lost macro UQB$V_ST_SEREX = 200,5,1,0 %; ! Serious exception state macro UQB$V_ST_WRTPH = 200,6,1,0 %; ! Write protected literal UQB$C_LENGTH = 208; literal UQB$K_LENGTH = 208; !*** MODULE $VCADEF *** ! + ! ! VCA - Volume Cache Block. This block contains the specialized caches for ! a disk volume; to wit, the file ID cache, the extent cache, and the quota ! file cache. The file ID cache and extent cache are together in one block; ! the quota cache is located separately in another block. Both are pointed to ! by the VCB. ! ! - ! *************************************************************************** ! WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! * ! *************************************************************************** ! If you add/remove fields *before* SER_QFL then be sure to realign SER_QFL* ! to be QUADWORD aligned. The danger area is between *##### * ! * ! Also, *DO NOT* insert any fields between SER_QFL and SER_QBL * ! * ! *************************************************************************** ! WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! WARNING! * ! *************************************************************************** literal VCA$M_FIDC_VALID = %X'1'; literal VCA$M_EXTC_VALID = %X'2'; literal VCA$M_FIDC_FLUSH = %X'4'; literal VCA$M_EXTC_FLUSH = %X'8'; literal VCA$C_QUEUE = 16; ! Offset of queue header literal VCA$K_LENGTH = 24; ! length of block header literal VCA$C_LENGTH = 24; ! length of block header literal VCA$S_VCADEF = 24; ! Old size name - synonym ! literal VCA$S_VCA = 24; ! ! Be careful between here.......... ! ################################################## ! macro VCA$L_FIDCACHE = 0,0,32,1 %; ! pointer to file ID cache macro VCA$L_EXTCACHE = 4,0,32,1 %; ! pointer to extent cache macro VCA$W_SIZE = 8,0,16,0 %; ! block size macro VCA$B_TYPE = 10,0,8,0 %; ! block type code macro VCA$B_FLAGS = 11,0,8,1 %; ! cache flags macro VCA$V_FIDC_VALID = 11,0,1,0 %; ! FID cache valid macro VCA$V_EXTC_VALID = 11,1,1,0 %; ! Extent cache valid macro VCA$V_FIDC_FLUSH = 11,2,1,0 %; ! FID cache to be flushed macro VCA$V_EXTC_FLUSH = 11,3,1,0 %; ! Extent cache to be flushed macro VCA$L_CACHE_SPACE_USED = 12,0,32,1 %; ! Amount of space consumed/released macro VCA$L_SER_QFL = 16,0,32,1 %; ! Extent/FID cache macro VCA$L_SER_QBL = 20,0,32,1 %; ! serialization queue header ! ! .........and here ! ################################################## ! ! The file ID cache consists of the cache header, followed by a longword ! vector of file numbers, densely packed. ! literal VCA$S_VCADEF1 = 52; ! Old size name - synonym literal VCA$S_VCA1 = 52; macro VCA$L_FIDSIZE = 0,0,32,0 %; ! number of entries allocated macro VCA$L_FIDCOUNT = 4,0,32,0 %; ! number of entries present macro VCA$L_FIDCLKID = 8,0,32,0 %; ! FID cache lock id. macro VCA$B_FIDCACB = 12,0,0,0 %; literal VCA$S_FIDCACB = 36; ! FID cache blocking ACB macro VCA$L_FIDLIST = 48,0,32,1 %; ! first entry in list ! ! The extent cache consists of the cache header, followed by a quadword ! vector of extents, densely packed. Each quadword contains block count ! and starting LBN. ! literal VCA$S_VCADEF2 = 64; ! Old size name - synonym literal VCA$S_VCA2 = 64; macro VCA$L_EXTSIZE = 0,0,32,0 %; ! number of entries allocated macro VCA$L_EXTCOUNT = 4,0,32,0 %; ! number of entries present macro VCA$L_EXTTOTAL = 8,0,32,0 %; ! total number of blocks contained in cache macro VCA$L_EXTLIMIT = 12,0,32,0 %; ! limit of volume to be cached, in percent/10 macro VCA$L_EXTCLKID = 16,0,32,0 %; ! EXT cache lock id. macro VCA$B_EXTCACB = 20,0,0,0 %; literal VCA$S_EXTCACB = 36; ! Extent cache blocking ACB. macro VCA$Q_EXTLIST = 56,0,0,0 %; literal VCA$S_EXTLIST = 8; ! first entry in list literal VCA$S_VCADEF3 = 8; ! Old size name - synonym literal VCA$S_VCA3 = 8; macro VCA$L_EXTBLOCKS = 0,0,32,0 %; ! number of blocks macro VCA$L_EXTLBN = 4,0,32,0 %; ! starting LBN ! ! The quota cache consists of the cache header, followed by the cache ! entries. Each cache entry is a block as defined below. ! literal VCA$M_CACHEVALID = %X'1'; literal VCA$M_CACHEFLUSH = %X'2'; literal VCA$S_VCADEF4 = 92; ! Old size name - synonym literal VCA$S_VCA4 = 92; macro VCA$L_QUOSIZE = 0,0,32,0 %; ! number of entries allocated macro VCA$L_QUOCLKID = 4,0,32,0 %; ! whole cache lock ID macro VCA$B_QUOCFLAGS = 11,0,8,1 %; ! cache flags macro VCA$V_CACHEVALID = 11,0,1,0 %; ! cache is valid macro VCA$V_CACHEFLUSH = 11,1,1,0 %; ! cache is to be flushed macro VCA$L_QUOLRU = 12,0,32,0 %; ! current LRU counter macro VCA$B_QUOACB = 16,0,0,0 %; literal VCA$S_QUOACB = 36; ! ACB to deliver blocking AST macro VCA$B_QUOFLUSHACB = 52,0,0,0 %; literal VCA$S_QUOFLUSHACB = 36; ! ACB to deliver cache flush AST macro VCA$L_QUOLIST = 88,0,32,1 %; ! start of entries literal VCA$M_QUOVALID = %X'1'; literal VCA$M_QUODIRTY = %X'2'; literal VCA$K_QUOLENGTH = 28; ! length of quota cache entry literal VCA$C_QUOLENGTH = 28; ! length of quota cache entry literal VCA$S_VCADEF5 = 28; ! Old size name - synonym literal VCA$S_VCA5 = 28; macro VCA$R_QUOLOCK = 0,0,0,0 %; literal VCA$S_QUOLOCK = 24; ! lock status block macro VCA$W_QUOSTATUS = 0,0,16,0 %; ! $ENQ status macro VCA$W_QUOINDEX = 0,0,16,0 %; ! index in cache of this entry macro VCA$W_QUOLRUX = 2,0,16,0 %; ! LRU index for entry macro VCA$L_QUOLKID = 4,0,32,0 %; ! lock ID of cache entry macro VCA$L_QUORECNUM = 8,0,24,0 %; literal VCA$S_QUORECNUM = 3; ! record number macro VCA$B_QUOFLAGS = 11,0,8,0 %; ! flags byte macro VCA$V_QUOVALID = 11,0,1,0 %; ! valid entry is present macro VCA$V_QUODIRTY = 11,1,1,0 %; ! dirty flag macro VCA$L_USAGE = 12,0,32,0 %; ! current usage macro VCA$L_PERMQUOTA = 16,0,32,0 %; ! permanent quota macro VCA$L_OVERDRAFT = 20,0,32,0 %; ! overdraft limit macro VCA$L_QUOUIC = 24,0,32,0 %; ! UIC !*** MODULE $VCBDEF *** literal VCB$K_MRKLEN = 11; ! Old size name for Mark length literal VCB$C_MRKLEN = 11; ! Old size name for Mark length literal VCB$M_WRITE_IF = %X'1'; literal VCB$M_WRITE_SM = %X'2'; literal VCB$M_HOMBLKBAD = %X'4'; literal VCB$M_IDXHDRBAD = %X'8'; literal VCB$M_NOALLOC = %X'10'; literal VCB$M_EXTFID = %X'20'; literal VCB$M_GROUP = %X'40'; literal VCB$M_SYSTEM = %X'80'; literal VCB$M_HIGH_SIERRA = %X'1'; literal VCB$M_NOSWITCH = %X'2'; literal VCB$M_DSI = %X'4'; literal VCB$M_XAR = %X'8'; literal VCB$M_UNUSED_1 = %X'10'; literal VCB$M_UNUSED_2 = %X'20'; literal VCB$M_PARTFILE = %X'1'; literal VCB$M_LOGICEOVS = %X'2'; literal VCB$M_WAIMOUVOL = %X'4'; literal VCB$M_WAIREWIND = %X'8'; literal VCB$M_WAIUSRLBL = %X'10'; literal VCB$M_CANCELIO = %X'20'; literal VCB$M_MUSTCLOSE = %X'40'; literal VCB$M_NOWRITE = %X'80'; literal VCB$M_SHADMAST = %X'1'; literal VCB$M_FAILED = %X'2'; literal VCB$M_REBLDNG = %X'8'; literal VCB$M_BLKASTREC = %X'10'; literal VCB$M_MVBEGUN = %X'20'; literal VCB$M_ADDING = %X'40'; literal VCB$M_PACKACKED = %X'80'; literal VCB$M_SUBSYSTEM = %X'1'; literal VCB$M_STRUC_ODS5 = %X'2'; literal VCB$M_ACCESSTIMES = %X'4'; literal VCB$M_HARDLINKS = %X'8'; literal VCB$M_SPECIAL_FILES = %X'10'; literal VCB$K_COMLEN = 232; ! LENGTH OF COMMON AREA literal VCB$C_COMLEN = 232; ! LENGTH OF COMMON AREA literal VCB$S_VCBDEF_COMMON = 232; ! OLD LENGTH NAME FOR COMPATABILITY literal VCB$M_FILE_ATTRIBUTES = %X'F'; literal VCB$M_FILE_CONTENTS = %X'F0'; literal VCB$C_DEFAULT = 0; ! use default caching policy literal VCB$C_WRITETHROUGH = 1; ! use writethrough caching literal VCB$C_WRITEBEHIND = 2; ! use writebehind caching literal VCB$M_FLUSH_ON_CLOSE = %X'F00'; literal VCB$C_FLUSH = 1; ! flush file from cache when file closed literal VCB$C_NOFLUSH = 2; ! retain file in cache when file closed literal VCB$M_CACHING_OPTIONS_MBZ = %X'FFFFF000'; literal VCB$K_LENGTH = 424; ! LENGTH OF STANDARD VCB literal VCB$C_LENGTH = 424; ! LENGTH OF STANDARD VCB literal VCB$S_VCBDEF_DISKS = 424; ! Old length name for compatability literal VCB$K_F64_LEN = 418; ! length of F64-extended VCB literal VCB$C_F64_LEN = 418; ! length of F64-extended VCB literal VCB$S_VCBDEF_F64 = 418; ! old length name for compatability literal VCB$K_SHAD_LEN = 264; ! Shadow set member VCB length literal VCB$S_VCBDEF_SHADOW = 264; ! Old length name for compatability literal VCB$S_VCBDEF_CDROM = 288; ! Old size name, synonym for VCB$S_VCB_CDROM literal VCB$S_VCBDEF2 = 269; ! Old size name, synonym for VCB$S_VCB_MTAACP literal VCB$S_VCBDEF3 = 32; ! OLD LENGTH NAME FOR COMPATABILITY literal VCB$S_VCB = 424; macro VCB$L_FCBFL = 0,0,32,1 %; ! FCB listhead forward link macro VCB$L_BLOCKFL = 0,0,32,1 %; ! or - Blocked request listhead forward link macro VCB$L_MEMQFL = 0,0,32,1 %; ! or - Shadow set members queue forward link macro VCB$L_FCBBL = 4,0,32,1 %; ! FCB listhead backward link macro VCB$L_BLOCKBL = 4,0,32,1 %; ! or - Blocked request listhead backward link macro VCB$L_MEMQBL = 4,0,32,1 %; ! or - Shadow set members queue backward link macro VCB$W_SIZE = 8,0,16,0 %; ! Size of VCB in bytes macro VCB$B_TYPE = 10,0,8,0 %; ! structure type of VCB macro VCB$R_VCB_UNION = 11,0,0,0 %; literal VCB$S_VCB_UNION = 407; ! ! Common fields for file and volume VCBs. Note not all fields in the ! common area are valid for all types. ! macro VCB$B_STATUS = 11,0,8,0 %; ! Volume status: macro VCB$V_WRITE_IF = 11,0,1,0 %; ! Index file is write accessed macro VCB$V_WRITE_SM = 11,1,1,0 %; ! Storage map is write accessed macro VCB$V_HOMBLKBAD = 11,2,1,0 %; ! Primary home block is bad macro VCB$V_IDXHDRBAD = 11,3,1,0 %; ! Primary index file header is bad macro VCB$V_NOALLOC = 11,4,1,0 %; ! Allocation/deallocation inhibited (bad bitmaps) macro VCB$V_EXTFID = 11,5,1,0 %; ! Volume has 24 bit file numbers macro VCB$V_GROUP = 11,6,1,0 %; ! Volume is mounted /group macro VCB$V_SYSTEM = 11,7,1,0 %; ! Volume is mounted /system macro VCB$V_HIGH_SIERRA = 11,0,1,0 %; ! Volume is High Sierra macro VCB$V_NOSWITCH = 11,1,1,0 %; ! Disable Automatic Volume Switching macro VCB$V_DSI = 11,2,1,0 %; ! Enable protection based on DSI macro VCB$V_XAR = 11,3,1,0 %; ! Enable protection based on XAR macro VCB$V_PARTFILE = 11,0,1,0 %; ! Partial file exists on tape macro VCB$V_LOGICEOVS = 11,1,1,0 %; ! Positioned at logical end of volume set macro VCB$V_WAIMOUVOL = 11,2,1,0 %; ! Wait for volume mount macro VCB$V_WAIREWIND = 11,3,1,0 %; ! Wait for rewind completion macro VCB$V_WAIUSRLBL = 11,4,1,0 %; ! Wait for user label macro VCB$V_CANCELIO = 11,5,1,0 %; ! Cancel I/O macro VCB$V_MUSTCLOSE = 11,6,1,0 %; ! Must close file macro VCB$V_NOWRITE = 11,7,1,0 %; ! Don't write trailers macro VCB$V_SHADMAST = 11,0,1,0 %; ! This VCB is for shadow set master macro VCB$V_FAILED = 11,1,1,0 %; ! Member failed out of shadow set macro VCB$V_REBLDNG = 11,3,1,0 %; ! Mount verfication rebuilding shadow set macro VCB$V_BLKASTREC = 11,4,1,0 %; ! Shadowing lock blocking AST received macro VCB$V_MVBEGUN = 11,5,1,0 %; ! Mount verification initiated macro VCB$V_ADDING = 11,6,1,0 %; ! Adding member to shadow set macro VCB$V_PACKACKED = 11,7,1,0 %; ! Member PACKACKed during rebuild attempt macro VCB$L_TRANS = 12,0,32,0 %; ! VOLUME TRANSACTION COUNT macro VCB$L_RVT = 16,0,32,1 %; ! ADDRESS OF UCB OR RELATIVE VOLUME TABLE macro VCB$L_AQB = 20,0,32,1 %; ! ADDRESS OF AQB macro VCB$L_STATUS2 = 24,0,32,0 %; macro VCB$B_STATUS2 = 24,0,8,0 %; macro VCB$V_WRITETHRU = 24,0,1,0 %; ! VOLUME IS TO BE WRITE-THROUGH CACHED macro VCB$V_NOCACHE = 24,1,1,0 %; ! ALL CACHEING IS DISABLED ON VOLUME macro VCB$V_MOUNTVER = 24,2,1,0 %; ! VOLUME CAN UNDERGO MOUNT VERIFICATION macro VCB$V_ERASE = 24,3,1,0 %; ! ERASE DATA WHEN BLOCKS REMOVED FROM FILE macro VCB$V_NOHIGHWATER = 24,4,1,0 %; ! TURN OFF HIGH-WATER MARKING (D = ON) macro VCB$V_NOSHARE = 24,5,1,0 %; ! non-shared mount macro VCB$V_CLUSLOCK = 24,6,1,0 %; ! CLUSTER WIDE LOCKING NECESSARY macro VCB$V_SUBSET0 = 24,7,1,0 %; ! ODS-2 SUBSET 0 VOLUME macro VCB$B_CD_STATUS2 = 24,0,8,0 %; ! CD STATUS2 usage - same as disk macro VCB$L_STATUS3 = 28,0,32,0 %; macro VCB$V_SUBSYSTEM = 28,0,1,0 %; ! PROTECTED SUBSYSTEMS ENABLED macro VCB$V_STRUC_ODS5 = 28,1,1,0 %; ! ODS-5 STRUCTURES SUPPORTED macro VCB$V_ACCESSTIMES = 28,2,1,0 %; ! record access times macro VCB$V_HARDLINKS = 28,3,1,0 %; ! support POSIX hardlinks, rather than alias macro VCB$V_SPECIAL_FILES = 28,4,1,0 %; ! support special files (symlinks, etc.) macro VCB$V_NOXFCCACHE = 28,5,1,0 %; ! XFC VOLUME CACHING STATUS BIT macro VCB$V_XFC_DEPOSING = 28,6,1,0 %; ! XFC volume depose in progress bit macro VCB$T_VOLNAME = 32,0,0,0 %; literal VCB$S_VOLNAME = 12; ! VOLUME LABEL BLANK FILLED macro VCB$T_VOLIDENTIFIER = 32,0,0,0 %; literal VCB$S_VOLIDENTIFIER = 64; ! Extended volume identifier macro VCB$Q_MOUNTTIME = 96,0,0,0 %; literal VCB$S_MOUNTTIME = 8; ! VOLUME MOUNT TIME macro VCB$L_MCOUNT = 104,0,32,0 %; ! MOUNT COUNT macro VCB$L_CD_MCOUNT = 104,0,32,0 %; ! Alternate name used by CDrom file system macro VCB$L_RVN = 108,0,32,0 %; ! RELATIVE VOLUME NUMBER macro VCB$L_ORB = 112,0,32,1 %; ! Pointer to the volume's ORB macro VCB$L_READS = 116,0,32,0 %; ! Total count of read I/Os macro VCB$L_WRITES = 120,0,32,0 %; ! Total count of write I/Os macro VCB$L_SPLIT_IO = 124,0,32,0 %; ! Total count of split I/Os macro VCB$L_ASSIST_IO = 128,0,32,0 %; ! Total count of file system assisted I/Os macro VCB$L_SERIALNUM = 132,0,32,0 %; ! VOLUME SERIAL NUMBER (DISKS ONLY) macro VCB$L_VOLLKID = 136,0,32,0 %; ! VOLUME LOCK ID macro VCB$L_CLUSTER = 140,0,32,0 %; ! VOLUME CLUSTER SIZE macro VCB$L_RECORDSZ = 144,0,32,0 %; ! NUMBER OF BYTES IN A RECORD ! and align to quadword ! ! Files-11 A & B Volume Control Block Fields ! (ODS-I & ODS-II ) ! Note we are still in the common area of the VCB (also note that some ! of the preceding fields are also Files-11 related). Problem is the ! usage of fields is not clear-cut; some fields are also applicable to ! other file systems (present and future). Also, the CDrom ACP overlays ! a number Files-11 fields with its own equivalent, but differently named, ! fields. Rather than leave these fields in the file system specific VCB ! and trust to luck with the overlays, we have chosen to turn the overlays ! into proper unions. ! ! Note LBN and volume size related fields have been promoted to quadwords. ! ODS-II/V will never support volumes larger than 1TB; the promotions are ! in anticipation of a new file system that will use the VCB in common. macro VCB$Q_RETAINMIN = 168,0,0,0 %; literal VCB$S_RETAINMIN = 8; ! MINIMUM FILE RETENTION PERIOD (DISK) macro VCB$Q_EXP_DATE = 168,0,0,0 %; literal VCB$S_EXP_DATE = 8; ! DEFAULT FILE EXPIRATION DATE (TAPE) macro VCB$Q_RETAINMAX = 176,0,0,0 %; literal VCB$S_RETAINMAX = 8; ! MAXIMUM FILE RETENTION PERIOD ! The following fields are overlaid with equivalent but differently named fields in the CDrom VCB. macro VCB$L_FREE = 184,0,32,0 %; macro VCB$Q_FREE = 184,0,0,0 %; literal VCB$S_FREE = 8; macro VCB$L_CD_FREE = 184,0,32,0 %; macro VCB$Q_CD_FREE = 184,0,0,0 %; literal VCB$S_CD_FREE = 8; macro VCB$L_MAXFILES = 192,0,32,0 %; ! MAXIMUM NUMBER OF FILES ALLOWED ON VOLUME macro VCB$L_CD_MAXFILES = 192,0,32,0 %; macro VCB$L_WINDOW = 196,0,32,0 %; ! VOLUME DEFAULT WINDOW SIZE macro VCB$L_CD_WINDOW = 196,0,32,0 %; macro VCB$L_LRU_LIM = 200,0,32,0 %; ! VOLUME DIRECTORY LRU SIZE LIMIT macro VCB$L_CD_LRU_LIM = 200,0,32,0 %; macro VCB$L_BLOCKFACT = 204,0,32,0 %; ! VOLUME BLOCKING FACTOR macro VCB$L_LBBLOCKS = 204,0,32,0 %; ! Number of 512-byte blocks per logical block macro VCB$L_HOMELBN = 208,0,32,0 %; macro VCB$Q_HOMELBN = 208,0,0,0 %; literal VCB$S_HOMELBN = 8; macro VCB$L_VOLDESC = 208,0,32,0 %; ! LBN of CD volume descriptor macro VCB$Q_VOLDESC = 208,0,0,0 %; literal VCB$S_VOLDESC = 8; ! end of overlaid CDrom fields macro VCB$L_VOLSIZE = 216,0,32,0 %; macro VCB$Q_VOLSIZE = 216,0,0,0 %; literal VCB$S_VOLSIZE = 8; macro VCB$L_EXPSIZE = 224,0,32,0 %; macro VCB$Q_EXPSIZE = 224,0,0,0 %; literal VCB$S_EXPSIZE = 8; macro VCB$R_VCB_EXTENSIONS = 232,0,0,0 %; literal VCB$S_VCB_EXTENSIONS = 186; ! NESTED UNION CONTAINING MAJOR EXTENSIONS macro VCB$R_VCB_DISKS = 232,0,0,0 %; literal VCB$S_VCB_DISKS = 186; macro VCB$L_HOME2LBN = 232,0,32,0 %; macro VCB$Q_HOME2LBN = 232,0,0,0 %; literal VCB$S_HOME2LBN = 8; macro VCB$L_IXHDR2LBN = 240,0,32,0 %; macro VCB$Q_IXHDR2LBN = 240,0,0,0 %; literal VCB$S_IXHDR2LBN = 8; macro VCB$L_IBMAPLBN = 248,0,32,0 %; macro VCB$Q_IBMAPLBN = 248,0,0,0 %; literal VCB$S_IBMAPLBN = 8; macro VCB$L_SBMAPLBN = 256,0,32,0 %; macro VCB$Q_SBMAPLBN = 256,0,0,0 %; literal VCB$S_SBMAPLBN = 8; macro VCB$L_IBMAPSIZE = 264,0,32,0 %; ! SIZE OF INDEX FILE BITMAP macro VCB$L_IBMAPVBN = 268,0,32,0 %; ! CURRENT VBN IN INDEX FILE BIT MAP macro VCB$L_SBMAPSIZE = 272,0,32,0 %; ! SIZE OF STORAGE BITMAP macro VCB$L_SBMAPVBN = 276,0,32,0 %; ! CURRENT VBN IN STORAGE MAP macro VCB$L_EXTEND = 280,0,32,0 %; ! VOLUME DEFAULT FILE EXTENSION LENGTH macro VCB$L_FILEPROT = 284,0,32,0 %; ! VOLUME DEFAULT FILE PROTECTION macro VCB$L_EOFDELTA = 288,0,32,0 %; ! INDEX FILE EOF UPDATE COUNT macro VCB$L_RESFILES = 292,0,32,0 %; ! NUMBER OF RESERVED FILES ON VOLUME macro VCB$L_QUOTAFCB = 296,0,32,1 %; ! ADDRESS OF FCB OF DISK QUOTA FILE macro VCB$L_CACHE = 300,0,32,1 %; ! ADDRESS OF VOLUME CACHE BLOCK macro VCB$L_QUOCACHE = 304,0,32,1 %; ! ADDRESS OF VOLUME QUOTA CACHE macro VCB$L_QUOSIZE = 308,0,32,0 %; ! LENGTH OF QUOTA CACHE TO ALLOCATE macro VCB$L_SPL_CNT = 312,0,32,0 %; ! NUMBER OF DEVICES SPOOLED TO VOLUME macro VCB$L_PENDERR = 316,0,32,0 %; ! COUNT OF PENDING WRITE ERRORS macro VCB$T_VOLCKNAM = 320,0,0,0 %; literal VCB$S_VOLCKNAM = 12; ! NAME FOR VOLUME LOCKS macro VCB$L_MEMHDFL = 332,0,32,1 %; ! SHADOW SET MEMBERS QUEUE HEADER FL macro VCB$L_MEMHDBL = 336,0,32,1 %; ! SHADOW SET MEMBERS QUEUE HEADER BL macro VCB$B_SHAD_STS = 343,0,8,0 %; ! STATUS BYTE RELATIVE TO MEMHDFL macro VCB$L_BLOCKID = 344,0,32,0 %; ! VOLUME BLOCKING LOCK. macro VCB$L_ACTIVITY = 348,0,32,0 %; ! ACTIVITY COUNT/FLAG macro VCB$B_ACB = 352,0,0,0 %; literal VCB$S_ACB = 36; ! ACB FOR BLOCKING AST. macro VCB$L_CACHING_OPTIONS = 388,0,32,0 %; macro VCB$V_FILE_ATTRIBUTES = 388,0,4,0 %; literal VCB$S_FILE_ATTRIBUTES = 4; ! file attributes caching field macro VCB$V_FILE_CONTENTS = 388,4,4,0 %; literal VCB$S_FILE_CONTENTS = 4; ! file contents caching field macro VCB$V_FLUSH_ON_CLOSE = 388,8,4,0 %; literal VCB$S_FLUSH_ON_CLOSE = 4; ! flush file on close field macro VCB$V_CACHING_OPTIONS_MBZ = 388,12,20,0 %; literal VCB$S_CACHING_OPTIONS_MBZ = 20; ! must be zero macro VCB$Q_ACCESS_DELTA = 392,0,0,0 %; literal VCB$S_ACCESS_DELTA = 8; ! access time qranularity macro VCB$B_DVI_VOLCHAR = 400,0,0,1 %; literal VCB$S_DVI_VOLCHAR = 16; ! DVIVOLDEF structure for disk VCB macro VCB$W_BACKREV = 416,0,16,0 %; ! Copy of SCB$W_BACKREV macro VCB$R_VCB_SHADOW = 232,0,0,0 %; literal VCB$S_VCB_SHADOW = 32; ! ! SHADOW SET MEMBER VOLUME CONTROL BLOCK FIELDS ! macro VCB$L_MEM_UCB = 232,0,32,1 %; ! Shadow set member UCB address macro VCB$L_MAST_UCB = 236,0,32,1 %; ! Shadow set master UCB address macro VCB$L_MAST_VCB = 240,0,32,1 %; ! Shadow set master VCB address macro VCB$W_COPY_TYPE = 244,0,16,0 %; ! Member's MSCP copy type macro VCB$W_CPYSEQNUM = 246,0,16,0 %; ! IO$_COPYSHAD sequence number macro VCB$Q_WORK = 248,0,0,0 %; literal VCB$S_WORK = 8; ! Per-member workspace macro VCB$Q_SHDM_RESV = 256,0,0,0 %; literal VCB$S_SHDM_RESV = 8; ! Reserved for future enhancements macro VCB$R_VCB_CDROM = 232,0,0,0 %; literal VCB$S_VCB_CDROM = 56; ! ! Files-11 C & D Volume Control Block Fields ! (ISO 9660 and High Sierra) ! macro VCB$L_ORPHANED_VCB = 232,0,32,1 %; ! Singly linked list of Orphaned VCB's macro VCB$L_PTVECTOR = 236,0,32,1 %; ! Address Path Table Vector macro VCB$L_LBNCACHE = 240,0,32,1 %; ! Address of LBN cache listhead macro VCB$L_PTINDEX = 244,0,32,0 %; ! LBN of Path Table Index macro VCB$L_LBSIZE = 248,0,32,0 %; ! ISO 9660 Logical Block Size macro VCB$L_MXDIRNM = 252,0,32,0 %; ! Maximum directory record number macro VCB$L_MINREAD = 256,0,32,0 %; ! Minimum number of LBNs to read at once macro VCB$L_RDBYTES = 260,0,32,0 %; ! Number of bytes to read from disk at once macro VCB$L_LASTGRP = 264,0,32,0 %; ! Highest volume number of last volume group macro VCB$L_PTRVN = 268,0,32,0 %; ! RVN of volume containing current Path Table macro VCB$L_FAT_RFM = 272,0,32,0 %; ! Override FAT Record Format macro VCB$L_FAT_RAT = 276,0,32,0 %; ! Override FAT Record Attributes macro VCB$L_FAT_MRS = 280,0,32,0 %; ! Override FAT Maximum Record Size macro VCB$L_SECTORS = 284,0,32,0 %; ! Number of sectors on volume ! ! Compare with VCBDEF_DISK above, before overlaying any other CDROM fields ! macro VCB$R_VCB_MTAACP = 232,0,0,0 %; literal VCB$S_VCB_MTAACP = 37; ! ! MTAACP VOLUME CONTROL BLOCK FIELDS ! macro VCB$L_CUR_FID = 232,0,32,0 %; ! CURRENT FILE IDENTIFICATION macro VCB$W_CUR_NUM = 232,0,16,0 %; ! CURRENT FILE SECTION NUMBER macro VCB$W_CUR_SEQ = 234,0,16,0 %; ! CURRENT FILE SEQUENCE NUMBER macro VCB$L_START_FID = 236,0,32,0 %; ! FILE IDENTIFICATION AT START OF SEARCH macro VCB$W_START_NUM = 236,0,16,0 %; ! FILE SECTION NUMBER AT START OF SEARCH macro VCB$W_START_SEQ = 238,0,16,0 %; ! FILE SEQUENCE NUMBER AT START OF SEARCH macro VCB$W_MODE = 240,0,16,0 %; ! MODE OF OPERATION macro VCB$V_OVREXP = 240,0,1,0 %; ! OVERRIDE EXPIRATION macro VCB$V_OVRACC = 240,1,1,0 %; ! OVERRIDE ACCESS macro VCB$V_OVRLBL = 240,2,1,0 %; ! OVERRIDE LABELS macro VCB$V_OVRSETID = 240,3,1,0 %; ! OVERRIDE SET IDENTIFIER macro VCB$V_INTCHG = 240,4,1,0 %; ! INTERCHANGE TAPE macro VCB$V_EBCDIC = 240,5,1,0 %; ! EBCDIC CODE SET macro VCB$V_NOVOL2 = 240,6,1,0 %; ! DO NOT WRITE A VOL2 LABEL macro VCB$V_NOHDR3 = 240,7,1,0 %; ! DO NOT WRITE HDR3 LABELS macro VCB$V_STARFILE = 240,8,1,0 %; ! CURRENT FILE IS A STARLET PRODUCED FILE macro VCB$V_ENUSEREOT = 240,9,1,0 %; ! SET WHEN USER HANDLING OF EOT IS ENABLED macro VCB$V_BLANK = 240,10,1,0 %; ! SET FOR AVL WHEN NO READ SHOULD HAPPEN FIRST macro VCB$V_INIT = 240,11,1,0 %; ! SET FOR AVL WHEN NEXT VOL MOUNTED SHOULD BE INITED macro VCB$V_NOAUTO = 240,12,1,0 %; ! MTAACP NOT RUNNING IN AVL AND AVR MODE macro VCB$V_OVRVOLO = 240,13,1,0 %; ! OVERRIDE THEVOL1 OWNER IDENT FIELD macro VCB$V_FIL_ACCESS = 240,14,1,0 %; ! SET IF ACCESS ROUTINE ALLOWS CHECK OF VMS PROTECTION ON FILE macro VCB$B_TM = 242,0,8,0 %; ! NUMBER OF TM'S INTO FILE macro VCB$B_CUR_RVN = 243,0,8,0 %; ! CURRENT RELATIVE VOLUME macro VCB$L_ST_RECORD = 244,0,32,0 %; ! NUMBER OF RECORDS UP TO AND INCLUDING LAST TAPE MARK macro VCB$L_MVL = 248,0,32,1 %; ! ADDRESS OF MAGNETIC TAPE VOLUME LIST macro VCB$L_WCB = 252,0,32,1 %; ! ADDRESS OF WINDOW FOR THIS VOLUME macro VCB$L_VPFL = 256,0,32,1 %; ! VIRTUAL PAGE LIST HEAD macro VCB$L_VPBL = 260,0,32,1 %; ! VIRTUAL PAGE LIST TAIL macro VCB$L_USRLBLAST = 264,0,32,1 %; ! ADDRESS OF USER LABEL AST CONTROL BLOCK macro VCB$B_LBLCNT = 268,0,8,0 %; ! Count of HDRn labels read on file open ! End the Union of extensions ! End the member (which is a union with VCB_JACP) macro VCB$R_VCB_JACP = 11,0,0,0 %; literal VCB$S_VCB_JACP = 21; ! ! JOURNAL ACP VOLUME CONTROL BLOCK FIELDS ! macro VCB$B_QNAMECNT = 11,0,8,0 %; ! BYTE COUNT OF QUEUE NAME macro VCB$T_QNAME = 12,0,0,0 %; literal VCB$S_QNAME = 20; ! ASCII NAME OF QUEUE FOR THIS DEVICE !*** MODULE $VCIBDEF *** ! + ! VCIB - VAX Communication Interface Block ! ! The VCIB is the data structure used to define an instance of a VCI port ! between two VCMs. A single VCIB is used between only two layers. Those ! two layers may have many VCIBs between them; each one representing a ! different VCI port. Only the common fields within the VCIB are defined ! here. All layer-specific fields are defined elsewhere. Some constants ! used within the VCIB are defined here also. And the VCM IDs are also ! defined here. ! - ! VCI Registry function codes. literal VCIB$K_FC_REGISTER = 0; ! Register a VCM literal VCIB$K_FC_UNREGISTER = 1; ! Unregister a VCM literal VCIB$K_FC_CREATE_PORT = 2; ! Create a port to a lower VCM literal VCIB$K_FC_DELETE_PORT = 3; ! Delete a port to a lower VCM ! Registered users of the VCI. literal VCI$K_ID_MODEM = 257; ! Modem Connect literal VCI$K_ID_NWM = 2048; ! Network Management literal VCI$K_ID_CONF = 2049; ! Conformance Test Tool literal VCI$K_ID_SCL = 1280; ! Session Control literal VCI$K_ID_SCLSRV = 1281; ! Session Control Session Services literal VCI$K_ID_SCLMIN = 1282; ! Session Control Minimum Services literal VCI$K_ID_NSPTP = 1024; ! Transport - NSP literal VCI$K_ID_OSITP = 1025; ! Transport - OSI literal VCI$K_ID_LCLTP = 1026; ! Transport - Local literal VCI$K_ID_SCATP = 1027; ! Transport - SCA literal VCI$K_ID_LAT = 1028; ! Transport - LAT literal VCI$K_ID_LAST = 1029; ! Transport - LAST literal VCI$K_ID_LAVC = 1030; ! Transport - LAVC literal VCI$K_ID_MOP = 1031; ! Maintenance Operations literal VCI$K_ID_TCPIP = 1032; ! Transport - TCPIP literal VCI$K_ID_IP = 1032; ! Transport - IP literal VCI$K_ID_AMDS = 1033; ! Transport - AMDS literal VCI$K_ID_CUSTP = 1177; ! Transport - Customer literal VCI$K_ID_NRL = 768; ! Network Routing literal VCI$K_ID_ALIAS = 769; ! Alias (Routing portion) literal VCI$K_ID_CUSRL = 921; ! Routing - Customer literal VCI$K_ID_LAN = 513; ! Data Link - CSMACD & FDDI literal VCI$K_ID_DDCMP = 514; ! Data Link - DDCMP Synchronous literal VCI$K_ID_HDLC = 515; ! Data Link - HDLC Synchronous literal VCI$K_ID_ASY = 516; ! Data Link - Asynchronous literal VCI$K_ID_X25 = 517; ! Data Link - X.25 literal VCI$K_ID_ADM = 518; ! Data Link - ALTSTART DDCMP literal VCI$K_ID_ACM = 519; ! Data Link - ALTSTART CSMACD literal VCI$K_ID_LAPB = 520; ! Data Link - LAPB literal VCI$K_ID_LLC2 = 521; ! Data Link - LLC2 literal VCI$K_ID_NETBEUI = 528; ! Data Link - NETBEUI literal VCI$K_ID_IPX = 529; ! Data Link - IPX literal VCI$K_ID_DSP = 530; ! Data Link - Digital stream protocol literal VCI$K_ID_PP = 531; ! Data Link - PP literal VCI$K_ID_ASYN = 532; ! Data Link - ASYN literal VCI$K_ID_CUSDL = 665; ! Data Link - Customer literal VCI$K_ID_TST1 = 2304; ! Test VCM - 1st literal VCI$K_ID_TST2 = 2305; ! Test VCM - 2nd literal VCI$K_ID_TST3 = 2306; ! Test VCM - 3rd literal VCI$K_ID_TST4 = 2307; ! Test VCM - 4th literal VCI$K_ID_TST5 = 2308; ! Test VCM - 5th literal VCI$K_ID_TST6 = 2309; ! Test VCM - 6th literal VCI$K_ID_TST7 = 2310; ! Test VCM - 7th literal VCI$K_ID_TST8 = 2311; ! Test VCM - 8th literal VCI$K_ID_LANMON = 2312; ! Test VCM - Lan monitor literal VCI$K_ID_LANTEST = 2313; ! Test VCM - Lan test literal VCI$K_ID_DECNET_1 = 2560; ! DECnet reserved VCM 0..FF literal VCI$K_ID_DECNET_FF = 2815; ! DECnet reserved VCM 0..FF literal VCI$K_NUM_ID = 41; ! Number of valid VCMs ! VCIB data structure ! ! The common fields within the VCIB are defined now. literal VCIB$K_FIXED_LENGTH = 60; ! Length of fixed portion of VCIB literal VCIB$S_VCIBDEF = 60; macro VCIB$L_FLINK = 0,0,32,1 %; ! Forward Queue link macro VCIB$L_BLINK = 4,0,32,1 %; ! Backward Queue link macro VCIB$W_SIZE = 8,0,16,0 %; ! Size of structure macro VCIB$B_TYPE = 10,0,8,0 %; ! Type of structure - DYN$C_NET macro VCIB$B_SUB_TYPE = 11,0,8,0 %; ! Subtype of structure - DYN$C_VCIB macro VCIB$L_VCI_ID = 12,0,32,0 %; ! Field containing the VCI ID of the ! VCM (used by the lower VCM for ! validation of user) macro VCIB$W_VERSION_UPPER = 16,0,16,0 %; ! VCI Version of Upper VCM macro VCIB$W_VERSION_LOWER = 18,0,16,0 %; ! VCI Version of Lower VCM macro VCIB$A_PORTMGMT_SYNCH = 20,0,32,1 %; ! Address of Lower VCM's Port ! Management Synchronous service macro VCIB$A_PORTMGMT_INITIATE = 24,0,32,1 %; ! Address of Lower VCM's Port ! Management Initiate service macro VCIB$A_PORTMGMT_COMPLETE = 28,0,32,1 %; ! Address of Upper VCM's Port ! Management Complete service macro VCIB$A_CONTROL_SYNCH = 32,0,32,1 %; ! Address of Lower VCM's Control ! Synchronous service macro VCIB$A_CONTROL_INITIATE = 36,0,32,1 %; ! Address of Lower VCM's Control ! Initiate service macro VCIB$A_CONTROL_COMPLETE = 40,0,32,1 %; ! Address of Upper VCM's Control ! Complete service macro VCIB$A_TRANSMIT_INITIATE = 44,0,32,1 %; ! Address of Lower VCM's Transmit ! Initiate service macro VCIB$A_TRANSMIT_COMPLETE = 48,0,32,1 %; ! Address of Upper VCM's Transmit ! Complete service macro VCIB$A_RECEIVE_COMPLETE = 52,0,32,1 %; ! Address of Upper VCM's Receive ! Complete service macro VCIB$A_REPORT_EVENT = 56,0,32,1 %; ! Address of Upper VCM's Report ! Event service !*** MODULE $VCRPDEF *** ! + ! VCRP - VAX Communication Request Packet ! ! The VCRP is the data structure used to pass requests between VCMs. A ! single VCRP may traverse more than two VCMs. Only the common fields ! within the VCRP are defined here. All layer-specific fields are defined ! elsewhere. The common VCRP function codes are also defined here. ! ! THE FORMAT OF A VCRP DATA REQUEST PACKET SHOULD NOT CHANGE WITHOUT ! CORRESPONDING CHANGES BEING MAY TO THE DCBE. ! - ! Function codes used in the VCRP$L_FUNCTION field. The function codes ! are separated numerically by layer as follows: ! ! 0000-01FF Common function codes from the VCI functional specification ! 0200-02FF DLL Data Link function codes ! 0300-03FF NRL Network Routing function codes ! 0400-04FF TPL Transport function codes ! 0500-05FF SCL Session function codes ! 0600-06FF APP Application function codes literal VCRP$K_FC_ENABLE_PORT = 0; literal VCRP$K_FC_DISABLE_PORT = 1; literal VCRP$K_FC_GET = 2; literal VCRP$K_FC_SET = 3; literal VCRP$K_FC_TRANSMIT = 4; literal VCRP$K_FC_RECEIVE = 5; ! Define the fields used within the STACK area of the VCRP. literal STACK$k_STACK_HEADER = 12; ! Size of Stack Header literal STACK$K_STACK_SIZE = 208; ! Size of Stack in bytes literal STACK$S_VCRPSTACK = 220; macro STACK$L_LASTUSED = 0,0,32,1 %; ! Stack Last Used position pointer macro STACK$L_BTM = 4,0,32,1 %; ! Stack Bottom macro STACK$L_TOP = 8,0,32,1 %; ! Stack Top macro STACK$T_STACK = 12,0,0,0 %; literal STACK$S_STACK = 208; ! Context stack ! Size of entire stack area literal STACK$S_VCRPSTACKDEF = 220; ! VCRP data structure ! ! The common fields within the VCRP are defined now. The VCRP is created ! such that it can be used as an ACB, a DCBE, or a VCRP. So the fields at ! the beginning of the VCRP mimic the fields in the ACB and the DCBE. literal VCRP$M_ACB_FLAGS_VALID = %X'4'; literal VCRP$M_PKAST = %X'10'; literal VCRP$M_NODELETE = %X'20'; literal VCRP$M_QUOTA = %X'40'; literal VCRP$M_KAST = %X'80'; literal VCRP$K_ACB_LENGTH = 64; ! Length of VCRP ACB Block literal VCRP$M_CMN_LOCKED = %X'1'; literal VCRP$M_CMN_RETBUF = %X'2'; literal VCRP$M_CMN_CACHE = %X'4'; literal VCRP$M_CMN_MGMT = %X'8'; literal VCRP$K_DATA_INFORMATION_OFFSET = 196; literal VCRP$K_DATA_INFORMATION_LENGTH = 7; literal VCRP$K_MGMT_INFORMATION_OFFSET = 84; literal VCRP$K_MGMT_INFORMATION_LENGTH = 19; literal VCRP$K_CREATOR_DATA_OFFSET = 228; literal VCRP$K_CREATOR_DATA_LENGTH = 8; literal VCRP$K_INTERNAL_STACK_OFFSET = 248; literal VCRP$K_INTERNAL_STACK_LENGTH = 220; literal VCRP$K_SCRATCH_AREA_OFFSET = 468; literal VCRP$K_SCRATCH_AREA_LENGTH = 64; literal VCRP$K_FIXED_LENGTH = 532; ! Length of fixed part of VCRP ! If this VCM contains data, it will start here or after here. literal VCRP$C_DATA = 532; ! Offset into start of data literal VCRP$S_VCRP = 536; macro VCRP$L_FLINK = 0,0,32,1 %; ! Forward Queue link macro VCRP$L_BLINK = 4,0,32,1 %; ! Backward Queue link macro VCRP$W_SIZE = 8,0,16,0 %; ! Size of structure macro VCRP$B_TYPE = 10,0,8,0 %; ! Type of structure - DYN$C_VCRP macro VCRP$B_RMOD = 11,0,8,0 %; ! Request Modifier for ACB macro VCRP$V_MODE = 11,0,2,0 %; literal VCRP$S_MODE = 2; ! Mode for final delivery macro VCRP$V_ACB_FLAGS_VALID = 11,2,1,0 %; ! Flags in ACB_FLAGS cell are valid macro VCRP$V_PKAST = 11,4,1,0 %; ! Piggy back special kernel AST macro VCRP$V_NODELETE = 11,5,1,0 %; ! Don't delete ACB on delivery macro VCRP$V_QUOTA = 11,6,1,0 %; ! Account for quota macro VCRP$V_KAST = 11,7,1,0 %; ! Special kernel AST macro VCRP$L_PID = 12,0,32,0 %; ! Process Identifier macro VCRP$A_ASTADR = 16,0,32,1 %; ! Address of 32-bit user AST routine macro VCRP$L_ACB64X_OFFSET = 16,0,32,1 %; ! Offset to ACB64X extension macro VCRP$L_ASTPRM = 20,0,32,0 %; ! User 32-bit AST input parameter macro VCRP$L_ACB_FLAGS = 24,0,32,0 %; ! Flags for QAST, valid iff VCRP$V_ACB_FLAGS_VALID is set macro VCRP$L_THREAD_ID = 28,0,32,0 %; ! Kernel thread ID macro VCRP$A_KAST = 32,0,32,1 %; ! Special kernel mode AST routine macro VCRP$PQ_ACB64_AST = 40,0,0,1 %; literal VCRP$S_ACB64_AST = 8; ! 64-bit user AST routine address macro VCRP$Q_ACB64_ASTPRM = 48,0,0,0 %; literal VCRP$S_ACB64_ASTPRM = 8; ! 64-bit user AST parameter value macro VCRP$Q_USER_THREAD_ID = 56,0,0,0 %; literal VCRP$S_USER_THREAD_ID = 8; ! Unique user thread identifier macro VCRP$R_COMMON_FLAGS_OVERLAY = 64,0,16,0 %; macro VCRP$W_COMMON_FLAGS = 64,0,16,0 %; ! Common flags macro VCRP$V_CMN_LOCKED = 64,0,1,0 %; ! Buffer is locked down macro VCRP$V_CMN_RETBUF = 64,1,1,0 %; ! Return buffer immediately macro VCRP$V_CMN_CACHE = 64,2,1,0 %; ! Owner's cache buffer macro VCRP$V_CMN_MGMT = 64,3,1,0 %; ! Mgmt VCRP; not data VCRP macro VCRP$B_FLAGS = 66,0,8,0 %; ! User controlled VCRP flags macro VCRP$B_MODE = 67,0,8,0 %; ! macro VCRP$A_DEALLOC_RTN = 68,0,32,1 %; ! Address of VCRP deallocation routine ! ! This part of the VCRP contains the request specific information. ! VCRPs can contain either a Management request or a Data request. The ! type of VCRP request is determined by the VCRP$W_COMMON_FLAGS field. ! If VCRP$V_CMN_MGMT is set, then the VCRP is using the Management ! request format. IF VCRP$V_CMN_MGMT is NOT set, then the VCRP is ! using the Data request format. ! macro VCRP$R_VCRP_REQUEST = 72,0,0,0 %; literal VCRP$S_VCRP_REQUEST = 132; macro VCRP$R_REQUEST_OVERLAY = 72,0,0,0 %; ! ! Data Request Format. The position of these field are to be the same ! as the DCB fields of the same name. ! macro VCRP$R_DATA_REQUEST = 72,0,0,0 %; literal VCRP$S_DATA_REQUEST = 131; macro VCRP$A_DCB_LINK = 72,0,32,1 %; ! Address of next DCB in chain macro VCRP$L_SVAPTE = 76,0,32,1 %; ! Address of System Virtual Address PTE macro VCRP$L_BUFFER_ADDRESS = 80,0,32,1 %; ! VM Address of buffer specified in SVAPTE macro VCRP$L_BOFF = 84,0,32,0 %; ! Offset to start of data in buffer macro VCRP$L_BCNT = 88,0,32,0 %; ! Byte count of data in buffer macro VCRP$PQ_BUFFER_ADDR64 = 96,0,0,1 %; literal VCRP$S_BUFFER_ADDR64 = 8; ! 64-bit buffer address (upper-level VCM only) macro VCRP$R_DIOBM = 104,0,0,0 %; literal VCRP$S_DIOBM = 88; ! Embedded DIOBM to handle cross-process 32-bit PTE access ! ! All fields preceeding this comment should be similar in layout,name and size ! to a DCB. A programmer should verify that these fields are similar by ! adding the appropriate ASSUMES to his or her code. ! macro VCRP$L_TOTAL_PDU_SIZE = 192,0,32,0 %; ! Total PDU Size ! This 7 byte portion of the data request area can be used by each ! layer to allow its client to pass more information in the request. macro VCRP$T_DATA_INFORMATION = 196,0,0,1 %; literal VCRP$S_DATA_INFORMATION = 7; ! ! Management Request Format. ! macro VCRP$R_MGMT_REQUEST = 72,0,0,0 %; literal VCRP$S_MGMT_REQUEST = 31; macro VCRP$A_INPUT_LIST = 72,0,32,1 %; ! Address of Input item list macro VCRP$A_TEMPLATE_LIST = 76,0,32,1 %; ! Address of Template item list macro VCRP$A_OUTPUT_LIST = 80,0,32,1 %; ! Address of Output item list ! This 19 byte portion of the mgmt request area can be used by each ! layer to allow its client to pass more information in the request. macro VCRP$T_MGMT_INFORMATION = 84,0,0,1 %; literal VCRP$S_MGMT_INFORMATION = 19; macro VCRP$B_LES_FLAGS = 203,0,8,0 %; ! LES flags macro VCRP$L_FUNCTION = 204,0,32,0 %; ! Function for this request macro VCRP$L_ASSOCIATION_ID = 208,0,32,0 %; macro VCRP$L_CONNECTION_ID = 212,0,32,0 %; macro VCRP$R_STATUS_OVERLAY = 216,0,0,0 %; ! Status of request upon completion macro VCRP$R_QUAD_REQUEST = 216,0,0,0 %; literal VCRP$S_QUAD_REQUEST = 8; macro VCRP$Q_REQUEST_STATUS = 216,0,0,0 %; literal VCRP$S_REQUEST_STATUS = 8; macro VCRP$R_LONG_REQUEST = 216,0,0,0 %; literal VCRP$S_LONG_REQUEST = 8; macro VCRP$L_REQUEST_STATUS = 216,0,32,0 %; macro VCRP$L_REQUEST_STATUS_QUAL = 220,0,32,0 %; macro VCRP$A_CREATOR = 224,0,32,1 %; ! VCIB address of creator of VCRP ! The creator data section is a section that is used privately by the ! creator of the VCRP. macro VCRP$R_CREATOR_DATA_OVERLAY = 228,0,0,0 %; macro VCRP$R_QUAD_CREATOR_DATA = 228,0,0,0 %; literal VCRP$S_QUAD_CREATOR_DATA = 8; macro VCRP$Q_CREATOR_DATA = 228,0,0,0 %; literal VCRP$S_CREATOR_DATA = 8; macro VCRP$R_LONG_CREATOR_DATA = 228,0,0,0 %; literal VCRP$S_LONG_CREATOR_DATA = 8; macro VCRP$L_CREATOR_DATA1 = 228,0,32,0 %; macro VCRP$L_CREATOR_DATA2 = 232,0,32,0 %; macro VCRP$Q_LES = 236,0,0,0 %; literal VCRP$S_LES = 8; ! LES information ! The following fields describe the VCRP context stack, which is used by ! by VCM's to preserve request context. The use of the fields is as ! follows: ! ! STACK - contains an address which will point to a stack block. The ! stack block will contain the last used stack pointer ! (LASTUSED), the address of the end of the stack (BTM), the ! address of the top of the stack, and the stack itself ! (STACK). This is layout is used to insure that if the ! context stack is removed from the VCRP and allocated in a ! buffer pointed to by VCRP$A_STACK, that no VCM's will be ! adversely affected. ! LASTUSED - pointer to the last used location in the stack. ! BTM - pointer to the bottom of the stack ! TOP - pointer to the top of the stack ! STACK - Start of context stack. ! ! Saving on and restoring from the context stack can be done by using the ! VCRP_PUSH and VCRP_POP macros. macro VCRP$A_STACK = 244,0,32,1 %; ! Pointer stack block macro VCRP$T_INTERNAL_STACK = 248,0,0,0 %; literal VCRP$S_INTERNAL_STACK = 220; ! VCRP scratch area. This area is not guaranteed to be preserved across ! VCM's. It is intended to be used as VCM temporary data. macro VCRP$T_SCRATCH = 468,0,0,0 %; literal VCRP$S_SCRATCH = 64; macro VCRP$T_DATA = 532,0,0,0 %; ! Start of data (if embedded in the VCRP) literal VCRP$S_VCRPDEF = 536; !*** MODULE $DCBEDEF *** ! + ! DCBE - Data Chain Block ! ! The DCBE is the data structure used to chain data packets together. A ! chain may consist of on buffer or may buffers each pointed to by a DCBE. ! the format of the DCBE is the same as a VCRP data request, so that a ! VCRP may be the first DCBE in the chain, and describe the entire ! data request. ! ! THE FORMAT OF THIS PACKET SHOULD NOT CHANGE WITHOUT CORRESPONDING CHANGES ! BEING MAY TO A VCRP DATA REQUEST PACKET. ! - literal DCBE$M_CMN_LOCKED = %X'1'; literal DCBE$M_CMN_RETBUF = %X'2'; literal DCBE$M_CMN_CACHE = %X'4'; literal DCBE$G_SCRATCH = 92; ! Start of DCBE scratch area literal DCBE$S_SCRATCH = 4; ! Length of scratch area literal DCBE$S_DCB_HEADER_PE = 96; ! Length of PEDRIVER-specific DCBE header literal DCBE$S_DCBE = 192; macro DCBE$L_FLINK = 0,0,32,1 %; ! Forward Queue link macro DCBE$L_BLINK = 4,0,32,1 %; ! Backward Queue link macro DCBE$W_SIZE = 8,0,16,0 %; ! Size of structure macro DCBE$B_TYPE = 10,0,8,0 %; ! Type of structure - DYN$C_NET macro DCBE$B_SUB_TYPE = 11,0,8,0 %; ! Subtype of structure - DYN$C_VCI_DCB macro DCBE$L_RESERVED = 12,0,0,1 %; literal DCBE$S_RESERVED = 52; ! Reserved to ensure that VCRP and ! DCB look the same up to DCB_HEADER macro DCBE$R_COMMON_FLAGS_OVERLAY = 64,0,16,0 %; macro DCBE$W_COMMON_FLAGS = 64,0,16,0 %; ! Common flags used by all users of DCBs macro DCBE$V_CMN_LOCKED = 64,0,1,0 %; ! Indicates buffer is locked down for direct I/O macro DCBE$V_CMN_RETBUF = 64,1,1,0 %; ! Indicates buffer must be return to owner immediately macro DCBE$V_CMN_CACHE = 64,2,1,0 %; ! Indicates buffer came from creator's cache macro DCBE$B_FLAGS = 66,0,8,0 %; ! User controlled DCB flags macro DCBE$B_MODE = 67,0,8,0 %; ! macro DCBE$A_DEALLOC_RTN = 68,0,32,1 %; ! Address of routine to deallocate VCRP macro DCBE$A_DCB_LINK = 72,0,32,1 %; ! Address of next DCB in chain macro DCBE$L_SVAPTE = 76,0,32,1 %; ! Address of System Virtual Address PTE macro DCBE$L_BUFFER_ADDRESS = 80,0,32,1 %; ! VM Address of buffer specified in SVAPTE macro DCBE$L_BOFF = 84,0,32,0 %; ! Offset to start of data in buffer macro DCBE$L_BCNT = 88,0,32,0 %; ! Byte count of data in buffer macro DCBE$PQ_BUFFER_ADDR64 = 96,0,0,1 %; literal DCBE$S_BUFFER_ADDR64 = 8; ! 64-bit buffer address (upper-level VCM only) macro DCBE$R_DIOBM = 104,0,0,0 %; literal DCBE$S_DIOBM = 88; ! Embedded DIOBM to handle cross-process 32-bit PTE access literal DCBE$K_DCB_HEADER = 192; ! Length of DCB header literal DCBE$S_DCBEDEF = 192; !*** MODULE SSVECDEF *** literal SSVEC_K_LENGTH = 16; ! Size of list element literal SSVEC_S_SSVECDEF = 16; ! Old size name - synonym literal SSVEC_S_SSVEC = 16; macro SSVEC_L_TOUCH_STACK = 0,0,32,1 %; ! Touch user's stack macro SSVEC_L_SAVESP = 4,0,32,1 %; ! Save Caller's SP macro SSVEC_L_LDA_CODE = 8,0,32,0 %; ! Load CHM code into R0 macro SSVEC_L_CHMX = 12,0,32,0 %; ! CHMx instruction !*** MODULE DISPDEF *** literal DISP_K_LENGTH = 16; ! Size of list element literal DISP_S_DISPDEF = 16; ! Old size name - synonym literal DISP_S_DISP = 16; macro DISP_A_SERVICE_ROUTINE = 0,0,32,0 %; ! Address of first instruction of ! service-specific procedure macro DISP_A_ENTRY_POINT = 4,0,32,0 %; ! Actual code address macro DISP_B_FLAGS = 8,0,8,0 %; ! Flags (first byte for compatibility) macro DISP_W_VECTOR_INDEX = 12,0,16,1 %; ! Index into SYS$PUBLIC_VECTORS !*** MODULE SSDESCRDEF *** literal EXIT_K_NORMAL_EXIT = 0; ! Default exit code literal EXIT_K_RMS_STALL = 1; ! RMS wait for I/O completion literal EXIT_K_RMS_WAIT = 2; ! RMS $WAIT eit code literal EXIT_K_ASSIGN_EXIT = 3; ! Special exit code for $ASSIGN to perform ! assign to network object in caller's mode. literal SSDESCR_M_CLASS_0 = %X'1'; literal SSDESCR_M_CLASS_1 = %X'2'; literal SSDESCR_M_CLASS_2 = %X'4'; literal SSDESCR_M_CLASS_3 = %X'8'; literal SSDESCR_M_CLASS_4 = %X'10'; literal SSDESCR_M_CLASS_5 = %X'20'; literal SSDESCR_M_CLASS_6 = %X'40'; literal SSDESCR_M_CLASS_7 = %X'80'; literal MODE_K_KERNEL = 0; ! Service executes in KERNEL mode literal MODE_K_EXEC = 1; ! Service executes in EXECUTIVE mode literal MODE_K_SUPER = 2; ! Service executes in SUPERVISOR mode literal MODE_K_USER = 3; ! Service executes in USER mode literal MODE_K_CALLERS_MODE = 4; ! Service executes in the mode of the caller literal TYPE_K_NORMAL = 0; ! No composite type, default value literal TYPE_K_QIOW = 1; ! Composite type QIOW literal TYPE_K_ENQW = 2; ! Composite type ENQW literal TYPE_K_GETDVIW = 3; ! Composite type GETDVIW literal TYPE_K_GETJPIW = 4; ! Composite type GETJPIW literal TYPE_K_GETSYIW = 5; ! Composite type GETSYIW literal TYPE_K_SNDJBCW = 6; ! Composite type SNDJBCW literal TYPE_K_GETLKIW = 7; ! Composite type GETLKIW literal TYPE_K_BRKTHRUW = 8; ! Composite type BRKTHRUW literal TYPE_K_GETQUIW = 9; ! Composite type GETQUIW literal TYPE_K_END_RU = 10; ! Composite type END_RU literal TYPE_K_START_TRANSW = 11; ! Composite type START_TRANS literal TYPE_K_END_TRANSW = 12; ! Composite type END_TRANS literal TYPE_K_ABORT_TRANSW = 13; ! Composite type ABORT_TRANS literal TYPE_K_DECLARE_RMW = 14; ! Composite type DECLARE_RM literal TYPE_K_FORGET_RMW = 15; ! Composite type FORGET_RM literal TYPE_K_JOIN_RMW = 16; ! Composite type JOIN_RM literal TYPE_K_FINISH_RMOPW = 17; ! Composite type FINISH_RMOP literal TYPE_K_ADD_BRANCHW = 18; ! Composite type ADD_BRANCH literal TYPE_K_START_BRANCHW = 19; ! Composite type START_BRANCH literal TYPE_K_IPCW = 20; ! Composite type IPCW literal TYPE_K_END_BRANCHW = 21; ! Composite type END_BRANCHW literal TYPE_K_AUDIT_EVENTW = 22; ! Composite type AUDIT_EVENTW literal TYPE_K_CHECK_PRIVILEGEW = 23; ! Composite type CHECK_PRIVILEGE literal TYPE_K_MAXIMUM = 24; ! Maximum number of types literal SSFLAG_K_WCM = 1; ! May return WCM literal SSFLAG_K_WCM_NO_REEXEC = 2; ! Don't reexecute literal SSFLAG_K_CLRREG = 4; ! Clear scratch regs literal SSFLAG_K_RETURN_ANY = 8; ! May return any val literal SSFLAG_K_WCM_NO_SAVE = 16; ! Don't save regs literal SSFLAG_K_STACK_ARGS = 32; ! pointer->stack args literal SSFLAG_K_THREAD_SAFE = 64; ! no inner-mode synchronization literal SSFLAG_K_64_BIT_ARGS = 128; ! No sign-extension checking necessary literal SSFLAG_K_CHECK_UPCALL = 256; ! Inner mode semaphore waits can ! potentially be done by thread manager literal SSFLAG_K_EXCLUSIVE = 512; ! service requires exclusive access to inner mode literal SSFLAG_K_TOLERANT = 1024; ! thread-safe service which blocks exclusive services literal SSFLAG_K_IMSEM_RELEASE = 2048; ! must release semaphore literal SSFLAG_K_RESET_ASTEN = 4096; ! dispatcher must reenable ASTs literal SSFLAG_K_NOPCB = 8192; ! no pcb in R4 literal SSDESCR_S_SSDESCR = 16; macro SSDESCR_A_VECTOR_ADDRESS = 0,0,32,0 %; ! Address of vector in S0 space macro SSDESCR_A_ENTRY_ADDRESS = 4,0,32,0 %; ! Self-relative pointer to .ENTRY mask macro SSDESCR_B_SYNCH_TYPE = 8,0,8,0 %; ! Composite service type macro SSDESCR_B_FLAGS = 9,0,8,0 %; ! Flags byte, see FLAGS32 macro SSDESCR_B_INHIBIT_MASK = 10,0,8,0 %; ! System service inhibit mask macro SSDESCR_V_CLASS_0 = 10,0,1,0 %; macro SSDESCR_V_CLASS_1 = 10,1,1,0 %; macro SSDESCR_V_CLASS_2 = 10,2,1,0 %; macro SSDESCR_V_CLASS_3 = 10,3,1,0 %; macro SSDESCR_V_CLASS_4 = 10,4,1,0 %; macro SSDESCR_V_CLASS_5 = 10,5,1,0 %; macro SSDESCR_V_CLASS_6 = 10,6,1,0 %; macro SSDESCR_V_CLASS_7 = 10,7,1,0 %; macro SSDESCR_B_MODE = 11,0,8,0 %; ! Access mode in which service executes macro SSDESCR_L_FLAGS32 = 12,0,32,0 %; ! Longword to allow for 32 flags ! copy of FLAGS byte plus ! additional bits greater than 8 ! ! ********* NOTE WELL ********* ! ! The following masks must EXACTLY EQUAL the PLV masks defined in ! [LIB]PLVDEF.SDL. The system service dispatcher assumes, for example, that ! PLV$M_WAIT_CALLERS_MODE equals SSFLAG_K_WCM. Ensure that any additions to ! the SSFLAG flags are reflected in [LIB]VECTORS.SDL (and vice versa). ! ! Also note that although PLVFLG is defined to be a quadword, the dispatcher ! treats the array of kernel flags and exec flags as an array of LONGWORD ! flags. ! ! ********* END NOTE WELL ********* ! literal SSDESCR_K_LENGTH = 16; ! Size of list element literal SSDESCR_S_SSDESCRDEF = 16; ! Old size name - synonym literal FASTSS$K_CLRAST = 1; ! CLRAST change mode code literal FASTSS$K_WTAMI = 2; ! WTAMI change mode code literal FASTSS$K_UNWIND_CLRAST = 3; ! UNWIND_CLRAST change mode code !*** MODULE $VHPTDEF *** ! ! Definitions for Virtual Hash Page Table ! literal VHPT$M_P = %X'1'; literal VHPT$M_MBZ0 = %X'2'; literal VHPT$M_MA = %X'1C'; literal VHPT$M_A = %X'20'; literal VHPT$M_D = %X'40'; literal VHPT$M_PL = %X'180'; literal VHPT$M_AR = %X'E00'; literal VHPT$M_PPN = %X'3FFFFFFFFF000'; literal VHPT$M_MBZ1 = %X'C000000000000'; literal VHPT$M_ED = %X'10000000000000'; literal VHPT$M_IGN0 = %X'FFE0000000000000'; literal VHPT$M_MBZ2 = %X'3'; literal VHPT$M_PS = %X'FC'; literal VHPT$M_KEY = %X'FFFFFF00'; literal VHPT$M_MBZ3 = %X'FFFFFFFF00000000'; literal VHPT$M_TAG = %X'7FFFFFFFFFFFFFFF'; literal VHPT$M_TI = %X'8000000000000000'; literal VHPT$m_reserved4_0 = %X'FFFFFFFF'; literal VHPT$M_RID = %X'FFFFFF00000000'; literal VHPT$m_reserved4_1 = %X'1F00000000000000'; literal VHPT$M_VRN = %X'E000000000000000'; literal VHPT$S_VHPT = 32; macro VHPT$R_VHPTDEF_QUAD1 = 0,0,0,0 %; literal VHPT$S_VHPTDEF_QUAD1 = 8; macro VHPT$Q_PTE0 = 0,0,0,0 %; literal VHPT$S_PTE0 = 8; ! Refered to as PTE0 sometimes macro VHPT$V_P = 0,0,1,0 %; ! Present bit macro VHPT$V_MBZ0 = 0,1,1,0 %; ! Reserved (MBZ) macro VHPT$V_MA = 0,2,3,0 %; literal VHPT$S_MA = 3; ! Memory Attribute macro VHPT$V_A = 0,5,1,0 %; ! Accessed bit macro VHPT$V_D = 0,6,1,0 %; ! Dirty bit macro VHPT$V_PL = 0,7,2,0 %; literal VHPT$S_PL = 2; ! Privilege level macro VHPT$V_AR = 0,9,3,0 %; literal VHPT$S_AR = 3; ! Access Rights macro VHPT$V_PPN = 0,12,38,0 %; literal VHPT$S_PPN = 38; ! Physical page number macro VHPT$V_MBZ1 = 4,18,2,0 %; literal VHPT$S_MBZ1 = 2; ! Reserved bits (MBZ) macro VHPT$V_ED = 4,20,1,0 %; ! Exception deferral macro VHPT$V_IGN0 = 4,21,11,0 %; literal VHPT$S_IGN0 = 11; ! Ignored bits {63:53} macro VHPT$R_VHPTDEF_QUAD2 = 8,0,0,0 %; literal VHPT$S_VHPTDEF_QUAD2 = 8; macro VHPT$Q_VHPT_QUAD2 = 8,0,0,0 %; literal VHPT$S_VHPT_QUAD2 = 8; ! Second Quadword macro VHPT$V_MBZ2 = 8,0,2,0 %; literal VHPT$S_MBZ2 = 2; ! Reserved (MBZ) macro VHPT$V_PS = 8,2,6,0 %; literal VHPT$S_PS = 6; ! Page Size macro VHPT$V_KEY = 8,8,24,0 %; literal VHPT$S_KEY = 24; ! Protection key macro VHPT$V_MBZ3 = 12,0,32,0 %; literal VHPT$S_MBZ3 = 32; ! Reserved (MBZ) macro VHPT$R_VHPTDEF_QUAD3 = 16,0,0,0 %; literal VHPT$S_VHPTDEF_QUAD3 = 8; macro VHPT$Q_VHPT_QUAD3 = 16,0,0,0 %; literal VHPT$S_VHPT_QUAD3 = 8; ! Third Quadword macro VHPT$V_TAG = 16,0,63,0 %; literal VHPT$S_TAG = 63; ! Translation tag macro VHPT$V_TI = 20,31,1,0 %; ! Tag Invalid bit macro VHPT$R_VHPTDEF_QUAD4 = 24,0,0,0 %; literal VHPT$S_VHPTDEF_QUAD4 = 8; macro VHPT$Q_VHPT_QUAD4 = 24,0,0,0 %; literal VHPT$S_VHPT_QUAD4 = 8; ! Fourth Quadword macro VHPT$Q_IGN1 = 24,0,0,0 %; literal VHPT$S_IGN1 = 8; ! Ignored macro VHPT$v_reserved4_0 = 24,0,32,0 %; literal VHPT$s_reserved4_0 = 32; macro VHPT$V_RID = 28,0,24,0 %; literal VHPT$S_RID = 24; ! RID for entry macro VHPT$v_reserved4_1 = 28,24,5,0 %; literal VHPT$s_reserved4_1 = 5; macro VHPT$V_VRN = 28,29,3,0 %; literal VHPT$S_VRN = 3; ! VRN for entry !*** MODULE $VL1DEF *** ! + ! VOL1 ANSI MAGNETIC TAPE LABEL ! THIS IS THE FIRST BLOCK ON EVERY ANSI LABELED MAGNETIC TAPE. ! IT IDENTIFIES THE VOLUME AND ITS PROTECTION. ! - literal VL1$S_VL1DEF = 80; literal VL1$S_VL1 = 80; macro VL1$L_VL1LID = 0,0,32,0 %; ! LABEL IDENTIFIER AND NUMBER 'VOL1' macro VL1$T_VOLLBL = 4,0,0,0 %; literal VL1$S_VOLLBL = 6; ! VOLUME LABEL macro VL1$B_VOLACCESS = 10,0,8,0 %; ! VOLUME ACCESS macro VL1$T_SYSCODE = 24,0,0,0 %; literal VL1$S_SYSCODE = 13; ! SYSTEM CODE macro VL1$T_OWNER_IDENT = 37,0,0,0 %; literal VL1$S_OWNER_IDENT = 14; ! VOL1 OWNER ID FIELD macro VL1$T_VOLOWNER = 37,0,0,0 %; literal VL1$S_VOLOWNER = 13; ! VOLUME OWNER IDENTIFICATION macro VL1$B_DECSTDVER = 50,0,8,0 %; ! DEC STANDARD VERSION macro VL1$B_LBLSTDVER = 79,0,8,0 %; ! LABEL STANDARD VERSION '3' !*** MODULE $VL2DEF *** ! + ! VOL2 ANSI MAGNETIC TAPE LABEL ! THIS IS BLOCK IS WRITTEN TO TAPES WHEN A VMS PROTECTION IS SPECIFIED ! - literal VL2$S_VL2DEF = 19; literal VL2$S_VL2 = 19; macro VL2$L_VL2LID = 0,0,32,0 %; ! LABEL IDENTIFIER AND NUMBER 'VOL2' macro VL2$T_VOLOWNER = 4,0,0,0 %; literal VL2$S_VOLOWNER = 15; ! VOLUME OWNER IDENTIFICATION !*** MODULE $VLEDEF *** ! ! VLE (Vector List Extension) ! This structure is used to hold the list of interrupt vectors used by a ! particular controller when the controller requires more than one vector. ! If the VLE flag in an IDB is set, the field IDB$L_VECTOR points to this ! structure. ! literal VLE$K_LENGTH = 12; literal VLE$C_LENGTH = 12; literal VLE$S_VLEDEF = 12; ! Old size name - synonym literal VLE$S_VLE = 16; macro VLE$PS_IDB = 0,0,32,1 %; ! pointer to parent IDB macro VLE$L_NUMVEC = 4,0,32,0 %; ! number of vector entries in the VLE macro VLE$W_SIZE = 8,0,16,0 %; ! size of this structure macro VLE$B_TYPE = 10,0,8,0 %; ! structure type macro VLE$B_SUBTYPE = 11,0,8,0 %; ! structure subtype ! VECTOR_LIST is an array of unsigned longwords containing the appropriate ! byte offset into either the SCB or the ADP vector table. ! put the constant's in front of the definition of vector list so that the ! header size constants stay the same. macro VLE$L_VECTOR_LIST = 12,0,32,1 %; literal VLE$S_VECTOR_LIST = 4; ! beginning of interrupt vector list !*** MODULE $WCBDEF *** ! + ! WCB - WINDOW CONTROL BLOCK ! ! THERE IS A WINDOW CONTROL BLOCK FOR EACH FILE ACCESSED BY A PROCESS. ! IT CONTAINS MAPPING INFORMATION SUCH THAT A LARGE PERCENTAGE OF VIRTUAL ! FILE I/O CAN BE MAPPED FROM VIRTUAL TO LOGICAL BLOCK NUMBERS WITHOUT ! HAVING TO READ THE RESPECTIVE FILE HEADER. ! - literal WCB$M_READ = %X'1'; literal WCB$M_WRITE = %X'2'; literal WCB$M_NOTFCP = %X'4'; literal WCB$M_SHRWCB = %X'8'; literal WCB$M_OVERDRAWN = %X'10'; literal WCB$M_COMPLETE = %X'20'; literal WCB$M_CATHEDRAL = %X'40'; literal WCB$M_EXPIRE = %X'80'; literal WCB$M_CONTROL = %X'1000'; literal WCB$M_NO_READ_DATA = %X'2000'; literal WCB$K_MAP = 80; ! MAP POINTERS START HERE literal WCB$C_MAP = 80; ! MAP POINTERS START HERE literal WCB$K_LENGTH = 80; ! LENGTH OF STANDARD WCB SANS POINTERS literal WCB$C_LENGTH = 80; ! LENGTH OF STANDARD WCB SANS POINTERS ! NOTE THAT VIRTUAL MAPPING literal WCB$S_WCBDEF = 104; ! Old size name - synonym literal WCB$S_WCB = 104; macro WCB$L_WLFL = 0,0,32,1 %; ! WINDOW LIST FORWARD LINK macro WCB$L_WLBL = 4,0,32,1 %; ! WINDOW LIST BACKWARD LINK macro WCB$W_SIZE = 8,0,16,0 %; ! SIZE OF WINDOW BLOCK IN BYTES macro WCB$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE OF WCB macro WCB$B_ACCESS = 11,0,8,0 %; ! ACCESS CONTROL BYTE macro WCB$V_READ = 11,0,1,0 %; ! READ ACCESS ALLOWED (1=YES) macro WCB$V_WRITE = 11,1,1,0 %; ! WRITE ACCESS ALLOWED (1=YES) macro WCB$V_NOTFCP = 11,2,1,0 %; ! FILE NOT ACCESSED BY FCP IF SET macro WCB$V_SHRWCB = 11,3,1,0 %; ! SHARED WINDOW macro WCB$V_OVERDRAWN = 11,4,1,0 %; ! FILE ACCESSOR HAS OVERDRAWN HIS QUOTA macro WCB$V_COMPLETE = 11,5,1,0 %; ! SET WINDOW MAPS ENTIRE FILE macro WCB$V_CATHEDRAL = 11,6,1,0 %; ! LARGE, COMPLEX WINDOW (SIC) TO MAP ! FILE COMPLETELY macro WCB$V_EXPIRE = 11,7,1,0 %; ! FILE EXPIRATION DATE MAY NEED TO BE SET macro WCB$L_PID = 12,0,32,0 %; ! PROCESS ID OF ACCESSOR PROCESS macro WCB$L_REFCNT = 16,0,32,0 %; ! REFERENCE COUNT FOR SHARED WINDOW macro WCB$L_ORGUCB = 20,0,32,1 %; ! ADDRESS OF ORIGINAL UCB FROM CCB macro WCB$L_ACON = 24,0,32,0 %; ! ACCESS CONTROL INFORMATION ! NOTE - THESE BITS TRACK THE BITS ! IN FIB$L_ACCTL macro WCB$V_NOWRITE = 24,0,1,0 %; ! NO OTHER WRITERS macro WCB$V_DLOCK = 24,1,1,0 %; ! ENABLE DEACCESS LOCK macro WCB$V_SPOOL = 24,4,1,0 %; ! SPOOL FILE ON CLOSE macro WCB$V_WRITECK = 24,5,1,0 %; ! ENABLE WRITE CHECK macro WCB$V_SEQONLY = 24,6,1,0 %; ! SEQUENTIAL ONLY ACCESS macro WCB$V_SNAPSHOT = 24,7,1,0 %; ! SNAPSHOT REVALIDATION PENDING macro WCB$V_WRITEAC = 24,8,1,0 %; ! WRITE ACCESS macro WCB$V_READCK = 24,9,1,0 %; ! ENABLE READ CHECK macro WCB$V_NOREAD = 24,10,1,0 %; ! NO OTHER READERS macro WCB$V_NOTRUNC = 24,11,1,0 %; ! NO TRUNCATES macro WCB$V_CONTROL = 24,12,1,0 %; ! CONTROL ACCESS TO FILE macro WCB$V_NO_READ_DATA = 24,13,1,0 %; ! NO READ ACCESS TO FILE DATA ! THE FOLLOWING FIELDS OVERLAY THE FIRST ! UNUSED FLAG IN WCB$W_ACON ABOVE (FILL_1). macro WCB$V_NOACCLOCK = 24,2,1,0 %; ! NO ACCESS LOCK CHECKING macro WCB$V_SSIO = 24,3,1,0 %; ! File is open for SSIO access. macro WCB$V_READINIT = 24,14,1,0 %; ! A READINIT WAS DONE OVER THIS CHANNEL macro WCB$V_WRITE_TURN = 24,15,1,0 %; ! FORCE WINDOW TURN ON WRITES macro WCB$PS_SSIO_SC = 28,0,32,1 %; ! Pointer to SSIO Stream Context (if SSIO access) macro WCB$L_NMAP = 32,0,32,0 %; ! NUMBER OF MAPPING POINTERS macro WCB$L_FCB = 36,0,32,1 %; ! ADDRESS OF FCB macro WCB$L_RVT = 40,0,32,1 %; ! ADDRESS OF RELATIVE VOLUME TABLE macro WCB$L_LINK = 44,0,32,1 %; ! LINK TO NEXT WINDOW SEGMENT macro WCB$Q_OPENTIME = 48,0,0,0 %; literal WCB$S_OPENTIME = 8; ! Creation time of WCB macro WCB$L_READS = 56,0,32,0 %; ! Count of read I/Os macro WCB$L_WRITES = 60,0,32,0 %; ! Count of write I/Os macro WCB$L_SPLIT_IO = 64,0,32,0 %; ! Count of split I/Os macro WCB$L_ASSIST_IO = 68,0,32,0 %; ! Count of file system assisted I/Os macro WCB$L_STVBN = 76,0,32,0 %; ! STARTING VBN MAPPED BY WINDOW ! NEEDS P1_COUNT IMMEDIATELY ! FOLLOWING STVBN macro WCB$W_P1_COUNT = 80,0,16,0 %; ! TMP macro WCB$L_P1_COUNT = 80,0,32,0 %; ! COUNT FIELD OF FIRST POINTER macro WCB$L_P1_LBN = 84,0,32,0 %; ! LBN FIELD OF SECOND POINTER macro WCB$L_P1_RVN = 88,0,32,0 %; ! RVN OF FIRST POINTER macro WCB$Q_DELIQ = 80,0,0,0 %; literal WCB$S_DELIQ = 8; ! DELETE PENDIONG QUEUE macro WCB$L_P2_COUNT = 92,0,32,0 %; ! COUNT FIELD OF SECOND POINTER macro WCB$L_P2_LBN = 96,0,32,0 %; ! LBN FIELD OF FIRST POINTER macro WCB$L_P2_RVN = 100,0,32,0 %; ! RVN OF SECOND POINTER ! FORMAT OF RETRIEVAL POINTER literal WCB$K_MAP_PTR_LENGTH = 12; literal WCB$C_MAP_PTR_LENGTH = 12; literal WCB$S_WCBDEF1 = 12; ! Old size name - synonym literal WCB$S_WCB1 = 12; macro WCB$L_COUNT = 0,0,32,0 %; ! COUNT FIELD macro WCB$L_LBN = 4,0,32,0 %; ! LBN FIELD macro WCB$L_RVN = 8,0,32,0 %; ! RVN FIELD literal WCB$S_WCBDEF2 = 13; ! Old size name - synonym literal WCB$S_WCB2 = 13; macro WCB$L_PREVCOUNT = -12,0,32,0 %; ! PREVIOUS RETRIEVAL POINTER macro WCB$L_PREVLBN = -8,0,32,0 %; macro WCB$L_PREVRVN = -4,0,32,0 %; ! RETRIEVAL POINTER FORMAT !*** MODULE $WSLDEF *** ! + ! WORKING SET LIST DEFINITIONS ! - literal WSL$M_VALID = %X'1'; literal WSL$M_PAGTYP = %X'E'; literal WSL$M_PFNLOCK = %X'10'; literal WSL$M_WSLOCK = %X'20'; literal WSL$M_GOODPAGE = %X'40'; literal WSL$M_MODIFY = %X'100'; literal WSL$C_LENGTH = 8; ! Size of WS list entry ! literal WSL$C_PROCESS = 0; ! Process page literal WSL$C_SYSTEM = 2; ! System page literal WSL$C_GLOBAL = 4; ! Global page (read only) literal WSL$C_GBLWRT = 6; ! Global Writable page literal WSL$C_PPGTBL = 8; ! Process Page Table literal WSL$C_GPGTBL = 10; ! Global Page Table literal WSL$C_RESERVED = 12; ! reserved literal WSL$C_UNKNOWN = 14; ! Uninitialized db for this PFN (should never appear in WS) literal WSL$S_WSLDEF = 8; literal WSL$C_SHIFT_SIZE = 3; ! WSLE size as a power of 2 literal WSL$S_WSL = 8; macro WSL$PQ_VA = 0,0,0,1 %; literal WSL$S_VA = 8; ! 64-bit address ! THE FOLLOWING 5 BITS MUST BE IN ORDER macro WSL$V_VALID = 0,0,1,0 %; ! WSL entry Valid macro WSL$V_PAGTYP = 0,1,3,0 %; literal WSL$S_PAGTYP = 3; ! Page type (see $PFNDEF for values) macro WSL$V_PFNLOCK = 0,4,1,0 %; ! Page frame lock ! THE PRECEDING 5 BITS MUST BE IN ORDER macro WSL$V_WSLOCK = 0,5,1,0 %; ! Working set lock macro WSL$V_GOODPAGE = 0,6,1,0 %; ! This page should remain in WS one more pass macro WSL$V_MODIFY = 0,8,1,0 %; ! Saved modify bit ! PAGE TYPE VIELD DEFINITIONS ! ! These constants have been adjusted by left-shifting the constant by the offset to the field WSL$V_PAGTYP. ! To use these when explicitly extracting the field, the adjustment must be removed. For example: ! ! IF .wsle [wsl$v_pagtyp] EQL (wsl$c_system ^-wsl$v_pagtyp) ! !*** MODULE $WQHDEF *** ! + ! WAIT QUEUE HEADER DEFINITIONS ! - literal WQH$K_LENGTH = 16; ! LENGTH OF WAIT QUEUE HEADER literal WQH$C_LENGTH = 16; ! LENGTH OF WAIT QUEUE HEADER literal WQH$S_WQHDEF = 16; literal WQH$S_WQH = 16; macro WQH$L_WQFL = 0,0,32,1 %; ! HEAD OR FORWARD LINK macro WQH$L_WQBL = 4,0,32,1 %; ! TAIL OR BACKWARD LINK macro WQH$L_WQCNT = 8,0,32,0 %; ! WAIT QUEUE COUNT macro WQH$L_WQSTATE = 12,0,32,0 %; ! STATE NUMBER FOR WAIT !*** MODULE $XIPDEF *** ! + ! XIP - Extended IRP ! ! - literal XIP_M_IOSA = %X'80000000'; literal XIP_S_XIP = 592; macro XIP_R_EMBEDDED_IRP = 0,0,0,0 %; literal XIP_S_EMBEDDED_IRP = 560; ! Starts with an IRP macro XIP_L_SCANCNT = 560,0,32,0 %; ! Count - 1 of pages remaining to scan macro XIP_L_DIREC = 564,0,32,0 %; ! +- page size macro XIP_PQ_STARTVA = 568,0,0,1 %; literal XIP_S_STARTVA = 8; ! Starting VA to scan macro XIP_L_UPDFLG = 576,0,32,0 %; ! Section update flags macro XIP_V_IOSA = 576,31,1,0 %; ! IRP contains pointer to IOSA macro XIP_L_ACCESS_MODE = 580,0,32,0 %; ! Maximized access mode for page ownership macro XIP_PS_RDE = 584,0,32,1 %; ! RDE address associated with STARTVA literal XIP_C_LENGTH = 592; ! LENGTH OF STRUCTURE !*** MODULE $XMIDEF *** ! + ! XMI Required Registers ! - literal XMI$C_IO_CLASS = 32; literal XMI$C_MEMORY_CLASS = 64; literal XMI$C_CPU_CLASS = 128; ! literal XMI$C_READ = 1; literal XMI$C_IREAD = 2; literal XMI$C_UWMASK = 6; literal XMI$C_WMASK = 7; literal XMI$C_INTR = 8; literal XMI$C_IDENT = 9; literal XMI$C_IVINTR = 15; ! XMI-2 additional commands literal XMI$C_OREAD = 3; literal XMI$C_DWMASK = 4; literal XMI$C_TBDATA = 11; literal XMI$M_EMP = %X'2'; literal XMI$M_DXTO = %X'4'; literal XMI$M_EHWW = %X'8'; literal XMI$M_FCMD = %X'F'; literal XMI$M_FCID = %X'3F0'; literal XMI$M_STF = %X'400'; literal XMI$M_ETF = %X'800'; literal XMI$M_NSES = %X'1000'; literal XMI$M_TTO = %X'2000'; literal XMI$M_TE = %X'4000'; literal XMI$M_CNAK = %X'8000'; literal XMI$M_RER = %X'10000'; literal XMI$M_RSE = %X'20000'; literal XMI$M_NRR = %X'40000'; literal XMI$M_CRD = %X'80000'; literal XMI$M_WDNAK = %X'100000'; literal XMI$M_RIDNAK = %X'200000'; literal XMI$M_WSE = %X'400000'; literal XMI$M_PE = %X'800000'; literal XMI$M_IPE = %X'1000000'; literal XMI$M_WEI = %X'2000000'; literal XMI$M_XFAULT = %X'4000000'; literal XMI$M_CC = %X'8000000'; literal XMI$M_XBAD = %X'10000000'; literal XMI$M_NHALT = %X'20000000'; literal XMI$M_NRESET = %X'40000000'; literal XMI$M_ES = %X'80000000'; literal XMI$M_SLEEP_MODE = %X'40000000'; literal XMI$M_FAEM_ENABLE = %X'80000000'; literal XMI$M_LOCMOD = %X'3'; literal XMI$M_XBADD = %X'4'; literal XMI$M_CRDID = %X'10000'; literal XMI$M_CCID = %X'20000'; literal XMI$M_SEO = %X'1'; literal XMI$M_OLR = %X'2'; literal XMI$M_URR = %X'4'; literal XMI$S_XMIDEF = 1592; ! Old size name - synonym literal XMI$S_XMI = 1592; macro XMI$L_XDEV = 0,0,32,0 %; ! XMI Device register macro XMI$W_DTYPE = 0,0,16,0 %; ! Device type macro XMI$B_DEV_ID = 0,0,8,0 %; ! Device ID macro XMI$B_CLASS = 1,0,8,0 %; ! Device class macro XMI$W_DREV = 2,0,16,0 %; ! Device Revision ! XMI commands ! macro XMI$L_XBE = 4,0,32,0 %; ! XMI Bus Error register macro XMI$$_FILL_1 = 4,0,1,0 %; ! Reserved bit macro XMI$V_EMP = 4,1,1,0 %; ! Enable More Protocol macro XMI$V_DXTO = 4,2,1,0 %; ! Disable XMI Timeout macro XMI$V_EHWW = 4,3,1,0 %; ! Enable HexaWord Write macro XMI$V_FCMD = 4,0,4,0 %; literal XMI$S_FCMD = 4; ! Failing Command (Pre V1.4) macro XMI$V_FCID = 4,4,6,0 %; literal XMI$S_FCID = 6; ! Failing Commander ID macro XMI$V_STF = 4,10,1,0 %; ! Self-test fail macro XMI$V_ETF = 4,11,1,0 %; ! Extended Test fail macro XMI$V_NSES = 4,12,1,0 %; ! Node-specific Err. Summary macro XMI$V_TTO = 4,13,1,0 %; ! Transaction timeout macro XMI$V_TE = 4,14,1,0 %; ! Transmit error macro XMI$V_CNAK = 4,15,1,0 %; ! Command NoAck macro XMI$V_RER = 4,16,1,0 %; ! Read Error Response macro XMI$V_RSE = 4,17,1,0 %; ! Read Sequence Error macro XMI$V_NRR = 4,18,1,0 %; ! No Read Response macro XMI$V_CRD = 4,19,1,0 %; ! Corrected Read Data macro XMI$V_WDNAK = 4,20,1,0 %; ! Write Data NoACk macro XMI$V_RIDNAK = 4,21,1,0 %; ! Read/IDENT Data NoAck macro XMI$V_WSE = 4,22,1,0 %; ! Write Sequence Error macro XMI$V_PE = 4,23,1,0 %; ! Parity Error macro XMI$V_IPE = 4,24,1,0 %; ! Inconsistent Parity Error macro XMI$V_WEI = 4,25,1,0 %; ! Write Error Interrupt macro XMI$V_XFAULT = 4,26,1,0 %; ! XMI Fault macro XMI$V_CC = 4,27,1,0 %; ! Corrected Confirmation macro XMI$V_XBAD = 4,28,1,0 %; ! XMI Bad macro XMI$V_NHALT = 4,29,1,0 %; ! Node Halt macro XMI$V_NRESET = 4,30,1,0 %; ! Node Reset macro XMI$V_ES = 4,31,1,0 %; ! Error Summary macro XMI$L_XFAD = 8,0,32,0 %; ! XMI Failing Address (physical) register macro XMI$L_XFADR0 = 8,0,32,0 %; ! XMI Failing Address (physical) register macro XMI$V_FADR = 8,0,30,0 %; literal XMI$S_FADR = 30; ! Failing Address macro XMI$V_FLN = 8,30,2,0 %; literal XMI$S_FLN = 2; ! Failing length ! register. This is identical ! to other node's XFAER except ! that for the XJA it is here ! at bb+C rather than at bb+2C. macro XMI$L_XJA_XFADRB = 12,0,32,0 %; ! XJA Failing Address register (physical) Ext. ! For the field definitions, use ! those defined below for XFAER. macro XMI$L_XGPR = 12,0,32,0 %; ! XMI General Purpose register macro XMI$L_XJA_XGPR = 16,0,32,0 %; ! XJA's General Purpose Register. macro XMI$L_XCOMM = 16,0,32,0 %; ! XMI Communication register macro XMI$L_XJA_XFAEMCTL = 20,0,32,0 %; ! XJA's FAEM Control Register macro XMI$V_XBI_WINDOW_MASK = 20,0,16,0 %; literal XMI$S_XBI_WINDOW_MASK = 16; ! XBI Window Space Mask macro XMI$V_SLEEP_MODE = 20,30,1,0 %; ! Set Sleep Mode macro XMI$V_FAEM_ENABLE = 20,31,1,0 %; ! Enable FAEM macro XMI$L_XJA_AOSTS = 24,0,32,0 %; ! XJA's Add On Self Test Status Register macro XMI$L_XJA_SERNUM = 28,0,32,0 %; ! XJA's Serial Number Register macro XMI$V_SERIAL_NUMBER = 28,0,17,0 %; literal XMI$S_SERIAL_NUMBER = 17; ! Serial Number macro XMI$V_PLANT = 28,17,4,0 %; literal XMI$S_PLANT = 4; ! Manufacturing Plant. macro XMI$V_REV = 28,21,4,0 %; literal XMI$S_REV = 4; ! Revision Level. macro XMI$V_VARI = 28,25,4,0 %; literal XMI$S_VARI = 4; ! Variation. macro XMI$L_NSCSR = 28,0,32,0 %; ! XMI-1 Node specific CSR macro XMI$L_NSCSR0 = 28,0,32,0 %; ! XMI-2 Node specific CSR macro XMI$L_XBCR = 36,0,32,0 %; ! XMI-1 Bus control register macro XMI$L_XBCR0 = 36,0,32,0 %; ! XMI-2 Bus control register macro XMI$V_LOCMOD = 36,0,2,0 %; literal XMI$S_LOCMOD = 2; ! Lockout mode bits macro XMI$V_XBADD = 36,2,1,0 %; ! XMI Bad Drive macro XMI$V_CRDID = 36,16,1,0 %; ! Corrected Read Int. disable macro XMI$V_CCID = 36,17,1,0 %; ! Corrected Conf. Int. disable macro XMI$L_XFAER = 44,0,32,0 %; ! XMI-1 Failing Address (physical) Ext register macro XMI$L_XFAER0 = 44,0,32,0 %; ! XMI-2 Failing Address (physical) Ext register macro XMI$V_MASK = 44,0,16,0 %; literal XMI$S_MASK = 16; ! Failing Mask macro XMI$V_ADDREXT = 44,16,10,0 %; literal XMI$S_ADDREXT = 10; ! Failing Address Extension bits [38:29] macro XMI$$_FILL_3 = 44,26,2,0 %; literal XMIS_FILL_3 = 2; ! Reserved bits macro XMI$V_FCMDX = 44,28,4,0 %; literal XMI$S_FCMDX = 4; ! Failing Command ! End of XMI-1 Register. The addition register only apply to XMI-2. macro XMI$L_XBEER = 52,0,32,0 %; ! XMI-1 Bus Error extension macro XMI$L_XBEER0 = 52,0,32,0 %; ! XMI-2 Bus Error extension macro XMI$V_SEO = 52,0,1,0 %; ! Second Error Occured macro XMI$V_OLR = 52,1,1,0 %; ! Only LOC Response macro XMI$V_URR = 52,2,1,0 %; ! Unexpected Read Response macro XMI$L_XBE1 = 516,0,32,0 %; ! XMI-2 Bus Error register macro XMI$L_XFAD1 = 520,0,32,0 %; ! XMI-2 Failing Addr (physical) register macro XMI$L_NSCSR1 = 540,0,32,0 %; ! XMI-2 Node specific CSR macro XMI$L_XBCR1 = 548,0,32,0 %; ! XMI-2 Bus control register macro XMI$L_XFAER1 = 556,0,32,0 %; ! XMI-2 Failing addr. (physical) extension macro XMI$L_XBEER1 = 564,0,32,0 %; ! XMI-2 Bus Error extension ! macro XMI$L_XBE2 = 1028,0,32,0 %; ! XMI-2 Bus Error register macro XMI$L_XFAD2 = 1032,0,32,0 %; ! XMI-2 Failing Addr (physical) register macro XMI$L_NSCSR2 = 1052,0,32,0 %; ! XMI-2 Node specific CSR macro XMI$L_XBCR2 = 1060,0,32,0 %; ! XMI-2 Bus control register macro XMI$L_XFAER2 = 1068,0,32,0 %; ! XMI-2 Failing addr. (physical) extension macro XMI$L_XBEER2 = 1076,0,32,0 %; ! XMI-2 Bus Error extension ! macro XMI$L_XBE3 = 1540,0,32,0 %; ! XMI-2 Bus Error register macro XMI$L_XFAD3 = 1544,0,32,0 %; ! XMI-2 Failing Addr (phsycial) register macro XMI$L_NSCSR3 = 1564,0,32,0 %; ! XMI-2 Node specific CSR macro XMI$L_XBCR3 = 1572,0,32,0 %; ! XMI-2 Bus control register macro XMI$L_XFAER3 = 1580,0,32,0 %; ! XMI-2 Failing addr. (physical) extension macro XMI$L_XBEER3 = 1588,0,32,0 %; ! XMI-2 Bus Error extension !*** MODULE $SSLOGDEF *** ! ! Log System Service system space pointer Block ! literal SSLB$M_IOINPROG = %X'1'; literal SSLB$M_UNLOAD = %X'2'; literal SSLB$M_NOARGS = %X'4'; literal SSLB$M_NOFILE = %X'8'; literal SSLB$K_LENGTH = 60; ! Length of SSLB literal SSLB$C_LENGTH = 60; ! Length of SSLB literal SSLB$S_SSLB = 64; macro SSLB$Q_FLAGS = 0,0,0,0 %; literal SSLB$S_FLAGS = 8; ! Global logging flags macro SSLB$V_IOINPROG = 0,0,1,0 %; ! I/O in progress macro SSLB$V_UNLOAD = 0,1,1,0 %; ! Unload issued macro SSLB$V_NOARGS = 0,2,1,0 %; ! Don't record service arguments macro SSLB$V_NOFILE = 0,3,1,0 %; ! Don't write log buffers to file macro SSLB$PQ_BUFFERS = 8,0,0,1 %; literal SSLB$S_BUFFERS = 8; ! Pointer to buffers macro SSLB$PQ_BUFHDRS = 16,0,0,1 %; literal SSLB$S_BUFHDRS = 8; ! Pointer to SSBUFs macro SSLB$Q_REGION_ID = 24,0,0,0 %; literal SSLB$S_REGION_ID = 8; ! ID of perm. region macro SSLB$Q_IOSB = 32,0,0,0 %; literal SSLB$S_IOSB = 8; ! IOSB for logfile extend macro SSLB$W_IOSB_STATUS = 32,0,16,0 %; ! Status of completed I/O macro SSLB$W_IOSB_BCNT = 34,0,16,0 %; ! Bytecount macro SSLB$L_IOSB_PID = 36,0,32,0 %; ! PID macro SSLB$L_LOGFIB = 40,0,32,1 %; ! Logfile FIB macro SSLB$L_CURBLK = 44,0,32,0 %; ! Logfile VBN macro SSLB$L_MAXBLK = 48,0,32,0 %; ! Max logfile VBN macro SSLB$L_CHANNEL = 52,0,32,0 %; ! Log file channel number macro SSLB$L_STATUS = 56,0,32,0 %; ! General saved failure status ! ! Log System Service Buffer Header ! literal SSBUF$M_FULL = %X'1'; literal SSBUF$K_LENGTH = 56; ! Length of allocation buffer header literal SSBUF$C_LENGTH = 56; ! Length of allocation buffer header literal SSBUF$S_SSBUFDEF = 56; literal SSBUF$S_SSBUF = 56; macro SSBUF$L_BUSY = 0,0,32,0 %; ! Number of busy messages in buffer macro SSBUF$L_MSGCNT = 4,0,32,0 %; ! Number of completed messages in buffer macro SSBUF$L_BUFIND = 8,0,32,0 %; ! Buffer number macro SSBUF$L_FLAGS = 12,0,32,0 %; ! Buffer control flags macro SSBUF$V_FULL = 12,0,1,0 %; ! Buffer full and needs to be ! written. No more allocs. macro SSBUF$PQ_START_BUF = 16,0,0,1 %; literal SSBUF$S_START_BUF = 8; ! Addr beginning of buffer macro SSBUF$PQ_NEXT_ENTRY = 24,0,0,1 %; literal SSBUF$S_NEXT_ENTRY = 8; ! Addr next avail entry in buff macro SSBUF$PQ_END_BUF = 32,0,0,1 %; literal SSBUF$S_END_BUF = 8; ! Addr end of buffer macro SSBUF$L_SEQNUM = 40,0,32,0 %; ! Sequence num for buff contents macro SSBUF$Q_IOSB = 48,0,0,0 %; literal SSBUF$S_IOSB = 8; ! IOSB for logfile extend macro SSBUF$W_STATUS = 48,0,16,0 %; ! Status of completed I/O macro SSBUF$W_BCNT = 50,0,16,0 %; ! Bytecount macro SSBUF$L_PID = 52,0,32,0 %; ! PID ! ! Log System Service Buffer Entry ! literal SSLOG$M_ENTRY_COMPLETE = %X'1'; literal SSLOG$K_STOP_LENGTH = 20; ! Length of allocation buffer header literal SSLOG$C_STOP_LENGTH = 20; ! Length of allocation buffer header literal SSLOG$K_IMAGE_START = 32; literal SSLOG$K_IMGNAM_LENGTH = 40; literal SSLOG$K_PIMAGE_START = 72; literal SSLOG$K_PIMGNAM_LENGTH = 40; literal SSLOG$K_START_LENGTH = 112; ! Length of allocation buffer header literal SSLOG$C_START_LENGTH = 112; ! Length of allocation buffer header literal SSLOG$K_LENGTH = 144; ! Length of allocation buffer header literal SSLOG$C_LENGTH = 144; ! Length of allocation buffer header literal SSLOG$C_IDH = 1; ! Version major ident literal SSLOG$C_IDH_IDS = 1; ! Version major ident literal SSLOG$C_IDL = 2; ! Version minor ident literal SSLOG$C_IDL_IDS = 2; ! Version minor ident ! associated with ID additions literal SSLOG$S_SSLOG = 144; macro SSLOG$L_SIZE = 0,0,32,0 %; ! Size in bytes of entire entry macro SSLOG$B_ENTRY_TYPE = 4,0,8,1 %; ! Type of entry LOGTYP$C_mumble macro SSLOG$B_FLAGS = 5,0,8,0 %; ! Buffer control flags macro SSLOG$V_ENTRY_COMPLETE = 5,0,1,0 %; ! Sys. service status written macro SSLOG$B_ACMODE = 6,0,8,0 %; ! Access mode of service requestor macro SSLOG$B_BUFIND = 7,0,8,0 %; ! Log buffer indicator macro SSLOG$Q_TIMESTAMP = 8,0,0,0 %; literal SSLOG$S_TIMESTAMP = 8; ! EXE$GQ_SYSTIME contents macro SSLOG$L_ENTRY_NUMBER = 16,0,32,0 %; ! Number associated with this entry macro SSLOG$L_VECTOR_INDEX = 20,0,32,0 %; ! Symbol vector entry number macro SSLOG$W_VERSION_IDH = 20,0,16,0 %; ! Version ID macro SSLOG$W_VERSION_IDL = 22,0,16,0 %; ! Rest of version ID macro SSLOG$L_CHM_NUMBER = 20,0,32,0 %; ! CHMx number for prot. image service macro SSLOG$L_IMAGE_OFFSET = 24,0,32,0 %; ! Image offset of system service request macro SSLOG$L_STATUS = 28,0,32,0 %; ! Service completion status macro SSLOG$T_IMAGE_NAME = 32,0,0,0 %; literal SSLOG$S_IMAGE_NAME = 40; ! Of system service request ASCIZ macro SSLOG$T_USERNAME = 32,0,0,0 %; literal SSLOG$S_USERNAME = 32; ! User name of current process ASCIZ macro SSLOG$L_BUFFER_COUNT = 64,0,32,0 %; ! Number of buffers macro SSLOG$L_START_FLAGS = 68,0,32,0 %; ! SSL startup flags macro SSLOG$T_SSNAME = 72,0,0,0 %; literal SSLOG$S_SSNAME = 32; ! System service name (currently unused) macro SSLOG$T_PROT_IMAGE_NAME = 72,0,0,0 %; literal SSLOG$S_PROT_IMAGE_NAME = 40; ! Name of protected image containing ! service ASCIZ macro SSLOG$L_EPID = 72,0,32,0 %; ! Current process ID macro SSLOG$L_BUFFER_SIZE = 76,0,32,0 %; ! Length in bytes of entire buffer macro SSLOG$T_SCSNODE = 80,0,0,0 %; literal SSLOG$S_SCSNODE = 7; ! Cluster node name ASCIZ macro SSLOG$B_PLATFORM = 87,0,8,0 %; ! SSLOG$C_PLATFORM_ALPHA or _IA64 macro SSLOG$T_PROCNAME = 88,0,0,0 %; literal SSLOG$S_PROCNAME = 16; ! Current process name ASCIZ macro SSLOG$L_ARG_OFFSET = 112,0,32,0 %; ! Byte offset to ARGCOUNT from entry start ! allows upward compatibility for fields ! added between this and ARGCOUNT macro SSLOG$L_STATUS_ENTRY_NUMBER = 116,0,32,0 %; ! Number at time status was written macro SSLOG$L_KTID = 120,0,32,0 %; ! Kernel thread ID macro SSLOG$L_CPUID = 124,0,32,0 %; ! CPU ID at 1st entry to $LOG_SYSTEM_SERVICE macro SSLOG$Q_TID = 128,0,0,0 %; literal SSLOG$S_TID = 8; ! Pthreads ID macro SSLOG$Q_ARGCOUNT = 136,0,0,0 %; literal SSLOG$S_ARGCOUNT = 8; ! Number of quadwords of args that follow !*** MODULE $MMAPDEF *** ! ! Memory Map Definitions. The memory map structure contains memory ! mapping data for a shared memory region. ! literal MMAP$M_VALID = %X'1'; literal MMAP$M_INIT_IN_PROGRESS = %X'2'; literal MMAP$M_RESERVED_2_15 = %X'FFFC'; literal MMAP$C_LENGTH = 64; ! Length of MMAP literal MMAP$S_MMAP = 64; macro MMAP$Q_VIRT_SIZE = 0,0,0,0 %; literal MMAP$S_VIRT_SIZE = 8; ! Virtual size in bytes macro MMAP$W_SIZE = 8,0,16,0 %; ! Size of the structure macro MMAP$B_TYPE = 10,0,8,0 %; ! Dynamic structure type macro MMAP$B_SUBTYPE = 11,0,8,0 %; ! Dynamic structure subtype macro MMAP$W_LEVEL_COUNT = 12,0,16,1 %; ! Number of PFNLST levels macro MMAP$W_FLAGS = 14,0,16,0 %; ! FLAGS word macro MMAP$V_VALID = 14,0,1,0 %; ! MMAP is valid macro MMAP$V_INIT_IN_PROGRESS = 14,1,1,0 %; ! Initialization is in progress macro MMAP$V_RESERVED_2_15 = 14,2,14,0 %; literal MMAP$S_RESERVED_2_15 = 14; macro MMAP$I_FIRST_PFN = 16,0,0,0 %; literal MMAP$S_FIRST_PFN = 8; ! First page in a contiguous range macro MMAP$L_TOP_PAGE_COUNT = 24,0,32,1 %; ! Number of pages at the top level macro MMAP$L_PFNLST_PAGE_COUNT = 28,0,32,1 %; ! Number of PFNLST pages macro MMAP$L_DATA_PAGE_COUNT = 32,0,32,1 %; ! Number of data pages ! Pad to 64 byte boundary literal PFNLST$M_VALID = %X'1'; literal PFNLST$M_UNUSED1 = %X'1E'; literal PFNLST$M_GH = %X'60'; literal PFNLST$M_UNUSED2 = %X'FFFFFF80'; literal PFNLST$M_PFN = %X'FFFFFFFF00000000'; literal PFNLST$C_LENGTH = 8; ! Length of PFNLST literal PFNLST$S_PFNLST = 8; macro PFNLST$V_VALID = 0,0,1,0 %; ! Valid Bit macro PFNLST$V_UNUSED1 = 0,1,4,0 %; literal PFNLST$S_UNUSED1 = 4; ! Bits Unused macro PFNLST$V_GH = 0,5,2,0 %; literal PFNLST$S_GH = 2; ! Granularity Hint macro PFNLST$V_UNUSED2 = 0,7,25,0 %; literal PFNLST$S_UNUSED2 = 25; ! Bits Unused macro PFNLST$V_PFN = 4,0,32,0 %; literal PFNLST$S_PFN = 32; ! Page Frame Number !*** MODULE $SPDTDEF *** ! + ! SPDT - SCSI Port Descriptor Table ! ! There is one SPDT per port. The SPDT contains the SCSI port information ! for one SCSI port. SPDT's are created by the unit init routines ! of the individual port drivers. During initialization the port driver's ! port routine entry points are initialized in the SPDT. The class drivers ! execute these entry points to interact with the underlying port hardware. ! ! This structure is read accessable to the class driver and readable and ! writeable by the port driver. ! ! ***NOTE1:**** New SPDT fields must be entered at the end of the data structure. ! ! ***NOTE2:**** If an INCOMPATIBLE CHANGE is made to this structure bump ! the version number of this structure. ! - literal SPDT$C_VERSION = 12; ! Compatible version number. literal SPDT$C_TYPE_PKS = 1; ! SCSI KZTSA/KZPSA (SimPort) literal SPDT$C_TYPE_PKC = 2; ! SCSI NCR 53C94 Port literal SPDT$C_TYPE_PKZ = 3; ! SCSI KZXZA NCR 53C710 Port literal SPDT$C_TYPE_PKT = 4; ! SCSI NCR 53C710 Port literal SPDT$C_TYPE_PKJ = 5; ! SCSI ADAPTEC 1742A Port literal SPDT$C_TYPE_PKE = 6; ! SCSI NCR 53C810 Port literal SPDT$C_TYPE_PKQ = 7; ! SCSI QLogic ISP1020 Port literal SPDT$C_TYPE_PG = 8; ! FCP port driver literal SPDT$C_TYPE_PKW = 9; ! SCSI SYMBIOS 53C8XX Port literal SPDT$C_TYPE_PKA = 10; ! SCSI Adaptec 7895/7899 port literal SPDT$C_TYPE_PKR = 11; ! Ramanujan CISS controller literal SPDT$C_TYPE_PKM = 12; ! SCSI LSI Logic 1030 Port literal SPDT$C_TYPE_PGQ = 13; ! QLogic ISP23xx FibreChannel port literal SPDT$C_TYPE_DE = 14; ! iSCSI port driver literal SPDT$C_TYPE_GSP = 15; ! X-54 HPVM Guest Storage Port (AVIO) literal SPDT$C_TYPE_PKD = 16; ! AHCI SATA controller literal SPDT$C_TYPE_PGA = 8; literal SPDT$M_PFLG_SYNCH = %X'1'; literal SPDT$M_PFLG_ASYNCH = %X'2'; literal SPDT$M_PFLG_MAPPING_REG = %X'4'; literal SPDT$M_PFLG_BUF_DMA = %X'8'; literal SPDT$M_PFLG_DIR_DMA = %X'10'; literal SPDT$M_PFLG_AEN = %X'20'; literal SPDT$M_PFLG_LUNS = %X'40'; literal SPDT$M_PFLG_CMDQ = %X'80'; literal SPDT$M_PFLG_AUTOSENSE = %X'100'; literal SPDT$M_PFLG_PORT_AUTOSENSE = %X'200'; literal SPDT$M_PFLG_SMART_PORT = %X'400'; literal SPDT$M_PFLG_DIPL = %X'800'; literal SPDT$M_PFLG_64BIT_LUNS = %X'1000'; literal SPDT$M_PFLG_TRANSPORT = %X'E000'; literal SPDT$K_PARALLEL = 0; literal SPDT$K_FIBRE_CHANNEL = 1; literal SPDT$K_ISCSI = 2; literal SPDT$K_SW_ISCSI = 2; ! X-52 literal SPDT$K_HW_ISCSI = 3; ! X-52 literal SPDT$K_SAS = 4; ! X-52 ! F Bits 19:16 literal SPDT$M_PFLG_PATH_INFO = %X'10000'; literal SPDT$M_PFLG_MAXBCNT_OVERRIDE = %X'20000'; literal SPDT$M_PFLG_EXT_LUN = %X'40000'; literal SPDT$M_PFLG_IMP_QFULL = %X'80000'; literal SPDT$M_PFLG_SPL_CTX = %X'100000'; literal SPDT$M_PFLG_PERF_DATA = %X'200000'; literal SPDT$M_PFLG_GO_IO_CREDITS = %X'400000'; literal SPDT$M_STS_ONLINE = %X'1'; literal SPDT$M_STS_TIMOUT = %X'2'; literal SPDT$M_STS_ERLOGIP = %X'4'; literal SPDT$M_STS_CANCEL = %X'8'; literal SPDT$M_STS_POWER = %X'10'; literal SPDT$M_STS_BSY = %X'20'; literal SPDT$M_STS_FAILED = %X'40'; literal SPDT$M_STS_FIFOLCK = %X'80'; literal SPDT$M_STS_QWORK_TODO = %X'100'; literal SPDT$M_STS_RESET_ISSUED = %X'200'; literal SPDT$m_spare = %X'400'; literal SPDT$M_STS_MULTIHOST = %X'800'; literal SPDT$M_STS_TIMEOUT_SOON = %X'1000'; literal SPDT$M_STS_TIMEOUT_NOW = %X'2000'; literal SPDT$M_STS_SAW_TAPE = %X'4000'; literal SPDT$M_STS_FIRST_CONFIG = %X'8000'; literal SPDT$M_DIPL_RESET_IN_PROGRESS = %X'1'; literal SPDT$M_DIPL_RESET_FORK_INUSE = %X'2'; literal SPDT$M_DIPL_RESET_DETECTED_WAIT = %X'4'; literal SPDT$M_DIPL_STDT_SCDT = %X'8'; literal SPDT$M_DIPL_RESET_CU_FORK_INUSE = %X'10'; literal SPDT$C_VEC_START = 88; ! * Start of SCSI Vector Table; used by SCSIDEBUG literal SPDT$C_CD_ABORT_COMMAND = 0; ! I Index in Class Driver vector table literal SPDT$C_CD_BUFFER_MAP = 1; ! I Index in Class Driver vector table literal SPDT$C_CD_BUFFER_UNMAP = 2; ! I Index in Class Driver vector table literal SPDT$C_CD_CMD_BUFFER_ALLOC = 3; ! I Index in Class Driver vector table literal SPDT$C_CD_CMD_BUFFER_DEALLOC = 4; ! I Index in Class Driver vector table literal SPDT$C_CD_CONNECT = 5; ! I Index in Class Driver vector table literal SPDT$C_CD_CONNECTION_CHAR_GET = 6; ! I Index in Class Driver vector table literal SPDT$C_CD_CONNECTION_CHAR_SET = 7; ! I Index in Class Driver vector table literal SPDT$C_CD_DISCONNECT = 8; ! I Index in Class Driver vector table literal SPDT$C_CD_QUEUE_FLUSH = 9; ! I Index in Class Driver vector table literal SPDT$C_CD_QUEUE_FREEZE = 10; ! I Index in Class Driver vector table literal SPDT$C_CD_QUEUE_RELEASE = 11; ! I Index in Class Driver vector table literal SPDT$C_CD_RESET_DEVICE = 12; ! I Index in Class Driver vector table literal SPDT$C_CD_RESET_SCSI_BUS = 13; ! I Index in Class Driver vector table literal SPDT$C_CD_SEND_COMMAND = 14; ! I Index in Class Driver vector table literal SPDT$C_CD_INITIAL_PROCESSING = 15; ! I Index in Class Driver vector table literal SPDT$C_CD_GET_PATH_INFO = 16; ! I Index in Class Driver vector table literal SPDT$C_CD_SCSIPATH_CONNECT = 17; ! I Index in Class Driver vector table literal SPDT$C_CD_GET_PORT_WWID = 18; ! I Index in Class Driver vector table literal SPDT$C_CD_FP_REQUEST = 19; ! I Index in Class Driver vector table literal SPDT$C_CD_FP_SEND = 20; ! I Index in Class Driver vector table literal SPDT$C_CD_FP_FREE_RBUN = 21; ! I Index in Class Driver vector table literal SPDT$C_CD_CANCEL = 21; ! I Index in Class Driver vector table literal SPDT$C_CD_VECTOR_RESERVED = 22; ! I Index in Class Driver vector table literal SPDT$C_PK_ABORT_COMMAND = 0; literal SPDT$C_PK_CMD_BUFFER_ALLOC = 1; literal SPDT$C_PK_CMD_BUFFER_DEALLOC = 2; literal SPDT$C_PK_CMD_WAIT_COMPLETION = 3; literal SPDT$C_PK_CONNECT = 4; literal SPDT$C_PK_CONNECTION_CHAR_SET = 5; literal SPDT$C_PK_INIT_SPDT = 6; literal SPDT$C_PK_INIT_STDT = 7; literal SPDT$C_PK_NEGOTIATE_SYNCH = 8; literal SPDT$C_PK_QUEUE_FLUSH = 9; literal SPDT$C_PK_QUEUE_FREEZE = 10; literal SPDT$C_PK_QUEUE_RELEASE = 11; literal SPDT$C_PK_RESET_SCSI_BUS = 12; literal SPDT$C_PK_SEND_COMMAND = 13; literal SPDT$C_PK_GET_PATH_INFO = 14; literal SPDT$C_PK_FP_REQUEST = 15; literal SPDT$C_PK_FP_SEND = 16; literal SPDT$C_PK_FP_FREE_RBUN = 17; literal SPDT$C_PK_FP_CMD_WAIT_COMP = 18; literal SPDT$C_PK_FP_KP_COMPLETION = 19; literal SPDT$C_PK_ALLOC_POOL = 20; literal SPDT$C_PK_FREE_POOL = 21; literal SPDT$C_PK_SCSI_COMMAND = 22; literal SPDT$C_PK_CANCEL = 23; literal SPDT$C_PK_TRIGGER = 24; literal SPDT$C_PK_TARGET_DISCONNECT = 25; literal SPDT$C_PK_VECTOR_RESERVED = 26; literal SPDT$K_STDT_HASH_SIZE = 16; ! Size of STDT_HASH_TABLE. literal SPDT$K_STDT_HASH_BITBASE = 0; ! Start bit of hash mask. literal SPDT$K_STDT_HASH_BITCNT = 4; ! Number of bits in hash mask. literal SPDT$K_STDT_HASH_BITMASK = 15; ! Bit mask for the hash value. ! literal SPDT$K_CMD_SLOTS = 255; ! Total number of command slot allocation bits. literal SPDT$S_CMD_BITS = 32; ! Total byte count of command slot allocation bit map. literal SPDT$C_PKSLENGTH = 936; ! SIZE OF SPDT literal SPDT$C_PKCLENGTH = 936; ! SIZE OF SPDT literal SPDT$C_PKNLENGTH = 936; ! SIZE OF SPDT literal SPDT$S_SPDTDEF = 936; ! Old size name, synonym for SPDT$S_SPDT literal SPDT$S_SPDT = 936; macro SPDT$L_FLINK = 0,0,32,1 %; ! O Link to next SCSI SPDT macro SPDT$L_VERSION_CHECK = 4,0,32,0 %; ! I Value used to check driver versions macro SPDT$W_SIZE = 8,0,16,0 %; ! I Structure size in bytes macro SPDT$B_TYPE = 10,0,8,0 %; ! I Structure type macro SPDT$B_SUBTYP = 11,0,8,0 %; ! I Structure subtype ! ! SCSI Port Identification. ! macro SPDT$W_SPDT_TYPE = 12,0,16,0 %; ! I Type of SPDT macro SPDT$L_SCSI_PORT_ID = 16,0,32,0 %; ! I SCSI port ID. (A..Z) macro SPDT$L_SCSI_BUS_ID = 20,0,32,0 %; ! I Mask value of host ID (parallel only) macro SPDT$R_SCSI_ID_OVERLAY = 24,0,0,0 %; macro SPDT$IS_SCSI_ID_NUM = 24,0,32,0 %; ! I SCSI bus ID numeric value macro SPDT$Q_SCSI_ID_NUM = 24,0,0,0 %; literal SPDT$S_SCSI_ID_NUM = 8; ! I SCSI bus ID for wide devices, - ! I or high SCSI ID's ! ! Define the port characteristics and status. ! macro SPDT$L_PORT_FLAGS = 32,0,32,0 %; ! F Port specific flags. ! F Bits 03:00 macro SPDT$V_PFLG_SYNCH = 32,0,1,0 %; ! F Supports synchronous mode. macro SPDT$V_PFLG_ASYNCH = 32,1,1,0 %; ! F Supports asynchronous mode. macro SPDT$V_PFLG_MAPPING_REG = 32,2,1,0 %; ! F Supports mapping registers. macro SPDT$V_PFLG_BUF_DMA = 32,3,1,0 %; ! F Supports buffered DMA. ! F Bits 07:04 macro SPDT$V_PFLG_DIR_DMA = 32,4,1,0 %; ! F Supports direct DMA. macro SPDT$V_PFLG_AEN = 32,5,1,0 %; ! F Supports Async Event Notification macro SPDT$V_PFLG_LUNS = 32,6,1,0 %; ! F Supports LUNS macro SPDT$V_PFLG_CMDQ = 32,7,1,0 %; ! F Set if port supports command queueing. ! F Bits 11:08 macro SPDT$V_PFLG_AUTOSENSE = 32,8,1,0 %; ! F Set if the port driver supports autosense. Tested by class drivers. macro SPDT$V_PFLG_PORT_AUTOSENSE = 32,9,1,0 %; ! F Set if port specific hardware/software supports autosense. macro SPDT$V_PFLG_SMART_PORT = 32,10,1,0 %; ! F Set if the port hardware is an intelligent SCSI adapter. macro SPDT$V_PFLG_DIPL = 32,11,1,0 %; ! F Set if the port stalls at DIPL .vs. FORK ! F Bits 15:12 macro SPDT$V_PFLG_64BIT_LUNS = 32,12,1,0 %; ! F Supports 64-bit LUNs. macro SPDT$V_PFLG_TRANSPORT = 32,13,3,0 %; literal SPDT$S_PFLG_TRANSPORT = 3; ! F Physical transport (parallel, FC etc) macro SPDT$V_PFLG_PATH_INFO = 32,16,1,0 %; ! F Accepts connects via sc$scsipath_connect macro SPDT$V_PFLG_MAXBCNT_OVERRIDE = 32,17,1,0 %; ! F Port override for max byte count macro SPDT$V_PFLG_EXT_LUN = 32,18,1,0 %; ! F Supports external LUNs macro SPDT$V_PFLG_IMP_QFULL = 32,19,1,0 %; ! F Improved (over SCSI-2 Queue Manager) Queue Full handling ! F Bits 23:20 macro SPDT$V_PFLG_SPL_CTX = 32,20,1,0 %; ! F Port uses Fork-Port-Dyn spinlock context model macro SPDT$V_PFLG_PERF_DATA = 32,21,1,0 %; ! F Port collects performance data macro SPDT$V_PFLG_GO_IO_CREDITS = 32,22,1,0 %; ! F Port restarts class driver for I/O credits ! F Bits 27:24 ! F Bits 31:28 macro SPDT$L_STS = 36,0,32,0 %; ! F Port device status macro SPDT$V_STS_ONLINE = 36,0,1,0 %; ! F Unit online (1=yes) macro SPDT$V_STS_TIMOUT = 36,1,1,0 %; ! F Unit timed out (1=yes) macro SPDT$V_STS_ERLOGIP = 36,2,1,0 %; ! F Error log in progress on unit (1=yes) macro SPDT$V_STS_CANCEL = 36,3,1,0 %; ! F Cancel I/O on unit (1=yes) macro SPDT$V_STS_POWER = 36,4,1,0 %; ! F Power failed while unit busy (1=yes) macro SPDT$V_STS_BSY = 36,5,1,0 %; ! F Unit is busy (1=yes) macro SPDT$V_STS_FAILED = 36,6,1,0 %; ! F Port failed operation or initialization. macro SPDT$V_STS_FIFOLCK = 36,7,1,0 %; ! F N53C94 FIFO in use macro SPDT$V_STS_QWORK_TODO = 36,8,1,0 %; ! F Set when queue manager has more work to do. macro SPDT$V_STS_RESET_ISSUED = 36,9,1,0 %; ! F Set when PORT issues a reset. macro SPDT$v_spare = 36,10,1,0 %; ! F placeholder for obsolete field macro SPDT$V_STS_MULTIHOST = 36,11,1,0 %; ! F Multiple hosts (for SCSI clusters) macro SPDT$V_STS_TIMEOUT_SOON = 36,12,1,0 %; ! F I/O's to SCSI Port adapter will time out soon macro SPDT$V_STS_TIMEOUT_NOW = 36,13,1,0 %; ! F I/O's to SCSI Port adapter are timing out now macro SPDT$V_STS_SAW_TAPE = 36,14,1,0 %; ! F At one time (and maybe now) a tape was seen macro SPDT$V_STS_FIRST_CONFIG = 36,15,1,0 %; ! F IOGEN$SCS_CONFIG has run once macro SPDT$L_DIPL_STS = 40,0,32,0 %; ! D Port device status manipulated at DIPL macro SPDT$V_DIPL_RESET_IN_PROGRESS = 40,0,1,0 %; ! D Bus Reset in progress macro SPDT$V_DIPL_RESET_FORK_INUSE = 40,1,1,0 %; ! D Bus Reset fork block in use macro SPDT$V_DIPL_RESET_DETECTED_WAIT = 40,2,1,0 %; ! D External reset wait in progress macro SPDT$V_DIPL_STDT_SCDT = 40,3,1,0 %; ! D Deallocation of either SCDT or STDT macro SPDT$V_DIPL_RESET_CU_FORK_INUSE = 40,4,1,0 %; ! D Bus Reset Cleanup fork block in use macro SPDT$IS_FLCK = 44,0,32,0 %; ! I Fork lock index macro SPDT$L_DLCK = 48,0,32,1 %; ! I Device lock address macro SPDT$B_DIPL = 52,0,8,0 %; ! I Device IPL macro SPDT$IS_SAVIPL = 56,0,32,0 %; ! I Saved IPL macro SPDT$IW_ERL_TYPE = 60,0,16,0 %; ! I ERL$DEVICEATN type/subtype codes macro SPDT$IS_CRCTX_SHIFT = 64,0,32,0 %; ! F Counted res. size, as a shift factor macro SPDT$IS_CRCTX_BWP_MASK = 68,0,32,0 %; ! F Counted res. size, as a BWP mask macro SPDT$IS_SCSI_INT_MSK = 72,0,32,0 %; ! F Port-specific interrupt mask macro SPDT$L_MAXBYTECNT = 76,0,32,0 %; ! I Maximum byte count for a transfer. macro SPDT$L_MAX_FP_BCNT = 80,0,32,0 %; ! F Maximum byte count for a FastPath transfer. macro SPDT$L_TIMEOUT_COUNT = 84,0,32,0 %; ! F Counted of I/O's about to time out ! ! The SCSI Port Interface entry points follow. These entry ! points are fork entry points that the class driver envokes ! to execute port specific functions. ! ! Vectors are now also identified by a constant index so they ! can be referenced in a table of copied pointers, whether the ! pointers are longword or quadword ! macro SPDT$R_CD_VECTORS_UNION = 88,0,0,0 %; literal SPDT$S_CD_VECTORS_UNION = 128; macro SPDT$R_CD_VECTORS_STRUCT = 88,0,0,0 %; literal SPDT$S_CD_VECTORS_STRUCT = 128; macro SPDT$PS_CD_ABORT_COMMAND = 88,0,32,1 %; ! I Abort outstanding cmd. macro SPDT$PS_CD_BUFFER_MAP = 92,0,32,1 %; ! I Map a buffer for read or write transfer macro SPDT$PS_CD_BUFFER_UNMAP = 96,0,32,1 %; ! I Unmap a buffer macro SPDT$PS_CD_CMD_BUFFER_ALLOC = 100,0,32,1 %; ! I Allocate a message buffer macro SPDT$PS_CD_CMD_BUFFER_DEALLOC = 104,0,32,1 %; ! I Deallocate buffer macro SPDT$PS_CD_CONNECT = 108,0,32,1 %; ! I Request connection to target. macro SPDT$PS_CD_CONNECTION_CHAR_GET = 112,0,32,1 %; ! I Get connect char. macro SPDT$PS_CD_CONNECTION_CHAR_SET = 116,0,32,1 %; ! I Set connect char. macro SPDT$PS_CD_DISCONNECT = 120,0,32,1 %; ! I Break connection. macro SPDT$PS_CD_QUEUE_FLUSH = 124,0,32,1 %; ! I Address of SC$FLUSH_QUEUE in the port driver. macro SPDT$PS_CD_QUEUE_FREEZE = 128,0,32,1 %; ! I Address of SC$FREEZE_QUEUE in the port driver. macro SPDT$PS_CD_QUEUE_RELEASE = 132,0,32,1 %; ! I Address of SC$RELEASE_QUEUE in the port driver. macro SPDT$PS_CD_RESET_DEVICE = 136,0,32,1 %; ! I Perform a device reset. macro SPDT$PS_CD_RESET_SCSI_BUS = 140,0,32,1 %; ! I Maintenace reset of port macro SPDT$PS_CD_SEND_COMMAND = 144,0,32,1 %; ! I Start processing a SCSI command on the device. macro SPDT$PS_CD_INITIAL_PROCESSING = 148,0,32,1 %; ! I Perform a tolerant INQUIRY command macro SPDT$PS_CD_GET_PATH_INFO = 152,0,32,1 %; ! I Fetch target and LUN macro SPDT$PS_CD_SCSIPATH_CONNECT = 156,0,32,1 %; ! I Connect using path info macro SPDT$PS_CD_GET_PORT_WWID = 160,0,32,1 %; ! I Request a given port's World Wide ID macro SPDT$PS_CD_FP_REQUEST = 164,0,32,1 %; ! I Get permission to FastPath request. macro SPDT$PS_CD_FP_SEND = 168,0,32,1 %; ! I Start processing a FastPath SCSI command on device. macro SPDT$PS_CD_FP_FREE_RBUN = 172,0,32,1 %; ! I Deallocate FastPath buffer macro SPDT$PS_CD_CANCEL = 176,0,32,1 %; ! I Cancel I/O on port ! If you add a vector here, update the symbol used to define CD_VECTOR_RESERVED below macro SPDT$PS_CD_VECTORS = 88,0,0,1 %; literal SPDT$S_CD_VECTORS = 92; ! ! The SCSI Port Interface entry points follow. These entry ! points are the entry points from SCSI2COMMON and SCSI2SUBS into ! the port specific routines. ! macro SPDT$R_PK_VECTORS_UNION = 216,0,0,0 %; literal SPDT$S_PK_VECTORS_UNION = 116; macro SPDT$R_PK_VECTORS_STRUCT = 216,0,0,0 %; literal SPDT$S_PK_VECTORS_STRUCT = 116; macro SPDT$PS_PK_ABORT_COMMAND = 216,0,32,1 %; ! I Abort the outstanding requests. macro SPDT$PS_PK_CMD_BUFFER_ALLOC = 220,0,32,1 %; ! I Allocate a command buffer. macro SPDT$PS_PK_CMD_BUFFER_DEALLOC = 224,0,32,1 %; ! I Deallocate a command buffer. macro SPDT$PS_PK_CMD_WAIT_COMPLETION = 228,0,32,1 %; ! I Wait for the SCSI request to complete. macro SPDT$PS_PK_CONNECT = 232,0,32,1 %; ! I Complete connection and SCDT initialization. macro SPDT$PS_PK_CONNECTION_CHAR_SET = 236,0,32,1 %; ! I Finish setting the connection characteristics. macro SPDT$PS_PK_INIT_SPDT = 240,0,32,1 %; ! I Complete SPDT initialization. macro SPDT$PS_PK_INIT_STDT = 244,0,32,1 %; ! I Complete STDT initialization. macro SPDT$PS_PK_NEGOTIATE_SYNCH = 248,0,32,1 %; ! I Re-negotiate the transfer mode macro SPDT$PS_PK_QUEUE_FLUSH = 252,0,32,1 %; ! I Flush the device queue. macro SPDT$PS_PK_QUEUE_FREEZE = 256,0,32,1 %; ! I Freeze the device queue. macro SPDT$PS_PK_QUEUE_RELEASE = 260,0,32,1 %; ! I Release the device queue. macro SPDT$PS_PK_RESET_SCSI_BUS = 264,0,32,1 %; ! I Reset the SCSI bus. macro SPDT$PS_PK_SEND_COMMAND = 268,0,32,1 %; ! I Initiate the SCSI request. macro SPDT$PS_PK_GET_PATH_INFO = 272,0,32,1 %; ! I Fetch target and LUN. macro SPDT$PS_PK_FP_REQUEST = 276,0,32,1 %; ! I Get permission to FastPath request. macro SPDT$PS_PK_FP_SEND = 280,0,32,1 %; ! I Start processing a FastPath SCSI command on device. macro SPDT$PS_PK_FP_FREE_RBUN = 284,0,32,1 %; ! I Deallocate FastPath buffer macro SPDT$PS_PK_FP_CMD_WAIT_COMP = 288,0,32,1 %; ! I Wait for the FastPath request to complete. macro SPDT$PS_PK_FP_KP_COMPLETION = 292,0,32,1 %; ! I Complete FastPath request in KP context [X-37] macro SPDT$PS_PK_ALLOC_POOL = 296,0,32,1 %; ! I Allocate non-paged pool (X-46) macro SPDT$PS_PK_FREE_POOL = 300,0,32,1 %; ! I Deallocate non-paged pool (X-46) macro SPDT$PS_PK_SCSI_COMMAND = 304,0,32,1 %; ! I SCSI command (X-46) macro SPDT$PS_PK_CANCEL = 308,0,32,1 %; ! I Cancel I/O on port macro SPDT$PS_PK_TRIGGER = 312,0,32,1 %; ! I Trigger analyzer ! X-46A1a macro SPDT$PS_PK_TARGET_DISCONNECT = 316,0,32,1 %; ! I Disconnect a target (STDT) ! If you add a vector here, update the symbol used to define PK_VECTOR_RESERVED below ! Dimension decremented from 10 to 9 for PK_FP_COMPLETION in X-37 ! Dimension decremented from 9 to 6 for PK_ALLOC_POOL, PK_FREE_POOL, and ! PK_SCSI_COMMAND in X-46 ! Dimension decremented from 6 to 5 for PK_CANCEL in X-47 ! Dimension decremented from 5 to 4 for PK_TRIGGER in X-50 ! Dimension decremented from 4 to 3 for PK_TARGET_DISCONNECT in X-50/X-46A1b macro SPDT$PS_PK_VECTORS = 216,0,0,1 %; literal SPDT$S_PK_VECTORS = 108; ! ! The "runtime library" entry point interface follows. These entry ! points are called by the port specific driver routines to perform ! support functions. ! macro SPDT$PS_RL_CHECK_CMDQ_STATUS = 332,0,32,1 %; ! I Check CMDQ status processing macro SPDT$PS_RL_CHECK_ONDECK_BLOCKED = 336,0,32,1 %; ! I Check if ONDECK_KPB is blocked macro SPDT$PS_RL_CMD_SLOT_ALLOC = 340,0,32,1 %; ! I Allocate a command slot macro SPDT$PS_RL_CMD_SLOT_DEALLOC = 344,0,32,1 %; ! I Deallocate a command slot macro SPDT$PS_RL_CREATE_PORT = 348,0,32,1 %; ! I Create a new SPDT for a new SCSI port macro SPDT$PS_RL_POOL_ALLOC = 352,0,32,1 %; ! I Allocate non-paged pool macro SPDT$PS_RL_POOL_ALLOC_PHYSICAL = 356,0,32,1 %; ! I Allocate non-paged pool of physically contigous memory macro SPDT$PS_RL_POOL_DEALLOC = 360,0,32,1 %; ! I Deallocate non-paged pool macro SPDT$PS_RL_INIT_SCDRP = 364,0,32,1 %; ! I Initialize SCDRP for port usage macro SPDT$PS_RL_TIMEOUT_SETUP_TQE = 368,0,32,1 %; ! I Initialize port timer macro SPDT$PS_RL_QUEUE_RESET_DIPL = 372,0,32,1 %; ! I Queue device reset from DIPL macro SPDT$PS_RL_QUEUE_RESET_FORK = 376,0,32,1 %; ! I Queue device reset from FORK macro SPDT$PS_RL_RESET_DETECTED_DIPL = 380,0,32,1 %; ! I Bus reset detected from DIPL macro SPDT$PS_RL_RESET_DETECTED_FORK = 384,0,32,1 %; ! I Bus reset detected from FORK macro SPDT$PS_RL_RESET_DETECTED_WAIT = 388,0,32,1 %; ! I Bus reset detected wait request ! ! Wait queues ! macro SPDT$L_PORT_WQFL = 432,0,32,1 %; ! F Port wait queue forward link macro SPDT$L_PORT_WQBL = 436,0,32,1 %; ! F Port wait queue backward link macro SPDT$L_WAITQFL = 440,0,32,1 %; ! F Listhead for fork blocks waiting macro SPDT$L_WAITQBL = 444,0,32,1 %; ! F For nonpaged pool macro SPDT$PS_RESET_WAIT_LIST = 448,0,32,1 %; ! D Single-Linked-List for bus reset waiters ! ! Related Port Data Structures. ! macro SPDT$L_ADP = 452,0,32,1 %; ! I Address of ADP macro SPDT$PS_CRAB = 456,0,32,1 %; ! I Address of CRAB macro SPDT$PS_PORT_CRAM = 460,0,32,1 %; ! I Address of CRAM macro SPDT$L_PORT_IDB = 464,0,32,1 %; ! I Address of port IDB. macro SPDT$L_PORT_UCB = 468,0,32,1 %; ! I Address of port UCB. macro SPDT$PS_ERL_SCDT = 472,0,32,1 %; ! F SCDT address for error logging operation macro SPDT$L_SCSI_DEBUG = 476,0,32,1 %; ! F SCSIDEBUG data structure pointer macro SPDT$PS_RBUN_LAL = 480,0,32,1 %; ! P X-48 Listhead for available RBUNs macro SPDT$L_RBUN_LAL_SEQNUM = 484,0,32,0 %; ! P Sequence number for RBUN_LAL macro SPDT$PS_QMAN_KPB = 488,0,32,1 %; ! F Queue manager's KPB address. macro SPDT$PS_CHIP_KPB = 492,0,32,1 %; ! S KPB address that owns the SCSI chip. macro SPDT$PS_ONDECK_KPB = 496,0,32,1 %; ! S KPB address that is waiting for the SCSI chip. macro SPDT$PS_SPL_PORT = 500,0,32,1 %; ! I Port spinlock address ! ! This TQE is used by the port driver to timeout pending disconnected IO's ! When this TQE expires, the timer thread will timeout expired pending IO's. ! macro SPDT$B_TQE = 504,0,0,0 %; literal SPDT$S_TQE = 64; ! F Timer queue entry macro SPDT$L_TQE_DELAY = 568,0,32,0 %; ! F Delay time for next TQE delay. ! ! Define the reset fork block ! macro SPDT$R_RESET_FKB = 576,0,0,0 %; literal SPDT$S_RESET_FKB = 48; ! I Embedded quadword aligned reset fork block ! ! Define a SCSI bus-reset-cleanup fork block ! macro SPDT$R_RESET_CLEANUP_FKB = 624,0,0,0 %; literal SPDT$S_RESET_CLEANUP_FKB = 48; ! I Embedded quadword aligned reset cleanup fork block ! ! Port specific DMA information. ! macro SPDT$L_DMA_BASE = 672,0,32,1 %; ! F Base address of DMA buffer macro SPDT$L_SPTE_BASE = 676,0,32,1 %; ! F S0 base address of buffer macro SPDT$L_SPTE_SVAPTE = 680,0,32,1 %; ! F SVAPTE of 1st SPTE used to double map macro SPDT$IS_EXTMAPREG = 684,0,32,0 %; ! F Extra (guard etc.) map regs needed macro SPDT$Q_READ_PAD_BA = 688,0,0,0 %; literal SPDT$S_READ_PAD_BA = 8; ! F Bus address of black hole page macro SPDT$Q_WRITE_PAD_BA = 696,0,0,0 %; literal SPDT$S_WRITE_PAD_BA = 8; ! F Bus address of erase page ! ! SCSI port event counters ! ! These counters are for events that are characteristic of the ! port not a connection and that don't need to be recorded on ! a connection by connection basis. ! macro SPDT$L_TARRST_CNT = 704,0,32,0 %; ! F Count of target initiated bus resets. macro SPDT$L_RETRY_CNT = 708,0,32,0 %; ! F Count of total number of retry attempts. macro SPDT$L_STRAY_INT_CNT = 712,0,32,0 %; ! F Count of interrupts when no owner of chan. macro SPDT$L_UNEXP_INT_CNT = 716,0,32,0 %; ! F Count of unexpected interrupts when chan owned. macro SPDT$L_NODISCON_CNT = 720,0,32,0 %; ! F Count of reselections when not disconnected. macro SPDT$IS_EVENT_CNT = 724,0,32,0 %; ! F Count number of events this interrupt. macro SPDT$IS_TOTAL_IO_COUNT = 728,0,32,1 %; ! F Total outstanding I/O count (DEVICE_QUEUE & PORT_QUEUE). macro SPDT$IS_PORT_IO_COUNT = 732,0,32,1 %; ! F Count of I/Os currently on all PORT_QUEUEs. macro SPDT$IS_DEV_IO_COUNT = 736,0,32,1 %; ! F Count of I/Os currently on all DEVICE_QUEUEs. macro SPDT$IS_QUEUE_SPINS = 740,0,32,1 %; ! F Number of loops through the queue manager. macro SPDT$IS_QUEUE_EXITS = 744,0,32,1 %; ! F Number of times the queue manager has exited. ! ! STDT hash table information. ! ! Number of bits in the hash value ! Changed from 3 to 4 for high SCSI Id's ! Starting position of those bits. macro SPDT$PS_STDT_HASH_TABLE = 748,0,0,1 %; literal SPDT$S_STDT_HASH_TABLE = 64; ! F STDT hash table. ! Command buffer slot information. ! ! The following fields are used to manage allocation of command ! buffer slots, for port drivers that require that concept. ! macro SPDT$PS_CMD_BASE = 812,0,32,1 %; ! I Base address of CMD buffers macro SPDT$PS_CMD_SPDT = 816,0,32,1 %; ! I The SPDT that manages command slots macro SPDT$PS_CMDWTFL = 820,0,32,1 %; ! F Wait queue forward pointer macro SPDT$PS_CMDWTBL = 824,0,32,1 %; ! F Wait queue backward pointer ! Total number of command slots. ! Total longwords for command slot allocation bit map. macro SPDT$IL_CMD_BITS = 828,0,0,0 %; ! F Command slot allocation bit map. ! Create max bus & bus config width for - ! high SCSI ID's macro SPDT$L_SCSI_BUS_WIDTHS = 860,0,32,0 %; ! F SCSI bus width related values macro SPDT$IW_MAX_BUS_WIDTH = 860,0,16,0 %; ! F Maximum supported by adapter macro SPDT$IW_CONFIG_BUS_WIDTH = 862,0,16,0 %; ! F Maximum supported as configured ! F macro SPDT$L_SCSI_AUTO_ID = 864,0,32,0 %; ! F SCSI ID of device for which LUN autoconfig is inhibited macro SPDT$PS_SPL_FORK = 868,0,32,1 %; ! I Fork spinlock address macro SPDT$L_FP_CDB_LENGTH = 872,0,32,1 %; ! CDB length supported on FastPath, 0 if variable macro SPDT$PS_FP_KPB_FKB = 876,0,32,1 %; ! Fork/wait block used to allocate & start FastPath KPBs macro SPDT$PS_FP_KPB_WQFL = 880,0,32,1 %; ! FastPath KPB Wait Queue forward link macro SPDT$PS_FP_KPB_WQBL = 884,0,32,1 %; ! FastPath KPB Wait Queue backward link ! ! Save some space for future expansion. Reserved to Digital, ALPHA/VMS development. ! macro SPDT$L_RSVD_LONG = 888,0,0,1 %; literal SPDT$S_RSVD_LONG = 12; ! F Port specific space that may be used for any purpose. ! ! Save some space for Port specific extensions. ! macro SPDT$L_PORT_SPECIFIC = 900,0,0,1 %; literal SPDT$S_PORT_SPECIFIC = 12; ! F Port specific space that may be used for any purpose. ! ! Define the length of this structure. ! macro SPDT$PS_FIRST_STDT = 912,0,32,1 %; ! F First STDT on which to to try to start I/O macro SPDT$PS_QDEPTH_TABLE = 916,0,32,1 %; ! F Address of a port-specific queue depth table macro SPDT$PS_PK_INTERCEPT = 920,0,32,1 %; ! I Intercepted class driver vectors macro SPDT$PS_CD_INTERCEPT = 924,0,32,1 %; ! I Intercepted port driver vectors macro SPDT$L_DEF_SPL_CTX = 928,0,32,1 %; ! I Default spinlock context macro SPDT$PS_SPL_DYN = 932,0,32,1 %; ! I Dynamic spinlock address !*** MODULE $LCKCTXDEF *** ! + ! LCKCTX - LOCK CONTEXT BLOCK ! ! - literal LCKCTX$M_BUSY = %X'1'; literal LCKCTX$M_CANCEL = %X'2'; literal LCKCTX$M_CMP_RQD = %X'4'; literal LCKCTX$K_LEN = 200; ! FIXED LENGTH literal LCKCTX$C_LEN = 200; ! FIXED LENGTH literal LCKCTX$S_LCKCTXDEF = 200; literal LCKCTX$S_LCKCTX = 200; macro LCKCTX$L_FQFL = 0,0,32,1 %; ! FORWARD LINK macro LCKCTX$L_FQBL = 4,0,32,1 %; ! BACKWARD LINK macro LCKCTX$W_SIZE = 8,0,16,0 %; ! SIZE macro LCKCTX$B_TYPE = 10,0,8,0 %; ! TYPE macro LCKCTX$B_FLCK = 11,0,8,0 %; ! FORK LOCK macro LCKCTX$L_FPC = 12,0,32,0 %; ! FORK PC macro LCKCTX$Q_FR3 = 16,0,0,1 %; literal LCKCTX$S_FR3 = 8; ! FORK R3 macro LCKCTX$Q_FR4 = 24,0,0,1 %; literal LCKCTX$S_FR4 = 8; ! FORK R4 macro LCKCTX$L_FLAGS = 32,0,32,0 %; ! FLAGS macro LCKCTX$V_BUSY = 32,0,1,0 %; ! BUSY macro LCKCTX$V_CANCEL = 32,1,1,0 %; ! OPERATION CANCELED macro LCKCTX$V_CMP_RQD = 32,2,1,0 %; ! COMPLETION REQUIRED macro LCKCTX$Q_LKB = 40,0,0,1 %; literal LCKCTX$S_LKB = 8; ! LKB ADDRESS macro LCKCTX$Q_CR3 = 48,0,0,0 %; literal LCKCTX$S_CR3 = 8; ! CALLER'S R3 macro LCKCTX$Q_CR4 = 56,0,0,0 %; literal LCKCTX$S_CR4 = 8; ! CALLER'S R4 macro LCKCTX$Q_CR5 = 64,0,0,0 %; literal LCKCTX$S_CR5 = 8; ! CALLER'S R5 macro LCKCTX$PQ_RET1 = 72,0,0,1 %; literal LCKCTX$S_RET1 = 8; ! STORAGE FOR SECOND RETURN macro LCKCTX$Q_TMP1 = 80,0,0,0 %; literal LCKCTX$S_TMP1 = 8; ! TEMPORARY STORAGE macro LCKCTX$PQ_CPLADR = 48,0,0,1 %; literal LCKCTX$S_CPLADR = 8; ! COMPLETION NOTIFICATION ADDR macro LCKCTX$Q_CPLPRM = 56,0,0,0 %; literal LCKCTX$S_CPLPRM = 8; ! CONTEXT PARAMETER macro LCKCTX$B_ARGS = 88,0,0,1 %; literal LCKCTX$S_ARGS = 112; ! WHOLE ARGUMENT LIST macro LCKCTX$Q_ENQ_LOCK_ACMODE = 88,0,0,0 %; literal LCKCTX$S_ENQ_LOCK_ACMODE = 8; macro LCKCTX$Q_ENQ_LKMODE = 96,0,0,0 %; literal LCKCTX$S_ENQ_LKMODE = 8; macro LCKCTX$Q_ENQ_LKSB = 104,0,0,0 %; literal LCKCTX$S_ENQ_LKSB = 8; macro LCKCTX$Q_ENQ_FLAGS = 112,0,0,0 %; literal LCKCTX$S_ENQ_FLAGS = 8; macro LCKCTX$Q_ENQ_RESNAM = 120,0,0,0 %; literal LCKCTX$S_ENQ_RESNAM = 8; macro LCKCTX$Q_ENQ_PARID = 128,0,0,0 %; literal LCKCTX$S_ENQ_PARID = 8; macro LCKCTX$Q_ENQ_CMP_ADR = 136,0,0,0 %; literal LCKCTX$S_ENQ_CMP_ADR = 8; macro LCKCTX$Q_ENQ_CTX_PRM1 = 144,0,0,0 %; literal LCKCTX$S_ENQ_CTX_PRM1 = 8; macro LCKCTX$Q_ENQ_CTX_PRM2 = 152,0,0,0 %; literal LCKCTX$S_ENQ_CTX_PRM2 = 8; macro LCKCTX$Q_ENQ_CTX_PRM3 = 160,0,0,0 %; literal LCKCTX$S_ENQ_CTX_PRM3 = 8; macro LCKCTX$Q_ENQ_BLK_ADR = 168,0,0,0 %; literal LCKCTX$S_ENQ_BLK_ADR = 8; macro LCKCTX$Q_ENQ_NAME_ACMODE = 176,0,0,0 %; literal LCKCTX$S_ENQ_NAME_ACMODE = 8; macro LCKCTX$Q_ENQ_PRIORITY = 184,0,0,0 %; literal LCKCTX$S_ENQ_PRIORITY = 8; macro LCKCTX$PQ_ENQ_REQ_ACPTED_ADR = 192,0,0,1 %; literal LCKCTX$S_ENQ_REQ_ACPTED_ADR = 8; macro LCKCTX$Q_DEQ_LOCKID = 88,0,0,0 %; literal LCKCTX$S_DEQ_LOCKID = 8; macro LCKCTX$Q_DEQ_VALBLK = 96,0,0,0 %; literal LCKCTX$S_DEQ_VALBLK = 8; macro LCKCTX$Q_DEQ_FLAGS = 104,0,0,0 %; literal LCKCTX$S_DEQ_FLAGS = 8; macro LCKCTX$Q_DEQ_CTX_PRM1 = 112,0,0,0 %; literal LCKCTX$S_DEQ_CTX_PRM1 = 8; macro LCKCTX$Q_DEQ_CTX_PRM2 = 120,0,0,0 %; literal LCKCTX$S_DEQ_CTX_PRM2 = 8; macro LCKCTX$Q_DEQ_CTX_PRM3 = 128,0,0,0 %; literal LCKCTX$S_DEQ_CTX_PRM3 = 8; macro LCKCTX$PQ_DEQ_RETADR = 136,0,0,1 %; literal LCKCTX$S_DEQ_RETADR = 8; ! DEQ arguments must not ! overlap ENQ_CTX_PRM2 or later !*** MODULE $CPUDEF *** ! + ! structure that defines a single octaword FP value ! - literal CPU$S_BC_FPREG = 16; macro CPU$Q_BC_FP = 0,0,0,0 %; literal CPU$S_BC_FP = 16; ! + ! ! Per-CPU Database definitions. One of these structures exists for ! each CPU that is participating in symmetric multiprocessing. ! ! The per-CPU database consists of 2 parts. A fixed portion that exists ! for any CPU type is defined first. A variable portion is also defined as ! necessary for various CPU types. The contents of the variable portion ! are CPU-specific. ! ! When creating a per-CPU database, one must allocate space to include ! both the fixed portion and a variable portion that is specific to the ! CPU type for which the database is being created. ! ! - literal CPU$C_RESERVED = 0; ! Zero is reserved literal CPU$C_INIT = 1; ! CPU is being INITialized literal CPU$C_RUN = 2; ! CPU is RUNning literal CPU$C_STOPPING = 3; ! CPU is STOPping literal CPU$C_STOPPED = 4; ! CPU is STOPPED literal CPU$C_TIMOUT = 5; ! Boot of CPU timed out literal CPU$C_BOOT_REJECTED = 6; ! CPU refuses to join SMP literal CPU$C_BOOTED = 7; ! CPU booted - waiting for "go" literal CPU$C_NOT_CONFIGURED = 8; ! CPU exists, but not in configure set literal CPU$C_POWERED_DOWN = 9; ! CPU in configure set, but powered down literal CPU$C_DEALLOCATED = 10; ! CPU has been deallocated literal CPU$M_INV_TBS = %X'1'; literal CPU$M_INV_TBA = %X'2'; literal CPU$M_BUGCHK = %X'4'; literal CPU$M_BUGCHKACK = %X'8'; literal CPU$M_RECALSCHD = %X'10'; literal CPU$M_UPDASTSR = %X'20'; literal CPU$M_UPDATE_HWCLOCK = %X'40'; literal CPU$M_WORK_FQP = %X'80'; literal CPU$M_QLOST = %X'100'; literal CPU$M_RESCHED = %X'200'; literal CPU$M_VIRTCONS = %X'400'; literal CPU$M_IOPOST = %X'800'; literal CPU$M_INV_ISTREAM = %X'1000'; literal CPU$M_INV_TBSD = %X'2000'; literal CPU$M_INV_TBS_MMG = %X'4000'; literal CPU$M_INV_TBSD_MMG = %X'8000'; literal CPU$M_IO_INT_AFF = %X'10000'; literal CPU$M_IO_START_AFF = %X'20000'; literal CPU$M_UPDATE_SYSPTBR = %X'40000'; literal CPU$M_PERFMON = %X'80000'; literal CPU$M_READ_SCC = %X'100000'; literal CPU$M_CPUFILL_1 = %X'FFFFFFF'; literal CPU$M_CPUSPEC1 = %X'10000000'; literal CPU$M_CPUSPEC2 = %X'20000000'; literal CPU$M_CPUSPEC3 = %X'40000000'; literal CPU$M_CPUSPEC4 = %X'80000000'; literal CPU$K_NUM_SWIQS = 6; ! Number of software interrupt queues literal CPU$M_SYS_ASTEN = %X'F'; literal CPU$M_SYS_ASTSR = %X'F0'; literal CPU$M_SYS_UP = %X'4'; literal CPU$M_SYS_AC = %X'8'; literal CPU$M_SYS_MFL = %X'10'; literal CPU$M_SYS_MFH = %X'20'; literal CPU$M_DFH = %X'80000'; literal CPU$C_HWPCBLEN = 384; ! Length of HWPCB in 128 bytes literal CPU$K_HWPCBLEN = 384; ! Length of HWPCB in 128 bytes literal CPU$M_TERM_ASTEN = %X'F'; literal CPU$M_TERM_ASTSR = %X'F0'; literal CPU$M_TERM_UP = %X'4'; literal CPU$M_TERM_AC = %X'8'; literal CPU$M_TERM_MFL = %X'10'; literal CPU$M_TERM_MFH = %X'20'; literal CPU$M_TERM_DFH = %X'80000'; literal CPU$M_BC_AST_MFL = %X'1'; literal CPU$M_BC_AST_MFH = %X'2'; literal CPU$M_BC_AST_PSR_MFL = %X'4'; literal CPU$M_BC_AST_PSR_MFH = %X'8'; literal CPU$M_BC_AST_CALLED = %X'10'; literal CPU$M_SCHED = %X'1'; literal CPU$M_FOREVER = %X'2'; literal CPU$M_NEWPRIM = %X'4'; literal CPU$M_PSWITCH = %X'8'; literal CPU$M_BC_STACK = %X'10'; literal CPU$M_BC_CONTEXT = %X'20'; literal CPU$M_USER_CAPABILITIES_SET = %X'40'; literal CPU$M_RESET_LOW_POWER = %X'80'; literal CPU$M_STOPPING = %X'1'; literal CPU$M_PCSAMPLE_ACTIVE = %X'1'; literal CPU$M_IO_AFF_FKB_INUSE = %X'1'; literal CPU$M_PORT_ASSIGNED = %X'2'; literal CPU$M_DISTRIBUTED_INTS = %X'4'; literal CPU$M_LASTPAGE_TESTED = %X'20000000'; literal CPU$M_MCHECK = %X'40000000'; literal CPU$M_MEMORY_WRITE = %X'80000000'; literal CPU$M_AUTO_START = %X'1'; literal CPU$M_NOBINDINGS = %X'2'; literal CPU$K_BC_SWIS_1_LENGTH = 328; literal CPU$K_BC_SWIS_2_LENGTH = 72; literal CPU$S_CPU = 7672; macro CPU$L_CURPCB = 0,0,32,1 %; ! Address of CPU's current PCB macro CPU$L_CURKTB = 0,0,32,1 %; ! Address of CPU's current KTB macro CPU$L_SLOT_VA = 4,0,32,1 %; ! Address of CPU's HWRPB slot macro CPU$W_SIZE = 8,0,16,0 %; ! Structure size macro CPU$B_TYPE = 10,0,8,0 %; ! Structure type macro CPU$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro CPU$L_STATE = 12,0,32,0 %; ! State of this processor macro CPU$L_CPUMTX = 16,0,32,0 %; ! Count of CPUMTX acquires macro CPU$L_CUR_PRI = 20,0,32,0 %; ! Current Process Priority ! ! CPU type independent work request bits ! macro CPU$L_WORK_REQ = 24,0,32,0 %; ! Work request bitmask macro CPU$V_INV_TBS = 24,0,1,0 %; ! Invalidate TB single macro CPU$V_INV_TBA = 24,1,1,0 %; ! Invalidate TB all macro CPU$V_BUGCHK = 24,2,1,0 %; ! BUG_CHECK requested macro CPU$V_BUGCHKACK = 24,3,1,0 %; ! BUG_CHECK acked macro CPU$V_RECALSCHD = 24,4,1,0 %; ! Recalculate per cpu mask,reschedule macro CPU$V_UPDASTSR = 24,5,1,0 %; ! Update ASTSR register macro CPU$V_UPDATE_HWCLOCK = 24,6,1,0 %; ! Update local hardware clocks macro CPU$V_WORK_FQP = 24,7,1,0 %; ! Process work queue macro CPU$V_QLOST = 24,8,1,0 %; ! Stall until quorum regained macro CPU$V_RESCHED = 24,9,1,0 %; ! Issue IPL 3 SOFTINT macro CPU$V_VIRTCONS = 24,10,1,0 %; ! Enter virtual console mode (primary) macro CPU$V_IOPOST = 24,11,1,0 %; ! Issue IPL 4 SOFTINT macro CPU$V_INV_ISTREAM = 24,12,1,0 %; ! Invalidate cached instruction stream macro CPU$V_INV_TBSD = 24,13,1,0 %; ! Invalidate data TB single macro CPU$V_INV_TBS_MMG = 24,14,1,0 %; ! Invalidate TB single MMG synchronized macro CPU$V_INV_TBSD_MMG = 24,15,1,0 %; ! Invalidate TB single MMG synchronized macro CPU$V_IO_INT_AFF = 24,16,1,0 %; ! Fast Path I/O completion event macro CPU$V_IO_START_AFF = 24,17,1,0 %; ! Fast Path I/O start event macro CPU$V_UPDATE_SYSPTBR = 24,18,1,0 %; ! Update SYSPTBR register macro CPU$V_PERFMON = 24,19,1,0 %; ! Performance Monitoring macro CPU$V_READ_SCC = 24,20,1,0 %; ! Read SCC ! ! Define 4 CPU type specific work request bits as bit #s 28-31. ! macro CPU$V_CPUSPEC1 = 24,28,1,0 %; ! CPU specific macro CPU$V_CPUSPEC2 = 24,29,1,0 %; ! CPU specific macro CPU$V_CPUSPEC3 = 24,30,1,0 %; ! CPU specific macro CPU$V_CPUSPEC4 = 24,31,1,0 %; ! CPU specific ! macro CPU$L_PHY_CPUID = 28,0,32,0 %; ! CPU ID number macro CPU$L_BUSYWAIT = 36,0,32,0 %; ! <>0 = Spinning for lock ! macro CPU$Q_SWIQFL = 40,0,0,1 %; literal CPU$S_SWIQFL = 48; ! Software interrupt queues macro CPU$L_PSFL = 88,0,32,1 %; ! POST QUEUE forward link macro CPU$L_PSBL = 92,0,32,1 %; ! POST QUEUE backward link macro CPU$Q_WORK_FQFL = 96,0,0,0 %; literal CPU$S_WORK_FQFL = 8; ! Work packet queue macro CPU$Q_WORK_IFQ = 96,0,0,0 %; literal CPU$S_WORK_IFQ = 8; ! Work packet queue ! macro CPU$L_ZEROED_PAGE_SPTE = 104,0,32,1 %; ! SPTE address macro CPU$L_ZEROED_PAGE_VA = 108,0,32,1 %; ! VA for zeroed page filling macro CPU$Q_ZEROED_PAGE_STATE = 112,0,0,1 %; literal CPU$S_ZEROED_PAGE_STATE = 8; ! State for interrupted filling ! ****************************************************************** ! HWPCB for this CPU's dedicated System Process ! ! This Hardware Privileged Context Block provides the context for when this ! CPU has no other process to run. ! ! NOTE WELL: This HWPCB must be aligned to a 128 byte boundary, the ! architected natural alignment of a HWPCB. ! ! NOTE WELL: There are bit symbols defined here for accessing the saved ASTEN, ! ASTSR, FEN and DATFX values in the HWPCB. These symbols are NOT to be used when ! interfacing to the ASTEN, ASTSR, FEN or DATFX internal processor registers directly. ! See the specific internal register definitions for bitmasks and constants ! to be used when interfacing to the IPRs directly. ! macro CPU$Q_PHY_SYS_HWPCB = 120,0,0,0 %; literal CPU$S_PHY_SYS_HWPCB = 8; ! Physical address of HWPCB ! Start of aligned section macro CPU$Q_SYS_HWPCB = 128,0,0,0 %; literal CPU$S_SYS_HWPCB = 8; ! Base of HWPCB macro CPU$Q_SYS_KSP = 128,0,0,0 %; literal CPU$S_SYS_KSP = 8; ! Kernel stack pointer macro CPU$Q_SYS_ESP = 136,0,0,0 %; literal CPU$S_SYS_ESP = 8; ! Executive stack pointer macro CPU$Q_SYS_SSP = 144,0,0,0 %; literal CPU$S_SYS_SSP = 8; ! Supervisor stack pointer macro CPU$Q_SYS_USP = 152,0,0,0 %; literal CPU$S_SYS_USP = 8; ! User stack pointer ! Verified for IA64 port - JCH macro CPU$Q_SYS_KPFS = 160,0,0,0 %; literal CPU$S_SYS_KPFS = 8; ! PFS of thread switched out macro CPU$Q_SYS_KRNAT = 168,0,0,0 %; literal CPU$S_SYS_KRNAT = 8; ! RNAT of thread switched out macro CPU$PQ_SYS_KBSP = 176,0,0,1 %; literal CPU$S_SYS_KBSP = 8; ! Kernel Backing Store Pointer macro CPU$PQ_SYS_EBSP = 184,0,0,1 %; literal CPU$S_SYS_EBSP = 8; ! Exec Backing Store Pointer macro CPU$PQ_SYS_SBSP = 192,0,0,1 %; literal CPU$S_SYS_SBSP = 8; ! Supervisor Backing Store Pointer macro CPU$PQ_SYS_UBSP = 200,0,0,1 %; literal CPU$S_SYS_UBSP = 8; ! User Backing Store Pointer macro CPU$Q_SYS_PTBR = 208,0,0,0 %; literal CPU$S_SYS_PTBR = 128; ! Page Table PFN (Only vrnx 15 is used) macro CPU$Q_SYS_ASN = 336,0,0,0 %; literal CPU$S_SYS_ASN = 64; ! ASN/Region ID (Only vrn 7 is used) macro CPU$Q_SYS_ASTSR_ASTEN = 400,0,0,0 %; literal CPU$S_SYS_ASTSR_ASTEN = 8; ! ASTSR / ASTEN quadword macro CPU$V_SYS_ASTEN = 400,0,4,0 %; literal CPU$S_SYS_ASTEN = 4; ! AST Enable Register macro CPU$V_SYS_ASTSR = 400,4,4,0 %; literal CPU$S_SYS_ASTSR = 4; ! AST Pending Summary Register ! Process Attributes Section replaces Alpha FEN quadword macro CPU$IQ_SYS_PAS = 408,0,0,0 %; literal CPU$S_SYS_PAS = 8; ! Floating Point Disable / modified / PME / DATFX macro CPU$IL_SYS_PAS_L = 408,0,32,0 %; macro CPU$IL_SYS_PAS_H = 412,0,32,0 %; macro CPU$V_SYS_UP = 408,2,1,0 %; ! User Performance Monitor Enable macro CPU$V_SYS_AC = 408,3,1,0 %; ! Data Alignment Check Enable macro CPU$V_SYS_MFL = 408,4,1,0 %; ! Low FPRs modified macro CPU$V_SYS_MFH = 408,5,1,0 %; ! High FPRs modified macro CPU$V_DFH = 408,19,1,0 %; ! High Floating Point Disable ! sys_fill_44 bitfield length 44 fill; macro CPU$Q_SYS_CC = 416,0,0,0 %; literal CPU$S_SYS_CC = 8; ! Cycle Counter macro CPU$Q_UNQ = 424,0,0,0 %; literal CPU$S_UNQ = 8; macro CPU$B_SYS_PMOD = 432,0,8,0 %; macro CPU$b_sys_reserved_1 = 433,0,0,1 %; literal CPU$s_sys_reserved_1 = 7; macro CPU$Q_SYS_PAL_RSVD = 440,0,0,1 %; literal CPU$S_SYS_PAL_RSVD = 40; ! ! End of Hardware Privileged Context Block (HWPCB) for the system process ! ! ****************************************************************** ! ****************************************************************** ! HWPCB for this CPU's Terminating Process. ! ! This Hardware Privileged Context Block provides the context for when this ! CPU needs a place to run when a powerfail may, unexpectedly, happen. ! ! Remember, when a process's HWPCB is loaded (active on the CPU) the contents ! of the HWPCB are undefined since the processor may use that area as ! scratch space. All code paths that execute higher than IPL IPL$_POWER-2 (29) ! for an extended period of time may need to execute in the context of this ! process. Currently this includes most code surrounding powerfail/restart ! and parts of SMP$START_SECONDARY. ! ! NOTE WELL: This HWPCB must be aligned to a 128 byte boundary, the ! architected natural alignment of a HWPCB. ! ! NOTE WELL: There are bit symbols defined here for accessing the saved ASTEN, ! ASTSR, FEN and DATFX values in the HWPCB. These symbols are NOT to be used when ! interfacing to the ASTEN, ASTSR, FEN or DATFX internal processor registers directly. ! See the specific internal register definitions for bitmasks and constants ! to be used when interfacing to the IPRs directly. ! ! Start of aligned section macro CPU$Q_TERM_HWPCB = 512,0,0,0 %; literal CPU$S_TERM_HWPCB = 8; ! Base of HWPCB macro CPU$Q_TERM_KSP = 512,0,0,0 %; literal CPU$S_TERM_KSP = 8; ! Kernel stack pointer macro CPU$Q_TERM_ESP = 520,0,0,0 %; literal CPU$S_TERM_ESP = 8; ! Executive stack pointer macro CPU$Q_TERM_SSP = 528,0,0,0 %; literal CPU$S_TERM_SSP = 8; ! Supervisor stack pointer macro CPU$Q_TERM_USP = 536,0,0,0 %; literal CPU$S_TERM_USP = 8; ! User stack pointer ! Verified for IA64 port - JCH macro CPU$Q_TERM_KPFS = 544,0,0,0 %; literal CPU$S_TERM_KPFS = 8; ! PFS of thread switched out macro CPU$Q_TERM_KRNAT = 552,0,0,0 %; literal CPU$S_TERM_KRNAT = 8; ! RNAT of thread switched out macro CPU$PQ_TERM_KBSP = 560,0,0,1 %; literal CPU$S_TERM_KBSP = 8; ! Kernel Backing Store Pointer macro CPU$PQ_TERM_EBSP = 568,0,0,1 %; literal CPU$S_TERM_EBSP = 8; ! Exec Backing Store Pointer macro CPU$PQ_TERM_SBSP = 576,0,0,1 %; literal CPU$S_TERM_SBSP = 8; ! Supervisor Backing Store Pointer macro CPU$PQ_TERM_UBSP = 584,0,0,1 %; literal CPU$S_TERM_UBSP = 8; ! User Backing Store Pointer macro CPU$Q_TERM_PTBR = 592,0,0,0 %; literal CPU$S_TERM_PTBR = 128; ! Page Table PFN (Only vrnx 15 is used) macro CPU$Q_TERM_ASN = 720,0,0,0 %; literal CPU$S_TERM_ASN = 64; ! ASN/Region ID (Only vrn 7 is used) macro CPU$Q_TERM_ASTSR_ASTEN = 784,0,0,0 %; literal CPU$S_TERM_ASTSR_ASTEN = 8; ! ASTSR / ASTEN quadword macro CPU$V_TERM_ASTEN = 784,0,4,0 %; literal CPU$S_TERM_ASTEN = 4; ! AST Enable Register macro CPU$V_TERM_ASTSR = 784,4,4,0 %; literal CPU$S_TERM_ASTSR = 4; ! AST Pending Summary Register ! Process Attributes Section replaces Alpha FEN quadword macro CPU$IQ_TERM_PAS = 792,0,0,0 %; literal CPU$S_TERM_PAS = 8; ! Floating Point Disable / modified / PME / DATFX macro CPU$IL_TERM_PAS_L = 792,0,32,0 %; macro CPU$IL_TERM_PAS_H = 796,0,32,0 %; macro CPU$V_TERM_UP = 792,2,1,0 %; ! User Performance Monitor Enable macro CPU$V_TERM_AC = 792,3,1,0 %; ! Data Alignment Check Enable macro CPU$V_TERM_MFL = 792,4,1,0 %; ! Low FPRs modified macro CPU$V_TERM_MFH = 792,5,1,0 %; ! High FPRs modified macro CPU$V_TERM_DFH = 792,19,1,0 %; ! High Floating Point Disable ! term_fill_44 bitfield length 44 fill; macro CPU$Q_TERM_CC = 800,0,0,0 %; literal CPU$S_TERM_CC = 8; ! Cycle Counter macro CPU$Q_TERM_UNQ = 808,0,0,0 %; literal CPU$S_TERM_UNQ = 8; ! Process Unique Value macro CPU$B_TERM_PMOD = 816,0,8,0 %; macro CPU$b_term_reserved_1 = 817,0,0,1 %; literal CPU$s_term_reserved_1 = 7; macro CPU$Q_TERM_PAL_RSVD = 824,0,0,1 %; literal CPU$S_TERM_PAL_RSVD = 40; ! ! End of aligned portion of HWPCB. Next quadword is used so we don't need to ! convert a virtual address to a physical address every time we use the terminating ! process. ! macro CPU$Q_PHY_TERM_HWPCB = 896,0,0,0 %; literal CPU$S_PHY_TERM_HWPCB = 8; ! Physical address of HWPCB ! ! End of Hardware Privileged Context Block (HWPCB) for the terminating process ! ! ****************************************************************** ! ! Per-CPU state saved during powerfail interrupt processing. The state ! that is saved here is process independent, yet specific to this CPU. ! macro CPU$Q_SAVED_PCBB = 904,0,0,0 %; literal CPU$S_SAVED_PCBB = 8; ! PCBB from powerdown (non-zero ! if state successfully saved) macro CPU$Q_SCBB = 912,0,0,0 %; literal CPU$S_SCBB = 8; ! SCBB from powerdown macro CPU$Q_SISR = 920,0,0,0 %; literal CPU$S_SISR = 8; ! SISR from powerdown ! ****************************************************************** ! The following storage is used by BUGCHECK code. The order must be ! preserved since it is assumed by a table within SDA (see $CRASHDEF ! in [SDA]EVAX_SDADEF.SDL). ! macro CPU$Q_BC_KSP = 928,0,0,0 %; literal CPU$S_BC_KSP = 8; ! Stored KSP macro CPU$Q_BC_ESP = 936,0,0,0 %; literal CPU$S_BC_ESP = 8; ! Stored ESP macro CPU$Q_BC_SSP = 944,0,0,0 %; literal CPU$S_BC_SSP = 8; ! Stored SSP macro CPU$Q_BC_USP = 952,0,0,0 %; literal CPU$S_BC_USP = 8; ! Stored USP macro CPU$Q_BC_PTBR = 960,0,0,0 %; literal CPU$S_BC_PTBR = 128; ! Stored PTBR macro CPU$Q_BC_ASN = 1088,0,0,0 %; literal CPU$S_BC_ASN = 64; ! Stored ASN macro CPU$Q_BC_ASTSR_ASTEN = 1152,0,0,0 %; literal CPU$S_BC_ASTSR_ASTEN = 8; ! Stored AST SR and EN macro CPU$Q_BC_FEN = 1160,0,0,0 %; literal CPU$S_BC_FEN = 8; ! Stored FEN / UP / AC macro CPU$Q_BC_CC = 1168,0,0,0 %; literal CPU$S_BC_CC = 8; ! Stored CC macro CPU$Q_BC_UNQ = 1176,0,0,0 %; literal CPU$S_BC_UNQ = 8; ! Thread pointer (r13) macro CPU$B_BC_PMOD = 1184,0,8,0 %; ! Previous mode macro CPU$b_bc_reserved_1 = 1185,0,0,1 %; literal CPU$s_bc_reserved_1 = 7; macro CPU$Q_BC_PAL_RSVD = 1192,0,0,1 %; literal CPU$S_BC_PAL_RSVD = 40; ! PAL reserved area macro CPU$B_BC_FLAGS = 1232,0,8,1 %; macro CPU$R_BC_FLAG_BITS = 1232,0,8,0 %; macro CPU$V_BC_AST_MFL = 1232,0,1,0 %; ! F12-F15 have been saved in AST_Fxx fields below macro CPU$V_BC_AST_MFH = 1232,1,1,0 %; ! Upper floating regs have been saved in a separate structure following this one macro CPU$V_BC_AST_PSR_MFL = 1232,2,1,0 %; ! Saved PSR.mfl bit macro CPU$V_BC_AST_PSR_MFH = 1232,3,1,0 %; ! Saved PSR.mfl bit macro CPU$V_BC_AST_CALLED = 1232,4,1,0 %; ! ASTDEL has been called at least once with this frame macro CPU$B_BC_PPREVMODE = 1233,0,8,0 %; ! Save interrupted context's PREVMODE macro CPU$B_BC_PREVSTACK = 1234,0,8,0 %; ! What mode of stack (register and memory) do we return to? ! Note: The OS must prevent interruptions any time the register ! stack and memory stack are different modes macro CPU$B_BC_IPL = 1235,0,8,0 %; ! SWIS IPL state macro CPU$L_BC_STKALIGN = 1236,0,32,0 %; ! How much allocated on this stack for int frame? Guaranteed that ! STKALIGN & 0XFFF0 is the actual length of the structure. In other ! words, the structure is always allocated on a 16-byte boundary is ! is a multiple of 16-bytes long. macro CPU$W_BC_NATMASK = 1240,0,16,0 %; ! Mask of bits 3-9 of the interrupt frame when ! it was created. This shows the mapping ! between UNAT bits and registers. Used to calculate ! how to change the NAT save if interrupt frame is moved macro CPU$B_BC_TYPE = 1242,0,8,0 %; ! Make this structure look like a standard VMS structure macro CPU$B_BC_SUBTYPE = 1243,0,8,0 %; macro CPU$L_BC_TRAP_TYPE = 1244,0,32,0 %; ! Trap type macro CPU$Q_BC_IIP = 1248,0,0,0 %; literal CPU$S_BC_IIP = 8; ! Interruption Instr. Pointer (CR19) ! ! Register Stack Information ! macro CPU$Q_BC_RSC = 1256,0,0,0 %; literal CPU$S_BC_RSC = 8; ! Register Stack Control register macro CPU$Q_BC_BSP = 1264,0,0,0 %; literal CPU$S_BC_BSP = 8; ! (Kernel) Backing store pointer macro CPU$Q_BC_BSPSTORE = 1272,0,0,0 %; literal CPU$S_BC_BSPSTORE = 8; ! BSP store pointer for next spill macro CPU$Q_BC_RNAT = 1280,0,0,0 %; literal CPU$S_BC_RNAT = 8; ! RNAT register macro CPU$Q_BC_BSPBASE = 1288,0,0,0 %; literal CPU$S_BC_BSPBASE = 8; ! Base of backing store for the inner mode (used for loadrs) macro CPU$Q_BC_PFS = 1296,0,0,0 %; literal CPU$S_BC_PFS = 8; ! Previous function state ! ! Bookkeeping Info ! macro CPU$Q_BC_CONTEXT = 1304,0,0,0 %; literal CPU$S_BC_CONTEXT = 8; ! Opaque context left by trap handler to speed ! processing on the way out. If the interrupt frame is ! moved or if the return will be from a different mode, ! this quadword must be cleared. macro CPU$Q_BC_PAL_RESERVED_1 = 1312,0,0,1 %; literal CPU$S_BC_PAL_RESERVED_1 = 8; ! For the moment, not used macro CPU$Q_BC_AST_F12 = 1328,0,0,0 %; literal CPU$S_BC_AST_F12 = 16; ! f12 - temporary FP register; sometimes saved by AST macro CPU$Q_BC_AST_F13 = 1344,0,0,0 %; literal CPU$S_BC_AST_F13 = 16; ! f12 - temporary FP register; sometimes saved by AST macro CPU$Q_BC_AST_F14 = 1360,0,0,0 %; literal CPU$S_BC_AST_F14 = 16; ! f12 - temporary FP register; sometimes saved by AST macro CPU$Q_BC_AST_F15 = 1376,0,0,0 %; literal CPU$S_BC_AST_F15 = 16; ! f12 - temporary FP register; sometimes saved by AST ! End of overlay between Interrupt Frame and System Service Entry structures macro CPU$Q_BC_PREDS = 1392,0,0,0 %; literal CPU$S_BC_PREDS = 8; ! Predication registers ! ! Interrupt resources ! macro CPU$Q_BC_IPSR = 1400,0,0,0 %; literal CPU$S_BC_IPSR = 8; ! Interruption Processor Status (CR16) macro CPU$Q_BC_ISR = 1408,0,0,0 %; literal CPU$S_BC_ISR = 8; ! Interruption Status Register (CR17) macro CPU$Q_BC_CR18 = 1416,0,0,0 %; literal CPU$S_BC_CR18 = 8; ! Reserved control register macro CPU$Q_BC_IFA = 1424,0,0,0 %; literal CPU$S_BC_IFA = 8; ! Interruption Fault Address (CR20) macro CPU$Q_BC_ITIR = 1432,0,0,0 %; literal CPU$S_BC_ITIR = 8; ! Interruption TLB Insertion Register (CR21) macro CPU$Q_BC_IIPA = 1440,0,0,0 %; literal CPU$S_BC_IIPA = 8; ! Interruption immediate register (CR22) macro CPU$Q_BC_IFS = 1448,0,0,0 %; literal CPU$S_BC_IFS = 8; ! Interruption Function State (CR23) macro CPU$Q_BC_IIM = 1456,0,0,0 %; literal CPU$S_BC_IIM = 8; ! Interruption immediate (CR24) macro CPU$Q_BC_IHA = 1464,0,0,0 %; literal CPU$S_BC_IHA = 8; ! Interruption Hash Address (CR25) ! ! Application register state ! macro CPU$Q_BC_UNAT = 1472,0,0,0 %; literal CPU$S_BC_UNAT = 8; ! User NAT collection register macro CPU$Q_BC_CCV = 1480,0,0,0 %; literal CPU$S_BC_CCV = 8; ! CCV register macro CPU$Q_BC_DCR = 1488,0,0,0 %; literal CPU$S_BC_DCR = 8; ! Default control register macro CPU$Q_BC_LC = 1496,0,0,0 %; literal CPU$S_BC_LC = 8; ! Loop counter macro CPU$Q_BC_EC = 1504,0,0,0 %; literal CPU$S_BC_EC = 8; ! Epilogue counter (preserved, not saved by interrupt) macro CPU$Q_BC_NATS = 1512,0,0,0 %; literal CPU$S_BC_NATS = 8; ! NATs for registers saved in this structure ! ! Volatile and preserved integer registers. We need to preserve the preserved regs ! not so much to save their values, but to save their NATs ! macro CPU$Q_BC_REGBASE = 1520,0,0,0 %; literal CPU$S_BC_REGBASE = 8; ! Unused. Used to index into registers macro CPU$Q_BC_GP = 1528,0,0,0 %; literal CPU$S_BC_GP = 8; ! r1 - Used as global pointer macro CPU$Q_BC_R2 = 1536,0,0,0 %; literal CPU$S_BC_R2 = 8; ! r2 - temporary register macro CPU$Q_BC_R3 = 1544,0,0,0 %; literal CPU$S_BC_R3 = 8; ! r3 - temporary register macro CPU$Q_BC_R4 = 1552,0,0,0 %; literal CPU$S_BC_R4 = 8; ! r4 - preserved register (not saved by interrupt) macro CPU$Q_BC_R5 = 1560,0,0,0 %; literal CPU$S_BC_R5 = 8; ! r5 - preserved register (not saved by interrupt) macro CPU$Q_BC_R6 = 1568,0,0,0 %; literal CPU$S_BC_R6 = 8; ! r6 - preserved register (not saved by interrupt) macro CPU$Q_BC_R7 = 1576,0,0,0 %; literal CPU$S_BC_R7 = 8; ! r7 - preserved register (not saved by interrupt) macro CPU$Q_BC_R8 = 1584,0,0,0 %; literal CPU$S_BC_R8 = 8; ! r8 - return value macro CPU$Q_BC_R9 = 1592,0,0,0 %; literal CPU$S_BC_R9 = 8; ! r9 - argument pointer macro CPU$Q_BC_R10 = 1600,0,0,0 %; literal CPU$S_BC_R10 = 8; ! r10 - temporary register macro CPU$Q_BC_R11 = 1608,0,0,0 %; literal CPU$S_BC_R11 = 8; ! r11 - temporary register macro CPU$Q_BC_SP_CELL = 1616,0,0,0 %; literal CPU$S_BC_SP_CELL = 8; ! SP is actually saved in IPRs. Leave this so NATs remain lined up macro CPU$Q_BC_R13 = 1624,0,0,0 %; literal CPU$S_BC_R13 = 8; ! r13 - Thread Pointer macro CPU$Q_BC_R14 = 1632,0,0,0 %; literal CPU$S_BC_R14 = 8; ! r14 - temporary register macro CPU$Q_BC_R15 = 1640,0,0,0 %; literal CPU$S_BC_R15 = 8; ! r15 - temporary register macro CPU$Q_BC_R16 = 1648,0,0,0 %; literal CPU$S_BC_R16 = 8; ! r16 - temporary register macro CPU$Q_BC_R17 = 1656,0,0,0 %; literal CPU$S_BC_R17 = 8; ! r17 - temporary register macro CPU$Q_BC_R18 = 1664,0,0,0 %; literal CPU$S_BC_R18 = 8; ! r18 - temporary register macro CPU$Q_BC_R19 = 1672,0,0,0 %; literal CPU$S_BC_R19 = 8; ! r19 - temporary register macro CPU$Q_BC_R20 = 1680,0,0,0 %; literal CPU$S_BC_R20 = 8; ! r20 - temporary register macro CPU$Q_BC_R21 = 1688,0,0,0 %; literal CPU$S_BC_R21 = 8; ! r21 - temporary register macro CPU$Q_BC_R22 = 1696,0,0,0 %; literal CPU$S_BC_R22 = 8; ! r22 - temporary register macro CPU$Q_BC_R23 = 1704,0,0,0 %; literal CPU$S_BC_R23 = 8; ! r23 - temporary register macro CPU$Q_BC_R24 = 1712,0,0,0 %; literal CPU$S_BC_R24 = 8; ! r24 - temporary register macro CPU$Q_BC_R25 = 1720,0,0,0 %; literal CPU$S_BC_R25 = 8; ! r25 - temporary register macro CPU$Q_BC_R26 = 1728,0,0,0 %; literal CPU$S_BC_R26 = 8; ! r26 - temporary register macro CPU$Q_BC_R27 = 1736,0,0,0 %; literal CPU$S_BC_R27 = 8; ! r27 - temporary register macro CPU$Q_BC_R28 = 1744,0,0,0 %; literal CPU$S_BC_R28 = 8; ! r28 - temporary register macro CPU$Q_BC_R29 = 1752,0,0,0 %; literal CPU$S_BC_R29 = 8; ! r29 - temporary register macro CPU$Q_BC_R30 = 1760,0,0,0 %; literal CPU$S_BC_R30 = 8; ! r30 - temporary register macro CPU$Q_BC_R31 = 1768,0,0,0 %; literal CPU$S_BC_R31 = 8; ! r31 - temporary register ! ! Branch registers ! (br1-br5 are preserved) ! macro CPU$Q_BC_B0 = 1776,0,0,0 %; literal CPU$S_BC_B0 = 8; ! Return pointer on kernel entry macro CPU$Q_BC_B1 = 1784,0,0,0 %; literal CPU$S_BC_B1 = 8; ! b1 - Preserved branch register (not saved by interrupt) macro CPU$Q_BC_B2 = 1792,0,0,0 %; literal CPU$S_BC_B2 = 8; ! b2 - Preserved branch register (not saved by interrupt) macro CPU$Q_BC_B3 = 1800,0,0,0 %; literal CPU$S_BC_B3 = 8; ! b3 - Preserved branch register (not saved by interrupt) macro CPU$Q_BC_B4 = 1808,0,0,0 %; literal CPU$S_BC_B4 = 8; ! b4 - Preserved branch register (not saved by interrupt) macro CPU$Q_BC_B5 = 1816,0,0,0 %; literal CPU$S_BC_B5 = 8; ! b5 - Preserved branch register (not saved by interrupt) macro CPU$Q_BC_B6 = 1824,0,0,0 %; literal CPU$S_BC_B6 = 8; ! b6 - temporary branch register macro CPU$Q_BC_B7 = 1832,0,0,0 %; literal CPU$S_BC_B7 = 8; ! b7 - temporary branch register macro CPU$L_BC_IVT_OFFSET = 1840,0,32,0 %; ! - Offset in IVT (more specific than trap type) macro CPU$L_BC_RESERVED_2 = 1844,0,32,0 %; ! - Reserved for future use ! ! Floating point data ! macro CPU$Q_BC_FPSR = 1848,0,0,0 %; literal CPU$S_BC_FPSR = 8; ! Floating point status register ! ! Alignment for 128-bit floating point ! ! ! Reduced FP subset that compilers might use in the exec ! macro CPU$Q_BC_F6 = 1856,0,0,0 %; literal CPU$S_BC_F6 = 16; ! f6 - temporary FP register macro CPU$Q_BC_F7 = 1872,0,0,0 %; literal CPU$S_BC_F7 = 16; ! f7 - temporary FP register macro CPU$Q_BC_F8 = 1888,0,0,0 %; literal CPU$S_BC_F8 = 16; ! f8 - temporary FP register macro CPU$Q_BC_F9 = 1904,0,0,0 %; literal CPU$S_BC_F9 = 16; ! f9 - temporary FP register macro CPU$Q_BC_F10 = 1920,0,0,0 %; literal CPU$S_BC_F10 = 16; ! f10 - temporary FP register macro CPU$Q_BC_F11 = 1936,0,0,0 %; literal CPU$S_BC_F11 = 16; ! f11 - temporary FP register macro CPU$Q_BC_MCES = 1952,0,0,0 %; literal CPU$S_BC_MCES = 8; ! Stored MCES macro CPU$Q_BC_PCBB = 1960,0,0,0 %; literal CPU$S_BC_PCBB = 8; ! Stored PCBB macro CPU$Q_BC_PRBR = 1968,0,0,0 %; literal CPU$S_BC_PRBR = 8; ! Stored PRBR macro CPU$Q_BC_VPTB = 1976,0,0,0 %; literal CPU$S_BC_VPTB = 8; ! Stored VPTB macro CPU$Q_BC_SCBB = 1984,0,0,0 %; literal CPU$S_BC_SCBB = 8; ! Stored SCBB macro CPU$Q_BC_SISR = 1992,0,0,0 %; literal CPU$S_BC_SISR = 8; ! Stored SISR ! ! Alignment for 128-bit floating point ! macro CPU$R_BC_FR_VECTOR = 2000,0,0,0 %; literal CPU$S_BC_FR_VECTOR = 2048; ! Stored ia64 floating registers ! *** End of IA64 symbols that match $CRASHDEF in [SDA]EVAX_SDADEF.SDL. **** macro CPU$Q_BC_BUGSTK = 4048,0,0,0 %; literal CPU$S_BC_BUGSTK = 8; ! new BUGSTK pointer following context switch macro CPU$Q_BC_INTSTK = 4056,0,0,0 %; literal CPU$S_BC_INTSTK = 8; ! new INTSTK pointer following context switch macro CPU$Q_BC_KR0 = 4064,0,0,0 %; literal CPU$S_BC_KR0 = 8; ! Kernel registers macro CPU$Q_BC_KR1 = 4072,0,0,0 %; literal CPU$S_BC_KR1 = 8; macro CPU$Q_BC_KR2 = 4080,0,0,0 %; literal CPU$S_BC_KR2 = 8; macro CPU$Q_BC_KR3 = 4088,0,0,0 %; literal CPU$S_BC_KR3 = 8; macro CPU$Q_BC_KR4 = 4096,0,0,0 %; literal CPU$S_BC_KR4 = 8; macro CPU$Q_BC_KR5 = 4104,0,0,0 %; literal CPU$S_BC_KR5 = 8; macro CPU$Q_BC_KR6 = 4112,0,0,0 %; literal CPU$S_BC_KR6 = 8; macro CPU$Q_BC_KR7 = 4120,0,0,0 %; literal CPU$S_BC_KR7 = 8; macro CPU$Q_BC_ORIG_INTSTK = 4128,0,0,0 %; literal CPU$S_BC_ORIG_INTSTK = 8; ! ! ! ! End of storage used by BUGCHECK code. ! ****************************************************************** macro CPU$L_BUGCODE = 4136,0,32,0 %; ! BUGCHECK code macro CPU$L_CAPABILITY = 4140,0,32,0 %; ! Bitmask of CPU's capabilities macro CPU$Q_BOOT_TIME = 4144,0,0,0 %; literal CPU$S_BOOT_TIME = 8; ! System time this cpu booted macro CPU$Q_ASN = 4152,0,0,0 %; literal CPU$S_ASN = 8; ! Last ASN assigned for this CPU macro CPU$Q_ASNSEQ = 4160,0,0,0 %; literal CPU$S_ASNSEQ = 8; ! Current ASN sequence number ! ! Time counters defined as follows: ! (Also applies to UKERNEL and UNULLCPU cells) ! ! KERNEL mode in process context, no spinlock busywait active ! EXECUTIVE mode ! SUPERVISOR mode ! USER mode ! KERNEL mode in system context (PS = 1), no spinlock busywait active ! KERNEL mode in process or system context, spinlock busywait is active ! ! NULL time counter ! macro CPU$Q_KERNEL = 4168,0,0,0 %; literal CPU$S_KERNEL = 48; ! Clock ticks in each mode macro CPU$Q_SYSTEM_CONTEXT = 4200,0,0,0 %; literal CPU$S_SYSTEM_CONTEXT = 8; ! Clock ticks in interrupt mode macro CPU$Q_MPSYNCH = 4208,0,0,0 %; literal CPU$S_MPSYNCH = 8; ! Clock ticks in MP synchronization macro CPU$Q_NULLCPU = 4216,0,0,0 %; literal CPU$S_NULLCPU = 8; ! Clock ticks in per-CPU system process (null) macro CPU$L_HARDAFF = 4224,0,32,0 %; ! Count of processes with ! hard affinity for this CPU ! ! Spinlock acquisition/release tracking and verification data ! macro CPU$L_RANK_VEC = 4228,0,32,0 %; ! Ranks of spinlocks currently held macro CPU$L_IPL_VEC = 4232,0,32,0 %; ! IPL vector of held spinlocks macro CPU$L_IPL_ARRAY = 4236,0,0,1 %; literal CPU$S_IPL_ARRAY = 128; ! IPL counts of held spinlocks ! ! Cells for CPU sanity timer ! macro CPU$L_TPOINTER = 4364,0,32,1 %; ! Address of SANITY_TIMER of ! CPU being watched macro CPU$L_SANITY_TIMER = 4368,0,32,0 %; ! # of sanity cycles before this CPU times out macro CPU$L_SANITY_TICKS = 4372,0,32,0 %; ! # of ticks until next sanity cycle ! ! CPU flags ! macro CPU$L_FLAGS = 4376,0,32,0 %; ! Various CPU flags macro CPU$V_SCHED = 4376,0,1,0 %; ! Idle loop vying for SCHED macro CPU$V_FOREVER = 4376,1,1,0 %; ! STOP/CPU with /FOREVER qualifier macro CPU$V_NEWPRIM = 4376,2,1,0 %; ! Primary-to-be CPU macro CPU$V_PSWITCH = 4376,3,1,0 %; ! Live primary switch requested by primary CPU macro CPU$V_BC_STACK = 4376,4,1,0 %; ! Set if we swapped process context to write crash dump macro CPU$V_BC_CONTEXT = 4376,5,1,0 %; ! Set if database contains context from bugcheck macro CPU$V_USER_CAPABILITIES_SET = 4376,6,1,0 %; ! Set if user capabilities already initialized macro CPU$V_RESET_LOW_POWER = 4376,7,1,0 %; ! Tell the next clock soft-tick to reset the low power switch ! ! The following field, INTFLAGS, must be longword aligned since ! interlocked instructions are used to access the bitfields. ! macro CPU$L_INTFLAGS = 4380,0,32,0 %; ! Interlocked CPU flags macro CPU$V_STOPPING = 4380,0,1,0 %; ! CPU stopping flag ! ! System stack base and limit ! macro CPU$L_SYS_STACK_BASE = 4384,0,32,1 %; macro CPU$L_SYS_STACK_LIMIT = 4388,0,32,1 %; ! ! Descriptor used to locate the variable portion of the per-CPU database. ! This approach allows the fixed portion of the database to more easily ! grow over time. The offset represents a byte offset from the start of ! the fixed portion of the per-CPU database to a variable portion containing ! CPU-specific data. The variable portion is located adjacent to the fixed ! portion of the database. ! macro CPU$L_VARIABLE_OFFSET = 4392,0,32,0 %; ! Offset to variable portion of database macro CPU$L_VARIABLE_LENGTH = 4396,0,32,0 %; ! Length in bytes of variable portion ! ! Define cells for machine check recovery block. These two longwords ! are assumed to be adjacent. ! macro CPU$L_MCHK_MASK = 4400,0,32,0 %; ! Function mask for current recovery block macro CPU$L_MCHK_SP = 4404,0,32,1 %; ! Saved SP for return at end of block ! 0 (zero) if no current recovery block ! ! Define a cell to point to a machine check crashes save area. This pointer ! is used by SDA to display the machine check information after a crash. ! macro CPU$PQ_MCHK_CRASH_AREA_VA = 4408,0,0,1 %; literal CPU$S_MCHK_CRASH_AREA_VA = 8; ! VA of mcheck crash area macro CPU$PL_MCHK_CRASH_AREA_VA_L = 4408,0,32,1 %; macro CPU$IL_MCHK_CRASH_AREA_VA_H = 4412,0,32,0 %; ! ! Define cells for processor_corrected_error_svapte and processor_mchk_abort ! _svapte. ! macro CPU$L_PROC_CORRECTED_ERROR_SVAP = 4416,0,32,1 %; macro CPU$L_PROC_MCHK_ABORT_SVAPTE = 4420,0,32,1 %; ! sva of spte allocated during initialization ! used to map the logout areas. macro CPU$PQ_LOGOUT_AREA_VA = 4424,0,0,1 %; literal CPU$S_LOGOUT_AREA_VA = 8; ! VA of mcheck logout area macro CPU$PL_LOGOUT_AREA_VA_L = 4424,0,32,1 %; macro CPU$IL_LOGOUT_AREA_VA_H = 4428,0,32,0 %; ! ! Soft tick dynamic timing offsets to determine when a 10ms "soft" tick ! occurs for each CPU. ! macro CPU$L_SOFT_TICK = 4432,0,32,0 %; macro CPU$L_TIME_DEVIATION = 4436,0,32,1 %; ! ! The following fields support PC sampling. They must be longword aligned. ! macro CPU$L_PCSAMPLE_BUFFER = 4440,0,32,1 %; macro CPU$L_PCSAMPLE_FLAGS = 4444,0,32,0 %; macro CPU$V_PCSAMPLE_ACTIVE = 4444,0,1,0 %; ! Sample being collected. ! ! Performance monitoring cells to replace global roll-up cells in idle loop. ! These cells MUST remain on quadword boundaries since they are updated by ! system quadword builtins. Any changes above these offsets must take this ! into account. ! macro CPU$Q_IDLE_LOOP_COUNT = 4448,0,0,0 %; literal CPU$S_IDLE_LOOP_COUNT = 8; ! Count of idle code loops macro CPU$Q_ZEROED_PAGE_COUNT = 4456,0,0,0 %; literal CPU$S_ZEROED_PAGE_COUNT = 8; ! Count of free pages zeroed ! ! Rank counter cells for keeping track of the number of acquisitions ! in effect for a given ranking. This is primarily for portlock support, ! but is integrated into all static ranks for simplicity ! macro CPU$L_RANK_ARRAY = 4464,0,0,1 %; literal CPU$S_RANK_ARRAY = 128; ! Counts of acquisitions by rank ! ! Inline fork block for port-affinitized I/O activity ! macro CPU$L_IO_AFF_FKB = 4592,0,0,1 %; literal CPU$S_IO_AFF_FKB = 48; ! ! Flags field for Fast Path I/O - this field is clumped with the FKB above ! and the queue below to get the best cache block behavior ! macro CPU$L_IO_AFF_FLAGS = 4640,0,32,0 %; ! Fast Path I/O bits macro CPU$V_IO_AFF_FKB_INUSE = 4640,0,1,0 %; ! CPUDB FKB in use macro CPU$V_PORT_ASSIGNED = 4640,1,1,0 %; ! CPU has port affinity macro CPU$V_DISTRIBUTED_INTS = 4640,2,1,0 %; ! CPU has hw interrupt port(s) assigned. ! ! Absolute queue header for port-affinitized Fast Path I/O - must be ! quadword aligned ! macro CPU$PS_IO_START_AFF_QFL = 4648,0,32,1 %; ! UCB listhead macro CPU$PS_IO_START_AFF_QBL = 4652,0,32,1 %; ! ! The following space doubles as debugging space as well as providing ! 64-byte cache alignment for the following listhead. If the structure ! above changes this must reflected in this count. If this space gets ! filled in at some point, it is critical that the new cells not be ! highly accessed, otherwise we have potential hangs from overlapping ! memory lock interactions. ! ! Absolute interlocked queue for fastpath hardware interrupt ports ! assigned to this cpu ! macro CPU$PS_IO_INT_AFF_QFL = 4704,0,32,1 %; ! Fastpath HW interrupt macro CPU$PS_IO_INT_AFF_QBL = 4708,0,32,1 %; ! : ports UCB listhead ! ! Holder cell for CPU capabilities. This replaces the old CAPABILITY that ! existed further up the structure. The lower longword holds the system and ! user capabilities for this CPU. The upper longword is an affinity bitmask ! containing a single bit set in the CPUID position of this CPU. ! macro CPU$Q_CAPABILITIES = 4712,0,0,0 %; literal CPU$S_CAPABILITIES = 8; ! Caps and affinity macro CPU$L_CAPABILITIES = 4712,0,32,0 %; ! Just system and user caps ! Cell to hold a counter for emulated instructions. This counter is incremented ! when an instruction that is not available on this CPU (e.g. LDBU, LDWU) is ! executed in system context and is emulated. macro CPU$L_EMULATE_COUNT = 4720,0,32,1 %; macro CPU$L_UNTESTED_PAGE_STATE = 4724,0,32,0 %; ! State for interrupted memory test macro CPU$W_UNTESTED_CHUNKS = 4724,0,16,0 %; ! Count of 32-byte chunks remaining to be tested in current page macro CPU$V_LASTPAGE_TESTED = 4724,29,1,0 %; ! Last untested page is being tested macro CPU$V_MCHECK = 4724,30,1,0 %; ! Mcheck occurred during memory test macro CPU$V_MEMORY_WRITE = 4724,31,1,0 %; ! Memory test is in the write process macro CPU$Q_UNTESTED_PATTERN = 4728,0,0,0 %; literal CPU$S_UNTESTED_PATTERN = 8; macro CPU$L_UNTESTED_PAGE_SPTE = 4736,0,32,1 %; ! SPTE address macro CPU$L_UNTESTED_PAGE_VA = 4740,0,32,1 %; ! VA for testing memory macro CPU$Q_SCHED_DATA = 4744,0,0,1 %; literal CPU$S_SCHED_DATA = 680; ! scheduling data based on process ! priority level (5 quadwords for each ! priority level). See SCHED_DS structure ! below for more details. ! macro CPU$Q_SCC_DELTA = 5424,0,0,1 %; literal CPU$S_SCC_DELTA = 8; ! Offset from primary SCC value macro CPU$L_TRANSITION_FLAGS = 5432,0,32,0 %; ! Various CPU transition flags macro CPU$V_AUTO_START = 5432,0,1,0 %; ! CPU is automatically made active macro CPU$V_NOBINDINGS = 5432,1,1,0 %; ! Minimize features that prevent transition macro CPU$PQ_CTD_LISTHEAD = 5440,0,0,1 %; literal CPU$S_CTD_LISTHEAD = 8; ! Offset to CPU transition block macro CPU$L_FAILOVER_NODE = 5448,0,32,1 %; ! Node ID to fail this CPU over to macro CPU$PQ_GMP_LISTHEAD = 5456,0,0,1 %; literal CPU$S_GMP_LISTHEAD = 8; ! Address of listhead for GMPs macro CPU$PQ_EXTENSION_BLOCK = 5464,0,0,1 %; literal CPU$S_EXTENSION_BLOCK = 8; ! Pointer to extension of CPUDB macro CPU$PQ_LCKCPU = 5472,0,0,1 %; literal CPU$S_LCKCPU = 8; ! pointer to per-CPU lckmgr counter structure macro CPU$L_FP_ASGN_PORTS_FL = 5480,0,32,1 %; ! queue links to fastpath ports macro CPU$L_FP_ASGN_PORTS_BL = 5484,0,32,1 %; ! : macro CPU$L_FP_NUM_PORTS = 5488,0,32,1 %; ! number of fastpath ports assigned to this CPU macro CPU$L_FP_NUM_USER_PORTS = 5492,0,32,1 %; ! number of user preferred fastpath ports assigned macro CPU$L_FP_SPARE1 = 5496,0,32,1 %; macro CPU$L_FP_SPARE2 = 5500,0,32,1 %; macro CPU$L_FP_SPARE3 = 5504,0,32,1 %; macro CPU$L_FP_SPARE4 = 5508,0,32,1 %; macro CPU$L_RAD = 5512,0,32,1 %; ! This cell initialized to the RAD number the CPU belongs to macro CPU$L_RAD_SPARE1 = 5516,0,32,1 %; macro CPU$Q_BC_SCC = 5520,0,0,0 %; literal CPU$S_BC_SCC = 8; ! System Cycle Counter recorded by BUGCHECK (all platforms) ! ! TIMEDWAIT cells to support mixed-speed CPUs in heterogeneous SMP configurations ! macro CPU$Q_TMWT_SCALER = 5528,0,0,0 %; literal CPU$S_TMWT_SCALER = 8; ! Scaler value for SCC conversions macro CPU$Q_TMWT_DIVISOR = 5536,0,0,0 %; literal CPU$S_TMWT_DIVISOR = 8; ! Divisor value for SCC conversions macro CPU$Q_TMWT_SHIFT = 5544,0,0,0 %; literal CPU$S_TMWT_SHIFT = 8; ! Divisor shift count for SCC conversions ! ! Fastpath hardware interrupt ports housekeeping ! macro CPU$L_FP_ASGN_HWINT_PORTS_FL = 5552,0,32,1 %; ! queue links to hwint ports macro CPU$L_FP_ASGN_HWINT_PORTS_BL = 5556,0,32,1 %; ! : macro CPU$L_NUM_HWINT_PORTS = 5560,0,32,1 %; ! number HW int ports macro CPU$L_NUM_USRPRF_HWINT_PORTS = 5564,0,32,1 %; ! number user-assigned fastpath HW int ports macro CPU$Q_XFC_VAB_POINTER = 5568,0,0,0 %; literal CPU$S_XFC_VAB_POINTER = 8; ! Link to XFC per RAD structures ! Keep track of CPU load macro CPU$L_LOAD_FACTOR = 5576,0,32,0 %; ! This is the fixed point fraction of time CPU is usable macro CPU$L_BIN_5SEC = 5580,0,32,0 %; ! Which of 5 bins are we using macro CPU$L_USABLE_TICKS = 5584,0,0,0 %; literal CPU$S_USABLE_TICKS = 20; ! 5 bins counting the usable ticks macro CPU$L_TOTAL_TICKS = 5604,0,32,0 %; ! Total number of ticks during a second macro CPU$L_COUNTER_10MS = 5608,0,32,0 %; ! Count 10ms intervals to get one second macro CPU$L_FILLER_1 = 5612,0,32,1 %; ! Make quadwords even ! Per-CPU queues macro CPU$AQ_COM_QUEUES = 5616,0,0,1 %; literal CPU$S_COM_QUEUES = 512; ! 64 queue heads for this CPU macro CPU$Q_COM_QUEUE_SUMMARY = 6128,0,0,0 %; literal CPU$S_COM_QUEUE_SUMMARY = 8; ! Bits to show which CPU queues are used ! Per-RAD database pointer macro CPU$PQ_RAD_DATABASE = 6136,0,0,1 %; literal CPU$S_RAD_DATABASE = 8; ! Pointer to the RAD database for RAD this CPU belongs to macro CPU$PQ_CFLUSH_VA_PTE = 6144,0,0,1 %; literal CPU$S_CFLUSH_VA_PTE = 8; ! Pointer to PTE mapping S2 space VA macro CPU$PQ_CFLUSH_VA = 6152,0,0,1 %; literal CPU$S_CFLUSH_VA = 8; ! Pointer to S2 space VA used by cflush ! Per-CPU timing cells to be filled in when CPU joins the active set macro CPU$Q_ITM_WIDTH = 6160,0,0,1 %; literal CPU$S_ITM_WIDTH = 8; ! Width of clock tick in IPF ITM units macro CPU$L_MAX_DEVIATION = 6168,0,32,1 %; macro CPU$L_MINIMUM_TICKS = 6172,0,32,0 %; macro CPU$L_OVER_DELTA = 6176,0,32,1 %; macro CPU$L_UNDER_DELTA = 6180,0,32,1 %; ! ! System register stack base and limit ! macro CPU$Q_SYS_REGSTACK_BASE = 6184,0,0,1 %; literal CPU$S_SYS_REGSTACK_BASE = 8; macro CPU$Q_SYS_REGSTACK_LIMIT = 6192,0,0,1 %; literal CPU$S_SYS_REGSTACK_LIMIT = 8; ! ! Termination and slot stack bases ! macro CPU$Q_SLOT_STACK_BASE = 6200,0,0,1 %; literal CPU$S_SLOT_STACK_BASE = 8; macro CPU$Q_SLOT_REGSTACK_BASE = 6208,0,0,1 %; literal CPU$S_SLOT_REGSTACK_BASE = 8; ! ! VHPT virtual address and setup info ! macro CPU$PQ_VHPT_VA = 6216,0,0,1 %; literal CPU$S_VHPT_VA = 8; ! VA of VHPT for this CPU macro CPU$L_VHPT_TRS = 6224,0,32,1 %; ! Number of TRs used for VHPT macro CPU$L_VHPT_PS = 6228,0,32,1 %; ! Pagesize used for VHPT ! ! More BUGCHECK cells: the contents of the CR.PTA register; data from SWIS ! (SWIS$L_GH_PS thru SWIS$Q_DTNVFLT without the fill); the region registers ! macro CPU$Q_BC_PTA = 6232,0,0,1 %; literal CPU$S_BC_PTA = 8; ! Saved contents of CR.PTA macro CPU$L_BC_SWIS_GH_PS = 6240,0,0,0 %; literal CPU$S_BC_SWIS_GH_PS = 64; ! GH to PS conversions macro CPU$Q_BC_SWIS_VPTB = 6304,0,0,0 %; literal CPU$S_BC_SWIS_VPTB = 128; ! Virtual page table bases macro CPU$Q_BC_SWIS_PPN_MASK = 6432,0,0,0 %; literal CPU$S_BC_SWIS_PPN_MASK = 8; ! Physical page mask (takes PA bits into account) macro CPU$Q_BC_SWIS_PT_PA = 6440,0,0,0 %; literal CPU$S_BC_SWIS_PT_PA = 128; ! Level 1 page table base physical addresses macro CPU$Q_BC_SWIS_VHPTFLT = 6568,0,0,0 %; literal CPU$S_BC_SWIS_VHPTFLT = 8; ! Count of VHPTFLT faults macro CPU$Q_BC_SWIS_ITLBFLT = 6576,0,0,0 %; literal CPU$S_BC_SWIS_ITLBFLT = 8; ! Count of ITLBFLT faults macro CPU$Q_BC_SWIS_DTLBFLT = 6584,0,0,0 %; literal CPU$S_BC_SWIS_DTLBFLT = 8; ! Count of DTLBFLT faults macro CPU$Q_BC_SWIS_ALTITLBFLT = 6592,0,0,0 %; literal CPU$S_BC_SWIS_ALTITLBFLT = 8; ! Count of ALTITLBFLT faults macro CPU$Q_BC_SWIS_ALTDTLBFLT = 6600,0,0,0 %; literal CPU$S_BC_SWIS_ALTDTLBFLT = 8; ! Count of ALTDTLBFLT faults macro CPU$Q_BC_SWIS_NESTEDTLBFLT = 6608,0,0,0 %; literal CPU$S_BC_SWIS_NESTEDTLBFLT = 8; ! Count of NESTEDTLBFLT faults macro CPU$Q_BC_SWIS_SPECLNFLT = 6616,0,0,0 %; literal CPU$S_BC_SWIS_SPECLNFLT = 8; ! Count of SPECLNFLT faults macro CPU$Q_BC_SWIS_ITNVFLT = 6624,0,0,0 %; literal CPU$S_BC_SWIS_ITNVFLT = 8; ! Count of *ITLBFLT -> TNV faults macro CPU$Q_BC_SWIS_DTNVFLT = 6632,0,0,0 %; literal CPU$S_BC_SWIS_DTNVFLT = 8; ! Count of *DTLBFLT -> TNV faults macro CPU$Q_BC_RR = 6640,0,0,0 %; literal CPU$S_BC_RR = 64; ! The region registers macro CPU$Q_BC_KBSP = 6704,0,0,0 %; literal CPU$S_BC_KBSP = 8; ! Kernel mode backing store pointer macro CPU$Q_BC_EBSP = 6712,0,0,0 %; literal CPU$S_BC_EBSP = 8; ! Exec mode backing store pointer macro CPU$Q_BC_SBSP = 6720,0,0,0 %; literal CPU$S_BC_SBSP = 8; ! Super mode backing store pointer macro CPU$Q_BC_UBSP = 6728,0,0,0 %; literal CPU$S_BC_UBSP = 8; ! User mode backing store pointer ! ! Virtual addresses of the physical buffers that hold the SAL-built error ! records for the four hardware interrupt types ! macro CPU$PQ_INIT_ERROR_RECORD_VA = 6736,0,0,1 %; literal CPU$S_INIT_ERROR_RECORD_VA = 8; ! VA of INIT error record buffer macro CPU$PL_INIT_ERROR_RECORD_VA_L = 6736,0,32,1 %; macro CPU$IL_INIT_ERROR_RECORD_VA_H = 6740,0,32,0 %; macro CPU$PQ_MCA_ERROR_RECORD_VA = 6744,0,0,1 %; literal CPU$S_MCA_ERROR_RECORD_VA = 8; ! VA of MCA error record buffer macro CPU$PL_MCA_ERROR_RECORD_VA_L = 6744,0,32,1 %; macro CPU$IL_MCA_ERROR_RECORD_VA_H = 6748,0,32,0 %; macro CPU$PQ_CMC_ERROR_RECORD_VA = 6752,0,0,1 %; literal CPU$S_CMC_ERROR_RECORD_VA = 8; ! VA of CMC error record buffer macro CPU$PL_CMC_ERROR_RECORD_VA_L = 6752,0,32,1 %; macro CPU$IL_CMC_ERROR_RECORD_VA_H = 6756,0,32,0 %; macro CPU$PQ_CPE_ERROR_RECORD_VA = 6760,0,0,1 %; literal CPU$S_CPE_ERROR_RECORD_VA = 8; ! VA of CPE error record buffer macro CPU$PL_CPE_ERROR_RECORD_VA_L = 6760,0,32,1 %; macro CPU$IL_CPE_ERROR_RECORD_VA_H = 6764,0,32,0 %; macro CPU$R_CBB_CPUID_MASK = 6768,0,0,0 %; literal CPU$S_CBB_CPUID_MASK = 48; ! Embedded CBB block macro CPU$L_CPUID_MASK = 6816,0,32,0 %; ! CPU ID in longword bitmask form macro CPU$Q_CPUID_MASK = 6816,0,0,0 %; literal CPU$S_CPUID_MASK = 8; ! CPU ID in quadword bitmask form ! ! Itanium power management data cells. ! macro CPU$L_LOW_POWER = 6944,0,32,1 %; ! Indicates if power management is on macro CPU$L_PWR_MGMT_ON = 6948,0,32,1 %; ! Incremented when Power Mgmt is on macro CPU$Q_PREV_NULLCPU = 6952,0,0,1 %; literal CPU$S_PREV_NULLCPU = 8; ! Previous NULLCPU value macro CPU$Q_LOW_POWER_ENTERED = 6960,0,0,1 %; literal CPU$S_LOW_POWER_ENTERED = 8; ! Number of times a low power state was entered ! ! CPU Thread data ! macro CPU$R_CBB_COTHREAD_MASK = 6968,0,0,0 %; literal CPU$S_CBB_COTHREAD_MASK = 48; ! Embedded CBB block macro CPU$Q_COTHREAD_MASK = 7016,0,0,0 %; literal CPU$S_COTHREAD_MASK = 8; ! CPU cothreads in quadword bitmask form macro CPU$Q_COTHREADD_DB_QFL = 7144,0,0,0 %; literal CPU$S_COTHREADD_DB_QFL = 8; ! Quadword queue to CPUDB which is another thread macro CPU$Q_COTHREADD_DB_QBL = 7152,0,0,0 %; literal CPU$S_COTHREADD_DB_QBL = 8; ! (Back link) macro CPU$L_MAX_CUR_COTHD_PRIORITY = 7160,0,32,0 %; ! The maximum priority of the cothreads on this core macro CPU$L_NUM_COTHREADS = 7164,0,32,0 %; ! How many threads are in the same core with this CPU? ! ! More processor registers to be saved at system crash ! macro CPU$Q_BC_TPR = 7168,0,0,1 %; literal CPU$S_BC_TPR = 8; ! Task Priority Register macro CPU$Q_BC_IRR0 = 7176,0,0,1 %; literal CPU$S_BC_IRR0 = 8; ! External Interrupt Register 0 macro CPU$Q_BC_IRR1 = 7184,0,0,1 %; literal CPU$S_BC_IRR1 = 8; ! External Interrupt Register 1 macro CPU$Q_BC_IRR2 = 7192,0,0,1 %; literal CPU$S_BC_IRR2 = 8; ! External Interrupt Register 2 macro CPU$Q_BC_IRR3 = 7200,0,0,1 %; literal CPU$S_BC_IRR3 = 8; ! External Interrupt Register 3 ! ! BUGcheck LOG buffer area for dump hints/info prior to bugcheck ! macro CPU$R_BUGLOG = 7208,0,0,1 %; literal CPU$S_BUGLOG = 256; ! ! Data cells to keep track of owner and sequence number of floating point register banks ! macro CPU$L_FP_HIGH_OWNER_PID = 7464,0,32,0 %; macro CPU$L_FP_LOW_OWNER_PID = 7468,0,32,0 %; macro CPU$Q_FP_HIGH_SEQUENCE_NUMBER = 7472,0,0,0 %; literal CPU$S_FP_HIGH_SEQUENCE_NUMBER = 8; macro CPU$Q_FP_LOW_SEQUENCE_NUMBER = 7480,0,0,0 %; literal CPU$S_FP_LOW_SEQUENCE_NUMBER = 8; ! ! Cells to hold the values in the first two protection key registers ! when the system crashes (only the first two are used, for FOE/iCache) ! macro CPU$Q_BC_PKR0 = 7488,0,0,0 %; literal CPU$S_BC_PKR0 = 8; macro CPU$Q_BC_PKR1 = 7496,0,0,0 %; literal CPU$S_BC_PKR1 = 8; ! ! Keep track of the current power/performance state in this CPU ! macro CPU$PQ_POWER_ACCOUNTING = 7504,0,0,1 %; literal CPU$S_POWER_ACCOUNTING = 8; ! Pointer to (possibly variable length) data to account for CPU pstate time macro CPU$L_CURRENT_PSTATE = 7512,0,32,0 %; macro CPU$L_SPARE_PSTATE_L = 7516,0,32,0 %; macro CPU$Q_SPARE_PSTATE_Q = 7520,0,0,0 %; literal CPU$S_SPARE_PSTATE_Q = 8; macro CPU$L_IDLE_EXITS = 7528,0,32,1 %; ! Decrement each time we exit idle. If <=0, stop saving power in idle. macro CPU$L_SPARE_COUNTER = 7532,0,32,0 %; macro CPU$Q_IDLE_PHL_STOPPED = 7536,0,0,0 %; literal CPU$S_IDLE_PHL_STOPPED = 8; macro CPU$Q_IDLE_PHL_RESTART_ABORT = 7544,0,0,0 %; literal CPU$S_IDLE_PHL_RESTART_ABORT = 8; ! ! Keep track of AR.RUC and related fields of this CPU ! macro CPU$L_RUC_SOFT_TICK = 7552,0,32,0 %; macro CPU$L_RUC_SPARE1 = 7556,0,32,0 %; macro CPU$Q_RUC_BASE = 7560,0,0,0 %; literal CPU$S_RUC_BASE = 8; macro CPU$Q_RUC_IN_USE_BY_HOST_MODE = 7568,0,0,0 %; literal CPU$S_RUC_IN_USE_BY_HOST_MODE = 8; ! Used to store the "CPU unavailable" time on VM ! ! Add new cells to hold the ITC and RUC values at every timer interrupt ! Also add new cells to hold the ITC and RUC values at the time of crash ! macro CPU$Q_LAST_TIMER_INT_ITC = 7576,0,0,0 %; literal CPU$S_LAST_TIMER_INT_ITC = 8; ! ITC value at the time of last timer interrupt macro CPU$Q_LAST_TIMER_INT_RUC = 7584,0,0,0 %; literal CPU$S_LAST_TIMER_INT_RUC = 8; ! RUC value at the time of last timer interrupt macro CPU$Q_BC_ITC = 7592,0,0,0 %; literal CPU$S_BC_ITC = 8; ! ITC value at the time of crash macro CPU$Q_BC_RUC = 7600,0,0,0 %; literal CPU$S_BC_RUC = 8; ! RUC value at the time of crash ! ! New cells should be added before this comment ! macro CPU$Q_BC_EXPANSION = 7608,0,0,1 %; literal CPU$S_BC_EXPANSION = 64; ! Make sure there's space at the end for new registers ! ! End of fixed portion of the per-CPU database. A variable portion may be required ! by this CPU type. ! ! ! Beginning of quadword aligned, variable portion of the per-CPU database. ! Access to this is via the VARIABLE_OFFSET and VARIABLE_LENGTH data cells ! in the fixed portion of the database. ! literal CPU$K_LENGTH = 7672; ! Total fixed structure size literal CPU$C_LENGTH = 7672; ! Total fixed structure size literal CPU$M_AGE_DATA = %X'1'; literal CPU$S_SCHED_DS = 40; macro CPU$Q_ACC_RUN = 0,0,0,0 %; literal CPU$S_ACC_RUN = 8; ! accumulated runtime macro CPU$Q_PROC_COUNT = 8,0,0,0 %; literal CPU$S_PROC_COUNT = 8; ! # of process run at this priority level macro CPU$Q_ACC_INTERRUPT = 16,0,0,0 %; literal CPU$S_ACC_INTERRUPT = 8; ! accumulated interrupt time macro CPU$Q_ACC_WAITIME = 24,0,0,0 %; literal CPU$S_ACC_WAITIME = 8; ! accumulated wait time macro CPU$Q_SCHED_FLAGS = 32,0,0,0 %; literal CPU$S_SCHED_FLAGS = 8; ! Scheduling flags macro CPU$V_AGE_DATA = 32,0,1,0 %; ! Indicates data needs to be aged literal CPU$K_SCHED_LENGTH = 40; ! byte length of each per-priority entry ! in the SCHED_DATA data structure !*** MODULE $ADPDEF *** ! + ! ADAPTER CONTROL BLOCK DEFINITIONS ! ! There is one ADP for each adapter on the system, where an adapter ! is defined as an interconnect between two busses or a multichannel ! device. ADPs are now arranged in a hierarchical structure reflecting ! the physical topology of the system and I/O buses. A special system ADP ! is placed at the root of the tree to represent a "virtual adapter" ! to the system bus. ADPs now contain a pointer to an array of ! information for each node on the remote bus to which the adapter ! connects. For example, the ADP for an XMI to BI adapter points to ! a 16-entry array for the 16 node BI bus. Each array entry contains ! several items including a hardware ID field, the base address of ! the node's CSR space, pointer(s) to data structure(s), a node ! number, and a bus-specific field. ! ! The ADP sometimes contains a pointer to a bus command table, which contains ! bit patterns representing commands on the target bus. These bit patterns ! are copied to the command field in the hardware mailbox for remote I/O ! bus register access on SRM-mailbox machines. ! - literal ADP$M_INDIRECT_VECTOR = %X'1'; literal ADP$M_ONLINE = %X'2'; literal ADP$M_BOOT_ADP = %X'4'; literal ADP$M_PCI_PCI_BRIDGE = %X'8'; literal ADP$M_EISA_PARENT = %X'10'; literal ADP$M_DEEP = %X'20'; literal ADP$M_PCI_MULTI = %X'40'; literal ADP$M_HCDP = %X'80'; literal ADP$M_MULTI_CHAN = %X'100'; literal ADP$M_SHUTDOWN = %X'1'; literal ADP$M_PORTONLY = %X'2'; literal ADP$M_STRUCT_ALLOCATED = %X'4'; literal ADP$M_DDMA64 = %X'1'; literal ADP$M_DDMA_MONSTER = %X'2'; literal ADP$M_DDMA32 = %X'4'; literal ADP$M_MAP_REGISTERS = %X'8'; literal ADP$M_BUFFER_COPYING = %X'10'; literal ADP$M_ALLOC_MAP_REGISTERS = %X'20'; literal ADP$S_ADP = 672; macro ADP$Q_CSR = 0,0,0,1 %; literal ADP$S_CSR = 8; ! Adapter control and status register macro ADP$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro ADP$B_TYPE = 10,0,8,0 %; ! Structure type code macro ADP$B_NUMBER = 11,0,8,0 %; ! Ordinal adapter number macro ADP$L_LINK = 12,0,32,1 %; ! Address of next adapter control block macro ADP$L_TR = 16,0,32,0 %; ! Configuration TR number macro ADP$L_ADPTYPE = 20,0,32,0 %; ! Software adapter type macro ADP$PS_NODE_DATA = 24,0,32,1 %; ! Address of adapter specific node data routine macro ADP$L_VECTOR = 28,0,32,1 %; ! Address of vector jump table macro ADP$L_CRB = 32,0,32,1 %; ! Address of channel request block macro ADP$PS_MBPR = 36,0,32,1 %; ! Address of mailbox pointer register macro ADP$Q_QUEUE_TIME = 40,0,0,0 %; literal ADP$S_QUEUE_TIME = 8; ! Timeout value for mailbox queueing operation macro ADP$Q_WAIT_TIME = 48,0,0,0 %; literal ADP$S_WAIT_TIME = 8; ! Timeout value for mailbox completion (DON bit set) macro ADP$PS_PARENT_ADP = 56,0,32,1 %; ! Address of parent ADP (0 if this is the root ADP) macro ADP$PS_PEER_ADP = 60,0,32,1 %; ! Address of next ADP in peer list macro ADP$PS_CHILD_ADP = 64,0,32,1 %; ! Address of first child ADP macro ADP$L_PROBE_CMD = 68,0,32,0 %; ! Command index used for probing bus macro ADP$PS_BUS_ARRAY = 72,0,32,1 %; ! Address of bus array macro ADP$PS_COMMAND_TBL = 76,0,32,1 %; ! Address of bus specific command table macro ADP$PS_SPINLOCK = 80,0,32,1 %; ! Address of spinlock structure ! For a bus-to-bus adapter, the node_num is the node number of the adapter ! on the primary bus. The sec_node_num is the node number of the adapter ! on the remote bus. Whether these fields are used or not depends on how ! the bus and adapter hardware are designed. Examples: for xmi, the lamb ! xmi node number is stored in sec_node_num. For the other XMI ! adapters, the xmi node number is stored in node_num and sec_node_num is ! not used. macro ADP$W_NODE_NUM = 84,0,16,0 %; macro ADP$W_PRIM_NODE_NUM = 84,0,16,0 %; ! Primary node number macro ADP$W_SEC_NODE_NUM = 86,0,16,0 %; ! Secondary node number macro ADP$B_HOSE_NUM = 90,0,8,0 %; ! I/O adapter hose number macro ADP$PS_ADP_SPECIFIC2 = 92,0,32,1 %; macro ADP$L_ADP_SPECIFIC2 = 92,0,32,0 %; macro ADP$L_HW_LOCATION = 92,0,32,0 %; ! Geographic locator macro ADP$L_A32_FREE_ITEMS = 92,0,32,0 %; ! Fbus specific usage macro ADP$PS_ADP_SPECIFIC3 = 96,0,32,1 %; macro ADP$L_ADP_SPECIFIC3 = 96,0,32,0 %; macro ADP$L_A64_ITEM_NUM = 96,0,32,0 %; ! Fbus specific usage macro ADP$L_CRAB = 100,0,32,1 %; ! Address of map register control block macro ADP$L_ADAPTER_FLAGS = 104,0,32,0 %; macro ADP$V_INDIRECT_VECTOR = 104,0,1,0 %; ! Indirect vectored interrupts macro ADP$V_ONLINE = 104,1,1,0 %; ! Adapter is online macro ADP$V_BOOT_ADP = 104,2,1,0 %; ! Adapter is boot adapter macro ADP$V_PCI_PCI_BRIDGE = 104,3,1,0 %; ! Adapter represents a PCI/PCI bridge macro ADP$V_EISA_PARENT = 104,4,1,0 %; ! EISA ADP is this adp's child macro ADP$V_DEEP = 104,5,1,0 %; ! Multiple IRQs per SCB macro ADP$V_PCI_MULTI = 104,6,1,0 %; ! ADP represents a ! multifunction device macro ADP$V_HCDP = 104,7,1,0 %; ! ADP for HCDP console devices macro ADP$V_MULTI_CHAN = 104,8,1,0 %; ! ADP for multi-channel device macro ADP$L_RESERVED1 = 108,0,32,0 %; ! Reserved for future expansion macro ADP$Q_HW_ID_MASK = 112,0,0,1 %; literal ADP$S_HW_ID_MASK = 8; ! Hardware ID mask 64-bits macro ADP$L_HW_ID_MASK_LO = 112,0,32,1 %; ! Hardware ID mask low 32-bits macro ADP$L_HW_ID_MASK_HI = 116,0,32,1 %; ! Hardware ID mask high 32-bits macro ADP$R_CBB_CPU_AFFINITY = 120,0,0,0 %; literal ADP$S_CBB_CPU_AFFINITY = 48; ! Embedded CBB block macro ADP$L_CPU_AFFINITY = 168,0,32,0 %; ! Records CPUs which devices have affinity with macro ADP$Q_CPU_AFFINITY = 168,0,0,0 %; literal ADP$S_CPU_AFFINITY = 8; ! Records CPUs which devices have affinity with macro ADP$PS_NODE_FUNCTION = 296,0,32,1 %; ! Address of adapter-specific node function routine macro ADP$L_VPORTSTS = 300,0,32,0 %; ! CI - Vax port status bits macro ADP$V_SHUTDOWN = 300,0,1,0 %; ! CI - adapter microcode is stopped macro ADP$V_PORTONLY = 300,1,1,0 %; ! CI - port restart only -- no adapter restart macro ADP$V_STRUCT_ALLOCATED = 300,2,1,0 %; ! CI/SCSI - adapter-wide structures allocated macro ADP$L_AVECTOR = 304,0,32,1 %; ! Addr of 1ST SCB vector for this adaptor macro ADP$Q_SCRATCH_BUF_PA = 312,0,0,0 %; literal ADP$S_SCRATCH_BUF_PA = 8; macro ADP$PS_SCRATCH_BUF_VA = 320,0,32,1 %; ! VA, PA, and length of a physically macro ADP$L_SCRATCH_BUF_LEN = 324,0,32,0 %; ! contiguous memory block macro ADP$L_LSDUMP = 328,0,32,1 %; ! Address of physical contiguous ! memory for the adapter memory dump. macro ADP$PS_PROBE_CSR = 332,0,32,1 %; ! Address of adapter-specific probe CSR routine macro ADP$PS_PROBE_CSR_CLEANUP = 336,0,32,1 %; ! Address of adapter-specific probe CSR cleanup routine macro ADP$PS_LOAD_MAP_REG = 340,0,32,1 %; ! Address of adapter-specific load map register routine macro ADP$PS_SHUTDOWN = 344,0,32,1 %; ! Address of adapter-specific shutdown routine macro ADP$PS_CONFIG_TABLE = 348,0,32,1 %; ! Pointer to autoconfiguration table macro ADP$PS_MAP_REG_BASE = 352,0,32,1 %; ! Base virtual address of adapter map registers macro ADP$PS_ADP_SPECIFIC = 356,0,32,1 %; ! ADP specific cell macro ADP$PS_ADP_SPECIFIC1 = 356,0,32,1 %; macro ADP$L_ADP_SPECIFIC1 = 356,0,32,0 %; macro ADP$L_A32_ITEM_NUM = 356,0,32,0 %; ! Fbus specific usage macro ADP$PS_ABLK = 356,0,32,1 %; ! PNDRIVER specific usage macro ADP$PS_IOC_BASE_VA = 356,0,32,1 %; ! IPF - SVA of IOC register base macro ADP$PS_DISABLE_INTERRUPTS = 360,0,32,1 %; ! Address of adapter-specific disable interrupts routine macro ADP$PS_STARTUP = 364,0,32,1 %; ! Address of adapter-specific startup routine macro ADP$PS_INIT = 368,0,32,1 %; ! Address of adapter-specific initialization routine macro ADP$PS_ADP_SPECIFIC4 = 372,0,32,1 %; macro ADP$L_ADP_SPECIFIC4 = 372,0,32,0 %; macro ADP$L_A64_FREE_ITEMS = 372,0,32,0 %; ! Fbus specific usage macro ADP$L_TOTAL_SG_ENTRIES = 372,0,32,0 %; ! For PCI specific usage with memory channel macro ADP$Q_HARDWARE_TYPE = 376,0,0,1 %; literal ADP$S_HARDWARE_TYPE = 8; ! Saved hardware device type and revision macro ADP$Q_HARDWARE_REV = 384,0,0,1 %; literal ADP$S_HARDWARE_REV = 8; ! info. Interpretation in adapter-specific. macro ADP$PS_CRAM_CMD = 392,0,32,1 %; ! Address of adapter-specific cram init routine macro ADP$PS_READ_PCI_CONFIG = 396,0,32,1 %; ! Address of adapter-specific read pci config routine macro ADP$PS_WRITE_PCI_CONFIG = 400,0,32,1 %; ! Address of adapter-specific write pci config routine macro ADP$PS_MAP_IO = 404,0,32,1 %; ! Address of adapter-specific I/O space mapping routine macro ADP$PS_READ_IO = 408,0,32,1 %; ! Address of adapter-specific read I/O space routine macro ADP$PS_WRITE_IO = 412,0,32,1 %; ! Address of adapter-specific write I/O space routine macro ADP$PS_IOHANDLE_FLINK = 416,0,32,1 %; ! Pointer to IOHANDLE structures associated with this bus macro ADP$PS_IOHANDLE_BLINK = 420,0,32,1 %; ! Pointer to IOHANDLE structures associated with this bus ! Make sure that INTD has quadword alignment macro ADP$L_INTD = 424,0,0,0 %; literal ADP$S_INTD = 16; ! Interrupt transfer vector macro ADP$L_BUS_NUM = 440,0,32,0 %; ! Bus number. Used for systems with remote PCI ! buses for Type1 config space address generation. macro ADP$W_FPARS_SBA_UID = 444,0,16,0 %; ! SBA UID as short integer macro ADP$B_FPARS_IOC_NO = 446,0,8,0 %; ! IOC number from low byte of UID macro ADP$B_FPARS_ROPE_NO = 447,0,8,0 %; ! Rope number from ACPI _SUN method macro ADP$Q_PCI_NODE_NUM = 448,0,0,1 %; literal ADP$S_PCI_NODE_NUM = 8; ! PCI node number of PCI/PCI bridge adapter macro ADP$L_PCI_NODE_NUM_L = 448,0,32,1 %; macro ADP$L_PCI_NODE_NUM = 448,0,32,1 %; ! Signed on IA64, unsigned on alpha macro ADP$L_PCI_NODE_NUM_H = 452,0,32,1 %; ! Make sure that SINTD has quadword alignment macro ADP$L_SINTD = 456,0,0,0 %; literal ADP$S_SINTD = 16; ! Shared Interrupt transfer vector macro ADP$Q_HW_HANDLE = 472,0,0,0 %; literal ADP$S_HW_HANDLE = 8; ! An opaque hw_handle to match this ADP with its hardware macro ADP$Q_PARENT_HH = 480,0,0,0 %; literal ADP$S_PARENT_HH = 8; ! Hardware Handle of this ADP's parent. macro ADP$PS_PRT = 488,0,32,1 %; ! Pointer to the PCI Routing Table macro ADP$PS_UNLOAD_MAP_REG = 492,0,32,1 %; ! Address of adapter-specific unload map register routine macro ADP$Q_IOTLB_IBASE = 496,0,0,1 %; literal ADP$S_IOTLB_IBASE = 8; ! IOTLB IOVA base macro ADP$Q_IOTLB_IMASK = 504,0,0,1 %; literal ADP$S_IOTLB_IMASK = 8; ! IOTLB IOVA mask; defines IOVA size macro ADP$Q_IOTLB_PA = 512,0,0,1 %; literal ADP$S_IOTLB_PA = 8; ! Physical address of IOTLB macro ADP$Q_IOC_BASE_PA = 520,0,0,0 %; literal ADP$S_IOC_BASE_PA = 8; ! IPF Physical address of IOC registers ! ! The TRA_OFFSET identifier is being deprecated in favor of ! the TRA_MMIO identifier, since we need a TRA for Port IO ! space as well. ! macro ADP$Q_TRA_MMIO = 528,0,0,0 %; literal ADP$S_TRA_MMIO = 8; macro ADP$Q_TRA_OFFSET = 528,0,0,0 %; literal ADP$S_TRA_OFFSET = 8; ! Offset between I/O and system views of MMIO macro ADP$Q_HID = 536,0,0,0 %; literal ADP$S_HID = 8; ! ACPI Object Hardware ID field macro ADP$Q_UID = 544,0,0,0 %; literal ADP$S_UID = 8; ! ACPI Object Unique ID field macro ADP$Q_INIT_IO_BRIDGE = 552,0,0,1 %; literal ADP$S_INIT_IO_BRIDGE = 8; ! init_io_bridge routine, if one exists. macro ADP$PS_INIT_IO_BRIDGE = 552,0,32,1 %; macro ADP$Q_SAL_HANDLE = 560,0,0,0 %; literal ADP$S_SAL_HANDLE = 8; ! Identify shared FPars resouce to SAL macro ADP$PS_CONFIG = 568,0,32,1 %; ! Short pointer to GPSCONFIG struct ! These flags describe the types of DMA that are supported by the PLATFORM. Putting ! the flags at the ADP level allows additional flexibility on platforms where DMA ! capabilities vary by, for example, I/O controller. ! ! Device drivers use the same set of flag values to describe the DMA capabilities ! supported by the driver. Note that capabilities may not be uniform across all ! driver functions; for example, command/response rings may be constrained to exist ! below 4GB at the same time that the driver/adapter support 64-bit transfer addresses. ! macro ADP$L_MAPPING_FLAGS = 572,0,32,0 %; macro ADP$V_DDMA64 = 572,0,1,0 %; ! 64-bit DDMA available macro ADP$V_DDMA_MONSTER = 572,1,1,0 %; ! DDMA Monster window macro ADP$V_DDMA32 = 572,2,1,0 %; ! 32-bit DDMA available macro ADP$V_MAP_REGISTERS = 572,3,1,0 %; ! Map registers available macro ADP$V_BUFFER_COPYING = 572,4,1,0 %; ! Copying to/from system buffers macro ADP$V_ALLOC_MAP_REGISTERS = 572,5,1,0 %; ! Allocate map regs before load macro ADP$Q_RESERVED14 = 576,0,0,0 %; literal ADP$S_RESERVED14 = 8; ! Reserved for future expansion macro ADP$PS_DEVSLOTS = 576,0,32,1 %; ! Short Pointer to SLOT Objects macro ADP$L_DEVSLOT_COUNT = 580,0,32,1 %; ! Number of Device SLOT Objects ! Cells that describe the 32-bit Direct DMA window ! macro ADP$Q_DMA_BASE_PA = 584,0,0,0 %; literal ADP$S_DMA_BASE_PA = 8; ! Base physical address of window macro ADP$Q_DMA_SIZE = 592,0,0,0 %; literal ADP$S_DMA_SIZE = 8; ! Size of window macro ADP$Q_DMA_PABA_32 = 600,0,0,0 %; literal ADP$S_DMA_PABA_32 = 8; ! PA to bus address offset ! Cells that describe the 64-bit Direct DMA window ! macro ADP$Q_DMA_PABA_64 = 608,0,0,0 %; literal ADP$S_DMA_PABA_64 = 8; ! PA to bus address offset ! ! ! This cell contains a pointer to the System Vector Map ! and is initialized by GPS$IRQ_SUPPPORT.C::irq$$init(). ! macro ADP$Q_SYS_VEC_MAP = 616,0,0,0 %; literal ADP$S_SYS_VEC_MAP = 8; macro ADP$PS_SYS_VEC_MAP = 616,0,32,1 %; ! ! ! This cell contains a pointer to an IO Access Data block ! defined in [IVMSLOA]LOCALDEFS.H as IORW_DATA. The cell ! is used in GPS$IO_SUPPORT to record salient details of ! the most recent IO Read attempt. ! macro ADP$Q_LAST_IO_READ = 624,0,0,0 %; literal ADP$S_LAST_IO_READ = 8; macro ADP$PS_LAST_IO_READ = 624,0,32,1 %; ! ! ! This cell contains a pointer to an IO Access Data block ! defined in [IVMSLOA]LOCALDEFS.H as IORW_DATA. The cell ! is used in GPS$IO_SUPPORT to record salient details of ! the most recent IO Write attempt. ! macro ADP$Q_LAST_IO_WRITE = 632,0,0,0 %; literal ADP$S_LAST_IO_WRITE = 8; macro ADP$PS_LAST_IO_WRITE = 632,0,32,1 %; ! ! ! This cell contains a pointer to the Vital Product Data (VPD). ! This is used by each device driver that supports VPD. ! macro ADP$Q_VPD = 640,0,0,0 %; literal ADP$S_VPD = 8; macro ADP$PS_VPD = 640,0,32,1 %; macro ADP$Q_TRA_PORTIO = 648,0,0,0 %; literal ADP$S_TRA_PORTIO = 8; ! TRA for Port IO space. macro ADP$Q_CID_LIST = 656,0,0,0 %; literal ADP$S_CID_LIST = 8; ! Pointer to the CID list macro ADP$PS_CID_LIST = 656,0,32,1 %; ! copied from ACPI macro ADP$Q_RESERVED24 = 664,0,0,0 %; literal ADP$S_RESERVED24 = 8; ! Reserved for future expansion literal ADP$K_CIADPLEN = 672; ! Length of ADP for CI literal ADP$C_CIADPLEN = 672; ! Length of ADP for CI literal ADP$K_NIADPLEN = 672; ! Length of ADP for NI literal ADP$C_NIADPLEN = 672; ! Length of ADP for NI literal ADP$K_GBIADPLEN = 672; ! Length of ADP for Generic BI device literal ADP$C_GBIADPLEN = 672; ! Length of ADP for Generic BI device literal ADP$K_MINADPLEN = 672; ! Length of smallest available ADP literal ADP$C_MINADPLEN = 672; ! Length of smallest available ADP literal ADP$S_ADPDEF = 672; ! Old ADP size field for compatiblity !*** MODULE $BUSARRAYDEF *** ! + ! Bus Array -- each node on a bus has an entry in the Bus Array for that bus. ! ! A Bus Array is pointed to by a field in the ADP. A Bus Array consists ! of a header and a number of entries (one for each node on the bus or one ! for each channel on an adapter). ! Each entry contains info on the node, such as hardware id, base CSR ! address, a pointer to a data structure, and node number. ! ! - ! Define Bus Array Entry ! ================================================================ ! BUSARRAYENTRY ! ================================================================ ! Characterizes hardware connected to the bus adapter represented ! by the ADP. The Bus Array is comprised of a number of these ! BUSARRAYENTRYs, one for each node on the bus. ! literal BUSARRAY$M_NO_RECONNECT = %X'1'; literal BUSARRAY$M_MSI = %X'2'; literal BUSARRAY$M_INVALID_BAE = %X'4'; literal BUSARRAY$M_SPAREBIT03 = %X'8'; literal BUSARRAY$M_MULTI = %X'10'; literal BUSARRAY$M_CHANNEL = %X'20'; literal BUSARRAY$M_PCI_BRIDGE = %X'40'; literal BUSARRAY$M_NO_DRIVER = %X'80'; literal BUSARRAY$M_INT_ENABLED = %X'100'; literal BUSARRAY$M_DELMODE = %X'E00'; literal BUSARRAY$M_POLARITY = %X'1000'; literal BUSARRAY$M_TRIGMODE = %X'2000'; literal BUSARRAY$M_MSIX = %X'4000'; literal BUSARRAY$M_CONSOLE = %X'8000'; literal BUSARRAY$S_BUSARRAYENTRY = 272; macro BUSARRAY$Q_HW_ID = 0,0,0,0 %; literal BUSARRAY$S_HW_ID = 8; ! Hardware ID. macro BUSARRAY$W_PCI_VEND_ID = 0,0,16,0 %; ! Vendor ID macro BUSARRAY$W_PCI_DEV_ID = 2,0,16,0 %; ! Device ID macro BUSARRAY$W_PCI_SUBVEND_ID = 4,0,16,0 %; ! Subsytem Vendor ID macro BUSARRAY$W_PCI_SUBSYS_ID = 6,0,16,0 %; ! Subsystem (Device) ID macro BUSARRAY$L_PCI_DEV_VEND_ID = 0,0,32,0 %; ! Device & Vendor ID macro BUSARRAY$L_PCI_SUBSYS_VEND_ID = 4,0,32,0 %; ! Subsystem Vendor & subsys ID macro BUSARRAY$Q_CSR = 8,0,0,0 %; literal BUSARRAY$S_CSR = 8; ! Base CSR address macro BUSARRAY$Q_NODE_NUMBER = 16,0,0,1 %; literal BUSARRAY$S_NODE_NUMBER = 8; macro BUSARRAY$L_NODE_NUMBER_L = 16,0,32,1 %; macro BUSARRAY$L_NODE_NUMBER = 16,0,32,1 %; macro BUSARRAY$L_NODE_NUMBER_H = 20,0,32,1 %; macro BUSARRAY$L_FLAGS = 24,0,32,0 %; ! Flags macro BUSARRAY$V_NO_RECONNECT = 24,0,1,0 %; macro BUSARRAY$V_MSI = 24,1,1,0 %; ! PCI 2.2 & PCIX message signaled interrupts. macro BUSARRAY$V_INVALID_BAE = 24,2,1,0 %; ! Invalid BAE - ignore. macro BUSARRAY$V_SPAREBIT03 = 24,3,1,0 %; ! A named bit for future needs. macro BUSARRAY$V_MULTI = 24,4,1,0 %; ! multi-function or multi-channel device macro BUSARRAY$V_CHANNEL = 24,5,1,0 %; ! This BUSARRAYENTRY is a channel macro BUSARRAY$V_PCI_BRIDGE = 24,6,1,0 %; ! PCI-PCI Bridge device macro BUSARRAY$V_NO_DRIVER = 24,7,1,0 %; ! No entry in SYS$CONFIG.DAT macro BUSARRAY$V_INT_ENABLED = 24,8,1,0 %; macro BUSARRAY$V_DELMODE = 24,9,3,0 %; literal BUSARRAY$S_DELMODE = 3; ! IOSAPIC delivery mode macro BUSARRAY$V_POLARITY = 24,12,1,0 %; ! 0=Active-hi, 1=Active-lo macro BUSARRAY$V_TRIGMODE = 24,13,1,0 %; ! 0=Edge, 1=Level macro BUSARRAY$V_MSIX = 24,14,1,0 %; ! MSI-X interrupt deivery macro BUSARRAY$V_CONSOLE = 24,15,1,0 %; ! The one and only console device macro BUSARRAY$PS_CRB = 28,0,32,1 %; ! Pointer to Channel Request Block macro BUSARRAY$PS_ADP = 32,0,32,1 %; ! Pointer to subordinate ADP macro BUSARRAY$L_AUTOCONFIG = 36,0,32,0 %; ! Reserved for Autoconfigure macro BUSARRAY$PS_AUTOCONFIG = 36,0,32,1 %; ! Reserved for Autoconfigure macro BUSARRAY$L_CTRLLTR = 40,0,32,0 %; macro BUSARRAY$B_CTRLLTR = 40,0,8,0 %; ! Make sure the following quadword stays aligned properly macro BUSARRAY$Q_BUS_SPECIFIC = 48,0,0,0 %; literal BUSARRAY$S_BUS_SPECIFIC = 8; macro BUSARRAY$L_BUS_SPECIFIC_L = 48,0,32,0 %; macro BUSARRAY$PS_BUS_SPECIFIC_L = 48,0,32,1 %; macro BUSARRAY$L_INT_VEC = 48,0,32,0 %; ! Offset into SCB or vector table macro BUSARRAY$L_SYS_IRQ = 48,0,32,0 %; ! System IRQ (4*SYS_IRQ = vector table offset) macro BUSARRAY$L_SCB_OFFSET = 48,0,32,0 %; ! Offset into the SCB macro BUSARRAY$L_BUS_SPECIFIC_H = 52,0,32,0 %; macro BUSARRAY$PS_BUS_SPECIFIC_H = 52,0,32,1 %; macro BUSARRAY$L_BUS_SPECIFIC_1 = 52,0,32,0 %; macro BUSARRAY$PS_BUS_SPECIFIC_1 = 52,0,32,1 %; macro BUSARRAY$L_BUS_SPECIFIC_2 = 56,0,32,0 %; macro BUSARRAY$PS_BUS_SPECIFIC_2 = 56,0,32,1 %; macro BUSARRAY$PS_BAX = 56,0,32,1 %; macro BUSARRAY$Q_HW_HANDLE = 64,0,0,0 %; literal BUSARRAY$S_HW_HANDLE = 8; ! An opaque handle used to map this entry to its hardware macro BUSARRAY$Q_PARENT_HH = 72,0,0,0 %; literal BUSARRAY$S_PARENT_HH = 8; ! Hardware handle of this entry's parent macro BUSARRAY$L_GSIN = 80,0,32,1 %; ! Global System Interrupt Number macro BUSARRAY$L_IVEC = 84,0,32,1 %; ! Assigned Interrupt vector (see DIDTDEF and SAPICDEF) macro BUSARRAY$PS_IOSAPIC = 88,0,32,1 %; ! System address of the IOSAPIC for this device. macro BUSARRAY$R_CBB_CPU_AFFINITY = 96,0,0,0 %; literal BUSARRAY$S_CBB_CPU_AFFINITY = 48; ! Embedded CBB block macro BUSARRAY$L_CPU_AFFINITY = 144,0,32,0 %; ! Identifies CPU the device is interrupting on macro BUSARRAY$Q_CPU_AFFINITY = 144,0,0,0 %; literal BUSARRAY$S_CPU_AFFINITY = 8; ! Identifies CPU the device is interrupting on literal BUSARRAYENTRY$K_LENGTH = 272; ! ================================================================ ! BUSARRAY_HEADER ! ================================================================ ! Descriptor for the Bus Array hanging off the ADP. ! literal BUSARRAYHEADER$K_LENGTH = 24; ! Keep length before ENTRY_LIST, which has no real ! length literal BUSARRAY$S_BUSARRAYHEADER = 24; ! Old size name literal BUSARRAY$S_BUSARRAY_HEADER = 296; macro BUSARRAY$PS_PARENT_ADP = 0,0,32,1 %; ! Point back to ADP macro BUSARRAY$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro BUSARRAY$B_TYPE = 10,0,8,0 %; ! Structure type macro BUSARRAY$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro BUSARRAY$L_BUS_TYPE = 12,0,32,0 %; ! Bus Type code macro BUSARRAY$L_BUS_NODE_CNT = 16,0,32,0 %; ! Number of entries in Bus Array macro BUSARRAY$Q_ENTRY_LIST = 24,0,0,1 %; literal BUSARRAY$S_ENTRY_LIST = 8; ! Bus Array entries start ! at entry_list macro BUSARRAY$R_BUS_ARRAY_ENTRY = 24,0,0,0 %; literal BUSARRAY$S_BUS_ARRAY_ENTRY = 272; ! First bus array in the list ! ================================================================ ! BAX - BUSARRAYENTRY EXTENSION ! ================================================================ ! This structure is the BusArray eXtension and provides more ! detail for the characterization of the hardware represented ! by the BUSARRAYENTRY. ! literal BAX$K_LENGTH = 112; literal BAX$S_BAX = 112; ! ! ! The following field points back to the ADP on which this BAX ! resides. ! macro BAX$PS_PARENT_ADP = 0,0,32,1 %; ! Mother ADP ! ! ! This field points back to the BUSARRAYENTRY that "owns" this BAX ! instance. ! macro BAX$PS_PARENT_BAE = 4,0,32,1 %; ! ! ! -------------------------------------------------------------- ! General Data ! -------------------------------------------------------------- ! macro BAX$L_CHANNEL = 8,0,32,0 %; ! Channel number macro BAX$PS_VEC_LIST = 12,0,32,1 %; ! Interrupt Vectors List see IOCDEF macro BAX$L_INT_MECH = 16,0,32,0 %; ! Interrupt delivery mechanism ! ! ! -------------------------------------------------------------- ! Descriptor for Bus-specific data buffer. ! -------------------------------------------------------------- ! For PCI busses, this is a snapshot of the Config Header. ! macro BAX$Q_BUS_DATA_AREA = 24,0,0,1 %; literal BAX$S_BUS_DATA_AREA = 32; macro BAX$L_BUS_DATA_SIZE = 24,0,32,0 %; macro BAX$L_BUS_DATA_TYPE = 28,0,32,0 %; macro BAX$PS_BUS_DATA = 32,0,32,1 %; ! ! ! -------------------------------------------------------------- ! Interrupt Routine Pointers ! -------------------------------------------------------------- ! Since PCI-X, it has been possible for devices on the same bus ! to use different interrupt technologies. These fields provide ! long (64-bit) and short (32-bit) pointers to the device-specific ! Interrupt Init, Enable, Disable, and Redirection routines. These ! fields are initialized with the appropriate routine pointer when ! the interrupt technology is determined (IOSAPIC, MSI, MSI-X...), ! during device configuration. The IRQ init and node_function ! routines will call through these pointers to the correct routine ! for the device. ! macro BAX$PS_MSIABS = 56,0,32,1 %; macro BAX$PS_INIT_INTERRUPT = 60,0,32,1 %; macro BAX$PS_ENABLE_INTERRUPT = 64,0,32,1 %; macro BAX$PS_DISABLE_INTERRUPT = 68,0,32,1 %; macro BAX$PS_REDIRECT_INTERRUPT = 72,0,32,1 %; ! ! ! -------------------------------------------------------------- ! Multiple Vector Interrupt Routines and Data ! -------------------------------------------------------------- macro BAX$PS_MVI_DATA = 76,0,32,1 %; macro BAX$PS_MVI_REQUEST_VECTORS = 80,0,32,1 %; macro BAX$PS_MVI_MAP_VECTOR = 84,0,32,1 %; macro BAX$PS_MVI_DISPATCH_VTE = 88,0,32,1 %; ! MSIX only macro BAX$PS_MVI_DISPATCH_UNIQUE = 92,0,32,1 %; macro BAX$PS_MVI_DISPATCH_VECTOR = 96,0,32,1 %; macro BAX$PS_MVI_MASK_VECTOR = 100,0,32,1 %; macro BAX$PS_MVI_UNMASK_VECTOR = 104,0,32,1 %; macro BAX$PS_MVI_PENDING_VECTOR = 108,0,32,1 %; ! ! ! Fill to quadword boundary ! !*** MODULE $PCBDEF *** ! ! Software Process Control Block Definitions ! literal PCB$M_RES = %X'1'; literal PCB$M_DELPEN = %X'2'; literal PCB$M_FORCPEN = %X'4'; literal PCB$M_INQUAN = %X'8'; literal PCB$M_PSWAPM = %X'10'; literal PCB$M_RESPEN = %X'20'; literal PCB$M_SSFEXC = %X'40'; literal PCB$M_SSFEXCE = %X'80'; literal PCB$M_SSFEXCS = %X'100'; literal PCB$M_SSFEXCU = %X'200'; literal PCB$M_SSRWAIT = %X'400'; literal PCB$M_SUSPEN = %X'800'; literal PCB$M_WALL = %X'2000'; literal PCB$M_BATCH = %X'4000'; literal PCB$M_NOACNT = %X'8000'; literal PCB$M_NOSUSPEND = %X'10000'; literal PCB$M_ASTPEN = %X'20000'; literal PCB$M_PHDRES = %X'40000'; literal PCB$M_HIBER = %X'80000'; literal PCB$M_LOGIN = %X'100000'; literal PCB$M_NETWRK = %X'200000'; literal PCB$M_PWRAST = %X'400000'; literal PCB$M_NODELET = %X'800000'; literal PCB$M_DISAWS = %X'1000000'; literal PCB$M_INTER = %X'2000000'; literal PCB$M_RECOVER = %X'4000000'; literal PCB$M_HARDAFF = %X'10000000'; literal PCB$M_ERDACT = %X'20000000'; literal PCB$M_SOFTSUSP = %X'40000000'; literal PCB$M_PREEMPTED = %X'80000000'; literal PCB$M_QUANTUM_RESCHED = %X'1'; literal PCB$M_DISABLE_PREEMPT_PKTA_LOCK = %X'2'; literal PCB$M_FREDLOCK = %X'4'; literal PCB$M_PHDLOCK = %X'8'; literal PCB$M_TCB = %X'10'; literal PCB$M_TBS_STATE_PENDING = %X'20'; literal PCB$M_SS_LOGGING_ENABLE = %X'40'; literal PCB$M_SS_LOGGING_PERM = %X'80'; literal PCB$M_BRK_RUNDOWN_LOADED = %X'100'; literal PCB$M_CLASS_SCHED_PERM = %X'8000'; literal PCB$M_TERM_NOTIFY = %X'10000'; literal PCB$M_BYTLM_LOAN = %X'20000'; literal PCB$M_DISABLE_PREEMPT = %X'40000'; literal PCB$M_NOUNSHELVE = %X'80000'; literal PCB$M_SHELVING_RESERVED = %X'100000'; literal PCB$M_CLASS_SCHEDULED = %X'200000'; literal PCB$M_CLASS_SUPPLIED = %X'400000'; literal PCB$M_IN_TBS_STATE = %X'800000'; literal PCB$M_WINDFALL = %X'1000000'; literal PCB$M_NOTIFY = %X'2000000'; literal PCB$M_SINGLE_THREADED = %X'3C000000'; literal PCB$M_RWAST = %X'40000000'; literal PCB$M_SOFT_SINGLE_THREAD = %X'80000000'; literal PCB$M_EPID_WILD = %X'80000000'; literal PCB$M_FORK = %X'1'; literal PCB$K_SCHED_OTHER = 0; ! Native VMS policy (MBZ) literal PCB$K_SCHED_FIFO = 1; ! POSIX FIFO policy literal PCB$K_SCHED_RR = 2; ! POSIX Round-Robbin policy ! [1..10] for POSIX literal PCB$K_SCHED_POLICY_CNT = 3; ! # legal sched policies literal PCB$K_ALL_THREADS = -2147483648; ! policy affects all kernel threads literal PCB$K_MAX_KT_COUNT = 256; ! Absolute maximum number of kernel threads literal PCB$M_EVENT_NO_FLAG = %X'1'; literal PCB$M_IN_DELPAG = %X'1'; literal PCB$M_WAKEPEN = %X'1000'; literal PCB$M_SECAUDIT = %X'8000000'; literal PCB$M_UPCALL_AST_BLOCKED = %X'80000000'; literal PCB$M_SUGID_IMAGE = %X'1'; literal PCB$M_SUGID_PROCESS = %X'2'; literal PCB$S_PCB = 2352; macro PCB$L_SQFL = 0,0,32,1 %; ! State queue forward link macro PCB$L_SQBL = 4,0,32,1 %; ! State queue backward link macro PCB$W_SIZE = 8,0,16,0 %; ! Size, in bytes macro PCB$B_TYPE = 10,0,8,0 %; ! Structure type code for PCB macro PCB$L_AST_PENDING = 12,0,32,0 %; ! AST pending mask macro PCB$Q_PHYPCB = 16,0,0,0 %; literal PCB$S_PHYPCB = 8; ! Physical address of HWPCB macro PCB$Q_LEFC_SWAPPED = 24,0,0,0 %; literal PCB$S_LEFC_SWAPPED = 8; ! Local event flags - swapped macro PCB$L_LEFC_0_SWAPPED = 24,0,32,0 %; ! Cluster 0 macro PCB$L_LEFC_1_SWAPPED = 28,0,32,0 %; ! Cluster 1 macro PCB$L_ASTQFL_SPK = 32,0,32,1 %; ! Special kernel AST queue forward link (head) macro PCB$L_ASTQBL_SPK = 36,0,32,1 %; ! Special kernel AST queue back link (tail) macro PCB$L_ASTQFL_K = 40,0,32,1 %; ! Kernel AST queue forward link (head) macro PCB$L_ASTQBL_K = 44,0,32,1 %; ! Kernel AST queue back link (tail) macro PCB$L_ASTQFL_E = 48,0,32,1 %; ! Executive AST queue forward link (head) macro PCB$L_ASTQBL_E = 52,0,32,1 %; ! Executive AST queue back link (tail) macro PCB$L_ASTQFL_S = 56,0,32,1 %; ! Supervisor AST queue forward link (head) macro PCB$L_ASTQBL_S = 60,0,32,1 %; ! Supervisor AST queue back link (tail) macro PCB$L_ASTQFL_U = 64,0,32,1 %; ! User AST queue forward link (head) macro PCB$L_ASTQBL_U = 68,0,32,1 %; ! User AST queue back link (tail) macro PCB$L_PRVCPU = 72,0,32,1 %; ! Previous CPU (not current CPU) macro PCB$L_CPU_ID = 76,0,32,1 %; ! Current CPU (last one to load context) macro PCB$Q_PRVASN = 80,0,0,0 %; literal PCB$S_PRVASN = 64; ! Previous ASN/RID (1 per region) macro PCB$Q_PRVASNSEQ = 144,0,0,0 %; literal PCB$S_PRVASNSEQ = 8; ! Previous ASN/RID Sequence Number macro PCB$Q_ONCPUCNT = 152,0,0,0 %; literal PCB$S_ONCPUCNT = 8; ! Count of threads in CUR state macro PCB$L_ASTACT = 160,0,32,0 %; ! Access modes with active ASTs macro PCB$L_STATE = 164,0,32,0 %; ! Process state macro PCB$L_PRI = 168,0,32,0 %; ! Process current priority macro PCB$L_PRIB = 172,0,32,0 %; ! Base priority macro PCB$L_AFFINITY_SKIP = 176,0,32,0 %; ! Affinity skip count macro PCB$L_OWNER = 180,0,32,0 %; ! EPID of owner, if a subprocess macro PCB$L_STS = 184,0,32,0 %; ! Process status flags macro PCB$V_RES = 184,0,1,0 %; ! Resident, in balance set macro PCB$V_DELPEN = 184,1,1,0 %; ! Delete pending macro PCB$V_FORCPEN = 184,2,1,0 %; ! Force exit pending macro PCB$V_INQUAN = 184,3,1,0 %; ! Initial quantum in progress macro PCB$V_PSWAPM = 184,4,1,0 %; ! Process swap mode, 1=NOSWAP macro PCB$V_RESPEN = 184,5,1,0 %; ! Resume pending, skip suspend macro PCB$V_SSFEXC = 184,6,1,0 %; ! System service exception enable (K) macro PCB$V_SSFEXCE = 184,7,1,0 %; ! System service exception enable (E) macro PCB$V_SSFEXCS = 184,8,1,0 %; ! System service exception enable (S) macro PCB$V_SSFEXCU = 184,9,1,0 %; ! System service exception enable (U) macro PCB$V_SSRWAIT = 184,10,1,0 %; ! System service resource wait disable macro PCB$V_SUSPEN = 184,11,1,0 %; ! Suspend pending macro PCB$V_WALL = 184,13,1,0 %; ! Wait for all events in mask macro PCB$V_BATCH = 184,14,1,0 %; ! Process is a batch job macro PCB$V_NOACNT = 184,15,1,0 %; ! No accounting for process macro PCB$V_NOSUSPEND = 184,16,1,0 %; ! Process cannot be suspended macro PCB$V_ASTPEN = 184,17,1,0 %; ! AST pending macro PCB$V_PHDRES = 184,18,1,0 %; ! Process header resident macro PCB$V_HIBER = 184,19,1,0 %; ! Hibernate after initial image activate macro PCB$V_LOGIN = 184,20,1,0 %; ! Login without reading UAF macro PCB$V_NETWRK = 184,21,1,0 %; ! Network connect job macro PCB$V_PWRAST = 184,22,1,0 %; ! Power fail AST macro PCB$V_NODELET = 184,23,1,0 %; ! No delete macro PCB$V_DISAWS = 184,24,1,0 %; ! Disable automatic WS adjustment macro PCB$V_INTER = 184,25,1,0 %; ! Process is an interactive job macro PCB$V_RECOVER = 184,26,1,0 %; ! Process can recover locks macro PCB$V_HARDAFF = 184,28,1,0 %; ! Process is bound to particular CPU macro PCB$V_ERDACT = 184,29,1,0 %; ! Exec mode rundown active macro PCB$V_SOFTSUSP = 184,30,1,0 %; ! Process is in "soft" suspend macro PCB$V_PREEMPTED = 184,31,1,0 %; ! Hard suspend has preempted soft macro PCB$L_STS2 = 188,0,32,0 %; ! Process status flags (2nd LW) macro PCB$V_QUANTUM_RESCHED = 188,0,1,0 %; ! Quantum-oriented process reschedule macro PCB$V_DISABLE_PREEMPT_PKTA_LOCK = 188,1,1,0 %; ! Disable preempt locked the PKTA macro PCB$V_FREDLOCK = 188,2,1,0 %; ! Don't swap PHD -- process has FRED pages macro PCB$V_PHDLOCK = 188,3,1,0 %; ! Don't swap PHD -- process has $LCKPAG pages macro PCB$V_TCB = 188,4,1,0 %; ! TCB process macro PCB$V_TBS_STATE_PENDING = 188,5,1,0 %; ! Going to TBS, but not on the queue yet macro PCB$V_SS_LOGGING_ENABLE = 188,6,1,0 %; ! Enable system service logging macro PCB$V_SS_LOGGING_PERM = 188,7,1,0 %; ! Logging persists across image rundown macro PCB$V_BRK_RUNDOWN_LOADED = 188,8,1,0 %; ! image rundown handler loaded by $BRKTHRU macro PCB$V_CLASS_SCHED_PERM = 188,15,1,0 %; ! process is part of permanent scheduling class macro PCB$V_TERM_NOTIFY = 188,16,1,0 %; ! termination notification macro PCB$V_BYTLM_LOAN = 188,17,1,0 %; ! Process has received rundown BYTLIM loan macro PCB$V_DISABLE_PREEMPT = 188,18,1,0 %; ! Allow process to prevent preemption macro PCB$V_NOUNSHELVE = 188,19,1,0 %; ! if set, don't auto-unshelve macro PCB$V_SHELVING_RESERVED = 188,20,1,0 %; ! Reserved for shelving facility macro PCB$V_CLASS_SCHEDULED = 188,21,1,0 %; ! This process is class scheduled macro PCB$V_CLASS_SUPPLIED = 188,22,1,0 %; ! This process has been assigned a class, ! or an explicit "No class" (happens only ! when CLASS_SCHEDULED is cleared) macro PCB$V_IN_TBS_STATE = 188,23,1,0 %; ! This process is in TBS state macro PCB$V_WINDFALL = 188,24,1,0 %; ! Process eligible for windfall macro PCB$V_NOTIFY = 188,25,1,0 %; ! Send process termination msg. to CSP macro PCB$V_SINGLE_THREADED = 188,26,4,0 %; literal PCB$S_SINGLE_THREADED = 4; ! single threaded bits, 1 per mode macro PCB$V_RWAST = 188,30,1,0 %; ! A thread is in RWAST macro PCB$V_SOFT_SINGLE_THREAD = 188,31,1,0 %; ! ASTs allowed during $single_thread macro PCB$L_PRISAV = 192,0,32,0 %; ! Saved current priority macro PCB$L_PRIBSAV = 196,0,32,0 %; ! Saved base priority macro PCB$L_AUTHPRI = 200,0,32,0 %; ! Initial process priority macro PCB$L_ONQTIME = 204,0,32,0 %; ! Abs time when placed on COM/COMO queue, ! adjusted for process wait time macro PCB$L_WAITIME = 208,0,32,0 %; ! Abs time of last process event macro PCB$L_ASTCNT = 212,0,32,0 %; ! AST count remaining macro PCB$L_BIOCNT = 216,0,32,0 %; ! Buffered I/O count remaining macro PCB$L_BIOLM = 220,0,32,0 %; ! Buffered I/O limit macro PCB$L_DIOCNT = 224,0,32,1 %; ! Direct I/O count remaining macro PCB$L_DIOLM = 228,0,32,1 %; ! Direct I/O count limit macro PCB$L_PRCCNT = 232,0,32,0 %; ! Subprocess count macro PCB$PS_IBRVEC = 236,0,32,1 %; ! Instruction break register array ptr (IA64) macro PCB$PS_DBRVEC = 240,0,32,1 %; ! Data break register array ptr (IA64) macro PCB$L_WEFC = 244,0,32,0 %; ! Waiting EF cluster number macro PCB$L_EFWM = 248,0,32,0 %; ! Event flag wait mask macro PCB$L_EFCS = 252,0,32,0 %; ! Local event flag cluster, system macro PCB$L_EFCU = 256,0,32,0 %; ! Local event flag cluster, user macro PCB$L_EFC2P = 260,0,32,1 %; ! Pointer to global cluster #2 macro PCB$L_EFC3P = 264,0,32,1 %; ! Pointer to global cluster #3 macro PCB$W_PGFLCHAR = 260,0,16,0 %; ! Page file characteristics macro PCB$B_PGFLINDEX = 262,0,8,0 %; ! Desired SYSTEM page file index macro PCB$L_PID = 268,0,32,0 %; ! Process ID used by exec on local node only ! ! *** WARNING - THE INTERNAL STRUCTURE OF THE EPID IS SUBJECT TO RADICAL CHANGE BETWEEN ! *** VERSIONS OF VMS. NO ASSUMPTIONS SHOULD EVER BE MADE ABOUT ITS FORMAT ! macro PCB$L_EPID = 272,0,32,0 %; ! Cluster-wide process ID seen by the world macro PCB$V_EPID_PROC = 272,0,21,0 %; literal PCB$S_EPID_PROC = 21; ! Process ID field, can convert to PCB$l_pid macro PCB$V_EPID_NODE_IDX = 272,21,8,0 %; literal PCB$S_EPID_NODE_IDX = 8; ! IDX - index to table of node identifications macro PCB$V_EPID_NODE_SEQ = 272,29,2,0 %; literal PCB$S_EPID_NODE_SEQ = 2; ! SEQ - sequence number for node table entry reuse macro PCB$V_EPID_WILD = 272,31,1,0 %; ! Flag that EPID is wildcard context for $GETJPI, ! and not a valid EPID macro PCB$L_EOWNER = 276,0,32,0 %; ! EPID of process owner macro PCB$L_APTCNT = 280,0,32,0 %; ! Active page table count on outswap macro PCB$L_MTXCNT = 284,0,32,0 %; ! Count of mutex semaphores owned macro PCB$L_GPGCNT = 288,0,32,0 %; ! Global page count in WS macro PCB$L_PPGCNT = 292,0,32,0 %; ! Process page count in WS macro PCB$L_WSSWP = 296,0,32,1 %; ! Swap file disk address macro PCB$L_SWAPSIZE = 300,0,32,0 %; ! Swap block allocation macro PCB$L_PHD = 304,0,32,1 %; ! Address of Process Header macro PCB$L_JIB = 308,0,32,1 %; ! Address of Job Information Block macro PCB$R_PCBARB = 312,0,0,0 %; literal PCB$S_PCBARB = 124; macro PCB$Q_PRIV = 312,0,0,0 %; literal PCB$S_PRIV = 8; ! Current privilege mask macro PCB$L_ARB = 320,0,32,1 %; ! Address of Access Rights Block macro PCB$L_UIC = 372,0,32,0 %; ! Logon UIC of process macro PCB$W_MEM = 372,0,16,0 %; ! Member number in UIC macro PCB$W_GRP = 374,0,16,0 %; ! Group number in UIC macro PCB$L_ORB = 436,0,32,1 %; ! Address of process ORB macro PCB$L_TMBU = 440,0,32,0 %; ! Termination mailbox unit number macro PCB$L_HOME_RAD = 444,0,32,0 %; ! Number of the RAD that contains most process memory macro PCB$L_DLCKPRI = 452,0,32,1 %; ! Deadlock resolution priority macro PCB$L_DEFPROT = 456,0,32,0 %; ! Process default protection macro PCB$L_PMB = 460,0,32,1 %; ! PMB address macro PCB$L_AFFINITY = 464,0,32,1 %; ! CPU ID for affinity macro PCB$L_CAPABILITY = 468,0,32,0 %; ! CPU capability selection bitmask macro PCB$L_CPUTIM = 472,0,32,0 %; ! Accumulated CPU time at last outswap macro PCB$T_LNAME = 476,0,0,0 %; literal PCB$S_LNAME = 16; ! Process name macro PCB$L_PRCPDB = 492,0,32,1 %; ! Address of process Performance Data Block ! **** For DIGITAL software use only ***** macro PCB$L_PIXHIST = 496,0,32,0 %; ! PIXSCAN history summary LW (bitmask) macro PCB$L_AFFINITY_CALLBACK = 500,0,32,1 %; ! Callback for breaking affinity macro PCB$L_PERMANENT_CAPABILITY = 504,0,32,0 %; ! Permanent capability mask macro PCB$Q_CWPSSRV_QUEUE = 512,0,0,0 %; literal PCB$S_CWPSSRV_QUEUE = 8; ! CWPS service block queue macro PCB$L_CAPABILITY_SEQ = 524,0,32,1 %; ! Copy of last sequence number macro PCB$Q_BUFOBJ_LIST = 528,0,0,0 %; literal PCB$S_BUFOBJ_LIST = 8; ! Defined buffer objects queue head macro PCB$L_AST_BLOCKED = 536,0,32,0 %; ! AST blocked bits macro PCB$L_CLASS_QUANT = 540,0,32,1 %; ! Address of cell containing class quantum macro PCB$W_CLASS_EXTRA_TICKS = 544,0,16,0 %; ! if class scheduled, extra ticks given to this KTB macro PCB$B_PKTA_LOCK = 546,0,8,0 %; ! Number of lockers of PKTA structure macro PCB$b_fill_2 = 547,0,8,0 %; macro PCB$A_CURRENT_TX = 548,0,32,0 %; ! Pointer to process default transaction macro PCB$A_CURRENT_CD = 552,0,32,0 %; ! Pointer to process default commit domain macro PCB$A_CURRENT_VERTEX = 556,0,32,0 %; ! Pointer to process default execution vertex macro PCB$Q_XSCB_QUE = 560,0,0,0 %; literal PCB$S_XSCB_QUE = 8; ! Transaction Segment list macro PCB$A_XSCB_FLINK = 560,0,32,0 %; macro PCB$A_XSCB_BLINK = 564,0,32,0 %; macro PCB$Q_RMCB_QUE = 568,0,0,0 %; literal PCB$S_RMCB_QUE = 8; ! Declared resource manager list macro PCB$A_RMCB_FLINK = 568,0,32,0 %; macro PCB$A_RMCB_BLINK = 572,0,32,0 %; macro PCB$Q_CD_QUE = 576,0,0,0 %; literal PCB$S_CD_QUE = 8; ! Commit domain membership list macro PCB$A_CD_FLINK = 576,0,32,0 %; macro PCB$A_CD_BLINK = 580,0,32,0 %; macro PCB$L_DPC = 584,0,32,0 %; ! Delete pending count macro PCB$L_CPUTIME_REF = 588,0,32,0 %; ! CPUTIME at last TICK time macro PCB$L_ACC_WAITIME = 592,0,32,0 %; ! Accumulated wait time macro PCB$L_PRCSTR = 596,0,32,1 %; ! alternate procstrt macro PCB$L_XPCB = 600,0,32,1 %; ! address of the POSIX extended PCB macro PCB$L_PSX_FORK_STATUS = 604,0,32,0 %; ! POSIX fork status cell macro PCB$L_PSX_FLAGS = 608,0,32,0 %; ! POSIX flags macro PCB$V_FORK = 608,0,1,0 %; ! In fork synchronization macro PCB$L_PSX_ACTRTN = 612,0,32,1 %; ! POSIX fork action routine macro PCB$Q_PSX_ACTPRM = 616,0,0,0 %; literal PCB$S_PSX_ACTPRM = 8; ! POSIX fork action routine parameter macro PCB$L_KERNEL_COUNTER = 624,0,32,0 %; ! Per-process kernel mode counters macro PCB$L_EXEC_COUNTER = 628,0,32,0 %; ! Per-process exec mode counters macro PCB$L_SUPER_COUNTER = 632,0,32,0 %; ! Per-process super mode counters macro PCB$L_USER_COUNTER = 636,0,32,0 %; ! Per-process user mode counters macro PCB$L_SCHED_POLICY = 640,0,32,0 %; ! POSIX sched policy macro PCB$A_FREWSLE_CALLOUT = 644,0,32,0 %; ! Routine to notify of WSLE about to be removed macro PCB$L_FREWSLE_PARAM = 648,0,32,0 %; ! Parameter to pass to FREWSLE_CALLOUT routine macro PCB$L_PQB = 648,0,32,1 %; ! Pointer to Process Quota Block ! (process creation only) macro PCB$L_BUFOBJ_CNT = 652,0,32,0 %; ! Buffer object page count on outswap macro PCB$L_NOAUDIT = 656,0,32,0 %; ! count of reasons not to audit macro PCB$L_SOURCE_EPID = 660,0,32,0 %; ! Impersonation EPID macro PCB$Q_RDPB_QUE = 664,0,0,0 %; literal PCB$S_RDPB_QUE = 8; ! Resource Domain pointer block macro PCB$A_RDPB_FLINK = 664,0,32,0 %; macro PCB$A_RDPB_BLINK = 668,0,32,0 %; macro PCB$Q_FILES_64 = 672,0,0,0 %; literal PCB$S_FILES_64 = 8; ! s-64 bits and bobs macro PCB$Q_KEEP_IN_WS = 680,0,0,1 %; literal PCB$S_KEEP_IN_WS = 8; ! Base of range macro PCB$Q_KEEP_IN_WS2 = 688,0,0,1 %; literal PCB$S_KEEP_IN_WS2 = 8; ! End of range macro PCB$L_TQUANTUM = 700,0,32,0 %; ! Per user thread quantum macro PCB$L_MULTITHREAD = 704,0,32,0 %; ! Max Kthread count macro PCB$L_KT_COUNT = 708,0,32,0 %; ! Kthread count macro PCB$L_KT_HIGH = 712,0,32,0 %; ! highest ktb vector entry used macro PCB$L_KTBVEC = 716,0,32,1 %; ! KTB vector adddress macro PCB$L_WAKE_ACB = 720,0,32,1 %; ! WAKE upcall ACB address macro PCB$L_ST_ACK_COUNT = 724,0,32,0 %; ! Thread ACK cnt for $single_thread macro PCB$L_THREAD_EVENTS = 728,0,32,0 %; ! Events to pass notification to the thread manager macro PCB$V_EVENT_NO_FLAG = 728,0,1,0 %; ! The no-flag event macro PCB$L_POSTEF_ACB = 732,0,32,1 %; ! Postef upcall ACB macro PCB$Q_POSTEF = 736,0,0,0 %; literal PCB$S_POSTEF = 8; ! SET local event flags macro PCB$L_POSTEF1 = 736,0,32,0 %; ! Cluster 0 macro PCB$L_POSTEF2 = 740,0,32,0 %; ! Cluster 1 macro PCB$L_SWP_SEQ = 744,0,32,0 %; ! Outswap seq number macro PCB$L_SWP_KT = 748,0,32,0 %; ! Outswappable kt count macro PCB$L_IM_ASTQFL_SPK = 752,0,32,1 %; ! Special kernel AST queue forward link (head) macro PCB$L_IM_ASTQBL_SPK = 756,0,32,1 %; ! Special kernel AST queue back link (tail) macro PCB$L_IM_ASTQFL_K = 760,0,32,1 %; ! Kernel AST queue forward link (head) macro PCB$L_IM_ASTQBL_K = 764,0,32,1 %; ! Kernel AST queue back link (tail) macro PCB$L_IM_ASTQFL_E = 768,0,32,1 %; ! Executive AST queue forward link (head) macro PCB$L_IM_ASTQBL_E = 772,0,32,1 %; ! Executive AST queue back link (tail) macro PCB$PS_CCBSVA = 776,0,32,1 %; ! SVA of CCB for Fast-IO users macro PCB$L_MAXFIX = 780,0,32,0 %; ! Maximum fandle index macro PCB$PS_FANDLE = 784,0,32,1 %; ! Fandle vector for Fast-IO users macro PCB$Q_ST_KT_ARRAY = 792,0,0,0 %; literal PCB$S_ST_KT_ARRAY = 8; ! Single thread array of kernel thread ids macro PCB$AR_NATURAL_PSB = 800,0,32,1 %; ! Pointer to Natural Persona macro PCB$L_STS3 = 804,0,32,0 %; ! Process status flags macro PCB$V_IN_DELPAG = 804,0,1,0 %; ! Process has entered MMG$DELPAG_64_WORK macro PCB$V_WAKEPEN = 804,12,1,0 %; ! Wake pending, skip hibernate macro PCB$V_SECAUDIT = 804,27,1,0 %; ! Mandatory security auditing enabled macro PCB$V_UPCALL_AST_BLOCKED = 804,31,1,0 %; ! indicates that upcall ASTs are blocked macro PCB$L_INITIAL_KTB = 808,0,32,1 %; ! Initial KTB, overlays KTB$L_PCB macro PCB$L_PCB = 808,0,32,1 %; ! PCB, overlays PCB$L_INITIAL_KTB macro PCB$L_DEADLOCK_WAIT = 816,0,32,1 %; ! per-process deadlock wait macro PCB$L_CTX_WAITQ = 928,0,32,1 %; ! list of synch/context wait blocks macro PCB$Q_LOCKQFL = 936,0,0,1 %; literal PCB$S_LOCKQFL = 8; ! Lock queue forward link macro PCB$Q_LOCKQBL = 944,0,0,1 %; literal PCB$S_LOCKQBL = 8; ! Lock queue backward link macro PCB$L_CLASS_LINK = 992,0,32,1 %; ! Link PCB into scheduling class macro PCB$L_SESSION_ID = 996,0,32,1 %; ! Pointer to POSIX Session ID block macro PCB$L_PROCESS_GROUP = 1000,0,32,1 %; ! Pointer to POSIX Process Group block macro PCB$L_CREATOR = 1004,0,32,0 %; ! EPID of creator process (Unix-style parent) macro PCB$L_LCKRQ = 1008,0,32,0 %; ! pointer to LCKRQ packet macro PCB$Q_TQE_FLAGS = 1032,0,0,0 %; literal PCB$S_TQE_FLAGS = 8; ! TQE flags macro PCB$L_TIMER = 1032,0,32,0 %; ! Timer Request info macro PCB$L_WAKEUP = 1036,0,32,0 %; ! Wakeup Call info macro PCB$L_ACB_STALL_QUEUE = 1040,0,32,1 %; ! Address of ACB stall queue macro PCB$L_SPINLOCK = 1044,0,32,1 %; ! Address of the PCB specific spinlock macro PCB$L_DELPRC_FORCED = 1048,0,32,0 %; ! Mask of modes for which DELPRC forced exit is active macro PCB$L_IMAGE_PERSONA = 1052,0,32,0 %; ! Index of persona granted by an image, ! or of the POSIX/COE "Real" persona. macro PCB$L_SAVED_UID = 1056,0,32,0 %; ! UID saved from a SETUID operation macro PCB$L_SAVED_GID = 1060,0,32,0 %; ! GID saved from a SETGID operation macro PCB$L_IMAGE_FLAGS = 1064,0,32,0 %; ! process state determined by image activation macro PCB$V_SUGID_IMAGE = 1064,0,1,0 %; ! Running a SUID or SGID image macro PCB$V_SUGID_PROCESS = 1064,1,1,0 %; ! subprocess, decended from running a SGUID image macro PCB$R_CBB_PERM_CPU_AFFINITY = 1072,0,0,0 %; literal PCB$S_CBB_PERM_CPU_AFFINITY = 48; ! Embedded CBB block macro PCB$L_PERMANENT_CPU_AFFINITY = 1120,0,32,0 %; ! Permanent CPU affinity macro PCB$Q_PERMANENT_CPU_AFFINITY = 1120,0,0,0 %; literal PCB$S_PERMANENT_CPU_AFFINITY = 8; ! Permanent CPU affinity macro PCB$R_CBB_CURRENT_AFFINITY = 1248,0,0,0 %; literal PCB$S_CBB_CURRENT_AFFINITY = 48; ! Embedded CBB block macro PCB$L_CURRENT_AFFINITY = 1296,0,32,0 %; ! Current CPU mask macro PCB$Q_CURRENT_AFFINITY = 1296,0,0,0 %; literal PCB$S_CURRENT_AFFINITY = 8; ! Current CPU mask macro PCB$R_CBB_ACTIVE_CPUS = 1424,0,0,0 %; literal PCB$S_CBB_ACTIVE_CPUS = 48; ! Embedded CBB block macro PCB$L_ACTIVE_CPUS = 1472,0,32,0 %; ! CPUs owned by this process macro PCB$Q_ACTIVE_CPUS = 1472,0,0,0 %; literal PCB$S_ACTIVE_CPUS = 8; ! CPUs owned by this process macro PCB$R_CBB_AFFINITIES = 1600,0,0,0 %; literal PCB$S_CBB_AFFINITIES = 48; ! Embedded CBB block macro PCB$L_AFFINITIES = 1648,0,32,0 %; ! Thread affinity mask macro PCB$Q_AFFINITIES = 1648,0,0,0 %; literal PCB$S_AFFINITIES = 8; ! Thread affinity mask macro PCB$R_CBB_PERMANENT_AFFINITIES = 1776,0,0,0 %; literal PCB$S_CBB_PERMANENT_AFFINITIES = 48; ! Embedded CBB block macro PCB$L_PERMANENT_AFFINITIES = 1824,0,32,0 %; ! Thread permanent affinity mask macro PCB$Q_PERMANENT_AFFINITIES = 1824,0,0,0 %; literal PCB$S_PERMANENT_AFFINITIES = 8; ! Thread permanent affinity mask macro PCB$R_CBB_SAVED_AFFINITIES = 1952,0,0,0 %; literal PCB$S_CBB_SAVED_AFFINITIES = 48; ! Embedded CBB block macro PCB$L_SAVED_AFFINITIES = 2000,0,32,0 %; ! Thread saved affinity mask macro PCB$Q_SAVED_AFFINITIES = 2000,0,0,0 %; literal PCB$S_SAVED_AFFINITIES = 8; ! Thread saved affinity mask macro PCB$T_TERMINAL = 2128,0,0,0 %; literal PCB$S_TERMINAL = 16; ! Terminal device name string ! for interactive jobs macro PCB$L_KT_DELETED_THREAD_COUNT = 2152,0,32,0 %; ! Deleted kernel thread count macro PCB$Q_KERNEL_COUNTER_FRAC = 2168,0,0,0 %; literal PCB$S_KERNEL_COUNTER_FRAC = 8; ! Fractional tick for kernel mode macro PCB$Q_EXEC_COUNTER_FRAC = 2176,0,0,0 %; literal PCB$S_EXEC_COUNTER_FRAC = 8; ! Fractional tick for exec mode macro PCB$Q_SUPER_COUNTER_FRAC = 2184,0,0,0 %; literal PCB$S_SUPER_COUNTER_FRAC = 8; ! Fractional tick for super mode macro PCB$Q_USER_COUNTER_FRAC = 2192,0,0,0 %; literal PCB$S_USER_COUNTER_FRAC = 8; ! Fractional tick for user mode macro PCB$L_KT_LIMIT = 2264,0,32,1 %; macro PCB$L_SPARE = 2268,0,32,1 %; ! Pad to quadword; available for either KTB or PCB literal PCB$K_LENGTH = 2352; ! Length of PCB literal PCB$C_LENGTH = 2352; ! Length of PCB literal PCB$S_PCBDEF = 2352; ! Old PCB size for compatibility literal KTB$M_RES = %X'1'; literal KTB$M_DELPEN = %X'2'; literal KTB$M_FORCPEN = %X'4'; literal KTB$M_INQUAN = %X'8'; literal KTB$M_PSWAPM = %X'10'; literal KTB$M_RESPEN = %X'20'; literal KTB$M_SSFEXC = %X'40'; literal KTB$M_SSFEXCE = %X'80'; literal KTB$M_SSFEXCS = %X'100'; literal KTB$M_SSFEXCU = %X'200'; literal KTB$M_SSRWAIT = %X'400'; literal KTB$M_SUSPEN = %X'800'; literal KTB$M_WALL = %X'2000'; literal KTB$M_BATCH = %X'4000'; literal KTB$M_NOACNT = %X'8000'; literal KTB$M_NOSUSPEND = %X'10000'; literal KTB$M_ASTPEN = %X'20000'; literal KTB$M_PHDRES = %X'40000'; literal KTB$M_HIBER = %X'80000'; literal KTB$M_LOGIN = %X'100000'; literal KTB$M_NETWRK = %X'200000'; literal KTB$M_PWRAST = %X'400000'; literal KTB$M_NODELET = %X'800000'; literal KTB$M_DISAWS = %X'1000000'; literal KTB$M_INTER = %X'2000000'; literal KTB$M_RECOVER = %X'4000000'; literal KTB$M_HARDAFF = %X'10000000'; literal KTB$M_ERDACT = %X'20000000'; literal KTB$M_SOFTSUSP = %X'40000000'; literal KTB$M_PREEMPTED = %X'80000000'; literal KTB$M_QUANTUM_RESCHED = %X'1'; literal KTB$M_PHDLOCK = %X'8'; literal KTB$M_TCB = %X'10'; literal KTB$M_TBS_STATE_PENDING = %X'20'; literal KTB$M_CLASS_SCHED_PERM = %X'8000'; literal KTB$M_TERM_NOTIFY = %X'10000'; literal KTB$M_BYTLM_LOAN = %X'20000'; literal KTB$M_NOUNSHELVE = %X'80000'; literal KTB$M_SHELVING_RESERVED = %X'100000'; literal KTB$M_CLASS_SCHEDULED = %X'200000'; literal KTB$M_CLASS_SUPPLIED = %X'400000'; literal KTB$M_IN_TBS_STATE = %X'800000'; literal KTB$M_WINDFALL = %X'1000000'; literal KTB$M_NOTIFY = %X'2000000'; literal KTB$M_SINGLE_THREADED = %X'3C000000'; literal KTB$M_EPID_WILD = %X'80000000'; literal KTB$K_SCHED_OTHER = 0; ! Native VMS policy (MBZ) literal KTB$K_SCHED_FIFO = 1; ! POSIX FIFO policy literal KTB$K_SCHED_RR = 2; ! POSIX Round-Robbin policy ! [1..10] for POSIX literal KTB$K_SCHED_POLICY_CNT = 3; ! # legal sched policies literal KTB$M_WAKEPEN = %X'1000'; literal KTB$M_SECAUDIT = %X'8000000'; literal KTB$M_UPCALL_AST_BLOCKED = %X'80000000'; literal KTB$M_DELETE_PENDING = %X'1'; literal KTB$M_SCHED_CONTEXT_SAVED = %X'2'; literal KTB$M_SINGLE_THREAD_ACT = %X'3C'; literal KTB$M_TOLERANT = %X'40'; literal KTB$M_SOFT_RAD_AFFINITY = %X'80'; literal KTB$S_KTB = 2352; macro KTB$L_SQFL = 0,0,32,1 %; ! State queue forward link macro KTB$L_SQBL = 4,0,32,1 %; ! State queue backward link macro KTB$W_SIZE = 8,0,16,0 %; ! Size, in bytes macro KTB$B_TYPE = 10,0,8,0 %; ! Structure type code for KTB macro KTB$L_AST_PENDING = 12,0,32,0 %; ! AST pending mask macro KTB$Q_PHYPCB = 16,0,0,0 %; literal KTB$S_PHYPCB = 8; ! Physical address of HWPCB macro KTB$L_ASTQFL_SPK = 32,0,32,1 %; ! Special kernel AST queue forward link (head) macro KTB$L_ASTQBL_SPK = 36,0,32,1 %; ! Special kernel AST queue back link (tail) macro KTB$L_ASTQFL_K = 40,0,32,1 %; ! Kernel AST queue forward link (head) macro KTB$L_ASTQBL_K = 44,0,32,1 %; ! Kernel AST queue back link (tail) macro KTB$L_ASTQFL_E = 48,0,32,1 %; ! Executive AST queue forward link (head) macro KTB$L_ASTQBL_E = 52,0,32,1 %; ! Executive AST queue back link (tail) macro KTB$L_ASTQFL_S = 56,0,32,1 %; ! Supervisor AST queue forward link (head) macro KTB$L_ASTQBL_S = 60,0,32,1 %; ! Supervisor AST queue back link (tail) macro KTB$L_ASTQFL_U = 64,0,32,1 %; ! User AST queue forward link (head) macro KTB$L_ASTQBL_U = 68,0,32,1 %; ! User AST queue back link (tail) macro KTB$L_CPU_ID = 76,0,32,1 %; ! Current CPU (last one to load context) macro KTB$L_ASTACT = 160,0,32,0 %; ! Access modes with active ASTs macro KTB$L_STATE = 164,0,32,0 %; ! Process state macro KTB$L_PRI = 168,0,32,0 %; ! Process current priority macro KTB$L_PRIB = 172,0,32,0 %; ! Base priority macro KTB$L_AFFINITY_SKIP = 176,0,32,0 %; ! Affinity skip count macro KTB$L_OWNER = 180,0,32,0 %; ! PID of creator macro KTB$L_STS = 184,0,32,0 %; ! Process status flags macro KTB$V_RES = 184,0,1,0 %; ! Resident, in balance set macro KTB$V_DELPEN = 184,1,1,0 %; ! Delete pending macro KTB$V_FORCPEN = 184,2,1,0 %; ! Force exit pending macro KTB$V_INQUAN = 184,3,1,0 %; ! Initial quantum in progress macro KTB$V_PSWAPM = 184,4,1,0 %; ! Process swap mode, 1=NOSWAP macro KTB$V_RESPEN = 184,5,1,0 %; ! Resume pending, skip suspend macro KTB$V_SSFEXC = 184,6,1,0 %; ! System service exception enable (K) macro KTB$V_SSFEXCE = 184,7,1,0 %; ! System service exception enable (E) macro KTB$V_SSFEXCS = 184,8,1,0 %; ! System service exception enable (S) macro KTB$V_SSFEXCU = 184,9,1,0 %; ! System service exception enable (U) macro KTB$V_SSRWAIT = 184,10,1,0 %; ! System service resource wait disable macro KTB$V_SUSPEN = 184,11,1,0 %; ! Suspend pending macro KTB$V_WALL = 184,13,1,0 %; ! Wait for all events in mask macro KTB$V_BATCH = 184,14,1,0 %; ! Process is a batch job macro KTB$V_NOACNT = 184,15,1,0 %; ! No accounting for process macro KTB$V_NOSUSPEND = 184,16,1,0 %; ! Process cannot be suspended macro KTB$V_ASTPEN = 184,17,1,0 %; ! AST pending macro KTB$V_PHDRES = 184,18,1,0 %; ! Process header resident macro KTB$V_HIBER = 184,19,1,0 %; ! Hibernate after initial image activate macro KTB$V_LOGIN = 184,20,1,0 %; ! Login without reading UAF macro KTB$V_NETWRK = 184,21,1,0 %; ! Network connect job macro KTB$V_PWRAST = 184,22,1,0 %; ! Power fail AST macro KTB$V_NODELET = 184,23,1,0 %; ! No delete macro KTB$V_DISAWS = 184,24,1,0 %; ! Disable automatic WS adjustment macro KTB$V_INTER = 184,25,1,0 %; ! Process is an interactive job macro KTB$V_RECOVER = 184,26,1,0 %; ! Process can recover locks macro KTB$V_HARDAFF = 184,28,1,0 %; ! Process is bound to particular CPU macro KTB$V_ERDACT = 184,29,1,0 %; ! Exec mode rundown active macro KTB$V_SOFTSUSP = 184,30,1,0 %; ! Process is in "soft" suspend macro KTB$V_PREEMPTED = 184,31,1,0 %; ! Hard suspend has preempted soft macro KTB$L_STS2 = 188,0,32,0 %; ! Process status flags (2nd LW) macro KTB$V_QUANTUM_RESCHED = 188,0,1,0 %; ! Quantum-oriented process reschedule macro KTB$V_PHDLOCK = 188,3,1,0 %; ! Don't swap PHD -- process has $LCKPAG pages macro KTB$V_TCB = 188,4,1,0 %; ! TCB process macro KTB$V_TBS_STATE_PENDING = 188,5,1,0 %; ! Going to TBS, but not on the queue yet macro KTB$V_CLASS_SCHED_PERM = 188,15,1,0 %; ! process is part of permanent scheduling class macro KTB$V_TERM_NOTIFY = 188,16,1,0 %; ! termination notification macro KTB$V_BYTLM_LOAN = 188,17,1,0 %; ! Process has received rundown BYTLIM loan macro KTB$V_NOUNSHELVE = 188,19,1,0 %; ! if set, don't auto-unshelve macro KTB$V_SHELVING_RESERVED = 188,20,1,0 %; ! Reserved for shelving facility macro KTB$V_CLASS_SCHEDULED = 188,21,1,0 %; ! This process is class scheduled macro KTB$V_CLASS_SUPPLIED = 188,22,1,0 %; ! This process has been assigned a class, ! or an explicit "No class" (happens only ! when CLASS_SCHEDULED is cleared) macro KTB$V_IN_TBS_STATE = 188,23,1,0 %; ! This process is in TBS state macro KTB$V_WINDFALL = 188,24,1,0 %; ! Process eligible for windfall macro KTB$V_NOTIFY = 188,25,1,0 %; ! Send process termination msg. to CSP macro KTB$V_SINGLE_THREADED = 188,26,4,0 %; literal KTB$S_SINGLE_THREADED = 4; ! single threaded bits, 1 per mode macro KTB$L_PRISAV = 192,0,32,0 %; ! Saved current priority macro KTB$L_PRIBSAV = 196,0,32,0 %; ! Saved base priority macro KTB$L_AUTHPRI = 200,0,32,0 %; ! Initial process priority macro KTB$L_ONQTIME = 204,0,32,0 %; ! Abs time when placed on COM/COMO queue, ! adjusted for process wait time macro KTB$L_WAITIME = 208,0,32,0 %; ! Abs time of last process event macro KTB$L_WEFC = 244,0,32,0 %; ! Waiting EF cluster number macro KTB$L_EFWM = 248,0,32,0 %; ! Event flag wait mask macro KTB$L_PID = 268,0,32,0 %; ! Process ID used by exec on local node only ! ! *** WARNING - THE INTERNAL STRUCTURE OF THE EPID IS SUBJECT TO RADICAL CHANGE BETWEEN ! *** VERSIONS OF VMS. NO ASSUMPTIONS SHOULD EVER BE MADE ABOUT ITS FORMAT ! macro KTB$L_EPID = 272,0,32,0 %; ! Cluster-wide process ID seen by the world macro KTB$V_EPID_PROC = 272,0,21,0 %; literal KTB$S_EPID_PROC = 21; ! Process ID field, can convert to KTB$l_pid macro KTB$V_EPID_NODE_IDX = 272,21,8,0 %; literal KTB$S_EPID_NODE_IDX = 8; ! IDX - index to table of node identifications macro KTB$V_EPID_NODE_SEQ = 272,29,2,0 %; literal KTB$S_EPID_NODE_SEQ = 2; ! SEQ - sequence number for node table entry reuse macro KTB$V_EPID_WILD = 272,31,1,0 %; ! Flag that EPID is wildcard context for $GETJPI, ! and not a valid EPID macro KTB$L_MTXCNT = 284,0,32,0 %; ! Count of mutex semaphores owned macro KTB$L_PHD = 304,0,32,1 %; ! Address of Process Header macro KTB$L_JIB = 308,0,32,1 %; ! Address of Job Information Block macro KTB$L_HOME_RAD = 444,0,32,0 %; ! Which RAD is most of our memory in? macro KTB$L_SRA_SKIP_COUNT = 448,0,32,0 %; ! How many times has KT been skipped because of soft RAD affinity? macro KTB$L_AFFINITY = 464,0,32,1 %; ! CPU ID for affinity macro KTB$L_CAPABILITY = 468,0,32,0 %; ! CPU capability selection bitmask macro KTB$L_PERMANENT_CAPABILITY = 504,0,32,0 %; ! Permanent capability mask macro KTB$L_CAPABILITY_SEQ = 524,0,32,1 %; ! Copy of last sequence number macro KTB$L_AST_BLOCKED = 536,0,32,0 %; ! AST blocked bits macro KTB$L_CLASS_QUANT = 540,0,32,1 %; ! Address of cell containing class quantum macro KTB$W_CLASS_EXTRA_TICKS = 544,0,16,0 %; ! If class scheduled, extra ticks given to this KTB macro KTB$L_SCHED_POLICY = 640,0,32,0 %; ! POSIX sched policy macro KTB$L_STS3 = 804,0,32,0 %; ! Process status flags macro KTB$V_WAKEPEN = 804,12,1,0 %; ! Wake pending, skip hibernate macro KTB$V_SECAUDIT = 804,27,1,0 %; ! Mandatory security auditing enabled macro KTB$V_UPCALL_AST_BLOCKED = 804,31,1,0 %; ! indicates that upcall ASTs are blocked macro KTB$L_PCB = 808,0,32,1 %; ! PCB, overlays PCB$L_INITIAL_KTB macro KTB$L_INITIAL_KTB = 808,0,32,1 %; ! Initial KTB, overlays KTB$L_PCB macro KTB$L_FLAGS = 812,0,32,0 %; ! Kernel thread flags macro KTB$V_DELETE_PENDING = 812,0,1,0 %; ! Delete pending macro KTB$V_SCHED_CONTEXT_SAVED = 812,1,1,0 %; ! Saved scheduling state macro KTB$V_SINGLE_THREAD_ACT = 812,2,4,0 %; literal KTB$S_SINGLE_THREAD_ACT = 4; ! single thread active bits, 1 per mode macro KTB$V_TOLERANT = 812,6,1,0 %; ! Thread is executing a tolerant system service macro KTB$V_SOFT_RAD_AFFINITY = 812,7,1,0 %; ! Soft RAD affinity is in effect for this KT macro KTB$L_PER_KT_AREA = 820,0,32,1 %; ! Address of kthread p1 area macro KTB$L_TQUANT_ACB = 824,0,32,1 %; ! Tquantum upcall ACB macro KTB$L_TQUANT = 828,0,32,0 %; ! Remaining per user thread quantum macro KTB$L_QUANT = 832,0,32,0 %; ! Remaining per kernel thread quantum macro KTB$L_TM_CALLBACKS = 836,0,32,1 %; ! Address of callback vector macro KTB$L_CALLBACK_ERR = 840,0,32,0 %; ! Error bits if callback fails macro KTB$Q_CAPABILITIES = 848,0,0,0 %; literal KTB$S_CAPABILITIES = 8; ! Thread capabilities and affinities macro KTB$L_CAPABILITIES = 848,0,32,0 %; ! Thread system and user capability mask macro KTB$Q_PERMANENT_CAPABILITIES = 856,0,0,0 %; literal KTB$S_PERMANENT_CAPABILITIES = 8; ! Thread permanent capabilities and affinities macro KTB$L_PERMANENT_CAPABILITIES = 856,0,32,0 %; ! Thread permanent system and user capability mask macro KTB$Q_SAVED_CAPABILITIES = 864,0,0,0 %; literal KTB$S_SAVED_CAPABILITIES = 8; ! Thread capabilities and affinities macro KTB$L_SAVED_CAPABILITIES = 864,0,32,0 %; ! Thread system and user capability mask macro KTB$L_BIAS_CELL = 872,0,32,0 %; ! Implicit affinity CPU bias macro KTB$L_PERSONA_ID = 876,0,32,0 %; ! Unique Persona Identifier macro KTB$AR_PSB = 880,0,32,1 %; ! Pointer to active Persona macro KTB$L_SWP_SEQ = 884,0,32,0 %; ! Current swapper's sequence macro KTB$Q_VOL_WAITS = 888,0,0,1 %; literal KTB$S_VOL_WAITS = 8; ! # of voluntary waits over a specific time macro KTB$L_CURR_VOL_WAITS = 896,0,32,1 %; ! current # of voluntary waits (...and counting) macro KTB$L_QEND_COUNT = 900,0,32,1 %; ! # of quantum ends incurred macro KTB$Q_COMQ_WAIT = 904,0,0,0 %; literal KTB$S_COMQ_WAIT = 8; ! SCC at the time the thread was placed on the ! COM queue macro KTB$Q_RUNTIME_START = 912,0,0,0 %; literal KTB$S_RUNTIME_START = 8; ! SCC at time thread placed into execution macro KTB$Q_INTTIME_START = 920,0,0,0 %; literal KTB$S_INTTIME_START = 8; ! current # of interrupt ticks (hard ticks) when ! thread placed into execution macro KTB$L_SOFT_BROKEN = 928,0,32,1 %; ! # of times soft affinity has been broken macro KTB$Q_ACC_RUN = 952,0,0,0 %; literal KTB$S_ACC_RUN = 8; ! Accumulated run time. macro KTB$Q_ACC_WAIT = 960,0,0,0 %; literal KTB$S_ACC_WAIT = 8; ! Accumulated wait time. macro KTB$Q_ACC_INTERRUPT = 968,0,0,0 %; literal KTB$S_ACC_INTERRUPT = 8; ! Accumulated interrupt time. macro KTB$L_RUN_COUNT = 976,0,32,1 %; ! # of times run on this s.a. CPU. macro KTB$L_GLOCK_WAIT_STATUS = 980,0,32,0 %; ! Status of glock wait macro KTB$Q_GLOCK = 984,0,0,0 %; literal KTB$S_GLOCK = 8; ! Galaxy lock handle macro KTB$L_LCKRQ = 1008,0,32,0 %; ! pointer to LCKRQ packet macro KTB$L_COMQ_HEAD = 1012,0,32,0 %; ! If in COM, what queue are we in? macro KTB$Q_SCHED_COUNT = 1016,0,0,0 %; literal KTB$S_SCHED_COUNT = 8; ! How many times has this KTB been scheduled macro KTB$Q_FRED = 1024,0,0,1 %; literal KTB$S_FRED = 8; ! Address of FRED block macro KTB$Q_VIRPCB = 1024,0,0,1 %; literal KTB$S_VIRPCB = 8; ! VA of HWPCB macro KTB$Q_TQE_FLAGS = 1032,0,0,0 %; literal KTB$S_TQE_FLAGS = 8; ! TQE flags macro KTB$L_TIMER = 1032,0,32,0 %; ! Timer Request info macro KTB$L_WAKEUP = 1036,0,32,0 %; ! Wakeup Call info macro KTB$R_CBB_PERM_CPU_AFFINITY = 1072,0,0,0 %; literal KTB$S_CBB_PERM_CPU_AFFINITY = 48; ! Embedded CBB block macro KTB$L_PERMANENT_CPU_AFFINITY = 1120,0,32,0 %; ! Permanent CPU affinity macro KTB$Q_PERMANENT_CPU_AFFINITY = 1120,0,0,0 %; literal KTB$S_PERMANENT_CPU_AFFINITY = 8; ! Permanent CPU affinity macro KTB$R_CBB_CURRENT_AFFINITY = 1248,0,0,0 %; literal KTB$S_CBB_CURRENT_AFFINITY = 48; ! Embedded CBB block macro KTB$L_CURRENT_AFFINITY = 1296,0,32,0 %; ! Current CPU mask macro KTB$Q_CURRENT_AFFINITY = 1296,0,0,0 %; literal KTB$S_CURRENT_AFFINITY = 8; ! Current CPU mask macro KTB$R_CBB_ACTIVE_CPUS = 1424,0,0,0 %; literal KTB$S_CBB_ACTIVE_CPUS = 48; ! Embedded CBB block macro KTB$L_ACTIVE_CPUS = 1472,0,32,0 %; ! CPUs owned by this process macro KTB$Q_ACTIVE_CPUS = 1472,0,0,0 %; literal KTB$S_ACTIVE_CPUS = 8; ! CPUs owned by this process macro KTB$R_CBB_AFFINITIES = 1600,0,0,0 %; literal KTB$S_CBB_AFFINITIES = 48; ! Embedded CBB block macro KTB$L_AFFINITIES = 1648,0,32,0 %; ! Thread affinity mask macro KTB$Q_AFFINITIES = 1648,0,0,0 %; literal KTB$S_AFFINITIES = 8; ! Thread affinity mask macro KTB$R_CBB_PERMANENT_AFFINITIES = 1776,0,0,0 %; literal KTB$S_CBB_PERMANENT_AFFINITIES = 48; ! Embedded CBB block macro KTB$L_PERMANENT_AFFINITIES = 1824,0,32,0 %; ! Thread permanent affinity mask macro KTB$Q_PERMANENT_AFFINITIES = 1824,0,0,0 %; literal KTB$S_PERMANENT_AFFINITIES = 8; ! Thread permanent affinity mask macro KTB$R_CBB_SAVED_AFFINITIES = 1952,0,0,0 %; literal KTB$S_CBB_SAVED_AFFINITIES = 48; ! Embedded CBB block macro KTB$L_SAVED_AFFINITIES = 2000,0,32,0 %; ! Thread saved affinity mask macro KTB$Q_SAVED_AFFINITIES = 2000,0,0,0 %; literal KTB$S_SAVED_AFFINITIES = 8; ! Thread saved affinity mask macro KTB$PQ_FP_DISABLED_ACTION = 2144,0,0,1 %; literal KTB$S_FP_DISABLED_ACTION = 8; ! If we get float disabled fault, what to do? macro KTB$L_KT_KERNEL_COUNTER = 2200,0,32,0 %; ! Per-kthread kernel mode counters macro KTB$L_KT_EXEC_COUNTER = 2204,0,32,0 %; ! Per-kthread exec mode counters macro KTB$L_KT_SUPER_COUNTER = 2208,0,32,0 %; ! Per-kthread super mode counters macro KTB$L_KT_USER_COUNTER = 2212,0,32,0 %; ! Per-kthread user mode counters macro KTB$Q_KT_KERNEL_COUNTER_FRAC = 2216,0,0,0 %; literal KTB$S_KT_KERNEL_COUNTER_FRAC = 8; ! Fractional tick for kernel mode macro KTB$Q_KT_EXEC_COUNTER_FRAC = 2224,0,0,0 %; literal KTB$S_KT_EXEC_COUNTER_FRAC = 8; ! Fractional tick for exec mode macro KTB$Q_KT_SUPER_COUNTER_FRAC = 2232,0,0,0 %; literal KTB$S_KT_SUPER_COUNTER_FRAC = 8; ! Fractional tick for super mode macro KTB$Q_KT_USER_COUNTER_FRAC = 2240,0,0,0 %; literal KTB$S_KT_USER_COUNTER_FRAC = 8; ! Fractional tick for user mode macro KTB$Q_FP_LOW_SEQUENCE_NUMBER = 2248,0,0,0 %; literal KTB$S_FP_LOW_SEQUENCE_NUMBER = 8; ! Sequence number for low floating registers macro KTB$Q_FP_HIGH_SEQUENCE_NUMBER = 2256,0,0,0 %; literal KTB$S_FP_HIGH_SEQUENCE_NUMBER = 8; ! Sequence number for high floating registers macro KTB$L_SPARE = 2268,0,32,0 %; ! Available for either KTB or PCB macro KTB$PQ_POWER_ACCOUNTING = 2272,0,0,1 %; literal KTB$S_POWER_ACCOUNTING = 8; ! Power/performance accounting pointer macro KTB$L_DEF_SCHED_FKB = 2304,0,0,1 %; literal KTB$S_DEF_SCHED_FKB = 48; literal KTB$K_LENGTH = 2352; ! Length of KTB literal KTB$C_LENGTH = 2352; ! Length of KTB literal KTB$S_KTBDEF = 2352; ! Old KTB size for compatibility !*** MODULE $MPDEVDEF *** ! Include base definitions literal MPDEV$M_ENABLE = %X'1'; literal MPDEV$M_REMOTE = %X'2'; literal MPDEV$M_POLLER = %X'4'; literal MPDEV$M_SCSI_ERROR_POLL = %X'8'; literal MPDEV$S_MPDEV_SGN_FLGS = 4; ! Definition for Multipath sysgen ! parameters. macro MPDEV$V_ENABLE = 0,0,1,0 %; ! enable Multipath macro MPDEV$V_REMOTE = 0,1,1,0 %; ! enable Multipath for remote paths macro MPDEV$V_POLLER = 0,2,1,0 %; ! enable Multipath poller macro MPDEV$V_SCSI_ERROR_POLL = 0,3,1,0 %; ! enable polling to flush SCSI errors literal MPDEV$M_ERRORLOG = %X'1'; literal MPDEV$M_INHIBIT_PATHBAL = %X'2'; literal MPDEV$S_MPDEV_D1_FLGS = 4; ! Definition for Multipath sysgen ! debugging parameters. macro MPDEV$V_ERRORLOG = 0,0,1,0 %; ! enable error logging macro MPDEV$V_INHIBIT_PATHBAL = 0,1,1,0 %; ! inhibit path balancing ! Multipath specific data structure literal MPDEV$M_CP_MANUAL = %X'1'; literal MPDEV$M_PV_IRP_ACTIVE = %X'2'; literal MPDEV$M_PV_PACKACK_SUCCESS = %X'4'; literal MPDEV$M_WAS_FNDACT = %X'8'; literal MPDEV$M_PVIRP_SRVIO = %X'10'; literal MPDEV$M_DEVICE_POLL_ACTIVE = %X'20'; literal MPDEV$K_IO_ERROR = 1; ! I/O error initiated path verification literal MPDEV$K_MANUAL_SWITCH = 2; ! Manual switch requested literal MPDEV$K_FIND_ACTIVE = 3; ! Proactive search for active path literal MPDEV$K_ST_STABLE = 1; ! Path is stable literal MPDEV$K_ST_DRAINING = 2; ! Draining I/O from current path literal MPDEV$K_ST_SWLCLCON = 3; ! Path switching is being attempted to ! only local path that are connected literal MPDEV$K_ST_SWLCLANY = 4; ! Path switching is being attempted to ! any local path literal MPDEV$K_ST_SWANY = 5; ! Path switching is being attempted to any path literal MPDEV$K_ST_STACP = 6; ! Attempt to stay on current path literal MPDEV$K_ST_RESIDUAL = 7; ! Waiting for "leftover" PVIRP from earlier path ver ! ..can't go to STABLE until that PVIRP completes literal MPDEV$K_PACKACK_TIMLIM_SECS = 5; ! Default time limit (seconds) literal MPDEV$S_MPDEV = 360; macro MPDEV$PS_FLINK = 0,0,32,1 %; ! Forward pointer macro MPDEV$PS_BLINK = 4,0,32,1 %; ! Backward pointer macro MPDEV$W_SIZE = 8,0,16,0 %; ! Size of the data buffer macro MPDEV$B_TYPE = 10,0,8,0 %; ! Data structure type macro MPDEV$B_SUBTYPE = 11,0,8,0 %; ! Data structure sub-type macro MPDEV$PS_PRIMARY_UCB = 12,0,32,1 %; ! Pointer to the primary ucb macro MPDEV$PS_CURRENT_UCB = 16,0,32,1 %; ! Pointer to the current UCB in the multipath set. macro MPDEV$PS_PRIMARY_FDT = 20,0,32,1 %; ! Saved value of primary path's UCB$PS_FDT_2 macro MPDEV$R_CBB_PRIMARY_AFFINITY = 24,0,0,0 %; literal MPDEV$S_CBB_PRIMARY_AFFINITY = 48; ! Embedded CBB block macro MPDEV$L_PRIMARY_AFFINITY = 72,0,32,0 %; ! Saved value of primary path's UCB$L_AFFINITY macro MPDEV$Q_PRIMARY_AFFINITY = 72,0,0,0 %; literal MPDEV$S_PRIMARY_AFFINITY = 8; ! Saved value of primary path's UCB$L_AFFINITY macro MPDEV$L_SET_FLAGS = 200,0,32,0 %; ! Status flags for whole set macro MPDEV$V_CP_MANUAL = 200,0,1,0 %; ! Current path selected via a manual switch macro MPDEV$V_PV_IRP_ACTIVE = 200,1,1,0 %; ! A PV IRP is active macro MPDEV$V_PV_PACKACK_SUCCESS = 200,2,1,0 %; ! Most recent PV packack completed successfully macro MPDEV$V_WAS_FNDACT = 200,3,1,0 %; ! Event started out as "find active" macro MPDEV$V_PVIRP_SRVIO = 200,4,1,0 %; ! Current PV IRP was originally a SRVIO macro MPDEV$V_DEVICE_POLL_ACTIVE = 200,5,1,0 %; ! Search for a working path in this set is in progress macro MPDEV$PS_DDT = 204,0,32,1 %; ! Pointer to the newly created DDT macro MPDEV$PS_PV_UCB = 208,0,32,1 %; ! Pointer to the path UCB last issued a path ! verification IRP macro MPDEV$L_EB_TYPE_CODE = 212,0,32,0 %; ! Multipath event block codes macro MPDEV$L_EB_STATE = 216,0,32,0 %; ! Multipath automatic path switching state ! Values are 1,2,3,... macro MPDEV$Q_EB_START_TIME = 224,0,0,0 %; literal MPDEV$S_EB_START_TIME = 8; ! Time this event started macro MPDEV$PS_EB_START_UCB = 232,0,32,1 %; ! UCB of current path at start of the event macro MPDEV$L_EB_LCLCON_RETRIES = 236,0,32,1 %; ! Number of scans of the multipath set when path ! verification is in progress and MPDEV$L_EB_STATE ! is MPDEV$K_ST_SWLCLCON macro MPDEV$L_EB_SAVED_MVIRP_FUNC = 240,0,32,0 %; ! Saved value of the MVIRP's IRP$L_FUNC field while ! the IRP is being used as a path verification IRP macro MPDEV$L_EB_SAVED_MVIRP_PID = 244,0,32,0 %; ! Saved value of the MVIRP's IRP$L_PID field while ! the IRP is being used as a path verification IRP macro MPDEV$L_EB_SAVED_MVIRP_STS = 248,0,32,0 %; ! Saved value of the MVIRP's IRP$L_STS field while ! the IRP is being used as a path verification IRP macro MPDEV$L_EB_SAVED_MVIRP_STS2 = 252,0,32,0 %; ! Saved value of the MVIRP's IRP$L_STS2 field while ! the IRP is being used as a path verification IRP macro MPDEV$L_DRIVER1 = 256,0,32,0 %; ! Driver-specific field macro MPDEV$PS_CUCB = 256,0,32,1 %; ! DK uses it as a CUCB field macro MPDEV$L_DRIVER2 = 260,0,32,0 %; ! Driver-specific field macro MPDEV$L_DRIVER3 = 264,0,32,0 %; ! Driver-specific field macro MPDEV$L_DRIVER4 = 268,0,32,0 %; ! Driver-specific field macro MPDEV$PS_NOTIFY_MPDEV_ACB = 272,0,32,1 %; ! Address of mpdev_acb macro MPDEV$L_EB_PACKACK_RESCANS_LEFT = 276,0,32,1 %; ! Number of path/state rescans left for this packack macro MPDEV$L_EB_PACKACK_TIMLIM = 280,0,32,0 %; ! Path verification packack time limit (ABSTIM value) macro MPDEV$Q_EB_END_TIME = 288,0,0,0 %; literal MPDEV$S_EB_END_TIME = 8; ! Time this event ended macro MPDEV$PS_EB_SAVED_MVIRP = 296,0,32,1 %; ! MVIRP whose values are saved macro MPDEV$L_EB_ST_AT_PATH_SWITCH = 300,0,32,0 %; ! State at last path switch macro MPDEV$L_NUM_PATH_VER = 304,0,32,0 %; ! Number of path verifications started macro MPDEV$L_NUM_PATH_SWITCH_AUTO = 308,0,32,0 %; ! Number of automatic path switches macro MPDEV$L_NUM_PATH_SWITCH_MAN = 312,0,32,0 %; ! Number of manual path switches macro MPDEV$L_NUM_MVIRP_OK = 316,0,32,0 %; ! Number of times a MVIRP packack was completed successfully macro MPDEV$L_NUM_MVIRP_FAIL = 320,0,32,0 %; ! Number of times a MVIRP packack was failed macro MPDEV$L_NUM_MVIRP_CONC = 324,0,32,0 %; ! Number of times a concurrent MVIRP packack was intercepted macro MPDEV$L_NUM_FIND_ACTIVE = 328,0,32,0 %; ! Number of times a "find active path" scan initiated macro MPDEV$PS_SWITCH_TO_UCB = 332,0,32,1 %; ! New path selected during path verification macro MPDEV$L_FAILBACK_TIME = 336,0,32,0 %; ! abstim of last failback attempt macro MPDEV$PS_CONC_PACKACK_FL = 344,0,32,1 %; macro MPDEV$PS_CONC_PACKACK_BL = 348,0,32,1 %; ! list of IRP's of concurrent packacks macro MPDEV$L_SPARE_1 = 352,0,32,0 %; macro MPDEV$L_SPARE_2 = 356,0,32,0 %; literal MPDEV$C_LENGTH = 360; ! Length of a MPDEV literal MPDEV$K_LENGTH = 360; ! Length of a MPDEV ! Poller path block data structure literal MPDEV_PPB$M_PATH_AVAILABLE = %X'1'; literal MPDEV_PPB$M_ALL_PATHS_DISABLED = %X'2'; literal MPDEV_PPB$M_NORMAL_TIMER = %X'4'; literal MPDEV_PPB$M_FAIL_TIMER = %X'8'; literal MPDEV_PPB$M_FAILBACK_PENDING = %X'10'; literal MPDEV_PPB$M_POLLING_IRP_ACTIVE = %X'20'; literal MPDEV_PPB$M_SCAN_ACTIVE = %X'40'; literal MPDEV_PPB$M_PATH_VERIFY_FAILED = %X'80'; literal MPDEV_PPB$M_ENABLED_FOUND = %X'100'; literal MPDEV_PPB$M_PVIP_RESPONDING = %X'200'; literal MPDEV_PPB$M_POLLING_STARTED = %X'400'; literal MPDEV_PPB$M_POLLING_ENABLED = %X'1'; literal MPDEV_PPB$M_PATH_IS_DISTANT = %X'2'; literal MPDEV_PPB$S_MPDEV_PPB = 680; macro MPDEV_PPB$PS_FLINK = 0,0,32,1 %; ! Forward link macro MPDEV_PPB$PS_BLINK = 4,0,32,1 %; ! Backward link macro MPDEV_PPB$W_SIZE = 8,0,16,0 %; ! Structure size macro MPDEV_PPB$B_TYPE = 10,0,8,0 %; ! Structure type macro MPDEV_PPB$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro MPDEV_PPB$L_STATUS1 = 12,0,32,0 %; ! Statuses modified via polling routines macro MPDEV_PPB$V_PATH_AVAILABLE = 12,0,1,0 %; ! Path was available at last poll (D) macro MPDEV_PPB$V_ALL_PATHS_DISABLED = 12,1,1,0 %; ! All devices on this path were not testable at last poll macro MPDEV_PPB$V_NORMAL_TIMER = 12,2,1,0 %; ! Poller is waiting using "working path" timer interval macro MPDEV_PPB$V_FAIL_TIMER = 12,3,1,0 %; ! Poller is waiting using "failed path" timer interval macro MPDEV_PPB$V_FAILBACK_PENDING = 12,4,1,0 %; ! A device has failed over from local to remote; when a local path becomes ! available, check to see if it can be failed back to the local path macro MPDEV_PPB$V_POLLING_IRP_ACTIVE = 12,5,1,0 %; ! Polling IRP is active macro MPDEV_PPB$V_SCAN_ACTIVE = 12,6,1,0 %; ! A poller scan of devices on this path is in progress macro MPDEV_PPB$V_PATH_VERIFY_FAILED = 12,7,1,0 %; ! In this scan: At least one poller path verify has failed macro MPDEV_PPB$V_ENABLED_FOUND = 12,8,1,0 %; ! In this scan: An enabled device was found macro MPDEV_PPB$V_PVIP_RESPONDING = 12,9,1,0 %; ! In this scan: Found a device in PVIP with "not responding" clear macro MPDEV_PPB$V_POLLING_STARTED = 12,10,1,0 %; ! Polling has been started on this path macro MPDEV_PPB$L_STATUS2 = 16,0,32,0 %; ! Statuses modified via SET DEVICE macro MPDEV_PPB$V_POLLING_ENABLED = 16,0,1,0 %; ! Path check enabled (D) macro MPDEV_PPB$V_PATH_IS_DISTANT = 16,1,1,0 %; ! Path is not local to this system macro MPDEV_PPB$PS_PATH_TEST_UCB = 20,0,32,1 %; ! UCB most recently used to test the path (never zero) macro MPDEV_PPB$PS_PATH_TEST_UCB_CP = 24,0,32,1 %; ! Current path on device when polling IRP issued (valid only if POLLING_IRP_ACTI macro MPDEV_PPB$PS_SUD_LIST = 28,0,32,1 %; ! List head of SUDs for devices that share this path macro MPDEV_PPB$Q_TRANSITION_TIME = 32,0,0,0 %; literal MPDEV_PPB$S_TRANSITION_TIME = 8; ! Time of most recent change to PATH_AVAILABLE flag macro MPDEV_PPB$Q_TIME_USER_DISABLED = 40,0,0,0 %; literal MPDEV_PPB$S_TIME_USER_DISABLED = 8; ! Time of most recent change to ALL_PATHS_DISABLED flag macro MPDEV_PPB$L_CURRENT_UCB_COUNT = 48,0,32,0 %; ! number of current UCB's on this path macro MPDEV_PPB$R_TQE = 56,0,0,0 %; literal MPDEV_PPB$S_TQE = 64; ! Timer Queue Entry macro MPDEV_PPB$R_IRP = 120,0,0,0 %; literal MPDEV_PPB$S_IRP = 560; ! I/O Request Packet literal MPDEV_PPB$C_LENGTH = 680; ! Length of a MPDEV_PPB literal MPDEV_PPB$K_LENGTH = 680; ! Length of a MPDEV_PPB ! List header data structure literal MPDEV_QUEHDR$S_MPDEV_QUEHDR = 8; macro MPDEV_QUEHDR$PS_FLINK = 0,0,32,1 %; ! Forward link macro MPDEV_QUEHDR$PS_BLINK = 4,0,32,1 %; ! Backward link literal MPDEV_QUEHDR$C_LENGTH = 8; ! Length of a MPDEV_QUEHDR literal MPDEV_QUEHDR$K_LENGTH = 8; ! Length of a MPDEV_QUEHDR ! Mpdev acb to deliver completion AST in multipath system services literal MPDEV_ACB$S_MPDEV_ACB = 104; macro MPDEV_ACB$R_BASE_ACB = 0,0,0,0 %; literal MPDEV_ACB$S_BASE_ACB = 64; ! Imbeded ACB64 structure macro MPDEV_ACB$PS_DESIRED_PATH = 64,0,32,1 %; ! Pointer to desired path UCB macro MPDEV_ACB$L_SPARE_1 = 68,0,32,0 %; ! spare (we'd get a filler longword here, anyway) macro MPDEV_ACB$PQ_IOSB_ADDRESS = 72,0,0,1 %; literal MPDEV_ACB$S_IOSB_ADDRESS = 8; ! Pointer to IOSB macro MPDEV_ACB$L_EFN = 80,0,32,0 %; ! Event flag macro MPDEV_ACB$L_STATUS = 84,0,32,0 %; ! Status macro MPDEV_ACB$L_IMGCNT = 88,0,32,0 %; ! Image count macro MPDEV_ACB$L_SPARE_2 = 92,0,32,0 %; ! another spare (again, we'd get a filler longword here) macro MPDEV_ACB$Q_FLAGS = 96,0,0,0 %; literal MPDEV_ACB$S_FLAGS = 8; ! flags literal MPDEV_ACB$C_LENGTH = 104; ! Length of a MPDEV_ACB literal MPDEV_ACB$K_LENGTH = 104; ! Length of a MPDEV_ACB ! *************************************************************************** ! ! Miscellaneous Multipath-related constants that are not public ! ! Note: Constants that are used in a specific cell of a data structure are ! defined inside the definition of the structure. ! Define constants used by the "bent pin" heuristic in MPDEV$PV_TRACK_PVS. ! If in the current tracking interval of MPDEV$K_TRACKING_INTERVAL seconds ! we've successfully successfully completed at least MPDEV$K_TRACKING_THRESHOLD ! MVIRP packacks, then fail any additional MVIRP packacks on this path for ! the remainder of the tracking interval. ! ! These value were chosen so that this heuristic could come into play if a path ! were to enter into mount verification repeatedly due to frequent SCSI command ! timeouts, which are 24 seconds for disk commands. literal MPDEV$K_TRACKING_INTERVAL = 300; ! Time in seconds literal MPDEV$K_TRACKING_THRESHOLD = 10; ! Number of invocations ! Constant used in [CLIUTL]SETDEVICE.B32 to check for the maximum displayable path name literal MPDEV$K_MAX_DSPLYPATH_SIZE = 292; ! X-38 ! Symbolic constant for the time-limit, in seconds, for the deferral of path ! balancing when a newly configured path is not yet available for use. literal MPDEV$K_PATHBAL_AVAIL_WAIT = 5; !*** MODULE $SCSIDEF IDENT X-34 *** ! ! Bit definitions for FIBRE_SCSI_RSV1 ! literal SCSI$M_DK_BOOT_LOG = %X'1'; literal SCSI$M_VERBOSE = %X'2'; literal SCSI$M_DIS_PER_RES_UNK = %X'4'; literal SCSI$M_DIS_PER_RES_HSG = %X'8'; literal SCSI$M_DIS_PER_RES_HSV = %X'10'; literal SCSI$M_DIS_PER_RES_MSA = %X'20'; literal SCSI$M_DIS_PER_RES_VERS = %X'40'; literal SCSI$M_DIS_PER_RES_HPXP = %X'80'; literal SCSI$M_DIS_PER_RES_BIT8 = %X'100'; literal SCSI$M_DIS_PER_RES_BIT9 = %X'200'; literal SCSI$M_DIS_PER_RES_BITA = %X'400'; literal SCSI$M_DIS_PER_RES_BITB = %X'800'; literal SCSI$M_DIS_PER_RES_BITC = %X'1000'; literal SCSI$M_DIS_PER_RES_BITD = %X'2000'; literal SCSI$M_DIS_PER_RES_BITE = %X'4000'; literal SCSI$M_DIS_PER_RES_BITF = %X'8000'; literal SCSI$V_RWH = 16; ! Base bit offset of Read/Write History bits literal SCSI$M_RWH_SCSI = %X'10000'; literal SCSI$M_RWH_FC = %X'20000'; literal SCSI$M_RWH_SW_ISCSI = %X'40000'; literal SCSI$M_RWH_HW_ISCSI = %X'80000'; literal SCSI$M_RWH_SAS = %X'100000'; literal SCSI$M_RWH_ALL = 2031616; ! Define all-transport constant mask literal SCSI$M_FIX_OS_MODE = %X'200000'; literal SCSI$M_CRASH_ON_RESET_FAIL = %X'40000000'; literal SCSI$M_ENABLE_PKR_RESET = %X'80000000'; literal SCSI$S_FIBRE_SCSI_RSV1 = 8; macro SCSI$V_DK_BOOT_LOG = 0,0,1,0 %; ! Enable DKLOG for boot device macro SCSI$V_VERBOSE = 0,1,1,0 %; ! Driver is verbose on boot macro SCSI$V_DIS_PER_RES_UNK = 0,2,1,0 %; ! Selective disables for Persistent Reservations macro SCSI$V_DIS_PER_RES_HSG = 0,3,1,0 %; macro SCSI$V_DIS_PER_RES_HSV = 0,4,1,0 %; macro SCSI$V_DIS_PER_RES_MSA = 0,5,1,0 %; macro SCSI$V_DIS_PER_RES_VERS = 0,6,1,0 %; macro SCSI$V_DIS_PER_RES_HPXP = 0,7,1,0 %; macro SCSI$V_DIS_PER_RES_BIT8 = 0,8,1,0 %; ! Reserved for future devices macro SCSI$V_DIS_PER_RES_BIT9 = 0,9,1,0 %; macro SCSI$V_DIS_PER_RES_BITA = 0,10,1,0 %; macro SCSI$V_DIS_PER_RES_BITB = 0,11,1,0 %; macro SCSI$V_DIS_PER_RES_BITC = 0,12,1,0 %; macro SCSI$V_DIS_PER_RES_BITD = 0,13,1,0 %; macro SCSI$V_DIS_PER_RES_BITE = 0,14,1,0 %; macro SCSI$V_DIS_PER_RES_BITF = 0,15,1,0 %; ! X-33 ! Initialize all-transport RWH mask ! Add SCSI to mask macro SCSI$V_RWH_SCSI = 0,16,1,0 %; ! Enable SCSI R/W History ! Add FibreChannel to mask macro SCSI$V_RWH_FC = 0,17,1,0 %; ! Enable FibreChannel R/W History ! Add SW iSCSI to mask macro SCSI$V_RWH_SW_ISCSI = 0,18,1,0 %; ! Enable SW iSCSI R/W History ! Add HW iSCSI to mask macro SCSI$V_RWH_HW_ISCSI = 0,19,1,0 %; ! Enable HW iSCSI R/W History ! Add SAS to mask macro SCSI$V_RWH_SAS = 0,20,1,0 %; ! Enable SAS R/W History macro SCSI$V_FIX_OS_MODE = 0,21,1,0 %; ! X-34 Allow OS mode bit update (QLogic) macro SCSI$V_CRASH_ON_RESET_FAIL = 0,30,1,0 %; macro SCSI$V_ENABLE_PKR_RESET = 0,31,1,0 %; ! ! INQUIRY command ! ! The Inquiry command is also defined in the class drivers and in SCSI2AUTO. ! It is defined here for use by IOGEN$FIBRE_CONFIG and any other module that ! might need it. ! literal INQ_CMD$K_INQ_OPCODE = 18; literal INQ_CMD$M_ENABLE_VPD = %X'1'; literal INQ_CMD$M_COMMAND_DATA = %X'2'; literal INQ_CMD$K_LENGTH = 6; literal INQ_CMD$S_INQ_CMD = 8; macro INQ_CMD$B_OPCODE = 0,0,8,0 %; ! Operation code macro INQ_CMD$B_FLAGS = 1,0,8,0 %; macro INQ_CMD$V_ENABLE_VPD = 1,0,1,0 %; ! Enable return of Vital Product Data macro INQ_CMD$V_COMMAND_DATA = 1,1,1,0 %; ! Enable return of Command Support Data macro INQ_CMD$B_VPD_PAGE = 2,0,8,0 %; ! VPD page or command support query opcode macro INQ_CMD$B_RESERVED2 = 3,0,8,0 %; ! reserved macro INQ_CMD$B_ALLOC_LENGTH = 4,0,8,0 %; ! Allocation length macro INQ_CMD$B_CONTROL = 5,0,8,0 %; ! Control byte ! ! Standard INQUIRY data ! ! The standard inquiry data contains 36 bytes, followed by a variable number of ! vendor specific parameters. ! literal SCSI$INQ$M_DEVICE_TYPE = %X'1F'; literal SCSI$C_DISK = 0; ! 00: Direct-access device (e.g., magnetic disk) literal SCSI$C_TAPE = 1; ! 01: Sequential-access device (e.g., magnetic tape) literal SCSI$C_PRINTER = 2; ! 02: Printer device literal SCSI$C_CPU = 3; ! 03: Processor device literal SCSI$C_WORM = 4; ! 04: Write-once device literal SCSI$C_CDROM = 5; ! 05: CD-ROM device literal SCSI$C_SCANNER = 6; ! 06: Scanner device literal SCSI$C_OPTICAL = 7; ! 07: Optical memory device (e.g., some optical disks) literal SCSI$C_JUKEBOX = 8; ! 08: Medium Changer device (e.g., jukeboxes) literal SCSI$C_INTERCONNECT = 9; ! 09: Communications device ! 0A: Reserved ! 0B: Reserved literal SCSI$C_SCC = 12; ! 0C: Storage array controller (RAID) literal SCSI$C_ENC_SVCS = 13; ! 0D: Enclosure services literal SCSI$C_RBC = 14; ! 0E: Simplified direct-access ! 0F-16: Reserved ! 17-1E: Reserved literal SCSI$C_UNKNOWN = 31; ! 1F: Unknown or no device type literal SCSI$INQ$M_QUALIFIER = %X'E0'; literal SCSI$C_LUN_CONNECTED = 0; ! Peripheral device is connected to LUN literal SCSI$C_LUN_NOCONNECT = 1; ! Peripheral device is not connected to LUN literal SCSI$C_LUN_UNAVAILABLE = 3; ! Peripheral device does not support LUNs literal SCSI$INQ$M_MODIFIER = %X'7F'; literal SCSI$INQ$M_RMB = %X'80'; literal SCSI$INQ$M_ANSI_VERSION = %X'7'; literal SCSI$C_ANSI_UNKNOWN = 0; ! 0: The device ANSI version is unknown literal SCSI$C_ANSI_SCSI_1 = 1; ! 1: The device complies to SCSI-1 (ANSI X3.131-1986) literal SCSI$C_ANSI_SCSI_2 = 2; ! 2: The device complies to SCSI-2 (revision ?) literal SCSI$C_ANSI_SCSI_3_SPC1 = 3; ! 3: The device complies to SCSI-3 SPC-1 literal SCSI$C_ANSI_SCSI_3_SPC2 = 4; ! 4: The device complies to SCSI-3 SPC-2 literal SCSI$C_ANSI_SCSI_3_SPC3 = 5; ! 5: The device complies to SCSI-3 SPC-3 literal SCSI$C_ANSI_SCSI_3 = 3; ! 3: The device complies to SCSI_3 literal SCSI$INQ$M_ECMA_VERSION = %X'38'; literal SCSI$INQ$M_ISO_VERSION = %X'C0'; literal SCSI$INQ$M_RESP_DATA_FORMAT = %X'F'; literal SCSI$C_SCSI_1 = 0; ! INQUIRY data in SCSI-1 format literal SCSI$C_OTHER = 1; ! INQUIRY data in pre-SCSI-2 format literal SCSI$C_SCSI_2 = 2; ! INQUIRY data in SCSI-2 format literal SCSI$INQ$M_HIERARCH_SUPPORT = %X'10'; literal SCSI$INQ$M_NORMAL_ACA = %X'20'; literal SCSI$INQ$M_TRMIOP = %X'40'; literal SCSI$INQ$M_AENC = %X'80'; literal SCSI$INQ$M_PROTECT = %X'1'; literal SCSI$INQ$M_3PC = %X'8'; literal SCSI$INQ$M_TPGS = %X'30'; literal SCSI$INQ$C_NO_ASYM = 0; ! No asymmetric logical unit access literal SCSI$INQ$C_IMPLICIT_ASYM_ONLY = 1; ! Implicit asymmetric access only literal SCSI$INQ$C_EXPLICIT_ASYM_ONLY = 2; ! Explicit asymmetric access only literal SCSI$INQ$C_IMPL_EXPL_ASYM = 3; ! Both implicit and explicit asymmetric access supported literal SCSI$INQ$M_ACC = %X'40'; literal SCSI$INQ$M_SSC_SUPPORT = %X'80'; literal SCSI$INQ$M_ADDRESS_16BIT = %X'1'; literal SCSI$INQ$M_ADDRESS_32BIT = %X'2'; literal SCSI$INQ$M_REQ_ACK_XFERS = %X'4'; literal SCSI$INQ$M_MEDIUM_CHANGER = %X'8'; literal SCSI$INQ$M_MULTI_PORT = %X'10'; literal SCSI$INQ$M_VENDOR_SPEC1 = %X'20'; literal SCSI$INQ$M_ENCLOSURE_SVCS = %X'40'; literal SCSI$INQ$M_BASIC_QUEUING = %X'80'; literal SCSI$INQ$M_SFTRE = %X'1'; literal SCSI$INQ$M_CMDQUE = %X'2'; literal SCSI$INQ$M_XFER_DISABLE = %X'4'; literal SCSI$INQ$M_LINKED = %X'8'; literal SCSI$INQ$M_SYNC = %X'10'; literal SCSI$INQ$M_WBUS16 = %X'20'; literal SCSI$INQ$M_WBUS32 = %X'40'; literal SCSI$INQ$M_RELADR = %X'80'; literal INQ_DATA$K_STANDARD_LENGTH = 36; literal SCSI$INQ$M_IUS = %X'1'; literal SCSI$INQ$M_QAS = %X'2'; literal SCSI$INQ$M_CLOCKING = %X'C'; literal SCSI$C_ST_ONLY = 0; ! Device server supports only ST literal SCSI$C_DT_ONLY = 1; ! Device server supports only DT literal SCSI$C_ST_AND_DT = 3; ! Device server supports ST and DT literal SCSI$INQ$M_RESERVED3 = %X'F'; literal SCSI$INQ$M_OTHER_STATUS = %X'10'; literal SCSI$INQ$M_MULTIBUS = %X'20'; literal SCSI$INQ$M_BOOT_PREFERENCE = %X'40'; literal SCSI$INQ$M_EXT_LUN_SUPPORT = %X'80'; literal INQ_DATA$K_LENGTH = 255; literal SCSI$INQ$S_INQUIRY_DATA = 256; macro SCSI$INQ$R_PERIPHERAL = 0,0,8,0 %; literal SCSI$INQ$S_PERIPHERAL = 1; ! Peripheral device types & qualifiers macro SCSI$INQ$V_DEVICE_TYPE = 0,0,5,0 %; literal SCSI$INQ$S_DEVICE_TYPE = 5; ! Peripheral device type macro SCSI$INQ$V_QUALIFIER = 0,5,3,0 %; literal SCSI$INQ$S_QUALIFIER = 3; ! Peripheral qualifer macro SCSI$INQ$R_DEVICE_TYPE_MOD = 1,0,8,0 %; literal SCSI$INQ$S_DEVICE_TYPE_MOD = 1; ! Device Type Modifiers macro SCSI$INQ$V_MODIFIER = 1,0,7,0 %; literal SCSI$INQ$S_MODIFIER = 7; ! SCSI-2: Device Type Modifiers macro SCSI$INQ$V_RMB = 1,7,1,0 %; ! Removalable media bit macro SCSI$INQ$R_VERSION = 2,0,8,0 %; literal SCSI$INQ$S_VERSION = 1; ! SCSI Versions macro SCSI$INQ$V_ANSI_VERSION = 2,0,3,0 %; literal SCSI$INQ$S_ANSI_VERSION = 3; ! ANSI Approved Version macro SCSI$INQ$V_ECMA_VERSION = 2,3,3,0 %; literal SCSI$INQ$S_ECMA_VERSION = 3; ! ECMA version number macro SCSI$INQ$V_ISO_VERSION = 2,6,2,0 %; literal SCSI$INQ$S_ISO_VERSION = 2; ! ISO version number macro SCSI$INQ$R_FLAGS_1 = 3,0,8,0 %; literal SCSI$INQ$S_FLAGS_1 = 1; ! SCSI INQUIRY Flags macro SCSI$INQ$V_RESP_DATA_FORMAT = 3,0,4,0 %; literal SCSI$INQ$S_RESP_DATA_FORMAT = 4; ! Response data (INQUIRY) format macro SCSI$INQ$V_HIERARCH_SUPPORT = 3,4,1,0 %; ! SCSI-3: Hierarchical addressing model used macro SCSI$INQ$V_NORMAL_ACA = 3,5,1,0 %; ! SCSI-3: CDB NACA bit supported macro SCSI$INQ$V_TRMIOP = 3,6,1,0 %; ! Device supports terminate I/O process macro SCSI$INQ$V_AENC = 3,7,1,0 %; ! Device supports Asych. Event Notification macro SCSI$INQ$B_ADD_LENGTH = 4,0,8,0 %; ! Additional length in bytes of parameters macro SCSI$INQ$R_SSCS = 5,0,8,0 %; literal SCSI$INQ$S_SSCS = 1; macro SCSI$INQ$V_PROTECT = 5,0,1,0 %; ! Logical unit supports protection information macro SCSI$INQ$V_3PC = 5,3,1,0 %; ! Third-party Copy support macro SCSI$INQ$V_TPGS = 5,4,2,0 %; literal SCSI$INQ$S_TPGS = 2; ! Target port group support macro SCSI$INQ$V_ACC = 5,6,1,0 %; ! Device contains an access controls coordinator macro SCSI$INQ$V_SSC_SUPPORT = 5,7,1,0 %; ! SCSI-3: Device has embedded storage array controller macro SCSI$INQ$R_FLAGS_2 = 6,0,8,0 %; literal SCSI$INQ$S_FLAGS_2 = 1; ! SCSI-3 Flags macro SCSI$INQ$V_ADDRESS_16BIT = 6,0,1,0 %; ! 16 bit SCSI addresses supported macro SCSI$INQ$V_ADDRESS_32BIT = 6,1,1,0 %; ! 32 bit SCSI addresses supported macro SCSI$INQ$V_REQ_ACK_XFERS = 6,2,1,0 %; ! Request/Acknowledge transfer supported macro SCSI$INQ$V_MEDIUM_CHANGER = 6,3,1,0 %; ! Device has medium transport element macro SCSI$INQ$V_MULTI_PORT = 6,4,1,0 %; ! Device has 2 or more ports macro SCSI$INQ$V_VENDOR_SPEC1 = 6,5,1,0 %; ! Defined by vendor macro SCSI$INQ$V_ENCLOSURE_SVCS = 6,6,1,0 %; ! Device has embedded enclosure services component macro SCSI$INQ$V_BASIC_QUEUING = 6,7,1,0 %; ! Basic task management (SAM) model supported macro SCSI$INQ$R_FLAGS = 7,0,8,0 %; literal SCSI$INQ$S_FLAGS = 1; ! SCSI INQUIRY Flags macro SCSI$INQ$V_SFTRE = 7,0,1,0 %; ! SCSI-2: Device supports soft resets. (SCSI-3: vendor-specific). macro SCSI$INQ$V_CMDQUE = 7,1,1,0 %; ! Device supports tagged command queueing macro SCSI$INQ$V_XFER_DISABLE = 7,2,1,0 %; ! SCSI-3: Supports continue task, target transfer disable macro SCSI$INQ$V_LINKED = 7,3,1,0 %; ! Device supports linked commands macro SCSI$INQ$V_SYNC = 7,4,1,0 %; ! Device supports synchronous data xfer macro SCSI$INQ$V_WBUS16 = 7,5,1,0 %; ! Device supports 16-bit data xfers macro SCSI$INQ$V_WBUS32 = 7,6,1,0 %; ! Device supports 32-bit data xfers macro SCSI$INQ$V_RELADR = 7,7,1,0 %; ! Device supports relative address for linked cmds macro SCSI$INQ$B_VENDOR_ID = 8,0,0,1 %; literal SCSI$INQ$S_VENDOR_ID = 8; ! Vendor Identification field macro SCSI$INQ$B_PRODUCT_ID = 16,0,0,1 %; literal SCSI$INQ$S_PRODUCT_ID = 16; ! Product Identification field macro SCSI$INQ$B_PRODUCT_REVISION = 32,0,32,1 %; literal SCSI$INQ$S_PRODUCT_REVISION = 4; ! Vendor Product Revision level macro SCSI$INQ$B_THIS_SERIAL_NO = 36,0,0,0 %; literal SCSI$INQ$S_THIS_SERIAL_NO = 10; ! This controller's serial number macro SCSI$INQ$B_OTHER_SERIAL_NO = 46,0,0,0 %; literal SCSI$INQ$S_OTHER_SERIAL_NO = 10; ! Other controller's serial number macro SCSI$INQ$R_FLAGS_4 = 56,0,8,0 %; literal SCSI$INQ$S_FLAGS_4 = 1; ! Additional SCSI INQUIRY Flags from SPC-3 macro SCSI$INQ$V_IUS = 56,0,1,0 %; ! Indicates Information Units support macro SCSI$INQ$V_QAS = 56,1,1,0 %; ! Indicates Quick Arbitration and Selection support macro SCSI$INQ$V_CLOCKING = 56,2,2,0 %; literal SCSI$INQ$S_CLOCKING = 2; ! Indicates ST and DT synchronous transfer support macro SCSI$INQ$R_FLAGS_3 = 96,0,8,0 %; literal SCSI$INQ$S_FLAGS_3 = 1; ! SCSI-3 Flags macro SCSI$INQ$V_RESERVED3 = 96,0,4,0 %; literal SCSI$INQ$S_RESERVED3 = 4; ! reserved macro SCSI$INQ$V_OTHER_STATUS = 96,4,1,0 %; ! Other controller is up macro SCSI$INQ$V_MULTIBUS = 96,5,1,0 %; ! In multi-bus failover mode (HCCF) macro SCSI$INQ$V_BOOT_PREFERENCE = 96,6,1,0 %; ! Owned by this controller at controller boot macro SCSI$INQ$V_EXT_LUN_SUPPORT = 96,7,1,0 %; ! 32 LUNs per target support macro SCSI$INQ$B_PREFERRED_LUNS = 97,0,0,0 %; literal SCSI$INQ$S_PREFERRED_LUNS = 32; ! LUNs preferred to this controller macro SCSI$INQ$B_NODE_ID = 130,0,0,0 %; literal SCSI$INQ$S_NODE_ID = 8; ! Alternate location for node's WWID macro SCSI$INQ$B_ALLOCATION_CLASS = 242,0,32,0 %; literal SCSI$INQ$S_ALLOCATION_CLASS = 4; ! Allocation class macro SCSI$INQ$B_FILL1 = 255,0,8,0 %; ! Fill for alignment ! ! Mode Parameter Header (six byte) ! literal SCSI$MPH6$S_MODE_PARAM_HDR_6 = 4; macro SCSI$MPH6$B_DATA_LENGTH = 0,0,8,0 %; ! Mode data Length macro SCSI$MPH6$B_MEDIUM_TYPE = 1,0,8,0 %; ! Medium type macro SCSI$MPH6$B_DEVICE_PARAM = 2,0,8,0 %; ! Device-specific parameter macro SCSI$MPH6$B_BLOCK_LENGTH = 3,0,8,0 %; ! Block descriptor length ! ! Mode Parameter Header (ten byte) ! literal SCSI$MPH10$S_MODE_PARAM_HDR_10 = 8; macro SCSI$MPH10$W_DATA_LENGTH = 0,0,16,0 %; ! Mode data Length macro SCSI$MPH10$B_MEDIUM_TYPE = 2,0,8,0 %; ! Medium type macro SCSI$MPH10$B_DEVICE_PARAM = 3,0,8,0 %; ! Device-specific parameter macro SCSI$MPH10$B_RESERVED1 = 4,0,16,0 %; literal SCSI$MPH10$S_RESERVED1 = 2; ! Reserved macro SCSI$MPH10$W_BLOCK_LENGTH = 6,0,16,0 %; ! Block descriptor length ! ! Mode Parameters used with direct access devices (DK) ! literal SCSI$DK$C_DEFAULT = 0; ! Default medium type (currently mounted medium type) literal SCSI$DK$C_SS = 1; ! Flexible disk, single-sided; unspecified medium literal SCSI$DK$C_DS = 2; ! Flexible disk, double-sided; unspecified medium literal SCSI$DK$C_DD = 3; ! Flexible disk, double-sided; double-density ! ! Direct-Access params ! literal SCSI$DK$M_DPOFUA = %X'10'; literal SCSI$DK$M_WP = %X'80'; literal SCSI$DK$S_DISK_SPECIFIC_PARAM = 1; macro SCSI$DK$V_DPOFUA = 0,4,1,0 %; ! Disable Page Out/Force Unit Access macro SCSI$DK$V_WP = 0,7,1,0 %; ! Write Protect ! ! CD-ROM specific parameter ! literal SCSI$CD$M_EBC = %X'1'; literal SCSI$CD$M_CACHE = %X'10'; literal SCSI$CD$S_CDROM_SPECIFIC_PARAM = 1; macro SCSI$CD$V_EBC = 0,0,1,0 %; ! Enable Blank Check macro SCSI$CD$V_CACHE = 0,4,1,0 %; ! Device supports cache memory ! ! Mode Parameter Block Descriptor ! literal SCSI$MPBD$S_MODE_PARAMETER = 8; macro SCSI$MPBD$B_DENSITY = 0,0,8,0 %; ! Device specific density code macro SCSI$MPBD$B_BLOCK = 1,0,24,0 %; literal SCSI$MPBD$S_BLOCK = 3; ! # of logical blocks density applies macro SCSI$MPBD$B_LENGTH = 5,0,24,0 %; literal SCSI$MPBD$S_LENGTH = 3; ! # of bytes in each logical block ! ! Identify Message ! literal SCSI$IDENT$M_LUNTRN = %X'7'; literal SCSI$IDENT$M_LUNTAR = %X'20'; literal SCSI$IDENT$M_DISC_PRIV = %X'40'; literal SCSI$IDENT$M_IDENTIFY = %X'80'; literal SCSI$IDENT$S_IDENTIFY_MESSAGE = 1; macro SCSI$IDENT$R_FLAGS = 0,0,8,0 %; literal SCSI$IDENT$S_FLAGS = 1; macro SCSI$IDENT$V_LUNTRN = 0,0,3,0 %; literal SCSI$IDENT$S_LUNTRN = 3; ! Logical Unit Target Routine # macro SCSI$IDENT$V_LUNTAR = 0,5,1,0 %; ! Logical Unit Target direction macro SCSI$IDENT$V_DISC_PRIV = 0,6,1,0 %; ! Grant target privilege of disconnecting macro SCSI$IDENT$V_IDENTIFY = 0,7,1,0 %; ! Message is an IDENTIFY message ! ! Define SCSI status codes ! literal SCSI$C_GOOD = 0; ! Sucessfull completion of command literal SCSI$C_CHECK_CONDITION = 2; ! Contingent allegiance condition literal SCSI$C_CONDITION_MET = 4; ! Requested operation satisfied literal SCSI$C_BUSY = 8; ! Target busy literal SCSI$C_INTERMEDIATE = 16; ! Completed linked command in series literal SCSI$C_INTERMEDIATE_COND_MET = 20; ! INTERMEDIATE and CONDITION_MET literal SCSI$C_RESERVATION_CONFLICT = 24; ! Conflicting reservation conflict literal SCSI$C_COMMAND_TERMINATED = 34; ! Target terminates current I/O literal SCSI$C_QUEUE_FULL = 40; ! Command queue is full literal SCSI$M_STATUS_BYTE_RESERVED = 193; ! Status byte reserved bits ! ! Define SCSI Message Codes ! literal SCSI$C_COMMAND_COMPLETE = 0; ! I/O completed literal SCSI$C_EXTENDED_MESSAGE = 1; ! Start multi-byte extended message literal SCSI$C_SAVE_DATA_POINTERS = 2; ! Save active pointers literal SCSI$C_RESTORE_POINTERS = 3; ! Restore saved pointers literal SCSI$C_DISCONNECT = 4; ! Connection will disconnect literal SCSI$C_INITIATOR_DETECT_ERROR = 5; ! Inform target that error have occured literal SCSI$C_ABORT = 6; ! Clear active I/O, plus queued I/O literal SCSI$C_MESSAGE_REJECT = 7; ! Last message was inappropriate literal SCSI$C_NO_OPERATION = 8; ! Reponse when no current command literal SCSI$C_MESSAGE_PARITY_ERROR = 9; ! Last message byte had parity error literal SCSI$C_LINKED_COMMAND = 10; ! Linked command is complete literal SCSI$C_LINKED_COMMAND_FLAGED = 11; ! Linked command is complete (with flag) literal SCSI$C_BUS_DEVICE_RESET = 12; ! Reset device, go to bus free literal SCSI$C_ABORT_TAG = 13; ! Clear tagged command literal SCSI$C_CLEAR_QUEUE = 14; ! Clear all queued commands literal SCSI$C_INITIATE_RECOVERY = 15; ! Start ECA processing literal SCSI$C_RELEASE_RECOVERY = 16; ! Finish ECA processing literal SCSI$C_TERMINATE_IO_PROCESS = 17; ! Terminate I/O process literal SCSI$C_CLEAR_ACA = 22; literal SCSI$C_SIMPLE_QUEUE_TAG = 32; ! Queue I/O to queue literal SCSI$C_HEAD_OF_QUEUE_TAG = 33; ! Queue I/O to head of queue literal SCSI$C_ORDERED_QUEUE_TAG = 34; ! Queue I/O in order to queue literal SCSI$C_IGNORE_WIDE_RESIDUE = 35; ! Ignore residual bytes ! ! Define SCSI Message Codes ! literal SCSI$C_MODIFY_DATA_POINTER = 0; ! Modify data pointers literal SCSI$C_SYNCH_DATA_TRANSFER = 1; ! Synchronous Data Transfer Request literal SCSI$C_WIDE_DATA_TRANSFER = 3; ! Wide Data Transfer Request ! ! Sense Data Format ! literal SCSI$SNS$M_ERROR_CODE = %X'7F'; literal SCSI$SC1$C_CURRENT = 112; ! Current error codes literal SCSI$SC1$C_DEFERRED = 113; ! Current error codes literal SCSI$SNS$M_VALID = %X'80'; literal SCSI$SNS$M_SENSE_KEY = %X'F'; literal SCSI$SNS$M_ILI = %X'20'; literal SCSI$SNS$M_EOM = %X'40'; literal SCSI$SNS$M_FILEMARK = %X'80'; literal SCSI$SNS$R_ADD_INFORMATION_OS = 8; ! literal SCSI$C_RECOVERED_DATA = 23; ! Recovered data... ! ^X00 - with no error correction applied literal SCSI$C_INVALID_CDB_FIELD = 36; ! Invalid field in CDB ! ^X00 - invalid field in CDB literal SCSI$SNS$M_BIT_POINTER = %X'7'; literal SCSI$SNS$M_BPV = %X'8'; literal SCSI$SNS$M_C_D = %X'40'; literal SCSI$SNS$M_SKSV = %X'80'; literal SCSI$SNS$R_ADD_SENSE_OS = 18; ! literal SCSI$SNS$S_SENSE_DATA = 19; macro SCSI$SNS$R_ERROR_CODE_FIELD = 0,0,8,0 %; literal SCSI$SNS$S_ERROR_CODE_FIELD = 1; macro SCSI$SNS$V_ERROR_CODE = 0,0,7,0 %; literal SCSI$SNS$S_ERROR_CODE = 7; ! Sense data error codes macro SCSI$SNS$V_VALID = 0,7,1,0 %; ! Information Field Valid macro SCSI$SNS$B_SEGEMENT = 1,0,8,0 %; ! # of current segement desc. macro SCSI$SNS$R_FLAGS = 2,0,8,0 %; literal SCSI$SNS$S_FLAGS = 1; macro SCSI$SNS$V_SENSE_KEY = 2,0,4,0 %; literal SCSI$SNS$S_SENSE_KEY = 4; ! Information field macro SCSI$SNS$V_ILI = 2,5,1,0 %; ! Incorrect Length Indicator macro SCSI$SNS$V_EOM = 2,6,1,0 %; ! End of Medium Indicator macro SCSI$SNS$V_FILEMARK = 2,7,1,0 %; ! Filemark or Setmark seen macro SCSI$SNS$R_INFORMATION = 3,0,32,0 %; literal SCSI$SNS$S_INFORMATION = 4; ! Device/Command specific info. macro SCSI$SNS$L_LBA_ADDRESS = 3,0,32,0 %; ! Logical Block Address (Dev. Type 0,4,5,7) macro SCSI$SNS$L_RESIDUAL_LENGTH = 3,0,32,0 %; ! (requested - actual) length (Dev. Type 1,2,3) macro SCSI$SNS$L_RESIDUAL_BLOCKS = 3,0,32,0 %; ! (requested - actual) blocks (COPY, VERIFY, COMPARE) macro SCSI$SNS$L_DATA_BLOCKS = 3,0,32,0 %; ! Count of Data Blocks macro SCSI$SNS$L_FILE_MARKS = 3,0,32,0 %; ! Count of File Marks macro SCSI$SNS$L_SET_MARKS = 3,0,32,0 %; ! Count of Set Marks macro SCSI$SNS$B_ADD_SENSE_LEN = 7,0,8,0 %; ! Additional Sense Length macro SCSI$SNS$R_ADD_INFORMATION = 8,0,32,0 %; literal SCSI$SNS$S_ADD_INFORMATION = 4; ! Command specific info. macro SCSI$SNS$B_SENSE_INFORMATION = 8,0,32,0 %; literal SCSI$SNS$S_SENSE_INFORMATION = 4; ! Sense information macro SCSI$SNS$B_ADD_SENSE_CODE = 12,0,8,0 %; ! Additional Sense Code ! ^X01 - with retries ! ^X02 - with positive head offset ! ^X03 - with negative head offset ! ^X04 - with retries and/or circ applied ! ^X05 - using previous sector id ! ^X06 - without ecc - data auto-reallocated ! ^X07 - without ecc - recommend reassignment macro SCSI$SNS$B_ADD_SENSE_QUAL = 13,0,8,0 %; ! Additional Sense Qualifier macro SCSI$SNS$B_FRU_CODE = 14,0,8,0 %; ! Field Replaceable Unit Code macro SCSI$SNS$R_SENSE_KEY_SPECIFIC = 15,0,24,0 %; literal SCSI$SNS$S_SENSE_KEY_SPECIFIC = 3; macro SCSI$SNS$V_BIT_POINTER = 15,0,3,0 %; literal SCSI$SNS$S_BIT_POINTER = 3; ! Bitfield pointer to error byte macro SCSI$SNS$V_BPV = 15,3,1,0 %; ! Bit Pointer Valid macro SCSI$SNS$V_C_D = 15,6,1,0 %; ! Command_Data error indicator macro SCSI$SNS$V_SKSV = 15,7,1,0 %; ! Sense Key Specific - Valid macro SCSI$SNS$W_FIELD_POINTER = 16,0,16,0 %; ! Command or Data byte error pointer macro SCSI$SNS$R_ADD_SENSE = 18,0,8,0 %; literal SCSI$SNS$S_ADD_SENSE = 1; ! Additional Sense data0 macro SCSI$SNS$B_ADD_SENSE_BYTES = 18,0,8,0 %; literal SCSI$SNS$S_ADD_SENSE_BYTES = 1; ! Additional Sense Bytes ! ! Define SCSI sense key codes. ! literal SCSI$C_NO_SENSE = 0; ! No sense key information returned literal SCSI$C_RECOVERED_ERROR = 1; ! Command completed with some recovery action literal SCSI$C_NOT_READY = 2; ! Logical unit cannot be accessed literal SCSI$C_MEDIUM_ERROR = 3; ! Command failed with non-recovered medium error literal SCSI$C_HARDWARE_ERROR = 4; ! Command failed with non-recovered hardware error literal SCSI$C_ILLEGAL_REQUEST = 5; ! Illegal parameter in the command descriptor block literal SCSI$C_UNIT_ATTENTION = 6; ! Removable medium change or target has been reset literal SCSI$C_DATA_PROTECT = 7; ! Read/Write of medium failed due to protection literal SCSI$C_BLANK_CHECK = 8; ! Read/Write found blank medium, end-of-data, etc. literal SCSI$C_VENDOR_SPECIFIC = 9; ! Vendor specific conditions reported literal SCSI$C_COPY_ABORTED = 10; ! Copy, compare or Copy/Verify aborted due to error literal SCSI$C_ABORTED_COMMAND = 11; ! Targeted aborted current command literal SCSI$C_EQUAL = 12; ! Search Data command has equal comparison literal SCSI$C_VOLUME_OVERFLOW = 13; ! Buffered device has reach end of parition literal SCSI$C_MISCOMPARE = 14; ! Source data command has unequal comparison literal SCSI$C_RESERVED = 15; ! Reserved ! ! Selected SCSI Mode Page Codes ! literal SCSI$C_AUDIO_CONTROL_PAGE = 14; ! CD-ROM Audio Control Page literal SCSI$C_MEDIA_CHANGE = 40; ! Medium change ! ^X00 - Not ready to ready transition (medium change) literal SCSI$C_MODE_CHANGE = 42; ! Mode change ! ^X00 - Parameters changed ! ^X01 - Mode parameters changed ! ^X02 - Log parameters changed literal SCSI$C_INCOMPATIBLE_MEDIA = 48; ! Unformatted media ! ^X00 - Incompatible medium installed ! ^X01 - Cannot read medium - unknown format ! ^X02 - Cannot read medium - incompatible format ! ^X03 - Cleaning cartridge installed literal SCSI$C_DRIVE_NOT_READY = 4; ! Logical unit... ! ^X00 - not ready, cause not reportable ! ^X01 - is in process of becoming ready ! ^X02 - not ready, initializing command required ! ^X03 - not ready, manual intervention required ! ^X04 - not ready, format in progress literal SCSI$C_MEDIUM_NOT_PRESENT = 58; ! Medium not present ! ^X00 - Medium not present ? ! ! Type codes for Optical Memory Medium-Type Codes ! literal SCSI$OPT$C_MEDIA_DEFAULT = 0; ! Default (only one medium type supported) literal SCSI$OPT$C_MEDIA_RO = 1; ! Optical Read Only medium literal SCSI$OPT$C_MEDIA_WORM = 2; ! Optical Write Once medium literal SCSI$OPT$C_MEDIA_ERASE = 3; ! Optical Reversible or Erasable medium literal SCSI$OPT$C_MEDIA_RO_WORM = 4; ! Combination of Read only and Write Once medium literal SCSI$OPT$C_MEDIA_RO_ERASE = 5; ! Combination of Read only and Reversible or Erasable medium literal SCSI$OPT$C_MEDIA_WORM_ERASE = 6; ! Combination of Write Once and Reversible or Erasable medium ! ! Mode sense page code paramaters ! literal SCSI$PGCD$C_VENDOR_SPECIFIC = 0; ! Vendor-Specific (does not require page format) literal SCSI$PGCD$C_READ_WRITE_ERR = 1; ! Read-Write Error Recovery Page literal SCSI$PGCD$C_DISCONNECT_REC = 2; ! Disconnect-Reconnect Page literal SCSI$PGCD$C_FORMAT_DEVICE = 3; ! Format Device Page literal SCSI$PGCD$C_RIGID_DISK = 4; ! Rigid Disk Geometry Page literal SCSI$PGCD$C_FLEXIBLE_DISK = 5; ! Flexible Disk Page literal SCSI$PGCD$C_RESERVED = 6; ! Reserved literal SCSI$PGCD$C_VERIFY_ERROR = 7; ! Verify Error Recovery Page literal SCSI$PGCD$C_CACHING = 8; ! Caching Page literal SCSI$PGCD$C_PERIPHERAL = 9; ! Peripheral Device Page literal SCSI$PGCD$C_CONTROL_MODE = 10; ! Control Mode Page literal SCSI$PGCD$C_MEDIUM_TYPES = 11; ! Medium Types Supported Page literal SCSI$PGCD$C_NOTCH_PARTION = 12; ! Notch and Partition Page literal SCSI$PGCD$C_ALL_PAGES = 63; ! Return all pages literal SCSI$PGCD$C_MAX_PAGE_CODE = 63; ! Maximum Page Code literal SCSI$PGCD$M_CURRENT = 0; ! Current Values literal SCSI$PGCD$M_CHANGEABLE = 64; ! Changeable Values literal SCSI$PGCD$M_DEFAULT = 128; ! Default Values literal SCSI$PGCD$M_SAVED = 192; ! Saved Values literal SCSI$PGCD$C_PAGE_SIZE = 512; ! Initial Page Size ! ! Audio Control Parameters Page ! literal SCSI$ACP$M_PAGE_CODE = %X'3F'; literal SCSI$ACP$C_PAGE_CODE = 14; literal SCSI$ACP$M_PS = %X'80'; literal SCSI$S_HEADER = 2; ! SCSI Page header size (PAGE_CODE+PAGE_LENGTH) literal SCSI$ACP$C_PAGE_LENGTH = 14; literal SCSI$ACP$M_SOTC = %X'2'; literal SCSI$ACP$M_IMMED = %X'4'; literal SCSI$ACP$M_LBA_FORMAT = %X'F000000'; literal SCSI$ACP$M_CHANNEL_0 = %X'1'; literal SCSI$ACP$M_CHANNEL_1 = %X'2'; literal SCSI$ACP$M_CHANNEL_2 = %X'4'; literal SCSI$ACP$M_CHANNEL_3 = %X'8'; literal SCSI$ACP$S_AUDIO_CONTROL = 16; macro SCSI$ACP$R_PAGE_CODE_FIELD = 0,0,8,0 %; literal SCSI$ACP$S_PAGE_CODE_FIELD = 1; ! Page code & save bits macro SCSI$ACP$V_PAGE_CODE = 0,0,6,0 %; literal SCSI$ACP$S_PAGE_CODE = 6; ! Page code macro SCSI$ACP$V_PS = 0,7,1,0 %; ! PS - Parameters Saveable bit in non-VM macro SCSI$ACP$B_PAGE_LENGTH = 1,0,8,0 %; ! Page length macro SCSI$ACP$R_AUDIO_CONTROL_FLAGS = 2,0,32,0 %; literal SCSI$ACP$S_AUDIO_CONTROL_FLAGS = 4; ! Audio Control Flags macro SCSI$ACP$V_SOTC = 2,1,1,0 %; ! Stop On Track Crossing macro SCSI$ACP$V_IMMED = 2,2,1,0 %; ! Send completion status immediately macro SCSI$ACP$V_LBA_FORMAT = 2,24,4,0 %; literal SCSI$ACP$S_LBA_FORMAT = 4; ! Format of LBSa / Second macro SCSI$ACP$W_LBS_PER_SEC = 6,0,16,0 %; ! Logical blocks per sec. of audio playback macro SCSI$ACP$W_CHANNEL_VOLUME = 8,0,0,0 %; literal SCSI$ACP$S_CHANNEL_VOLUME = 8; macro SCSI$ACP$V_CHANNEL_0 = 8,0,1,0 %; ! Connect audio channel 0 to this port macro SCSI$ACP$V_CHANNEL_1 = 8,1,1,0 %; ! Connect audio channel 1 to this port macro SCSI$ACP$V_CHANNEL_2 = 8,2,1,0 %; ! Connect audio channel 2 to this port macro SCSI$ACP$V_CHANNEL_3 = 8,3,1,0 %; ! Connect audio channel 3 to this port macro SCSI$ACP$B_VOLUME = 9,0,8,0 %; ! Channel volume from %X00(muted) to %XFF(full) ! ! Control Mode Page ! literal SCSI$CMP$M_PAGE_CODE = %X'3F'; literal SCSI$CMP$C_PAGE_CODE = 10; literal SCSI$CMP$M_PS = %X'80'; literal SCSI$CMP$C_PAGE_LENGTH = 6; literal SCSI$CMP$M_RLEC = %X'1'; literal SCSI$CMP$M_DQUE = %X'100'; literal SCSI$CMP$M_QERR = %X'200'; literal SCSI$CMP$M_QAM = %X'7000'; literal SCSI$QAM$C_RESTRICTED = 0; ! Restricted Re-ordering literal SCSI$QAM$C_UNRESTRICTED = 1; ! Unrestricted Re-ordering literal SCSI$CMP$M_EAENP = %X'8000'; literal SCSI$CMP$M_UAAENP = %X'10000'; literal SCSI$CMP$M_RAENP = %X'20000'; literal SCSI$CMP$M_EECA = %X'400000'; literal SCSI$CMP$C_LENGTH = 8; ! Length of the SCSI Control Mode page literal SCSI$CMP$K_LENGTH = 8; ! Length of the SCSI Control Mode page literal SCSI$CMP$S_CONTROL_MODE = 8; macro SCSI$CMP$R_PAGE_CODE_FIELD = 0,0,8,0 %; literal SCSI$CMP$S_PAGE_CODE_FIELD = 1; ! Page code & save bits macro SCSI$CMP$V_PAGE_CODE = 0,0,6,0 %; literal SCSI$CMP$S_PAGE_CODE = 6; ! Page code macro SCSI$CMP$V_PS = 0,7,1,0 %; ! PS - Parameters Saveable bit in non-VM macro SCSI$CMP$B_PAGE_LENGTH = 1,0,8,0 %; ! Page length macro SCSI$CMP$R_CONTROL_MODE_FLAGS = 2,0,24,0 %; literal SCSI$CMP$S_CONTROL_MODE_FLAGS = 3; ! Control Mode Flags macro SCSI$CMP$V_RLEC = 2,0,1,0 %; ! Targer reports log exception conditions macro SCSI$CMP$V_DQUE = 2,8,1,0 %; ! Disable tagged queuing macro SCSI$CMP$V_QERR = 2,9,1,0 %; ! Abort queue processing on CA or ACA macro SCSI$CMP$V_QAM = 2,12,3,0 %; literal SCSI$CMP$S_QAM = 3; ! Queue Algorithm Modifier Field macro SCSI$CMP$V_EAENP = 2,15,1,0 %; ! Error - AEN macro SCSI$CMP$V_UAAENP = 2,16,1,0 %; ! Unit Attention - AEN macro SCSI$CMP$V_RAENP = 2,17,1,0 %; ! Ready - AEN macro SCSI$CMP$V_EECA = 2,22,1,0 %; ! Enable Extended Contingent Allegiance macro SCSI$CMP$W_READY_AEN = 6,0,16,0 %; ! Ready AEN holdoff period ! ! Read-Write Error Recovery Page ! ! Define the error recover parameters that the target shall use during any command ! that performs a read-write operation. ! literal SCSI$ERP$M_PAGE_CODE = %X'3F'; literal SCSI$ERP$C_PAGE_CODE = 1; literal SCSI$ERP$M_PS = %X'80'; literal SCSI$ERP$C_PAGE_LENGTH = 10; literal SCSI$ERP$M_DCR = %X'1'; literal SCSI$ERP$M_DTE = %X'2'; literal SCSI$ERP$M_PER = %X'4'; literal SCSI$ERP$M_EER = %X'8'; literal SCSI$ERP$M_RC = %X'10'; literal SCSI$ERP$M_TB = %X'20'; literal SCSI$ERP$M_ARRE = %X'40'; literal SCSI$ERP$M_AWRE = %X'80'; literal SCSI$ERP$C_LENGTH = 16; ! Length of the SCSI Error Recovery page literal SCSI$ERP$K_LENGTH = 16; ! Length of the SCSI Error Recovery page literal SCSI$ERP$S_ERROR_RECOVERY = 16; macro SCSI$ERP$R_PAGE_CODE_FIELD = 0,0,8,0 %; literal SCSI$ERP$S_PAGE_CODE_FIELD = 1; ! Page code & save bits macro SCSI$ERP$V_PAGE_CODE = 0,0,6,0 %; literal SCSI$ERP$S_PAGE_CODE = 6; ! Page code macro SCSI$ERP$V_PS = 0,7,1,0 %; ! PS - Parameters Saveable bit in non-VM macro SCSI$ERP$B_PAGE_LENGTH = 1,0,8,0 %; ! Page length macro SCSI$ERP$R_RECOVERY_FLAGS = 2,0,8,0 %; literal SCSI$ERP$S_RECOVERY_FLAGS = 1; ! Read-Write Error Recovery Page flags macro SCSI$ERP$V_DCR = 2,0,1,0 %; ! Disable error correction macro SCSI$ERP$V_DTE = 2,1,1,0 %; ! Disable transfer on error macro SCSI$ERP$V_PER = 2,2,1,0 %; ! Post error macro SCSI$ERP$V_EER = 2,3,1,0 %; ! Enable early correction macro SCSI$ERP$V_RC = 2,4,1,0 %; ! Read continuous macro SCSI$ERP$V_TB = 2,5,1,0 %; ! Transfer block macro SCSI$ERP$V_ARRE = 2,6,1,0 %; ! Automatic read relocation of blocks macro SCSI$ERP$V_AWRE = 2,7,1,0 %; ! Automatic write relocation of blocks macro SCSI$ERP$B_READ_RERTY_COUNT = 3,0,8,0 %; ! Read count of retry attempts macro SCSI$ERP$B_CORRECTION_SPAN = 4,0,8,0 %; ! Bit size of largest data error attempt macro SCSI$ERP$B_HEAD_OFFSET_COUNT = 5,0,8,0 %; ! 2's complement of head offset from track macro SCSI$ERP$B_DATA_STROBE_OFFSET = 6,0,8,0 %; ! 2's complement of data strobe offset macro SCSI$ERP$B_WRITE_RETRY_COUNT = 8,0,8,0 %; ! Write count of retry attempts macro SCSI$ERP$W_RECOVERY_TIME_LIMIT = 10,0,16,0 %; ! ms max. time for error recovery ! ! Format Device Page ! literal SCSI$FMT$M_PAGE_CODE = %X'3F'; literal SCSI$FMT$C_PAGE_CODE = 3; literal SCSI$FMT$M_PS = %X'80'; literal SCSI$FMT$C_PAGE_LENGTH = 22; literal SCSI$FMT$M_SURF = %X'10'; literal SCSI$FMT$M_RMB = %X'20'; literal SCSI$FMT$M_HSEC = %X'40'; literal SCSI$FMT$M_SSEC = %X'80'; literal SCSI$FMT$S_FORMAT_DEVICE = 24; macro SCSI$FMT$R_PAGE_CODE_FIELD = 0,0,8,0 %; literal SCSI$FMT$S_PAGE_CODE_FIELD = 1; ! Page code & save bits macro SCSI$FMT$V_PAGE_CODE = 0,0,6,0 %; literal SCSI$FMT$S_PAGE_CODE = 6; ! Page code macro SCSI$FMT$V_PS = 0,7,1,0 %; ! PS - Parameters Saveable bit in non-VM macro SCSI$FMT$B_PAGE_LENGTH = 1,0,8,0 %; ! Page length macro SCSI$FMT$W_TRACKS = 2,0,16,0 %; ! Tracks per Zone macro SCSI$FMT$W_ALT_SECTORS = 4,0,16,0 %; ! Alternate Sectors per Zone macro SCSI$FMT$W_ALT_TRACKS = 6,0,16,0 %; ! Alternate Tracks per Zone macro SCSI$FMT$W_ALT_TRACKS_UNIT = 8,0,16,0 %; ! Alternate Tracks per Logical Unit macro SCSI$FMT$W_SECTORS = 10,0,16,0 %; ! Sectors per Track macro SCSI$FMT$W_SECTOR_SIZE = 12,0,16,0 %; ! Data Bytes per Physical Sector macro SCSI$FMT$W_INTERLEAVE = 14,0,16,0 %; ! Interleave macro SCSI$FMT$W_TRACK_SKEW = 16,0,16,0 %; ! Track Skew Factor macro SCSI$FMT$W_CYL_SKEW = 18,0,16,0 %; ! Cylinder Skew Factor macro SCSI$FMT$R_FLAGS = 20,0,8,0 %; literal SCSI$FMT$S_FLAGS = 1; macro SCSI$FMT$V_SURF = 20,4,1,0 %; ! Sector .vs. Cylindar allocation macro SCSI$FMT$V_RMB = 20,5,1,0 %; ! Removeable macro SCSI$FMT$V_HSEC = 20,6,1,0 %; ! Hard Sector Formatting macro SCSI$FMT$V_SSEC = 20,7,1,0 %; ! Soft Sector Formatting ! ! Rigid Disk Driver Page ! ! The rigid disk drive geometry page specifies parameters for direct-access ! devices employing a rigid disk drive. ! literal SCSI$RGD$M_PAGE_CODE = %X'3F'; literal SCSI$RGD$C_PAGE_CODE = 4; literal SCSI$RGD$M_PS = %X'80'; literal SCSI$RGD$C_PAGE_LENGTH = 22; literal SCSI$RGD$M_RPL = %X'3'; literal SCSI$RGD$C_DISABLED = 0; ! Spindle Synchronization is disabled literal SCSI$RGD$C_SLAVE = 1; ! Synchronized-Spindle Slave literal SCSI$RGD$C_MASTER = 2; ! Synchronized-Spindle Master. literal SCSI$RGD$C_CONTROL = 3; ! Synchronized-Spindle Master Control literal SCSI$RGD$S_RIGID_DISK = 21; macro SCSI$RGD$R_PAGE_CODE_FIELD = 0,0,8,0 %; literal SCSI$RGD$S_PAGE_CODE_FIELD = 1; ! Page code & save bits macro SCSI$RGD$V_PAGE_CODE = 0,0,6,0 %; literal SCSI$RGD$S_PAGE_CODE = 6; ! Page code macro SCSI$RGD$V_PS = 0,7,1,0 %; ! PS - Parameters Saveable bit in non-VM macro SCSI$RGD$B_PAGE_LENGTH = 1,0,8,0 %; ! Page length macro SCSI$RGD$B_CYLINDERS = 2,0,24,1 %; literal SCSI$RGD$S_CYLINDERS = 3; ! Number of cylinders macro SCSI$RGD$B_HEADS = 5,0,8,0 %; ! Number of heads macro SCSI$RGD$W_CYLINDER_WRITE = 6,0,16,0 %; ! Starting Cylinder-Write Precompensation macro SCSI$RGD$W_CYLINDER_REDUCED = 8,0,16,0 %; ! Starting Cylinder-Reduced Write Current macro SCSI$RGD$W_STEP_RATE = 10,0,16,0 %; ! Drive Step Rate macro SCSI$RGD$W_LANDING_ZONE = 12,0,16,0 %; ! Landing Zone Cylinder macro SCSI$RGD$R_FLAGS = 14,0,8,0 %; literal SCSI$RGD$S_FLAGS = 1; ! SCSI FLEXIBLE PAGE Flags macro SCSI$RGD$V_RPL = 14,0,2,0 %; literal SCSI$RGD$S_RPL = 2; ! Rotational Position Locking macro SCSI$RGD$B_ROTATIONAL_OFFSET = 15,0,8,0 %; ! Rotational Offset macro SCSI$RGD$W_MEDIUM_ROTATION = 17,0,16,0 %; ! Medium Rotation Rate macro SCSI$RGD$W_ROTATIONAL_OFFSET = 19,0,16,0 %; ! Rotational Offset ! ! Flexible Disk Page ! ! The flexible disk page contains parameters for control and reporting of ! flexible disk drive parameters ! literal SCSI$FLX$M_PAGE_CODE = %X'3F'; literal SCSI$FLX$C_PAGE_CODE = 5; literal SCSI$FLX$M_PS = %X'80'; literal SCSI$FLX$C_PAGE_LENGTH = 30; literal SCSI$FLX$C_XFR_250KHZ = 64000; ! 250 kbit/second transfer rate literal SCSI$FLX$C_XFR_300KHZ = 11265; ! 300 kbit/second transfer rate literal SCSI$FLX$C_XFR_500KHZ = 62465; ! 500 kbit/second transfer rate literal SCSI$FLX$C_XFR_1MHZ = 59395; ! 1 megabit/second transfer rate literal SCSI$FLX$C_XFR_2MHZ = 53255; ! 2 megabit/second transfer rate literal SCSI$FLX$C_XFR_5MHZ = 34835; ! 5 megabit/second transfer rate literal SCSI$FLX$M_MO = %X'20'; literal SCSI$FLX$M_SSN = %X'40'; literal SCSI$FLX$M_TRDY = %X'80'; literal SCSI$FLX$M_SPC = %X'F00'; literal SCSI$FLX$M_PIN2 = %X'1'; literal SCSI$FLX$M_PIN34 = %X'2'; literal SCSI$FLX$M_PIN1 = %X'4'; literal SCSI$FLX$M_PIN4 = %X'8'; literal SCSI$FLX$S_FLEXIBLE_DISK = 31; macro SCSI$FLX$R_PAGE_CODE_FIELD = 0,0,8,0 %; literal SCSI$FLX$S_PAGE_CODE_FIELD = 1; ! Page code & save bits macro SCSI$FLX$V_PAGE_CODE = 0,0,6,0 %; literal SCSI$FLX$S_PAGE_CODE = 6; ! Page code macro SCSI$FLX$V_PS = 0,7,1,0 %; ! PS - Parameters Saveable bit in non-VM macro SCSI$FLX$B_PAGE_LENGTH = 1,0,8,0 %; ! Page length macro SCSI$FLX$W_TRANSFER_RATE = 2,0,16,0 %; ! Transfer rate KHZ ! (Note: Definitions are SCSI Endian) macro SCSI$FLX$B_HEADS = 4,0,8,0 %; ! Number of heads macro SCSI$FLX$B_SECTORS_TRACK = 5,0,8,0 %; ! Sectors per track macro SCSI$FLX$W_SECTOR_SIZE = 6,0,16,0 %; ! Data bytes per sector macro SCSI$FLX$W_CYLINDERS = 8,0,16,0 %; ! Number of cylinders macro SCSI$FLX$W_CYLINDER_WRITE = 10,0,16,0 %; ! Starting Cylinder-Write Precompensation macro SCSI$FLX$W_CYLINDER_REDUCED = 12,0,16,0 %; ! Starting Cylinder-Reduced Write Current macro SCSI$FLX$W_STEP_RATE = 14,0,16,0 %; ! Drive Step Rate macro SCSI$FLX$B_STEP_PULSE = 16,0,8,0 %; ! Drive Step Pulse Width macro SCSI$FLX$W_HEAD_SETTLE = 17,0,16,0 %; ! Head Settle Delay macro SCSI$FLX$B_MOTOR_ON = 19,0,8,0 %; ! Motor on Delay macro SCSI$FLX$B_MOTOR_OFF = 20,0,8,0 %; ! Motor off Delay macro SCSI$FLX$R_FLAGS = 21,0,16,0 %; literal SCSI$FLX$S_FLAGS = 2; ! SCSI FLEXIBLE PAGE Flags macro SCSI$FLX$V_MO = 21,5,1,0 %; ! Motor on macro SCSI$FLX$V_SSN = 21,6,1,0 %; ! Starting Sector Number macro SCSI$FLX$V_TRDY = 21,7,1,0 %; ! True-Ready, media is accessable macro SCSI$FLX$V_SPC = 21,8,4,0 %; literal SCSI$FLX$S_SPC = 4; ! Step pulse/cylinder macro SCSI$FLX$B_WRITE_COMP = 23,0,8,0 %; ! Write Compensation macro SCSI$FLX$B_HEAD_LOAD = 24,0,8,0 %; ! Head Load Delay macro SCSI$FLX$B_HEAD_UNLOAD = 25,0,8,0 %; ! Head Unload delay macro SCSI$FLX$R_PINS = 26,0,8,0 %; literal SCSI$FLX$S_PINS = 1; macro SCSI$FLX$V_PIN2 = 26,0,1,0 %; ! Pin 2 of drive interface macro SCSI$FLX$V_PIN34 = 26,1,1,0 %; ! Pin 34 of drive interface macro SCSI$FLX$V_PIN1 = 26,2,1,0 %; ! Pin 1 of drive interface macro SCSI$FLX$V_PIN4 = 26,3,1,0 %; ! Pin 4 of drive interface macro SCSI$FLX$W_ROTATION = 27,0,16,0 %; ! Medium Rotation Rate ! ! Subchannel Data Format Codes ! literal SCSI$SUB$C_SUBQ_CHANNEL_DATA = 0; ! Sub-Q Channel data literal SCSI$SUB$C_CD_ROM_POSITION = 1; ! CD-ROM Current Position literal SCSI$SUB$C_MCN = 2; ! Media Catalog Number (UPC/Bar Code) literal SCSI$SUB$C_ISRC = 3; ! Track International-Standard-Recording-Code ! ! Sub-Q Channel Data Format ! literal SCSI$SUBQ$C_NOT_VALID = 0; ! Audio status byte not supported or not valid literal SCSI$SUBQ$C_PLAY = 1; ! Audio play operation in progress. literal SCSI$SUBQ$C_PAUSED = 2; ! Audio play operation paused. literal SCSI$SUBQ$C_COMPLETE = 3; ! Audio play operation successfully completed. literal SCSI$SUBQ$C_ERROR = 4; ! Audio play operation stopped due to error. literal SCSI$SUBQ$C_ACTIVE = 5; ! No current audio status to return literal SCSI$SUBQ$M_CONTROL = %X'F'; literal SCSI$SUBQ$C_PRE_EMPHASIS = 0; ! Audio with pre-emphasis literal SCSI$SUBQ$C_COPY_PERMITTED = 1; ! Digital copy permitted literal SCSI$SUBQ$C_DATA_TRACK = 2; ! Data verses audio track literal SCSI$SUBQ$C_FOUR_CHANNEL = 3; ! Four verses two channel audio literal SCSI$SUBQ$M_ADR = %X'F0'; literal SCSI$SUBQ$C_UNKNOWN = 0; ! mode information not supplied literal SCSI$SUBQ$C_CURRENT_POS = 1; ! Current position data (track,index,abs-addr,rel-addr) literal SCSI$SUBQ$C_MCN = 2; ! encodes media catalog number literal SCSI$SUBQ$C_ISRC = 3; ! encodes ISRC literal SCSI$SUBQ$M_MC_VAL = %X'80'; literal SCSI$SUBQ$C_MCN_LENGTH = 32; ! Length of Subq MCN data literal SCSI$SUBQ$M_TC_VAL = %X'80'; literal SCSI$SUBQ$S_SUBQ_CHANNEL = 48; macro SCSI$SUBQ$B_AUDIO_STATUS = 1,0,8,0 %; ! Audio Status macro SCSI$SUBQ$W_DATA_LENGTH = 2,0,16,0 %; ! Sub-channel Data Length macro SCSI$SUBQ$B_FORMAT_CODE = 4,0,8,0 %; ! Sub-channel data format code macro SCSI$SUBQ$R_FIELD0 = 5,0,8,0 %; literal SCSI$SUBQ$S_FIELD0 = 1; macro SCSI$SUBQ$V_CONTROL = 5,0,4,0 %; literal SCSI$SUBQ$S_CONTROL = 4; ! Control macro SCSI$SUBQ$V_ADR = 5,4,4,0 %; literal SCSI$SUBQ$S_ADR = 4; ! Audio Data Recorded Format macro SCSI$SUBQ$B_TRACK = 6,0,8,0 %; ! Current Track number macro SCSI$SUBQ$B_INDEX = 7,0,8,0 %; ! Current Index number macro SCSI$SUBQ$L_ABS_ADDRESS = 8,0,32,0 %; ! Absolute CD-ROM Address macro SCSI$SUBQ$L_REL_ADDRESS = 12,0,32,0 %; ! Track Relative CD-ROM Address macro SCSI$SUBQ$R_FIELD1 = 16,0,8,0 %; literal SCSI$SUBQ$S_FIELD1 = 1; macro SCSI$SUBQ$V_MC_VAL = 16,7,1,0 %; ! Media Catalog Valid bit macro SCSI$SUBQ$B_MCN = 17,0,0,0 %; literal SCSI$SUBQ$S_MCN = 15; ! Media Catalog Number (UPC/Bar Code) macro SCSI$SUBQ$R_FIELD2 = 32,0,8,0 %; literal SCSI$SUBQ$S_FIELD2 = 1; macro SCSI$SUBQ$V_TC_VAL = 32,7,1,0 %; ! Track ISRC Valid macro SCSI$SUBQ$B_IRRC = 33,0,0,0 %; literal SCSI$SUBQ$S_IRRC = 15; ! Track International-Standard-Recording-Code ! ! SCSIPATH structure used in sending IOGEN$_DEVPATH information to ! SYS$LOAD_DRIVER. Note that TARGET_ID and LUN fields may be assigned a ! -1 value so they cannot be unsigned. These two fields should also remain ! quadword aligned in this structure. ! literal SCSIPATH$K_VMS = 1; ! VMS path identifiers (e.g. FC-LA) literal SCSIPATH$K_CONSOLE = 2; ! Console path identifiers (e.g. AL-PA) literal SCSIPATH$K_QIOSERVER = 3; ! QIOServer path identifier literal SCSIPATH$C_LENGTH = 24; ! Length of the SCSIPATH structure literal SCSIPATH$K_LENGTH = 24; ! Length of the SCSIPATH structure literal SCSIPATH$S_SCSIPATH = 24; macro SCSIPATH$B_TYPE = 0,0,8,0 %; ! SCSIPATH type macro SCSIPATH$B_RESERVED1 = 1,0,24,0 %; literal SCSIPATH$S_RESERVED1 = 3; ! reserved macro SCSIPATH$PS_PORT_UCB = 4,0,32,1 %; ! Pointer to port's UCB address macro SCSIPATH$Q_TARGET_ID = 8,0,0,1 %; literal SCSIPATH$S_TARGET_ID = 8; ! Target ID macro SCSIPATH$Q_LUN = 16,0,0,1 %; literal SCSIPATH$S_LUN = 8; ! Logical Unit Number ! ! SCSI-3 Report Changeable Device Identifier command. ! literal DEVID_CMD$K_WR_DEVID_OPCODE = 235; ! Write Changeable Device ID literal DEVID_CMD$K_RD_DEVID_OPCODE = 236; ! Read Changeable Device ID literal DEVID_CMD$K_LENGTH = 10; literal DEVID_CMD$S_DEVID_CMD = 12; macro DEVID_CMD$B_OPCODE = 0,0,8,0 %; ! Operation code macro DEVID_CMD$B_RESERVED1 = 1,0,0,0 %; literal DEVID_CMD$S_RESERVED1 = 6; ! reserved macro DEVID_CMD$B_ALLOC_LENGTH = 7,0,16,0 %; literal DEVID_CMD$S_ALLOC_LENGTH = 2; ! Allocation length macro DEVID_CMD$B_CONTROL = 9,0,8,0 %; ! Control byte ! ! SCSI-3 Report Changeable Device Identifier data. ! literal DEVID_HDR$K_LENGTH = 4; literal DEVID$K_LENGTH = 255; literal DEVID$S_DEVID = 256; macro DEVID$B_RESERVED1 = 0,0,8,0 %; ! reserved macro DEVID$B_RESERVED2 = 1,0,8,0 %; ! reserved macro DEVID$R_VALID_FIELD = 2,0,8,0 %; literal DEVID$S_VALID_FIELD = 1; macro DEVID$V_VALID = 2,0,1,0 %; ! Identifier is valid macro DEVID$V_RESERVED3 = 2,1,7,0 %; literal DEVID$S_RESERVED3 = 7; ! reserved macro DEVID$B_IDENT_LEN = 3,0,8,0 %; ! No. of bytes following this one macro DEVID$B_IDENT = 4,0,0,0 %; literal DEVID$S_IDENT = 251; ! Device identifier ! ! SCSI-3 Report_LUNs command. ! literal RPTLUN_CMD$K_RPTLUN_OPCODE = 160; literal RPTLUN_CMD$K_LENGTH = 12; literal RPTLUN_CMD$S_RPTLUN_CMD = 12; macro RPTLUN_CMD$B_OPCODE = 0,0,8,0 %; ! Operation code macro RPTLUN_CMD$B_RESERVED1 = 1,0,0,0 %; literal RPTLUN_CMD$S_RESERVED1 = 5; ! reserved macro RPTLUN_CMD$B_ALLOC_LENGTH = 6,0,32,0 %; literal RPTLUN_CMD$S_ALLOC_LENGTH = 4; ! Allocation length macro RPTLUN_CMD$B_RESERVED2 = 10,0,8,0 %; ! reserved macro RPTLUN_CMD$B_CONTROL = 11,0,8,0 %; ! Control byte ! ! The next two structures hold SCSI-3 Report_LUNs return data. There is a ! quadword header, RPTLUN_DATAHDR, followed by n quadwords, each holding a LUN. ! Each LUN resides in a quadword LUNLIST_ENTRY structure. The number of these ! entires for an instance of Report_LUNs return data is specified by ! LIST_LENGTH. ! literal LUNLIST_ENTRY$S_LUNLIST_ENTRY = 8; macro LUNLIST_ENTRY$Q_LUN = 0,0,0,0 %; literal LUNLIST_ENTRY$S_LUN = 8; ! Entry in the LUN list literal RPTLUN_HDR$K_LENGTH = 8; literal RPTLUN_DATA$S_RPTLUN_DATA = 16; macro RPTLUN_DATA$L_LIST_LENGTH = 0,0,32,0 %; ! No. of LUNs * 8 bytes/LUN macro RPTLUN_DATA$L_RESERVED1 = 4,0,32,0 %; ! reserved macro RPTLUN_DATA$R_LUN_LIST = 8,0,0,0 %; literal RPTLUN_DATA$S_LUN_LIST = 8; ! Start of the LUN list ! ! Identification Descriptor contained in Inquiry Page 83 data - Device ! Identification Page. ! literal PG83_IDENT$K_RESERVED = 0; ! 0:Reserved literal PG83_IDENT$K_BINARY = 1; ! 1:Identifier is in binary literal PG83_IDENT$K_ASCII = 2; ! 2:Identifier is in ASCII literal PG83_IDENT$K_FIBRECHANNEL = 0; ! 0:Protocol - Fibre Channel literal PG83_IDENT$K_PARALLELSCSI = 1; ! 1:Protocol - Parallel SCSI literal PG83_IDENT$K_SSA = 2; ! 2:Protocol - SSA literal PG83_IDENT$K_IEEE1394 = 3; ! 3:Protocol - Firewire literal PG83_IDENT$K_RDMA = 4; ! 4:Protocol - Remote Direct Memory Access literal PG83_IDENT$K_ISCSI = 5; ! 5:Protocol - Internet SCSI literal PG83_IDENT$K_SAS = 6; ! 6:Protocol - Serial Attached SCSI literal PG83_IDENT$K_ADT = 7; ! 7:Protocol - Automation/Drive Interface literal PG83_IDENT$K_ATAPI = 8; ! 8:Protocol - ATA Packet Interface literal PG83_IDENT$K_VENDOR_SPEC = 0; ! 0:Vendor-specific literal PG83_IDENT$K_VENDOR_ID = 1; ! 1:Based on an 8-byte Vendor ID literal PG83_IDENT$K_IEEE_EUI64 = 2; ! 2:IEEE Extended Unique ID literal PG83_IDENT$K_FCPH_NAME_ID = 3; ! 3:FC-PH Name ID literal PG83_IDENT$K_USER_SUPPLIED = 4; ! 4:User-supplied Device ID (UDID) - Relative Target Port literal PG83_IDENT$K_TP_GROUP = 5; ! 5:Target Port Group literal PG83_IDENT$K_LU_GROUP = 6; ! 6:Logical Unit Group literal PG83_IDENT$K_MD5_STRING = 7; ! 7:MD5 Logical Unit Identifier literal PG83_IDENT$K_SCSI_NAME = 8; ! 8:SCSI Name String literal PG83_IDENT$K_DEVICE_ASSOC = 0; ! 0:Identifier assoc. with device literal PG83_IDENT$K_PORT_ASSOC = 1; ! 1:Identifier assoc. with port literal PG83_IDENT$K_LUN_ASSOC = 2; ! 2:Identifier assoc. contains addressed Logical unit literal IDENT_HDR$K_LENGTH = 4; literal FCPH$C_STD_ID = 1; ! Standard IEEE format literal FCPH$C_EXT_ID = 2; ! IEEE Extended format literal FCPH$C_REG_ID = 5; ! IEEE Registered Name format literal FCPH$C_REGEXT_ID = 6; ! IEEE Registered Extended format literal PG83_IDENT$S_PG83_IDENT = 5; macro PG83_IDENT$R_CODESET_FIELD = 0,0,8,0 %; literal PG83_IDENT$S_CODESET_FIELD = 1; macro PG83_IDENT$V_CODESET = 0,0,4,0 %; literal PG83_IDENT$S_CODESET = 4; ! Identifier is in ASCII vs. binary macro PG83_IDENT$V_PROTOCOL_ID = 0,4,4,0 %; literal PG83_IDENT$S_PROTOCOL_ID = 4; ! Protocol Identifier macro PG83_IDENT$R_IDTYPE_FIELD = 1,0,8,0 %; literal PG83_IDENT$S_IDTYPE_FIELD = 1; macro PG83_IDENT$V_ID_TYPE = 1,0,4,0 %; literal PG83_IDENT$S_ID_TYPE = 4; ! Identifier format macro PG83_IDENT$V_ASSOC = 1,4,2,0 %; literal PG83_IDENT$S_ASSOC = 2; ! Entity with which IDENTIFIER is associated macro PG83_IDENT$V_RESERVED2 = 1,6,1,0 %; ! reserved macro PG83_IDENT$V_PIV = 1,7,1,0 %; ! Protocol Identifier Value macro PG83_IDENT$B_RESERVED3 = 2,0,8,0 %; ! reserved macro PG83_IDENT$B_IDENT_LEN = 3,0,8,0 %; ! No. of bytes following this one macro PG83_IDENT$B_IDENT = 4,0,8,0 %; ! Device identifier (255 - 8 bytes of header) macro PG83_IDENT$V_UNUSED = 4,0,4,0 %; literal PG83_IDENT$S_UNUSED = 4; ! Meaning depends on what type of FC-PH identifier this is macro PG83_IDENT$V_NAA = 4,4,4,0 %; literal PG83_IDENT$S_NAA = 4; ! FC-PH Name Address Authority ! ! Page 83 Inquiry data - Device Identification Page. Contains Identification ! Descriptor list starting at offset 'IDENT_LIST'. ! literal PAGE83_HDR$K_LENGTH = 4; literal PAGE83$K_LENGTH = 255; literal PAGE83$S_PAGE83 = 256; macro PAGE83$R_PERIPHERAL = 0,0,8,0 %; literal PAGE83$S_PERIPHERAL = 1; macro PAGE83$V_DEVICE_TYPE = 0,0,5,0 %; literal PAGE83$S_DEVICE_TYPE = 5; ! Peripheral device type macro PAGE83$V_QUALIFIER = 0,5,3,0 %; literal PAGE83$S_QUALIFIER = 3; ! Peripheral qualifer macro PAGE83$B_PAGE_CODE = 1,0,8,0 %; ! Identifies page as Page 83 macro PAGE83$B_RESERVED1 = 2,0,8,0 %; ! reserved macro PAGE83$B_PAGE_LEN = 3,0,8,0 %; ! No. of bytes following this one macro PAGE83$B_IDENT_LIST = 4,0,0,0 %; literal PAGE83$S_IDENT_LIST = 251; ! Start of the Ident list. ! ! Page 00 Inquiry data - Supported VPD Page ! literal PAGE00_HDR$K_LENGTH = 4; literal PAGE00$K_LENGTH = 80; literal PAGE00$S_PAGE00 = 80; macro PAGE00$R_PERIPHERAL = 0,0,8,0 %; literal PAGE00$S_PERIPHERAL = 1; macro PAGE00$V_DEVICE_TYPE = 0,0,5,0 %; literal PAGE00$S_DEVICE_TYPE = 5; ! Peripheral device type macro PAGE00$V_QUALIFIER = 0,5,3,0 %; literal PAGE00$S_QUALIFIER = 3; ! Peripheral qualifer macro PAGE00$B_PAGE_CODE = 1,0,8,0 %; ! Identifies page as Page 0 macro PAGE00$B_RESERVED1 = 2,0,8,0 %; ! reserved macro PAGE00$B_PAGE_LEN = 3,0,8,0 %; ! No. of bytes in page list macro PAGE00$B_SUPPORTED_PAGE = 4,0,0,0 %; literal PAGE00$S_SUPPORTED_PAGE = 76; ! List of up to 76 pages ! ! Page 80 Inquiry data - Unit Serial Number Page. ! literal PAGE80_HDR$K_LENGTH = 4; literal PAGE80$K_LENGTH = 255; literal PAGE80$S_PAGE80 = 256; macro PAGE80$R_PERIPHERAL = 0,0,8,0 %; literal PAGE80$S_PERIPHERAL = 1; macro PAGE80$V_DEVICE_TYPE = 0,0,5,0 %; literal PAGE80$S_DEVICE_TYPE = 5; ! Peripheral device type macro PAGE80$V_QUALIFIER = 0,5,3,0 %; literal PAGE80$S_QUALIFIER = 3; ! Peripheral qualifer macro PAGE80$B_PAGE_CODE = 1,0,8,0 %; ! Identifies page as Page 80 macro PAGE80$B_RESERVED1 = 2,0,8,0 %; ! reserved macro PAGE80$B_PAGE_LEN = 3,0,8,0 %; ! No. of bytes in serial number macro PAGE80$B_SERIAL_NO = 4,0,0,0 %; literal PAGE80$S_SERIAL_NO = 251; ! Product serial number (255 - 4 bytes of header) ! ! SCSI Poll Thread Block used by IOGEN$SCSI_CONFIG ! literal SPTB$K_LENGTH = 299; literal SPTB$S_SPTBDEF = 299; macro SPTB$L_SIZE = 0,0,32,0 %; ! actual size allocated macro SPTB$L_LKID = 4,0,32,0 %; ! thread's SCSIPOLL lock id macro SPTB$L_CHANNEL = 8,0,32,0 %; ! thread's channel to the SCSI port macro SPTB$L_RETRIES = 12,0,32,1 %; ! number of retries left on this port macro SPTB$Q_IOSB = 16,0,0,1 %; literal SPTB$S_IOSB = 8; ! IOSB for polling operation macro SPTB$W_STATUS = 16,0,16,0 %; ! completion status macro SPTB$W_RETLEN = 18,0,16,0 %; ! bytes read from port macro SPTB$L_SCSI_ID = 24,0,32,0 %; ! current SCSI ID to poll in thread macro SPTB$L_LUN = 28,0,32,0 %; ! current LUN to poll in thread macro SPTB$PS_BUSARRAY = 32,0,32,1 %; ! address of CRB's busarray entry list macro SPTB$L_HANDLE = 36,0,32,0 %; ! autoconfiguration handle macro SPTB$L_ALLOCLS = 40,0,32,0 %; ! port allocation class macro SPTB$T_INQUIRYBUF = 44,0,0,0 %; literal SPTB$S_INQUIRYBUF = 255; ! buffer for SCSI INQUIRY command ! ! SCSI-3 REPORT DENSITY command. ! literal RPTDENS_CMD$K_RPTDENS_OPCODE = 68; literal RPTDENS_CMD$K_LENGTH = 10; literal RPTDENS_CMD$S_RPTDENS_CMD = 12; macro RPTDENS_CMD$B_OPCODE = 0,0,8,0 %; ! Operation code macro RPTDENS_CMD$B_RESERVED1 = 1,0,0,0 %; literal RPTDENS_CMD$S_RESERVED1 = 6; ! reserved macro RPTDENS_CMD$B_ALLOC_LENGTH = 7,0,16,0 %; literal RPTDENS_CMD$S_ALLOC_LENGTH = 2; ! Allocation length macro RPTDENS_CMD$B_CONTROL = 9,0,8,0 %; ! Control byte ! ! The next two structures describe SCSI-3 tapes REPORT DENSITY return data. ! Each instance of the REPORT DENSITY command returns one RPTDENS_DATA ! structure. RPTDENS_DATA contains a quadword header, followed by ! n 52-byte entries, each holding a density support data block descriptor ! (one for each different density supported by the tape drive). ! The actual number of descriptors is specified by LIST_LENGTH_MSB/LSB. ! literal DENS_DESC$M_RESERVED1 = %X'1'; literal DENS_DESC$M_DEFLT = %X'20'; literal DENS_DESC$M_DUP = %X'40'; literal DENS_DESC$M_WRTOK = %X'80'; literal DENS_DESC$K_LENGTH = 52; ! Length per descriptor literal DENS_DESC$S_DENS_DESCRIPTOR = 52; macro DENS_DESC$B_PRIMARY_DENS_CODE = 0,0,8,0 %; macro DENS_DESC$B_SECONDARY_DENS_CODE = 1,0,8,0 %; macro DENS_DESC$R_FLAGS = 2,0,8,0 %; literal DENS_DESC$S_FLAGS = 1; macro DENS_DESC$V_RESERVED1 = 2,0,1,0 %; literal DENS_DESC$S_RESERVED1 = 5; macro DENS_DESC$V_DEFLT = 2,5,1,0 %; macro DENS_DESC$V_DUP = 2,6,1,0 %; macro DENS_DESC$V_WRTOK = 2,7,1,0 %; macro DENS_DESC$B_RESERVED2 = 3,0,8,0 %; macro DENS_DESC$B_RESERVED3 = 4,0,8,0 %; macro DENS_DESC$B_BITS_PER_MM = 5,0,24,0 %; literal DENS_DESC$S_BITS_PER_MM = 3; macro DENS_DESC$B_MEDIA_WIDTH = 8,0,16,0 %; literal DENS_DESC$S_MEDIA_WIDTH = 2; macro DENS_DESC$B_TRACKS = 10,0,16,0 %; literal DENS_DESC$S_TRACKS = 2; macro DENS_DESC$B_CAPACITY = 12,0,32,0 %; literal DENS_DESC$S_CAPACITY = 4; macro DENS_DESC$B_ASSIGNING_ORG = 16,0,0,0 %; literal DENS_DESC$S_ASSIGNING_ORG = 8; macro DENS_DESC$B_DENSITY_NAME = 24,0,0,0 %; literal DENS_DESC$S_DENSITY_NAME = 8; macro DENS_DESC$B_DESCRIPTION = 32,0,0,0 %; literal DENS_DESC$S_DESCRIPTION = 20; literal RPTDENS_HDR$K_LENGTH = 4; literal RPTDENS$S_RPTDENS_DATA = 56; macro RPTDENS$B_LIST_LENGTH_MSB = 0,0,8,0 %; ! 2 + (# of desc * 52 bytes/desc) macro RPTDENS$B_LIST_LENGTH_LSB = 1,0,8,0 %; ! 2 + (# of desc * 52 bytes/desc) macro RPTDENS$B_RESERVED1 = 2,0,16,0 %; literal RPTDENS$S_RESERVED1 = 2; ! Reserved macro RPTDENS$R_FIRST_DESC = 4,0,0,0 %; literal RPTDENS$S_FIRST_DESC = 52; ! Start of the descriptor list ! ! Page x0F -- Data Compression Page. ! literal PAGE_0F$K_PAGE_CODE = 15; literal PAGE_0F$K_PAGE_LENGTH = 14; literal PAGE_0F$M_DCC = %X'40'; literal PAGE_0F$M_DCE = %X'80'; literal PAGE_0F$M_RED = %X'60'; literal PAGE_0F$M_DDE = %X'80'; literal PAGE_0F$K_NOCOMP = 0; literal PAGE_0F$K_DEFAULT = 1; literal PAGE_0F$K_IBM_ALDC_512 = 3; literal PAGE_0F$K_IBM_ALDC_1024 = 4; literal PAGE_0F$K_IBM_ALDC_2048 = 5; literal PAGE_0F$K_IBM_IDRC = 16; literal PAGE_0F$K_DCLZ = 32; literal PAGE_0F$S_DATCOMP_PG = 16; macro PAGE_0F$R_PAGECODE_FIELD = 0,0,8,0 %; literal PAGE_0F$S_PAGECODE_FIELD = 1; ! Page code field macro PAGE_0F$V_PAGECODE = 0,0,6,0 %; literal PAGE_0F$S_PAGECODE = 6; macro PAGE_0F$V_RSVD1 = 0,6,1,0 %; ! Reserved macro PAGE_0F$V_PS = 0,7,1,0 %; ! Parameters savable (Mode sense only) macro PAGE_0F$B_PAGE_LEN = 1,0,8,0 %; ! No. of bytes following this one macro PAGE_0F$R_FLAGS = 2,0,8,0 %; literal PAGE_0F$S_FLAGS = 1; macro PAGE_0F$V_RSVD2 = 2,0,6,0 %; literal PAGE_0F$S_RSVD2 = 6; ! Reserved macro PAGE_0F$V_DCC = 2,6,1,0 %; ! Data compression capable macro PAGE_0F$V_DCE = 2,7,1,0 %; ! Data compression enable macro PAGE_0F$R_FLAGS2 = 3,0,8,0 %; literal PAGE_0F$S_FLAGS2 = 1; macro PAGE_0F$V_RSVD3 = 3,0,5,0 %; literal PAGE_0F$S_RSVD3 = 5; ! Reserved macro PAGE_0F$V_RED = 3,5,2,0 %; literal PAGE_0F$S_RED = 2; ! Report exception on decompression macro PAGE_0F$V_DDE = 3,7,1,0 %; ! Data decompression enable macro PAGE_0F$L_COMP_ALGORITHM = 4,0,32,0 %; macro PAGE_0F$B_COMP_BYTES = 4,0,32,0 %; literal PAGE_0F$S_COMP_BYTES = 4; macro PAGE_0F$L_DECOMP_ALGORITHM = 8,0,32,0 %; macro PAGE_0F$B_DECOMP_BYTES = 8,0,32,0 %; literal PAGE_0F$S_DECOMP_BYTES = 4; macro PAGE_0F$B_RSVD4 = 12,0,32,0 %; literal PAGE_0F$S_RSVD4 = 4; ! ! Reading wwiddef.sdi is necessary because the DEV_WWID_DUPLE ! structure contains an embedded WWID type. ! ! It is assumed that wwiddef.sdi has already been created by the build. ! ! ! DEV_WWID_DUPLE used in device naming of (initially) Fibre Channel tapes. ! literal DEV_WWID_DUPLE$S_DEV_WWID_DUPLE = 312; macro DEV_WWID_DUPLE$PS_FLINK = 0,0,32,1 %; ! Forward link macro DEV_WWID_DUPLE$PS_BLINK = 4,0,32,1 %; ! Backward link macro DEV_WWID_DUPLE$W_SIZE = 8,0,16,0 %; ! Size macro DEV_WWID_DUPLE$B_TYPE = 10,0,8,0 %; ! Type macro DEV_WWID_DUPLE$B_SUBTYPE = 11,0,8,0 %; ! Subtype macro DEV_WWID_DUPLE$L_FLAGS = 12,0,32,0 %; ! Flags (future use) macro DEV_WWID_DUPLE$T_DEVICE = 16,0,0,0 %; literal DEV_WWID_DUPLE$S_DEVICE = 16; ! Device name macro DEV_WWID_DUPLE$R_WWID = 32,0,0,0 %; literal DEV_WWID_DUPLE$S_WWID = 280; ! WWID literal DEV_WWID_DUPLE$K_LENGTH = 312; literal DEV_WWID_DUPLE$C_LENGTH = 312; ! ! PERSISTENT RESERVE OUT command. ! literal SCSI$K_PER_RES_SUPPORT = 1; literal PROUT_CMD$K_PROUT_OPCODE = 95; literal PROUT_CMD$M_SERVICE_ACTION = %X'1F00'; literal PROUT_CMD$C_REGISTER = 0; ! 00: Register literal PROUT_CMD$C_RESERVE = 1; ! 01: Reserve literal PROUT_CMD$C_RELEASE = 2; ! 02: Release literal PROUT_CMD$C_CLEAR = 3; ! 03: Clear literal PROUT_CMD$C_PREEMPT = 4; ! 04: Preempt literal PROUT_CMD$C_PREEMPT_ABORT = 5; ! 05: Preempt & Abort literal PROUT_CMD$C_REGISTER_IGNORE = 6; ! 06: Register and Ignore Existing Key literal PROUT_CMD$M_RESERVED1 = %X'E000'; literal PROUT_CMD$M_TYPE = %X'F0000'; literal PROUT_CMD$C_OBSELETE1 = 0; ! 00: Obselete literal PROUT_CMD$C_WRITE_EX = 1; ! 01: Write Exclusive literal PROUT_CMD$C_OBSELETE2 = 2; ! 02: Obselete literal PROUT_CMD$C_EXCLUSIVE = 3; ! 03: Exclusive Access literal PROUT_CMD$C_OBSELETE3 = 4; ! 04: Obselete literal PROUT_CMD$C_WRITE_EX_RO = 5; ! 05: Write Exclusive Registrants Only literal PROUT_CMD$C_EXCLUSIVE_RO = 6; ! 06: Exclusive Registrants Only literal PROUT_CMD$M_SCOPE = %X'F00000'; literal PROUT_CMD$C_LOGICAL_UNIT = 0; ! 00: Logical Unit literal PROUT_CMD$C_OBSELETE4 = 1; ! 01: Obselete literal PROUT_CMD$C_ELEMENT = 2; ! 02: Element literal PROUT_CMD$K_PROUT_PLL = 24; ! Fixed length of x18 literal PROUT_CMD$K_LENGTH = 10; literal PROUT_CMD$S_PROUT_CMD = 10; macro PROUT_CMD$B_OPCODE = 0,0,8,0 %; ! Operation code macro PROUT_CMD$V_SERVICE_ACTION = 0,8,5,0 %; literal PROUT_CMD$S_SERVICE_ACTION = 5; ! Service Action field macro PROUT_CMD$V_RESERVED1 = 0,13,3,0 %; literal PROUT_CMD$S_RESERVED1 = 3; ! Reserved bits macro PROUT_CMD$V_TYPE = 0,16,4,0 %; literal PROUT_CMD$S_TYPE = 4; ! Reservation Type field macro PROUT_CMD$V_SCOPE = 0,20,4,0 %; literal PROUT_CMD$S_SCOPE = 4; ! Scope field macro PROUT_CMD$L_RESERVED2 = 3,0,32,0 %; ! Reserved macro PROUT_CMD$B_PARAM_LIST_LEN_MSB = 7,0,8,0 %; ! Parameter List Length MSB macro PROUT_CMD$B_PARAM_LIST_LEN_LSB = 8,0,8,0 %; ! Parameter List Length LSB macro PROUT_CMD$B_CONTROL = 9,0,8,0 %; ! Control byte ! ! PERSISTENT RESERVE OUT parameter list. ! literal PROUT_PL$M_APTPL = %X'0'; literal PROUT_PL$M_RESERVED = %X'0'; literal PROUT_PL$K_LENGTH = 24; literal PROUT_PL$S_PROUT_PL = 24; macro PROUT_PL$Q_RESERVATION_KEY = 0,0,0,0 %; literal PROUT_PL$S_RESERVATION_KEY = 8; ! Reservation Key macro PROUT_PL$Q_SA_RESERVATION_KEY = 8,0,0,0 %; literal PROUT_PL$S_SA_RESERVATION_KEY = 8; ! Service action key macro PROUT_PL$L_SCOPE_ADDRESS = 16,0,32,0 %; ! Scope address macro PROUT_PL$V_APTPL = 20,0,1,0 %; ! APTPL bit macro PROUT_PL$V_RESERVED = 20,1,15,0 %; literal PROUT_PL$S_RESERVED = 15; ! Reserved bits macro PROUT_PL$W_OBSELETE = 22,0,16,0 %; ! Obselete ! ! PERSISTENT RESERVE IN command. ! literal PRIN_CMD$K_PRIN_OPCODE = 94; literal PRIN_CMD$M_SERVICE_ACTION = %X'1F00'; literal PRIN_CMD$C_READ_KEYS = 0; ! 00: Read Keys literal PRIN_CMD$C_READ_RESERVATION = 1; ! 01: Read Reservation literal PRIN_CMD$M_RESERVED1 = %X'E000'; literal PRIN_CMD$K_LENGTH = 10; literal PRIN_CMD$S_PRIN_CMD = 10; macro PRIN_CMD$B_OPCODE = 0,0,8,0 %; ! Operation code macro PRIN_CMD$V_SERVICE_ACTION = 0,8,5,0 %; literal PRIN_CMD$S_SERVICE_ACTION = 5; ! Service Action field macro PRIN_CMD$V_RESERVED1 = 0,13,3,0 %; literal PRIN_CMD$S_RESERVED1 = 3; ! Reserved bits macro PRIN_CMD$L_RESERVED2 = 2,0,32,0 %; ! Reserved macro PRIN_CMD$B_RESERVED3 = 6,0,8,0 %; ! Reserved macro PRIN_CMD$W_ALLOCATION_LEN = 7,0,16,0 %; ! Allocation Length macro PRIN_CMD$B_CONTROL = 9,0,8,0 %; ! Control ! ! PERSISTENT RESERVE IN keys parameter list. ! literal PRIN_KEYS$K_LENGTH = 16; literal PRIN_KEYS$S_PRIN_KEYS = 16; macro PRIN_KEYS$L_GENERATION = 0,0,32,0 %; ! Generation # macro PRIN_KEYS$L_ADDITIONAL_LEN = 4,0,32,0 %; ! Additional Length macro PRIN_KEYS$Q_KEY = 8,0,0,0 %; literal PRIN_KEYS$S_KEY = 8; ! First Key ! ! PERSISTENT RESERVE IN reservations parameter list. ! literal PRIN_RES$M_TYPE = %X'0'; literal PRIN_RES$C_OBSELETE1 = 0; ! 00: Obselete literal PRIN_RES$C_WRITE_EX = 1; ! 01: Write Exclusive literal PRIN_RES$C_OBSELETE2 = 2; ! 02: Obselete literal PRIN_RES$C_EXCLUSIVE = 3; ! 03: Exclusive Access literal PRIN_RES$C_OBSELETE3 = 4; ! 04: Obselete literal PRIN_RES$C_WRITE_EX_RO = 5; ! 05: Write Exclusive Registrants Only literal PRIN_RES$C_EXCLUSIVE_RO = 6; ! 06: Exclusive Registrants Only literal PRIN_RES$M_SCOPE = %X'0'; literal PRIN_RES$C_LOGICAL_UNIT = 0; ! 00: Logical Unit literal PRIN_RES$C_OBSELETE4 = 1; ! 01: Obselete literal PRIN_RES$C_ELEMENT = 2; ! 02: Element literal PRIN_RES$K_LENGTH = 24; literal PRIN_RES$S_PRIN_RES = 24; macro PRIN_RES$L_GENERATION = 0,0,32,0 %; ! Generation # macro PRIN_RES$L_ADDITIONAL_LEN = 4,0,32,0 %; ! Additional Length macro PRIN_RES$Q_KEY = 8,0,0,0 %; literal PRIN_RES$S_KEY = 8; ! First Key macro PRIN_RES$L_SCOPE_ADDRESS = 16,0,32,0 %; ! Scope address macro PRIN_RES$B_RESERVED1 = 20,0,8,0 %; ! Reserved byte macro PRIN_RES$V_TYPE = 20,8,4,0 %; literal PRIN_RES$S_TYPE = 4; ! Reservation Type field macro PRIN_RES$V_SCOPE = 20,12,4,0 %; literal PRIN_RES$S_SCOPE = 4; ! Scope field macro PRIN_RES$W_OBSELETE = 22,0,16,0 %; ! Obselete word ! ! 10-byte Read & Write CDBs have same format, differ only in opcode ! literal SCSI$K_READ_10_OPCODE = 40; literal SCSI$K_WRITE_10_OPCODE = 42; literal RW_10_CMD$M_RELADR = %X'1'; literal RW_10_CMD$M_FUA = %X'8'; literal RW_10_CMD$M_DPO = %X'10'; literal RW_10_CMD$M_LUN = %X'E0'; literal RW_10_CMD$K_LENGTH = 10; literal RW_10_CMD$S_RW_10_CMD = 12; macro RW_10_CMD$B_OPCODE = 0,0,8,0 %; ! Operation code macro RW_10_CMD$B_FLAGS = 1,0,8,0 %; macro RW_10_CMD$V_RELADR = 1,0,1,0 %; ! Relative addressing macro RW_10_CMD$V_FUA = 1,3,1,0 %; ! Force Unit Access macro RW_10_CMD$V_DPO = 1,4,1,0 %; ! Disable Page Out macro RW_10_CMD$V_LUN = 1,5,3,0 %; literal RW_10_CMD$S_LUN = 3; ! Logical Unit Number macro RW_10_CMD$L_LBA = 2,0,32,0 %; ! Logical Block Address macro RW_10_CMD$B_RESERVED2 = 6,0,8,0 %; ! Reserved byte MBZ macro RW_10_CMD$W_BLKCNT = 7,0,16,0 %; ! Block count macro RW_10_CMD$B_CONTROL = 9,0,8,0 %; ! Control byte ! ! MAINTENANCE IN/OUT command. ! literal MAINT_CMD$K_IN_OPCODE = 163; literal MAINT_CMD$K_OUT_OPCODE = 164; literal MAINT_CMD$M_SERVICE_ACTION = %X'1F00'; literal MAINT_CMD$C_RPT_P_EXTENT = 0; ! 00: Report assigned/unassigned P_EXTENT literal MAINT_CMD$C_RPT_CMPNT = 1; ! 01: Report Component Device literal MAINT_CMD$C_RPT_CMPNT_ATT = 2; ! 02: Report Component Device attachments literal MAINT_CMD$C_RPT_PRPHRL = 3; ! 03: Report Peripheral Device literal MAINT_CMD$C_RPT_PRPHRL_ASS = 4; ! 04: Report Peripheral Device Associations literal MAINT_CMD$C_RPT_PERCMP_ID = 5; ! 05: Report Peripheral Device / Component Identifier literal MAINT_CMD$C_RPT_STATES = 6; ! 06: Report States literal MAINT_CMD$C_RPT_DEV_ID = 7; ! 07: Report Device Identification literal MAINT_CMD$C_RPT_UNCFG_CAP = 8; ! 08: Report Unconfigured Capacity literal MAINT_CMD$C_RPT_SUPPORT_CFG = 9; ! 09: Report Supported Configuration Method literal MAINT_CMD$C_RPT_TGT_PORT_GRPS = 10; ! 0A: Report Target Port Groups ! Service Actions for MAINTENANCE OUT literal MAINT_CMD$C_ADD_PERCMP = 0; ! 00: Add Peripheral / Component Device literal MAINT_CMD$C_ATT_CMPNT = 1; ! 01: Attach to Component Device literal MAINT_CMD$C_EXG_P_EXTENT = 2; ! 02: Exchange P_EXTENT literal MAINT_CMD$C_EXG_PERCMP = 3; ! 03: Exchange Peripheral / Component Device literal MAINT_CMD$C_INSTRT_CMPNT = 4; ! 04: Instruct Component Device literal MAINT_CMD$C_REM_PERCMP = 5; ! 05: Remove Peripheral Device / Component Device literal MAINT_CMD$C_SET_PERCMP_ID = 6; ! 06: Set Peripheral Component Identifier literal MAINT_CMD$C_BRK_PERCMP = 7; ! 07: Break Peripheral Component Device literal MAINT_CMD$C_RESERVE8 = 8; ! 08: Restricted literal MAINT_CMD$C_RESERVE9 = 9; ! 09: Restricted literal MAINT_CMD$C_SET_TGT_PORT_GRPS = 10; ! 0A: Set Target Port Groups literal MAINT_CMD$M_RESERVED1 = %X'E000'; literal MAINT_CMD$M_LUN_TYPE = %X'F000000'; literal MAINT_CMD$M_RESERVED2 = %X'F0000000'; literal MAINT_CMD$M_SELECT_RPT = %X'3'; literal MAINT_CMD$SR$C_RPT_ALL = 0; ! 00: Report All Peripheral Devices literal MAINT_CMD$SR$C_RPT_LUN = 1; ! 01: Report only specified literal MAINT_CMD$SR$C_RPT_ALL_UNAVAIL = 2; ! 02: Report All Unavailable Devices literal MAINT_CMD$M_ASSIGN = %X'4'; literal MAINT_CMD$M_RPTMBUS = %X'8'; literal MAINT_CMD$M_RPT_STATES = %X'30'; literal MAINT_CMD$RS$C_RPT_ALL = 0; ! 00: Report All states for all LUNS literal MAINT_CMD$RS$C_RPT_LUN_TYPE = 1; ! 01: Report All states for specified LUN TYPE literal MAINT_CMD$RS$C_RPT_LUN = 2; ! 02: Report All stated for specified LUN literal MAINT_CMD$M_SETLUN = %X'40'; literal MAINT_CMD$M_RESERVED4 = %X'80'; literal MAINT_CMD$M_RPTSEL = %X'1'; literal MAINT_CMD$M_PORC = %X'2'; literal MAINT_CMD$M_RESERVED5 = %X'FC'; literal MAINT_CMD$M_IMMED = %X'1'; literal MAINT_CMD$M_RESERVED6 = %X'FE'; literal MAINT_CMD$K_LENGTH = 12; literal MAINT_CMD$S_MAINT_CMD = 12; macro MAINT_CMD$B_OPCODE = 0,0,8,0 %; ! Operation code macro MAINT_CMD$V_SERVICE_ACTION = 0,8,5,0 %; literal MAINT_CMD$S_SERVICE_ACTION = 5; ! Service Action field ! Service Actions for MAINTENANCE IN macro MAINT_CMD$R_B2_OVERLAY = 2,0,8,0 %; macro MAINT_CMD$B_DEVICE_TYPE = 2,0,8,0 %; ! Device Type macro MAINT_CMD$B_CMPNT_INSTR = 2,0,8,0 %; ! Component Device Instruction macro MAINT_CMD$V_LUN_TYPE = 0,24,4,0 %; literal MAINT_CMD$S_LUN_TYPE = 4; ! LUN Type field macro MAINT_CMD$R_LUN_OVERLAY = 4,0,16,0 %; macro MAINT_CMD$W_LUN = 4,0,16,0 %; macro MAINT_CMD$R_LUN_BYTES = 4,0,16,0 %; literal MAINT_CMD$S_LUN_BYTES = 2; macro MAINT_CMD$B_LUN_MSB = 4,0,8,0 %; ! Logical Unit Number MSB macro MAINT_CMD$B_LUN_LSB = 5,0,8,0 %; ! Logical Unit Number LSB macro MAINT_CMD$R_PARAM_OVERLAY = 6,0,32,0 %; macro MAINT_CMD$B_ALLOC_LENGTH = 6,0,32,0 %; literal MAINT_CMD$S_ALLOC_LENGTH = 4; ! Allocation/Parameter list length macro MAINT_CMD$R_NEW_LUN_ST = 6,0,32,0 %; literal MAINT_CMD$S_NEW_LUN_ST = 4; macro MAINT_CMD$R_NEW_LUN_OVERLAY = 8,0,16,0 %; macro MAINT_CMD$W_NEW_LUN = 8,0,16,0 %; macro MAINT_CMD$R_NEW_LUN_BYTES = 8,0,16,0 %; literal MAINT_CMD$S_NEW_LUN_BYTES = 2; macro MAINT_CMD$B_NEW_LUN_MSB = 8,0,8,0 %; ! New Logical Unit Number MSB macro MAINT_CMD$B_NEW_LUN_LSB = 9,0,8,0 %; ! New Logical Unit Number LSB macro MAINT_CMD$R_CMD_FLAGS_OVERLAY = 10,0,8,0 %; macro MAINT_CMD$B_CMD_FLAGS = 10,0,8,0 %; ! Command specific flags macro MAINT_CMD$R_CMD_BITS1 = 10,0,8,0 %; macro MAINT_CMD$V_SELECT_RPT = 10,0,2,0 %; literal MAINT_CMD$S_SELECT_RPT = 2; ! Select report code macro MAINT_CMD$V_ASSIGN = 10,2,1,0 %; ! Report Assigned p_extents bit macro MAINT_CMD$V_RPTMBUS = 10,3,1,0 %; ! Report Multiple Bus bit macro MAINT_CMD$V_RPT_STATES = 10,4,2,0 %; literal MAINT_CMD$S_RPT_STATES = 2; ! Report States macro MAINT_CMD$V_SETLUN = 10,6,1,0 %; ! SETLUN bit macro MAINT_CMD$R_CMD_BITS2 = 10,0,8,0 %; macro MAINT_CMD$V_RPTSEL = 10,0,1,0 %; ! Report Select bit macro MAINT_CMD$V_PORC = 10,1,1,0 %; ! Peripheral or Component bit macro MAINT_CMD$R_CMD_BITS3 = 10,0,8,0 %; macro MAINT_CMD$V_IMMED = 10,0,1,0 %; ! Immediate bit macro MAINT_CMD$B_CONTROL = 11,0,8,0 %; ! Control byte ! p_extent descriptor literal SCSI$PXT$S_P_EXTENT = 12; macro SCSI$PXT$R_LUN_OVERLAY = 0,0,16,0 %; macro SCSI$PXT$R_LUN_BYTES = 0,0,16,0 %; literal SCSI$PXT$S_LUN_BYTES = 2; macro SCSI$PXT$B_LUN_MSB = 0,0,8,0 %; ! Logical Unit Number MSB macro SCSI$PXT$B_LUN_LSB = 1,0,8,0 %; ! Logical Unit Number LSB macro SCSI$PXT$W_LUN = 0,0,16,0 %; macro SCSI$PXT$L_START_LBA_P = 2,0,32,0 %; ! First Addressable Block of the p_extent. macro SCSI$PXT$L_NUMBER_LBA_P = 6,0,32,0 %; ! Number of blocks in the p_extent macro SCSI$PXT$W_BYTES_LBA_P = 10,0,16,0 %; ! Number of bytes in each block ! Assign / Deassign p_extent Descriptor literal SCSI$APXT$M_STATE = %X'7F'; literal SCSI$APXT$C_AVAILABLE = 0; ! 00: The accessed device / p_extent is operational literal SCSI$APXT$C_BROKEN = 1; ! 01: Is capable of being supported but has failed literal SCSI$APXT$C_NOT_AVAIL = 2; ! 02: Is capable of being supported but not connected literal SCSI$APXT$C_NOT_SUPPORT = 3; ! 03: Target can not support addressed device / p_extent literal SCSI$APXT$C_PRESENT = 4; ! 04: Device / p_extent is present, no other status available literal SCSI$APXT$C_READYING = 5; ! 05: The device / p_extent is being initialized, access is limited literal SCSI$APXT$C_REBUILD = 6; ! 06: The device / p_extent is being rebuilt literal SCSI$APXT$M_RESERVED3 = %X'80'; literal SCSI$APXT$S_ASSGN_P_EXTENT = 16; macro SCSI$APXT$R_EXTENT = 0,0,0,0 %; literal SCSI$APXT$S_EXTENT = 12; ! P_EXTENT structure macro SCSI$APXT$B_DEV_TYPE = 14,0,8,0 %; ! Peripheral Device Type macro SCSI$APXT$R_P_EXT_STATE = 15,0,8,0 %; literal SCSI$APXT$S_P_EXT_STATE = 1; macro SCSI$APXT$V_STATE = 15,0,7,0 %; literal SCSI$APXT$S_STATE = 7; ! Component and Peripheral Device Descriptors literal SCSI$DEV$C_SACL = 0; ! 00: Controller electronics that contain a SACL literal SCSI$DEV$C_NON_VOL_CACHE = 1; ! 01: Non-volatile cache literal SCSI$DEV$C_POWER = 2; ! 02: Power supply literal SCSI$DEV$C_UPS = 3; ! 03: Uninterruptable power supply literal SCSI$DEV$C_DISPLAY = 4; ! 04: Display literal SCSI$DEV$C_KEY_PAD = 5; ! 05: Key pad entry literal SCSI$DEV$C_FAN = 6; ! 06: Fan literal SCSI$DEV$M_DEV_STATE = %X'7F'; literal SCSI$SPARE$C_AVAILABLE = 0; ! 00: The addressed spare is operational literal SCSI$SPARE$C_BROKEN = 1; ! 01: The spare is supported but has failed literal SCSI$SPARE$C_NOT_AVAIL = 2; ! 02: The spare is supported but not configured literal SCSI$SPARE$C_NOT_SUPPORT = 3; ! 03: The spare is not capable of configuration literal SCSI$SPARE$C_PRESENT = 4; ! 04: The spare is present, no other status known literal SCSI$SPARE$C_SPARE_USED = 5; ! 05: The spare has been exchanged with a failed object literal SCSI$DEV$C_AVAILABLE = 0; ! 00: The addressed component device is operational literal SCSI$DEV$C_BROKEN = 1; ! 01: The device is supported but has failed literal SCSI$DEV$C_ITTU = 3; ! 03: The addressed device is the reporting component device literal SCSI$DEV$C_NOT_AVAIL = 4; ! 04: The component device is supported but not present literal SCSI$DEV$C_NOT_SUPPORT = 5; ! 05: Target can not support a component at given address literal SCSI$DEV$C_PRESENT = 6; ! 06: The component device is present, no other status known literal SCSI$DEV$C_READYING = 7; ! 07: The component device is being initialized, access is limited literal SCSI$DEV$M_REPLACE = %X'80'; literal SCSI$DEV$S_DEV_DESC = 4; macro SCSI$DEV$B_DEV_TYPE = 0,0,8,0 %; macro SCSI$DEV$R_DEV_STATUS = 1,0,8,0 %; literal SCSI$DEV$S_DEV_STATUS = 1; macro SCSI$DEV$V_DEV_STATE = 1,0,7,0 %; literal SCSI$DEV$S_DEV_STATE = 7; macro SCSI$DEV$V_REPLACE = 1,7,1,0 %; macro SCSI$DEV$R_LUN_OVERLAY = 2,0,16,0 %; macro SCSI$DEV$R_LUN_BYTES = 2,0,16,0 %; literal SCSI$DEV$S_LUN_BYTES = 2; macro SCSI$DEV$B_LUN_MSB = 2,0,8,0 %; ! Logical Unit Number MSB macro SCSI$DEV$B_LUN_LSB = 3,0,8,0 %; ! Logical Unit Number LSB macro SCSI$DEV$W_LUN = 2,0,16,0 %; literal SCSI$CMPT$M_DEV_TYPE = %X'F'; literal SCSI$CMPT$M_RESERVED2 = %X'F0'; literal SCSI$CMPT$C_PHYS_LUN = 0; ! 00: Physical Logical Unit literal SCSI$CMPT$C_VOL_SET = 1; ! 01: Volume set ! 02: Reserved ! 03: Reserved literal SCSI$CMPT$C_CMPT_LUN = 4; ! 04: Component logical unit (component device) literal SCSI$CMPT$C_REDUND_GRP = 5; ! 05: Redundancy Group literal SCSI$CMPT$C_SPARE = 6; ! 06: Spare literal SCSI$CMPT$C_LUN_Z = 7; ! 07: LUN_Z literal SCSI$CMPT$S_LUN_DESC = 4; macro SCSI$CMPT$R_DTYPE = 1,0,8,0 %; literal SCSI$CMPT$S_DTYPE = 1; macro SCSI$CMPT$V_DEV_TYPE = 1,0,4,0 %; literal SCSI$CMPT$S_DEV_TYPE = 4; macro SCSI$CMPT$R_LUN_OVERLAY = 2,0,16,0 %; macro SCSI$CMPT$R_LUN_BYTES = 2,0,16,0 %; literal SCSI$CMPT$S_LUN_BYTES = 2; macro SCSI$CMPT$B_LUN_MSB = 2,0,8,0 %; ! Logical Unit Number MSB macro SCSI$CMPT$B_LUN_LSB = 3,0,8,0 %; ! Logical Unit Number LSB macro SCSI$CMPT$W_LUN = 2,0,16,0 %; literal SCSI$LUNZ$M_READYING = %X'1'; literal SCSI$LUNZ$M_NONAFAIL = %X'2'; literal SCSI$LUNZ$M_ABNORMAL = %X'4'; literal SCSI$LUNZ$M_RESERVED1 = %X'38'; literal SCSI$LUNZ$M_VS = %X'40'; literal SCSI$LUNZ$M_RESERVED2 = %X'80'; literal SCSI$LUNZ$S_LUN_Z_STATES = 1; macro SCSI$LUNZ$V_READYING = 0,0,1,0 %; ! At least one LUN is still readying macro SCSI$LUNZ$V_NONAFAIL = 0,1,1,0 %; ! Non Addressable part has failed macro SCSI$LUNZ$V_ABNORMAL = 0,2,1,0 %; ! One or more target units is unavailable macro SCSI$LUNZ$V_VS = 0,6,1,0 %; ! Vendor Specific ! ! Report Supported Configuration Method parameter list ! literal SCSI$RSCM$C_NOSUPPORT = 0; ! 00: Target does not support literal SCSI$RSCM$C_MIN_RPT = 1; ! 01: Mandatory reporting service actions literal SCSI$RSCM$C_SUPPORT = 3; ! 03: Mandatory reporting and configuration literal SCSI$RSCM$M_SIMPLE = %X'3'; literal SCSI$RSCM$M_RESERVED1 = %X'C'; literal SCSI$RSCM$M_BASIC = %X'30'; literal SCSI$RSCM$M_RESERVED2 = %X'C0'; literal SCSI$RSCM$M_GENERAL = %X'300'; literal SCSI$RSCM$M_RESERVED3 = %X'FC00'; literal SCSI$RSCM$S_RPT_CONFIG_METHOD = 4; macro SCSI$RSCM$V_SIMPLE = 0,0,2,0 %; literal SCSI$RSCM$S_SIMPLE = 2; ! Simple Configuration Method macro SCSI$RSCM$V_BASIC = 0,4,2,0 %; literal SCSI$RSCM$S_BASIC = 2; ! Basic Configuration macro SCSI$RSCM$V_GENERAL = 0,8,2,0 %; literal SCSI$RSCM$S_GENERAL = 2; ! ! Report Unconfigured Capacity parameter list ! literal SCSI$RUC$M_MOREP = %X'1'; literal SCSI$RUC$M_MOREPS = %X'2'; literal SCSI$RUC$M_RESERVED1 = %X'FC'; literal SCSI$RUC$S_RPT_UNCFG_CAP = 12; macro SCSI$RUC$L_P_EXTENT_CAP = 0,0,32,0 %; ! Unassigned P_EXTENT Capacity macro SCSI$RUC$L_PS_EXTENT_CAP = 4,0,32,0 %; ! Unassigned PS_EXTENT Capacity macro SCSI$RUC$R_FLAGS = 8,0,8,0 %; literal SCSI$RUC$S_FLAGS = 1; macro SCSI$RUC$V_MOREP = 8,0,1,0 %; ! Can not configure all p_extents in single volume macro SCSI$RUC$V_MOREPS = 8,1,1,0 %; ! Can not configure all ps_extents in single volume macro SCSI$RUC$W_BLOCKSIZE = 10,0,16,0 %; ! Bytes per block ! ! Volume set states ! literal SCSI$VSS$C_AVAILABLE = 0; ! 00: The addressed volume set is operational literal SCSI$VSS$C_BROKEN = 1; ! 01: The addressed volume set is broken literal SCSI$VSS$C_DATA_LOST = 2; ! 02: User data has been lost in volume set literal SCSI$VSS$C_EXPOSED = 3; ! 03: User data is valid but not protected literal SCSI$VSS$C_PART_EXPOSED = 4; ! 04: One or more units have failed, data still protected literal SCSI$VSS$C_PROT_REBUILD = 5; ! 05: One or more Redundancy Units are being rebuilt, data protected literal SCSI$VSS$C_NOT_AVAIL = 6; ! 06: The volume set is capable of support but not configured literal SCSI$VSS$C_NOT_SUPPORT = 7; ! 07: The volume set is not capable of being configured literal SCSI$VSS$C_READYING = 8; ! 08: The volume set is being initialized literal SCSI$VSS$C_REBUILD = 9; ! 09: One or more Redundancy Units are being rebuilt, data not protected literal SCSI$VSS$C_RECALC = 10; ! 0A: The volume set is doing a recalculate literal SCSI$VSS$C_SPARE_USED = 11; ! 0B: The Spare is in use for the addressed Volume set literal SCSI$VSS$C_PROT_DISABLED = 12; ! 0C: Protection of User Data disabled literal SCSI$VSS$C_VERIFY = 13; ! 0D: The addressed data set is doing a VERIFY literal SCSI$VSS$C_FRACT_EXPOSED = 14; ! 0E: Part of the user data is not protected literal SCSI$VSS$C_DYN_RECONFIG = 15; ! 0F: The address volume set is being reconfigured, data protected ! ! Redundancy group states ! literal SCSI$RGS$C_AVAILABLE = 0; ! 00: The addressed redundancy group is configured literal SCSI$RGS$C_EXPOSED = 1; ! 01: User data is intact, but not protected literal SCSI$RGS$C_INV_PROT_SPACE = 2; ! 02: User data has been lost literal SCSI$RGS$C_NOT_AVAIL = 3; ! 03: Group can be supported, has not been configured literal SCSI$RGS$C_NOT_SUPPORT = 4; ! 04: Group is not capable of being configured literal SCSI$RGS$C_PART_EXPOSED = 5; ! 05: One or more units have failed, data still protected literal SCSI$RGS$C_PRESENT = 6; ! 06: The group is present, other status unknown literal SCSI$RGS$C_PROT_REBUILD = 7; ! 07: The group is being rebuilt, data protected literal SCSI$RGS$C_REBUILD = 8; ! 08: The group is being rebuilt, data is not protected literal SCSI$RGS$C_RECALC = 9; ! 09: The redundancy group is in the process of recalulate operation literal SCSI$RGS$C_PROT_DISABLED = 10; ! 0A: Protection of User Data is disabled literal SCSI$RGS$C_VERIFY = 11; ! 0B: The redundancy group is doing a verify. literal SCSI$RGS$C_DYN_RECONFIG = 12; ! 0C: The redundancy group is being reconfigured, data protected ! ! Component Device Instruction field ! literal SCSI$CDI$C_DEVICE_OFF = 0; ! 00: Turn selected component device off literal SCSI$CDI$C_DEVICE_ON = 1; ! 01: Turn selected component device on ! ! Target port descriptor format, as defined by SPC-3. ! ! Note: This structure is used to define data returned by the REPORT ! TARGET PORT GROUPS command. ! literal SCSI$TP$S_TP = 4; macro SCSI$TP$W_OBSOLETE = 0,0,16,0 %; ! Obsolete macro SCSI$TP$R_TP_OVERLAY = 2,0,16,0 %; ! Target Port Group macro SCSI$TP$R_TP_BYTES = 2,0,16,0 %; literal SCSI$TP$S_TP_BYTES = 2; macro SCSI$TP$B_REL_TP_MSB = 2,0,8,0 %; ! Relative Target Port ID MSB macro SCSI$TP$B_REL_TP_LSB = 3,0,8,0 %; ! Relative Target Port ID LSB macro SCSI$TP$W_REL_TP = 2,0,16,0 %; ! ! TARGET PORT GROUP descriptor format, as defined by SPC-3. ! ! Note: This structure is used to define data returned by the REPORT ! TARGET PORT GROUPS command. ! literal SCSI$RPT_TPG$M_ASYM_ACC_STATE = %X'F'; literal SCSI$RPT_TPG$C_AO = 0; ! 0: Active/optimized literal SCSI$RPT_TPG$C_ANO = 1; ! 1: Active/non-optimized literal SCSI$RPT_TPG$C_STANDBY = 2; ! 2: Standby literal SCSI$RPT_TPG$C_UNAVAILABLE = 3; ! 3: Unavailable literal SCSI$RPT_TPG$C_TRANSIT = 15; ! F: Transitioning between states literal SCSI$RPT_TPG$M_RSVD1 = %X'70'; literal SCSI$RPT_TPG$M_PREF = %X'80'; literal SCSI$RPT_TPG$M_AO_SUP = %X'1'; literal SCSI$RPT_TPG$M_AN_SUP = %X'2'; literal SCSI$RPT_TPG$M_S_SUP = %X'4'; literal SCSI$RPT_TPG$M_U_SUP = %X'8'; literal SCSI$RPT_TPG$M_RSVD2 = %X'70'; literal SCSI$RPT_TPG$M_T_SUP = %X'80'; literal SCSI$RPT_TPG$C_NO_STATUS = 0; ! 0: No status available literal SCSI$RPT_TPG$C_CMD = 1; ! 1: Asymm state altered via SET TPG command literal SCSI$RPT_TPG$C_IMPLICIT = 2; ! 2: Asymm state altered by implicit behavior literal SCSI$RPT_TPG$C_HDR_LENGTH = 8; ! Size of RTPG header info literal SCSI$RPT_TPG$S_RPT_TPG = 12; macro SCSI$RPT_TPG$R_FLAGS_1 = 0,0,8,0 %; literal SCSI$RPT_TPG$S_FLAGS_1 = 1; macro SCSI$RPT_TPG$V_ASYM_ACC_STATE = 0,0,4,0 %; literal SCSI$RPT_TPG$S_ASYM_ACC_STATE = 4; ! Asymmetric access state macro SCSI$RPT_TPG$V_RSVD1 = 0,4,3,0 %; literal SCSI$RPT_TPG$S_RSVD1 = 3; ! Reserved macro SCSI$RPT_TPG$V_PREF = 0,7,1,0 %; ! Preferred target port macro SCSI$RPT_TPG$R_FLAGS_2 = 1,0,8,0 %; literal SCSI$RPT_TPG$S_FLAGS_2 = 1; macro SCSI$RPT_TPG$V_AO_SUP = 1,0,1,0 %; ! Active/optimized supported macro SCSI$RPT_TPG$V_AN_SUP = 1,1,1,0 %; ! Active/non-optimized supported macro SCSI$RPT_TPG$V_S_SUP = 1,2,1,0 %; ! Standby supported macro SCSI$RPT_TPG$V_U_SUP = 1,3,1,0 %; ! Unavailable supported macro SCSI$RPT_TPG$V_RSVD2 = 1,4,3,0 %; literal SCSI$RPT_TPG$S_RSVD2 = 3; ! Reserved macro SCSI$RPT_TPG$V_T_SUP = 1,7,1,0 %; ! Transitioning supported macro SCSI$RPT_TPG$R_TPG_OVERLAY = 2,0,16,0 %; ! Target Port Group macro SCSI$RPT_TPG$R_TPG_BYTES = 2,0,16,0 %; literal SCSI$RPT_TPG$S_TPG_BYTES = 2; macro SCSI$RPT_TPG$B_TPG_MSB = 2,0,8,0 %; ! Target Port Group MSB macro SCSI$RPT_TPG$B_TPG_LSB = 3,0,8,0 %; ! Target Port Group LSB macro SCSI$RPT_TPG$W_TPG = 2,0,16,0 %; macro SCSI$RPT_TPG$B_RSVD3 = 4,0,8,0 %; ! Reserved macro SCSI$RPT_TPG$B_STATUS_CODE = 5,0,8,0 %; ! Status code macro SCSI$RPT_TPG$B_VENDOR_SPEC = 6,0,8,0 %; ! Vendor specific macro SCSI$RPT_TPG$B_TP_CNT = 7,0,8,0 %; ! Target port count macro SCSI$RPT_TPG$R_TP_LST = 8,0,32,0 %; literal SCSI$RPT_TPG$S_TP_LST = 4; ! Start of TP list (variable length) ! ! REPORT TARGET PORT GROUPS parameter data format, as defined by SPC-3. ! ! Note: This structure is used to define data returned by the REPORT ! TARGET PORT GROUPS command. ! literal SCSI$RPT_TPG_DAT$S_RPT_TPG_DAT = 16; macro SCSI$RPT_TPG_DAT$L_RETURN_LEN = 0,0,32,0 %; ! Return data length macro SCSI$RPT_TPG_DAT$R_TPG_LST = 4,0,0,0 %; literal SCSI$RPT_TPG_DAT$S_TPG_LST = 12; ! Start of TPG list (variable length) ! ! Parameter list for SET TARGET PORT GROUP descriptor, as defined by SPC-3. ! ! Note: This structure is used to define data sent by the SET ! TARGET PORT GROUPS command. ! literal SCSI$SET_TPG$M_ASYM_ACC_STATE = %X'F'; literal SCSI$SET_TPG$C_AO = 0; ! 0: Active/optimized literal SCSI$SET_TPG$C_ANO = 1; ! 1: Active/non-optimized literal SCSI$SET_TPG$C_STANDBY = 2; ! 2: Standby literal SCSI$SET_TPG$C_UNAVAILABLE = 3; ! 3: Unavailable literal SCSI$SET_TPG$C_ILLEGAL = 15; ! F: Illegal Request literal SCSI$SET_TPG$M_RSVD1 = %X'F0'; literal SCSI$SET_TPG$S_SET_TPG = 4; macro SCSI$SET_TPG$R_FLAGS = 0,0,8,0 %; literal SCSI$SET_TPG$S_FLAGS = 1; macro SCSI$SET_TPG$V_ASYM_ACC_STATE = 0,0,4,0 %; literal SCSI$SET_TPG$S_ASYM_ACC_STATE = 4; ! Asymmetric access state macro SCSI$SET_TPG$V_RSVD1 = 0,4,4,0 %; literal SCSI$SET_TPG$S_RSVD1 = 4; ! Reserved macro SCSI$SET_TPG$B_RSVD2 = 1,0,8,0 %; ! Reserved macro SCSI$SET_TPG$R_TPG_OVERLAY = 2,0,16,0 %; ! Target Port Group macro SCSI$SET_TPG$R_TPG_BYTES = 2,0,16,0 %; literal SCSI$SET_TPG$S_TPG_BYTES = 2; macro SCSI$SET_TPG$B_TPG_MSB = 2,0,8,0 %; ! Target Port Group MSB macro SCSI$SET_TPG$B_TPG_LSB = 3,0,8,0 %; ! Target Port Group LSB macro SCSI$SET_TPG$W_TPG = 2,0,16,0 %; ! ! Parameter list for SET TARGET PORT GROUPS, as defined by SPC-3. ! ! Note: This structure is used to define data sent by the SET ! TARGET PORT GROUPS command. Exactly one SET_TPG structure is ! represented in the TPG_LST since that is the most common ! usage, but additional SET_TPG's are allowed. ! literal SCSI$SET_TPG_DAT$S_SET_TPG_DAT = 8; macro SCSI$SET_TPG_DAT$L_RSVD1 = 0,0,32,0 %; ! Reserved macro SCSI$SET_TPG_DAT$R_TPG_LST = 4,0,32,0 %; literal SCSI$SET_TPG_DAT$S_TPG_LST = 4; ! Start of TPG list (varaible length) !*** MODULE $UCBDEF *** literal UCB$K_V8_POWERED = 1; ! Build for V8 feature set. literal UCB$K_50BIT_PA = 1; ! 50BIT Physical addressing with V8.2 literal UCB$M_TIM = %X'1'; literal UCB$M_INT = %X'2'; literal UCB$M_ERLOGIP = %X'4'; literal UCB$M_CANCEL = %X'8'; literal UCB$M_ONLINE = %X'10'; literal UCB$M_POWER = %X'20'; literal UCB$M_TIMOUT = %X'40'; literal UCB$M_INTTYPE = %X'80'; literal UCB$M_BSY = %X'100'; literal UCB$M_MOUNTING = %X'200'; literal UCB$M_DEADMO = %X'400'; literal UCB$M_VALID = %X'800'; literal UCB$M_UNLOAD = %X'1000'; literal UCB$M_TEMPLATE = %X'2000'; literal UCB$M_MNTVERIP = %X'4000'; literal UCB$M_WRONGVOL = %X'8000'; literal UCB$M_DELETEUCB = %X'10000'; literal UCB$M_LCL_VALID = %X'20000'; literal UCB$M_SUPMVMSG = %X'40000'; literal UCB$M_MNTVERPND = %X'80000'; literal UCB$M_DISMOUNT = %X'100000'; literal UCB$M_CLUTRAN = %X'200000'; literal UCB$M_WRTLOCKMV = %X'400000'; literal UCB$M_SVPN_END = %X'800000'; literal UCB$M_ALTBSY = %X'1000000'; literal UCB$M_SNAPSHOT = %X'2000000'; literal UCB$M_NO_ASSIGN = %X'4000000'; literal UCB$M_EXFUNC_SUPP = %X'8000000'; literal UCB$M_FAST_PATH = %X'10000000'; literal UCB$M_PATHVERIP = %X'20000000'; literal UCB$M_FP_HWINT = %X'40000000'; literal UCB$M_IOPOST_LOCAL = %X'80000000'; literal UCB$M_JOB = %X'1'; literal UCB$M_TEMPL_BSY = %X'40'; literal UCB$M_PRMMBX = %X'1'; literal UCB$M_DELMBX = %X'2'; literal UCB$M_TT_TIMO = %X'2'; literal UCB$M_TT_NOTIF = %X'4'; literal UCB$M_TT_HANGUP = %X'8'; literal UCB$M_TT_NOLOGINS = %X'8000'; literal UCB$M_NT_BFROVF = %X'4'; literal UCB$M_NT_NAME = %X'10'; literal UCB$M_NT_BREAK = %X'20'; literal UCB$M_ECC = %X'1'; literal UCB$M_DIAGBUF = %X'2'; literal UCB$M_NOCNVRT = %X'4'; literal UCB$M_DX_WRITE = %X'8'; literal UCB$M_DATACACHE = %X'10'; literal UCB$M_MSCP_MNTVERIP = %X'100'; literal UCB$M_MSCP_INITING = %X'200'; literal UCB$M_MSCP_WAITBMP = %X'400'; literal UCB$M_MSCP_FLOVR = %X'800'; literal UCB$M_MSCP_PKACK = %X'1000'; literal UCB$M_MSCP_WRTP = %X'2000'; literal UCB$M_MSCP_IGNSRV = %X'4000'; literal UCB$M_MSCP_MVRESTART = %X'8000'; literal UCB$M_MSCP_LOCAL_DRAIN_WAITBMP = %X'10000'; literal UCB$M_DU_SHMV_STRTD = %X'8'; literal UCB$M_DU_0MNOTE = %X'20'; literal UCB$M_MVFKBBSY = %X'40'; literal UCB$M_GTUNMBSY = %X'80'; literal UCB$M_TU_OVRSQCHK = %X'1'; literal UCB$M_TU_TRACEACT = %X'2'; literal UCB$M_TU_SEQNOP = %X'4'; literal UCB$M_TU_1DENS = %X'8'; literal UCB$M_TU_DENS_DETERMINED = %X'10'; literal UCB$M_TU_MEDIA_LOADED = %X'20'; literal UCB$M_SHD_WLG_INV = %X'80'; literal UCB$M_SHD_SEQCMD_HERE = %X'400'; literal UCB$M_SHD_SEQCMD_THERE = %X'800'; literal UCB$M_SHD_PASSIVE_MV = %X'1000'; literal UCB$M_SHD_NODE_FAILURE = %X'2000'; literal UCB$M_SHD_WLGSTA_CHA = %X'4000'; literal UCB$M_SHD_VCB_DEQUEUE = %X'8000'; literal UCB$M_SHD_SEQCMD_PEND = %X'10000'; literal UCB$M_SHD_ST_DRAIN_IO = %X'20000'; literal UCB$M_SHD_MBRSHP_EVENT = %X'40000'; literal UCB$M_SHD_TGR_VALIDATE = %X'80000'; literal UCB$M_PORT_ONLINE = %X'1'; literal UCB$M_FKLOCK = %X'2'; literal UCB$M_MSGFKLOCK = %X'4'; literal UCB$M_INIFKLOCK = %X'8'; literal UCB$M_BAD_REV = %X'10'; literal UCB$M_PA_ERLOGIP = %X'20'; literal UCB$M_MFQEFKLOCK = %X'40'; literal UCB$M_MFQE_LOST = %X'80'; literal UCB$M_ADMIN_ONLINE = %X'100'; literal UCB$M_ADMIN_INIT = %X'200'; literal UCB$M_ADMIN_TEAR_DOWN = %X'400'; literal UCB$M_CHAN_ONLINE = %X'10000'; literal UCB$M_CHAN_INIT = %X'20000'; literal UCB$M_CHAN_TEAR_DOWN = %X'40000'; literal UCB$M_PB_TQE_BUSY = %X'1000000'; literal UCB$M_MBR_CALLBACK = %X'2000000'; literal UCB$M_SHUTDOWN_REQ = %X'4000000'; literal UCB$M_SHUTDOWN_IP = %X'8000000'; literal UCB$M_PB_LAST_GASP_EMULATED = %X'10000000'; literal UCB$S_UCB = 472; macro UCB$R_UCB_FKB = 0,0,0,0 %; literal UCB$S_UCB_FKB = 48; macro UCB$L_FQFL = 0,0,32,1 %; ! FORK QUEUE FORWARD LINK macro UCB$L_UNIT_SEED = 0,0,32,0 %; ! Longword Unit Seed macro UCB$W_UNIT_SEED = 0,0,16,0 %; ! UNIT NUMBER SEED macro UCB$W_MB_SEED = 0,0,16,0 %; ! MB -- UNIT NUMBER SEED (no longer used) macro UCB$L_RQFL = 0,0,32,1 %; ! NET -- RCV QUEUE FORWARD LINK macro UCB$L_MB_MSGQFL = 0,0,32,1 %; ! MAILBOX MESSAGE QUEUE LISTHEAD macro UCB$L_FQBL = 4,0,32,1 %; ! FORK QUEUE BACKWARD LINK macro UCB$L_RQBL = 4,0,32,1 %; ! NET -- RCV QUEUE BACKWARD LINK macro UCB$L_MB_MSGQBL = 4,0,32,1 %; ! MAILBOX MESSAGE QUEUE LISTHEAD macro UCB$W_SIZE = 8,0,16,0 %; ! SIZE OF UCB IN BYTES macro UCB$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE FOR UCB macro UCB$B_FLCK = 11,0,8,0 %; ! Fork lock number index macro UCB$L_FPC = 12,0,32,1 %; ! FORK PC macro UCB$L_ASTQFL = 12,0,32,1 %; ! MB -- AST QUEUE LISTHEAD FORWARD LINK macro UCB$L_MB_W_AST = 12,0,32,1 %; ! MAILBOX WRITE ATTN AST LIST macro UCB$T_PARTNER = 12,0,8,0 %; ! NET -- PARTNER'S NODENAME macro UCB$Q_FR3 = 16,0,0,1 %; literal UCB$S_FR3 = 8; ! FORK R3 macro UCB$L_FR3 = 16,0,32,1 %; ! FORK R3 longword overlay macro UCB$L_ASTQBL = 16,0,32,1 %; ! MB -- AST QUEUE LISTHEAD BACKWARD LINK macro UCB$L_MB_R_AST = 16,0,32,1 %; ! MAILBOX READ ATTN AST LIST macro UCB$Q_FR4 = 24,0,0,1 %; literal UCB$S_FR4 = 8; ! FORK R4 macro UCB$W_MSGMAX = 24,0,16,0 %; ! MB -- MAXIMUM MESSAGES ALLOWED macro UCB$W_MSGCNT = 26,0,16,0 %; ! MB -- CURRENT NUMBER OF MESSAGES macro UCB$L_FIRST = 24,0,32,1 %; ! NET -- ADDR OF 1ST SEG OF CHAINED MSG macro UCB$PS_SPINLOCK = 32,0,32,1 %; ! Pointer to a spinlock. macro UCB$W_BUFQUO = 48,0,16,0 %; ! BUFFERED I/O QUOTA CHARGED FOR THIS UCB macro UCB$W_DSTADDR = 48,0,16,0 %; ! NET -- REMOTE CONNECT NO. macro UCB$W_INIQUO = 50,0,16,0 %; ! INITIAL BUFFERED I/O QUOTA FOR THIS UCB macro UCB$W_SRCADDR = 50,0,16,0 %; ! NET -- LOCAL CONNECT NO. macro UCB$L_ORB = 52,0,32,1 %; ! OBJECT'S RIGHTS BLOCK ADDRESS macro UCB$L_LOCKID = 56,0,32,0 %; ! DEVICE LOCK ID macro UCB$L_CPID = 56,0,32,0 %; ! PID CHARGED FOR BUFQUO BY UCBCREDEL macro UCB$PS_CRAM = 60,0,32,1 %; ! ADDRESS OF FIRST UNIT CRAM macro UCB$L_CRB = 64,0,32,1 %; ! ADDRESS OF PRIMARY CHANNEL REQUEST BLOCK macro UCB$L_DLCK = 68,0,32,1 %; ! ADDRESS OF DEVICE IPL SPINLOCK macro UCB$L_DDB = 72,0,32,1 %; ! BACKPOINTER TO DEVICE DATA BLOCK macro UCB$L_PID = 76,0,32,0 %; ! PROCESS ID OF OWNER PROCESS macro UCB$L_LINK = 80,0,32,1 %; ! ADDRESS OF NEXT UCB FOR RESPECTIVE DDB macro UCB$L_BLINK = 84,0,32,1 %; ! Backwards Link macro UCB$L_VCB = 88,0,32,1 %; ! ADDRESS OF VOLUME CONTROL BLOCK macro UCB$Q_DEVCHAR = 96,0,0,0 %; literal UCB$S_DEVCHAR = 8; ! Device characteristic bits quadword macro UCB$L_DEVCHAR = 96,0,32,0 %; ! Original device characteristic bits macro UCB$L_DEVCHAR2 = 100,0,32,0 %; ! Extended device characteristic bits macro UCB$R_CBB_AFFINITY = 104,0,0,0 %; literal UCB$S_CBB_AFFINITY = 48; ! Embedded CBB block macro UCB$L_AFFINITY = 152,0,32,0 %; ! Device affinity macro UCB$Q_AFFINITY = 152,0,0,0 %; literal UCB$S_AFFINITY = 8; ! Device affinity macro UCB$L_XTRA = 280,0,32,0 %; ! EXTRA LONGWORD (FOR SMP) macro UCB$L_ALTIOWQ = 280,0,32,1 %; ! ALTERNATE STARTIO WAIT ! QUEUE macro UCB$B_DEVCLASS = 284,0,8,0 %; ! DEVICE CLASS macro UCB$B_DEVTYPE = 285,0,8,0 %; ! DEVICE TYPE macro UCB$W_DEVBUFSIZ = 286,0,16,0 %; ! DEVICE DEFAULT BUFFER SIZE macro UCB$Q_DEVDEPEND = 288,0,0,0 %; literal UCB$S_DEVDEPEND = 8; ! Device dependent quadword macro UCB$R_DEVDEPEND_Q_BLOCK = 288,0,0,0 %; literal UCB$S_DEVDEPEND_Q_BLOCK = 8; macro UCB$L_DEVDEPEND = 288,0,32,0 %; ! First device dependent longword macro UCB$R_DISK_DEVDEPEND = 288,0,32,0 %; literal UCB$S_DISK_DEVDEPEND = 4; ! Disk fields macro UCB$B_SECTORS = 288,0,8,0 %; ! Sectors per track macro UCB$B_TRACKS = 289,0,8,0 %; ! Track per cylinder macro UCB$W_CYLINDERS = 290,0,16,0 %; ! Cylinders per disk macro UCB$R_TERM_DEVDEPEND = 288,0,32,0 %; literal UCB$S_TERM_DEVDEPEND = 4; ! Terminal fields macro UCB$B_VERTSZ = 291,0,8,0 %; ! Vertical page size (lines per page) macro UCB$R_NET_DEVDEPEND = 288,0,32,0 %; literal UCB$S_NET_DEVDEPEND = 4; ! Network fields macro UCB$B_LOCSRV = 288,0,8,0 %; ! Local link services macro UCB$B_REMSRV = 289,0,8,0 %; ! Remote link services macro UCB$W_BYTESTOGO = 290,0,16,0 %; ! No. of bytes left in rcv bfr macro UCB$L_DEVDEPND2 = 292,0,32,0 %; ! Second device dependent long word macro UCB$L_TT_DEVDP1 = 292,0,32,0 %; ! Terminal -- Device dependent long word macro UCB$W_TU_FORMENU = 292,0,16,0 %; ! TU/TMSCP -- Supported formats (returned by GETDVI). macro UCB$Q_DEVDEPEND2 = 296,0,0,0 %; literal UCB$S_DEVDEPEND2 = 8; ! Device dependent quadword macro UCB$R_DEVDEPEND2_Q_BLOCK = 296,0,0,0 %; literal UCB$S_DEVDEPEND2_Q_BLOCK = 8; macro UCB$L_DEVDEPND3 = 296,0,32,0 %; ! 3rd device dependent longword macro UCB$L_DEVDEPND4 = 300,0,32,0 %; ! 4th device dependent long word macro UCB$R_TMV_BCNT = 296,0,0,0 %; literal UCB$S_TMV_BCNT = 8; ! Tape Mount verification byte counts macro UCB$W_TMV_BCNT1 = 296,0,16,0 %; ! Byte count for 1st CRC macro UCB$W_TMV_BCNT2 = 298,0,16,0 %; ! ...2nd CRC macro UCB$W_TMV_BCNT3 = 300,0,16,0 %; ! ...3rd CRC macro UCB$W_TMV_BCNT4 = 302,0,16,0 %; ! ...4th CRC macro UCB$L_IOQFL = 304,0,32,1 %; ! I/O QUEUE LISTHEAD FORWARD LINK macro UCB$L_IOQBL = 308,0,32,1 %; ! I/O QUEUE LISTHEAD BACKWARD LINK macro UCB$W_UNIT = 312,0,16,0 %; ! PHYSICAL DEVICE UNIT NUMBER macro UCB$L_UNIT = 312,0,32,0 %; macro UCB$W_CHARGE = 316,0,16,0 %; ! MAILBOX BYTE COUNT QUOTA CHARGE macro UCB$W_RWAITCNT = 316,0,16,0 %; ! CLASS DRIVERS -- THREADS WAITING RESOURCES macro UCB$B_CM1 = 316,0,8,0 %; ! LEVEL 1 CONTROLLER ALLOCATION MASK macro UCB$B_CM2 = 317,0,8,0 %; ! LEVEL 2 CONTROLLER ALLOCATION MASK macro UCB$L_IRP = 320,0,32,1 %; ! CURRENT I/O REQUEST PACKET ADDRESS macro UCB$L_REFC = 324,0,32,0 %; ! REFERENCE COUNT OF PROCESSES macro UCB$B_DIPL = 328,0,8,0 %; ! DEVICE INTERRUPT PRIORITY LEVEL macro UCB$B_STATE = 328,0,8,0 %; ! NET -- LINK STATE FOR NETWORK TRANSITIONS macro UCB$B_AMOD = 329,0,8,0 %; ! ALLOCATION ACCESS MODE macro UCB$W_FILL_0 = 330,0,16,1 %; macro UCB$L_AMB = 332,0,32,1 %; ! ASSOCIATED UNIT CONTROL BLOCK POINTER macro UCB$L_STS = 336,0,32,0 %; ! DEVICE UNIT STATUS macro UCB$V_TIM = 336,0,1,0 %; ! TIME OUT ENABLED (1=YES) macro UCB$V_INT = 336,1,1,0 %; ! INTERRUPT EXPECTED (1=YES) macro UCB$V_ERLOGIP = 336,2,1,0 %; ! ERROR LOG IN PROGRESS ON UNIT (1=YES) macro UCB$V_CANCEL = 336,3,1,0 %; ! CANCEL I/O ON UNIT (1=YES) macro UCB$V_ONLINE = 336,4,1,0 %; ! UNIT ONLINE (1=YES) macro UCB$V_POWER = 336,5,1,0 %; ! POWER FAILED WHILE UNIT BUSY (1=YES) macro UCB$V_TIMOUT = 336,6,1,0 %; ! UNIT TIMED OUT (1=YES) macro UCB$V_INTTYPE = 336,7,1,0 %; ! RECEIVER INTERRUPT IF SET macro UCB$V_BSY = 336,8,1,0 %; ! UNIT IS BUSY (1=YES) macro UCB$V_MOUNTING = 336,9,1,0 %; ! DEVICE IS BEING MOUNTED macro UCB$V_DEADMO = 336,10,1,0 %; ! DEALLOCATE AT DISMOUNT macro UCB$V_VALID = 336,11,1,0 %; ! VOLUME IS SOFTWARE VALID macro UCB$V_UNLOAD = 336,12,1,0 %; ! UNLOAD VOLUME AT DISMOUNT macro UCB$V_TEMPLATE = 336,13,1,0 %; ! SET IF THIS IS TEMPLATE UCB macro UCB$V_MNTVERIP = 336,14,1,0 %; ! MOUNT VERIFICATION IN PROGRESS macro UCB$V_WRONGVOL = 336,15,1,0 %; ! WRONG VOLUME DETECTED DURING MOUNT VERIFICATION macro UCB$V_DELETEUCB = 336,16,1,0 %; ! DELETE THIS UCB WHEN REFC REACHES ZERO macro UCB$V_LCL_VALID = 336,17,1,0 %; ! VOLUME IS VALID ON THE LOCAL NODE macro UCB$V_SUPMVMSG = 336,18,1,0 %; ! IF SET, SUPPRESS SUCCESS TYPE MOUNT VER. MSGS. macro UCB$V_MNTVERPND = 336,19,1,0 %; ! MOUNT VERIFICATION IS PENDING ON BUSY DEVICE. macro UCB$V_DISMOUNT = 336,20,1,0 %; ! DISMOUNT IN PROGRESS macro UCB$V_CLUTRAN = 336,21,1,0 %; ! VAXcluster STATE TRANSITION IN PROGRESS macro UCB$V_WRTLOCKMV = 336,22,1,0 %; ! Write-locked mount verification in progress macro UCB$V_SVPN_END = 336,23,1,0 %; ! Last byte used from page mapped by SVPN macro UCB$V_ALTBSY = 336,24,1,0 %; ! Unit is busy via alternate startio path macro UCB$V_SNAPSHOT = 336,25,1,0 %; ! Restart validation is in progress macro UCB$V_NO_ASSIGN = 336,26,1,0 %; ! Unit cannot have channels assigned to it. macro UCB$V_EXFUNC_SUPP = 336,27,1,0 %; ! Unit supports the EXFUNC bit macro UCB$V_FAST_PATH = 336,28,1,0 %; ! Unit supports FASTPATH affinity macro UCB$V_PATHVERIP = 336,29,1,0 %; ! Path verification in progress for this device macro UCB$V_FP_HWINT = 336,30,1,0 %; ! Unit supports FASTPATH HW interrupt cpu affinity macro UCB$V_IOPOST_LOCAL = 336,31,1,0 %; ! Unit supports I/O post processing on the current CPU macro UCB$L_DEVSTS = 340,0,32,0 %; ! DEVICE DEPENDENT STATUS macro UCB$V_JOB = 340,0,1,0 %; ! Job Controller notified macro UCB$V_TEMPL_BSY = 340,6,1,0 %; ! Template UCB is busy macro UCB$V_PRMMBX = 340,0,1,0 %; ! Permanent mailbox macro UCB$V_DELMBX = 340,1,1,0 %; ! Mailbox marked for delete macro UCB$V_TT_TIMO = 340,1,1,0 %; ! Terminal read timeout in progress macro UCB$V_TT_NOTIF = 340,2,1,0 %; ! Terminal user notified of unsolicted data macro UCB$V_TT_HANGUP = 340,3,1,0 %; ! Process hang up macro UCB$V_TT_DEVSTS_FILL = 340,4,11,0 %; literal UCB$S_TT_DEVSTS_FILL = 11; ! fill to the end the word macro UCB$V_TT_NOLOGINS = 340,15,1,0 %; ! NOLOGINS ALLOWED macro UCB$V_NT_BFROVF = 340,2,1,0 %; ! Too many bytes rcvd macro UCB$V_NT_NAME = 340,4,1,0 %; ! Link has declared a connect name macro UCB$V_NT_BREAK = 340,5,1,0 %; ! Link is being broken macro UCB$V_ECC = 340,0,1,0 %; ! ECC correction was made macro UCB$V_DIAGBUF = 340,1,1,0 %; ! Diagnostic buffer specified macro UCB$V_NOCNVRT = 340,2,1,0 %; ! No LBN to media address conversion macro UCB$V_DX_WRITE = 340,3,1,0 %; ! Console floppy write operation macro UCB$V_DATACACHE = 340,4,1,0 %; ! Data blocks being cached macro UCB$V_MSCP_MNTVERIP = 340,8,1,0 %; ! Mount verification in progress macro UCB$V_MSCP_INITING = 340,9,1,0 %; ! UCB is being initialized macro UCB$V_MSCP_WAITBMP = 340,10,1,0 %; ! RWAITCNT has been bumped macro UCB$V_MSCP_FLOVR = 340,11,1,0 %; ! Bit toggled everytime a failover succeeds. macro UCB$V_MSCP_PKACK = 340,12,1,0 %; ! Set when a IO$_PACKACK is in progress. macro UCB$V_MSCP_WRTP = 340,13,1,0 %; ! Unit MSCP write protected in some way. macro UCB$V_MSCP_IGNSRV = 340,14,1,0 %; ! Ignore served paths during connection failover. macro UCB$V_MSCP_MVRESTART = 340,15,1,0 %; ! Restart Mount Ver to pickup new path macro UCB$V_MSCP_LOCAL_DRAIN_WAITBMP = 340,16,1,0 %; ! RWAIT bumped due to io$_local_drain processing macro UCB$V_DU_SHMV_STRTD = 340,3,1,0 %; ! Shadowing mount verification started macro UCB$V_DU_0MNOTE = 340,5,1,0 %; ! Zero members message sent macro UCB$V_MVFKBBSY = 340,6,1,0 %; ! DUTU mount verify fork block busy macro UCB$V_GTUNMBSY = 340,7,1,0 %; ! DUTU get unit name fork block busy macro UCB$V_TU_OVRSQCHK = 340,0,1,0 %; ! Override sequence checking macro UCB$V_TU_TRACEACT = 340,1,1,0 %; ! IRP trace table active macro UCB$V_TU_SEQNOP = 340,2,1,0 %; ! Sequential NOP tape operation in progress macro UCB$V_TU_1DENS = 340,3,1,0 %; ! Single density device macro UCB$V_TU_DENS_DETERMINED = 340,4,1,0 %; ! Density already determined. Basically a ! bit that says that a particular part of ! PACKACK processing has already been done ! once for this unit. macro UCB$V_TU_MEDIA_LOADED = 340,5,1,0 %; ! Media loaded into drive and drive available. macro UCB$V_SHD_WLG_INV = 340,7,1,0 %; ! Status of write logging on this V.U. macro UCB$V_SHD_SEQCMD_HERE = 340,10,1,0 %; ! Sequential command in progress on this node macro UCB$V_SHD_SEQCMD_THERE = 340,11,1,0 %; ! Sequential command in progress on another node macro UCB$V_SHD_PASSIVE_MV = 340,12,1,0 %; ! Passive MV in progress macro UCB$V_SHD_NODE_FAILURE = 340,13,1,0 %; ! Node failure in progress macro UCB$V_SHD_WLGSTA_CHA = 340,14,1,0 %; ! Write log state change macro UCB$V_SHD_VCB_DEQUEUE = 340,15,1,0 %; ! Indicate DEQUE required on VCB macro UCB$V_SHD_SEQCMD_PEND = 340,16,1,0 %; ! Sequential command has been requested by this system macro UCB$V_SHD_ST_DRAIN_IO = 340,17,1,0 %; ! Insure that all user I/O has been returned by the lower layers macro UCB$V_SHD_MBRSHP_EVENT = 340,18,1,0 %; ! When creating membership event threads stall new I/O macro UCB$V_SHD_TGR_VALIDATE = 340,19,1,0 %; ! SHLK$TRIGGER_VALIDATE when another system has finished changing VU membership macro UCB$V_PORT_ONLINE = 340,0,1,0 %; ! Port is online. macro UCB$V_FKLOCK = 340,1,1,0 %; ! Fork block interlock bit macro UCB$V_MSGFKLOCK = 340,2,1,0 %; ! Fork block interlock for ! printing operator msgs macro UCB$V_INIFKLOCK = 340,3,1,0 %; ! Fork block interlock for ! adapter errors macro UCB$V_BAD_REV = 340,4,1,0 %; ! Bad Port Revision flag macro UCB$V_PA_ERLOGIP = 340,5,1,0 %; ! Error log buffer in the ! extended UCB is in use macro UCB$V_MFQEFKLOCK = 340,6,1,0 %; ! Fork block interlock for ! emergency pool allocation macro UCB$V_MFQE_LOST = 340,7,1,0 %; ! Lost MFQE interrupt because ! the fork block was in use macro UCB$V_ADMIN_ONLINE = 340,8,1,0 %; ! Admin unit is on-line macro UCB$V_ADMIN_INIT = 340,9,1,0 %; ! Admin unit init in-progress macro UCB$V_ADMIN_TEAR_DOWN = 340,10,1,0 %; ! Admin unit tear down in-progress macro UCB$V_CHAN_ONLINE = 340,16,1,0 %; ! Channel is on-line macro UCB$V_CHAN_INIT = 340,17,1,0 %; ! Channel init in-progress macro UCB$V_CHAN_TEAR_DOWN = 340,18,1,0 %; ! Channel tear down in-progress macro UCB$V_PB_TQE_BUSY = 340,24,1,0 %; ! PB_TQE is busy macro UCB$V_MBR_CALLBACK = 340,25,1,0 %; ! Galaxy Membership Callback has ! been registered macro UCB$V_SHUTDOWN_REQ = 340,26,1,0 %; ! Shutdown Requsted macro UCB$V_SHUTDOWN_IP = 340,27,1,0 %; ! Shutdown In Progress macro UCB$V_PB_LAST_GASP_EMULATED = 340,28,1,0 %; ! Last gasp emulation ! initiated macro UCB$L_QLEN = 344,0,32,1 %; ! Device queue length ! ! UCB$PS_START_AFF_QFL is used by IOC$INITIATE, IOC$INITIATE_NEW_IO and ! IOC$INITIATE_PORT_CPU as follows, and any new use of this cell must ! conform to this logic; also note that all reads from and writes to ! this cell must be performed holding IOLOCK8. ! ! 1) If the field contains the UCB's address: ! ! - The UCB is not on any CPU's Start I/O Affinity queue ! - The UCB is being processed by IOC$INITIATE_PORT_CPU ! ! 1) If the field is zero: ! ! - The UCB is not on any CPU's Start I/O Affinity queue ! - The UCB is not being processed by IOC$INITIATE_PORT_CPU ! ! 3) The only other values this field should ever take are those which ! are written to it when it is used to queue the UCB to a CPU's ! Start I/O Affinity queue ! macro UCB$PS_START_AFF_QFL = 348,0,32,1 %; ! CPUDB Affinity queue flink macro UCB$PS_START_AFF_QBL = 352,0,32,1 %; ! CPUDB Affinity queue blink macro UCB$L_PORT_CPUDB = 356,0,32,1 %; ! Device's CPUDB addr for FastPath macro UCB$PS_IO_COUNTERS = 360,0,32,1 %; ! IOCNT debug counters macro UCB$L_DUETIM = 364,0,32,0 %; ! DUE TIME FOR I/O COMPLETION macro UCB$L_OPCNT = 368,0,32,0 %; ! COUNT OF OPERATIONS COMPLETED macro UCB$L_SVPN = 372,0,32,0 %; ! SYSTEM VIRTUAL PAGE/MAP REGISTER NUMBER macro UCB$L_SVAPTE = 376,0,32,1 %; ! SYSTEM VIRTUAL ADDRESS OF PTE macro UCB$L_BCNT = 380,0,32,0 %; ! BYTE COUNT OF TRANSFER macro UCB$L_BOFF = 384,0,32,0 %; ! Byte offset in page macro UCB$L_SOFTERRCNT = 388,0,32,0 %; ! SOFT ERROR COUNT macro UCB$L_ERTCNT = 392,0,32,0 %; ! ERROR LOG DEVICE CURRENT ERROR RETRY COUNT macro UCB$L_ERTMAX = 396,0,32,0 %; ! ERROR LOG DEVICE MAXIMUM ERROR RETRY COUNT macro UCB$L_ERRCNT = 400,0,32,0 %; ! DEVICE ERROR COUNT macro UCB$L_PDT = 404,0,32,1 %; ! ADDR OF PORT DESCRIPTOR TABLE macro UCB$L_DDT = 408,0,32,1 %; ! ADDR OF DDT (OPTIONAL BUT PREFERRED) macro UCB$PS_ADP = 412,0,32,1 %; ! ADDR OF ADP macro UCB$PS_CRCTX = 416,0,32,1 %; ! ADDR OF COUNTED RESOURCE CONTEXT BLK macro UCB$L_MEDIA_ID = 420,0,32,0 %; ! BIT ENCODED MEDIA IDENTIFICATION macro UCB$V_MEDIA_ID_NN = 420,0,7,0 %; literal UCB$S_MEDIA_ID_NN = 7; ! MEDIA NAME NUMBER macro UCB$V_MEDIA_ID_N2 = 420,7,5,0 %; literal UCB$S_MEDIA_ID_N2 = 5; ! MEDIA NAME CHAR 2 macro UCB$V_MEDIA_ID_N1 = 420,12,5,0 %; literal UCB$S_MEDIA_ID_N1 = 5; ! MEDIA NAME CHAR 1 macro UCB$V_MEDIA_ID_N0 = 420,17,5,0 %; literal UCB$S_MEDIA_ID_N0 = 5; ! MEDIA NAME CHAR 0 macro UCB$V_MEDIA_ID_T1 = 420,22,5,0 %; literal UCB$S_MEDIA_ID_T1 = 5; ! MEDIA TYPE CHAR 1 macro UCB$V_MEDIA_ID_T0 = 420,27,5,0 %; literal UCB$S_MEDIA_ID_T0 = 5; ! MEDIA TYPE CHAR 0 macro UCB$PS_DTN = 424,0,32,1 %; ! ADDR OF DEVICE TYPE NAME DTN STRUC macro UCB$PS_DTN_LINK = 428,0,32,1 %; ! ADDR OF NEXT UCB WITH THIS DEVICE TYPE macro UCB$PS_TOUTROUT = 432,0,32,1 %; ! DEVICE TIMEOUT ROUTINE PROCEDURE VALUE macro UCB$PS_SUD = 436,0,32,1 %; ! ADDR OF SUD FOR THIS UCB ! Spare Space - Reserved for use by HP literal UCB$K_LENGTH = 472; ! LENGTH OF STANDARD UCB literal UCB$C_LENGTH = 472; ! LENGTH OF STANDARD UCB literal UCB$S_UCBDEF = 472; ! OLD UCBDEF SIZE NAME FOR COMPATIBILITY ! ! DEVICE DEPENDENT UCB EXTENSIONS ! ! MAILBOX ! literal UCB$S_MB_UCB = 552; macro UCB$L_MB_READERREFC = 472,0,32,0 %; ! REFERENCE COUNT OF READ ENABLED CHANNELS TO DEVICE macro UCB$L_MB_WRITERREFC = 476,0,32,0 %; ! REFERENCE COUNT OF WRITE ENABLED CHANNELS TO DEVICE macro UCB$L_MB_READQFL = 480,0,32,1 %; ! MAILBOX READ IRP QUEUE LISTHEAD macro UCB$L_MB_READQBL = 484,0,32,1 %; macro UCB$L_MB_WRITERWAITQFL = 488,0,32,1 %; ! MAILBOX WAIT FOR WRITE CHANNEL TO BE ASSIGNED QUEUE macro UCB$L_MB_WRITERWAITQBL = 492,0,32,1 %; macro UCB$L_MB_READERWAITQFL = 496,0,32,1 %; ! MAILBOX WAIT FOR READ CHANNEL TO BE ASSIGNED QUEUE macro UCB$L_MB_READERWAITQBL = 500,0,32,1 %; macro UCB$L_MB_NOWRITERWAITQFL = 504,0,32,1 %; ! MAILBOX WAIT FOR ALL WRITE CHANNELS TO BE DEASSIGNED QUEUE macro UCB$L_MB_NOWRITERWAITQBL = 508,0,32,1 %; macro UCB$L_MB_NOREADERWAITQFL = 512,0,32,1 %; ! MAILBOX WAIT FOR ALL READ CHANNELS TO BE DEASSIGNED QUEUE macro UCB$L_MB_NOREADERWAITQBL = 516,0,32,1 %; macro UCB$L_MB_ROOM_NOTIFY = 520,0,32,1 %; ! ROOM NOTIFY AST LIST macro UCB$L_LOGADR = 524,0,32,1 %; ! LOGICAL NAME BLOCK ADDRESS macro UCB$L_MB_LOGADR = 524,0,32,1 %; ! and a synonym to let SDA find the field macro UCB$PS_MB_LAST_CHANNEL = 528,0,32,1 %; ! Pointer to Last channel deassign routine macro UCB$T_QUAD_FILL1 = 532,0,32,0 %; literal UCB$S_QUAD_FILL1 = 4; ! Fill bytes for quadword alignment macro UCB$Q_MB_CONTEXT = 536,0,0,0 %; literal UCB$S_MB_CONTEXT = 8; ! 64 bit context data passed back when last channel deassign rotuine is called. macro UCB$L_MB_BUFQUO = 544,0,32,1 %; ! MAILBOX Buffer Quota macro UCB$L_MB_INIQUO = 548,0,32,1 %; ! MAILBOX Initial Buffer Quota literal UCB$K_MB_UCBLENGTH = 552; ! SIZE OF MAILBOX UCB literal UCB$C_MB_UCBLENGTH = 552; ! SIZE OF MAILBOX UCB literal UCB$C_MB_LENGTH = 552; ! SIZE OF MAILBOX UCB for SDA FORMAT literal UCB$S_MB_EXTENSION = 552; ! Old step-1 size name for compatibility ! ! ERROR LOG DEVICES (ALL) ! literal UCB$S_ERL_UCB = 488; macro UCB$L_EMB = 472,0,32,1 %; ! ADDRESS OF ERROR MESSAGE BUFFER macro UCB$L_FUNC = 476,0,32,0 %; ! I/O function modifiers macro UCB$L_DPC = 480,0,32,1 %; ! SAVED DRIVER SUBROUTINE RETURN ADDRESS macro UCB$W_MT3_DENSITY = 484,0,16,0 %; ! Current Tape Density word. (For Tape Only) literal UCB$K_ERL_LENGTH = 488; ! SIZE OF ERROR LOG UCB literal UCB$C_ERL_LENGTH = 488; ! SIZE OF ERROR LOG UCB literal UCB$S_UCBDEF4 = 488; ! Old step-1 size name for compatibility ! ! DUAL PORTED DEVICES (ALL DISKS AND MOST TAPES) ! literal UCB$S_DP_UCB = 504; macro UCB$L_DP_DDB = 488,0,32,1 %; ! Pointer to alternate DDB macro UCB$L_DP_LINK = 492,0,32,1 %; ! Address of next UCB for this DDB macro UCB$L_DP_ALTUCB = 496,0,32,1 %; ! Addr of alternate UCB for this unit macro UCB$L_2P_DDB = 488,0,32,1 %; ! Pointer to alternate DDB macro UCB$L_2P_LINK = 492,0,32,1 %; ! Address of next UCB for this DDB macro UCB$L_2P_ALTUCB = 496,0,32,1 %; ! Addr of alternate UCB for this unit literal UCB$K_DP_LENGTH = 504; ! Size of dual path UCB literal UCB$C_DP_LENGTH = 504; ! size of dual path UCB literal UCB$K_2P_LENGTH = 504; ! Size of dual path UCB literal UCB$C_2P_LENGTH = 504; ! size of dual path UCB literal UCB$S_DUALPATH_EXTENSION = 504; ! Old step-1 size name for compatibility ! ! ALL DISKS AND TAPES ! literal UCB$M_AST_ARMED = %X'8000'; literal UCB$K_LCL_DISK_LENGTH = 548; ! Size of local disk UCB literal UCB$C_LCL_DISK_LENGTH = 548; ! Size of local disk UCB literal UCB$K_LCL_TAPE_LENGTH = 536; ! Size of local tape UCB literal UCB$C_LCL_TAPE_LENGTH = 536; ! Size of local tape UCB literal UCB$S_DT_UCB = 552; macro UCB$W_DIRSEQ = 504,0,16,0 %; ! Directory sequence number macro UCB$V_AST_ARMED = 504,15,1,0 %; ! Blocking AST armed flag macro UCB$B_ONLCNT = 506,0,8,0 %; ! Online count macro UCB$Q_MAXBLOCK_64 = 512,0,0,0 %; literal UCB$S_MAXBLOCK_64 = 8; ! 64-bit highest block macro UCB$L_MAXBLOCK = 512,0,32,0 %; ! Random access device highest block macro UCB$L_MAXBCNT = 520,0,32,0 %; ! Maximum transfer BCNT macro UCB$L_DCCB = 524,0,32,1 %; ! Pointer to data cache control block macro UCB$L_QLENACC = 528,0,32,0 %; ! Queue length accumulator macro UCB$L_USN = 532,0,32,0 %; ! Reserved macro UCB$PS_MOUNT_LIST = 536,0,32,1 %; ! Reserved macro UCB$T_MSCP_DSPLY_PATH = 540,0,0,0 %; literal UCB$S_MSCP_DSPLY_PATH = 8; ! Displayable path buffer. macro UCB$L_RECORD = 512,0,32,0 %; ! Current tape position or frame counter macro UCB$L_PREV_RECORD_L = 516,0,32,0 %; ! Tape position prior at start of last I/O (longword) macro UCB$B_PREV_RECORD = 516,0,8,0 %; ! Tape position prior at start of last I/O macro UCB$L_TMV_RECORD = 524,0,32,0 %; ! Position following last guaranteed successful I/O macro UCB$W_TMV_CRC1 = 528,0,16,0 %; ! 1st CRC for Mount Ver's media validation macro UCB$W_TMV_CRC2 = 530,0,16,0 %; ! 2nd CRC ... macro UCB$W_TMV_CRC3 = 532,0,16,0 %; ! 3rd CRC ... macro UCB$W_TMV_CRC4 = 534,0,16,0 %; ! 4th CRC ... macro UCB$L_ALLOCLASS = 548,0,32,0 %; ! Device allocation class literal UCB$K_DT_LENGTH = 552; ! Size of disk/tape UCB literal UCB$C_DT_LENGTH = 552; ! size of disk/tape UCB literal UCB$S_DISKTAPE_UCB_EXTENSION = 552; ! Old step-1 size name for compatibility ! ! MSCP DISKS AND TAPES UCB EXTENSION ! literal UCB$S_MSCP_UCB = 608; macro UCB$L_CDDB = 552,0,32,1 %; ! Pointer to active CDDB macro UCB$L_2P_CDDB = 556,0,32,1 %; ! Pointer to alternate CDDB macro UCB$L_CDDB_LINK = 560,0,32,1 %; ! Pointer to next UCB in CDDB chain macro UCB$L_CDT = 564,0,32,1 %; ! Pointer to active CDT macro UCB$L_WAIT_CDDB = 568,0,32,1 %; ! Address of CDDB waiting for mnt. ver. to complete on this UCB macro UCB$L_PREF_CDDB = 572,0,32,1 %; ! CDDB address for preferred path macro UCB$Q_UNIT_ID = 576,0,0,0 %; literal UCB$S_UNIT_ID = 8; ! Unique MSCP unit identifier macro UCB$W_MSCPUNIT = 584,0,16,0 %; ! Primary path MSCP unit number macro UCB$W_UNIT_FLAGS = 586,0,16,0 %; ! MSCP unit flags macro UCB$W_LCL_MSCPUNIT = 588,0,16,0 %; ! MSCP unit number for local (non-emulated) controllers macro UCB$W_SRV_MSCPUNIT = 590,0,16,0 %; ! MSCP unit number for served (emulated) controllers macro UCB$L_MSCPDEVPARAM = 592,0,32,0 %; ! MSCP device-dependent parameters macro UCB$B_FREECAP = 596,0,8,0 %; ! Free capacity macro UCB$B_FAIL_MUTEX = 597,0,8,0 %; ! MUTEX for device failover macro UCB$W_MSCP_RESVDW = 598,0,16,0 %; ! Reserved for MSCP enhancements macro UCB$L_SHAD = 600,0,32,1 %; ! Virtual Unit Pointer to HBS SHAD macro UCB$L_DUTUFKBLINK = 604,0,32,0 %; ! Link to permanent fork blocks literal UCB$K_MSCP_DISK_LENGTH = 608; ! Size of MSCP disk UCB literal UCB$C_MSCP_DISK_LENGTH = 608; ! Size of MSCP disk UCB (for SDA) literal UCB$K_MSCP_TAPE_LENGTH = 608; ! Size of MSCP tape UCB literal UCB$C_MSCP_TAPE_LENGTH = 608; ! Size of MSCP tape UCB (for SDA) literal UCB$S_MSCP_UCB_EXTENSION = 608; ! Old step-1 size name for compatibility ! ! DISK CLASS DRIVER DEVICE DEPENDENT UNIT CONTROL BLOCK OFFSETS ! literal UCB$S_DU_UCB = 640; macro UCB$L_DU_VOLSER = 608,0,32,0 %; ! Serial umber as returned ! in ONLINE end packet. macro UCB$L_DU_USIZE = 612,0,32,0 %; ! Size of user visible area of ! unit in logical blocks macro UCB$L_DU_TOTSZ = 616,0,32,0 %; ! Size of unit including RCT ! area in logical blocks macro UCB$W_DU_RCTSIZE = 620,0,16,0 %; ! Size of the RCT in blocks macro UCB$B_DU_RCTCPYS = 622,0,8,0 %; ! Number of RCT copies on the unit macro UCB$B_DU_RBNPTRK = 623,0,8,0 %; ! RBNs per track macro UCB$W_DU_LBNPTRK = 624,0,16,0 %; ! LBNs per track macro UCB$W_DU_TRKPGRP = 626,0,16,0 %; ! Tracks per group macro UCB$W_DU_GRPPCYL = 628,0,16,0 %; ! Groups per cylinder macro UCB$W_DU_MUNTC = 630,0,16,0 %; ! Multi-unit code macro UCB$B_DU_USVR = 632,0,8,0 %; ! Unit software version macro UCB$B_DU_UHVR = 633,0,8,0 %; ! Unit hardware version literal UCB$K_DU_LENGTH = 640; ! Size of DISK CLASS DRIVER dependent UCB ! Old step-1 size name for compatibility literal UCB$S_DUDRIVER_EXTENSION = 640; ! ! TAPE CLASS DRIVER DEVICE DEPENDENT UNIT CONTROL BLOCK OFFSETS ! literal UCB$M_TU_RPTREQ = %X'1'; literal UCB$M_TU_RPTPND = %X'2'; literal UCB$M_TU_DENSITY = %X'4'; literal UCB$S_TU_UCB = 640; macro UCB$L_TU_MAXWRCNT = 608,0,32,0 %; ! Largest size record likely to have reliability statistics. macro UCB$W_TU_FORMAT = 612,0,16,0 %; ! Format (density). macro UCB$W_TU_SPEED = 614,0,16,0 %; ! Current speed. macro UCB$W_TU_NOISE = 616,0,16,0 %; ! Size of noise records ignored by controller. macro UCB$B_TU_SOFTERR = 618,0,8,0 %; ! Media quality reporting counter. macro UCB$B_TU_SOFTFLAGS = 619,0,8,0 %; ! Media quality reporting flags. macro UCB$V_TU_RPTREQ = 619,0,1,0 %; ! Report request. macro UCB$V_TU_RPTPND = 619,1,1,0 %; ! Report pending. macro UCB$V_TU_DENSITY = 619,2,1,0 %; ! Density check done if set. macro UCB$L_TRACEBEG = 620,0,32,1 %; ! Pointer to beginning of trace ring. macro UCB$L_TRACEPTR = 624,0,32,1 %; ! Pointer to next available slot. macro UCB$L_TRACEND = 628,0,32,1 %; ! Pointer to beyond trace ring. macro UCB$L_TRACE_NEXT_SLOT = 632,0,32,1 %; ! Number of next trace slot to use. literal UCB$K_TU_LENGTH = 640; ! Size of TAPE CLASS DRIVER dependent UCB ! Old step-1 size name for compatibility literal UCB$S_TUDRIVER_EXTENSION = 640; ! ! SCSI Port Driver Extensions ! literal UCB$M_PK_IFKB_LOCK = %X'1'; literal UCB$S_SCSI_UCB = 552; macro UCB$IL_PK_CUR_DATA = 488,0,32,0 %; ! Selection bus data snapshot macro UCB$IL_PK_RESEL_ID = 492,0,32,0 %; ! [RE]selection saved id macro UCB$IL_PK_EXFLAGS = 496,0,32,0 %; ! Port extended flags macro UCB$V_PK_IFKB_LOCK = 496,0,1,0 %; ! Init FKB locked macro UCB$IB_PK_INIFKBLK = 500,0,0,1 %; literal UCB$S_PK_INIFKBLK = 48; ! Initialization fork block macro UCB$PS_PK_INIKPB = 500,0,32,1 %; ! Initializtion KPB pointer literal UCB$K_PK_LENGTH = 552; ! Size of SCSI port UCB literal UCB$C_PK_LENGTH = 552; ! Size of SCSI port UCB for SDA FORMAT literal UCB$S_SCSI_PORT_EXTENSION = 552; ! Old step-1 size name for compatibility ! ! NETWORK LOGICAL LINK (NETWORK MAILBOX) EXTENSION ! literal UCB$M_BACKP = %X'20'; literal UCB$C_LOGLNK = 1; ! CONNECT IS FOR LOGICAL LINK (NOT SINGLE MSG) literal UCB$S_NET_UCB = 488; macro UCB$L_NT_DATSSB = 472,0,32,1 %; ! ADDRESS OF DATA SUBCHANNEL STATUS BLOCK macro UCB$L_NT_INTSSB = 476,0,32,1 %; ! ADDRESS OF INT/LS SSB macro UCB$W_NT_CHAN = 480,0,16,0 %; ! DDCMP CHANNEL NO. macro UCB$V_LTYPE = 482,0,2,0 %; literal UCB$S_LTYPE = 2; ! LINK TYPE BITS macro UCB$V_SEGFLO = 482,2,1,0 %; ! SEGMENT REQUEST COUNTS macro UCB$V_MSGFLO = 482,3,1,0 %; ! MESSAGE REQUEST COUNTS macro UCB$V_MSGACK = 482,4,1,0 %; ! MESSAGE ACK/NAK macro UCB$V_BACKP = 482,5,1,0 %; ! BACKPRESSURE (1=> NO FLOW) macro UCB$V_LNKPRI = 482,6,2,0 %; literal UCB$S_LNKPRI = 2; ! LINK PRIORITY (IGNORED) ! NETWORK CONSTANTS literal UCB$S_UCBDEF7 = 488; ! Old step-1 size name for compatibility ! ! NI DEVICE EXTENSION ! literal UCB$S_NI_UCB = 480; macro UCB$L_NI_HWAPTR = 472,0,32,1 %; ! ADDRESS OF NI DEVICE HARDWARE ADDRESS macro UCB$L_NI_MLTPTR = 476,0,32,1 %; ! ADDRESS OF PROTOCOL MULTICAST TABLE literal UCB$K_NI_LENGTH = 480; ! SIZE OF NI DEVICE UCB literal UCB$C_NI_LENGTH = 480; ! SIZE OF NI DEVICE UCB literal UCB$S_UCBDEF9 = 480; ! Old step-1 size name for compatibility ! ! DAP DEVICE EXTENSION (FOR DEVICES THAT USE THE DAP INTERFACE WITHOUT ! UNDELYING DECNET, SUCH AS CERTAIN CONSOLE DISKS). ! literal UCB$S_DAP_UCB = 504; macro UCB$T_DAPDEVNAM = 472,0,0,0 %; literal UCB$S_DAPDEVNAM = 32; ! EQUIVALENCE NAME STRING literal UCB$K_DAPDEV_LENGTH = 504; ! SIZE OF DAP DEVICE UCB literal UCB$C_DAPDEV_LENGTH = 504; ! SIZE OF DAP DEVICE UCB literal UCB$S_UCBDEF10 = 504; ! Old step-1 size name for compatibility literal UCB$K_BGN_ADPTAB = 600; literal UCB$M_LBDG = %X'1'; literal UCB$M_POLL = %X'2'; literal UCB$M_LOCAL = %X'4'; literal UCB$M_SINGLE_PATH = %X'8'; literal UCB$M_STORAGE = %X'10'; literal UCB$K_BGN_ADPSUB = 628; literal UCB$K_BGN_PDTSUB = 692; literal UCB$K_END_ADPTAB = 732; literal UCB$K_TAB_LEN = 132; literal UCB$K_LMPKTBYTS = 64; literal UCB$K_ERRDGBYTS = 180; literal UCB$K_LMBUFSIZ = 104; literal UCB$K_ERRDGSIZ = 220; literal UCB$M_RSP_FKB_IN_USE = %X'1'; literal UCB$S_PA_UCB = 1168; ! ! Skip the common UCB ! ! ! Define private PA fields ! macro UCB$L_INIFKBLK = 488,0,0,1 %; literal UCB$S_INIFKBLK = 48; ! Error fork block for handling ! severe adapter errors macro UCB$L_MFQEFKBLK = 536,0,0,1 %; literal UCB$S_MFQEFKBLK = 48; ! Pool allocation fork block for ! handling message free queue ! interrupts macro UCB$W_INCARN = 584,0,16,0 %; ! Last BVP incarnation number macro UCB$L_ADP = 588,0,32,1 %; ! Address of the ADP macro UCB$L_INIRETURN = 592,0,32,0 %; ! Initialization thread return ! address ! ! Fields used to link a port driver with the generic SCS port code. The port ! driver initializes these routines with pointers to hardware-dependent routines ! at unit initialization time. ! macro UCB$L_NDT = 600,0,32,0 %; ! Adapter hardware code macro UCB$B_DT = 604,0,8,0 %; ! Adapter device type macro UCB$V_LBDG = 605,0,1,0 %; ! Loopback datagram macro UCB$V_POLL = 605,1,1,0 %; ! Configuration polling macro UCB$V_LOCAL = 605,2,1,0 %; ! Local MSCP port (BVP ports) macro UCB$V_SINGLE_PATH = 605,3,1,0 %; ! Only one path available macro UCB$V_STORAGE = 605,4,1,0 %; ! Port is for remote storage only macro UCB$B_INI_FLAGS = 605,0,8,0 %; macro UCB$B_MSG_TYP = 608,0,8,0 %; ! Error log message type macro UCB$B_PDT_TYPE = 609,0,8,0 %; ! Type of PDT macro UCB$W_PDT_SIZE = 610,0,16,0 %; ! Size of PDT macro UCB$L_PPD_SIZE = 612,0,32,0 %; ! Size of the PPD header macro UCB$L_LSINDX = 616,0,32,1 %; ! Local store dump start address macro UCB$L_LSLENGTH = 620,0,32,0 %; ! Dump size in longwords macro UCB$L_PMC = 624,0,32,1 %; ! Address of the PMC register ! used to disable interrupts ! on port power-up macro UCB$L_REV_TABLE = 628,0,32,0 %; ! Port version table macro UCB$L_POWER_FAIL = 632,0,32,1 %; ! Power failure recovery routine macro UCB$L_INIT_PDT = 636,0,32,1 %; ! PDT initialization routine macro UCB$L_START_UCODE = 640,0,32,1 %; ! Microcode load and start routine macro UCB$L_ENB_INT = 644,0,32,1 %; ! Interrupt enable routine macro UCB$L_FORMAT_REV = 648,0,32,1 %; ! Verify port version routine macro UCB$L_TIMER = 652,0,32,1 %; ! Periodic wakeup routine macro UCB$L_POKE_PORT = 656,0,32,1 %; ! Poke the port's sanity timer macro UCB$L_INTERRUPT = 660,0,32,1 %; ! Adapter interrupt service routine macro UCB$L_STOP_UCODE = 664,0,32,1 %; ! Microcode shutdown routine macro UCB$L_UNMAP_PDT = 668,0,32,1 %; ! Unmap register pointers routine macro UCB$L_REG_DUMP = 672,0,32,1 %; ! Register dump routine macro UCB$L_REG_DISP = 676,0,32,1 %; ! Error log register display routine macro UCB$L_MEM_DUMP = 680,0,32,1 %; ! Memory dump routine macro UCB$L_RELEASE_PS = 684,0,32,1 %; ! Release port status register routine macro UCB$L_INS_COMQL = 692,0,32,0 %; ! Notify port of non-empty CMDQ0 macro UCB$L_INS_COMQH = 696,0,32,0 %; ! Notify port of non-empty CMDQ1 macro UCB$L_INS_DFREQ = 700,0,32,0 %; ! Notify port of non-empty DFQ macro UCB$L_INS_MFREQ = 704,0,32,0 %; ! Notify port of non-empty MFQ macro UCB$L_INS_COMQM = 708,0,32,0 %; macro UCB$L_INIT_ABLK = 712,0,32,0 %; macro UCB$L_CMPL_INT = 716,0,32,0 %; macro UCB$L_MISC_INT2 = 720,0,32,0 %; macro UCB$L_MSGFKBLK = 736,0,0,1 %; literal UCB$S_MSGFKBLK = 48; ! Fork block for starting ! error messages to operator macro UCB$T_OPA0_TEMP = 784,0,0,0 %; literal UCB$S_OPA0_TEMP = 24; ! Field used to store optional ! OPA0: error logging information ! (access to this field is also ! protected by UCB$V_MSGFKLOCK) macro UCB$B_LMEST = 808,0,8,0 %; ! Error subtype macro UCB$B_LMET = 809,0,8,0 %; ! Error type macro UCB$B_LMERTCNT = 810,0,8,0 %; ! Error retry count macro UCB$B_LMERTMAX = 811,0,8,0 %; ! Maximum error retry count macro UCB$W_LMERRCNT = 812,0,16,0 %; ! Accumulated errors macro UCB$N_LSADDR = 816,0,0,0 %; literal UCB$S_LSADDR = 6; ! Local station address macro UCB$N_LSID = 822,0,0,0 %; literal UCB$S_LSID = 6; ! Local station ID macro UCB$N_RSADDR = 828,0,0,0 %; literal UCB$S_RSADDR = 6; ! Remote station address macro UCB$N_RSID = 834,0,0,0 %; literal UCB$S_RSID = 6; ! Remote station ID macro UCB$L_CICMD = 840,0,32,0 %; ! CI packet command longword macro UCB$W_MSGBYTCNT = 844,0,16,0 %; ! CI packet byte count macro UCB$W_MSGPPDTYP = 846,0,16,0 %; ! CI packet PPD type macro UCB$T_MSGDATA = 848,0,0,0 %; literal UCB$S_MSGDATA = 64; ! CI packet data macro UCB$L_RSPFKBLK = 1088,0,0,1 %; literal UCB$S_RSPFKBLK = 48; ! Response Q fork block for thread ! that drains response Queue. macro UCB$L_RSP_STS = 1136,0,32,0 %; ! Resp Queue status mask macro UCB$V_RSP_FKB_IN_USE = 1136,0,1,0 %; ! Resp Q fork block in use ! it's own cache block. Place only static ! data in these fields if necessary as this ! cache block is in high demand on SMP systems. literal UCB$C_PALENGTH = 1168; literal UCB$C_PA_LENGTH = 1168; ! For SDA FORMAT literal UCB$S_PAUCBDEF = 1168; ! Old PAUCBDEF size name for compatibility literal UCB$M_PI_ENABLE = %X'1'; literal UCB$M_PI_FKB_BUSY = %X'2'; literal UCB$M_PI_TQE_BUSY = %X'4'; literal UCB$S_PI_UCB = 1376; ! ! Skip the common UCB plus the PA extension ! ! ! Define private PI fields ! macro UCB$B_PI_FKB = 1168,0,0,0 %; literal UCB$S_PI_FKB = 48; macro UCB$B_PI_TQE = 1216,0,0,0 %; literal UCB$S_PI_TQE = 64; macro UCB$Q_PI_TFQ = 1280,0,0,0 %; literal UCB$S_PI_TFQ = 8; macro UCB$L_PI_TFQ_FLINK = 1280,0,32,1 %; macro UCB$L_PI_TFQ_BLINK = 1284,0,32,1 %; macro UCB$Q_PI_TQ = 1288,0,0,0 %; literal UCB$S_PI_TQ = 8; macro UCB$L_PI_TQ_FLINK = 1288,0,32,1 %; macro UCB$L_PI_TQ_BLINK = 1292,0,32,1 %; macro UCB$Q_PI_IFQ = 1296,0,0,0 %; literal UCB$S_PI_IFQ = 8; macro UCB$L_PI_IFQ_FLINK = 1296,0,32,1 %; macro UCB$L_PI_IFQ_BLINK = 1300,0,32,1 %; macro UCB$Q_PI_IQ = 1304,0,0,0 %; literal UCB$S_PI_IQ = 8; macro UCB$L_PI_IQ_FLINK = 1304,0,32,1 %; macro UCB$L_PI_IQ_BLINK = 1308,0,32,1 %; macro UCB$L_PI_SVA = 1312,0,32,0 %; macro UCB$L_PI_SVPN = 1316,0,32,0 %; macro UCB$L_PI_SCRIPT = 1320,0,32,0 %; macro UCB$L_PI_TGT_SCRIPT = 1324,0,32,0 %; macro UCB$L_PI_DAT_SCRIPT = 1328,0,32,0 %; macro UCB$L_PI_INI_SCRIPT = 1332,0,32,0 %; macro UCB$L_PI_RL_STAT = 1336,0,32,0 %; macro UCB$L_PI_WL_DSP = 1340,0,32,0 %; macro UCB$L_PI_TGT_C710D = 1344,0,32,0 %; macro UCB$L_PI_INI_C710D = 1348,0,32,0 %; macro UCB$L_PI_CURR_SCRIPT = 1352,0,32,0 %; macro UCB$L_PI_DSA = 1356,0,32,0 %; macro UCB$L_PI_DSPS = 1360,0,32,0 %; macro UCB$L_PI_SCRATCH = 1364,0,32,0 %; macro UCB$L_PI_EXP_INT = 1368,0,32,0 %; macro UCB$V_PI_ENABLE = 1372,0,1,0 %; macro UCB$V_PI_FKB_BUSY = 1372,1,1,0 %; macro UCB$V_PI_TQE_BUSY = 1372,2,1,0 %; macro UCB$B_PI_FLAGS = 1372,0,8,0 %; literal UCB$C_PILENGTH = 1376; literal UCB$C_PI_LENGTH = 1376; ! For SDA FORMAT literal UCB$S_PIUCBDEF = 1376; ! Old PIUCBDEF size name for compatibility literal UCB$m_pb_open = %X'1'; literal UCB$m_pb_opening = %X'2'; literal UCB$m_pb_nip = %X'4'; literal UCB$m_pb_start = %X'8'; literal UCB$m_pb_aborted = %X'1'; literal UCB$m_pb_terminated = %X'2'; literal UCB$m_pb_rwf = %X'4'; literal UCB$m_pb_iwf = %X'8'; literal UCB$m_pb_smsd = %X'10'; literal UCB$K_A_end = 0; ! A_end node index literal UCB$K_B_end = 1; ! B_end node index literal UCB$C_PB_LENGTH = 1668; literal UCB$S_PB_UCB = 1672; ! ! Skip the common UCB plus the PA extension ! ! ! Define private PB fields; ! ! ! The following fields are only associated with the Admin Units. ! macro UCB$pq_pb_gnode_cbb = 1376,0,0,1 %; literal UCB$s_pb_gnode_cbb = 8; macro UCB$ps_pb_gnode_ucb_list = 1384,0,32,1 %; ! macro UCB$ps_pb_template_ucb = 1388,0,32,1 %; ! pointer to the template UCB macro UCB$r_pb_smci_section_id = 1392,0,0,0 %; literal UCB$s_pb_smci_section_id = 8; ! SMCI Section region id macro UCB$l_pb_status = 1400,0,32,0 %; macro UCB$ps_pb_tqe = 1404,0,32,1 %; macro UCB$ps_pb_idb = 1408,0,32,1 %; macro UCB$ps_pb_admin_ucb = 1412,0,32,1 %; macro UCB$ps_pb_discovery_tqe = 1416,0,32,1 %; macro UCB$l_pb_remote_gnode = 1420,0,32,0 %; macro UCB$q_pb_incarnation = 1424,0,0,0 %; literal UCB$s_pb_incarnation = 8; macro UCB$l_pb_chansts = 1432,0,32,0 %; ! channel status longword macro UCB$w_pb_chansts = 1432,0,16,0 %; ! channel status word macro UCB$v_pb_open = 1432,0,1,0 %; ! channel local end open macro UCB$v_pb_opening = 1432,1,1,0 %; ! ready to go to open state macro UCB$v_pb_nip = 1432,2,1,0 %; ! negotiations in progress macro UCB$v_pb_start = 1432,3,1,0 %; ! starting, negotiations macro UCB$w_pb_chanerr = 1434,0,16,0 %; ! channel status error word macro UCB$v_pb_aborted = 1434,0,1,0 %; ! we were told to die macro UCB$v_pb_terminated = 1434,1,1,0 %; ! we kill ourselves macro UCB$v_pb_rwf = 1434,2,1,0 %; ! remque workq failure macro UCB$v_pb_iwf = 1434,3,1,0 %; ! insque workq failure macro UCB$v_pb_smsd = 1434,4,1,0 %; ! sh. mem. shutting down macro UCB$l_pb_lnode_idx = 1436,0,32,0 %; ! local end index A or B macro UCB$l_pb_rnode_idx = 1440,0,32,0 %; ! remote end index A or B macro UCB$ps_pb_fkb = 1444,0,32,1 %; ! Pointer interrupt fork block macro UCB$pq_pb_nb = 1448,0,0,1 %; literal UCB$s_pb_nb = 8; ! negotiation section pointer macro UCB$l_pb_nb_len = 1456,0,32,1 %; macro UCB$ps_pb_smh = 1460,0,32,1 %; ! channel handle pointer macro UCB$ps_pb_smh_self = 1464,0,32,1 %; ! channel handle pointer self macro UCB$l_pb_gnode = 1468,0,0,0 %; literal UCB$s_pb_gnode = 8; ! gNode number A,B macro UCB$l_pb_node_block = 1476,0,0,0 %; literal UCB$s_pb_node_block = 8; ! gNode number A,B macro UCB$l_pb_workq = 1484,0,0,0 %; literal UCB$s_pb_workq = 16; ! Other end work queue pointer macro UCB$l_pb_freeq = 1500,0,32,0 %; ! Local-end Harter free head macro UCB$r_pb_reg_id = 1504,0,0,0 %; literal UCB$s_pb_reg_id = 8; ! Channel region id macro UCB$l_pb_msg_nworkq = 1512,0,32,0 %; ! Number of work queues macro UCB$l_pb_msg_buffers = 1516,0,32,0 %; ! Number of buffers macro UCB$l_pb_msg_dg_size = 1520,0,32,0 %; ! buffer size macro UCB$l_pb_msg_scshdr_size = 1524,0,32,0 %; ! scs/ppd header macro UCB$l_pb_msg_smwe_size = 1528,0,32,0 %; ! SMWE header macro UCB$l_pb_msg_smch_size = 1532,0,32,0 %; ! SMCH header macro UCB$l_pb_msg_smnd_size = 1536,0,32,0 %; ! SMND header macro UCB$l_pb_msg_netsize = 1540,0,32,0 %; ! decnet header size macro UCB$l_pb_channel_add = 1544,0,32,0 %; ! number of channels for expansions macro UCB$l_dbg = 1548,0,0,0 %; literal UCB$s_dbg = 120; ! ! SNAPSHOT SERVICES (aka SnappyDisk) UCB EXTENSION ! literal UCB$S_SD_UCB = 600; macro UCB$Q_SD_EXPORT_QUEUE = 552,0,0,0 %; literal UCB$S_SD_EXPORT_QUEUE = 8; ! Device queue link macro UCB$PS_SD_SDCB = 560,0,32,1 %; ! snappy disk control block macro UCB$PS_SD_POOL_CONFIG = 564,0,32,1 %; ! Pointer to POOL_CONFIG lock macro UCB$L_SD_FAMILY_NUMBER = 568,0,32,0 %; ! Family number macro UCB$L_SD_SNAP_NUMBER = 572,0,32,0 %; ! Snap number macro UCB$L_SD_DEV_LOCKID = 576,0,32,0 %; ! Device Lock Id macro UCB$L_SD_UID_LOCKID = 580,0,32,0 %; ! UID Lock Id macro UCB$L_SD_SPARE1 = 584,0,32,0 %; ! Spare field macro UCB$L_SD_SPARE2 = 588,0,32,0 %; ! Spare field macro UCB$L_SD_SPARE3 = 592,0,32,0 %; ! Spare field macro UCB$L_SD_SPARE4 = 596,0,32,0 %; ! Spare field literal UCB$C_SD_LENGTH = 600; ! For SDA FORMAT literal UCB$S_SDUCBDEF = 600; MACRO UCB$PS_SDMB = UCB$L_DCCB %; ! ! SCSI/FibreChannel Disk Class Driver UCB Extension ! literal UCB$M_REMOVABLE = %X'1'; literal UCB$M_FIRST_ATTN_SEEN = %X'2'; literal UCB$M_SPINUP_INPROG = %X'4'; literal UCB$M_DISCONNECT = %X'8'; literal UCB$M_SYNCHRONOUS = %X'10'; literal UCB$M_MODE_SENSE_PAG1 = %X'20'; literal UCB$M_MODE_SENSE_PAG10 = %X'40'; literal UCB$M_DISABL_ERRLOG = %X'80'; literal UCB$M_OUT_OF_REV = %X'100'; literal UCB$M_HWL = %X'200'; literal UCB$M_FLOPPY = %X'400'; literal UCB$M_FORMAT = %X'800'; literal UCB$M_NOREASSIGN = %X'1000'; literal UCB$M_DD_BYPASS = %X'2000'; literal UCB$M_HBS_CHECK = %X'4000'; literal UCB$M_FLOPPY_MEDIA = %X'18000'; literal UCB$M_CDROM = %X'20000'; literal UCB$M_CD_VALID = %X'40000'; literal UCB$M_RAID = %X'80000'; literal UCB$M_PORT_CMDQ = %X'100000'; literal UCB$M_CMDQ = %X'200000'; literal UCB$M_OPTICAL = %X'400000'; literal UCB$M_WORM = %X'800000'; literal UCB$M_DDR = %X'1000000'; literal UCB$M_PORT_AEN = %X'2000000'; literal UCB$M_PORT_AUTOSENSE = %X'4000000'; literal UCB$M_TENBYTE = %X'8000000'; literal UCB$M_CLUSQ = %X'10000000'; literal UCB$M_HFAILOV = %X'20000000'; literal UCB$M_NO_FUA = %X'40000000'; literal UCB$M_NO_10BYTE_RW = %X'80000000'; literal UCB$M_CB_NOCMDQ = %X'1'; literal UCB$M_CB_INIT = %X'2'; literal UCB$M_CB_BBR_IN_PROG = %X'4'; literal UCB$M_CB_MNTVERIP = %X'8'; literal UCB$M_CB_KP_STARTIO = %X'10'; literal UCB$M_CB_CHECK_CONDITION = %X'20'; literal UCB$M_CB_QUEUE_FULL_EVNT = %X'40'; literal UCB$M_CB_BUS_RESET = %X'80'; literal UCB$M_CB_NO_SEND_CREDITS = %X'100'; literal UCB$M_CB_NO_CMD_BITS = %X'200'; literal UCB$M_CB_SINGLE_RW = %X'400'; literal UCB$M_CB_SINGLE_DC = %X'800'; literal UCB$M_CB_SINGLE_DSE = %X'1000'; literal UCB$M_CB_FORCE_ERROR = %X'2000'; literal UCB$M_CB_NOP = %X'4000'; literal UCB$M_CB_AVAILABLE = %X'8000'; literal UCB$M_CB_UNLOAD = %X'10000'; literal UCB$M_CB_PACKACK = %X'20000'; literal UCB$M_CB_DIAGNOSE = %X'40000'; literal UCB$M_CB_FORMAT = %X'80000'; literal UCB$M_CB_AUDIO = %X'100000'; literal UCB$M_CB_BUSY = %X'200000'; literal UCB$M_CB_LOCAL_DRAIN = %X'400000'; literal UCB$M_CB_LINK = %X'800000'; literal UCB$M_CB_PATH_VERIFY = %X'1000000'; literal UCB$K_DK_NUM_LONGWORDS_DIAGNOSE = 6; literal UCB$M_DTESET = %X'1'; literal UCB$M_XPLOOK = %X'2'; literal UCB$M_MULTIBUS_CAP = %X'4'; literal UCB$M_MULTIBUS_ENA = %X'8'; literal UCB$M_SECTORS_VIA_MS = %X'10'; literal UCB$M_TRK_CYL_VIA_MS = %X'20'; literal UCB$M_PR_PREEMPT = %X'80'; literal UCB$M_NOTREADY = %X'100'; literal UCB$M_CD_2K_BLOCKSIZE = %X'200'; literal UCB$M_DK_FIBRE = %X'1'; literal UCB$M_DK_HSG = %X'2'; literal UCB$M_DK_HSV = %X'4'; literal UCB$M_DK_XP = %X'8'; literal UCB$M_DK_ASYM_ACC_STATE = %X'F0000'; literal UCB$M_DK_TPG_NUM_VALID = %X'100000'; literal UCB$M_DK_RPT_TPG_SUPP = %X'200000'; literal UCB$M_DK_SET_TPG_SUPP = %X'400000'; literal UCB$M_DK_SAS = %X'1'; literal UCB$M_DK_SAS_DEV = %X'2'; literal UCB$M_DK_SAS_SATA_DEV = %X'4'; literal UCB$M_DK_SAS_IR_VOL = %X'8'; literal UCB$M_DK_SAS_RAID_VOL = %X'10'; literal UCB$C_DK_UCBLEN = 1472; literal UCB$C_DK_LENGTH = 1472; ! (For SDA) literal UCB$S_DK_UCB = 1472; macro UCB$L_DK_FLAGS = 608,0,32,0 %; macro UCB$V_REMOVABLE = 608,0,1,0 %; ! Media is removeable macro UCB$V_FIRST_ATTN_SEEN = 608,1,1,0 %; ! First UNIT ATTENTION CHECK CONDITION has been seen macro UCB$V_SPINUP_INPROG = 608,2,1,0 %; ! Disk is spinning up if set macro UCB$V_DISCONNECT = 608,3,1,0 %; ! Device supports (bus-level) disconnects macro UCB$V_SYNCHRONOUS = 608,4,1,0 %; ! Device supports synchronous data transfers macro UCB$V_MODE_SENSE_PAG1 = 608,5,1,0 %; ! macro UCB$V_MODE_SENSE_PAG10 = 608,6,1,0 %; ! macro UCB$V_DISABL_ERRLOG = 608,7,1,0 %; ! macro UCB$V_OUT_OF_REV = 608,8,1,0 %; ! macro UCB$V_HWL = 608,9,1,0 %; ! Hardware Write Locked macro UCB$V_FLOPPY = 608,10,1,0 %; ! This is a floppy disk macro UCB$V_FORMAT = 608,11,1,0 %; ! macro UCB$V_NOREASSIGN = 608,12,1,0 %; ! macro UCB$V_DD_BYPASS = 608,13,1,0 %; ! macro UCB$V_HBS_CHECK = 608,14,1,0 %; ! macro UCB$V_FLOPPY_MEDIA = 608,15,2,0 %; literal UCB$S_FLOPPY_MEDIA = 2; ! macro UCB$V_CDROM = 608,17,1,0 %; ! macro UCB$V_CD_VALID = 608,18,1,0 %; ! macro UCB$V_RAID = 608,19,1,0 %; ! macro UCB$V_PORT_CMDQ = 608,20,1,0 %; ! macro UCB$V_CMDQ = 608,21,1,0 %; ! Disk supports SCSI Command Queuing macro UCB$V_OPTICAL = 608,22,1,0 %; ! Optical disk macro UCB$V_WORM = 608,23,1,0 %; ! Write-Once, Read-Many macro UCB$V_DDR = 608,24,1,0 %; ! macro UCB$V_PORT_AEN = 608,25,1,0 %; ! Underlying port supports Asynchronous Event Notification macro UCB$V_PORT_AUTOSENSE = 608,26,1,0 %; ! Underlying port performs REQUEST SENSE automatically macro UCB$V_TENBYTE = 608,27,1,0 %; ! macro UCB$V_CLUSQ = 608,28,1,0 %; ! macro UCB$V_HFAILOV = 608,29,1,0 %; ! macro UCB$V_NO_FUA = 608,30,1,0 %; ! Forced Unit Access not supported macro UCB$V_NO_10BYTE_RW = 608,31,1,0 %; ! Device does not support 10-byte Reads or Writes macro UCB$L_DK_CLASS_BUSY = 612,0,32,0 %; ! Class Busy bits show details about why UCB$V_BSY is set macro UCB$V_CB_NOCMDQ = 612,0,1,0 %; ! macro UCB$V_CB_INIT = 612,1,1,0 %; ! macro UCB$V_CB_BBR_IN_PROG = 612,2,1,0 %; ! macro UCB$V_CB_MNTVERIP = 612,3,1,0 %; ! macro UCB$V_CB_KP_STARTIO = 612,4,1,0 %; ! macro UCB$V_CB_CHECK_CONDITION = 612,5,1,0 %; ! macro UCB$V_CB_QUEUE_FULL_EVNT = 612,6,1,0 %; ! macro UCB$V_CB_BUS_RESET = 612,7,1,0 %; ! macro UCB$V_CB_NO_SEND_CREDITS = 612,8,1,0 %; ! macro UCB$V_CB_NO_CMD_BITS = 612,9,1,0 %; ! macro UCB$V_CB_SINGLE_RW = 612,10,1,0 %; ! macro UCB$V_CB_SINGLE_DC = 612,11,1,0 %; ! macro UCB$V_CB_SINGLE_DSE = 612,12,1,0 %; ! macro UCB$V_CB_FORCE_ERROR = 612,13,1,0 %; ! macro UCB$V_CB_NOP = 612,14,1,0 %; ! macro UCB$V_CB_AVAILABLE = 612,15,1,0 %; ! macro UCB$V_CB_UNLOAD = 612,16,1,0 %; ! macro UCB$V_CB_PACKACK = 612,17,1,0 %; ! macro UCB$V_CB_DIAGNOSE = 612,18,1,0 %; ! macro UCB$V_CB_FORMAT = 612,19,1,0 %; ! macro UCB$V_CB_AUDIO = 612,20,1,0 %; ! macro UCB$V_CB_BUSY = 612,21,1,0 %; ! macro UCB$V_CB_LOCAL_DRAIN = 612,22,1,0 %; ! macro UCB$V_CB_LINK = 612,23,1,0 %; ! macro UCB$V_CB_PATH_VERIFY = 612,24,1,0 %; ! macro UCB$R_DK_IRP_LIST_UNION = 616,0,0,0 %; literal UCB$S_DK_IRP_LIST_UNION = 8; ! NormalPath Active-IRP list macro UCB$Q_DK_IRP_LIST = 616,0,0,0 %; literal UCB$S_DK_IRP_LIST = 8; ! macro UCB$R_DK_ACTIVE_IRP_QUEUE = 616,0,0,0 %; literal UCB$S_DK_ACTIVE_IRP_QUEUE = 8; ! macro UCB$PS_DK_ACTIVE_IRP_QFL = 616,0,32,1 %; ! macro UCB$PS_DK_ACTIVE_IRP_QBL = 620,0,32,1 %; ! ! ! macro UCB$L_DK_FLUSH_IOQFL = 624,0,32,1 %; ! macro UCB$L_DK_FLUSH_IOQBL = 628,0,32,1 %; ! macro UCB$R_DK_DC_WAIT_UNION = 632,0,0,0 %; literal UCB$S_DK_DC_WAIT_UNION = 8; ! DataCheck Wait Queue macro UCB$Q_DK_DC_WAIT_LIST = 632,0,0,0 %; literal UCB$S_DK_DC_WAIT_LIST = 8; ! macro UCB$R_DK_DC_WAIT_QUEUE = 632,0,0,0 %; literal UCB$S_DK_DC_WAIT_QUEUE = 8; ! macro UCB$PS_DK_DC_WAIT_QFL = 632,0,32,1 %; ! macro UCB$PS_DK_DC_WAIT_QBL = 636,0,32,1 %; ! ! ! macro UCB$R_DK_DRAIN_UNION = 640,0,0,0 %; literal UCB$S_DK_DRAIN_UNION = 8; ! Queue of SCDRPs waiting for all I/O in front of them to drain macro UCB$Q_DK_DRAIN_LIST = 640,0,0,0 %; literal UCB$S_DK_DRAIN_LIST = 8; ! macro UCB$R_DK_DRAIN_QUEUE = 640,0,0,0 %; literal UCB$S_DK_DRAIN_QUEUE = 8; ! macro UCB$PS_DK_DRAIN_QFL = 640,0,32,1 %; ! macro UCB$PS_DK_DRAIN_QBL = 644,0,32,1 %; ! ! ! macro UCB$IS_DK_DRAIN_COUNT = 648,0,32,1 %; ! Number of SCDRPs on the Drain Queue macro UCB$L_DK_QUEUED_IO_COUNT = 652,0,32,1 %; ! Number of IRPs on the Active IRP list macro UCB$PS_DK_SCDRP = 656,0,32,1 %; ! macro UCB$PS_DK_UNITINIT_KPB = 660,0,32,1 %; ! macro UCB$PS_DK_SCDT = 664,0,32,1 %; ! SCSI Connection Descriptor Table address macro UCB$Q_DK_CUR_LBN_64 = 672,0,0,0 %; literal UCB$S_DK_CUR_LBN_64 = 8; ! Current LBN (64-bit) macro UCB$L_DK_CUR_LBN = 672,0,32,0 %; ! (32-bit) macro UCB$L_DK_FAIRNESS_CNT = 680,0,32,1 %; ! macro UCB$L_DK_HW_REV = 684,0,32,0 %; ! macro UCB$L_DK_ERROR_TYPE = 688,0,32,0 %; ! macro UCB$L_DK_ERR_MASK = 692,0,32,0 %; ! macro UCB$L_DK_VMS_STATUS = 696,0,32,0 %; ! macro UCB$L_DK_DISABLE_DDR = 700,0,32,0 %; macro UCB$L_DK_INITMO = 704,0,32,0 %; ! macro UCB$PS_DK_AUCB_ADDR = 708,0,32,1 %; ! macro UCB$PS_DK_FORMAT_PARAM = 712,0,32,1 %; ! macro UCB$PS_DK_SAVE_CONN_CHAR = 716,0,32,1 %; ! macro UCB$R_DK_DIAGNOSE = 720,0,0,0 %; literal UCB$S_DK_DIAGNOSE = 24; macro UCB$W_DK_READL_LEN = 744,0,16,1 %; ! macro UCB$W_DK_PHASE_TMO = 746,0,16,1 %; ! Phase-Change Timeout in seconds macro UCB$W_DK_DISC_TMO = 748,0,16,1 %; ! Disconnect Timeout in seconds macro UCB$W_DK_BLOCK_SIZE = 750,0,16,1 %; ! Block size in bytes macro UCB$B_DK_LUN = 752,0,8,1 %; ! Logical Unit Number macro UCB$B_DK_SEEK_DIR = 753,0,8,1 %; ! macro UCB$B_DK_SCSI_VERSION = 754,0,8,1 %; ! macro UCB$B_DK_RW_RETRY = 755,0,8,1 %; ! macro UCB$B_DK_REASSIGN_RETRY = 756,0,8,1 %; ! macro UCB$B_DK_REWRITE_RETRY = 757,0,8,1 %; ! macro UCB$B_DK_READY_RETRY = 758,0,8,1 %; ! ! For CD-ROMS, Sub-Channel Q - Media Catalog Data (UPC) macro UCB$B_DK_MCN_SCDATA = 759,0,0,1 %; literal UCB$S_DK_MCN_SCDATA = 32; macro UCB$R_DK_SENSE_INFO = 792,0,0,1 %; literal UCB$S_DK_SENSE_INFO = 10; macro UCB$B_DK_SENSE_LEN = 802,0,16,1 %; literal UCB$S_DK_SENSE_LEN = 2; ! Error Recovery parameters macro UCB$R_DK_RECOV_PAR = 804,0,0,1 %; literal UCB$S_DK_RECOV_PAR = 16; ! Error Recovery changeable parameters macro UCB$R_DK_RECOV_CPAR = 820,0,0,1 %; literal UCB$S_DK_RECOV_CPAR = 16; ! Control Mode parameters macro UCB$R_DK_CTRL_MODE = 836,0,0,1 %; literal UCB$S_DK_CTRL_MODE = 8; ! Control Mode changeable parameters macro UCB$R_DK_CTRL_MODE_CPAR = 844,0,0,1 %; literal UCB$S_DK_CTRL_MODE_CPAR = 8; macro UCB$L_DK_QDEPTH = 852,0,32,1 %; ! Current maximum queue depth for this device (NormalPath) macro UCB$L_DK_QDEPTH_TURNS = 856,0,32,1 %; ! How many times queue depth has been changed macro UCB$L_DK_READ_COUNT = 860,0,32,1 %; ! Number of NormalPath reads done macro UCB$L_DK_WRITE_COUNT = 864,0,32,1 %; ! Number of NormalPath writes done macro UCB$L_DK_OTHER_COUNT = 868,0,32,1 %; ! Number of non-Read & non-Write I/O functions macro UCB$L_DK_FP_RW_COUNT = 872,0,32,1 %; ! Number of FastPath I/Os (R/W implied) macro UCB$L_DK_FP_ERR_COUNT = 876,0,32,1 %; ! Number of other-than SS$_CLASSUPER FastPath completions macro UCB$L_DK_READ_XLEN_HIST = 880,0,32,1 %; ! Pointer to Read histogram pool macro UCB$L_DK_WRITE_XLEN_HIST = 884,0,32,1 %; ! Pointer to Write histogram pool macro UCB$L_DK_XLEN_HIST = 888,0,32,1 %; ! Pointer to total histogram pool macro UCB$L_DK_XLEN_HIST_CYCLE = 892,0,32,1 %; ! # I/Os per histogram turnover macro UCB$PS_DK_BUSY_BIT_IRP = 896,0,32,1 %; ! Also referred to as the Golden IRP macro UCB$L_DK_TOP_OF_RING = 900,0,32,1 %; ! Pointer to first byte of ring buffer macro UCB$L_DK_RING_POINTER = 904,0,32,1 %; ! Pointer to next ring buffer entry macro UCB$L_DK_RING_COUNTER = 908,0,32,1 %; ! Number of ring buffer entries left before wrapping is required ! These fields count reasons for our returning SS$_MEDOFL to help us diagnose excessive Mount Verifies macro UCB$L_DK_TIMEOUT = 912,0,32,1 %; ! I/O Timed Out macro UCB$L_DK_DRVERR = 916,0,32,1 %; ! SS$_DRVERR returned from port macro UCB$L_DK_CTRLERR = 920,0,32,1 %; ! SS$_CTRLERR ... macro UCB$L_DK_DEVOFFLINE = 924,0,32,1 %; ! SS$_DEVOFFLINE ... macro UCB$L_DK_UNIT_ATTENTION = 928,0,32,1 %; ! Unit Attention CHECK CONDITION macro UCB$L_DK_VENDOR_SPECIFIC = 932,0,32,1 %; ! macro UCB$L_DK_COPY_ABORTED = 936,0,32,1 %; ! macro UCB$L_DK_NOT_READY = 940,0,32,1 %; ! macro UCB$L_DK_RESERVED = 944,0,32,1 %; ! macro UCB$L_DK_MEDOFL = 948,0,32,1 %; ! macro UCB$L_DK_UNEXPLAINED = 952,0,32,1 %; ! macro UCB$L_DK_INQUIRY_DATA = 956,0,0,1 %; literal UCB$S_DK_INQUIRY_DATA = 36; ! Overflow from DK_FLAGS macro UCB$L_DK_FLAGS2 = 992,0,32,0 %; macro UCB$V_DTESET = 992,0,1,0 %; ! macro UCB$V_XPLOOK = 992,1,1,0 %; ! macro UCB$V_MULTIBUS_CAP = 992,2,1,0 %; ! macro UCB$V_MULTIBUS_ENA = 992,3,1,0 %; ! macro UCB$V_SECTORS_VIA_MS = 992,4,1,0 %; ! macro UCB$V_TRK_CYL_VIA_MS = 992,5,1,0 %; ! macro UCB$V_PR_PREEMPT = 992,7,1,0 %; ! Persistent Reservation Preemption in Progress macro UCB$V_NOTREADY = 992,8,1,0 %; ! Last command returned NOT_READY key macro UCB$V_CD_2K_BLOCKSIZE = 992,9,1,0 %; ! CD/DVD using 2K block mode ! SCSIPATH structure macro UCB$R_DK_PATH_INFO = 1000,0,0,1 %; literal UCB$S_DK_PATH_INFO = 24; ! Obsolete (X-116) macro UCB$R_DK_OLD_DSPLYPATH_ID = 1024,0,0,1 %; literal UCB$S_DK_OLD_DSPLYPATH_ID = 28; ! Obsolete (X-116) macro UCB$L_DK_GET_PATH_INFO_RETRIES = 1052,0,32,1 %; ! ! FastPath Attention flag - set by NormalPath code (while holding ! the portlock) to get the FastPath code's attention macro UCB$Q_DK_FP_ATTN = 1056,0,0,0 %; literal UCB$S_DK_FP_ATTN = 8; ! FibreChannel-disk boolean macro UCB$Q_DK_FIBRE = 1064,0,0,0 %; literal UCB$S_DK_FIBRE = 8; macro UCB$V_DK_FIBRE = 1064,0,1,0 %; macro UCB$V_DK_HSG = 1064,1,1,0 %; macro UCB$V_DK_HSV = 1064,2,1,0 %; macro UCB$V_DK_XP = 1064,3,1,0 %; ! Queue of active FastPath IRPs, synchronized with port spinlock macro UCB$R_DK_FP_IRP_LIST_UNION = 1072,0,0,0 %; literal UCB$S_DK_FP_IRP_LIST_UNION = 8; ! macro UCB$Q_DK_FP_IRP_LIST = 1072,0,0,0 %; literal UCB$S_DK_FP_IRP_LIST = 8; ! macro UCB$R_DK_FP_IRP_QUEUE = 1072,0,0,0 %; literal UCB$S_DK_FP_IRP_QUEUE = 8; ! macro UCB$PS_DK_FP_IRP_QFL = 1072,0,32,1 %; ! macro UCB$PS_DK_FP_IRP_QBL = 1076,0,32,1 %; ! ! ! ! Count of active FastPath IRPs, synchronized with port spinlock macro UCB$Q_DK_FP_IRP_COUNT = 1080,0,0,0 %; literal UCB$S_DK_FP_IRP_COUNT = 8; ! ! FastPath Start I/O flag, synchronized with fork spinlock, used to avoid excesssive stack depth and avoid FORKs macro UCB$Q_DK_FP_START_IO = 1088,0,0,0 %; literal UCB$S_DK_FP_START_IO = 8; ! UCB$L_DISC_TMO + UCB$L_PHASE_TMO summed in this field to avoid unnecessary per-I/O operation macro UCB$PS_DK_SPL_FORK = 1096,0,32,1 %; macro UCB$L_DK_FP_TIMEOUT = 1100,0,32,0 %; macro UCB$PS_DK_SPL_PORT = 1104,0,32,1 %; macro UCB$L_DK_LOG_FLAG = 1108,0,32,0 %; ! Logging flags/controls macro UCB$PQ_DK_DATACHECK_SPTE = 1112,0,0,1 %; literal UCB$S_DK_DATACHECK_SPTE = 8; ! per-ucb S2 space spte macro UCB$PQ_DK_DATACHECK_SVA = 1120,0,0,1 %; literal UCB$S_DK_DATACHECK_SVA = 8; ! and her address macro UCB$L_DK_IRP_WAIT_4_KPB = 1128,0,32,1 %; ! If nonzero, IRP in "fork wait" for a KPB macro UCB$PS_DK_QDEPTH_TABLE = 1132,0,32,1 %; ! Pointer to optional Size vs. Maximum queue depth table macro UCB$PS_DK_QUORUM_IRP = 1136,0,32,1 %; ! Pointer to pending Quorum IRP macro UCB$PQ_DK_BUFFIO_SPTE = 1144,0,0,1 %; literal UCB$S_DK_BUFFIO_SPTE = 8; ! Pointer to temp DMA Buffer PTE macro UCB$PQ_DK_BUFFIO_SVA = 1152,0,0,1 %; literal UCB$S_DK_BUFFIO_SVA = 8; ! Pointer to temp DMA Buffer macro UCB$L_DK_TPG_INFO = 1160,0,32,0 %; ! Target port group info for Active-Active macro UCB$W_DK_TPG_NUM = 1160,0,16,1 %; ! Target port group number macro UCB$V_DK_ASYM_ACC_STATE = 1160,16,4,0 %; literal UCB$S_DK_ASYM_ACC_STATE = 4; ! Asymmetric access state macro UCB$V_DK_TPG_NUM_VALID = 1160,20,1,0 %; ! TPG num is valid macro UCB$V_DK_RPT_TPG_SUPP = 1160,21,1,0 %; ! RPT TARG PORT GRPS cmd supported macro UCB$V_DK_SET_TPG_SUPP = 1160,22,1,0 %; ! SET TARG PORT GRPS cmd supported macro UCB$L_DK_UA_RING_POINTER = 1164,0,32,1 %; ! Used by SDA's MKLOG ! Display path size for DK, MK, and GK devices (X-116) macro UCB$R_DK_DSPLYPATH_ID = 1168,0,0,1 %; literal UCB$S_DK_DSPLYPATH_ID = 292; ! Moved here in X-116 ! SAS device boolean macro UCB$Q_DK_SAS = 1464,0,0,0 %; literal UCB$S_DK_SAS = 8; macro UCB$V_DK_SAS = 1464,0,1,0 %; macro UCB$V_DK_SAS_DEV = 1464,1,1,0 %; macro UCB$V_DK_SAS_SATA_DEV = 1464,2,1,0 %; macro UCB$V_DK_SAS_IR_VOL = 1464,3,1,0 %; macro UCB$V_DK_SAS_RAID_VOL = 1464,4,1,0 %; ! ! SCSI Tape Class Driver UCB Extension ! literal UCB$S_MK_UCB = 1320; macro UCB$B_MK_LCL_TAPE = 0,0,0,1 %; literal UCB$S_MK_LCL_TAPE = 536; ! Standard tape UCB fields macro UCB$R_MK_OLD_DSPLYPATH_ID = 976,0,0,1 %; literal UCB$S_MK_OLD_DSPLYPATH_ID = 28; ! Obsolete (X-116) macro UCB$L_MK_RING_POINTER = 1012,0,32,1 %; ! Used by SDA's MKLOG macro UCB$L_MK_LOG_FLAG = 1016,0,32,0 %; ! Used by SDA's MKLOG macro UCB$L_MK_UA_RING_POINTER = 1020,0,32,1 %; ! Used by SDA's MKLOG macro UCB$R_MK_DSPLYPATH_ID = 1024,0,0,1 %; literal UCB$S_MK_DSPLYPATH_ID = 292; ! Pathname, used by SDA's MKLOG (moved in X-116) ! ! SCSI Generic Class Driver UCB Extension ! literal UCB$S_GK_UCB = 1008; macro UCB$R_GK_OLD_DSPLYPATH_ID = 680,0,0,1 %; literal UCB$S_GK_OLD_DSPLYPATH_ID = 28; ! Obsolete (X-116) macro UCB$L_GK_RING_POINTER = 708,0,32,1 %; ! Used by SDA's GKLOG macro UCB$L_GK_LOG_FLAG = 712,0,32,0 %; ! Used by SDA's GKLOG macro UCB$R_GK_DSPLYPATH_ID = 716,0,0,1 %; literal UCB$S_GK_DSPLYPATH_ID = 292; ! Pathname, used by SDA's GKLOG (moved in X-116) ! ! DECram (MD) Disk Class Driver UCB Extension ! literal UCB$m_md_memory = %X'1'; literal UCB$m_md_ucb_fip = %X'2'; literal UCB$m_md_updatingfile = %X'4'; literal UCB$m_md_intio = %X'8'; literal UCB$m_md_dtregion = %X'10'; literal UCB$m_md_dtentry_cre = %X'20'; literal UCB$m_md_dtentry_mod = %X'40'; literal UCB$m_md_updatinghome = %X'80'; literal UCB$m_md_updatingfmt = %X'100'; literal UCB$m_md_rsvd1 = %X'200'; literal UCB$K_MD_LENGTH = 964; literal UCB$C_MD_LENGTH = 964; literal UCB$S_MD_UCB = 968; macro UCB$v_md_memory = 608,0,1,0 %; ! memory region allocated macro UCB$v_md_ucb_fip = 608,1,1,0 %; ! io$_format in progress macro UCB$v_md_updatingfile = 608,2,1,0 %; ! mdrecover.dat update in progress macro UCB$v_md_intio = 608,3,1,0 %; ! internal IO to create new disk macro UCB$v_md_dtregion = 608,4,1,0 %; ! disktab region created macro UCB$v_md_dtentry_cre = 608,5,1,0 %; ! disktab entry created macro UCB$v_md_dtentry_mod = 608,6,1,0 %; ! disktab entry modified macro UCB$v_md_updatinghome = 608,7,1,0 %; ! homeblock update in progress macro UCB$v_md_updatingfmt = 608,8,1,0 %; ! format update in progress macro UCB$v_md_rsvd1 = 608,9,1,0 %; ! macro UCB$L_MD_STATUS = 608,0,32,0 %; macro UCB$l_md_lbn = 612,0,32,0 %; ! irp$l_media macro UCB$l_md_homelbn = 616,0,32,0 %; ! homeblock LBN macro UCB$l_md_ramfunction = 620,0,32,0 %; ! irp$l_func macro UCB$l_md_ramcontrol = 624,0,32,0 %; ! irp$q_qio_p2 (bits 0-31) macro UCB$l_md_ramrad = 628,0,32,0 %; ! irp$l_qio_p6 macro UCB$q_md_ramcapacity = 632,0,0,0 %; literal UCB$s_md_ramcapacity = 8; ! irp$q_qio_p1 macro UCB$pq_md_disktab_sva = 640,0,0,1 %; literal UCB$s_md_disktab_sva = 8; ! disktab section address macro UCB$pq_md_disktab_pte = 648,0,0,1 %; literal UCB$s_md_disktab_pte = 8; ! debug macro UCB$r_md_disktab_shm_reg_id = 656,0,0,0 %; literal UCB$s_md_disktab_shm_reg_id = 8; ! disktab gsection region id macro UCB$l_md_disktab_len = 664,0,32,0 %; ! disktab gsection length macro UCB$l_md_frsterr_status = 668,0,32,0 %; ! last error status macro UCB$pq_md_disk_sva = 672,0,0,1 %; literal UCB$s_md_disk_sva = 8; ! disk section address macro UCB$pq_md_disk_pte = 680,0,0,1 %; literal UCB$s_md_disk_pte = 8; ! disk section address macro UCB$r_md_disk_reg_id = 688,0,0,0 %; literal UCB$s_md_disk_reg_id = 8; ! disk gsection region id macro UCB$l_md_disk_len = 696,0,32,0 %; ! disk length in pages macro UCB$l_md_lasterr_status = 700,0,32,0 %; ! last error status macro UCB$pq_md_user_buffer_sva = 704,0,0,1 %; literal UCB$s_md_user_buffer_sva = 8; ! user buffer VA macro UCB$pq_md_user_buffer_pte = 712,0,0,1 %; literal UCB$s_md_user_buffer_pte = 8; ! user buffer pte macro UCB$pq_md_gnodes_cbb = 720,0,0,1 %; literal UCB$s_md_gnodes_cbb = 8; ! gnode CBB bitmap pointer macro UCB$l_md_pfns = 728,0,32,0 %; ! number of pfns allocated macro UCB$L_md_create_disk_link = 732,0,32,1 %; ! link to next disk to create macro UCB$r_md_lksb_lock = 736,0,0,0 %; literal UCB$s_md_lksb_lock = 20; ! embebed Lock LKSB macro UCB$w_md_lock_status = 736,0,16,0 %; ! lock status macro UCB$w_md_lock_rsvd = 738,0,16,0 %; macro UCB$l_md_lock_lockid = 740,0,32,0 %; ! lock lock ID macro UCB$t_md_lock_valblk = 744,0,0,0 %; literal UCB$s_md_lock_valblk = 12; ! lock value block macro UCB$t_md_volname = 756,0,0,0 %; literal UCB$s_md_volname = 12; ! disk label macro UCB$r_md_lksb_perm = 768,0,0,0 %; literal UCB$s_md_lksb_perm = 20; ! embebed Perm LKSB macro UCB$w_md_perm_status = 768,0,16,0 %; ! perm status macro UCB$w_md_perm_rsvd = 770,0,16,0 %; macro UCB$l_md_perm_lockid = 772,0,32,0 %; ! perm lock ID macro UCB$t_md_perm_valblk = 776,0,0,0 %; literal UCB$s_md_perm_valblk = 12; ! perm value block macro UCB$b_md_nomem_retrycnt = 788,0,8,0 %; ! no memory retry count macro UCB$b_md_nofork_retrycnt = 789,0,8,0 %; ! no fork retry count macro UCB$b_md_noastcln_retrycnt = 790,0,8,0 %; ! no AST clean retry count macro UCB$b_md_rsvd_retrycnt = 791,0,8,0 %; ! rsvd retry count macro UCB$q_md_reserved1 = 792,0,0,0 %; literal UCB$s_md_reserved1 = 8; ! reserved quadword macro UCB$R_FKB = 800,0,0,0 %; literal UCB$S_FKB = 48; ! Embedded FKB$ macro UCB$l_md_dtlockfqfkb = 800,0,32,0 %; ! FORK QUEUE FORWARD LINK lw macro UCB$L_md_pdtlockfqfkb = 800,0,32,1 %; ! FORK QUEUE FORWARD LINK ptr macro UCB$L_md_pdtlockbqfkb = 804,0,32,1 %; ! FORK QUEUE BACKWARD LINK macro UCB$w_md_dtlckfkbsize = 808,0,16,0 %; ! SIZE OF UCB IN BYTES macro UCB$b_md_dtlckfkbtype = 810,0,8,0 %; ! STRUCTURE TYPE FOR UCB macro UCB$b_md_dtlckfkbflck = 811,0,8,0 %; ! Fork lock number index macro UCB$L_md_pdtlckfkbfpc = 812,0,32,1 %; ! FORK PC macro UCB$q_md_dtlckfkbfr3 = 816,0,0,1 %; literal UCB$s_md_dtlckfkbfr3 = 8; ! FORK R3 macro UCB$q_md_dtlckfkbfr4 = 824,0,0,1 %; literal UCB$s_md_dtlckfkbfr4 = 8; ! FORK R4 macro UCB$R_FKB2 = 848,0,0,0 %; literal UCB$S_FKB2 = 48; ! Embedded FKB$ macro UCB$l_md_updatefilefqfkb = 848,0,32,0 %; ! FORK QUEUE FORWARD LINK lw macro UCB$L_md_pupdatefilefqfkb = 848,0,32,1 %; ! FORK QUEUE FORWARD LINK ptr macro UCB$L_md_pupdatefilebqfkb = 852,0,32,1 %; ! FORK QUEUE BACKWARD LINK macro UCB$w_md_updtflfkbsize = 856,0,16,0 %; ! SIZE OF UCB IN BYTES macro UCB$b_md_updtflfkbtype = 858,0,8,0 %; ! STRUCTURE TYPE FOR UCB macro UCB$b_md_updtflfkbflck = 859,0,8,0 %; ! Fork lock number index macro UCB$L_md_pupdtflfkbfpc = 860,0,32,1 %; ! FORK PC macro UCB$q_md_updtflfkbfr3 = 864,0,0,1 %; literal UCB$s_md_updtflfkbfr3 = 8; ! FORK R3 macro UCB$q_md_updtflfkbfr4 = 872,0,0,1 %; literal UCB$s_md_updtflfkbfr4 = 8; ! FORK R4 macro UCB$l_md_dbg = 896,0,0,0 %; literal UCB$s_md_dbg = 40; ! debug macro UCB$q_md_qdbg = 896,0,0,0 %; literal UCB$s_md_qdbg = 40; ! debug macro UCB$pq_md_src = 936,0,0,1 %; literal UCB$s_md_src = 8; ! debug macro UCB$pq_md_dst = 944,0,0,1 %; literal UCB$s_md_dst = 8; ! debug macro UCB$l_md_debuglevel = 952,0,32,0 %; ! debug macro UCB$l_md_version = 956,0,32,0 %; ! reserved longword macro UCB$l_md_reserved2 = 960,0,32,0 %; ! reserved longword ! *** Add new extensions immediately before this line!!!!! *** ! *** All symbols in the UCB extension for device XX should *** ! *** have names that begin XX_, including the length symbol *** ! *** UCB$C_XX_LENGTH. (Note the need for "tag C" when creating *** ! *** this symbol, otherwise you'll get UCB$K_XX_LENGTH.) *** ! *** Contact the SDA maintainer so that SDA can be taught how *** ! *** to format the XX extension to the UCB. *** ! ! SUPPLEMENTAL UCB DATA definition ! This structure is intended to contain information which should belong ! in the UCB but can't because we cannot change the size of the UCB ! without impacting customers. ! literal SUD$M_AUX_SUD_ALLOC = %X'1'; literal SUD$M_PATH_AVAILABLE = %X'1'; literal SUD$M_OK2UINIT = %X'2'; literal SUD$M_PV_TRIED = %X'4'; literal SUD$M_PACKACK_TRIED = %X'8'; literal SUD$M_SWITCH_TRIED = %X'10'; literal SUD$M_PATH_USER_DISABLED = %X'20'; literal SUD$M_NOTCURPATH_IOIP = %X'40'; literal SUD$M_POLL_ENABLED = %X'80'; literal SUD$M_NOT_RESPONDING = %X'100'; literal SUD$M_NO_PR_SUPP = %X'200'; literal SUD$M_MV_MSG_SUPPRESSED = %X'400'; literal SUD$M_CFGCBK_PND = %X'800'; literal SUD$M_MVSUPMSG_OVERRIDE = %X'1000'; literal SUD$M_SHUNNED_ON_LAST_PV = %X'2000'; literal SUD$M_WWID_PRESENT = %X'1'; literal SUD$M_FC_PORT_NAME_PRESENT = %X'2'; literal SUD$M_FC_NODE_NAME_PRESENT = %X'4'; literal SUD$M_PR_DISABLED = %X'8'; literal SUD$M_CLONED_UCB = %X'10'; literal SUD$M_NOSYNCH_CANCEL = %X'20'; literal SUD$M_SAS_ADDRESS_PRESENT = %X'40'; literal SUD$M_SATA_END_DEVICE = %X'80'; literal SUD$M_IR_VOLUME = %X'100'; literal SUD$M_CISS_EXT_LUN = %X'200'; literal SUD$M_FP_ON_PORT_QUEUE = %X'1'; literal SUD$M_FP_USER_PREF_CPU = %X'2'; literal SUD$M_FP_ON_HWINT_PORT_QUEUE = %X'4'; literal SUD$M_FP_USRPRF_HWINT_CPU = %X'8'; literal SUD$M_FP_INIT_FAILED = %X'10'; literal SUD$S_SUD = 256; macro SUD$PS_UCBLINK = 0,0,32,1 %; ! Pointer to UCB for this SUD macro SUD$PS_AUX_SUD = 4,0,32,1 %; ! Pointer to Driver UCB extension area. macro SUD$W_SIZE = 8,0,16,0 %; ! Size of SUD, in bytes. macro SUD$B_TYPE = 10,0,8,0 %; ! Nonpaged pool packet type, DYN$C_MISC macro SUD$B_SUBTYPE = 11,0,8,0 %; ! Nonpaged pool packet subtype, DYN$C_SUD ! Flag bits macro SUD$L_FLAGS = 12,0,32,0 %; macro SUD$V_AUX_SUD_ALLOC = 12,0,1,0 %; ! Area pointed to by SUD$PS_AUX_SUD has been allocated macro SUD$L_STS = 16,0,32,0 %; macro SUD$V_PATH_AVAILABLE = 16,0,1,0 %; ! Set by driver once unit init is complete. macro SUD$V_OK2UINIT = 16,1,1,0 %; ! Set by driver if unit init failed. It states that ! this UCB can be reused. macro SUD$V_PV_TRIED = 16,2,1,0 %; ! Set if path verification I/O has been issued to ! this path while path verification is in progress macro SUD$V_PACKACK_TRIED = 16,3,1,0 %; ! Set if packack I/O has been issued to ! this path while path verification is in progress macro SUD$V_SWITCH_TRIED = 16,4,1,0 %; ! Set if path switch has been switched to ! while path verification is in progress macro SUD$V_PATH_USER_DISABLED = 16,5,1,0 %; ! Set if access denied via user request macro SUD$V_NOTCURPATH_IOIP = 16,6,1,0 %; ! Set if this path is not the current path but it ! has I/O in progress macro SUD$V_POLL_ENABLED = 16,7,1,0 %; ! Poll enabled on this path macro SUD$V_NOT_RESPONDING = 16,8,1,0 %; ! Device is not responding via this path macro SUD$V_NO_PR_SUPP = 16,9,1,0 %; ! No Persistent Reservation Support macro SUD$V_MV_MSG_SUPPRESSED = 16,10,1,0 %; ! MV start msg has been automatically suppressed, for now macro SUD$V_CFGCBK_PND = 16,11,1,0 %; ! Device configuration call back pending macro SUD$V_MVSUPMSG_OVERRIDE = 16,12,1,0 %; ! Override message suppression for this MV event macro SUD$V_SHUNNED_ON_LAST_PV = 16,13,1,0 %; ! Path was shunned on the most recent path verification attempt macro SUD$L_DEVCHAR3 = 20,0,32,0 %; macro SUD$V_WWID_PRESENT = 20,0,1,0 %; ! this SUD contains WWID macro SUD$V_FC_PORT_NAME_PRESENT = 20,1,1,0 %; ! this SUD contains a fibre channel port name macro SUD$V_FC_NODE_NAME_PRESENT = 20,2,1,0 %; ! this SUD contains a fibre channel node name macro SUD$V_PR_DISABLED = 20,3,1,0 %; ! Persistent Reservations are disabled macro SUD$V_CLONED_UCB = 20,4,1,0 %; ! indicates, if this UCB is a cloned UCB macro SUD$V_NOSYNCH_CANCEL = 20,5,1,0 %; ! driver cancel routine will be called without forklock macro SUD$V_SAS_ADDRESS_PRESENT = 20,6,1,0 %; ! this SUD contains a SAS Port Address macro SUD$V_SATA_END_DEVICE = 20,7,1,0 %; ! this SUD contains a SATA WWID macro SUD$V_IR_VOLUME = 20,8,1,0 %; ! this SUD contains an Integrated RAID WWID macro SUD$V_CISS_EXT_LUN = 20,9,1,0 %; ! this SUD contains a CISS external Lun macro SUD$Q_SCSSYSTEMID = 24,0,0,0 %; literal SUD$S_SCSSYSTEMID = 8; ! SCS system ID macro SUD$L_Spare_1 = 32,0,32,0 %; ! macro SUD$L_Spare_2 = 36,0,32,0 %; ! macro SUD$L_Spare_3 = 40,0,32,0 %; ! macro SUD$L_Spare_4 = 44,0,32,0 %; ! macro SUD$L_WWID_OFFSET = 48,0,32,0 %; ! WWID ofset macro SUD$L_WWID_LENGTH = 52,0,32,0 %; ! WWID length macro SUD$PS_MPDEV = 56,0,32,1 %; ! Pointer to the multipath structure macro SUD$PS_MPDEV_PRIMARY_UCB = 60,0,32,1 %; ! Pointer to the primary paths UCB macro SUD$PS_MPDEV_NEXT_UCB = 64,0,32,1 %; ! Pointer to the next UCB in a multipath set. macro SUD$Q_MPDEV_SWITCH_TO_TIME = 72,0,0,0 %; literal SUD$S_MPDEV_SWITCH_TO_TIME = 8; ! last time this path was switched to macro SUD$Q_MPDEV_SWITCH_FROM_TIME = 80,0,0,0 %; literal SUD$S_MPDEV_SWITCH_FROM_TIME = 8; ! last time this path was switched from macro SUD$PS_MPDEV_PPB = 88,0,32,1 %; ! Pointer to Path Poller Block for this path macro SUD$L_FP_FLAGS = 92,0,32,0 %; ! Fastpath flags macro SUD$V_FP_ON_PORT_QUEUE = 92,0,1,0 %; ! set if port already on port queue macro SUD$V_FP_USER_PREF_CPU = 92,1,1,0 %; ! set if user has assigned this port macro SUD$V_FP_ON_HWINT_PORT_QUEUE = 92,2,1,0 %; ! set if port already on FASTPATH HW interrupt ports queue macro SUD$V_FP_USRPRF_HWINT_CPU = 92,3,1,0 %; ! set if user has assigned this port to a HW interrupt CPU. macro SUD$V_FP_INIT_FAILED = 92,4,1,0 %; ! exe$fp_port_init() failed to init this port ! Fastpath preferred CPU state macro SUD$L_FP_USRPRF_CPUDB = 96,0,32,1 %; ! CPU db addr of user-preferred port macro SUD$L_FP_PORTS_LINK = 100,0,32,1 %; ! single-link queue of ports. macro SUD$L_FP_ASGN_PORTS_FL = 104,0,32,1 %; ! queue links into per-CPU assigned macro SUD$L_FP_ASGN_PORTS_BL = 108,0,32,1 %; ! ports queue. ! Fastpath HW interrupt CPU state macro SUD$L_FP_HWINT_CPU = 112,0,32,1 %; ! CPU db addr of current HW interrupt CPU. macro SUD$L_FP_USRPRF_HWINT_CPU = 116,0,32,1 %; ! CPU db addr of user-preferred HW interrupt CPU. macro SUD$L_FP_HWINT_PORTS_LINK = 120,0,32,1 %; ! single-link queue of all HW interrupt ports. macro SUD$L_FP_ASGN_HWINT_PORTS_FL = 124,0,32,1 %; ! queue links into the current HW interrupt macro SUD$L_FP_ASGN_HWINT_PORTS_BL = 128,0,32,1 %; ! CPU's list of HW interrupt ports assigned to it.. ! Fastpath contingency cells macro SUD$L_FP_SPARE1 = 132,0,32,1 %; macro SUD$L_FP_SPARE2 = 136,0,32,1 %; macro SUD$L_FP_SPARE3 = 140,0,32,1 %; macro SUD$L_FP_SPARE4 = 144,0,32,1 %; macro SUD$L_MPDEV_PV_IOST1 = 148,0,32,0 %; ! Last PV I/O status on path macro SUD$L_MPDEV_PV_ABSTIM = 152,0,32,0 %; ! Last PV time (abstim) macro SUD$L_MPDEV_TRACKING_END = 156,0,32,0 %; ! Current tracking interval end (abstim) macro SUD$L_MPDEV_TRACKING_COUNT = 160,0,32,0 %; ! PV incursions during interval macro SUD$L_MPDEV_PV_DURATION = 164,0,32,0 %; ! Last PV I/O duration (seconds) macro SUD$PS_MPDEV_PATH_LINK = 168,0,32,1 %; ! Pointer to next SUD on same MPDEV_PPB (null terminated) macro SUD$L_MPDEV_SHUNNED_COUNT = 172,0,32,0 %; ! Total number of times path has been shunned macro SUD$L_MPDEV_SPARE_6 = 176,0,32,1 %; ! Reserved for multipath macro SUD$L_MPDEV_PATH_ID = 180,0,32,1 %; ! Path id for multipath macro SUD$PS_FC_PORT_NAME = 184,0,32,1 %; ! Pointer to fibre channel port name macro SUD$PS_FC_NODE_NAME = 188,0,32,1 %; ! Pointer to fibre channel node name macro SUD$l_BUSY_BIT_IRP_P = 192,0,32,1 %; ! Pointer to ucb$r_busy_bit_irp macro SUD$L_MPDEV_SPARE_7 = 196,0,32,1 %; ! Reserved for multipath macro SUD$L_MPDEV_SPARE_8 = 200,0,32,1 %; ! Reserved for multipath macro SUD$L_MPDEV_SPARE_9 = 204,0,32,1 %; ! Reserved for multipath macro SUD$L_MPDEV_SPARE_10 = 208,0,32,1 %; ! Reserved for multipath macro SUD$L_HBVS_SPARE_1 = 212,0,32,1 %; ! Reserved for HBVS macro SUD$L_HBVS_SPARE_2 = 216,0,32,1 %; ! Reserved for HBVS macro SUD$L_MVSUPMSG_INTVL_END = 220,0,32,0 %; ! End of current quiet MV interval in ABSTIM seconds macro SUD$L_MVSUPMSG_INTVL_NUM = 224,0,32,0 %; ! Count of suppressed MV messages so far in current interval macro SUD$L_MVSUPMSG_TOTAL_NUM = 228,0,32,0 %; ! Total count of suppressed MV messages since boot for this device macro SUD$L_MVSUPMSG_INTVL = 232,0,32,0 %; ! MV msg suppression interval in seconds for this device ! Changed by SET DEVICE/MV_INTERVAL=n, 0 means use system-wide value macro SUD$L_MVSUPMSG_NUM = 236,0,32,0 %; ! MV msg suppression threshold count ! Changed by SET DEVICE/MV_NUMBER=n, 0 means use system-wide value macro SUD$Q_LAST_ERRRST = 240,0,0,0 %; literal SUD$S_LAST_ERRRST = 8; ! Last time the error count of was reset macro SUD$L_MPDEV_PATH_SWITCH_COUNT = 248,0,32,0 %; ! count of successful path switches to this path literal SUD$C_LENGTH = 256; ! Length of a SUD literal SUD$K_LENGTH = 256; ! Length of a SUD !*** MODULE $TTYUCBDEF *** ! ! $TTYUCBDEF follows here only because there is no way to get the ! UCB$K_LENGTH symbol into another module. TTYUCBDEF was formerly ! included in TTYDEF.MAR. ! ! TERMINAL DRIVER DEFINITIONS ! ! These definitions define the device dependent extensions of the UCB. ! Certain portions of the ucb are assumed to be contiguous and must not ! be split. These areas are documented in the following definitions. ! literal UCB$S_LTRM_UCB = 520; ! ! Logical terminal UCB extension ! macro UCB$L_TL_CTRLY = 472,0,32,1 %; ! CONTROL Y AST BLOCK LIST HEAD macro UCB$L_TL_CTRLC = 476,0,32,1 %; ! CONTROL C AST BLOCK LIST HEAD macro UCB$L_TL_OUTBAND = 480,0,32,0 %; ! OUT OF BAND CHARACTER MASK macro UCB$L_TL_BANDQUE = 484,0,32,1 %; ! OUT OF BAND AST QUEUE macro UCB$L_TL_PHYUCB = 488,0,32,1 %; ! THE PHYSICAL UCB ADDRESS macro UCB$L_TL_CTLPID = 492,0,32,0 %; ! CONTROLING PID (USED WITH SPAWN) macro UCB$Q_TL_BRKTHRU = 496,0,0,0 %; literal UCB$S_TL_BRKTHRU = 8; ! FACILITY BROADCAST BITMASK macro UCB$L_TL_POSIX_DATA = 504,0,32,1 %; ! POSIX PTC POINTER macro UCB$L_TL_ASIAN_DATA = 508,0,32,1 %; ! ASIAN DATA POINTER macro UCB$B_TL_A_MODE = 512,0,8,0 %; ! CURRENT ASIAN MODES macro UCB$L_TL_A_CHARSET = 512,0,32,0 %; ! CHARACTER SET BITMASK macro UCB$L_TL_A_FI_UCB = 516,0,32,1 %; ! POINTER TO ASIAN INPUT SERVER ! ! Terminal class driver dependant region ! Split here between local and remote terminal UCB's, each of ! which has it's own type. ! literal UCB$C_TL_LENGTH = 520; literal UCB$K_TL_LENGTH = 520; literal TTY$M_ST_POWER = %X'1'; literal TTY$M_ST_CTRLS = %X'2'; literal TTY$M_ST_LOSTCTS = %X'4'; literal TTY$M_ST_MODEM_OFF = %X'8'; literal TTY$M_ST_POSIXSTALL = %X'10'; literal TTY$M_ST_FILL = %X'20'; literal TTY$M_ST_CURSOR = %X'40'; literal TTY$M_ST_SENDLF = %X'80'; literal TTY$M_ST_BACKSPACE = %X'100'; literal TTY$M_ST_MULTI = %X'200'; literal TTY$M_ST_WRITE = %X'400'; literal TTY$M_ST_POSIXWRITE = %X'800'; literal TTY$M_ST_EOL = %X'1000'; literal TTY$M_ST_EDITREAD = %X'2000'; literal TTY$M_ST_RDVERIFY = %X'4000'; literal TTY$M_ST_RECALL = %X'8000'; literal TTY$M_ST_READ = %X'10000'; literal TTY$M_ST_POSIXREAD = %X'20000'; literal TTY$M_ST_CTRLO = %X'1'; literal TTY$M_ST_DEL = %X'2'; literal TTY$M_ST_PASALL = %X'4'; literal TTY$M_ST_NOECHO = %X'8'; literal TTY$M_ST_WRTALL = %X'10'; literal TTY$M_ST_PROMPT = %X'20'; literal TTY$M_ST_NOFLTR = %X'40'; literal TTY$M_ST_ESC = %X'80'; literal TTY$M_ST_BADESC = %X'100'; literal TTY$M_ST_NL = %X'200'; literal TTY$M_ST_REFRSH = %X'400'; literal TTY$M_ST_ESCAPE = %X'800'; literal TTY$M_ST_TYPFUL = %X'1000'; literal TTY$M_ST_SKIPLF = %X'2000'; literal TTY$M_ST_ESC_O = %X'4000'; literal TTY$M_ST_WRAP = %X'8000'; literal TTY$M_ST_OVRFLO = %X'10000'; literal TTY$M_ST_AUTOP = %X'20000'; literal TTY$M_ST_CTRLR = %X'40000'; literal TTY$M_ST_SKIPCRLF = %X'80000'; literal TTY$M_ST_EDITING = %X'100000'; literal TTY$M_ST_TABEXPAND = %X'200000'; literal TTY$M_ST_QUOTING = %X'400000'; literal TTY$M_ST_OVERSTRIKE = %X'800000'; literal TTY$M_ST_TERMNORM = %X'1000000'; literal TTY$M_ST_ECHAES = %X'2000000'; literal TTY$M_ST_PRE = %X'4000000'; literal TTY$M_ST_NINTMULTI = %X'8000000'; literal TTY$M_ST_RECONNECT = %X'10000000'; literal TTY$M_ST_CTSLOW = %X'20000000'; literal TTY$M_ST_TABRIGHT = %X'40000000'; literal UCB$M_TT_XXPARITY = %X'1'; literal UCB$M_TT_DISPARERR = %X'2'; literal UCB$M_TT_USERFRAME = %X'4'; literal UCB$M_TT_LEN = %X'18'; literal UCB$M_TT_STOP = %X'20'; literal UCB$M_TT_PARTY = %X'40'; literal UCB$M_TT_ODD = %X'80'; literal TTY$M_TANK_PREMPT = %X'100'; literal TTY$M_TANK_STOP = %X'200'; literal TTY$M_TANK_HOLD = %X'400'; literal TTY$M_TANK_BURST = %X'800'; literal TTY$M_TANK_DMA = %X'1000'; literal TTY$M_PC_NOTIME = %X'1'; literal TTY$M_PC_DMAENA = %X'2'; literal TTY$M_PC_DMAAVL = %X'4'; literal TTY$M_PC_PRMMAP = %X'8'; literal TTY$M_PC_MAPAVL = %X'10'; literal TTY$M_PC_XOFAVL = %X'20'; literal TTY$M_PC_XOFENA = %X'40'; literal TTY$M_PC_NOCRLF = %X'80'; literal TTY$M_PC_BREAK = %X'100'; literal TTY$M_PC_PORTFDT = %X'200'; literal TTY$M_PC_NOMODEM = %X'400'; literal TTY$M_PC_NODISCONNECT = %X'800'; literal TTY$M_PC_SMART_READ = %X'1000'; literal TTY$M_PC_ACCPORNAM = %X'2000'; literal TTY$M_PC_FRAME = %X'4000'; literal TTY$M_PC_MULTISESSION = %X'8000'; literal UCB$M_TT_DSBL = %X'80'; literal UCB$S_TTY_UCB = 752; ! READ TIMEOUT CONTROL macro UCB$L_TT_RDUE = 520,0,32,0 %; ! ABSTIME WHEN READ TIMEOUT DUE macro UCB$L_TT_RTIMOU = 524,0,32,1 %; ! ADDRESS OF READ TIMEOUT ROUTINE ! TERMINAL DRIVER STATE TABLE ! (NOTE: Any changes made to this state table must also be made to ! the SX state table.) macro UCB$Q_TT_STATE = 528,0,0,0 %; literal UCB$S_TT_STATE = 8; ! CURRENT UNIT STATE VECTOR macro UCB$L_TT_STATE1 = 528,0,32,0 %; macro TTY$V_ST_POWER = 528,0,1,0 %; ! macro TTY$V_ST_CTRLS = 528,1,1,0 %; ! macro TTY$V_ST_LOSTCTS = 528,2,1,0 %; ! Reserved for future work macro TTY$V_ST_MODEM_OFF = 528,3,1,0 %; ! macro TTY$V_ST_POSIXSTALL = 528,4,1,0 %; ! POSIX timed output wait macro TTY$V_ST_FILL = 528,5,1,0 %; ! macro TTY$V_ST_CURSOR = 528,6,1,0 %; ! macro TTY$V_ST_SENDLF = 528,7,1,0 %; ! macro TTY$V_ST_BACKSPACE = 528,8,1,0 %; ! macro TTY$V_ST_MULTI = 528,9,1,0 %; ! macro TTY$V_ST_WRITE = 528,10,1,0 %; macro TTY$V_ST_POSIXWRITE = 528,11,1,0 %; ! POSIX special case write macro TTY$V_ST_EOL = 528,12,1,0 %; ! macro TTY$V_ST_EDITREAD = 528,13,1,0 %; ! macro TTY$V_ST_RDVERIFY = 528,14,1,0 %; ! macro TTY$V_ST_RECALL = 528,15,1,0 %; ! macro TTY$V_ST_READ = 528,16,1,0 %; ! macro TTY$V_ST_POSIXREAD = 528,17,1,0 %; ! macro UCB$L_TT_STATE2 = 532,0,32,0 %; macro TTY$V_ST_CTRLO = 532,0,1,0 %; ! macro TTY$V_ST_DEL = 532,1,1,0 %; ! macro TTY$V_ST_PASALL = 532,2,1,0 %; ! macro TTY$V_ST_NOECHO = 532,3,1,0 %; ! macro TTY$V_ST_WRTALL = 532,4,1,0 %; ! macro TTY$V_ST_PROMPT = 532,5,1,0 %; ! macro TTY$V_ST_NOFLTR = 532,6,1,0 %; ! macro TTY$V_ST_ESC = 532,7,1,0 %; ! macro TTY$V_ST_BADESC = 532,8,1,0 %; ! macro TTY$V_ST_NL = 532,9,1,0 %; ! macro TTY$V_ST_REFRSH = 532,10,1,0 %; ! macro TTY$V_ST_ESCAPE = 532,11,1,0 %; ! macro TTY$V_ST_TYPFUL = 532,12,1,0 %; ! macro TTY$V_ST_SKIPLF = 532,13,1,0 %; ! macro TTY$V_ST_ESC_O = 532,14,1,0 %; ! macro TTY$V_ST_WRAP = 532,15,1,0 %; ! macro TTY$V_ST_OVRFLO = 532,16,1,0 %; ! macro TTY$V_ST_AUTOP = 532,17,1,0 %; ! macro TTY$V_ST_CTRLR = 532,18,1,0 %; ! macro TTY$V_ST_SKIPCRLF = 532,19,1,0 %; ! macro TTY$V_ST_EDITING = 532,20,1,0 %; ! macro TTY$V_ST_TABEXPAND = 532,21,1,0 %; ! macro TTY$V_ST_QUOTING = 532,22,1,0 %; ! macro TTY$V_ST_OVERSTRIKE = 532,23,1,0 %; ! macro TTY$V_ST_TERMNORM = 532,24,1,0 %; ! macro TTY$V_ST_ECHAES = 532,25,1,0 %; ! macro TTY$V_ST_PRE = 532,26,1,0 %; ! macro TTY$V_ST_NINTMULTI = 532,27,1,0 %; ! macro TTY$V_ST_RECONNECT = 532,28,1,0 %; ! macro TTY$V_ST_CTSLOW = 532,29,1,0 %; ! macro TTY$V_ST_TABRIGHT = 532,30,1,0 %; ! macro UCB$L_TT_LOGUCB = 536,0,32,1 %; ! ADDRESS OF THE LOGICAL UCB ! DEFAULT CHARACTERISTICS macro UCB$L_TT_DECHAR = 540,0,32,0 %; ! DEFAULT DEVICE CHARACTERISTICS macro UCB$L_TT_DECHA1 = 544,0,32,0 %; ! DEFAULT DEVICE CHAR EXTENSIONS macro UCB$L_TT_DECHA2 = 548,0,32,0 %; ! MORE DEVICE CHARACTERISTICS macro UCB$L_TT_DECHA3 = 552,0,32,0 %; ! ANOTHER DEVICE CHAR EXTENSIONS ! WRITE QUEUE POINTERS macro UCB$L_TT_WFLINK = 560,0,32,1 %; ! Write queue forward link. macro UCB$L_TT_WBLINK = 564,0,32,1 %; ! Write queue backward link. macro UCB$L_TT_WRTBUF = 568,0,32,1 %; ! Current write buffer block. ! ADDRESS AND LENGTH OF MULTI-ECHO STRING macro UCB$L_TT_MULTI = 572,0,32,1 %; ! CURRENT MULTIECHO BUFFER ADDRESS macro UCB$W_TT_MULTILEN = 576,0,16,0 %; ! LENGTH OF STRING TO OUTPUT macro UCB$W_TT_SMLTLEN = 580,0,16,0 %; ! SAVED MULTI LENGTH macro UCB$L_TT_SMLT = 584,0,32,1 %; ! AND THE SAVED ADDRESS ! -- ********************************************************************** ! DEFAULT SPEED, FILL ,PARITY (MUST BE CONTIGUOUS) ! ++ ******************************************************************* macro UCB$W_TT_DESPEE = 588,0,16,0 %; ! DEFAULT SPEED macro UCB$B_TT_DECRF = 590,0,8,0 %; ! DEFAULT CR FILL macro UCB$B_TT_DELFF = 591,0,8,0 %; ! DEFAULT LF FILL macro UCB$B_TT_DEPARI = 592,0,8,0 %; ! DEFAULT PARITY/CHAR SIZE macro UCB$B_TT_DEFSPE_SPARE1 = 593,0,8,0 %; macro UCB$W_TT_DEFSPE_SPARE2 = 594,0,16,0 %; ! -- ********************************************************************** ! ! DEFAULT TERMINAL TYPE AND SIZE ! ! ++ *********************************************************************** macro UCB$W_TT_DESIZE = 596,0,16,0 %; ! DEFAULT LINE SIZE macro UCB$B_TT_DETYPE = 598,0,8,0 %; ! DEFAULT TERMINAL TYPE macro UCB$B_TT_SPARE1 = 599,0,8,0 %; ! SPARE BYTE MUST FOLLOW ! -- ********************************************************************** ! SPEED, FILL, PARITY (MUST BE CONTIGUOUS) ! ++ ***************************************************************** macro UCB$W_TT_SPEED = 600,0,16,0 %; ! SPEED CODES (SPLIT SPEED) macro UCB$B_TT_TSPEED = 600,0,8,0 %; ! TRANSMIT SPEED macro UCB$B_TT_RSPEED = 601,0,8,0 %; ! RECEIVE SPEED macro UCB$B_TT_CRFILL = 602,0,8,0 %; ! NUMBER FILLS TO OUTPUT ON CR macro UCB$B_TT_LFFILL = 603,0,8,0 %; ! NUMBER FILLS TO OUTPUT ON LF macro UCB$B_TT_PARITY = 604,0,8,0 %; ! PARITY AND CHARACTER SIZE DEFINITIONS macro UCB$V_TT_XXPARITY = 604,0,1,0 %; ! UNUSED ?? macro UCB$V_TT_DISPARERR = 604,1,1,0 %; ! SPECIFY DISREGARD PARITY ERRORS macro UCB$V_TT_USERFRAME = 604,2,1,0 %; ! SPECIFY USER FRAME SETUP macro UCB$V_TT_LEN = 604,3,2,0 %; literal UCB$S_TT_LEN = 2; ! CHARACTER LENGTH macro UCB$V_TT_STOP = 604,5,1,0 %; ! STOP BITS macro UCB$V_TT_PARTY = 604,6,1,0 %; ! PARITY ENABLED macro UCB$V_TT_ODD = 604,7,1,0 %; ! ODD PARITY macro UCB$B_TT_PAR_SPARE1 = 605,0,8,0 %; macro UCB$W_TT_PAR_SPARE2 = 606,0,16,0 %; ! -- ****************************************************************** ! Typeahead buffer address macro UCB$L_TT_TYPAHD = 608,0,32,1 %; ! TYPEAHEAD BUFFER ADDRESS ! CURRENT CURSOR AND LINE POSITION FOR FORMATTED OPERATIONS macro UCB$W_TT_CURSOR = 612,0,16,0 %; ! CURRENT CURSOR POSITION macro UCB$B_TT_LINE = 616,0,8,0 %; ! CURRENT LINE ON PAGE macro UCB$B_TT_LASTC = 620,0,8,0 %; ! LAST FORMATTED OUTPUT CHARACTER ! Number of back spaces to output for non-ansi terminals macro UCB$W_TT_BSPLEN = 624,0,16,0 %; ! NUMBER OF BACKSPACES ! FILL HANDLING macro UCB$B_TT_FILL = 628,0,8,0 %; ! CURRENT FILL COUNT ! ESCAPE SYNTAX RULE STATE. macro UCB$B_TT_ESC = 632,0,8,0 %; ! CURRENT READ ESCAPE SYNTAX STATE macro UCB$B_TT_ESC_O = 636,0,8,0 %; ! OUPUT ESCAPE STATE ! Count of characters in interrupt string macro UCB$B_TT_INTCNT = 640,0,8,0 %; ! Bit used for modem control macro UCB$W_TT_UNITBIT = 644,0,16,0 %; ! BIT USED TO ENABLE AND DISABLE MODEM CONTROL. ! PORT SPECIFIC OUTPUT CONTROL macro UCB$W_TT_HOLD = 648,0,16,0 %; ! UNIT HOLDING TANK AND PORT DISPATCH macro TTY$B_TANK_CHAR = 648,0,8,0 %; ! CHARACTER macro TTY$V_TANK_PREMPT = 648,8,1,0 %; ! SEND PREMPT CHARACTER macro TTY$V_TANK_STOP = 648,9,1,0 %; ! STOP OUTPUT macro TTY$V_TANK_HOLD = 648,10,1,0 %; ! CHAR IN TANK macro TTY$V_TANK_BURST = 648,11,1,0 %; ! BURST ACTIVE macro TTY$V_TANK_DMA = 648,12,1,0 %; ! DMA ACTIVE **** SHOULD MOVE BEFORE BURST **** macro UCB$B_TT_PREMPT = 652,0,8,0 %; ! THE BYTE USED TO PREMPT INPUT macro UCB$B_TT_OUTYPE = 656,0,8,1 %; ! TYPE OF OUTPUT THAT THIS CALL ! CLASS & PORT VECTOR POINTERS macro UCB$L_TT_GETNXT = 660,0,32,1 %; ! ADDRESS OF CLASS INPUT ROUTINE macro UCB$L_TT_PUTNXT = 664,0,32,1 %; ! ADDRESS OF CLASS OUTPUT ROUTINE macro UCB$L_TT_CLASS = 668,0,32,1 %; ! ADDRESS OF CLASS VECTOR macro UCB$L_TT_PORT = 672,0,32,1 %; ! ADDRESS OF PORT VECTOR macro UCB$L_TT_OUTADR = 676,0,32,1 %; ! ADDRESS OF OUTPUT CURRENT STREAM macro UCB$W_TT_OUTLEN = 680,0,16,0 %; ! LENGTH OF OUTPUT STREAM macro UCB$L_TT_PRTCTL = 684,0,32,0 %; macro UCB$W_TT_PRTCTL = 684,0,16,0 %; ! THE PORT DRIVER CONTROL WORD macro TTY$V_PC_NOTIME = 684,0,1,0 %; ! IF SET NO TIMEOUT WILL BE CALCULATED macro TTY$V_PC_DMAENA = 684,1,1,0 %; ! DMA CURRENTLY ENABLED macro TTY$V_PC_DMAAVL = 684,2,1,0 %; ! DMA SUPPORTED ON THIS PORT macro TTY$V_PC_PRMMAP = 684,3,1,0 %; ! UNIT CAN HAVE PERMANENT MAP REGISTERS macro TTY$V_PC_MAPAVL = 684,4,1,0 %; ! MAP REGISTER CURRENTLY ALLOCATED macro TTY$V_PC_XOFAVL = 684,5,1,0 %; ! AUTO XOFF SUPPORTED ON THIS PORT macro TTY$V_PC_XOFENA = 684,6,1,0 %; ! AUTO XOFF CURRENTLY ENABLED macro TTY$V_PC_NOCRLF = 684,7,1,0 %; ! don't do free linefeed after creturn macro TTY$V_PC_BREAK = 684,8,1,0 %; ! TURN ON OR OFF BREAK macro TTY$V_PC_PORTFDT = 684,9,1,0 %; ! PORT CONTAINS FDT ROUTINE macro TTY$V_PC_NOMODEM = 684,10,1,0 %; ! Port cannot support modem operations macro TTY$V_PC_NODISCONNECT = 684,11,1,0 %; ! Device cannot support virtual terminal operations macro TTY$V_PC_SMART_READ = 684,12,1,0 %; ! Port contains additional read capabilities macro TTY$V_PC_ACCPORNAM = 684,13,1,0 %; ! Port supports access port name macro TTY$V_PC_FRAME = 684,14,1,0 %; ! GETNXT and PUTNXT use frame macro TTY$V_PC_MULTISESSION = 684,15,1,0 %; ! part of multi-session terminal ! MODEM CONTROL DEFINITIONS macro UCB$L_TT_DS_ST = 688,0,32,0 %; ! CURRENT MODEM STATE macro UCB$B_TT_DS_RCV = 692,0,8,0 %; ! CURRENT RECEIVE MODEM macro UCB$B_TT_DS_TX = 696,0,8,0 %; ! CURRENT TRANSMIT MODEM macro UCB$W_TT_DS_TIM = 700,0,16,0 %; ! CURRENT MODEM TIMEOUT macro UCB$B_TT_MAINT = 704,0,8,0 %; ! MAINTENANCE PARAMETERS macro UCB$V_TT_MAINT_FILL = 704,0,7,0 %; literal UCB$S_TT_MAINT_FILL = 7; macro UCB$V_TT_DSBL = 704,7,1,0 %; ! LINE DISABLED macro UCB$B_TT_OLDCPZORG = 708,0,8,0 %; ! Old cursor position macro UCB$W_TT_FILLRUP = 712,0,16,0 %; ! FILL to align next macro UCB$L_TT_FBK = 716,0,32,1 %; ! PTR TO FALLBACK BLOCK macro UCB$L_TT_RDVERIFY = 720,0,32,1 %; ! PTR TO READ/VERIFY TABLE macro UCB$L_TT_CLASS1 = 724,0,32,0 %; ! CLASS DRIVER LONGWORD macro UCB$L_TT_CLASS2 = 728,0,32,0 %; ! AND ANOTHER ONE macro UCB$L_TT_ACCPORNAM = 732,0,32,1 %; ! Address of counted string describing the port ! typicall LAT server name / and port name or number ! ***************************************************************************** ! ! Asian VMS extension ! ! ++ ************************************************************************** macro UCB$L_TT_A_GCBADR = 736,0,32,1 %; ! Glyph Control Block address macro UCB$W_TT_A_EDSTS = 740,0,16,0 %; ! Multi-byte line edit states macro UCB$B_TT_A_STATE = 742,0,8,0 %; ! On-demand loading states macro UCB$B_TT_A_PARSE = 743,0,8,0 %; ! ODL parse states macro UCB$B_TT_A_TRANS = 744,0,8,0 %; ! JIS conversion states macro UCB$B_TT_A_XEDSTS = 745,0,8,0 %; ! Extended line edit states macro UCB$W_TT_A_RESRV1 = 746,0,16,0 %; ! Reserved macro UCB$B_TT_A_CHAR = 748,0,8,0 %; ! Default Asian modes macro UCB$L_TT_A_DECHSET = 748,0,32,0 %; ! Default char set bitmask literal UCB$C_TT_CLSLEN = 752; literal UCB$K_TT_CLSLEN = 752; literal TTY$M_TP_ABORT = %X'1'; literal TTY$M_TP_ALLOC = %X'2'; literal TTY$M_TP_DLLOC = %X'4'; literal UCB$S_TPD_UCB = 760; ! ! ! Terminal Port driver dependant extension region ! ! macro UCB$L_TP_MAP = 752,0,32,1 %; ! UNIBUS MAP REGISTERS macro UCB$B_TP_STAT = 756,0,8,0 %; ! DMA PORT SPECIFIC STATUS macro TTY$V_TP_ABORT = 756,0,1,0 %; ! DMA ABORT REQUESTED ON THIS LINE macro TTY$V_TP_ALLOC = 756,1,1,0 %; ! ALLOC MAP FORK IN PROGRESS macro TTY$V_TP_DLLOC = 756,2,1,0 %; ! DEALLOCATE MAP FORK IN PROGRESS macro UCB$B_TP_SPARE1 = 757,0,8,0 %; macro UCB$W_TP_SPARE2 = 758,0,16,0 %; literal UCB$C_TP_LENGTH = 760; literal UCB$K_TP_LENGTH = 760; literal UCB$C_TT_LENGTH = 760; literal UCB$K_TT_LENGTH = 760; ! TERMINAL DRIVER SX STATE TABLE ! (NOTE: Any changes made to this state table must also be made to ! the ST state table.) literal TTY$M_SX_LOSTCTS = %X'4'; literal TTY$M_SX_POSIXSTALL = %X'10'; literal TTY$S_SX_STATE = 768; macro TTY$R_TT_STATE_SX = 760,0,0,0 %; literal TTY$S_TT_STATE_SX = 8; macro TTY$V_SX_POWER = 760,0,1,0 %; ! macro TTY$V_SX_CTRLS = 760,1,1,0 %; ! macro TTY$V_SX_LOSTCTS = 760,2,1,0 %; ! Reserved for future work macro TTY$V_SX_MODEM_OFF = 760,3,1,0 %; ! macro TTY$V_SX_POSIXSTALL = 760,4,1,0 %; ! POSIX timed output wait macro TTY$V_SX_FILL = 760,5,1,0 %; ! macro TTY$V_SX_CURSOR = 760,6,1,0 %; ! macro TTY$V_SX_SENDLF = 760,7,1,0 %; ! macro TTY$V_SX_BACKSPACE = 760,8,1,0 %; ! OUTPUT BACKSPACES FOR SEVERAL LOOPS macro TTY$V_SX_MULTI = 760,9,1,0 %; ! macro TTY$V_SX_WRITE = 760,10,1,0 %; ! Write state macro TTY$V_SX_POSIXWRITE = 760,11,1,0 %; ! POSIX Write state macro TTY$V_SX_EOL = 760,12,1,0 %; ! macro TTY$V_SX_EDITREAD = 760,13,1,0 %; ! macro TTY$V_SX_RDVERIFY = 760,14,1,0 %; ! macro TTY$V_SX_RECALL = 760,15,1,0 %; ! macro TTY$V_SX_READ = 760,16,1,0 %; ! macro TTY$V_SX_POSIXREAD = 760,17,1,0 %; ! macro TTY$V_SX_FILLBITS = 760,18,14,0 %; literal TTY$S_SX_FILLBITS = 14; ! END OF FIRST LONGWORD macro TTY$V_SX_CTRLO = 764,0,1,0 %; ! macro TTY$V_SX_DEL = 764,1,1,0 %; ! macro TTY$V_SX_PASALL = 764,2,1,0 %; ! macro TTY$V_SX_NOECHO = 764,3,1,0 %; ! macro TTY$V_SX_WRTALL = 764,4,1,0 %; ! macro TTY$V_SX_PROMPT = 764,5,1,0 %; ! macro TTY$V_SX_NOFLTR = 764,6,1,0 %; ! macro TTY$V_SX_ESC = 764,7,1,0 %; ! macro TTY$V_SX_BADESC = 764,8,1,0 %; ! macro TTY$V_SX_NL = 764,9,1,0 %; ! New line must directly precede macro TTY$V_SX_REFRSH = 764,10,1,0 %; ! refresh, or all breaks. macro TTY$V_SX_ESCAPE = 764,11,1,0 %; ! macro TTY$V_SX_TYPFUL = 764,12,1,0 %; ! macro TTY$V_SX_SKIPLF = 764,13,1,0 %; ! macro TTY$V_SX_ESC_O = 764,14,1,0 %; ! macro TTY$V_SX_WRAP = 764,15,1,0 %; ! macro TTY$V_SX_OVRFLO = 764,16,1,0 %; ! macro TTY$V_SX_AUTOP = 764,17,1,0 %; ! macro TTY$V_SX_CTRLR = 764,18,1,0 %; ! macro TTY$V_SX_SKIPCRLF = 764,19,1,0 %; ! macro TTY$V_SX_EDITING = 764,20,1,0 %; ! macro TTY$V_SX_TABEXPAND = 764,21,1,0 %; ! macro TTY$V_SX_QUOTING = 764,22,1,0 %; ! macro TTY$V_SX_OVERSTRIKE = 764,23,1,0 %; ! macro TTY$V_SX_TERMNORM = 764,24,1,0 %; ! macro TTY$V_SX_ECHAES = 764,25,1,0 %; ! macro TTY$V_SX_PRE = 764,26,1,0 %; ! macro TTY$V_SX_NINTMULTI = 764,27,1,0 %; ! macro TTY$V_SX_RECONNECT = 764,28,1,0 %; ! macro TTY$V_SX_CTSLOW = 764,29,1,0 %; ! macro TTY$V_SX_TABRIGHT = 764,30,1,0 %; ! literal TTY$S_TTYUCB = 248; ! Old size name literal TTY$S_TTYRTTUCB = 248; ! Old size name literal TTY$S_TTYUCBDEF = 768; ! Old size name, synonym for TTYUCB$S_TTYUCB literal FLG$M_CTRLO = %X'1'; literal FLG$M_CANCTRLO = %X'2'; literal FLG$M_VAXTOVAX = %X'4'; literal FLG$M_CTRLC = %X'8'; literal FLG$M_INIT = %X'10'; literal FLG$M_RESET_TIMER = %X'20'; literal FLG$M_DECNET_BUSY = %X'40'; literal FLG$M_OUTPUT_BUSY = %X'80'; literal FLG$M_READ_BUSY = %X'100'; literal FLG$M_SENSE_BUSY = %X'200'; literal FLG$M_OOB_CHAR = %X'400'; literal FLG$M_FLUSH_OUTPUT = %X'800'; literal FLG$M_CLR_NOBRDCST = %X'1000'; literal FLG$M_READ_ABORT = %X'2000'; literal FLG$M_READ_ABORTED = %X'4000'; literal FLG$M_ISUPPORT = %X'8000'; literal FLG$M_PARTIAL_READ = %X'10000'; literal UCB$S_RTT_UCB = 704; ! ! remote terminal extension ! macro UCB$R_RTTUCB = 520,0,0,0 %; literal UCB$S_RTTUCB = 178; macro UCB$L_RTT_NETUCB = 520,0,32,1 %; ! NET DEVICE UCB macro UCB$L_RTT_NETWIND = 524,0,32,1 %; ! NET DEVICE WCB macro UCB$L_RTT_IRPFL = 528,0,32,1 %; ! IRP QUEUE macro UCB$L_RTT_IRPBL = 532,0,32,1 %; ! IRP QUEUE macro UCB$L_RTT_NETIRP = 536,0,32,1 %; ! READ NET IIRP macro UCB$L_RTT_BANDINCL = 540,0,32,1 %; ! OUT OF BAND INCLUDES macro UCB$L_RTT_BANDINMSK = 544,0,32,0 %; ! OUT OF BAND INCLUDE MASK macro UCB$L_RTT_BANDEXCL = 548,0,32,0 %; ! out of band exclude mask macro UCB$L_RTT_BANDEXMSK = 552,0,32,0 %; ! out of band exclude macro UCB$B_RTT_PROVRS = 556,0,8,0 %; ! PROTOCOL VERSION macro UCB$B_RTT_PROECO = 557,0,8,0 %; ! PROTOCOL ECO macro UCB$W_RTT_LINK = 558,0,16,0 %; ! LINK NUMBER (for LOGINOUT) macro UCB$B_RTT_OBJ = 560,0,8,0 %; ! OBJECT NUMBER CONNECTED macro UCB$W_RTT_SYSTYPE = 561,0,16,0 %; ! SYSTEM TYPE (VMS=7) macro UCB$B_RTT_FILLBYTE = 563,0,8,0 %; ! fill - use when convenient ! CTERM driver only macro UCB$L_CT_FLAGS = 564,0,32,0 %; ! MISC FLAGS macro FLG$V_CTRLO = 564,0,1,0 %; ! CTRLO IN PROGRESS macro FLG$V_CANCTRLO = 564,1,1,0 %; ! CANCEL CTRLO ON WRITE macro FLG$V_VAXTOVAX = 564,2,1,0 %; ! VAX TO VAX macro FLG$V_CTRLC = 564,3,1,0 %; ! CTRL/C DELIVERED macro FLG$V_INIT = 564,4,1,0 %; ! AWAITING FIRST WRITE macro FLG$V_RESET_TIMER = 564,5,1,0 %; ! Restart timer due to write. macro FLG$V_DECNET_BUSY = 564,6,1,0 %; ! DECnet Output task busy. macro FLG$V_OUTPUT_BUSY = 564,7,1,0 %; ! Output task busy. macro FLG$V_READ_BUSY = 564,8,1,0 %; ! Read task busy. macro FLG$V_SENSE_BUSY = 564,9,1,0 %; ! Sense task busy. macro FLG$V_OOB_CHAR = 564,10,1,0 %; ! Process OOB character later. macro FLG$V_FLUSH_OUTPUT = 564,11,1,0 %; ! Flush output for out-of-band abort. macro FLG$V_CLR_NOBRDCST = 564,12,1,0 %; ! Don't broadcast until after first write. macro FLG$V_READ_ABORT = 564,13,1,0 %; ! Read abort in progress. macro FLG$V_READ_ABORTED = 564,14,1,0 %; ! Read has already been aborted. macro FLG$V_ISUPPORT = 564,15,1,0 %; ! Support of ISUPPORT msg macro FLG$V_PARTIAL_READ = 564,16,1,0 %; ! Partial read in progress macro UCB$L_CT_WIIRP = 568,0,32,1 %; ! WRITE IIRP macro UCB$L_CT_TQE = 572,0,32,1 %; ! TQE ADDRESS macro UCB$L_CT_NETQFL = 576,0,32,1 %; ! Queue of DCB's waiting macro UCB$L_CT_NETQBL = 580,0,32,1 %; ! for write IRP macro UCB$L_CT_SENSEQFL = 584,0,32,1 %; ! Queue for pending macro UCB$L_CT_SENSEQBL = 588,0,32,1 %; ! IO$_SENSExxxx IRPs. macro UCB$L_CT_READQFL = 592,0,32,1 %; ! Queue for pending macro UCB$L_CT_READQBL = 596,0,32,1 %; ! read IRPs. macro UCB$L_CT_WRTDCB = 600,0,32,1 %; ! First DCB in current write chain. macro UCB$L_CT_CURDCB = 604,0,32,1 %; ! Last DCB added to write chain. macro UCB$W_CT_REMSIZ = 608,0,16,0 %; ! Remaining size in message. macro UCB$W_CT_QDCBCNT = 610,0,16,1 %; ! Number of queued DCBs. macro UCB$W_CT_MAXMSG = 612,0,16,0 %; ! MAX WRITE TO NET SIZE macro UCB$W_CT_MAXREAD = 614,0,16,0 %; ! MAX READ IN SERVER macro UCB$L_CT_LEGALMSG = 616,0,32,0 %; ! LEGAL MESSAGE MASK macro UCB$B_CT_VERSION = 620,0,8,0 %; ! CTERM VERSION macro UCB$B_CT_ECO = 621,0,8,0 %; ! CTERM ECO macro UCB$W_CT_SPEED = 622,0,16,0 %; ! SPEED macro UCB$B_CT_CRFILL = 624,0,8,0 %; ! CR FILL macro UCB$B_CT_LFFILL = 625,0,8,0 %; ! LF FILL macro UCB$W_CT_PARITY = 626,0,16,0 %; ! CTERM PARITY macro UCB$L_CT_INCLUDE = 628,0,32,0 %; ! INCLUDE OUT-OF-BAND CHARACTER MASK macro UCB$L_CT_EXCLUDE = 632,0,32,0 %; ! EXCLUDE OUT-OF-BAND CHARACTER MASK macro UCB$L_CT_ABORT = 636,0,32,0 %; ! ABORT OUT-OF-BAND CHARACTER MASK macro UCB$B_CT_OOB_CHAR = 640,0,8,0 %; ! Received out of band character. macro UCB$B_CT_FILL_BYTE = 641,0,0,0 %; literal UCB$S_CT_FILL_BYTE = 43; ! fill macro UCB$W_CT_PRTCTL = 684,0,16,0 %; ! Same as UCB$W_TT_PRTCTL macro UCB$Q_CT_ISUPPORT = 686,0,0,0 %; literal UCB$S_CT_ISUPPORT = 8; ! Messages supported macro UCB$L_CT_FILL_LONGWORD = 694,0,32,0 %; ! fill literal UCB$C_RTT_LENGTH = 704; ! Length must be same for both RTTDRIVER literal UCB$K_RTT_LENGTH = 704; ! and CTDRIVER. !*** MODULE $FTUCBDEF *** ! ! $FTUCBDEF follows here only because there is no way to get the the ! UCB$K_TT_LENGTH into another module. ! ! Pseudo Terminal Driver definitions ! ! These definitions define the device dependent extenstions of the TTYUCB. ! Certain portions of the UCB are assumed to be contigious and must not be ! split. The AST list heads are order and must remain in order $PTDDEF in ! STARDEFMP.SDL is in the same order. ! literal UCB$M_FT_BSY = %X'1'; literal UCB$M_FT_DELPEND = %X'2'; literal UCB$M_FT_DELETE_ACT = %X'4'; literal UCB$M_FT_INPUT_CRIT = %X'8'; literal UCB$C_FT_LENGTH = 904; ! Size of FT UCB literal UCB$K_FT_LENGTH = 904; ! " " " " literal UCB$S_FT_UCB = 904; macro UCB$L_FT_IPID = 752,0,32,0 %; ! Interal PID of UCB control process macro UCB$L_FT_1ST_PAGE = 756,0,32,1 %; ! P0/P1 address of first page of I/O buffer macro UCB$L_FT_LST_PAGE = 760,0,32,1 %; ! P0/P1 address of end of the I/O buffer macro UCB$L_FT_S0_PAGE = 764,0,32,1 %; ! S0 address of first page that maps I/O buffer macro UCB$Q_FT_BUFFER_HANDLE = 768,0,0,0 %; literal UCB$S_FT_BUFFER_HANDLE = 8; ! Pointer to buffer handle used by buffer object code ! ! Driver private state information ! macro UCB$W_FT_STS = 776,0,16,0 %; ! Driver private status word macro UCB$V_FT_BSY = 776,0,1,0 %; ! Read request pending macro UCB$V_FT_DELPEND = 776,1,1,0 %; ! It is safe to queue deletion fork macro UCB$V_FT_DELETE_ACT = 776,2,1,0 %; ! Deletion fork queued macro UCB$V_FT_INPUT_CRIT = 776,3,1,0 %; ! Type ahead buffer running out or out of space macro UCB$W_FT_CHAN = 778,0,16,0 %; ! Control applications channel number macro UCB$L_FT_READQFL = 780,0,32,1 %; ! Read requests queue forward link macro UCB$L_FT_READQBL = 784,0,32,1 %; ! Read requests queue backward link macro UCB$L_FT_CURR_READ = 788,0,32,1 %; ! Currend read request packet address ! ! AST list head this must remain in order and should not be changed. ! ! The AST list head is overlaid and becomes the fork block used to delete the ! UCB when the control connection deassigns it's channel. This is safe becuase ! once the control connection channel is deleted it is impossible to enable one ! of these ASTs. ! macro UCB$R_FT_DELETE_FORK = 792,0,0,0 %; literal UCB$S_FT_DELETE_FORK = 48; macro UCB$R_FTUCB = 792,0,0,0 %; literal UCB$S_FTUCB = 44; macro UCB$L_FT_HANGUP_AST = 792,0,32,1 %; ! Address of hangup template ACB macro UCB$L_FT_XON_AST = 796,0,32,1 %; ! Address of XON template ACB macro UCB$L_FT_BELL_AST = 800,0,32,1 %; ! Address of BELL template ACB macro UCB$L_FT_DC3_AST = 804,0,32,1 %; ! Address of DC3 template ACB macro UCB$L_FT_STOP_AST = 808,0,32,1 %; ! Address of stop output template ACB macro UCB$L_FT_RESUME_AST = 812,0,32,1 %; ! Address of resume output template ACB macro UCB$L_FT_SET_AST = 816,0,32,1 %; ! Address of changed characteristics template ACB macro UCB$L_FT_ABORT_AST = 820,0,32,1 %; ! Address of abort output template ACB macro UCB$L_FT_START_READ_AST = 824,0,32,1 %; ! Address of start read template ACB macro UCB$L_FT_MIDDLE_READ_AST = 828,0,32,1 %; ! Address of middle read template ACB macro UCB$L_FT_END_READ_AST = 832,0,32,1 %; ! Address of end read template ACB macro UCB$R_FT_FORK_OVERLAY = 792,0,0,0 %; macro UCB$L_FT_FQFL = 792,0,32,1 %; ! Fork queue forward link macro UCB$L_FT_FQBL = 796,0,32,1 %; ! Fork queue backward link macro UCB$W_FT_FRKSIZE = 800,0,16,0 %; ! Size of the fork block macro UCB$B_FT_FRK_TYPE = 802,0,8,0 %; ! Type of structure macro UCB$B_FT_FLCK = 803,0,8,0 %; ! Fork lock index macro UCB$L_FT_FPC = 804,0,32,1 %; ! Fork PC this points device deletion routine macro UCB$Q_FT_FR3 = 808,0,0,1 %; literal UCB$S_FT_FR3 = 8; ! R3 will be 0 macro UCB$Q_FT_FR4 = 816,0,0,1 %; literal UCB$S_FT_FR4 = 8; ! UCB address ! End Union ! ! Add 64 bytes of storage for Access Port Name. The string is of the ! form first byte is length followed by 63 ASCII characters. ! macro UCB$B_FT_PORTNAME_STRING = 840,0,0,0 %; literal UCB$S_FT_PORTNAME_STRING = 64; literal UCB$S_FTUCBDEF = 904; ! Old size name, synonym for UCB$S_FT_UCB !*** MODULE $EMBHDDEF *** ! ! ERROR MESSAGE BUFFER HEADER ! ! Header revisions literal EMB$K_HD_REV_V50 = 2; literal EMB$K_HD_REV_V51 = 3; literal EMB$K_HD_REV_HICKORY = 4; literal EMB$K_HD_REV_V10 = 5; literal EMB$K_HD_REV_V20 = 6; literal EMB$K_HD_REV_V30 = 7; ! Header revisions literal EMB$C_HD_REV_V50 = 2; literal EMB$C_HD_REV_V51 = 3; literal EMB$C_HD_REV_HICKORY = 4; literal EMB$C_HD_REV_V10 = 5; literal EMB$C_HD_REV_V20 = 6; literal EMB$C_HD_REV_V30 = 7; ! OS ID's literal EMB$C_OS_RESERVED = 0; literal EMB$C_OS_VAXVMS = 1; literal EMB$C_OS_VAXELN = 2; literal EMB$C_OS_ALPHAVMS = 3; ! OS ID's literal EMB$K_OS_RESERVED = 0; literal EMB$K_OS_VAXVMS = 1; literal EMB$K_OS_VAXELN = 2; literal EMB$K_OS_ALPHAVMS = 3; ! This determines the SCS node name buffer size macro SCS_NAME_LEN = 0,0,0,0 %; literal S_SCS_NAME_LEN = 16; ! Define type so other EMBxxxDEF files can use it. literal EMB$C_SCS_NAME_LENGTH = 16; ! Buffer size for SCS name literal EMB$K_SCS_NAME_LENGTH = 16; ! Buffer size for SCS name literal EMB$S_EMBHD_NONFIXED = 96; ! ! Starting with HD_SID, this aggregate is common to all EMBxxxDEF modules, ! so a change here requires a corresponding change to those modules, as well ! as an increase to the header revision. ! macro EMB$L_HD_SID = 0,0,32,0 %; ! System ID macro EMB$W_HD_HDR_REV = 4,0,16,0 %; ! Header revision (in 1's complement) macro EMB$L_HD_SYSTYPE = 6,0,32,0 %; ! System type register macro EMB$W_HD_XSID_RSV = 6,0,16,0 %; ! Reserved for type-dependent info macro EMB$B_HD_XSID_REV = 8,0,8,0 %; ! Revision level of CPU macro EMB$B_HD_XSID_TYP = 9,0,8,0 %; ! Sys type, CPU type macro EMB$L_CPUID = 10,0,32,0 %; ! Unique CPU ID macro EMB$B_DEV_CLASS = 14,0,8,0 %; ! Device class macro EMB$B_DEV_TYPE = 15,0,8,0 %; ! Device type macro EMB$T_SCS_NAME = 16,0,0,0 %; literal EMB$S_SCS_NAME = 16; ! SCS node name ASCIC macro EMB$W_FLAGS = 32,0,16,0 %; ! Misc. flags macro EMB$B_OS_ID = 34,0,8,0 %; ! Logging OS ID macro EMB$B_HDRSZ = 35,0,8,0 %; ! Size of this header macro EMB$W_HD_ENTRY = 36,0,16,0 %; ! Entry type macro EMB$B_DEVTYP = 36,0,8,0 %; ! Device type macro EMB$B_DEVCLS = 37,0,8,0 %; ! Device class macro EMB$Q_HD_TIME = 38,0,0,0 %; literal EMB$S_HD_TIME = 8; ! Time of entry macro EMB$W_HD_ERRSEQ = 46,0,16,0 %; ! Error sequence number macro EMB$Q_HD_SWVERS = 48,0,0,0 %; literal EMB$S_HD_SWVERS = 8; ! Software version macro EMB$L_HD_ERRMSK = 56,0,32,0 %; ! Error mask macro EMB$L_HD_ABSTIM = 60,0,32,0 %; ! Contents of exe$gl_abstim macro EMB$B_HD_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_HD_HW_NAME = 65,0,0,0 %; literal EMB$S_HD_HW_NAME = 31; ! Marketing name of this system literal EMB$K_HD_LENGTH = 96; ! Length of header that is common to all messages literal EMB$C_HD_LENGTH = 96; ! Length of header that is common to all messages literal EMB$C_LENGTH = 16; ! LENGTH OF FIXED PART OF MESSAGE HEADER literal EMB$K_LENGTH = 16; ! LENGTH OF FIXED PART OF MESSAGE HEADER literal EMB$S_EMBHDDEF = 112; ! Old size name - synonym literal EMB$S_EMBHD = 112; macro EMB$L_SIZE = 4,0,32,0 %; ! Size of error message in bytes - new style record macro EMB$W_SIZE = 4,0,16,0 %; ! Size of error message in bytes - old style record macro EMB$L_BUFIND = 8,0,32,0 %; ! Buffer index macro EMB$B_VALID = 12,0,8,0 %; ! Error message valid indicator literal EMB$S_EMBTRAILER = 32; macro EMB$Q_TR_S2_BUF_ADDR = 0,0,0,1 %; literal EMB$S_TR_S2_BUF_ADDR = 8; macro EMB$L_TR_SPARE = 8,0,32,1 %; macro EMB$L_TR_ACTUAL_SIZE = 12,0,32,1 %; macro EMB$L_TR_ACTIVE_CPUS = 16,0,32,0 %; macro EMB$L_TR_LOGGING_CPU = 20,0,32,0 %; macro EMB$Q_TR_TDF = 24,0,0,0 %; literal EMB$S_TR_TDF = 8; literal EMB$C_TR_LENGTH = 32; ! Length of EMB trailer literal EMB$K_TR_LENGTH = 32; ! Length of EMB trailer literal EMB$M_EM_BUS = %X'1'; literal EMB$M_EM_CPU = %X'2'; literal EMB$M_EM_MEMORY = %X'4'; literal EMB$M_EM_ADAPTER = %X'8'; literal EMB$M_EM_CACHE = %X'10'; literal EMB$M_EM_VECTOR = %X'20'; literal EMB$M_RSRVD1 = %X'40'; literal EMB$S_ERRMSK_FIELDS = 4; macro EMB$V_EM_BUS = 0,0,1,0 %; ! Bus error macro EMB$V_EM_CPU = 0,1,1,0 %; ! CPU error macro EMB$V_EM_MEMORY = 0,2,1,0 %; ! Memory error macro EMB$V_EM_ADAPTER = 0,3,1,0 %; ! Adapter error macro EMB$V_EM_CACHE = 0,4,1,0 %; ! Cache error macro EMB$V_EM_VECTOR = 0,5,1,0 %; ! Vector error macro EMB$V_RSRVD1 = 0,6,1,0 %; ! Reserved literal EMB$M_FL_DDR = %X'1'; literal EMB$M_FL_OVWRT = %X'2'; literal EMB$S_FLAGS_FIELDS = 4; macro EMB$V_FL_DDR = 0,0,1,0 %; ! DDR packet flag macro EMB$V_FL_OVWRT = 0,1,1,0 %; ! Overwrite detected !*** MODULE $EMBCRDEF *** ! ! CRASH-RESTART ERROR MESSAGE BUFFER FORMAT ! literal EMB$K_CR_LENGTH = 480; literal EMB$C_CR_LENGTH = 480; literal EMB$S_EMBCRBUF = 480; macro EMB$L_CR_SID = 0,0,32,0 %; ! SYSTEM ID macro EMB$W_CR_HDR_REV = 4,0,16,0 %; ! HEADER REV LEVEL macro EMB$L_CR_XSID = 6,0,32,0 %; ! SYS_TYPE REGISTER macro EMB$L_CR_CPUID = 10,0,32,0 %; ! UNIQUE CPU ID macro EMB$B_CR_DEV_CLASS = 14,0,8,0 %; ! DEVICE CLASS macro EMB$B_CR_DEV_TYPE = 15,0,8,0 %; ! DEVICE TYPE macro EMB$B_CR_SCS_NAME = 16,0,0,0 %; literal EMB$S_CR_SCS_NAME = 16; ! SCS node name in ASCIC macro EMB$W_CR_FLAGS = 32,0,16,0 %; ! MISC. FLAGS macro EMB$B_CR_OS_ID = 34,0,8,0 %; ! LOGGING OS ID macro EMB$B_CR_HDRSZ = 35,0,8,0 %; ! HEADER SIZE macro EMB$W_CR_ENTRY = 36,0,16,0 %; ! ENTRY TYPE macro EMB$Q_CR_TIME = 38,0,0,0 %; literal EMB$S_CR_TIME = 8; ! TIME IN 64 BITS macro EMB$W_CR_ERRSEQ = 46,0,16,0 %; ! ERROR SEQUENCE NUMBER macro EMB$Q_CR_SWVERS = 48,0,0,0 %; literal EMB$S_CR_SWVERS = 8; ! SOFTWARE VERSION macro EMB$L_CR_ERRMSK = 56,0,32,0 %; ! ERROR MASK macro EMB$L_CR_ABSTIM = 60,0,32,0 %; ! CONTENTS OF EXE$GL_ABSTIM macro EMB$B_CR_HW_NAME_LEN = 64,0,8,0 %; ! Length of marketing name of this system macro EMB$T_CR_HW_NAME = 65,0,0,0 %; literal EMB$S_CR_HW_NAME = 31; ! marketing name of this system macro EMB$Q_CR_KSP = 96,0,0,0 %; literal EMB$S_CR_KSP = 8; ! KERNEL STACK POINTER macro EMB$Q_CR_ESP = 104,0,0,0 %; literal EMB$S_CR_ESP = 8; ! EXECUTIVE STACK POINTER macro EMB$Q_CR_SSP = 112,0,0,0 %; literal EMB$S_CR_SSP = 8; ! SUPERVISOR STACK POINTER macro EMB$Q_CR_USP = 120,0,0,0 %; literal EMB$S_CR_USP = 8; ! USER STACK POINTER macro EMB$Q_CR_R0 = 128,0,0,0 %; literal EMB$S_CR_R0 = 8; ! REGISTER R0 macro EMB$Q_CR_R1 = 136,0,0,0 %; literal EMB$S_CR_R1 = 8; ! REGISTER R1 macro EMB$Q_CR_R2 = 144,0,0,0 %; literal EMB$S_CR_R2 = 8; ! REGISTER R2 macro EMB$Q_CR_R3 = 152,0,0,0 %; literal EMB$S_CR_R3 = 8; ! REGISTER R3 macro EMB$Q_CR_R4 = 160,0,0,0 %; literal EMB$S_CR_R4 = 8; ! REGISTER R4 macro EMB$Q_CR_R5 = 168,0,0,0 %; literal EMB$S_CR_R5 = 8; ! REGISTER R5 macro EMB$Q_CR_R6 = 176,0,0,0 %; literal EMB$S_CR_R6 = 8; ! REGISTER R6 macro EMB$Q_CR_R7 = 184,0,0,0 %; literal EMB$S_CR_R7 = 8; ! REGISTER R7 macro EMB$Q_CR_R8 = 192,0,0,0 %; literal EMB$S_CR_R8 = 8; ! REGISTER R8 macro EMB$Q_CR_R9 = 200,0,0,0 %; literal EMB$S_CR_R9 = 8; ! REGISTER R9 macro EMB$Q_CR_R10 = 208,0,0,0 %; literal EMB$S_CR_R10 = 8; ! REGISTER R10 macro EMB$Q_CR_R11 = 216,0,0,0 %; literal EMB$S_CR_R11 = 8; ! REGISTER R11 macro EMB$Q_CR_R12 = 224,0,0,0 %; literal EMB$S_CR_R12 = 8; ! REGISTER R12 macro EMB$Q_CR_R13 = 232,0,0,0 %; literal EMB$S_CR_R13 = 8; ! REGISTER R13 macro EMB$Q_CR_R14 = 240,0,0,0 %; literal EMB$S_CR_R14 = 8; ! REGISTER R14 macro EMB$Q_CR_R15 = 248,0,0,0 %; literal EMB$S_CR_R15 = 8; ! REGISTER R15 macro EMB$Q_CR_R16 = 256,0,0,0 %; literal EMB$S_CR_R16 = 8; ! REGISTER R16 macro EMB$Q_CR_R17 = 264,0,0,0 %; literal EMB$S_CR_R17 = 8; ! REGISTER R17 macro EMB$Q_CR_R18 = 272,0,0,0 %; literal EMB$S_CR_R18 = 8; ! REGISTER R18 macro EMB$Q_CR_R19 = 280,0,0,0 %; literal EMB$S_CR_R19 = 8; ! REGISTER R19 macro EMB$Q_CR_R20 = 288,0,0,0 %; literal EMB$S_CR_R20 = 8; ! REGISTER R20 macro EMB$Q_CR_R21 = 296,0,0,0 %; literal EMB$S_CR_R21 = 8; ! REGISTER R21 macro EMB$Q_CR_R22 = 304,0,0,0 %; literal EMB$S_CR_R22 = 8; ! REGISTER R22 macro EMB$Q_CR_R23 = 312,0,0,0 %; literal EMB$S_CR_R23 = 8; ! REGISTER R23 macro EMB$Q_CR_R24 = 320,0,0,0 %; literal EMB$S_CR_R24 = 8; ! REGISTER R24 macro EMB$Q_CR_R25 = 328,0,0,0 %; literal EMB$S_CR_R25 = 8; ! REGISTER R25 macro EMB$Q_CR_R26 = 336,0,0,0 %; literal EMB$S_CR_R26 = 8; ! REGISTER R26 macro EMB$Q_CR_R27 = 344,0,0,0 %; literal EMB$S_CR_R27 = 8; ! REGISTER R27 macro EMB$Q_CR_R28 = 352,0,0,0 %; literal EMB$S_CR_R28 = 8; ! REGISTER R28 macro EMB$Q_CR_FP = 360,0,0,0 %; literal EMB$S_CR_FP = 8; ! FRAME POINTER macro EMB$Q_CR_SP = 368,0,0,0 %; literal EMB$S_CR_SP = 8; ! CURRENT STACK POINTER macro EMB$Q_CR_PC = 376,0,0,0 %; literal EMB$S_CR_PC = 8; ! PROGRAM COUNTER macro EMB$Q_CR_PSL = 384,0,0,0 %; literal EMB$S_CR_PSL = 8; ! PROCESSOR STATUS macro EMB$Q_CR_PTBR = 392,0,0,0 %; literal EMB$S_CR_PTBR = 8; ! PAGE TABLE BASE REGISTER macro EMB$Q_CR_PCBB = 400,0,0,0 %; literal EMB$S_CR_PCBB = 8; ! PRIVILEGED CONTEXT BLOCK BASE macro EMB$Q_CR_PRBR = 408,0,0,0 %; literal EMB$S_CR_PRBR = 8; ! PROCESSOR BASE REGISTER macro EMB$Q_CR_VPTB = 416,0,0,0 %; literal EMB$S_CR_VPTB = 8; ! VIRTUAL PAGE TABLE BASE REGISTER macro EMB$Q_CR_SCBB = 424,0,0,0 %; literal EMB$S_CR_SCBB = 8; ! SYSTEM CONTROL BLOCK BASE macro EMB$Q_CR_SISR = 432,0,0,0 %; literal EMB$S_CR_SISR = 8; ! SOFTWARE INTERRUPT SUMMARY REG macro EMB$Q_CR_ASN = 440,0,0,0 %; literal EMB$S_CR_ASN = 8; ! ADDRESS SPACE NUMBER macro EMB$Q_CR_ASTSR_ASTEN = 448,0,0,0 %; literal EMB$S_CR_ASTSR_ASTEN = 8; ! AST SUMMARY AND ENABLE REGS macro EMB$Q_CR_FEN = 456,0,0,0 %; literal EMB$S_CR_FEN = 8; ! FLOATING ENABLE macro EMB$Q_CR_IPL = 464,0,0,0 %; literal EMB$S_CR_IPL = 8; ! INTERRUPT PRIORITY LEVEL macro EMB$Q_CR_MCES = 472,0,0,0 %; literal EMB$S_CR_MCES = 8; ! MACHINE CHECK ERROR SUMMARY REG ! Remember start of CPU-dependent info literal EMB$S_EMBCRDEF = 484; ! Old size name - synonym literal EMB$S_EMBCR = 484; macro EMB$L_CR_CPUREG = 480,0,32,0 %; ! START OF CPU-SPECIFIC IPR'S ! CPU-specific registers for the 11/780: literal EMB$K_CR1_LENGTH = 576; literal EMB$C_CR1_LENGTH = 576; literal EMB$S_EMBCRDEF1 = 576; ! Old size name - synonym literal EMB$S_EMBCR1 = 576; macro EMB$L_CR_ICR = 480,0,32,0 %; ! INTERVAL COUNT REGISTER macro EMB$L_CR_TODR = 484,0,32,0 %; ! TIME OF DAY REGISTER macro EMB$L_CR_ACCS = 488,0,32,0 %; ! ACCELERATOR CONTROL REGISTER macro EMB$L_CR_SBIFS = 492,0,32,0 %; ! SBI FAULT STATUS macro EMB$L_CR_SBISC = 496,0,32,0 %; ! SBI COMPARATOR REGISTER macro EMB$L_CR_SBIMT = 500,0,32,0 %; ! SBI MAINT REGISTER macro EMB$L_CR_SBIER = 504,0,32,0 %; ! SBI ERROR REGISTER macro EMB$L_CR_SBITA = 508,0,32,1 %; ! SBI TIMEOUT ADDR REGISTER macro EMB$L_CR_SBIS = 512,0,0,0 %; literal EMB$S_CR_SBIS = 64; ! SBI SILO ! CPU-specific registers for the 11/750: literal EMB$K_CR2_LENGTH = 512; literal EMB$C_CR2_LENGTH = 512; literal EMB$S_EMBCRDEF2 = 512; ! Old size name - synonym literal EMB$S_EMBCR2 = 512; macro EMB$L_CR_TBDR = 492,0,32,0 %; ! TB DISABLE REGISTER macro EMB$L_CR_CADR = 496,0,32,0 %; ! CACHE DISABLE REGISTER macro EMB$L_CR_MCESR = 500,0,32,0 %; ! MACHINE CHECK ERROR SUMMARY macro EMB$L_CR_CAER = 504,0,32,0 %; ! CACHE ERROR REGISTER macro EMB$L_CR_CMIERR = 508,0,32,0 %; ! CMI ERROR SUMMARY REGISTER ! 16 UNUSED LONGWDS IN EMB literal EMB$K_CR3_LENGTH = 600; ! SIZE OF FIXED PART OF BUGCHECK MESSAGE literal EMB$C_CR3_LENGTH = 600; ! SIZE OF FIXED PART OF BUGCHECK MESSAGE literal EMB$S_EMBCRDEF3 = 600; ! Old size name - synonym literal EMB$S_EMBCR3 = 600; macro EMB$L_CR_CODE = 576,0,32,0 %; ! BUGCHECK/CRASH CODE macro EMB$L_CR_PID = 580,0,32,0 %; ! CURRENT PROCESS ID macro EMB$T_CR_LNAME = 584,0,0,0 %; literal EMB$S_CR_LNAME = 16; ! CURRENT PROCESS NAME !*** MODULE $SPLDEF *** ! ! SPINLOCK Control Block ! literal SPL$C_SPL_SPINLOCK = 1; ! Static system spinlock literal SPL$C_SPL_FORKLOCK = 2; ! Spinlock used for FORKLOCK literal SPL$C_SPL_DEVICELOCK = 3; ! Dynamic spinlock (devicelock) literal SPL$C_SPL_PORTLOCK_TEMPLATE = 4; ! Static portlock template literal SPL$C_SPL_PORTLOCK = 5; ! Dynamic ranked portlock literal SPL$M_INTERLOCK = %X'1'; literal SPL$M_DYNAMIC_THRESHOLD = %X'1'; literal SPL$M_BITMAP_POINTERS = %X'8000000000000000'; literal SPL$K_PC_VEC_CNT = 8; ! Size of PC vector literal SPL$S_SPL = 256; macro SPL$L_OWN_CPU = 0,0,32,1 %; ! Owner CPU's per-cpu database addr macro SPL$L_OWN_CNT = 4,0,32,1 %; ! Count of concurrent acquires macro SPL$W_SIZE = 8,0,16,0 %; ! Structure size macro SPL$B_TYPE = 10,0,8,0 %; ! Structure type macro SPL$B_SUBTYPE = 11,0,8,0 %; ! Spinlock subtype macro SPL$L_SPINLOCK = 12,0,32,0 %; ! Structure lock semaphore macro SPL$V_INTERLOCK = 12,0,1,0 %; ! Spinlock access interlock macro SPL$PS_SHARE_ARRAY = 16,0,32,1 %; ! Pointer for Share array macro SPL$PS_SHARE_LINK = 20,0,32,1 %; ! Pointer to the first Share ! array element macro SPL$Q_RELEASE_COUNT = 24,0,0,0 %; literal SPL$S_RELEASE_COUNT = 8; ! Count of spinlock releases macro SPL$Q_HISTORY_BITMASK = 32,0,0,0 %; literal SPL$S_HISTORY_BITMASK = 8; ! CPU bitmask of acqs in sequence macro SPL$L_RANK = 64,0,32,1 %; ! RANK of spinlock macro SPL$L_IPL = 68,0,32,0 %; ! Lock IPL macro SPL$B_IPL = 68,0,8,0 %; ! Defined for first byte only macro SPL$L_TIMO_INT = 72,0,32,0 %; ! Busywait timeout interval macro SPL$T_NAME = 76,0,0,0 %; literal SPL$S_NAME = 12; ! Spinlock name macro SPL$Q_ABUSE_THRESHOLD = 88,0,0,0 %; literal SPL$S_ABUSE_THRESHOLD = 8; ! Lock releases before abuse state macro SPL$Q_ABUSE_BITMASK = 96,0,0,0 %; literal SPL$S_ABUSE_BITMASK = 8; ! CPU bitmask that are currently abused macro SPL$Q_FLAGS = 104,0,0,0 %; literal SPL$S_FLAGS = 8; ! Behavioral flags macro SPL$V_DYNAMIC_THRESHOLD = 104,0,1,0 %; ! Set if threshold is dynamic macro SPL$V_BITMAP_POINTERS = 108,31,1,0 %; ! Set if abuse/history bitmasks are bitmap pointers macro SPL$L_RLS_PC = 128,0,32,1 %; ! PC of nested acquisition releaser macro SPL$Q_RLS_PC = 128,0,0,1 %; literal SPL$S_RLS_PC = 8; ! PC of nested acquisition releaser macro SPL$L_WAIT_CPUS = 136,0,32,1 %; ! Count of waiting CPUs ! ! After much consultation, we think that BUSY_WAITS should be unsigned. ! The MACRO-32 source treats it as an unsigned longword integer, and ! tests for overflow by testing if the value is zero. ! macro SPL$L_BUSY_WAITS = 140,0,32,0 %; ! Count of failed acquisitions macro SPL$Q_SPINS = 144,0,0,1 %; literal SPL$S_SPINS = 8; ! Count number of spins macro SPL$Q_ACQ_COUNT = 152,0,0,0 %; literal SPL$S_ACQ_COUNT = 8; ! Count of actual acquisitions ! ! Que header for singly linked deferred work. This queue header is synchronized ! by atomic updates. FKB type structures are queued to this header. If ! the queue is non-empty, the FPC routine in each FKB will be called passing ! fr3 and fr4. Note that the FLCK field is ignored. ! macro SPL$L_DEFERRED_WORK_FLINK = 160,0,32,1 %; macro SPL$L_VEC_INX = 188,0,32,1 %; ! PC vector index macro SPL$L_OWN_PC_VEC = 192,0,32,1 %; ! 8 double longword PCs of acquires/releases macro SPL$Q_OWN_PC_VEC = 192,0,0,1 %; literal SPL$S_OWN_PC_VEC = 64; ! 8 PCs of quadword acquires/releases literal SPL$K_LENGTH = 256; ! Structure size literal SPL$C_LENGTH = 256; ! Structure size literal SPL$S_SPLDEF = 256; ! Old size name, synonym for SPL$S_SPL ! ! The SPL_SHR structure is utilized for spinlocks being accessed as sharelocks. ! An array of SPL_SHR structure is allocated when a lock is going to be used ! as a sharelock by the SMP$MAKE_LOCK routine. Enough elements are allocated ! for the maximum number of CPUs possible in the system. The SPL$ structure ! will point the array via SPL$L_SHARE_ARRAY. ! ! These elements are 128 bytes to avoid CPU cache contention. ! literal SPL_SHR$K_LENGTH = 128; ! Structure size literal SPL_SHR$C_LENGTH = 128; ! Structure size literal SPL_SHR$S_SPL_SHR = 128; macro SPL_SHR$L_LINK = 0,0,32,0 %; ! Link to next Share Array Element macro SPL_SHR$L_SHARE_COUNT = 4,0,32,1 %; ! Number of Shared Acquires macro SPL_SHR$W_MBO = 8,0,16,0 %; ! must-be-one field macro SPL_SHR$B_TYPE = 10,0,8,0 %; ! Structure type (DYN$C_SPL_SHR) macro SPL_SHR$B_SUBTYPE = 11,0,8,0 %; ! Spinlock subtype (0) macro SPL_SHR$L_CPU_ID = 12,0,32,1 %; ! CPU ID associated with this element macro SPL_SHR$Q_SIZE = 16,0,0,1 %; literal SPL_SHR$S_SIZE = 8; ! Size macro SPL_SHR$Q_TIMEOUT_INT = 24,0,0,1 %; literal SPL_SHR$S_TIMEOUT_INT = 8; ! Busywait timeout interval (in ns.) literal SPLDBG$K_REV1 = 1; literal SPLDBG$K_REVISION = 1; literal SPLDBG$K_ACQ = 1; literal SPLDBG$K_REL = 2; literal SPLDBG$K_SPIN = 3; literal SPLDBG$K_FORKDSPTH = 4; literal SPLDBG$K_FORKEND = 5; literal SPLDBG$K_MAX_FLAG = 5; literal SPLDBG$K_ACQNOIPL = 1; literal SPLDBG$K_ACQUIRE = 2; literal SPLDBG$K_ACQUIREL = 3; literal SPLDBG$K_ACQNOIPL_OWN = 4; literal SPLDBG$K_ACQUIRE_OWN = 5; literal SPLDBG$K_ACQUIREL_OWN = 6; literal SPLDBG$K_ACQUIRE_SHR_OWN = 7; literal SPLDBG$K_ACQ_NOSPIN_OWN = 8; literal SPLDBG$K_ACQ_SHR_NOSPIN_OWN = 9; literal SPLDBG$K_ACQNOIPL_SPIN = 10; literal SPLDBG$K_ACQUIRE_SPIN = 11; literal SPLDBG$K_ACQUIREL_SPIN = 12; literal SPLDBG$K_RESTORE = 13; literal SPLDBG$K_RESTOREL = 14; literal SPLDBG$K_RELEASE = 15; literal SPLDBG$K_RELEASEL = 16; literal SPLDBG$K_ACQUIRE_SHR = 17; literal SPLDBG$K_ACQUIRE_SHR_SPIN = 18; literal SPLDBG$K_RELEASE_SHR = 19; literal SPLDBG$K_RESTORE_SHR = 20; literal SPLDBG$K_ACQ_NOSPIN = 21; literal SPLDBG$K_ACQ_NOSPIN_INUSE = 22; literal SPLDBG$K_ACQ_SHR_NOSPIN = 23; literal SPLDBG$K_ACQ_SHR_NOSPIN_INUSE = 24; literal SPLDBG$K_ACQ_CVT_TO_EX = 25; literal SPLDBG$K_ACQ_CVT_TO_EX_INUSE = 26; literal SPLDBG$K_ACQ_CVT_TO_EX_SPIN = 27; literal SPLDBG$K_ACQ_CVT_TO_SHR = 28; literal SPLDBG$K_MAX_MODE = 28; literal SPLDBG$M_ACQUIRE = %X'1'; literal SPLDBG$M_RELEASE = %X'2'; literal SPLDBG$M_SPINWAIT = %X'4'; literal SPLDBG$M_LCKMGR = %X'8'; literal SPLDBG$M_FORKDSPTH = %X'10'; literal SPLDBG$M_FORKEND = %X'20'; literal SPLDBG$K_LENGTH = 116; ! Structure size literal SPLDBG$C_LENGTH = 116; ! Structure size literal SPLDBG$S_SPLDBG = 120; macro SPLDBG$Q_TRACE_BUFFER = 0,0,0,1 %; literal SPLDBG$S_TRACE_BUFFER = 8; ! pointer to trace buffer macro SPLDBG$W_MBO = 8,0,16,0 %; ! must-be-one field macro SPLDBG$B_TYPE = 10,0,8,0 %; ! Structure type (DYN$C_SPLX) macro SPLDBG$B_SUBTYPE = 11,0,8,0 %; ! Spinlock subtype (DYN$C_SPLDBG) macro SPLDBG$L_REVISION = 12,0,32,0 %; ! revision field macro SPLDBG$Q_SIZE = 16,0,0,1 %; literal SPLDBG$S_SIZE = 8; ! Size macro SPLDBG$L_START_TRACE = 24,0,32,1 %; ! ptr to start trace routine macro SPLDBG$L_STOP_TRACE = 28,0,32,1 %; ! ptr to stop trace routine macro SPLDBG$L_TRACE_ACQUIRE = 32,0,32,1 %; ! ptr to trace acquire routine macro SPLDBG$L_TRACE_RELEASE = 36,0,32,1 %; ! ptr to trace release routine macro SPLDBG$L_TRACE_SPINWAIT = 40,0,32,1 %; ! ptr to trace spinwait routine macro SPLDBG$L_TRACE_FORKDSPTH = 44,0,32,1 %; ! ptr to trace fork dispatch routine macro SPLDBG$L_TRACE_FORKEND = 48,0,32,1 %; ! ptr to trace end fork routine macro SPLDBG$L_TRACE_FLAGS = 52,0,32,0 %; ! trace flags macro SPLDBG$V_ACQUIRE = 52,0,1,0 %; macro SPLDBG$V_RELEASE = 52,1,1,0 %; macro SPLDBG$V_SPINWAIT = 52,2,1,0 %; macro SPLDBG$V_LCKMGR = 52,3,1,0 %; macro SPLDBG$V_FORKDSPTH = 52,4,1,0 %; macro SPLDBG$V_FORKEND = 52,5,1,0 %; macro SPLDBG$L_SPL_FLAGS = 56,0,32,0 %; ! trace specific spinlock macro SPLDBG$L_CPU_FLAGS = 60,0,32,1 %; ! trace specific CPU macro SPLDBG$L_FRK_FLAGS = 64,0,32,0 %; ! trace specific forklock macro SPLDBG$L_TRACE_RUN = 68,0,32,0 %; ! trace run index macro SPLDBG$Q_RESERVED1 = 72,0,0,0 %; literal SPLDBG$S_RESERVED1 = 8; macro SPLDBG$Q_RESERVED2 = 80,0,0,0 %; literal SPLDBG$S_RESERVED2 = 8; macro SPLDBG$Q_RESERVED3 = 88,0,0,0 %; literal SPLDBG$S_RESERVED3 = 8; macro SPLDBG$Q_RESERVED4 = 96,0,0,0 %; literal SPLDBG$S_RESERVED4 = 8; macro SPLDBG$PQ_SCC = 104,0,32,1 %; ! pointer to array of cycle counts per possible CPU macro SPLDBG$PQ_SYSTIME = 108,0,32,1 %; ! pointer to array of systime info per possible CPU macro SPLDBG$L_MAX_CPUS = 112,0,32,1 %; literal SPLTRE$K_LENGTH = 40; ! Structure size literal SPLTRE$S_SPLTRE = 40; macro SPLTRE$Q_TIMESTAMP = 0,0,0,0 %; literal SPLTRE$S_TIMESTAMP = 8; ! timestamp in system cycle counts macro SPLTRE$Q_PC = 8,0,0,1 %; literal SPLTRE$S_PC = 8; ! callers PC or fork PC macro SPLTRE$L_CPUID = 16,0,32,0 %; ! current CPU id or address of CPU db macro SPLTRE$L_MODE = 20,0,32,0 %; ! general trace category macro SPLTRE$L_FLAG = 24,0,32,0 %; ! which event was traced macro SPLTRE$L_PCB = 28,0,32,1 %; ! current process during trace macro SPLTRE$Q_SPL_ADDR = 32,0,0,1 %; literal SPLTRE$S_SPL_ADDR = 8; ! spinlock tracing: address of spinlock macro SPLTRE$L_FLCK = 32,0,32,0 %; ! fork tracing: fork lock index literal SPLTRH$K_LENGTH = 72; ! Structure size literal SPLTRH$S_SPLTRH = 72; macro SPLTRH$L_IDX = 0,0,32,1 %; ! current index into trace buffer macro SPLTRH$L_MAX_IDX = 4,0,32,0 %; ! maximum trace index macro SPLTRH$W_MBO = 8,0,16,0 %; ! must-be-one field macro SPLTRH$B_TYPE = 10,0,8,0 %; ! Structure type (DYN$C_SPLX) macro SPLTRH$B_SUBTYPE = 11,0,8,0 %; ! Spinlock subtype (DYN$C_SPLTRH) macro SPLTRH$L_FILL1 = 12,0,32,0 %; macro SPLTRH$Q_SIZE = 16,0,0,1 %; literal SPLTRH$S_SIZE = 8; ! Size macro SPLTRH$Q_ENTRY_PTR = 24,0,0,1 %; literal SPLTRH$S_ENTRY_PTR = 8; ! pointer to first trace entry macro SPLTRH$R_ENTRY = 32,0,0,0 %; literal SPLTRH$S_ENTRY = 40; ! array of trace entries ! ! NPP data structure to hold a list of spinlock addresses ! that are not in one of SDA's known lists (static, device, ! port, mailbox, PCB, cached PCB, Pshared). ! Note that size of structure (and number of entries) can ! be changed by altering #splptr_size below. ! literal SPLPTR$C_ENTRIES = 125; ! the maximum number of addresses literal SPLPTR$C_LENGTH = 512; ! Structure size literal SPLPTR$S_SPLPTR = 512; ! Size of SPLPTR structure macro SPLPTR$PS_FLINK = 0,0,32,1 %; ! Pointer to next array macro SPLPTR$L_COUNT = 4,0,32,0 %; ! Number of entries used in this block macro SPLPTR$W_SIZE = 8,0,16,0 %; ! Structure size (SPLPTR$C_LENGTH) macro SPLPTR$B_TYPE = 10,0,8,0 %; ! Structure type (DYN$C_SPLX) macro SPLPTR$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype (DYN$C_SPLPTR) ! Number of longword entries that will fit macro SPLPTR$PS_SPINLOCK = 12,0,0,1 %; literal SPLPTR$S_SPINLOCK = 500; ! Up to n spinlock addresses !*** MODULE $DMPDEF *** ! ! LAYOUT OF THE HEADER BLOCK OF THE SYSTEM DUMP FILE ! (WHICH IS THE FIRST TWO DISK BLOCKS OF SYS$SYSTEM:SYSDUMP.DMP) ! literal DMP$M_OLDDUMP = %X'1'; literal DMP$M_EMPTY = %X'2'; literal DMP$M_HDRBLK = %X'4'; literal DMP$M_ERRLOG = %X'8'; literal DMP$M_MEMORY = %X'10'; literal DMP$M_STUB = %X'20'; literal DMP$M_WRITECOMP = %X'40'; literal DMP$M_ERRLOGCOMP = %X'80'; literal DMP$M_TRAP_VALID = %X'100'; literal DMP$M_ORIGINAL = %X'200'; literal DMP$M_COLLECT = %X'400'; literal DMP$M_PARTIAL = %X'800'; literal DMP$M_BITS_12_14 = %X'7000'; literal DMP$M_I64DUMP = %X'8000'; literal DMP$M_COMPRESSED = %X'10000'; literal DMP$M_NOTSAVED = %X'20000'; literal DMP$M_VAXDUMP = %X'40000'; literal DMP$M_ALPHADUMP = %X'80000'; literal DMP$M_BAD4GBDUMP = %X'100000'; literal DMP$M_MODIFIED = %X'200000'; literal DMP$M_SHMEMDUMP = %X'400000'; literal DMP$M_PROCDUMP = %X'800000'; literal DMP$M_BITS_24_28 = %X'1F000000'; literal DMP$M_EXCLDATA = %X'20000000'; literal DMP$M_FEN = %X'C0000000'; literal DMP$M_FEN_MFL = 1; literal DMP$M_FEN_MFH = 2; literal DMP$M_DUMPSTYLE = %X'1'; literal DMP$M_FULL_MESSAGES = %X'2'; literal DMP$M_DO_DOSD = %X'4'; literal DMP$M_COMPRESS = %X'8'; literal DMP$M_SKIP_SHARED = %X'10'; literal DMP$M_KEY_ONLY = %X'20'; literal DMP$M_BITS_6_9 = %X'3C0'; literal DMP$M_SUPER_VERBOSE = %X'400'; literal DMP$M_SKIP_SYSDISK = %X'800'; literal DMP$M_DO_GLXFATAL = %X'1000'; literal DMP$M_DISABLE_GLXRMTPFN = %X'2000'; literal DMP$M_ALLOW_HBVS_DUMPDEV = %X'4000'; literal DMP$M_DATACHECK = %X'8000'; literal DMP$M_SKIP_INIT = %X'10000'; literal DMP$M_BITS_17_23 = %X'FE0000'; literal DMP$M_MEM_STACK_PAGES = %X'F000000'; literal DMP$M_REG_STACK_PAGES = %X'F0000000'; literal DMP$K_DEFAULT_MEM_STACK_PAGES = 2; ! Default memory stack size for IA64 literal DMP$K_DEFAULT_REG_STACK_PAGES = 3; ! Default register stack size for IA64 literal DMP$K_DUMPVER = 2561; ! DUMP FILE VERSION NUMBER literal DMP$K_PROCVER = 769; ! PROCESS DUMP FILE VERSION NUMBER literal DMP$K_SHMEMVER = 769; ! SHARED MEMORY DUMP FILE VERSION NUMBER literal DMP$K_LENGTH = 1024; ! Length of dump header literal DMP$S_DMP = 1024; macro DMP$L_ERRSEQ = 0,0,32,0 %; ! LAST ERROR LOG SEQ. NUMBER macro DMP$L_FLAGS = 4,0,32,0 %; ! DUMP FILE FLAGS **** KEEP AT OFFSET 4. **** macro DMP$V_OLDDUMP = 4,0,1,0 %; ! SET IF DUMP ALREADY ANALYZED macro DMP$V_EMPTY = 4,1,1,0 %; ! SET IF DUMP HAS NO DATA BLOCKS macro DMP$V_HDRBLK = 4,2,1,0 %; ! SET IF ERROR WRITING DUMP HEADER macro DMP$V_ERRLOG = 4,3,1,0 %; ! SET IF ERROR WRITING ERROR LOGS TO DUMP FILE macro DMP$V_MEMORY = 4,4,1,0 %; ! SET IF ERROR WRITING MEMORY CONTENTS TO DUMP FILE macro DMP$V_STUB = 4,5,1,0 %; ! SET IF SYS$ERRLOG.DMP BEING WRITTEN macro DMP$V_WRITECOMP = 4,6,1,0 %; ! SET IF DUMP WRITE WAS COMPLETED macro DMP$V_ERRLOGCOMP = 4,7,1,0 %; ! SET IF HEADER/ERROR LOGS WRITE WAS COMPLETED macro DMP$V_TRAP_VALID = 4,8,1,0 %; ! Set if a trap happened macro DMP$V_ORIGINAL = 4,9,1,0 %; ! Set by BUGCHECK, cleared by SDA COPY macro DMP$V_COLLECT = 4,10,1,0 %; ! Set if a COLLECT/SAVE file macro DMP$V_PARTIAL = 4,11,1,0 %; ! Set if a partial dump not including error logs, PT space, etc, macro DMP$V_BITS_12_14 = 4,12,3,0 %; literal DMP$S_BITS_12_14 = 3; ! Spare to keep bits in old FLAGS2 in matching positions macro DMP$V_I64DUMP = 4,15,1,0 %; ! Set for IA64 dumps **** KEEP AT BIT 15. **** macro DMP$V_COMPRESSED = 4,16,1,0 %; ! SET IF DUMP DATA IS COMPRESSED (in this copy) macro DMP$V_NOTSAVED = 4,17,1,0 %; ! Set by SYSINIT if SAVEDUMP not set and dump in PAGEFILE.SYS macro DMP$V_VAXDUMP = 4,18,1,0 %; ! Never set **** KEEP AT BIT 18. **** macro DMP$V_ALPHADUMP = 4,19,1,0 %; ! Set for Alpha dumps **** KEEP AT BIT 19. **** macro DMP$V_BAD4GBDUMP = 4,20,1,0 %; ! Set if memory above 4GB written directly (no buffer pages available) macro DMP$V_MODIFIED = 4,21,1,0 %; ! Dump has been modified with /OVERRIDE macro DMP$V_SHMEMDUMP = 4,22,1,0 %; ! Galaxy Shared Memory Dump **** KEEP AT BIT 22. **** macro DMP$V_PROCDUMP = 4,23,1,0 %; ! Process dump **** KEEP AT BIT 23. **** macro DMP$V_BITS_24_28 = 4,24,5,0 %; literal DMP$S_BITS_24_28 = 5; ! Spare ! Remaining bits are specific to process dumps macro DMP$V_EXCLDATA = 4,29,1,0 %; ! Set if data wasn't saved because of insufficient privilege macro DMP$V_FEN = 4,30,2,0 %; literal DMP$S_FEN = 2; ! Set if FEN was set in the process ! (Only 1 bit used on Alpha, both bits on IPF) macro DMP$L_DUMPSTYLE = 8,0,32,0 %; ! Setting of SYSGEN parameter DUMPSTYLE when dump written macro DMP$V_DUMPSTYLE = 8,0,1,0 %; ! Full vs. Selective macro DMP$V_FULL_MESSAGES = 8,1,1,0 %; ! Minimal console output vs. Verbose macro DMP$V_DO_DOSD = 8,2,1,0 %; ! System disk vs. DOSD disk macro DMP$V_COMPRESS = 8,3,1,0 %; ! Raw vs. Compressed (when writing the original dump) macro DMP$V_SKIP_SHARED = 8,4,1,0 %; ! Dump shared memory vs. Don't dump it macro DMP$V_KEY_ONLY = 8,5,1,0 %; ! Only dump system space, key processes, key global pages macro DMP$V_BITS_6_9 = 8,6,4,0 %; literal DMP$S_BITS_6_9 = 4; ! Spare bits for future documented features macro DMP$V_SUPER_VERBOSE = 8,10,1,0 %; ! Diagnostics macro DMP$V_SKIP_SYSDISK = 8,11,1,0 %; ! Don't touch system disk macro DMP$V_DO_GLXFATAL = 8,12,1,0 %; ! Force Galaxy-wide crash macro DMP$V_DISABLE_GLXRMTPFN = 8,13,1,0 %; ! Disable Galaxy remote PFN checks macro DMP$V_ALLOW_HBVS_DUMPDEV = 8,14,1,0 %; ! Allow DOSD to be shadow set member macro DMP$V_DATACHECK = 8,15,1,0 %; ! Do a datacheck read after each write I/O macro DMP$V_SKIP_INIT = 8,16,1,0 %; ! Don't fill in the SCB/IDT (i.e. primitive exception display) ! **** Note: SKIP_INIT is not dynamic in SYSGEN!!!! **** macro DMP$V_BITS_17_23 = 8,17,7,0 %; literal DMP$S_BITS_17_23 = 7; ! Spare bits for future undocumented features macro DMP$V_MEM_STACK_PAGES = 8,24,4,0 %; literal DMP$S_MEM_STACK_PAGES = 4; ! Additional pages for BUGCHECK's stack macro DMP$V_REG_STACK_PAGES = 8,28,4,0 %; literal DMP$S_REG_STACK_PAGES = 4; ! Additional pages for BUGCHECK's stack (only useful on IA64) macro DMP$W_MEMMAP_ENTRIES = 12,0,16,0 %; ! Entries in memory map (full dump) macro DMP$W_ERLBUFPAGES = 14,0,16,0 %; ! # pagelets / S0 error log buffer macro DMP$Q_PTBR = 16,0,0,0 %; literal DMP$S_PTBR = 8; ! PAGE TABLE BASE REGISTER (SYSPTBR if VIRBND or IA64) macro DMP$Q_KSP = 24,0,0,0 %; literal DMP$S_KSP = 8; ! KERNEL STACK POINTER macro DMP$Q_ESP = 32,0,0,0 %; literal DMP$S_ESP = 8; ! EXECUTIVE STACK POINTER macro DMP$Q_SSP = 40,0,0,0 %; literal DMP$S_SSP = 8; ! SUPERVISOR STACK POINTER macro DMP$Q_USP = 48,0,0,0 %; literal DMP$S_USP = 8; ! USER STACK POINTER macro DMP$Q_SYSIDENT = 56,0,0,0 %; literal DMP$S_SYSIDENT = 8; ! TEXT ident for SYS.EXE **** KEEP AT OFFSET 56. **** macro DMP$L_ERLBUFADR = 64,0,32,1 %; ! Address of S0 error log buffers macro DMP$W_PAGEBITS = 68,0,16,0 %; ! NUMBER OF BITS IN PAGE INDEX macro DMP$W_VA_BITS = 70,0,16,0 %; ! NUMBER OF BITS IN VIRTUAL ADDRESS macro DMP$L_SYMVECT_VA = 72,0,32,1 %; ! ABSOLUTE VIRTUAL ADDRESS OF SYMBOL VECTOR IN MEMORY macro DMP$L_SYMVECT_END = 76,0,32,1 %; ! ABSOLUTE VIRTUAL ADDRESS OF END OF SYMBOL VECTOR IN MEMORY macro DMP$L_DUMPBLOCKCNT = 80,0,32,0 %; ! COUNT OF BLOCKS DUMPED macro DMP$L_NOCOMPBLOCKCNT = 84,0,32,0 %; ! As DUMPBLOCKCNT with no compression macro DMP$L_SYSVER = 88,0,32,0 %; ! SYSTEM VERSION NUMBER **** KEEP AT OFFSET 88. **** macro DMP$L_CHECK = 92,0,32,0 %; ! ONES COMPLEMENT OF SYSVER **** KEEP AT OFFSET 92. **** macro DMP$W_DUMPVER = 96,0,16,0 %; ! DUMP FILE VERSION NUMBER **** KEEP AT OFFSET 96. **** macro DMP$W_ERLBUFCNT = 98,0,16,0 %; ! # S0 error log buffers macro DMP$W_ERLBUFHEAD = 100,0,16,0 %; ! Index of next S0 error log buffer to be written to file macro DMP$W_ERLBUFTAIL = 102,0,16,0 %; ! Index of next available S0 error log buffer macro DMP$Q_L2_BASE = 104,0,0,0 %; literal DMP$S_L2_BASE = 8; ! Crash-time contents of mmg$gq_l2_base macro DMP$Q_L1_BASE = 112,0,0,0 %; literal DMP$S_L1_BASE = 8; ! Crash-time contents of mmg$gq_l1_base macro DMP$Q_PT_BASE = 120,0,0,0 %; literal DMP$S_PT_BASE = 8; ! Crash-time contents of mmg$gq_pt_base macro DMP$Q_CRASHTIME = 128,0,0,0 %; literal DMP$S_CRASHTIME = 8; ! Crash date/time macro DMP$Q_LINKTIME = 136,0,0,0 %; literal DMP$S_LINKTIME = 8; ! Link date/time of base image in system dumped macro DMP$L_CHFCTXADR = 144,0,32,1 %; ! Base address of CHFCTX block (process dumps) macro DMP$L_CALL_HANDL = 148,0,32,1 %; ! Address of SYS$GL_CALL_HANDL (process dumps) macro DMP$L_ASTDEL = 152,0,32,1 %; ! Address of SYS$GL_ASTDEL (process dumps) macro DMP$L_ASTDEL_K = 156,0,32,1 %; ! Address of SYS$GL_ASTDEL_K (process dumps) macro DMP$L_ERRSTATUS = 160,0,32,0 %; ! LAST ERROR STATUS FROM DUMP WRITE macro DMP$L_DUMPERRS = 164,0,32,0 %; ! COUNT OF ERRORS DURING DUMP WRITE macro DMP$L_MAXCOMPENTRIES = 168,0,32,0 %; ! Worst case count of compression map entries in dump macro DMP$L_SHORTBLOCKCNT = 172,0,32,0 %; ! THE NUMBER OF ADDITIONAL BLOCKS NEEDED FOR COMPLETE DUMP macro DMP$L_COMPENTRYPAGES = 176,0,32,0 %; ! Max # pages mapped by a data compression map entry macro DMP$L_SAVEPRCCNT = 180,0,32,0 %; ! Count of saved processes (subset dump) macro DMP$W_SAVERADCNT = 184,0,16,0 %; ! Count of saved RADs (selective dump) macro DMP$W_REGIONCNT = 186,0,16,0 %; ! Count of regions dumped (shared memory) macro DMP$L_PCBVEC = 188,0,32,1 %; ! Pointer to PCB vector (Process dumps) macro DMP$L_TEB_ADDR = 192,0,32,1 %; ! Address of thread environment block (Process dumps) macro DMP$L_MAXPIX = 196,0,32,0 %; ! Highest process index (Process dumps) macro DMP$L_L1_INDEX = 200,0,32,0 %; macro DMP$L_LEVEL_WIDTH = 204,0,32,0 %; macro DMP$L_NPAGEDYN = 208,0,32,1 %; macro DMP$L_BALBASE = 212,0,32,1 %; macro DMP$L_BAL_END = 216,0,32,1 %; macro DMP$L_BSLOTSZ = 220,0,32,0 %; macro DMP$L_PIXBAS = 224,0,32,1 %; macro DMP$L_KTB_ADDRESS = 228,0,32,1 %; macro DMP$L_SYSPHD = 232,0,32,1 %; macro DMP$L_HPDESC = 236,0,32,1 %; macro DMP$Q_SYS_VIRT_BASE = 240,0,0,0 %; literal DMP$S_SYS_VIRT_BASE = 8; macro DMP$Q_SHARED_VA_PTES = 248,0,0,0 %; literal DMP$S_SHARED_VA_PTES = 8; macro DMP$Q_GPT_BASE = 256,0,0,0 %; literal DMP$S_GPT_BASE = 8; macro DMP$Q_MAX_GPTE = 264,0,0,0 %; literal DMP$S_MAX_GPTE = 8; macro DMP$Q_PFN_DATABASE = 272,0,0,0 %; literal DMP$S_PFN_DATABASE = 8; macro DMP$B_ASTSR_ASTEN = 280,0,8,0 %; ! AST summary register and AST enable bits (process dumps only) macro DMP$B_TRAPINFO_BLKS = 281,0,8,0 %; ! # blocks set aside for trap data macro DMP$B_CRASHERL_BLKS = 282,0,8,0 %; ! # blocks for crash error log entry macro DMP$B_IMGDMP_ICB_BLKS = 283,0,8,0 %; ! # blocks used for invocation context (process dumps only) macro DMP$B_IMGDMP_REG_BLKS = 284,0,8,0 %; ! # blocks used for internal registers (process dumps only) macro DMP$T_NODENAME = 287,0,0,0 %; literal DMP$S_NODENAME = 9; ! ASCIC node name macro DMP$T_PROCNAME = 296,0,0,0 %; literal DMP$S_PROCNAME = 16; ! ASCIC process name macro DMP$T_MODELNAME = 312,0,0,0 %; literal DMP$S_MODELNAME = 32; ! ASCIC model name macro DMP$L_BUGCODE = 344,0,32,0 %; ! The bugcheck code macro DMP$L_MCH_ARRAY = 348,0,32,1 %; ! Address of the mechanism array (process dumps) macro DMP$Q_ERLBUFADR_S2 = 352,0,0,1 %; literal DMP$S_ERLBUFADR_S2 = 8; ! Address of S2 error log buffers macro DMP$L_ERLBUFPAGES_S2 = 360,0,32,0 %; ! # pagelets / S2 error log buffer macro DMP$L_ERLBUFCNT_S2 = 364,0,32,0 %; ! # S2 error log buffers macro DMP$L_ERLBUFHEAD_S2 = 368,0,32,0 %; ! Index of next S2 error log buffer to be written to file macro DMP$L_ERLBUFTAIL_S2 = 372,0,32,0 %; ! Index of next available S2 error log buffer macro DMP$L_COLLECT_TOTAL = 376,0,32,0 %; ! The total size of the file-ID + unwind-data collection macro DMP$L_COLLECT_DISK = 380,0,32,0 %; ! The size of the disk portion of the collection ! (a subset of and the final blocks of COLLECT_TOTAL) macro DMP$L_KEYBLOCKCNT = 384,0,32,0 %; ! Count of blocks dumped for system space, key processes, key globals macro DMP$L_NOCOMPKEYCNT = 388,0,32,0 %; ! As KEYBLOCKCNT with no compression macro DMP$L_COMPENTRIES = 392,0,32,0 %; ! Count of compression map entries in this (partial copy of a) dump macro DMP$L_FRAGBLOCKS = 396,0,32,0 %; ! Number of blocks BUGCHECK could use because file too fragmented macro DMP$L_ADD_PCB_ASTCNT = 400,0,32,1 %; ! ASTCNT adjustment required to take process dump macro DMP$L_ADD_PCB_BIOCNT = 404,0,32,1 %; ! BIOCNT adjustment required to take process dump macro DMP$L_ADD_PCB_DIOCNT = 408,0,32,1 %; ! DIOCNT adjustment required to take process dump macro DMP$L_ADD_JIB_BYTCNT = 412,0,32,1 %; ! BYTCNT adjustment required to take process dump macro DMP$L_ADD_JIB_FILCNT = 416,0,32,1 %; ! FILCNT adjustment required to take process dump macro DMP$L_ADD_JIB_TQCNT = 420,0,32,1 %; ! TQCNT adjustment required to take process dump macro DMP$L_ADD_JIB_PGFLCNT = 424,0,32,1 %; ! PGFLCNT adjustment required to take process dump macro DMP$L_ADD_JIB_ENQCNT = 428,0,32,1 %; ! ENQCNT adjustment required to take process dump macro DMP$Q_ADD_PHD_CPULIM = 432,0,0,0 %; literal DMP$S_ADD_PHD_CPULIM = 8; ! CPULIM adjustment required to take process dump ! (not yet used, but would be recorded as a delta time) macro DMP$Q_WSLBASE = 440,0,0,0 %; literal DMP$S_WSLBASE = 8; ! Base address of working set pages in S2 space (process dumps) macro DMP$Q_WSL_END = 448,0,0,0 %; literal DMP$S_WSL_END = 8; ! End address of working set pages in S2 space (process dumps) macro DMP$T_EXTRA_SPACE = 456,0,0,0 %; literal DMP$S_EXTRA_SPACE = 564; macro DMP$L_CHECKSUM = 1020,0,32,0 %; ! Last longword of 2-block header **** KEEP AT OFFSET 1020. **** literal DMP$K_VAX_EMB_LENGTH = 12; ! Length of EMB header on VAX literal DMP$S_DMP_COMPAT = 136; macro DMP$Q_V731_SYSIDENT = 48,0,0,0 %; literal DMP$S_V731_SYSIDENT = 8; ! TEXT ident for SYS.EXE **** KEEP AT OFFSET 48. **** macro DMP$Q_VAX_EMBCR_SWVERS = 48,0,0,0 %; literal DMP$S_VAX_EMBCR_SWVERS = 8; ! SOFTWARE VERSION IN VAX CRASH ERRLOG **** KEEP AT OFFSET 48. **** macro DMP$L_PRE_V731_SYSVER = 68,0,32,0 %; ! SYSTEM VERSION NUMBER **** KEEP AT OFFSET 68. **** macro DMP$L_PRE_V731_CHECK = 72,0,32,0 %; ! ONES COMPLEMENT OF SYSVER **** KEEP AT OFFSET 72. **** macro DMP$W_PRE_V731_DUMPVER = 76,0,16,0 %; ! DUMP FILE VERSION NUMBER **** KEEP AT OFFSET 76. **** macro DMP$Q_PRE_V731_SYSIDENT = 104,0,0,0 %; literal DMP$S_PRE_V731_SYSIDENT = 8; ! TEXT ident for SYS.EXE **** KEEP AT OFFSET 104. **** macro DMP$L_COMPAT_FILL_4 = 104,0,32,0 %; macro DMP$W_VAX_DUMPVER = 108,0,16,0 %; ! DUMP FILE VERSION NUMBER ON VAX **** KEEP AT OFFSET 108. **** macro DMP$W_COMPAT_FILL_5 = 110,0,16,0 %; macro DMP$L_VAX_CRASHERL = 132,0,32,0 %; ! SYSTEM CRASH ERR LOG ENTRY ON VAX **** KEEP AT OFFSET 132. **** literal DMP$K_TRAPINFO_LENGTH = 1024; ! Length of trap entry buffer literal DMP$S_DMP_TRAPINFO_ENTRY = 1024; macro DMP$T_TRAPINFO = 0,0,0,0 %; literal DMP$S_TRAPINFO = 768; macro DMP$PQ_TRAP_INTSTK = 768,0,0,1 %; literal DMP$S_TRAP_INTSTK = 8; ! address of INTSTK structure macro DMP$T_TRAPINFO_FILL = 776,0,0,0 %; literal DMP$S_TRAPINFO_FILL = 248; literal DMP$K_CRASHERL_LENGTH = 1024; ! Length of crash error log buffer literal DMP$S_DMP_CRASHERL_ENTRY = 1024; macro DMP$T_CRASHERL_ENTRY_FILL = 616,0,0,0 %; literal DMP$S_CRASHERL_ENTRY_FILL = 408; literal DMP$K_IMGDMP_ICB_LENGTH = 2560; ! Length of invo context block literal DMP$S_DMP_IMGDMP_ICB = 2560; macro DMP$R_IMGDMP_ICB = 0,0,0,0 %; literal DMP$S_IMGDMP_ICB = 2112; literal DMP$K_IMGDMP_REGS_LENGTH = 512; ! Length of general registers literal DMP$S_DMP_IMGDMP_REGS = 512; macro DMP$Q_IMGDMP_IPSR = 0,0,0,0 %; literal DMP$S_IMGDMP_IPSR = 8; macro DMP$Q_IMGDMP_ISR = 8,0,0,0 %; literal DMP$S_IMGDMP_ISR = 8; macro DMP$Q_IMGDMP_KBSP = 16,0,0,0 %; literal DMP$S_IMGDMP_KBSP = 8; ! Kernel BSP macro DMP$Q_IMGDMP_EBSP = 24,0,0,0 %; literal DMP$S_IMGDMP_EBSP = 8; ! Executive BSP macro DMP$Q_IMGDMP_SBSP = 32,0,0,0 %; literal DMP$S_IMGDMP_SBSP = 8; ! Supervisor BSP macro DMP$Q_IMGDMP_UBSP = 40,0,0,0 %; literal DMP$S_IMGDMP_UBSP = 8; ! User BSP literal DMP$M_NODUMP = %X'1'; literal DMP$M_POWEROFF = %X'2'; literal DMP$M_BADMEMORY = %X'4'; literal DMP$M_BIB_STATE = %X'8'; literal DMP$M_LONG_FILL = %X'FFFFFFF0'; literal DMP$S_DUMPMASK = 4; macro DMP$V_NODUMP = 0,0,1,0 %; ! Do not write dumpfile macro DMP$V_POWEROFF = 0,1,1,0 %; ! Request power off of system macro DMP$V_BADMEMORY = 0,2,1,0 %; ! Memory is too broken to try dumping it macro DMP$V_BIB_STATE = 0,3,1,0 %; ! Request shutdown to BIB state literal DMP$C_FRAG_GCT = -1; ! if all bits set then GCT fragment literal DMP$K_FRAG_MAP_LENGTH = 32; literal DMP$C_FRAG_MAP_LENGTH = 32; literal DMP$S_DMP_MEMMAP = 32; macro DMP$L_FRAG_MAP_LENGTH = 0,0,32,1 %; ! Size of structure macro DMP$L_FRAG_FLAGS = 4,0,32,0 %; ! See [STARLET]PMMDEF.SDL for these macro DMP$Q_FRAG_START_PFN = 8,0,0,0 %; literal DMP$S_FRAG_START_PFN = 8; ! Start PFN of fragment macro DMP$Q_FRAG_LENGTH = 16,0,0,0 %; literal DMP$S_FRAG_LENGTH = 8; ! Actual block count for memory fragment macro DMP$Q_FRAG_NOCOMP_LENGTH = 24,0,0,0 %; literal DMP$S_FRAG_NOCOMP_LENGTH = 8; ! As FRAG_LENGTH without compression literal DMP$M_SPARE = %X'7FF'; literal DMP$M_LMBHDR = %X'800'; literal DMP$M_UNCOMP = %X'1000'; literal DMP$M_OVERRUN = %X'2000'; literal DMP$M_IO_ERROR = %X'4000'; literal DMP$M_NOCOMP = %X'8000'; literal DMP$K_REPEAT = 0; ! Repeated character sequence literal DMP$K_REENCODE_1 = 1; ! 1-bit re-encoding literal DMP$K_REENCODE_2 = 2; ! 2-bit re-encoding literal DMP$K_REENCODE_3 = 3; ! 3-bit re-encoding literal DMP$K_REENCODE_4 = 4; ! 4-bit re-encoding literal DMP$K_REENCODE_5 = 5; ! 5-bit re-encoding literal DMP$K_REENCODE_6 = 6; ! 6-bit re-encoding literal DMP$K_BITMAP_1 = 7; ! Bitmap (one dominant character) literal DMP$K_BITMAP_3 = 8; ! Bitmap (2-3 dominant characters) literal DMP$K_BITMAP_7 = 9; ! Bitmap (4-7 dominant characters) literal DMP$K_INCREMENT = 10; ! Incrementing character sequence literal DMP$K_DECREMENT = 11; ! Decrementing character sequence literal DMP$K_NOCOMP = 12; ! No compression literal DMP$K_COMPRESSION_TYPES = 13; ! Number of types literal DMP$M_RECOMP = 32; ! Recompressed section literal DMP$M_FINAL = 64; ! Final section to restore literal DMP$M_FIRST = 128; ! Section is first in a "raw" read literal DMP$S_DMP_CBLOCK = 8; macro DMP$Q_COMP_ENTRY = 0,0,0,0 %; literal DMP$S_COMP_ENTRY = 8; ! An entire entry macro DMP$L_COMP_ENDING_VBN = 0,0,32,0 %; ! Final uncompressed VBN from this section macro DMP$W_COMP_BLOCKS = 4,0,16,0 %; ! The count of compressed blocks in this section macro DMP$W_COMP_FLAGS = 6,0,16,0 %; ! Flags for this section macro DMP$V_LMBHDR = 6,11,1,0 %; ! LMB header (so we can distinguish from map entries for holes) macro DMP$V_UNCOMP = 6,12,1,0 %; ! Uncompressed data section macro DMP$V_OVERRUN = 6,13,1,0 %; ! Dumpfile filled while writing this section macro DMP$V_IO_ERROR = 6,14,1,0 %; ! I/O error occurred while writing this section macro DMP$V_NOCOMP = 6,15,1,0 %; ! Non-compressed section (LMB header, holes) ! Compression types literal DMP$K_SQUEEZE_LENGTH = 72; literal DMP$K_MAX_COMPRESSIONS = 4; literal DMP$K_MAX_IO_RAW = 32768; literal DMP$K_MAX_IO_112 = 57344; ! max full-page I/O without split literal DMP$K_MAX_IO_124 = 63488; ! max raw data when no compression possible literal DMP$K_MAX_IO_127 = 65024; ! max regular I/O without split literal DMP$K_MAX_IO = 65536; literal DMP$K_COMP_LENGTH = 2048; literal DMP$K_MIN_REPEAT = 16; literal DMP$K_ERROR_COUNT = 156; literal DMP$K_OVERRUN_COUNT = 159; literal DMP$K_STATS_ENTRIES = 162; literal DMP$K_SHORT_STATS = 39; literal DMP$S_DMP_SQUEEZE = 72; macro DMP$PQ_OUTPUT_START = 0,0,0,1 %; literal DMP$S_OUTPUT_START = 8; ! The output buffer being filled macro DMP$PQ_SQUEEZE_WORK = 8,0,0,1 %; literal DMP$S_SQUEEZE_WORK = 8; ! Address of the work area into which data is initially compressed macro DMP$PQ_BYTE_TABLE = 16,0,0,1 %; literal DMP$S_BYTE_TABLE = 8; ! Address of array where byte values are counted macro DMP$L_OUTPUT_USED = 24,0,32,1 %; ! How much of the output buffer has been used macro DMP$L_PRIOR_UNCOMP = 28,0,32,1 %; ! Length of prior uncompressed section in output buffer macro DMP$L_CURRENT_UNCOMP = 32,0,32,1 %; ! Offset to start of current uncompressed section in output buffer macro DMP$L_SQUEEZE_FLAGS = 36,0,32,1 %; ! DMP$M_UNCOMP gets set in here when an uncompressible section is created macro DMP$L_BASE_VBN = 40,0,32,1 %; ! Raw VBN of base of LMB (always zero in full dumps) macro DMP$PQ_WRITE_COMPRESSED_BLOCKS = 48,0,0,1 %; literal DMP$S_WRITE_COMPRESSED_BLOCKS = 8; ! Callback routine to write buffer contents macro DMP$PQ_SQUEEZE_STATS = 56,0,0,1 %; literal DMP$S_SQUEEZE_STATS = 8; ! Pointer to statistics array - 3 quadwords for each compression type ! for each compression attempt macro DMP$L_SQUEEZE_UNCOMP_COUNT = 64,0,32,0 %; macro DMP$L_SQUEEZE_MERGE_COUNT = 68,0,32,0 %; literal DMP$K_EXPLODE_LENGTH = 40; literal DMP$S_DMP_EXPLODE = 40; macro DMP$PS_INPUT_START = 0,0,32,1 %; ! The input buffer being processed macro DMP$PS_EXPLODE_WORK = 4,0,32,1 %; ! Address of the work area into which data is initially decompressed macro DMP$L_INPUT_USED = 8,0,32,1 %; ! How much of the input buffer has been used macro DMP$L_EXPLODE_FLAGS = 12,0,32,1 %; ! DMP$M_UNCOMP gets set in here when an uncompressible section is processed macro DMP$L_LOWEST_VBN = 16,0,32,1 %; ! Lowest VBN exploded left in the output buffer macro DMP$L_HIGHEST_VBN = 20,0,32,1 %; ! Highest VBN exploded left in the output buffer macro DMP$PS_READ_COMPRESSED_BLOCKS = 24,0,32,1 %; ! Callback routine to read more compressed data into the input buffer macro DMP$PS_EXPLODE_STATS = 28,0,32,1 %; ! Pointer to statistics array - 3 quadwords for each compression type ! for each decompression pass macro DMP$L_EXPLODE_UNCOMP_COUNT = 32,0,32,0 %; macro DMP$PS_EXPLODE_FILEDATA = 36,0,32,1 %; ! Pointer to the file_data stucture for the file being processed literal DMP_DISK$M_NO_ACCESS = %X'1'; literal DMP_DISK$M_SEPARATE = %X'2'; literal DMP_DISK$M_UNCOMBINED = %X'4'; literal DMP_DISK$K_LENGTH = 45; ! Base length of DMP_DISK_DATA literal DMP_DISK$S_DMP_DISK_DATA = 45; macro DMP_DISK$PQ_NEXT = 0,0,0,1 %; literal DMP_DISK$S_NEXT = 8; ! Pointer to next DMP_DISK_DATA structure macro DMP_DISK$PQ_FILE = 8,0,0,1 %; literal DMP_DISK$S_FILE = 8; ! Pointer to first DMP_FILE_DATA for this disk macro DMP_DISK$L_VBN = 16,0,32,0 %; ! Relative VBN in collection for this disk's file/code/etc data macro DMP_DISK$L_BLOCKS = 20,0,32,0 %; ! Count of blocks for this disk's file/code/etc data macro DMP_DISK$Q_DISK_DATA_LENGTH = 24,0,0,1 %; literal DMP_DISK$S_DISK_DATA_LENGTH = 8; ! Length of this DMP_DISK_DATA structure macro DMP_DISK$Q_DISK_DATA_TOTAL = 32,0,0,1 %; literal DMP_DISK$S_DISK_DATA_TOTAL = 8; ! Total length of all this disk's file/code/etc structures macro DMP_DISK$W_FLAGS = 40,0,16,0 %; macro DMP_DISK$V_NO_ACCESS = 40,0,1,0 %; ! Unable to access the disk macro DMP_DISK$V_SEPARATE = 40,1,1,0 %; ! This DMP_DISK_DATA was allocated separately (pre-reorg) macro DMP_DISK$V_UNCOMBINED = 40,2,1,0 %; ! The attached file/code/etc were allocated separately macro DMP_DISK$W_NAME_LENGTH = 42,0,16,0 %; ! Length of the disk name macro DMP_DISK$T_NAME = 44,0,8,0 %; literal DMP_DISK$S_NAME = 1; ! Start of the disk name literal DMP_FILE$M_NO_ACCESS = %X'1'; literal DMP_FILE$M_NO_UNWIND = %X'2'; literal DMP_FILE$M_SEPARATE = %X'4'; literal DMP_FILE$M_COUNTED = %X'8'; literal DMP_FILE$K_LENGTH = 53; ! Base length of DMP_FILE_DATA literal DMP_FILE$S_DMP_FILE_DATA = 53; macro DMP_FILE$PQ_NEXT = 0,0,0,1 %; literal DMP_FILE$S_NEXT = 8; ! Pointer to next DMP_FILE_DATA for this disk macro DMP_FILE$PQ_CODE = 8,0,0,1 %; literal DMP_FILE$S_CODE = 8; ! Pointer to first DMP_CODE_DATA for this file macro DMP_FILE$PQ_UNWIND = 16,0,0,1 %; literal DMP_FILE$S_UNWIND = 8; ! Pointer to first DMP_UNWIND_DATA for this file macro DMP_FILE$W_FID_NUM = 24,0,16,0 %; ! File number macro DMP_FILE$W_FID_SEQ = 26,0,16,0 %; ! File sequence number macro DMP_FILE$B_FID_RVN = 28,0,8,0 %; ! Short form relative volume number macro DMP_FILE$B_FID_NMX = 29,0,8,0 %; ! File number extension macro DMP_FILE$Q_FILE_DATA_LENGTH = 32,0,0,1 %; literal DMP_FILE$S_FILE_DATA_LENGTH = 8; ! Length of this DMP_FILE_DATA structure macro DMP_FILE$L_STATUS = 40,0,32,0 %; ! Status when we tried to open the file macro DMP_FILE$L_STV = 44,0,32,0 %; ! Corresponding STV if relevant macro DMP_FILE$W_FLAGS = 48,0,16,0 %; macro DMP_FILE$V_NO_ACCESS = 48,0,1,0 %; ! Unable to access the file macro DMP_FILE$V_NO_UNWIND = 48,1,1,0 %; ! An image file but no unwind data (e.g. message file) macro DMP_FILE$V_SEPARATE = 48,2,1,0 %; ! This DMP_FILE_DATA was allocated separately (pre-reorg) macro DMP_FILE$V_COUNTED = 48,3,1,0 %; ! Any DMP_UNWIND_DATAs for this file have been counted macro DMP_FILE$W_NAME_LENGTH = 50,0,16,0 %; ! Length of the file name macro DMP_FILE$T_NAME = 52,0,8,0 %; literal DMP_FILE$S_NAME = 1; ! Start of the file name literal DMP_CODE$M_SEPARATE = %X'1'; literal DMP_CODE$K_LENGTH = 64; ! Length of DMP_CODE_DATA literal DMP_CODE$S_DMP_CODE_DATA = 64; macro DMP_CODE$PQ_NEXT = 0,0,0,1 %; literal DMP_CODE$S_NEXT = 8; ! Pointer to next DMP_CODE_DATA for this file macro DMP_CODE$PQ_UNWIND = 8,0,0,1 %; literal DMP_CODE$S_UNWIND = 8; ! Pointer to DMP_UNWIND_DATA for this code segment macro DMP_CODE$Q_SEGNUM = 16,0,0,1 %; literal DMP_CODE$S_SEGNUM = 8; ! Code segment number macro DMP_CODE$PQ_CODE_OFFSET = 24,0,0,1 %; literal DMP_CODE$S_CODE_OFFSET = 8; ! Start offset of this code segment within the image macro DMP_CODE$Q_CODE_SIZE = 32,0,0,1 %; literal DMP_CODE$S_CODE_SIZE = 8; ! Size of this code segment macro DMP_CODE$Q_INFO_OFFSET = 40,0,0,1 %; literal DMP_CODE$S_INFO_OFFSET = 8; ! Start offset within unwind segment for this code segment macro DMP_CODE$Q_INFO_SIZE = 48,0,0,1 %; literal DMP_CODE$S_INFO_SIZE = 8; ! Size of unwind data for this code segment macro DMP_CODE$W_FLAGS = 56,0,16,0 %; macro DMP_CODE$V_SEPARATE = 56,0,1,0 %; ! This DMP_CODE_DATA was allocated separately (pre-reorg) literal DMP_UNWIND$M_NOT_HERE = %X'1'; literal DMP_UNWIND$M_SEPARATE = %X'2'; literal DMP_UNWIND$K_LENGTH = 80; ! Length of DMP_UNWIND_DATA literal DMP_UNWIND$S_DMP_UNWIND_DATA = 80; macro DMP_UNWIND$PQ_NEXT = 0,0,0,1 %; literal DMP_UNWIND$S_NEXT = 8; ! Pointer to next DMP_UNWIND_DATA for this file macro DMP_UNWIND$PQ_SEGMENT = 8,0,0,1 %; literal DMP_UNWIND$S_SEGMENT = 8; ! Address of in-memory copy of actual unwind segment macro DMP_UNWIND$Q_SEGLEN = 16,0,0,1 %; literal DMP_UNWIND$S_SEGLEN = 8; ! Length of in-memory copy of the unwind segment macro DMP_UNWIND$Q_SEGNUM = 24,0,0,1 %; literal DMP_UNWIND$S_SEGNUM = 8; ! Unwind segment number macro DMP_UNWIND$Q_IMAGE_OFFSET = 32,0,0,1 %; literal DMP_UNWIND$S_IMAGE_OFFSET = 8; ! Start offset of this unwind segment within the image macro DMP_UNWIND$Q_IMAGE_SEGLEN = 40,0,0,1 %; literal DMP_UNWIND$S_IMAGE_SEGLEN = 8; ! Size of unwind segment in image file macro DMP_UNWIND$Q_UNWTAB_LENGTH = 48,0,0,0 %; literal DMP_UNWIND$S_UNWTAB_LENGTH = 8; ! Size (in bytes) of unwind table portion of this segment macro DMP_UNWIND$L_CODESEG_COUNT = 56,0,32,0 %; ! Number of code segments described by this segment macro DMP_UNWIND$L_VBN = 60,0,32,0 %; ! Relative VBN in collection for this unwind segment macro DMP_UNWIND$L_BLOCKS = 64,0,32,0 %; ! Count of blocks for this unwind segment macro DMP_UNWIND$W_FLAGS = 68,0,16,0 %; macro DMP_UNWIND$V_NOT_HERE = 68,0,1,0 %; ! The unwind segment wasn't kept in memory during dump copy macro DMP_UNWIND$V_SEPARATE = 68,1,1,0 %; ! This DMP_UNWIND_DATA was allocated separately (pre-reorg) !*** MODULE $SHMEMDEF *** ! ! Shared Memory Management Definitions. The shared memory management ! structure contains the data needed to manage shared memory in a Galaxy. ! literal SHMEM$M_SHMEM_VALID = %X'1'; literal SHMEM$M_INIT_IN_PROGRESS = %X'2'; literal SHMEM$M_SHMEM_DEBUG = %X'4'; literal SHMEM$M_SHM_CPP_TESTED = %X'8'; literal SHMEM$M_RESERVED_BITS = %X'FFFFFFF0'; literal SHMEM$C_LENGTH = 256; ! Length of SHMEM literal SHMEM$S_SHMEM = 256; macro SHMEM$Q_INIT_TIME = 0,0,0,0 %; literal SHMEM$S_INIT_TIME = 8; ! Time of shared memory init macro SHMEM$W_MBO = 8,0,16,0 %; ! Must be one macro SHMEM$B_TYPE = 10,0,8,0 %; ! Dynamic structure type macro SHMEM$B_SUBTYPE = 11,0,8,0 %; ! Dynamic structure subtype macro SHMEM$L_VERSION = 12,0,32,0 %; ! Structure version number macro SHMEM$Q_SIZE = 16,0,0,0 %; literal SHMEM$S_SIZE = 8; ! Size of the structure macro SHMEM$L_FLAGS = 24,0,32,0 %; ! FLAGS longword macro SHMEM$V_SHMEM_VALID = 24,0,1,0 %; ! SHMEM is valid macro SHMEM$V_INIT_IN_PROGRESS = 24,1,1,0 %; ! Initialization is in progress macro SHMEM$V_SHMEM_DEBUG = 24,2,1,0 %; ! Debug structures are in use macro SHMEM$V_SHM_CPP_TESTED = 24,3,1,0 %; ! All pages in all SHM_CPPs have been tested macro SHMEM$V_RESERVED_BITS = 24,4,28,0 %; macro SHMEM$L_CREATOR_GNODE = 28,0,32,0 %; ! Creator's gNode id macro SHMEM$L_MAX_CPP_COUNT = 64,0,32,0 %; ! Maximum number of SHM_CPPs macro SHMEM$L_VALID_CPP_COUNT = 68,0,32,0 %; ! Total number of valid SHM_CPPs macro SHMEM$Q_SHM_CPP_SIZE = 72,0,0,0 %; literal SHMEM$S_SHM_CPP_SIZE = 8; ! Size of one SHM_CPP array element macro SHMEM$Q_CPP_ARRAY_OFF = 80,0,0,0 %; literal SHMEM$S_CPP_ARRAY_OFF = 8; ! Offset to the SHM_CPP array macro SHMEM$Q_GLOCK_OFF = 160,0,0,0 %; literal SHMEM$S_GLOCK_OFF = 8; ! Offset to gLock structure macro SHMEM$Q_GLOCK_HANDLE = 168,0,0,0 %; literal SHMEM$S_GLOCK_HANDLE = 8; ! GLock handle macro SHMEM$L_MAX_REG_COUNT = 176,0,32,0 %; ! Maximum number of SHM_REGs macro SHMEM$L_VALID_REG_COUNT = 180,0,32,0 %; ! Total number of valid regions macro SHMEM$Q_SHM_REG_SIZE = 184,0,0,0 %; literal SHMEM$S_SHM_REG_SIZE = 8; ! Size of one SHM_REG array element macro SHMEM$Q_TAG_ARRAY_OFF = 192,0,0,0 %; literal SHMEM$S_TAG_ARRAY_OFF = 8; ! Offset to the SHM_TAG array macro SHMEM$Q_REG_ARRAY_OFF = 200,0,0,0 %; literal SHMEM$S_REG_ARRAY_OFF = 8; ! Offset to the SHM_REG array ! ! Shared Memory Management Flags (not to be confused with SHMEM_FLAGS in ! GLXDEF). These flags are stored in GLX$GL_SHMEM_FLAGS. ! literal SHMEM$M_VALID = %X'1'; literal SHMEM$M_SUSPECT = %X'2'; literal SHMEM$M_RECOVER_IN_PROGRESS = %X'4'; literal SHMEM$M_EXIT_IN_PROGRESS = %X'8'; literal SHMEM$M_FLAGS_RESERVED = %X'FFFFFFF0'; literal SHMEM$S_GLX_SHMEM_FLAGS = 4; macro SHMEM$L_SHMEM_FLAGS = 0,0,32,0 %; macro SHMEM$V_VALID = 0,0,1,0 %; ! Shared memory is valid macro SHMEM$V_SUSPECT = 0,1,1,0 %; ! Shared memory is suspect macro SHMEM$V_RECOVER_IN_PROGRESS = 0,2,1,0 %; ! Shared memory recovery in progress macro SHMEM$V_EXIT_IN_PROGRESS = 0,3,1,0 %; ! Shared memory exit in progress macro SHMEM$V_FLAGS_RESERVED = 0,4,28,0 %; literal SHMEM$S_FLAGS_RESERVED = 28; !*** MODULE $SHM_DESCDEF *** ! ! Shared Memory Region Descriptor Definitions -- The shared memory region ! descriptor structure contains node private needed to manage the shared ! memory regions that this node is attached to. ! literal SHM_DESC$M_ATTACHED = %X'1'; literal SHM_DESC$M_GLX_GBLSEC = %X'2'; literal SHM_DESC$M_SYS_VA_VALID = %X'4'; literal SHM_DESC$M_ATTACH_DETACH = %X'8'; literal SHM_DESC$M_RESERVED_4_31 = %X'FFFFFFF0'; literal SHM_DESC$C_LENGTH = 128; ! Length of SHM_DESC literal SHM_DESC$S_SHM_DESC = 128; macro SHM_DESC$Q_SPARE1 = 0,0,0,0 %; literal SHM_DESC$S_SPARE1 = 8; ! Spare macro SHM_DESC$W_MBO = 8,0,16,0 %; ! Must be one macro SHM_DESC$B_TYPE = 10,0,8,0 %; ! Dynamic structure type macro SHM_DESC$B_SUBTYPE = 11,0,8,0 %; ! Dynamic structure subtype macro SHM_DESC$L_VERSION = 12,0,32,0 %; ! Structure version number macro SHM_DESC$Q_SIZE = 16,0,0,0 %; literal SHM_DESC$S_SIZE = 8; ! Size of the structure macro SHM_DESC$L_FLAGS = 24,0,32,0 %; ! FLAGS longword macro SHM_DESC$V_ATTACHED = 24,0,1,0 %; ! Node is attached to this SHM_REG macro SHM_DESC$V_GLX_GBLSEC = 24,1,1,0 %; ! Region is a global section macro SHM_DESC$V_SYS_VA_VALID = 24,2,1,0 %; ! Region is mapped into system space macro SHM_DESC$V_ATTACH_DETACH = 24,3,1,0 %; ! Callback routine called for attach and detach macro SHM_DESC$V_RESERVED_4_31 = 24,4,28,0 %; literal SHM_DESC$S_RESERVED_4_31 = 28; macro SHM_DESC$Q_IO_REFCNT = 32,0,0,1 %; literal SHM_DESC$S_IO_REFCNT = 8; ! Node private I/O reference count for the region macro SHM_DESC$Q_BO_REFCNT = 40,0,0,1 %; literal SHM_DESC$S_BO_REFCNT = 8; ! Node private buffer object reference count for the region macro SHM_DESC$R_SHM_ID = 48,0,0,0 %; literal SHM_DESC$S_SHM_ID = 8; ! SHM_ID of this region macro SHM_DESC$Q_VIRT_LENGTH = 56,0,0,0 %; literal SHM_DESC$S_VIRT_LENGTH = 8; ! Virtual length in bytes macro SHM_DESC$PQ_CALLBACK_ROUTINE = 64,0,0,1 %; literal SHM_DESC$S_CALLBACK_ROUTINE = 8; ! Address of callback routine macro SHM_DESC$Q_CONTEXT = 72,0,0,0 %; literal SHM_DESC$S_CONTEXT = 8; ! Additional context specified by caller macro SHM_DESC$PQ_GBLSEC_MAP_LIST = 80,0,0,1 %; literal SHM_DESC$S_GBLSEC_MAP_LIST = 8; ! Pointer to list of GBL_MAP structures ! (Change to proper type when GBL_MAP is defined) macro SHM_DESC$PQ_SYS_VA = 88,0,0,1 %; literal SHM_DESC$S_SYS_VA = 8; ! Address mapped to this region macro SHM_DESC$L_GSTX = 88,0,32,0 %; ! GSTX if this region is a global section macro SHM_DESC$R_PROTO_PTE = 96,0,0,0 %; literal SHM_DESC$S_PROTO_PTE = 8; ! Prototype PTE used to map this region !*** MODULE $PFNDEF *** ! + ! PFN memory data structure definition. This structure is used to access the ! fields within the PFN memory maps. In Galaxy systems, there is a PFN ! memory map for I/O space, private and shared memory. ! ! In non-Galaxy systems, there is only a PFN memory map for private memory. ! ! - literal PMAP$C_LENGTH = 16; ! Length of PMAP literal PMAP$S_PMAP = 16; macro PMAP$I_start_pfn = 0,0,0,0 %; literal PMAP$s_start_pfn = 8; ! First PFN in this cluster macro PMAP$I_pfn_count = 8,0,0,0 %; literal PMAP$s_pfn_count = 8; ! Number of PFNs in this cluster ! + ! In Galaxy shared memory, PLNKs are used as the structure that links PFN ! database entries in the free page list (and other lists). ! ! - literal PLNK$C_LENGTH = 16; ! Length of PLNK literal PLNK$S_PLNK = 16; macro PLNK$R_PLNK_I_QUADWORDS = 0,0,0,0 %; literal PLNK$S_PLNK_I_QUADWORDS = 16; macro PLNK$I_next_pfn = 0,0,0,0 %; literal PLNK$s_next_pfn = 8; ! Next PFN in this list, -1 terminates list macro PLNK$I_pfn_count = 8,0,0,0 %; literal PLNK$s_pfn_count = 8; ! Number of PFNs in this cluster ! + ! PFN Data Base Definitions ! - ! ! Define the PFN database record offsets. ! ! XDELTA provides embedded command strings for displaying the PFN database records. Any ! change to the PFN database record here must be implemented in the XDELTA command strings ! as well to avoid breaking them. ! literal PFN$M_PAGTYP = %X'7'; literal PFN$M_LOC = %X'F0'; literal PFN$M_BUFOBJ = %X'100'; literal PFN$M_COLLISION = %X'200'; literal PFN$M_BADPAG = %X'400'; literal PFN$M_RPTEVT = %X'800'; literal PFN$M_DELCON = %X'1000'; literal PFN$M_MODIFY = %X'2000'; literal PFN$M_UNAVAILABLE = %X'4000'; literal PFN$M_SWPPAG_VALID = %X'8000'; literal PFN$M_TOP_LEVEL_PT = %X'10000'; literal PFN$M_SLOT = %X'20000'; literal PFN$M_SHARED = %X'40000'; literal PFN$M_ZEROED = %X'80000'; literal PFN$M_VRNX = %X'F00000000000'; literal PFN$S_VRNX_WIDTH = 4; literal PFN$S_INDEX_WIDTH = 44; literal PFN$M_TYP0 = %X'10000'; literal PFN$M_PARTIAL_SECTION = %X'80000'; literal PFN$M_GBLBAK = %X'80000000'; literal PFN$M_STX = %X'FFFF00000000'; literal PFN$M_CRF = %X'1000000000000'; literal PFN$M_DZRO = %X'2000000000000'; literal PFN$M_WRT = %X'4000000000000'; literal PFN$M_STX_HIBIT = %X'8000000000000'; literal PFN$M_PGFLPAG = %X'FFFFFF00000000'; literal PFN$M_PGFLX = %X'FF00000000000000'; literal PFN$M_PGFLMAP = %X'FFFFFFFF00000000'; literal PFN$M_BAKX = %X'FFFFFFFFFF000000'; literal PFN$M_GPTX = %X'FFFFFFFF00000000'; literal PFN$C_ENTRY_SIZE = 64; ! literal PFN$C_FREPAGLST = 0; ! On FREE page list literal PFN$C_MFYPAGLST = 1; ! On MODIFIED page list literal PFN$C_BADPAGLST = 2; ! On BAD page list literal PFN$C_RELPEND = 3; ! RELease PENDing ! (when REFCNT=0 release PFN) literal PFN$C_UNTESTED = 3; ! On UNTESTED memory list literal PFN$C_RDERR = 4; ! Read error while paging in literal PFN$C_WRTINPROG = 5; ! Write in progress (by MFY PAG WRITER) literal PFN$C_RDINPROG = 6; ! Read in progress (page in) literal PFN$C_ZERO_LIST = 7; ! On ZEROED page list literal PFN$C_PRVPFN = 8; ! On private PFN list literal PFN$C_ACTIVE = 15; ! Page is ACTIVE and VALID ! literal PFN$C_PROCESS = 0; ! Process page literal PFN$C_SYSTEM = 1; ! System page literal PFN$C_GLOBAL = 2; ! Global page (read only) literal PFN$C_GBLWRT = 3; ! Global Writable page literal PFN$C_PPGTBL = 4; ! Process Page Table literal PFN$C_GPGTBL = 5; ! Global Page Table literal PFN$C_RESERVED = 6; ! reserved literal PFN$C_UNKNOWN = 7; ! Uninitialized db for this PFN literal PFN$C_PFNLST = 1; ! Shared memory PFNLST page literal PFN$C_SHM_REG = 3; ! Shared memory region page literal PFN$S_PFNDEF = 64; literal PFN$S_PFN = 64; macro PFN$R_SHM_LIST_LINK = 0,0,0,0 %; literal PFN$S_SHM_LIST_LINK = 16; macro PFN$R_SHM_REG_ID = 0,0,0,0 %; literal PFN$S_SHM_REG_ID = 8; ! Shared memory region ID macro PFN$I_FLINK = 0,0,0,0 %; literal PFN$S_FLINK = 8; ! Forward PFN link index macro PFN$L_SHRCNT = 0,0,32,0 %; ! Number of process PTEs mapped to global page macro PFN$I_BLINK = 8,0,0,0 %; literal PFN$S_BLINK = 8; ! Backward PFN link index macro PFN$L_WSLX_QW = 8,0,32,0 %; ! Working Set List Index for valid page, quadword index macro PFN$L_GBL_LCK_CNT = 8,0,32,0 %; ! Count of memory locks for global page macro PFN$L_PAGE_STATE = 16,0,32,0 %; ! Page state information ! ! VIELD definitions in PFN$AL_PAGE_STATE ! macro PFN$V_PAGTYP = 16,0,3,0 %; literal PFN$S_PAGTYP = 3; ! Page type macro PFN$V_LOC = 16,4,4,0 %; literal PFN$S_LOC = 4; ! Location of page macro PFN$V_BUFOBJ = 16,8,1,0 %; ! Set if any buffer objects reference this PFN macro PFN$V_COLLISION = 16,9,1,0 %; ! Empty collision queue when page read complete macro PFN$V_BADPAG = 16,10,1,0 %; ! Bad page bit macro PFN$V_RPTEVT = 16,11,1,0 %; ! Report event on I/O complete macro PFN$V_DELCON = 16,12,1,0 %; ! Delete PFN contents when REF=0 macro PFN$V_MODIFY = 16,13,1,0 %; ! Modify bit, indicates page is dirty macro PFN$V_UNAVAILABLE = 16,14,1,0 %; ! PFN is unavailable to software (such as for console) macro PFN$V_SWPPAG_VALID = 16,15,1,0 %; ! Set if SWPPAG contains a swap page number macro PFN$V_TOP_LEVEL_PT = 16,16,1,0 %; ! Denotes a page table at the highest level of translation hierarchy macro PFN$V_SLOT = 16,17,1,0 %; ! Donotes a page mapped into a process's balance slot macro PFN$V_SHARED = 16,18,1,0 %; ! Shared memory page macro PFN$V_ZEROED = 16,19,1,0 %; ! SHMGS page is zeroed ! Alpha macro PFN$R_PT_PFN_OVERLAY = 24,0,0,0 %; macro PFN$I_PT_PFN = 24,0,0,0 %; literal PFN$S_PT_PFN = 8; ! PFN of the PT that contains the PTE that maps target PFN macro PFN$L_SHM_CPP_ID = 24,0,32,0 %; ! SHM_CPP id that this page belongs to (if shared memory) ! IA64 macro PFN$Q_PTE_INDEX = 32,0,0,0 %; literal PFN$S_PTE_INDEX = 8; ! Container QW for the PTE index field ! PTE Index must occupies low 48 bits of this QW macro PFN$V_VRNX = 36,12,4,0 %; literal PFN$S_VRNX = 4; ! Virtual address space number macro PFN$W_REFCNT = 38,0,16,0 %; ! Number of references to this PFN's contents macro PFN$Q_BAK = 40,0,0,0 %; literal PFN$S_BAK = 8; ! Backing store address for this page macro PFN$L_PHD = 40,0,32,1 %; ! PHD VA (L1PT PFN only) macro PFN$I_COLOR_FLINK = 40,0,0,0 %; literal PFN$S_COLOR_FLINK = 8; ! Forward PFN link for page's color list macro PFN$V_TYP0 = 40,16,1,0 %; ! Backing store in section (not pagefile) macro PFN$V_PARTIAL_SECTION = 40,19,1,0 %; ! Page only partially maps a section macro PFN$V_GBLBAK = 40,31,1,0 %; ! Global backing store address (GPTX form) macro PFN$V_STX = 44,0,16,0 %; literal PFN$S_STX = 16; ! Section Table Index macro PFN$V_CRF = 44,16,1,0 %; ! Copy on Reference macro PFN$V_DZRO = 44,17,1,0 %; ! Demand Zero macro PFN$V_WRT = 44,18,1,0 %; ! Section file accessed for write macro PFN$V_STX_HIBIT = 44,19,1,0 %; macro PFN$V_PGFLPAG = 44,0,24,0 %; literal PFN$S_PGFLPAG = 24; ! Page file page (not a VBN) macro PFN$V_PGFLX = 44,24,8,0 %; literal PFN$S_PGFLX = 8; ! SYSTEM page file index macro PFN$V_PGFLMAP = 44,0,32,0 %; literal PFN$S_PGFLMAP = 32; ! PGFLPAG/PGFLX combination macro PFN$V_BAKX = 40,24,40,0 %; literal PFN$S_BAKX = 40; ! Backup address (uninterpreted) macro PFN$V_GPTX = 44,0,32,0 %; literal PFN$S_GPTX = 32; ! Global Page Table Index macro PFN$Q_BAK_PRVPFN = 40,0,0,0 %; literal PFN$S_BAK_PRVPFN = 8; ! Pointer to "owning" private list of (free) PFNs macro PFN$I_COLOR_BLINK = 48,0,0,0 %; literal PFN$S_COLOR_BLINK = 8; ! Backward PFN link for page's color list macro PFN$W_SWPPAG = 56,0,16,0 %; ! Page number in swap area to receive this page macro PFN$W_BO_REFC = 56,0,16,0 %; ! Buffer Object reference count (no swap possible) macro PFN$W_IO_STS = 56,0,16,0 %; macro PFN$W_PT_VAL_CNT = 58,0,16,0 %; macro PFN$W_PT_LCK_CNT = 60,0,16,0 %; macro PFN$W_PT_WIN_CNT = 62,0,16,0 %; ! Location VIELD values ! ! Page Type VIELD definitions ! ! PRVPFN - head of a private list of free PFNs literal PRVPFN$S_PRVPFN = 56; macro PRVPFN$L_SQFL = 0,0,32,1 %; ! PRVPFN queue flink macro PRVPFN$L_SQBL = 4,0,32,1 %; ! PRVPFN queue blink macro PRVPFN$W_SIZE = 8,0,16,0 %; ! structure size macro PRVPFN$B_TYPE = 10,0,8,0 %; ! structure type code (MISC) macro PRVPFN$B_SUBTYPE = 11,0,8,0 %; ! structure type subcode (PRVPFN) macro PRVPFN$I_COUNT = 16,0,0,0 %; literal PRVPFN$S_COUNT = 8; ! number of elements in list macro PRVPFN$I_HEAD = 24,0,0,0 %; literal PRVPFN$S_HEAD = 8; ! PFN of first element in queue macro PRVPFN$I_TAIL = 32,0,0,0 %; literal PRVPFN$S_TAIL = 8; ! PFN of last element in queue macro PRVPFN$L_RECLAIMABLE = 40,0,32,0 %; ! # PFNs attributed to this list macro PRVPFN$L_RECLAIMED = 44,0,32,0 %; ! # PFNs reclaimed but not yet returned macro PRVPFN$L_PRIORITY = 48,0,32,1 %; ! priority of elements on this list macro PRVPFN$A_CALLBACK = 52,0,32,1 %; ! callback routine literal PRVPFN$K_LENGTH = 56; ! length of block literal PRVPFN$C_LENGTH = 56; ! length of block !*** MODULE $SHM_CPPDEF *** ! ! Shared Memory CPP Definitions. The shared memory CPP structure contains ! the data needed to manage the physical pages within a shared memory CPP. ! literal SHM_CPP$M_VALID = %X'1'; literal SHM_CPP$M_INIT_IN_PROGRESS = %X'2'; literal SHM_CPP$M_RESERVED_2_31 = %X'FFFFFFFC'; literal SHM_CPP$C_LENGTH = 232; ! Length of SHM_CPP literal SHM_CPP$S_SHM_CPP = 232; macro SHM_CPP$W_MBO = 8,0,16,0 %; ! Must be one macro SHM_CPP$B_TYPE = 10,0,8,0 %; ! Dynamic structure type macro SHM_CPP$B_SUBTYPE = 11,0,8,0 %; ! Dynamic structure subtype macro SHM_CPP$L_VERSION = 12,0,32,0 %; ! Structure version number macro SHM_CPP$Q_SIZE = 16,0,0,0 %; literal SHM_CPP$S_SIZE = 8; ! Size of the structure macro SHM_CPP$L_FLAGS = 24,0,32,0 %; ! FLAGS longword macro SHM_CPP$V_VALID = 24,0,1,0 %; ! SHM_CPP is valid macro SHM_CPP$V_INIT_IN_PROGRESS = 24,1,1,0 %; ! Initialization is in progress macro SHM_CPP$V_RESERVED_2_31 = 24,2,30,0 %; literal SHM_CPP$S_RESERVED_2_31 = 30; macro SHM_CPP$I_PFN_COUNT = 32,0,0,0 %; literal SHM_CPP$S_PFN_COUNT = 8; ! Number of PFNs in this CPP macro SHM_CPP$I_MIN_PFN = 40,0,0,0 %; literal SHM_CPP$S_MIN_PFN = 8; ! Lowest PFN in this CPP macro SHM_CPP$I_MAX_PFN = 48,0,0,0 %; literal SHM_CPP$S_MAX_PFN = 8; ! Highest PFN in this CPP macro SHM_CPP$L_MAX_FRAGMENTS = 56,0,32,0 %; ! Maximum number of memory fragments macro SHM_CPP$L_FRAGMENT_COUNT = 60,0,32,0 %; ! Number of memory fragments macro SHM_CPP$Q_PMAP_OFF = 64,0,0,0 %; literal SHM_CPP$S_PMAP_OFF = 8; ! Offset to PMAP array macro SHM_CPP$Q_PFNDB_PMAP_OFF = 72,0,0,0 %; literal SHM_CPP$S_PFNDB_PMAP_OFF = 8; ! Offset to PFNDB PMAP array macro SHM_CPP$Q_GLOCK_OFF = 112,0,0,0 %; literal SHM_CPP$S_GLOCK_OFF = 8; ! Offset to gLock structure macro SHM_CPP$Q_GLOCK_HANDLE = 120,0,0,0 %; literal SHM_CPP$S_GLOCK_HANDLE = 8; ! Handle for gLock macro SHM_CPP$Q_GNODE_OFF = 128,0,0,0 %; literal SHM_CPP$S_GNODE_OFF = 8; ! Offset to gNode bitmask block macro SHM_CPP$R_FREE_LIST = 144,0,0,0 %; literal SHM_CPP$S_FREE_LIST = 16; ! First PFN in free page list/total free pages macro SHM_CPP$R_BAD_LIST = 160,0,0,0 %; literal SHM_CPP$S_BAD_LIST = 16; ! First PFN in bad page list/total bad pages macro SHM_CPP$R_UNTESTED_LIST = 176,0,0,0 %; literal SHM_CPP$S_UNTESTED_LIST = 16; ! First PFN in untested page list/total untested pages macro SHM_CPP$I_RECOVER_PFN = 192,0,0,0 %; literal SHM_CPP$S_RECOVER_PFN = 8; ! Base PFN of last allocated block macro SHM_CPP$L_RECOVER_COUNT = 200,0,32,0 %; ! Count of last allocated block !*** MODULE $gmdbdef *** ! ! Ident X-24 ! ! GMDBDEF.SDL -- Galaxy GMDB definitions ! ! Copyright © Digital Equipment Corporation, 1997 - 1998. ! All rights reserved. ! ! The software contained on this media is proprietary to and ! embodies the confidential technology of Digital Equipment ! Corporation. Possession, use, duplication, or dissemination ! of the software and media is authorized only pursuant to a ! valid written license from Digital Equipment Corporation. ! ! RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure ! by the U.S. Government is subject to restrictions as set ! forth in Subparagraph (c) (1) (ii) of DFARS 252.227-7013, ! or in FAR 52.227-19, as applicable. ! ! -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- ! ! ! Description: This file contains the definitions for values and structures ! needed contained in the Galaxy Management Database (GMDB) ! ! Environment: OpenVMS Operating System, privileged kernel-mode ! ! Author: Paul Harter ! ! Modifications: ! ! X-24 Susan M. Lewis 20-Mar-2000 ! Add a glxint$ code for Galaxy machine check handling. ! ! X-23 CMOS Christian Moser 26-OCT-1998 ! Obsolete old version fields in GMDB and NODEB. ! ! X-22 CMOS Christian Moser 22-SEP-1998 ! Remove the semi-colon of the quadword constant definitions, ! otherwise they cannot be used within an IF statement. ! Add crash timestamp field to nodeblock, so we know when the ! crash reason field was written. ! ! X-21 RAB Richard A. Bishop 8-Sep-1998 ! Change names of reserved fields so that as changes ! are made over time, SDA can see them ! ! X-20 CMOS Christian Moser 7-SEP-1998 ! Remove duplicate constants GLX_ST$_xxx instroduced in X-19, ! Bliss doesn't like them. ! ! X-19 CMOS Christian Moser 17-AUG-1998 ! Add Revision and version fields, move important and static ! fields (offset/length pairs) to the beginning and add ! padding. This is needed for possible future changes to the ! GMDB without forcing the whole Galaxy to be shut off for ! a version upgrade. ! ! X-18 RAB Richard A. Bishop 6-Jul-1998 ! Fix up reserved field name ! ! X-17 JRK390 Jim Kauffman 23-Jun-1998 ! Add glxint$ code for packet passing ! ! X-16 LGD Linda G. Duffell 26-May-1998 ! Add a GLXINT$ code for Shared Memory LAN. ! ! X-15 PKH-G026 Paul K. Harter, Jr. 2-Apr-1998 ! Change last_heartbeat field in node block to a quadword. ! ! X-14 AHM044 Drew Mason 2-Apr-1998 ! Add crash status code field to the node block. ! ! X-13 PKH-G019 Paul K. Harter, Jr. 10-Mar-1998 ! Add node timeout field to gmdb and some tracking fields ! to the node block. ! ! X-12 GHJ Gregory H. Jordan 5-Mar-1998 ! Add a glxint$ code for Shared Memory CI. ! ! X-11 AHM043 Drew Mason 5-Mar-1998 ! Add gmdb$q_died_time and gmdb$l_last_node. ! ! X-10 AHM043 Drew Mason 4-Mar-1998 ! Add nodeb$q_leaving_time. ! ! X-9 KLN2058 Karen L. Noel 3-Mar-1998 ! Add glxint$ codes for nodes attaching and detaching ! to and from shared memory regions. ! ! X-8 RAB Richard A. Bishop 26-Feb-1998 ! Add changes to enhance SDA support: word for gmdbl flags, ! some reserved fields, type/subtype for node block. ! ! X-7 AHM039 Drew Mason 18-Feb-1998 ! Add fields for node being removed and removal start time. ! ! X-6 AHM031 Drew Mason 12-Jan-1998 ! Add crash reason to the node block. ! ! X-5 JRK390 Jim Kauffman 8-Jan-1998 ! Locking communication bit definitions ! ! X-4 PKH-G005 Paul K. Harter, Jr. 18-Dec-1997 ! Added upper-bound values to galaxy and node state. ! ! X-3 PKH-G003 Paul K. Harter, Jr. 2-Dec-1997 ! Made fields in gmdb_lock naturally aligned. Added ! last_joiner to gmdb, and made incarnations into ! quadwords. Fixed typo in "to_remove_off" ! ! X-2 PKH-G001 Paul K. Harter, Jr. 19-Nov-1997 ! Added GMDB and NODEB fields and comments. Inserted ! alignment and padding. Added "broken" to gmdb lock. ! ! X-1 KLN2010 Karen L. Noel 23-Oct-1997 ! Initial entry ! ! values for galaxy state. literal glx_st$_all_dead = 0; literal glx_st$_creating = 1; literal glx_st$_node_joining = 2; literal glx_st$_node_leaving = 3; literal glx_st$_operational = 4; literal glx_st$_recovering = 5; literal glx_st$_validating = 6; literal glx_st$_reforming = 7; literal glx_st$_reform_pend = 8; literal glx_st$_crashing = 9; literal glx_st$_crash_pend = 10; literal glx_st$_too_big = 11; literal nb_st$_dead = 0; literal nb_st$_booting = 1; literal nb_st$_creating = 2; literal nb_st$_joining = 3; literal nb_st$_leaving = 4; literal nb_st$_member = 5; literal nb_st$_too_big = 6; literal gmdbl$m_locked = %X'1'; literal gmdbl$m_broken = %X'2'; literal gmdbl$m_reserved_2_15 = %X'FFFC'; literal gmdbl$S_gmdb_lock = 8; macro gmdbl$q_quad = 0,0,0,0 %; literal gmdbl$s_quad = 8; macro gmdbl$r_fields = 0,0,0,0 %; literal gmdbl$s_fields = 8; macro gmdbl$w_flags = 0,0,16,0 %; macro gmdbl$v_locked = 0,0,1,0 %; ! lock is currently held macro gmdbl$v_broken = 0,1,1,0 %; ! lock was taken from dead node macro gmdbl$v_reserved_2_15 = 0,2,14,0 %; literal gmdbl$s_reserved_2_15 = 14; macro gmdbl$w_extra = 2,0,16,0 %; macro gmdbl$l_owner = 4,0,32,0 %; ! if held, current owner ! GMDB revision and Galaxy version ! ! The Galaxy creator will fill in the GMDB revision field with GMDB$K_REVISION ! and any joining instances will verify their GMDB$K_MIN_REV against the GMDB ! revision. Any compatible change to the GMDB will bump the revision, and any ! incompatible change will also bump the minimum revision. ! Each Galaxy instance has a major and minor version, which will be used ! during the join decision. ! literal GMDB$K_PATTERN_L = 1481393956; ! string "$GLX" literal GMDB$K_PATTERN_H = 1111772487; ! string "GMDB" ! GMDB Revision Matrix: ! --------------------- ! Current Rev: Compatible with: Comment: ! 1.0 1.0 Initial Galaxy Implementation ! literal GMDB$K_REV_MAJ = 1; ! major GMDB revision literal GMDB$K_REV_MIN = 0; ! minor GMDB revision literal GMDB$K_REV1 = 1; ! initial Galaxy V1.0 ! Galaxy Version Matrix: ! ---------------------- ! Current Vers: Compatible with: Comment: ! 1.0 1.0 Initial Galaxy Implementation ! literal GLX$K_VERS_MAJ = 1; ! Major Galaxy version literal GLX$K_VERS_MIN = 0; ! Minor Galaxy version literal GLX$K_MIN_ALLOWED_MAJ = 1; ! minimum Galaxy version allowed literal GLX$K_MIN_ALLOWED_MIN = 0; ! minimum Galaxy version allowed literal gmdb$m_glock = %X'1'; literal gmdb$m_shmem = %X'2'; literal gmdb$m_cpucom = %X'4'; literal gmdb$m_cpuinfo = %X'8'; literal gmdb$m_member = %X'10'; literal gmdb$m_reserved_5_31 = %X'FFFFFFE0'; literal gmdb$c_length = 8192; ! length of fixed-size portion of GMDB literal gmdb$S_gmdb = 8192; ! Galaxy Management Database Header ! ! This is the fixed-length portion of the GMDB header. The rest ! of the header (the variable-length portion) is allocated immediately ! following this portion from a single PFN allocation. ! ! The total size of the header is the sum of the following rounded up ! to the nearest full page: ! ! GMDB$C_LENGTH - fixed length portion ! MAX_NODES * NODEB$C_LENGTH - node block array ! 1 * padTo128(exe$cbb_get_size(MAX_NODES)) - membership bit mask CBB ! ! macro gmdb$q_pattern = 0,0,0,0 %; literal gmdb$s_pattern = 8; ! GMDB Pattern ! New Standard VMS type/subtype word at offset 8 macro gmdb$w_mbo = 8,0,16,0 %; ! Must be one: implies quad size field macro gmdb$b_type = 10,0,8,0 %; ! Dynamic structure type macro gmdb$b_subtype = 11,0,8,0 %; ! Dynamic structure subtype macro gmdb$q_base_size = 16,0,0,0 %; literal gmdb$s_base_size = 8; ! size of gmdb base section macro gmdb$q_total_size = 24,0,0,0 %; literal gmdb$s_total_size = 8; ! size of entire gmdb ! GMDB lock quadword - synchronize access to GMDB - uses special acquire ! and release that verify node heartbeat to break ! lock held by a crashed node. ! macro gmdb$r_lock = 32,0,0,0 %; literal gmdb$s_lock = 8; macro gmdb$q_revision = 64,0,0,0 %; literal gmdb$s_revision = 8; ! GMDB Revision macro gmdb$l_revision_minor = 64,0,32,0 %; macro gmdb$l_revision_major = 68,0,32,0 %; ! The following operational version fields are filled in by looking at the ! Galaxy version field of all members. The lowest version becomes the current ! minimum operational version, and the highest the maximum operational version ! The minimum version allowed is needed during the join decision to figure ! out if an instance can join an existing Galaxy or not. ! macro gmdb$q_min_vers_operational = 72,0,0,0 %; literal gmdb$s_min_vers_operational = 8; ! min Galaxy version macro gmdb$l_min_vers_op_minor = 72,0,32,0 %; macro gmdb$l_min_vers_op_major = 76,0,32,0 %; macro gmdb$q_max_vers_operational = 80,0,0,0 %; literal gmdb$s_max_vers_operational = 8; ! max Galaxy version macro gmdb$l_max_vers_op_minor = 80,0,32,0 %; macro gmdb$l_max_vers_op_major = 84,0,32,0 %; macro gmdb$q_min_vers_allowed = 88,0,0,0 %; literal gmdb$s_min_vers_allowed = 8; ! min Galaxy version allowed macro gmdb$l_min_vers_allowed_minor = 88,0,32,0 %; macro gmdb$l_min_vers_allowed_major = 92,0,32,0 %; ! ! Offset-length pairs for sub-facility specific segments ! macro gmdb$q_nodeb_off = 96,0,0,0 %; literal gmdb$s_nodeb_off = 8; ! offset to node block array macro gmdb$q_nodeb_size = 104,0,0,0 %; literal gmdb$s_nodeb_size = 8; ! nodeblock size macro gmdb$q_mmask_off = 112,0,0,0 %; literal gmdb$s_mmask_off = 8; ! offset to galaxy membership mask (CBB) macro gmdb$q_mmask_len = 120,0,0,0 %; literal gmdb$s_mmask_len = 8; ! membership mask length macro gmdb$q_glock_off = 128,0,0,0 %; literal gmdb$s_glock_off = 8; ! offset to galaxy locks segment macro gmdb$q_glock_len = 136,0,0,0 %; literal gmdb$s_glock_len = 8; ! galaxy locks segment length macro gmdb$q_shmem_off = 144,0,0,0 %; literal gmdb$s_shmem_off = 8; ! offset to shared memory segment macro gmdb$q_shmem_len = 152,0,0,0 %; literal gmdb$s_shmem_len = 8; ! shared memory segment length macro gmdb$q_cpucom_off = 160,0,0,0 %; literal gmdb$s_cpucom_off = 8; ! offset to cpu communications segment macro gmdb$q_cpucom_len = 168,0,0,0 %; literal gmdb$s_cpucom_len = 8; ! cpu communications segment length macro gmdb$q_cpuinfo_off = 176,0,0,0 %; literal gmdb$s_cpuinfo_off = 8; ! offset to cpu information segment macro gmdb$q_cpuinfo_len = 184,0,0,0 %; literal gmdb$s_cpuinfo_len = 8; ! cpu information segment length macro gmdb$q_member_off = 192,0,0,0 %; literal gmdb$s_member_off = 8; ! (reserved) offset to membership segment macro gmdb$q_member_len = 200,0,0,0 %; literal gmdb$s_member_len = 8; ! (reserved) membership segment length ! macro gmdb$r_mmap = 512,0,0,0 %; literal gmdb$s_mmap = 64; ! MMAP for the rest of the GMDB macro gmdb$l_fill_1 = 576,0,32,0 %; ! unused field macro gmdb$l_max_node_id = 580,0,32,0 %; ! maximum node_id this platform macro gmdb$l_break_owner = 584,0,32,0 %; ! node holding lock while it was broken macro gmdb$l_breaker_id = 588,0,32,0 %; ! node breaking lock macro gmdb$q_incarnation = 592,0,0,1 %; literal gmdb$s_incarnation = 8; ! galaxy incarnation count macro gmdb$q_time = 600,0,0,0 %; literal gmdb$s_time = 8; ! galaxy creation time (systime) macro gmdb$q_died_time = 608,0,0,0 %; literal gmdb$s_died_time = 8; ! systime galaxy died macro gmdb$l_state = 616,0,32,0 %; ! galaxy state macro gmdb$l_node_timeout = 620,0,32,0 %; ! time in msecs. to call a node dead. macro gmdb$l_creator_node = 624,0,32,0 %; ! creator node for this incarnation macro gmdb$l_remover_node = 628,0,32,0 %; ! node_id of node removing dead members macro gmdb$l_last_joiner = 632,0,32,0 %; ! node_id of last node to join galaxy. macro gmdb$l_last_leaver = 636,0,32,0 %; ! node_id of last node to leave galaxy. macro gmdb$q_to_remove_off = 640,0,0,0 %; literal gmdb$s_to_remove_off = 8; ! offset to list of nodes to be removed macro gmdb$l_crash_node = 648,0,32,0 %; ! node_id of node requesting crash macro gmdb$l_crash_reason = 652,0,32,0 %; ! reason for crash_all_nodes macro gmdb$l_reform_node = 656,0,32,0 %; ! node_id of node requesting reform macro gmdb$l_reform_reason = 660,0,32,0 %; ! reason for reform macro gmdb$l_valid_node = 664,0,32,0 %; ! node_id of node requesting validate macro gmdb$l_valid_reason = 668,0,32,0 %; ! reason for validate macro gmdb$q_remove_time = 672,0,0,0 %; literal gmdb$s_remove_time = 8; ! start time of most recent removal macro gmdb$l_being_removed = 680,0,32,0 %; ! node_id of node currently being removed macro gmdb$l_last_member = 684,0,32,0 %; ! node_id of last node out when the ! galaxy died macro gmdb$r_subfac_valid = 688,0,32,0 %; literal gmdb$s_subfac_valid = 4; macro gmdb$l_subvlong = 688,0,32,0 %; macro gmdb$v_glock = 688,0,1,0 %; macro gmdb$v_shmem = 688,1,1,0 %; macro gmdb$v_cpucom = 688,2,1,0 %; macro gmdb$v_cpuinfo = 688,3,1,0 %; macro gmdb$v_member = 688,4,1,0 %; macro gmdb$v_reserved_5_31 = 688,5,27,0 %; literal gmdb$s_reserved_5_31 = 27; ! ! This is the end of the fixed-length portion of the gmdb header. ! Following this are structures whose size depends on the ! maximum number of galaxy nodes allowed for a particular platform. ! ! Offsets to these (from the base of the fixed length portion) are ! stored in the fixed length portion. ! ! nodeb array of node blocks ! ! members galaxy members ! crash_ack members who've confirmed crash (or in node block) ! validate_done members who've finished validate (or in node block) ! ! The sub-facility specific portions comprising the rest of the GMDB are ! allocated in segments of page granularity and have offsets stored in ! the gmdb ! ! ! The fixed-length portion of the header ends on a page boundary ! literal glxint$m_bugcheck = %X'1'; literal glxint$m_member_change = %X'2'; literal glxint$m_node_crashing = %X'4'; literal glxint$m_crash_all_nodes = %X'8'; literal glxint$m_node_leaving = %X'10'; literal glxint$m_validate_start = %X'20'; literal glxint$m_validate_done = %X'40'; literal glxint$m_reform_galaxy = %X'80'; literal glxint$m_reform_rejoin = %X'100'; literal glxint$m_writable_PFN = %X'200'; literal glxint$m_check_process = %X'400'; literal glxint$m_release_waiters = %X'800'; literal glxint$m_shm_reg_attach = %X'1000'; literal glxint$m_shm_reg_detach = %X'2000'; literal glxint$m_smci_workq = %X'4000'; literal glxint$m_smlan_int = %X'8000'; literal glxint$m_mcheck_req = %X'10000'; literal glxint$m_reserved_17_31 = %X'FFFE0000'; literal glxint$m_packet_sent = %X'100000000'; literal glxint$m_reserved_33_63 = %X'FFFFFFFE00000000'; literal nodeb$C_MAX_WATCH_INDEX = 4; ! watch heartbeat of at most 5 nodes literal nodeb$c_length = 512; ! node block size literal nodeb$S_nodeb = 512; macro nodeb$q_heartbeat = 0,0,0,0 %; literal nodeb$s_heartbeat = 8; ! this node's heartbeat ! New Standard VMS type/subtype word at offset 8 macro nodeb$w_mbo = 8,0,16,0 %; ! Must be one: implies quad size field macro nodeb$b_type = 10,0,8,0 %; ! Dynamic structure type macro nodeb$b_subtype = 11,0,8,0 %; ! Dynamic structure subtype macro nodeb$l_state = 12,0,32,0 %; ! node's current state macro nodeb$q_size = 16,0,0,0 %; literal nodeb$s_size = 8; ! size of nodeblock macro nodeb$q_version = 24,0,0,0 %; literal nodeb$s_version = 8; ! instance version macro nodeb$l_version_minor = 24,0,32,0 %; macro nodeb$l_version_major = 28,0,32,0 %; macro nodeb$q_min_vers_allowed = 32,0,0,0 %; literal nodeb$s_min_vers_allowed = 8; ! min Galaxy version allowed macro nodeb$l_min_vers_allowed_minor = 32,0,32,0 %; macro nodeb$l_min_vers_allowed_major = 36,0,32,0 %; macro nodeb$r_prim_int_u = 40,0,0,0 %; literal nodeb$s_prim_int_u = 8; ! galaxy primitive IP-interrupt mask macro glxint$q_whole_mask = 40,0,0,0 %; literal glxint$s_whole_mask = 8; macro glxint$v_bugcheck = 40,0,1,0 %; ! immediate bugcheck - 0 macro glxint$v_member_change = 40,1,1,0 %; ! membership changed - 1 macro glxint$v_node_crashing = 40,2,1,0 %; ! sender node crashing - 2 macro glxint$v_crash_all_nodes = 40,3,1,0 %; ! crash all galaxy nodes - 3 macro glxint$v_node_leaving = 40,4,1,0 %; ! node leaving galaxy - 4 macro glxint$v_validate_start = 40,5,1,0 %; ! start galaxy validation - 5 macro glxint$v_validate_done = 40,6,1,0 %; ! validation completed - 6 macro glxint$v_reform_galaxy = 40,7,1,0 %; ! initiate galaxy reformation - 7 macro glxint$v_reform_rejoin = 40,8,1,0 %; ! reform: nodes down, rejoin now - 8 macro glxint$v_writable_PFN = 40,9,1,0 %; ! sender has writable remote PFN - 9 macro glxint$v_check_process = 40,10,1,0 %; ! check process existence - 10 macro glxint$v_release_waiters = 40,11,1,0 %; ! release glock waiters - 11 macro glxint$v_shm_reg_attach = 40,12,1,0 %; ! node is attaching to a region - 12 macro glxint$v_shm_reg_detach = 40,13,1,0 %; ! node is detaching from a region - 13 macro glxint$v_smci_workq = 40,14,1,0 %; ! process SMCI Work Queues - 14 macro glxint$v_smlan_int = 40,15,1,0 %; ! process SMLAN interrupts - 15 macro glxint$v_mcheck_req = 40,16,1,0 %; ! process machine check request - 16 macro glxint$v_reserved_17_31 = 40,17,15,0 %; literal glxint$s_reserved_17_31 = 15; macro glxint$v_packet_sent = 44,0,1,0 %; ! packet queued notification - 32 macro glxint$v_reserved_33_63 = 44,1,31,0 %; literal glxint$s_reserved_33_63 = 31; macro nodeb$q_time = 48,0,0,0 %; literal nodeb$s_time = 8; ! time node joined galaxy (systime) macro nodeb$q_leaving_time = 56,0,0,0 %; literal nodeb$s_leaving_time = 8; ! time node left galaxy (systime) macro nodeb$q_name = 64,0,0,0 %; literal nodeb$s_name = 8; ! node's SCS node name macro nodeb$q_incarnation = 72,0,0,1 %; literal nodeb$s_incarnation = 8; ! node joined galaxy count macro nodeb$l_was_creator = 80,0,32,0 %; ! TRUE if this node created galaxy macro nodeb$l_nval_done = 84,0,32,0 %; ! node validation done macro nodeb$l_crash_ack = 88,0,32,0 %; ! node crash_all acknowledge macro nodeb$l_reform_done = 92,0,32,0 %; ! node reform done; ready to rejoin macro nodeb$l_crash_reason = 96,0,32,1 %; ! bugcheck code for local crash macro nodeb$l_crash_status = 100,0,32,1 %; ! system status code that caused ! Galaxy code to decide to crash ! with GLXFATAL macro nodeb$l_fill_2 = 104,0,32,0 %; ! unused field macro nodeb$l_lbrother = 108,0,32,0 %; ! little brother (watched by this node) macro nodeb$l_bbrother = 112,0,32,0 %; ! big brother (who watches this node) macro nodeb$l_last_watched = 116,0,32,0 %; ! last valid entry in watched_nodes macro nodeb$r_watched_nodes = 120,0,0,0 %; literal nodeb$s_watched_nodes = 80; macro nodeb$l_node_id = 120,0,32,0 %; ! node_id of node to watch macro nodeb$l_miss_count = 124,0,32,0 %; ! consecutive no-increase observations macro nodeb$q_last_heartbeat = 128,0,0,0 %; literal nodeb$s_last_heartbeat = 8; ! heartbeat last observation macro nodeb$q_crash_time = 256,0,0,0 %; literal nodeb$s_crash_time = 8; ! timestamp, when crash reason was written !*** MODULE $SHM_REGDEF *** ! ! Shared Memory Region Definitions. The shared memory region structure ! contains the data needed to manage the pages within a shared memory ! region. ! literal SHM_REG$M_VALID = %X'1'; literal SHM_REG$M_INIT_IN_PROGRESS = %X'2'; literal SHM_REG$M_SHARED_CONTEXT_VALID = %X'4'; literal SHM_REG$M_ATTACH_DETACH = %X'8'; literal SHM_REG$M_DELETED = %X'10'; literal SHM_REG$M_DELETE_IN_PROGRESS = %X'20'; literal SHM_REG$M_RESERVED_6_31 = %X'FFFFFFC0'; literal SHM_REG$C_LENGTH = 288; ! Length of SHM_REG literal SHM_REG$S_SHM_REG = 288; macro SHM_REG$W_MBO = 8,0,16,0 %; ! Must be one macro SHM_REG$B_TYPE = 10,0,8,0 %; ! Dynamic structure type macro SHM_REG$B_SUBTYPE = 11,0,8,0 %; ! Dynamic structure subtype macro SHM_REG$L_VERSION = 12,0,32,0 %; ! Structure version number macro SHM_REG$Q_SIZE = 16,0,0,0 %; literal SHM_REG$S_SIZE = 8; ! Size of the structure macro SHM_REG$L_FLAGS = 24,0,32,0 %; ! FLAGS longword macro SHM_REG$V_VALID = 24,0,1,0 %; ! SHM_REG is valid macro SHM_REG$V_INIT_IN_PROGRESS = 24,1,1,0 %; ! Initialization is in progress macro SHM_REG$V_SHARED_CONTEXT_VALID = 24,2,1,0 %; ! Context in SHM_REG is valid macro SHM_REG$V_ATTACH_DETACH = 24,3,1,0 %; ! Nodes expect attach/detach callbacks macro SHM_REG$V_DELETED = 24,4,1,0 %; ! The region is deleted macro SHM_REG$V_DELETE_IN_PROGRESS = 24,5,1,0 %; ! The region is being deleted macro SHM_REG$V_RESERVED_6_31 = 24,6,26,0 %; literal SHM_REG$S_RESERVED_6_31 = 26; macro SHM_REG$T_TAG = 32,0,0,0 %; literal SHM_REG$S_TAG = 64; ! "Name" of region macro SHM_REG$R_SHM_ID = 96,0,0,0 %; literal SHM_REG$S_SHM_ID = 8; ! SHM_ID of this region macro SHM_REG$Q_CREATE_TIME = 104,0,0,0 %; literal SHM_REG$S_CREATE_TIME = 8; ! Time of region creation macro SHM_REG$Q_SHARED_CONTEXT = 112,0,0,0 %; literal SHM_REG$S_SHARED_CONTEXT = 8; ! Shared context (global section ident, for example) macro SHM_REG$R_MMAP = 128,0,0,0 %; literal SHM_REG$S_MMAP = 64; ! Embedded MMAP to describe mapping of region macro SHM_REG$Q_GLOCK_OFF = 192,0,0,0 %; literal SHM_REG$S_GLOCK_OFF = 8; ! Offset to gLock structure macro SHM_REG$Q_GLOCK_HANDLE = 200,0,0,0 %; literal SHM_REG$S_GLOCK_HANDLE = 8; ! GLock handle macro SHM_REG$Q_ATT_GNODE_OFF = 208,0,0,0 %; literal SHM_REG$S_ATT_GNODE_OFF = 8; ! Offset to the attached gNode bitmask block macro SHM_REG$Q_IO_GNODE_OFF = 216,0,0,0 %; literal SHM_REG$S_IO_GNODE_OFF = 8; ! Offset to the I/O in progress bitmask block macro SHM_REG$Q_CPP_BITMASK_OFF = 224,0,0,0 %; literal SHM_REG$S_CPP_BITMASK_OFF = 8; ! Offset to the CPP bitmask lock literal SHM_MSG$S_SHM_MSG = 16; macro SHM_MSG$L_REASON = 0,0,32,1 %; ! Reason for callback macro SHM_MSG$L_GNODE_ID = 4,0,32,0 %; ! Node initiating message macro SHM_MSG$R_SHM_ID = 8,0,0,0 %; literal SHM_MSG$S_SHM_ID = 8; ! SHM_ID of this region !*** MODULE $SMCIDEF *** ! + ! PBTQE - PB TQE ! ! PB TQE is a standard TQE with some extention fields added ! at the end. ! - literal PBTQE$S_PB_TQE = 80; macro PBTQE$ps_dispatch_table = 64,0,32,1 %; macro PBTQE$l_next_step = 72,0,32,1 %; macro PBTQE$l_soft_errcnt = 76,0,32,1 %; ! + ! SMCH$ - Shared Memory Channel Block ! ! - literal SMCH$K_LENGTH = 52; ! Length of structure literal SMCH$C_LENGTH = 52; ! Length of structure literal smch$S_SMCH = 56; macro smch$q_creation_time = 0,0,0,0 %; literal smch$s_creation_time = 8; ! time of creation macro smch$w_size = 8,0,16,0 %; ! Size of SMCH$ in bytes macro smch$b_type = 10,0,8,0 %; ! Structure type DYN$C_SMCI macro smch$b_subtype = 11,0,8,0 %; ! Structure sub-type DYN$C_SMCI_SMCH macro smch$l_creator_node = 12,0,32,0 %; ! gNode ID of creator macro smch$q_virtual_size = 16,0,0,0 %; literal smch$s_virtual_size = 8; ! Max bytes for region macro smch$q_physical_size = 24,0,0,0 %; literal smch$s_physical_size = 8; ! Physical bytes for region macro smch$l_node_block = 32,0,0,1 %; literal smch$s_node_block = 8; ! Offset to A's SMND$ structure macro smch$l_buffer_start = 40,0,32,0 %; ! offset to head of entries section macro smch$l_buffer_end = 44,0,32,0 %; ! offset to end of entries section macro smch$l_total_buffers = 48,0,32,0 %; ! Number of carved channels ! + ! ! ! SMND$ - Shared Memory Node Specific Data ! ! ! - literal SMCI$K_VERSION = 2; literal SMCI$K_ECO = 0; literal SMND$K_V1 = 0; ! V1 capabilities literal smnd$m_open = %X'1'; literal smnd$m_norm_shtdwn = %X'2'; literal SMND$K_MAXPRIO_IDX = 1; ! max. prio index literal SMND$C_MAXPRIO_IDX = 1; ! max. prio index literal SMND$K_MAXPRIO = 2; ! number of priorities literal SMND$C_MAXPRIO = 2; ! number of priorities literal SMND$K_LENGTH = 192; ! Length of structure literal SMND$C_LENGTH = 192; ! Length of structure literal smnd$S_SMND = 192; ! constant VERSION equals 1 prefix SMCI$ tag K; macro smnd$q_version = 0,0,0,0 %; literal smnd$s_version = 8; ! SMCH$ Structure Version macro smnd$l_eco_level = 0,0,32,0 %; ! SMCH$ ECO Level macro smnd$l_version = 4,0,32,0 %; ! SMCH$ Structure Version macro smnd$w_size = 8,0,16,0 %; ! Size of SMND$ in bytes macro smnd$b_type = 10,0,8,0 %; ! Structure type DYN$C_SMCI macro smnd$b_subtype = 11,0,8,0 %; ! Structure sub-type DYN$C_SMCI_SMND macro smnd$l_chan_char = 12,0,32,1 %; ! Node Capabilites macro smnd$l_filler = 16,0,32,1 %; ! Node Capabilites macro smnd$l_gnode = 20,0,32,0 %; ! gNode ID macro smnd$q_status = 24,0,0,0 %; literal smnd$s_status = 8; ! status quadword macro smnd$v_open = 24,0,1,0 %; ! node ready macro smnd$v_norm_shtdwn = 24,1,1,0 %; ! normal shutdown macro smnd$l_free_head = 32,0,32,0 %; ! head of the Harter list macro smnd$l_mapped = 36,0,32,0 %; ! number of pages mapped macro smnd$q_npings = 40,0,0,0 %; literal smnd$s_npings = 8; ! Number of pings macro smnd$q_npings_skipped = 48,0,0,0 %; literal smnd$s_npings_skipped = 8; ! Number of times we didn't ping macro smnd$q_nallocated = 56,0,0,1 %; literal smnd$s_nallocated = 8; ! Number of allocated buffers ! ! We use a structure instead of just a quad/long-word because ! insqti - remqti lock 64 bytes at a time, and we don't want to ! lock a queue that other node is trying to access ! macro smnd$R_WQ_CLS = 64,0,0,0 %; literal smnd$S_WQ_CLS = 128; macro smnd$q_work_queue = 64,0,0,0 %; literal smnd$s_work_queue = 8; ! macro smnd$l_work_queue = 64,0,32,0 %; ! macro smnd$b_qbytes = 64,0,0,0 %; literal smnd$s_qbytes = 64; ! + ! ! SMWE$ - Work entry header ! ! - literal SMWE$K_FREE = 0; literal SMWE$K_SENDING = 1; literal SMWE$K_ALLOCATED = 2; literal SMWE$K_INSTANCE_OFFSET = 2; literal SMWE$K_LENGTH = 24; ! Length of structure literal SMWE$C_LENGTH = 24; ! Length of structure literal smwe$S_SMWE = 32; macro smwe$l_link = 0,0,0,0 %; literal smwe$s_link = 8; ! A and B forward link macro smwe$w_size = 8,0,16,0 %; ! Size of SMND$ in bytes macro smwe$b_type = 10,0,8,0 %; ! Structure type DYN$C_SMCI macro smwe$b_subtype = 11,0,8,0 %; ! Structure sub-type DYN$C_SMCI_SMWE macro smwe$l_offset = 12,0,32,0 %; ! offset from channel block macro smwe$l_status = 16,0,32,0 %; ! Longword for clearing macro smwe$w_state = 16,0,16,0 %; macro smwe$w_instance = 18,0,16,0 %; ! Will be 2 plus instance 0/1 ! (2 flags new usage) macro smwe$l_seq = 20,0,32,0 %; ! sequential number macro smwe$l_body = 24,0,32,0 %; ! dummy, pointer to SCS buffer ! + ! ! Negotiation block ! ! - literal nb$m_ready = %X'1'; literal nb$m_agree_h = %X'2'; literal NB$K_LENGTH = 240; ! Length of structure literal NB$C_LENGTH = 240; ! Length of structure literal nb$S_NB = 240; macro nb$q_reserved = 0,0,0,0 %; literal nb$s_reserved = 8; ! padding macro nb$w_size = 8,0,16,0 %; ! Size of NB$ in bytes macro nb$b_type = 10,0,8,0 %; ! Structure type DYN$C_SMCI macro nb$b_subtype = 11,0,8,0 %; ! Structure sub-type DYN$C_SMCI_NB macro nb$l_reserved = 12,0,32,0 %; ! padding macro nb$v_ready = 16,0,1,0 %; ! node ready writing macro nb$v_agree_h = 16,1,1,0 %; ! node agreed macro nb$q_nbsts = 16,0,0,0 %; literal nb$s_nbsts = 8; ! negotiation status quadword macro nb$q_password = 32,0,0,0 %; literal nb$s_password = 16; ! password macro nb$q_nworkq = 48,0,0,0 %; literal nb$s_nworkq = 16; ! number of work queues ??? macro nb$q_buffers = 64,0,0,0 %; literal nb$s_buffers = 16; ! number of buffers macro nb$q_netsize = 80,0,0,0 %; literal nb$s_netsize = 16; ! decnet header size macro nb$q_msg_dg_size = 96,0,0,0 %; literal nb$s_msg_dg_size = 16; ! buffer size macro nb$q_scshdr_size = 112,0,0,0 %; literal nb$s_scshdr_size = 16; ! scs/ppd buffer header size macro nb$q_smwe_size = 128,0,0,0 %; literal nb$s_smwe_size = 16; ! channel buffer header size macro nb$q_smch_size = 144,0,0,0 %; literal nb$s_smch_size = 16; ! channel header size macro nb$q_smnd_size = 160,0,0,0 %; literal nb$s_smnd_size = 16; ! node block size macro nb$q_chanchar = 176,0,0,0 %; literal nb$s_chanchar = 16; ! channel characteristic macro nb$q_channel_add = 192,0,0,0 %; literal nb$s_channel_add = 16; ! number of channels to expand macro nb$q_version = 208,0,0,0 %; literal nb$s_version = 16; ! number of channels to expand macro nb$q_eco_level = 224,0,0,0 %; literal nb$s_eco_level = 16; ! number of channels to expand ! + ! ! Channel Handle ! ! - literal SMH$C_MAX_BUFFERS = 1000; ! Number of buffers literal SMH$K_MAX_BUFFERS = 1000; ! Number of buffers literal SMH$C_BUFFERS = 20; ! Number of buffers literal SMH$K_BUFFERS = 20; ! Number of buffers literal SMH$K_ADD_CHANNELS = 1; ! literal SMH$C_ADD_CHANNELS = 1; ! literal SMH$K_A_end = 0; ! A_end node index literal SMH$K_B_end = 1; ! B_end node index literal smh$K_LENGTH = 212; ! Length of structure literal smh$C_LENGTH = 212; ! Length of structure literal smh$S_SMH = 216; macro smh$q_filler = 0,0,0,1 %; literal smh$s_filler = 8; ! filler macro smh$w_size = 8,0,16,0 %; ! Size of SMH$ in bytes macro smh$b_type = 10,0,8,0 %; ! Structure type DYN$C_SMCI macro smh$b_subtype = 11,0,8,0 %; ! Structure sub-type DYN$C_SMCI_SMH macro smh$B_TAG = 12,0,0,1 %; literal smh$S_TAG = 64; ! section name descriptor macro smh$l_chn_size = 76,0,32,0 %; ! channel entry size macro smh$l_buffers = 80,0,32,0 %; ! Number of buffers macro smh$l_hdr_size = 84,0,32,0 %; ! SMCH header macro smh$l_ndh_size = 88,0,32,0 %; ! SMND header macro smh$l_chb_size = 92,0,32,0 %; ! channel size macro smh$l_virtual_size = 96,0,32,0 %; ! virtual size macro smh$l_physical_size = 100,0,32,0 %; ! physical size macro smh$l_expand = 104,0,32,0 %; ! channel expansion in bytes macro smh$r_reg_id = 112,0,0,0 %; literal smh$s_reg_id = 8; ! Channel region id macro smh$pq_channel = 120,0,0,1 %; literal smh$s_channel = 8; ! channel section pointer macro smh$pl_channel = 120,0,32,1 %; ! channel section pointer macro smh$l_gnode = 128,0,0,0 %; literal smh$s_gnode = 8; ! gNode number A,B macro smh$l_lnode_idx = 136,0,32,0 %; ! local end index A or B macro smh$l_rnode_idx = 140,0,32,0 %; ! remote end index A or B macro smh$l_node_block = 144,0,0,0 %; literal smh$s_node_block = 8; ! gNode number A,B macro smh$l_workq = 152,0,0,0 %; literal smh$s_workq = 16; ! Other end work queue pointer macro smh$l_freeq = 168,0,32,0 %; ! Local-end Harter free head macro smh$l_dbg = 172,0,0,0 %; literal smh$s_dbg = 40; ! debug ! + ! ! Channel pfn packet ! ! - literal smpfn$K_LENGTH = 16; ! Length of structure literal smpfn$C_LENGTH = 16; ! Length of structure literal smpfn$K_DIVF = 3; ! shift factor for division literal smpfn$C_DIVF = 3; ! shift factor for division ! literal smpfn$K_MAXPKT = 9; ! max number of packets literal smpfn$C_MAXPKT = 9; ! max number of packets literal smpfn$S_SMPFN = 16; macro smpfn$I_PFN = 0,0,0,0 %; literal smpfn$S_PFN = 8; ! PFN macro smpfn$L_PADDING = 8,0,32,0 %; macro smpfn$W_LENGTH = 12,0,16,0 %; ! data length macro smpfn$w_boffset = 14,0,16,0 %; ! byte offset from beg. page ! The maximun number of pfn packets cannot be lower than 2. ! The maximun is limited by the lowest of this constant or whatever the ! the channel packet can hold ! ! + ! ! SMCI_FLAGS Sysgen Parameter Flags ! ! - literal smfl$m_allow_self = %X'1'; literal smfl$m_always_load = %X'2'; literal smfl$m_verbose = %X'4'; literal smfl$S_SMFL = 8; macro smfl$v_allow_self = 0,0,1,0 %; ! Allow local communications macro smfl$v_always_load = 0,1,1,0 %; ! Load regardless of cluster macro smfl$v_verbose = 0,2,1,0 %; ! Output more info to the console macro smfl$l_smfl_flags = 0,0,32,0 %; ! Flags longword literal pbfkb$m_fkb_busy = %X'1'; literal pbfkb$S_PB_FKB = 64; macro pbfkb$ps_flink = 0,0,32,1 %; ! flink macro pbfkb$ps_blink = 4,0,32,1 %; ! blink macro pbfkb$w_size = 8,0,16,0 %; ! Size of SMH$ in bytes macro pbfkb$b_type = 10,0,8,0 %; ! Structure type DYN$C_SMCI macro pbfkb$b_subtype = 11,0,8,0 %; ! Structure sub-type DYN$C_SMCI_PBFKB macro pbfkb$v_fkb_busy = 12,0,1,0 %; ! Fork block busy macro pbfkb$l_flags = 12,0,32,0 %; ! Flags longword !*** MODULE $PSBDEF *** ! ! The following constants apply to members of the PSB structure ! literal PSB$K_SIZE_ACCOUNT = 32; ! literal PSB$K_SIZE_USERNAME = 32; ! literal PSB$K_COUNT_PERSONAE = 8; ! literal PSB$K_COUNT_RIGHTS = 10; ! ! ! The following constants apply to members of the PSB structure ! PSB$AR_RIGHTS and PSB$AR_AUTHRIGHTS and should match their bitwise ! counterparts. ! ! NOTE : Any changes to the constants here must be reflected in ! bitfields in the RIGHTS_ENABLED field. ! literal PSB$K_RIGHTS_PERSONA = 0; literal PSB$K_RIGHTS_SYSTEM = 1; literal PSB$K_RIGHTS_INSTALLED = 2; literal PSB$K_RIGHTS_SUBSYSTEM = 3; literal PSB$K_RIGHTS_TEMPORARY = 4; literal PSB$K_RIGHTS_CHKPRO = 9; ! ! Persona Security Block definitions ! literal PSB$M_PERMANENT = %X'1'; literal PSB$M_SECAUDIT = %X'2'; literal PSB$M_CLONE = %X'8'; literal PSB$M_RMS = %X'10'; literal PSB$M_IO = %X'20'; literal PSB$M_TCB = %X'40'; literal PSB$M_DEBIT = %X'80'; literal PSB$M_RESERVE = %X'100'; literal PSB$M_DELEGATE = %X'200'; literal PSB$M_CREATE_USER = %X'400'; literal PSB$M_CREATE_TLV = %X'800'; literal PSB$M_CREATE_ITMLST = %X'1000'; literal PSB$K_FLAGS_BIT_COUNT = 13; ! Number of flags literal PSB$M_DELETE_PENDING = %X'20000000'; literal PSB$M_DP_PROCESSING = %X'40000000'; literal PSB$M_DEALLOCATED = %X'80000000'; literal PSB$K_RESERVE_PERSONA_LENGTH = 56; literal PSB$M_PERSONA = %X'1'; literal PSB$M_SYSTEM = %X'2'; literal PSB$M_INSTALLED = %X'4'; literal PSB$M_SUBSYSTEM = %X'8'; literal PSB$M_TEMPORARY = %X'10'; literal PSB$M_CHKPRO = %X'200'; literal PSB$K_CLONE_REGION_SIZE = 228; literal PSB$S_PSB = 296; macro PSB$L_FLINK = 0,0,32,1 %; ! Standard listhead forward link macro PSB$L_BLINK = 4,0,32,1 %; ! Standard listhead backward link macro PSB$W_SIZE = 8,0,16,0 %; ! Standard structure size, in bytes macro PSB$B_TYPE = 10,0,8,0 %; ! Standard type code for PSB (DYN$C_SECURITY) macro PSB$B_SUBTYPE = 11,0,8,0 %; ! Standard subtype code (DYN$C_SECURITY_PSB) macro PSB$L_DEBUG_DATA_1 = 12,0,32,0 %; ! First of 2 debug data cells macro PSB$L_DEBUG_FLINK = 12,0,32,1 %; ! Forward link to previous PSB (DEBUG) macro PSB$L_DEBUG_DATA_2 = 16,0,32,0 %; ! Second of 2 debug data cells macro PSB$L_DEBUG_BLINK = 16,0,32,1 %; ! Backward link to previous PSB (DEBUG) macro PSB$L_DEBUG_PID = 20,0,32,0 %; ! PID of process that allocated this PSB (DEBUG) macro PSB$L_FLAGS = 24,0,32,0 %; ! Every structure needs a set of flags :-) macro PSB$V_PERMANENT = 24,0,1,0 %; ! This PSB is permanent macro PSB$V_SECAUDIT = 24,1,1,0 %; ! Security audit Mandatory macro PSB$V_CLONE = 24,3,1,0 %; ! PSB created via Clone operation. macro PSB$V_RMS = 24,4,1,0 %; ! PSB created in RMS macro PSB$V_IO = 24,5,1,0 %; ! PSB created in IO macro PSB$V_TCB = 24,6,1,0 %; ! This PSB is part of the TCB macro PSB$V_DEBIT = 24,7,1,0 %; ! Debit BYTLM/BYTCNT for this structure macro PSB$V_RESERVE = 24,8,1,0 %; ! Dummy PSB ("Runt") to hold persona index in server macro PSB$V_DELEGATE = 24,9,1,0 %; ! PSB created via Delegate operation macro PSB$V_CREATE_USER = 24,10,1,0 %; ! PSB created via $PERSONA_CREATE with username parameter macro PSB$V_CREATE_TLV = 24,11,1,0 %; ! PSB created via $PERSONA_CREATE with profile (tlv) parameter macro PSB$V_CREATE_ITMLST = 24,12,1,0 %; ! PSB created via $PERSONA_CREATE with itemlist parameter macro PSB$V_DELETE_PENDING = 24,29,1,0 %; ! Request for persona delete pending ... macro PSB$V_DP_PROCESSING = 24,30,1,0 %; ! PSB in process od DELETE_PENDING processing macro PSB$V_DEALLOCATED = 24,31,1,0 %; ! PSB has been deallocated (pool monitoring) macro PSB$L_PERSONA_ID = 28,0,32,0 %; ! Persona id assigned to this PSB macro PSB$L_REFCOUNT = 32,0,32,0 %; ! Number of attached execution contexts to this PSB macro PSB$O_UID = 36,0,0,0 %; literal PSB$S_UID = 16; ! Universal identifier assigned to persona macro PSB$T_CLONE_REGION = 52,0,0,0 %; ! Start of area copied when PSB is cloned macro PSB$L_MODE = 52,0,32,0 %; ! Access level for this PSB (User,Supervisor,Exec,Kernel) ! End of the reserve PSB (runt). macro PSB$T_USERNAME = 56,0,0,0 %; literal PSB$S_USERNAME = 32; ! Persona Username macro PSB$T_ACCOUNT = 88,0,0,0 %; literal PSB$S_ACCOUNT = 32; ! Persona Account name macro PSB$L_NOAUDIT = 120,0,32,0 %; ! Non-zero implies no audit status macro PSB$L_UIC = 124,0,32,0 %; ! UIC of persona macro PSB$W_MEM = 124,0,16,0 %; ! Member number in UIC macro PSB$W_GRP = 126,0,16,0 %; ! Group number in UIC ! UIC_FLAGS must always follow UIC macro PSB$L_UIC_FLAGS = 128,0,32,0 %; ! UIC identifier flags longword ! (should always be zero) macro PSB$L_CONCEALED_COUNT = 132,0,32,0 %; ! Hidden reference tracking macro PSB$L_OFF_PROCESS_PTR = 136,0,32,1 %; ! Ptr to off_process ringbuffer macro PSB$Q_DOI = 144,0,0,0 %; literal PSB$S_DOI = 8; ! Domain Of Interpretation macro PSB$L_DOI = 144,0,32,0 %; macro PSB$L_DOI_PID = 148,0,32,0 %; macro PSB$Q_AUTHPRIV = 152,0,0,0 %; literal PSB$S_AUTHPRIV = 8; ! Allowable privileges macro PSB$Q_PERMPRIV = 160,0,0,0 %; literal PSB$S_PERMPRIV = 8; ! Permanent privileges macro PSB$Q_WORKPRIV = 168,0,0,0 %; literal PSB$S_WORKPRIV = 8; ! Current working privileges macro PSB$Q_IMAGE_WORKPRIV = 176,0,0,0 %; literal PSB$S_IMAGE_WORKPRIV = 8; ! Image working privileges macro PSB$L_RIGHTS_ENABLED = 184,0,32,0 %; ! Bitmap of enabled/disabled rights pointers macro PSB$V_PERSONA = 184,0,1,0 %; ! in rights array macro PSB$V_SYSTEM = 184,1,1,0 %; ! macro PSB$V_INSTALLED = 184,2,1,0 %; ! macro PSB$V_SUBSYSTEM = 184,3,1,0 %; ! macro PSB$V_TEMPORARY = 184,4,1,0 %; ! macro PSB$V_CHKPRO = 184,9,1,0 %; ! Rights slot reserved for CHKPRO processing macro PSB$AR_AUTHRIGHTS = 188,0,0,1 %; literal PSB$S_AUTHRIGHTS = 40; ! Array of pointers to authorized rights chains macro PSB$AR_RIGHTS = 228,0,0,1 %; literal PSB$S_RIGHTS = 40; ! Array of pointers to active rights chains macro PSB$AR_CLASS = 268,0,32,1 %; ! Pointer to classification data block macro PSB$L_POSIX_UID = 272,0,32,0 %; ! POSIX UID field macro PSB$L_POSIX_GID = 276,0,32,0 %; ! POSIX GID field macro PSB$L_PXB_COUNT = 280,0,32,0 %; ! Number of extensions registered when this persona is created. macro PSB$AR_PXB_ARRAY = 284,0,32,1 %; ! Pointer to array of pointers to this PSB's extension blocks. macro PSB$Q_PXB_MUTEX = 288,0,0,0 %; literal PSB$S_PXB_MUTEX = 8; ! Mutex to sych access to this PSB's fields. literal PSB$K_LENGTH = 296; ! Length of PSB structure literal PSA$S_PSB_ARRAY = 16; macro PSA$L_FLINK = 0,0,32,1 %; ! Standard listhead forward link macro PSA$L_BLINK = 4,0,32,1 %; ! Standard listhead backward link macro PSA$W_SIZE = 8,0,16,0 %; ! Standard structure size, in bytes macro PSA$B_TYPE = 10,0,8,0 %; ! Standard type code for PSB (DYN$C_SECURITY) macro PSA$B_SUBTYPE = 11,0,8,0 %; ! Standard subtype code (DYN$C_SECURITY_PSB) macro PSA$T_ELEMENTS = 16,0,0,0 %; ! Offset to first element in array ! ! The following constants are used in TLV conversion of PSB structures ! The first 6 items are positioned for backward compatibility the ! older CHP$_ item codes and should not be changed. ! ! The ADD_RIGHTS and ADD_AUTHRIGHTS codes below should not be used. They ! are here to be compatible with the item codes found in ISSDEF. ! ! Any changes to the list below should also be reflected in the ! module [STARLET] ISSDEF.SDL literal PSB$_TLV_FLAGS = 1; ! 1 literal PSB$_TLV_ARBFLAGS = 2; ! 2 CHP$_FLAGS Placeholder to avoid conflict with ARB TLVs literal PSB$_TLV_ARBPRIV = 3; ! 3 CHP$_PRIVS Placeholder to avoid conflict with ARB TLVs literal PSB$_TLV_MODE = 4; ! 4 literal PSB$_TLV_WORKCLASS = 5; ! 5 literal PSB$_TLV_RIGHTS = 6; ! 6 ! 7 ISS$_ADD_RIGHTS placeholder ! 8 ISS$_ADD_AUTHRIGHTS placeholder literal PSB$_TLV_USERNAME = 9; ! 9 literal PSB$_TLV_ACCOUNT = 10; ! 10 literal PSB$_TLV_NOAUDIT = 11; ! 11 literal PSB$_TLV_AUTHPRIV = 12; ! 12 literal PSB$_TLV_PERMPRIV = 13; ! 13 literal PSB$_TLV_IMAGE_WORKPRIV = 14; ! 14 literal PSB$_TLV_RIGHTS_ENABLED = 15; ! 15 literal PSB$_TLV_AUTHRIGHTS = 16; ! 16 literal PSB$_TLV_MINCLASS = 17; ! 17 literal PSB$_TLV_MAXCLASS = 18; ! 18 literal PSB$_TLV_UID = 19; ! 19 ! 20 ! 21 literal PSB$_TLV_UIC = 22; ! 22 literal PSB$_TLV_WORKPRIV = 23; ! 23 literal PSB$_TLV_POSIX_UID = 24; ! 24 literal PSB$_TLV_POSIX_GID = 25; ! 25 literal PSB$_TLV_MIN_CODE = 1; literal PSB$_TLV_MAX_CODE = 25; ! ! The following PSB RingBuffer structure is employed for recording recent persona activity ! for a given process. P1 storage is allocated during process creation for ! this purpose. ! ! ! literal PSBRB$M_CLONE_PSB = %X'1'; literal PSBRB$M_DEREFERENCE_PSB = %X'2'; literal PSBRB$M_DELETE_PERSONA = %X'4'; literal PSBRB$M_FREE_PSB = %X'8'; literal PSBRB$M_REFERENCE_PSB = %X'10'; literal PSBRB$M_ASSUME_PERSONA = %X'20'; literal PSBRB$M_SET_NATURAL = %X'40'; literal PSBRB$S_PSBRB = 80; macro PSBRB$L_FLINK = 0,0,32,1 %; ! Standard listhead forward link macro PSBRB$L_BLINK = 4,0,32,1 %; ! Standard listhead backward link macro PSBRB$W_SIZE = 8,0,16,0 %; ! Standard structure size, in bytes macro PSBRB$B_TYPE = 10,0,8,0 %; ! Standard type code for PSB (DYN$C_SECURITY) macro PSBRB$B_SUBTYPE = 11,0,8,0 %; ! Standard subtype code (DYN$C_SECURITY_PRB) macro PSBRB$L_MAX_INDEX = 12,0,32,0 %; ! Maximum number of records in ring macro PSBRB$L_CURRENT_INDEX = 16,0,32,0 %; ! Index of nex record to be written in the RingBuffer macro PSBRB$T_RECORDS = 20,0,0,0 %; ! Offset to first record in RingBuffer macro PSBRB$L_FUNCTION = 20,0,32,0 %; ! Define which support routine is reporting this record macro PSBRB$V_CLONE_PSB = 20,0,1,0 %; ! NSA$CLONE_PSB macro PSBRB$V_DEREFERENCE_PSB = 20,1,1,0 %; ! NSA$DEREFERENCE_PSB macro PSBRB$V_DELETE_PERSONA = 20,2,1,0 %; ! NSA$DELETE_PERSONA macro PSBRB$V_FREE_PSB = 20,3,1,0 %; ! NSA$FREE_PSB macro PSBRB$V_REFERENCE_PSB = 20,4,1,0 %; ! NSA$REFERENCE_PSB macro PSBRB$V_ASSUME_PERSONA = 20,5,1,0 %; ! NSA$ASSUME_PERSONA macro PSBRB$V_SET_NATURAL = 20,6,1,0 %; ! NSA$SET_NATURAL macro PSBRB$L_PSB = 24,0,32,0 %; ! Address of PSB being acted upon by the function macro PSBRB$L_REFCNT = 28,0,32,0 %; ! Current reference count the above PSB macro PSBRB$L_FLAGS = 32,0,32,0 %; ! Contents of PSB flags macro PSBRB$L_MODE = 36,0,32,0 %; ! Access mode of current PSB macro PSBRB$L_PC = 40,0,32,0 %; ! Address from where the function was called macro PSBRB$L_PSL = 44,0,32,0 %; ! PSL at the time of the operation macro PSBRB$L_UTHREAD_ID = 48,0,32,0 %; ! Current active DECthread (if any) macro PSBRB$L_KTB = 52,0,32,0 %; ! Current KTB macro PSBRB$L_CPU = 56,0,32,0 %; ! CPU ID from current KTB ! Function specific information macro PSBRB$L_AUX_1 = 60,0,32,0 %; ! $Assume = previous PSB ! $Clone = PSB being created macro PSBRB$L_AUX_2 = 64,0,32,0 %; ! $Assume = previous PSB reference count macro PSBRB$L_AUX_3 = 68,0,32,0 %; ! debug_data_1 macro PSBRB$L_AUX_4 = 72,0,32,0 %; ! debug_data_2 literal PSBRB$K_RINGBUFFER_RECORD_SIZE = 56; literal PSBRB$K_RINGBUFFER_RECORDS = 1000; literal PSBRB$K_RINGBUFFER_SIZE = 56020; !*** MODULE $CLUBDEF *** ! + ! CLUB - CLUSTER BLOCK. ! ! THERE IS ONE CLUB IN A VMS SYSTEM THAT IS PART OF A CLUSTER. ! THE CLUB DEFINES THE STATE OF THE THE CLUSTER AS KNOWN TO ! THE LOCAL SYSTEM. ! - ! ! THE CLUB FORK BLOCK (CLUBFKB) IS A SUBBLOCK OF THE CLUB THAT IS ! USED WHEN IT NECESSARY TO WAIT IN ORDER TO ALLOCATE MEMORY OR ! WHEN IT IS DESIRABLE TO FORK TO ALLOW OTHER FORK PROCESSES A ! CHANCE TO RUN. literal CLUBFKB$M_FKB_BUSY = %X'1'; literal CLUBFKB$M_FORKQ = %X'2'; literal CLUBFKB$C_LENGTH = 56; ! LENGTH OF CLUBFKB literal CLUBFKB$K_LENGTH = 56; ! LENGTH OF CLUBFKB literal CLUBFKB$S_CLUBFKBDEF = 56; ! Old size name, synonym literal CLUBFKB$S_CLUBFKB = 56; macro CLUBFKB$B_FORK_BLOCK = 0,0,0,1 %; literal CLUBFKB$S_FORK_BLOCK = 48; ! FORK BLOCK TO WAIT IN macro CLUBFKB$L_PC2 = 48,0,32,0 %; ! SAVED PC macro CLUBFKB$L_STATUS = 52,0,32,0 %; ! CLUSTER FAILOVER STATUS FLAGS macro CLUBFKB$V_FKB_BUSY = 52,0,1,0 %; ! FORK BLOCK IN USE FLAG macro CLUBFKB$V_FORKQ = 52,1,1,0 %; ! FORK BLOCK ON FORK QUEUE ! ! THE CLUB POWERFAIL FORK BLOCK (CLUBPWF) IS A SUBBLOCK OF THE CLUB ! THAT IS USED TO FORK FROM IPL 31 TO IPL SCS DURING POWER RECOVERY. literal CLUBPWF$M_BUSY = %X'1'; literal CLUBPWF$C_LENGTH = 56; ! LENGTH OF CLUBPWF literal CLUBPWF$K_LENGTH = 56; ! LENGTH OF CLUBPWF literal CLUBPWF$S_CLUBPWFDEF = 56; ! Old size name, synonym literal CLUBPWF$S_CLUBPWF = 56; macro CLUBPWF$B_FORK_BLOCK = 0,0,0,1 %; literal CLUBPWF$S_FORK_BLOCK = 48; ! FORK BLOCK TO WAIT IN ! Place STATUS in aligned quadword for interlocked instructions macro CLUBPWF$L_STATUS = 48,0,32,0 %; ! BLOCK STATUS FLAGS macro CLUBPWF$V_BUSY = 48,0,1,0 %; ! FORK BLOCK IN USE FLAG ! ! THE CLUSTER FAILOVER CONTROL BLOCK (CLUFCB) IS A SUBBLOCK OF ! THE CLUB THAT IS USED TO SEQUENCE FAILOVER ACTIONS IN A CLUSTER. ! literal CLUFCB$M_ACTIVE = %X'1'; literal CLUFCB$M_PENDING = %X'2'; literal CLUFCB$M_SYNC_NODE = %X'4'; literal CLUFCB$M_FKB_BUSY = %X'8'; literal CLUFCB$M_WAITING = %X'10'; literal CLUFCB$M_AUX = %X'20'; literal CLUFCB$M_RB_SUSPEND = %X'40'; literal CLUFCB$C_LENGTH = 136; ! LENGTH OF CLUFCB literal CLUFCB$K_LENGTH = 136; ! LENGTH OF CLUFCB literal CLUFCB$S_CLUFCBDEF = 136; ! Old size name, synonym literal CLUFCB$S_CLUFCB = 136; macro CLUFCB$B_FORK_BLOCK = 0,0,0,1 %; literal CLUFCB$S_FORK_BLOCK = 48; ! FORK BLOCK TO WAIT IN macro CLUFCB$L_STEP = 48,0,32,0 %; ! CURRENT FAILOVER STEP INDEX macro CLUFCB$L_ID = 52,0,32,0 %; ! FAILOVER INSTANCE IDENTIFICATION macro CLUFCB$L_STATUS = 56,0,32,0 %; ! CLUSTER FAILOVER STATUS FLAGS macro CLUFCB$V_ACTIVE = 56,0,1,0 %; ! FAILOVER ROUTINE ACTIVE macro CLUFCB$V_PENDING = 56,1,1,0 %; ! FAILOVER PENDING macro CLUFCB$V_SYNC_NODE = 56,2,1,0 %; ! LOCAL NODE IS SYNCHRONIZER macro CLUFCB$V_FKB_BUSY = 56,3,1,0 %; ! FORK BLOCK IN USE FLAG macro CLUFCB$V_WAITING = 56,4,1,0 %; ! WAITING FOR NODES TO RESPOND macro CLUFCB$V_AUX = 56,5,1,0 %; ! AUXILIARY FORK BLOCK ALLOCATED macro CLUFCB$V_RB_SUSPEND = 56,6,1,0 %; ! REBUILD SUSPENDED macro CLUFCB$L_SYNC_CSB = 60,0,32,1 %; ! ADDRESS OF CSB OF SYNCHRONIZING SYSTEM macro CLUFCB$B_NODEMAP = 64,0,0,1 %; literal CLUFCB$S_NODEMAP = 32; ! BITMAP OF ALL INVOLVED NODES macro CLUFCB$B_RESPMAP = 96,0,0,1 %; literal CLUFCB$S_RESPMAP = 32; ! BITMAP OF NODES READY FOR A STEP macro CLUFCB$L_INDEX = 128,0,32,0 %; ! STORAGE FOR BIT MAP INDEX macro CLUFCB$L_AUX_FKB = 132,0,32,1 %; ! ADDRESS OF AUXILIARY FORK BLOCK ! Cluster Page Cache (CLUPGC) - buffer cache of S0/S1 (Alpha sized) pages. ! An array of these structures is kept in the CLUB at the CLUB$L_PGCLIST offset. ! Each structure corresponds to the appropriate index for buffer size of 1-9 pages. ! Index level 0 is used for statistics across all buffer sizes. literal CLUPGC$S_CLUPGC = 32; macro CLUPGC$L_LINK = 0,0,32,0 %; ! First cached entry or zero macro CLUPGC$L_CUR_CACHED = 4,0,32,0 %; ! # cached entries of this size macro CLUPGC$L_CUR_IN_USE = 8,0,32,0 %; ! # active buffers of this size macro CLUPGC$L_MAX_IN_USE = 12,0,32,0 %; ! Max # active buffers of this size macro CLUPGC$L_MAX_CACHED = 16,0,32,0 %; ! Max # cached entries of this size macro CLUPGC$L_CACHE_LIM = 20,0,32,0 %; ! Limit value for this size macro CLUPGC$L_LAST_ALLOC = 24,0,32,0 %; ! ABSTIM of last allocation macro CLUPGC$L_LAST_DEALLOC = 28,0,32,0 %; ! ABSTIM of last deallocation literal CLUB$M_CLUSTER = %X'1'; literal CLUB$M_QF_ACTIVE = %X'2'; literal CLUB$M_QF_DYNVOTE = %X'4'; literal CLUB$M_QF_WATCHER = %X'8'; literal CLUB$M_SHUTDOWN = %X'10'; literal CLUB$M_QF_REFRESH_REQ = %X'20'; literal CLUB$M_LNM_RESYNCH = %X'40'; literal CLUB$M_STS_PPHASE = %X'100'; literal CLUB$M_STS_PH0 = %X'200'; literal CLUB$M_STS_PH1B = %X'400'; literal CLUB$M_STS_PH1 = %X'800'; literal CLUB$M_STS_PH2 = %X'1000'; literal CLUB$M_TDF_VALID = %X'2000'; literal CLUB$M_FKB_BUSY = %X'10000'; literal CLUB$M_UNLOCK = %X'20000'; literal CLUB$M_NO_FORM = %X'40000'; literal CLUB$M_INIT = %X'80000'; literal CLUB$M_BACKOUT = %X'100000'; literal CLUB$M_PRIOR_PROTOCOL = %X'200000'; literal CLUB$M_VERBOSE = %X'400000'; literal CLUB$M_LOST_CNX = %X'800000'; literal CLUB$M_QF_FAILED_NODE = %X'1000000'; literal CLUB$M_QF_VOTE = %X'2000000'; literal CLUB$M_QF_NEWVOTE = %X'4000000'; literal CLUB$M_ADJ_QUORUM = %X'8000000'; literal CLUB$M_QUORUM = %X'10000000'; literal CLUB$M_TRANSITION = %X'20000000'; literal CLUB$M_RESLOCKIP = %X'40000000'; literal CLUB$M_QTQEBSY = %X'80000000'; literal CLUB$M_LK_MERGEIP = %X'4'; literal CLUB$M_LK_DO_FULL = %X'8'; literal CLUB$M_LK_FULL = %X'10'; literal CLUB$M_LK_DO_DIR = %X'20'; literal CLUB$M_LK_DIR = %X'40'; literal CLUB$M_LK_NO_RMVDIR = %X'80'; literal CLUB$M_LK_INIT_RBLD = %X'100'; literal CLUB$M_LK_NO_RM = %X'200'; literal CLUB$M_LK_TABLE_V51 = %X'400'; literal CLUB$M_LK_SPECIAL_1 = %X'800'; literal CLUB$M_LK_RM_DSBL = %X'1000'; literal CLUB$M_LK_TABLE_1 = %X'2000'; literal CLUB$M_LK_SHUTDOWN = %X'4000'; literal CLUB$M_LK_SHUT_IP = %X'8000'; literal CLUB$M_NO_FQUORUM = %X'1'; literal CLUB$M_NO_DQUORUM = %X'2'; literal CLUB$M_IFW_REQ = %X'4'; literal CLUB$M_RNS_REQ = %X'8'; literal CLUB$M_CLUGEN_VALID = %X'1'; literal CLUB$C_LENGTH = 1056; ! LENGTH OF CLUB literal CLUB$K_LENGTH = 1056; ! LENGTH OF CLUB literal CLUB$S_CLUBDEF = 1056; ! Old size name, synonym literal CLUB$S_CLUB = 1056; macro CLUB$L_CSBQFL = 0,0,32,1 %; ! CSB QUEUE FORWARD LINK macro CLUB$L_CSBQBL = 4,0,32,1 %; ! CSB QUEUE BACKWARD LINK macro CLUB$W_SIZE = 8,0,16,0 %; ! SIZE OF CLUB IN BYTES macro CLUB$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE macro CLUB$B_SUBTYPE = 11,0,8,0 %; ! STRUCTURE SUBTYPE macro CLUB$L_POLL_CTX = 12,0,32,0 %; ! SCS POLLER CONTEXT macro CLUB$L_LOCAL_CSB = 16,0,32,1 %; ! ADDRESS OF THE CSB FOR LOCAL SYSTEM macro CLUB$L_ASTQFL = 20,0,32,1 %; ! AST QUEUE FORWARD LINK macro CLUB$L_ASTQBL = 24,0,32,1 %; ! AST QUEUE BACKWARD LINK macro CLUB$L_FLAGS = 28,0,32,0 %; ! CLUSTER STATUS FLAGS macro CLUB$V_CLUSTER = 28,0,1,0 %; ! THIS NODE IS MEMBER OF CLUSTER macro CLUB$V_QF_ACTIVE = 28,1,1,0 %; ! QUORUM FILE IS READABLE, CONTRIBUTE TO STATIC QUORUM macro CLUB$V_QF_DYNVOTE = 28,2,1,0 %; ! QUORUM FILE CAN CONTRIBUTE TO DYNAMIC QUORUM macro CLUB$V_QF_WATCHER = 28,3,1,0 %; ! NODE IS QUORUM FILE WATCHER macro CLUB$V_SHUTDOWN = 28,4,1,0 %; ! NODE READY FOR CLUSTER SHUTDOWN macro CLUB$V_QF_REFRESH_REQ = 28,5,1,0 %; ! QUORUM FILE REFRESH REQUESTED macro CLUB$V_LNM_RESYNCH = 28,6,1,0 %; ! CLUSTERWIDE LOGICAL NAME RESYNCH THREAD ACTIVE macro CLUB$V_STS_PPHASE = 28,8,1,0 %; ! STATUS ANALYZER POLLING PHASE macro CLUB$V_STS_PH0 = 28,9,1,0 %; ! STATUS ANALYZER, PHASE 0 SEEN macro CLUB$V_STS_PH1B = 28,10,1,0 %; ! STATUS ANALYZER, PHASE 1 (COORD CNX BROKEN) SEEN macro CLUB$V_STS_PH1 = 28,11,1,0 %; ! STATUS ANALYZER, PHASE 1 (COORD CNX OK) SEEN macro CLUB$V_STS_PH2 = 28,12,1,0 %; ! STATUS ANALYZER, PHASE 2 SEEN macro CLUB$V_TDF_VALID = 28,13,1,0 %; ! Indicates that TDF in club has been written macro CLUB$V_FKB_BUSY = 28,16,1,0 %; ! FORK BLOCK IN USE macro CLUB$V_UNLOCK = 28,17,1,0 %; ! UNLOCK REQUESTED macro CLUB$V_NO_FORM = 28,18,1,0 %; ! PROHIBIT NODE FROM FORMING A NEW CLUSTER macro CLUB$V_INIT = 28,19,1,0 %; ! READY FOR CLUSTER JOIN/FORMATION macro CLUB$V_BACKOUT = 28,20,1,0 %; ! MUST EVENTUALLY BACK-OUT TRANSITION macro CLUB$V_PRIOR_PROTOCOL = 28,21,1,0 %; ! Earlier version protocol present macro CLUB$V_VERBOSE = 28,22,1,0 %; ! VERBOSE MODE macro CLUB$V_LOST_CNX = 28,23,1,0 %; ! CONNECTION TO CLUSTER MEMBER HAS BEEN LOST macro CLUB$V_QF_FAILED_NODE = 28,24,1,0 %; ! A NODE HAS BEEN FAILED OUT macro CLUB$V_QF_VOTE = 28,25,1,0 %; ! QUORUM DISK IS CONTRIBUTING A (STATIC) VOTE macro CLUB$V_QF_NEWVOTE = 28,26,1,0 %; ! STAGING FOR QF_VOTE macro CLUB$V_ADJ_QUORUM = 28,27,1,0 %; ! QUORUM ADJUSTMENT REQUESTED macro CLUB$V_QUORUM = 28,28,1,0 %; ! CLUSTER IS IN QUORUM macro CLUB$V_TRANSITION = 28,29,1,0 %; ! STATE TRANSITION IN PROGRESS macro CLUB$V_RESLOCKIP = 28,30,1,0 %; ! RESERVATION LOCK IN PROGRESS macro CLUB$V_QTQEBSY = 28,31,1,0 %; ! QUORUM TQE IS ALREADY IN QUE macro CLUB$L_LK_FLAGS = 32,0,32,0 %; macro CLUB$V_LK_MERGEIP = 32,2,1,0 %; ! MERGE IN PROGRESS (LOCAL) macro CLUB$V_LK_DO_FULL = 32,3,1,0 %; ! DO A FULL REBUILD macro CLUB$V_LK_FULL = 32,4,1,0 %; ! FULL REBUILD macro CLUB$V_LK_DO_DIR = 32,5,1,0 %; ! DO A DIRECTORY REBUILD macro CLUB$V_LK_DIR = 32,6,1,0 %; ! DIRECTORY REBUILD macro CLUB$V_LK_NO_RMVDIR = 32,7,1,0 %; ! INHIBIT RMVDIRS macro CLUB$V_LK_INIT_RBLD = 32,8,1,0 %; ! INITIAL REBUILD FLAG macro CLUB$V_LK_NO_RM = 32,9,1,0 %; ! (obsolete) macro CLUB$V_LK_TABLE_V51 = 32,10,1,0 %; ! (obsolete) macro CLUB$V_LK_SPECIAL_1 = 32,11,1,0 %; ! (obsolete) macro CLUB$V_LK_RM_DSBL = 32,12,1,0 %; ! REMASTER DISABLED DUE TO REBUILD macro CLUB$V_LK_TABLE_1 = 32,13,1,0 %; ! FAILOVER TABLE 1 IN USE macro CLUB$V_LK_SHUTDOWN = 32,14,1,0 %; ! SHUTDOWN REQUESTED macro CLUB$V_LK_SHUT_IP = 32,15,1,0 %; ! SHUTDOWN IN PROGRESS macro CLUB$W_RSEQNUM = 36,0,16,0 %; ! FULL REBUILD SEQUENCE NUMBER macro CLUB$W_DIRSEQNUM = 38,0,16,0 %; ! DIRECTORY REBUILD SEQ macro CLUB$B_QSTATUS = 40,0,8,0 %; ! QUORUM STATUS FLAGS macro CLUB$V_NO_FQUORUM = 40,0,1,0 %; ! NO FORMAL QUORUM macro CLUB$V_NO_DQUORUM = 40,1,1,0 %; ! NO DYNAMIC QUORUM macro CLUB$V_IFW_REQ = 40,2,1,0 %; ! INCARNATION FILE WRITE REQUIRED macro CLUB$V_RNS_REQ = 40,3,1,0 %; ! REMOVED NODE STATUS REQUIRED macro CLUB$W_QDVOTES = 42,0,16,0 %; ! VOTES HELD BY QUORUM DISK macro CLUB$W_QUORUM = 44,0,16,0 %; ! CLUSTER QUORUM macro CLUB$W_VOTES = 46,0,16,0 %; ! CLUSTER VOTES macro CLUB$W_CEVOTES = 48,0,16,0 %; ! UNIVERSE OF VOTES macro CLUB$W_ADJ_CEVOTES = 50,0,16,0 %; ! UNIVERSE OF VOTES ADJUSTMENT REQUESTED VALUE macro CLUB$W_NODES = 52,0,16,0 %; ! NODES IN CLUSTER macro CLUB$B_FSYSID = 54,0,0,1 %; literal CLUB$S_FSYSID = 6; ! FOUNDING NODE'S SYSID macro CLUB$Q_FTIME = 64,0,0,1 %; literal CLUB$S_FTIME = 8; ! FOUNDING TIME macro CLUB$L_LST_XTN = 72,0,32,0 %; ! LAST COMPLETED TRANSACTION NUMBER macro CLUB$L_LST_COORD = 76,0,32,0 %; ! LAST COMPLETED TRANSACTION COORDINATOR CSID macro CLUB$Q_LST_TIME = 80,0,0,1 %; literal CLUB$S_LST_TIME = 8; ! LAST COMPLETED TRANSACTION TIME-STAMP macro CLUB$B_LST_CODE = 88,0,8,0 %; ! LAST COMPLETED TRANSACTION CODE macro CLUB$B_LST_PHASE = 89,0,8,0 %; ! LAST COMPLETED TRANSACTION CODE macro CLUB$W_NEWQDVOTES = 90,0,16,0 %; ! STAGING FOR QDVOTES macro CLUB$L_CUR_XTN = 92,0,32,0 %; ! CURRENT TRANSACTION NUMBER macro CLUB$L_CUR_COORD = 96,0,32,0 %; ! CURRENT TRANSACTION COORDINATOR CSID macro CLUB$Q_CUR_TIME = 104,0,0,1 %; literal CLUB$S_CUR_TIME = 8; ! CURRENT TRANSACTION TIME-STAMP macro CLUB$B_CUR_CODE = 112,0,8,0 %; ! TRANSACTION CODE macro CLUB$B_CUR_PHASE = 113,0,8,0 %; ! TRANSACTION PHASE macro CLUB$W_MSGCNT = 114,0,16,0 %; ! OUTSTANDING/WAITING MESSAGE COUNT macro CLUB$L_COORD = 116,0,32,1 %; ! COORDINATOR'S CSB ADDRESS macro CLUB$L_LOCAL_CSID = 120,0,32,0 %; ! LOCAL SYSTEM CSID macro CLUB$W_LOCAL_CSID_IDX = 120,0,16,0 %; ! SLOT INDEX macro CLUB$W_LOCAL_CSID_SEQ = 122,0,16,0 %; ! SEQUENCE NUMBER macro CLUB$W_NEXT_CSID = 124,0,16,0 %; ! INDEX OF NEXT CSID TO ASSIGN macro CLUB$W_FIRST_INDEX = 126,0,16,0 %; ! INDEX OF FIRST CSID ASSIGNED macro CLUB$L_MAX_XTN = 128,0,32,0 %; ! LARGEST TRANSACTION ID SEEN macro CLUB$L_RETRYCNT = 132,0,32,0 %; ! RESOURCE ALLOCATION RETRIES AVAILABLE macro CLUB$L_CTX0 = 136,0,32,0 %; ! LEVEL 0 CONTEXT AREA macro CLUB$L_RET1 = 140,0,32,0 %; ! LEVEL 1 SUBROUTINE RETURN macro CLUB$L_CTX1 = 144,0,32,0 %; ! LEVEL 1 CONTEXT AREA macro CLUB$L_RET2 = 148,0,32,0 %; ! LEVEL 2 SUBROUTINE RETURN macro CLUB$L_CTX2 = 152,0,32,0 %; ! LEVEL 2 CONTEXT AREA macro CLUB$L_TQE = 156,0,32,1 %; ! ADDRESS OF TIMER ENTRY macro CLUB$L_CSPIPID = 160,0,32,0 %; ! PID OF CLUSTER SERVER (FOR SCH$WAKE) macro CLUB$Q_NEWTIME = 168,0,0,0 %; literal CLUB$S_NEWTIME = 8; ! NEW VALUE OF TIME macro CLUB$Q_NEWTIME_REF = 176,0,0,0 %; literal CLUB$S_NEWTIME_REF = 8; ! LOCAL REFERENCE FOR NEW TIME macro CLUB$W_NEWQUORUM = 184,0,16,0 %; ! NEW VALUE FOR QUORUM macro CLUB$W_NEWCEVOTES = 186,0,16,0 %; ! NEW UNIVERSE OF VOTES macro CLUB$L_FMERIT = 188,0,32,0 %; ! FIGURE OF MERIT FOR OPTIMAL CLUSTER macro CLUB$L_E_MEMSEQ = 192,0,32,0 %; ! EXTENDED MEMBERSHIP STATE SEQUENCE NUMBER macro CLUB$W_MEMSEQ = 192,0,16,0 %; ! MEMBERSHIP STATE SEQUENCE NUMBER macro CLUB$L_RANDOM = 196,0,32,0 %; ! RANDOM NUMBER GENERATOR CONTEXT macro CLUB$L_CLUDCB = 200,0,32,1 %; ! ADDRESS OF QUORUM DISK CONTROL BLOCK macro CLUB$T_QDNAME = 204,0,0,0 %; literal CLUB$S_QDNAME = 16; ! QUORUM DISK FULLDEVNAM macro CLUB$L_CLUICB = 220,0,32,1 %; ! ADDRESS OF INCARNATION FILE CONTROL BLOCK macro CLUB$L_FOREIGN_CLUSTER = 224,0,32,0 %; ! SHIFT REGISTER INDICATING FOREIGN CLUSTER SEEN macro CLUB$L_ENBL_VERBOSE = 228,0,32,0 %; ! TIME TO ENABLE VERBOSE MODE macro CLUB$L_QLOST_CLUGEN = 232,0,32,0 %; ! CLUSTER GENERATION WHEN QUORUM LOST macro CLUB$L_STG_JOIN_CLUGEN = 236,0,32,0 %; ! STAGING AREA FOR CLUSTER GENERATION macro CLUB$L_JOIN_CLUGEN = 240,0,32,0 %; ! JOINING NODE'S LAST CLUSTER GENERATION NUMBER macro CLUB$W_STG_JOIN_FLAGS = 244,0,16,0 %; ! STAGING AREA FOR JOIN FLAGS macro CLUB$W_JOIN_FLAGS = 246,0,16,0 %; ! JOINING NODE'S FLAGS macro CLUB$V_CLUGEN_VALID = 246,0,1,0 %; ! GENERATION DATA FIELDS VALID macro CLUB$L_RM_QUOTA = 248,0,32,0 %; ! REMASTERING QUOTA macro CLUB$Q_CSPQ = 256,0,0,0 %; literal CLUB$S_CSPQ = 8; ! QUEUE FOR COMMUNICATION WITH CSP macro CLUB$B_FORK_BLOCK = 264,0,0,1 %; literal CLUB$S_FORK_BLOCK = 56; ! FORK BLOCK TO WAIT IN (CLUBFKB SUB-STRUCTURE) macro CLUB$B_NODEMAP = 320,0,0,1 %; literal CLUB$S_NODEMAP = 32; ! BITMAP OF ALL POSSIBLE NODES macro CLUB$B_CLUFCB = 352,0,0,1 %; literal CLUB$S_CLUFCB = 136; ! CLUSTER FAILOVER CONTROL BLOCK macro CLUB$R_PGC_FKB = 488,0,0,0 %; literal CLUB$S_PGC_FKB = 48; ! Fork Block for Cluster Page Cache Trimming/Recovery macro CLUB$B_CLUBPWF = 536,0,0,1 %; literal CLUB$S_CLUBPWF = 56; ! FORK BLOCK TO USE DURING POWER RECOVERY ! New cells located at end to minimize rebuiding. Should be moved someday. macro CLUB$L_RESLOCKTMO = 592,0,32,0 %; ! RESERVATION EXPIRATION TIME macro CLUB$L_RESLOCKCSID = 596,0,32,0 %; ! CSID OF RESERVATION HOLDER macro CLUB$L_LOCKTIME = 600,0,32,0 %; ! TIME LOCKED macro CLUB$W_MERGE_CNT = 604,0,16,0 %; ! MERGE COUNTER macro CLUB$W_PARSEQNUM = 606,0,16,0 %; ! PARTIAL REBUILD SEQUENCE NUMBER macro CLUB$B_NEWRBLD_REQ = 608,0,8,0 %; ! PROPOSED REBUILD REQUEST macro CLUB$B_RBLD_CLU = 609,0,8,0 %; ! REBUILD IN PROGRESS IN CLUSTER macro CLUB$B_RBLD_LOC = 610,0,8,0 %; ! REBUILD IN PROGRESS ON LOCAL NODE macro CLUB$L_CLURCBFL = 612,0,32,1 %; ! ACTIVE RCBs macro CLUB$L_CLURCBBL = 616,0,32,1 %; ! macro CLUB$W_RBLD_INHIB = 620,0,16,0 %; ! REASONS TO INHIBIT A LOCK REBUILD macro CLUB$W_NCNID = 624,0,16,0 %; ! NEXT CLUSTER NODE ID macro CLUB$W_NEWNCNID = 626,0,16,0 %; ! NEW NEXT CLUSTER NODE ID macro CLUB$L_TOFF = 628,0,32,0 %; ! LOCKING OFF macro CLUB$L_TON = 632,0,32,0 %; ! LOCKING ON macro CLUB$L_TBLS = 636,0,32,1 %; ! TABLE START macro CLUB$L_QTQE = 640,0,32,1 %; ! POINTER TO QUORUM LOSS TQE macro CLUB$L_SYNC_STEP = 644,0,32,0 %; ! SYNC STEP COUNT (move to clurcb) macro CLUB$Q_TDF = 648,0,0,0 %; literal CLUB$S_TDF = 8; ! DTS TDF macro CLUB$Q_BLOCK_SEQ = 656,0,0,0 %; literal CLUB$S_BLOCK_SEQ = 8; ! Fast Re-master Block ! Transfer Sequence # macro CLUB$B_LCKMGR_FORK_BLOCK = 664,0,0,1 %; literal CLUB$S_LCKMGR_FORK_BLOCK = 56; ! Fork block to fork down to LCKMGR macro CLUB$L_RMBUF_LINK = 720,0,32,0 %; ! Pointer to first free Remaster buffer macro CLUB$L_MAX_RMBUFS = 724,0,32,0 %; ! Maximum concurrent remaster xfers macro CLUB$L_CACHED_RMBUFS = 728,0,32,0 %; ! Number of cached rm xfer buffers macro CLUB$L_TOT_RMBUFS = 732,0,32,0 %; ! Total rm xfer buffers (cached + active) macro CLUB$L_CUR_CACHED = 740,0,32,0 %; ! # cached entries across all sizes macro CLUB$L_CUR_IN_USE = 744,0,32,0 %; ! # active buffers across all sizes macro CLUB$L_MAX_IN_USE = 748,0,32,0 %; ! Max # active buffers across all sizes macro CLUB$L_MAX_CACHED = 752,0,32,0 %; ! Max # cached entries across all sizes macro CLUB$L_LAST_ALLOC = 760,0,32,0 %; ! ABSTIM of last allocation (any size) macro CLUB$L_LAST_DEALLOC = 764,0,32,0 %; ! ABSTIM of last deallocation (any size) macro CLUB$R_PGCLIST = 736,0,0,0 %; literal CLUB$S_PGCLIST = 320; ! Cluster Page Cache List Array, Totals + [1..9] !*** MODULE $CLUSDADEF *** ! + ! $CLUSDADEF - define an incoming connect block. This block handles ! all of the activity for one connection. Since only one command ! can be active at any time, a permanent CDRP is allocated with ! this block. ! - literal CLUSDA$C_BUGCHK = 1; ! Cluster bugcheck protocol literal CLUSDA$C_PRTLEV = 2; ! 32-bit Remote SDA Protocol level literal CLUSDA$C_PRTLEV_64 = 3; ! 64-bit Remote SDA Protocol level literal CLUSDA$C_IDLE = 0; ! Idle literal CLUSDA$C_ACTIVE = 1; ! CDRP is in use literal CLUSDA$C_LENGTH = 24; ! LENGTH OF FIXED PART literal CLUSDA$K_LENGTH = 24; ! LENGTH OF FIXED PART literal CLUSDA$S_CLUSDA = 32; ! macro CLUSDA$L_FLINK = 0,0,32,1 %; ! Queue forward link macro CLUSDA$L_BLINK = 4,0,32,1 %; ! Queue backward link macro CLUSDA$W_SIZE = 8,0,16,0 %; ! Structure size macro CLUSDA$W_TYPE = 10,0,16,0 %; ! Structure type macro CLUSDA$L_CDT = 12,0,32,1 %; ! CDT address macro CLUSDA$L_PDT = 16,0,32,1 %; ! PDT address macro CLUSDA$W_STATE = 20,0,16,0 %; ! Connect state ! State values macro CLUSDA$B_CDRP = 24,0,8,1 %; literal CLUSDA$S_CDRP = 1; ! Start of permanent CDRP literal CLUSDA$S_CLUSDADEF = 32; ! ! Data structure built in NPP by CLUSTER_CRASH ! literal SCSSDA$K_LENGTH = 144; ! Length of the structure literal SCSSDA$S_SCSSDA = 144; macro SCSSDA$L_REF_COUNT = 0,0,32,0 %; ! Reference count for this block macro SCSSDA$L_CLUSTER_FLAG = 4,0,32,0 %; ! =1 if crashing all nodes macro SCSSDA$W_SIZE = 8,0,16,0 %; ! Structure size macro SCSSDA$B_TYPE = 10,0,8,0 %; ! Structure type macro SCSSDA$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro SCSSDA$L_ATTEMPTS = 12,0,32,0 %; ! Number of nodes we've attempted to crash macro SCSSDA$T_TARGET_NODE = 16,0,0,0 %; literal SCSSDA$S_TARGET_NODE = 8; ! Name of target node macro SCSSDA$T_MESSAGE_1 = 24,0,0,0 %; literal SCSSDA$S_MESSAGE_1 = 16; ! First part of coroner message macro SCSSDA$W_CONNECT = 40,0,16,0 %; ! The connect code macro SCSSDA$T_MESSAGE_2 = 42,0,0,0 %; literal SCSSDA$S_MESSAGE_2 = 14; ! Second part of coroner message macro SCSSDA$Q_SYSTEM_ID = 56,0,0,0 %; literal SCSSDA$S_SYSTEM_ID = 8; ! The target system's ID (from the SB) macro SCSSDA$T_SYSTEM_DATA = 64,0,0,0 %; literal SCSSDA$S_SYSTEM_DATA = 80; ! The SBO data returned by SCS$CONFIG_SYS !*** MODULE $CSBDEF *** ! + ! CSB - Cluster System Block ! ! There is one CSB for each system in the cluster. ! It is used by the connection manager to synchronize ! cluster communications and configuration. Access ! to the CSB is synchronized with the SCS spinlock. ! - literal CSB$M_CAP_VCC = %X'2'; literal CSB$M_CAP_EXT_STATUS = %X'8'; literal CSB$M_CAP_CWCREPRC = %X'10'; literal CSB$M_CAP_THREADS = %X'20'; literal CSB$M_CAP_CWLOGICALS = %X'40'; literal CSB$M_CAP_IPC_DEMULT_CONN = %X'80'; literal CSB$M_CAP_RMBXFR = %X'100'; literal CSB$M_CAP_WBM_SHADOW = %X'200'; literal CSB$M_CAP_WBM_ALL = %X'400'; literal CSB$M_CAP_SCHED_CLASS = %X'800'; literal CSB$M_CAP_WBM_AMCVP = %X'1000'; literal CSB$M_CAP_WBM_TYPE = %X'2000'; literal CSB$M_LONG_BREAK = %X'1'; literal CSB$M_MEMBER = %X'2'; literal CSB$M_REMOVED = %X'4'; literal CSB$M_QF_SAME = %X'8'; literal CSB$M_QF_WATCHER = %X'10'; literal CSB$M_QF_NOACCESS = %X'20'; literal CSB$M_CLUSTER = %X'100'; literal CSB$M_QF_ACTIVE = %X'200'; literal CSB$M_SHUTDOWN = %X'400'; literal CSB$M_GONE = %X'800'; literal CSB$M_RESYNCH_FKB_BSY = %X'1000'; literal CSB$M_RESEND_FKB_BSY = %X'2000'; literal CSB$M_RCVMSG_FRK_IP = %X'4000'; literal CSB$M_RCVMSG_FKB_BSY = %X'8000'; literal CSB$M_LOCKED = %X'10000'; literal CSB$M_SELECTED = %X'20000'; literal CSB$M_RESERVED1 = %X'40000'; literal CSB$M_SEND_EXT_STATUS = %X'80000'; literal CSB$M_FORCED_STALL = %X'100000'; literal CSB$M_LOCAL = %X'1000000'; literal CSB$M_STATUS_RCVD = %X'2000000'; literal CSB$M_SEND_STATUS = %X'4000000'; literal CSB$M_QF_RFRSH_RQD = %X'8000000'; literal CSB$M_QF_RFRSH_IP = %X'10000000'; literal CSB$M_QF_IOSYNCH = %X'20000000'; literal CSB$M_ACT_LSHARE = %X'40000000'; literal CSB$M_PASS_LSHARE = %X'80000000'; literal CSB$K_OPEN = 1; ! Open (normal) literal CSB$K_STATUS = 2; ! Sending/waiting for status literal CSB$K_RECONNECT = 3; ! Attempting to reconnect literal CSB$K_NEW = 4; ! Brand new block literal CSB$K_CONNECT = 5; ! Attempting initial connection literal CSB$K_ACCEPT = 6; ! Accepting initial connection literal CSB$K_DISCONNECT = 7; ! Disconnect in progress literal CSB$K_REACCEPT = 8; ! Accepting reconnect request literal CSB$K_WAIT = 9; ! Time-out in progress literal CSB$K_DEAD = 10; ! No connection possible literal CSB$K_LOCAL = 11; ! Local system CSB literal CSB$C_LENGTH = 520; ! Length of fixed portion of CSB literal CSB$K_LENGTH = 520; ! Length of fixed portion of CSB literal CSB$S_CSBDEF = 520; ! Old size name - synonym for fixed portion of CSB literal CSB$S_CSB = 520; macro CSB$L_SYSQFL = 0,0,32,1 %; ! System Queue Forward Link macro CSB$L_SYSQBL = 4,0,32,1 %; ! System Queue Backward Link macro CSB$W_SIZE = 8,0,16,0 %; ! Size of CSB in bytes macro CSB$B_TYPE = 10,0,8,0 %; ! Structure Type (DYN$C_CLU) macro CSB$B_SUBTYPE = 11,0,8,0 %; ! Structure Subtype (DYN$C_CLU_CSB) macro CSB$BIL_CLUVER = 12,0,32,0 %; macro CSB$B_CLUVER = 12,0,8,0 %; ! Cluster version number macro CSB$WIL_PROTOCOL = 16,0,32,0 %; macro CSB$B_ECOLVL = 16,0,8,0 %; ! Protocol ECO level macro CSB$B_VERNUM = 17,0,8,0 %; ! Protocol Version number macro CSB$L_CACHE_PROTOCOL_VER = 20,0,32,0 %; ! Cache protocol version macro CSB$W_LCKDIRWT = 24,0,16,0 %; ! Lock Manager distributed directory weight macro CSB$W_LCKRMWT = 26,0,16,0 %; ! Lock Manager remaster weight macro CSB$WIL_VOTES = 28,0,32,0 %; macro CSB$W_VOTES = 28,0,16,0 %; ! Votes held by node macro CSB$WIL_EVOTES = 32,0,32,0 %; macro CSB$W_EVOTES = 32,0,16,0 %; ! Remote node's Expected Votes macro CSB$WIL_QDVOTES = 36,0,32,0 %; macro CSB$W_QDVOTES = 36,0,16,0 %; ! Votes assigned to quorum disk macro CSB$WIL_QUORUM = 40,0,32,0 %; macro CSB$W_QUORUM = 40,0,16,0 %; ! Quorum set in node macro CSB$WIL_NODES = 44,0,32,0 %; macro CSB$W_NODES = 44,0,16,0 %; ! Number of nodes in remote cluster macro CSB$B_CNCT = 48,0,0,1 %; literal CSB$S_CNCT = 16; ! SCS CONNECT/ACCEPT Data Area macro CSB$B_NODEMAP = 64,0,0,1 %; literal CSB$S_NODEMAP = 32; ! Bitmap of node connectivity macro CSB$B_HWNAME = 96,0,0,1 %; literal CSB$S_HWNAME = 61; ! Hardware Model Name macro CSB$B_HWNAME_PAD = 157,0,24,1 %; literal CSB$S_HWNAME_PAD = 3; ! Explicitly pad to next quadword macro CSB$T_SW_VERSION = 160,0,0,0 %; literal CSB$S_SW_VERSION = 8; ! VMS Software Version macro CSB$Q_SWINCARN = 168,0,0,0 %; literal CSB$S_SWINCARN = 8; ! Remote Software Incarnation Number macro CSB$Q_REFTIME = 176,0,0,0 %; literal CSB$S_REFTIME = 8; ! Creation/Addition/Removal time macro CSB$Q_LNM_SEQNUM = 184,0,0,0 %; literal CSB$S_LNM_SEQNUM = 8; ! Clusterwide Logicals Sequence Number macro CSB$Q_LCKRM_BXFRSEQ = 192,0,0,0 %; literal CSB$S_LCKRM_BXFRSEQ = 8; ! LCKMGR Remaster Block XFER Sequence Number macro CSB$WIL_CNX_STS_R0 = 200,0,32,0 %; macro CSB$W_CNX_STS_R0 = 200,0,16,0 %; ! Connection request R0 status macro CSB$WIL_CNX_STS_R1 = 204,0,32,0 %; macro CSB$W_CNX_STS_R1 = 204,0,16,0 %; ! Connection request R1 status macro CSB$R_RESYNCH_FKB = 208,0,0,0 %; literal CSB$S_RESYNCH_FKB = 48; ! Message Build Resynch Fork Block macro CSB$R_RESEND_MSGS_FKB = 256,0,0,0 %; literal CSB$S_RESEND_MSGS_FKB = 48; ! Resend Messages Fork Block macro CSB$R_SCS2LCKMGR_FKB = 304,0,0,0 %; literal CSB$S_SCS2LCKMGR_FKB = 48; ! Received Messages Fork Block macro CSB$L_CDT = 352,0,32,1 %; ! Address of CDT macro CSB$L_PDT = 356,0,32,1 %; ! Address of PDT macro CSB$L_CLUB = 360,0,32,1 %; ! Address of CLUB macro CSB$L_SB = 364,0,32,1 %; ! Address of System Block for remote system macro CSB$L_TQE = 368,0,32,1 %; ! Address of Timer Queue Entry macro CSB$L_TIMEOUT = 372,0,32,0 %; ! Time to give up reCONNECTing macro CSB$L_RMAX_VCTMO = 376,0,32,0 %; ! Maximum Remote Virtual Circuit Timeout Interval macro CSB$L_ABSTIM_OFFSET = 380,0,32,1 %; ! Offset to obtain remote node's ABSTIM macro CSB$L_CSID = 384,0,32,0 %; ! Cluster System ID: macro CSB$W_CSID_IDX = 384,0,16,0 %; ! Slot index macro CSB$W_CSID_SEQ = 386,0,16,0 %; ! Sequence number macro CSB$WIL_CNID = 388,0,32,0 %; macro CSB$W_CNID = 388,0,16,0 %; ! Cluster Node ID macro CSB$L_PARTNERQFL = 392,0,32,1 %; ! Block XFER PARTNER BTX Queue Forward Link macro CSB$L_PARTNERQBL = 396,0,32,1 %; ! Block XFER PARTNER BTX Queue Backward Link macro CSB$L_WARMCDRPQFL = 400,0,32,1 %; ! Warm CDRP Queue Forward Link macro CSB$L_WARMCDRPQBL = 404,0,32,1 %; ! Warm CDRP Queue Backward Link macro CSB$Q_RM_CTXQ = 408,0,0,0 %; literal CSB$S_RM_CTXQ = 8; ! Remaster Context Block Queue: macro CSB$L_RM_CTXQFL = 408,0,32,0 %; ! CTXQ Forward Link macro CSB$L_RM_CTXQBL = 412,0,32,0 %; ! CTXQ Backward Link macro CSB$L_SENTQFL = 416,0,32,1 %; ! SENT Messages List Forward Link (Head) macro CSB$L_SENTQBL = 420,0,32,1 %; ! SENT Messages List Backward Link (Tail) macro CSB$L_RESENDQFL = 424,0,32,1 %; ! RESEND Messages List Forward Link (Head) macro CSB$L_RESENDQBL = 428,0,32,1 %; ! RESEND Messages List Backward Link (Tail) macro CSB$L_CAPABILITY = 432,0,32,0 %; ! Node capabilities macro CSB$V_CAP_VCC = 432,1,1,0 %; ! VCC Enabled macro CSB$V_CAP_EXT_STATUS = 432,3,1,0 %; ! Extended status message macro CSB$V_CAP_CWCREPRC = 432,4,1,0 %; ! Clusterwide $CREPRC support macro CSB$V_CAP_THREADS = 432,5,1,0 %; ! Kernel threads support macro CSB$V_CAP_CWLOGICALS = 432,6,1,0 %; ! Clusterwide Logicals support macro CSB$V_CAP_IPC_DEMULT_CONN = 432,7,1,0 %; ! IPC supports de-multiplexed connections macro CSB$V_CAP_RMBXFR = 432,8,1,0 %; ! Can send/receive block remasters macro CSB$V_CAP_WBM_SHADOW = 432,9,1,0 %; ! Supports Write BitMap for shadow member copy operations macro CSB$V_CAP_WBM_ALL = 432,10,1,0 %; ! Supports Write BitMap for all disks macro CSB$V_CAP_SCHED_CLASS = 432,11,1,0 %; ! Supports class scheduling via class scheduler database file macro CSB$V_CAP_WBM_AMCVP = 432,12,1,0 %; ! Supports AMCVP enhancements macro CSB$V_CAP_WBM_TYPE = 432,13,1,0 %; ! Supports WBM bitmap TYPE enhancements macro CSB$L_STATUS = 436,0,32,0 %; ! Status of node in cluster macro CSB$V_LONG_BREAK = 436,0,1,0 %; ! Long break in connection macro CSB$V_MEMBER = 436,1,1,0 %; ! Node is member of local cluster macro CSB$V_REMOVED = 436,2,1,0 %; ! Node removed from cluster macro CSB$V_QF_SAME = 436,3,1,0 %; ! Remote quorum disk matches local disk macro CSB$V_QF_WATCHER = 436,4,1,0 %; ! Remote node is watching a quorum file macro CSB$V_QF_NOACCESS = 436,5,1,0 %; ! Node will never access quorum disk macro CSB$V_CLUSTER = 436,8,1,0 %; ! Remote node is cluster member macro CSB$V_QF_ACTIVE = 436,9,1,0 %; ! Remote node's quorum file is readable macro CSB$V_SHUTDOWN = 436,10,1,0 %; ! Remote node ready for cluster shutdown macro CSB$V_GONE = 436,11,1,0 %; ! Known to have shutdown macro CSB$V_RESYNCH_FKB_BSY = 436,12,1,0 %; ! MSGBLD Resynch Fork Block busy macro CSB$V_RESEND_FKB_BSY = 436,13,1,0 %; ! Resend_Msgs Fork Block busy macro CSB$V_RCVMSG_FRK_IP = 436,14,1,0 %; ! SCS2LCKMGR fork thread is active macro CSB$V_RCVMSG_FKB_BSY = 436,15,1,0 %; ! SCS2LCKMGR fork block is queued, thread may or may not be active macro CSB$V_LOCKED = 436,16,1,0 %; ! Node locked by coordinator macro CSB$V_SELECTED = 436,17,1,0 %; ! Node selected by coordinator macro CSB$V_RESERVED1 = 436,18,1,0 %; ! Bit was used for a VAX release macro CSB$V_SEND_EXT_STATUS = 436,19,1,0 %; ! Need to send extended status macro CSB$V_FORCED_STALL = 436,20,1,0 %; ! Waiting for remote acks to avoid remote overload macro CSB$V_LOCAL = 436,24,1,0 %; ! This CSB is the local system macro CSB$V_STATUS_RCVD = 436,25,1,0 %; ! Status received from remote system macro CSB$V_SEND_STATUS = 436,26,1,0 %; ! Need to send status to remote system macro CSB$V_QF_RFRSH_RQD = 436,27,1,0 %; ! Need Quorum File refresh macro CSB$V_QF_RFRSH_IP = 436,28,1,0 %; ! Quorum File refresh in progress macro CSB$V_QF_IOSYNCH = 436,29,1,0 %; ! Quorum File I/O synch done macro CSB$V_ACT_LSHARE = 436,30,1,0 %; ! Active side to load sharing macro CSB$V_PASS_LSHARE = 436,31,1,0 %; ! Passive side to load sharing macro CSB$L_STATE = 440,0,32,0 %; ! State of connection macro CSB$L_CURRCDRP = 444,0,32,1 %; ! Address of CDRP in critical section macro CSB$L_REFCNT = 448,0,32,0 %; ! Reference count macro CSB$L_UNACKEDMSGS = 452,0,32,0 %; ! Number of unacked messages macro CSB$L_REMACKLIM = 456,0,32,0 %; ! Remote side's ACK Limit macro CSB$L_WARMCDRPS = 460,0,32,0 %; ! Number of CDRPs on free queue macro CSB$WIL_SENDSEQNM = 464,0,32,0 %; macro CSB$W_SENDSEQNM = 464,0,16,0 %; ! Next sequence number to send macro CSB$WIL_RCVDSEQNM = 468,0,32,0 %; macro CSB$W_RCVDSEQNM = 468,0,16,0 %; ! Last Sequence Number received macro CSB$WIL_ACKRSEQNM = 472,0,32,0 %; macro CSB$W_ACKRSEQNM = 472,0,16,0 %; ! Last ACK'd received Sequence Number macro CSB$WIL_LASTSENT = 476,0,32,0 %; macro CSB$W_LASTSENT = 476,0,16,0 %; ! Sequence Number of message last sent macro CSB$WIL_PASS_CNTR = 480,0,32,0 %; macro CSB$W_PASS_CNTR = 480,0,16,0 %; ! Total passive loadshare operations macro CSB$WIL_ACT_CNTR = 484,0,32,0 %; macro CSB$W_ACT_CNTR = 484,0,16,0 %; ! Total active loadshare operations macro CSB$WIL_ERR_CNTR = 488,0,32,0 %; macro CSB$W_ERR_CNTR = 488,0,16,0 %; ! Total errors on connection macro CSB$L_SCS2LCKMGR_MAXIDX = 492,0,32,0 %; ! Max index for SCS2LCKMGR_MSGARRAY macro CSB$L_MAXMSGSIZ = 496,0,32,0 %; ! Max message size allowed to send to this node macro CSB$L_SPARE_LW1 = 500,0,32,0 %; macro CSB$Q_SPARE_QW2 = 504,0,0,0 %; literal CSB$S_SPARE_QW2 = 8; macro CSB$L_SCS2LCKMGR_MSGCNT = 512,0,32,0 %; ! Number of received msgbufs waiting for LCKMGR spinlock (at element 0 of array) macro CSB$L_SCS2LCKMGR_MSGARRAY = 512,0,32,1 %; ! Array of msgbuf addresses waiting for LCKMGR spinlock (starting at element 1) ! N.B. -- Do not add any symbols beyond the lckmgr_fork_overlay -- it must be the last ! entry in the CSB as the SCS2LCKMGR_MSGARRAY is dynamically sized based on the ! CLUSTER_CREDITS SYSGEN parameter. !*** MODULE $RMMGTDEF *** ! ! RMDriver status constants ! literal RMSTS$K_RESERVED = 0; ! 0 - Reserved literal RMSTS$K_INITIAL = 1; ! 1 - Initial driver state literal RMSTS$K_DRIVER_INITED = 2; ! 2 - Driver has been inited, but not started literal RMSTS$K_DRIVER_STARTED = 3; ! 3 - Driver has been started literal RMSTS$K_DRIVER_STOPPED = 4; ! 4 - Driver has been stopped ! ! Managed Object parameter structure for requests requiring the RMDRIVER ! security data. ! literal RMSECDAT$K_V1_1_SECDAT_LEN = 8; ! Reg out data length literal RMSECDAT$C_V1_1_SECDAT_LEN = 8; ! Old VAX style length literal RMSECDAT$S_RMSECDAT = 8; macro RMSECDAT$Q_RM_SEC_TOKEN = 0,0,0,0 %; literal RMSECDAT$S_RM_SEC_TOKEN = 8; ! Security token for accessing RMDriver functions ! ! Managed Object registration data from GET_REGISTRATION request ! ! This structure represents data for Managed Object Parameter version 1.1 ! literal MORGR$K_OBJ_REG_STS_RESERVED = 0; ! 0 - Reserved (for debugging) literal MORGR$K_OBJ_REG_STS_REGISTERED = 1; ! 1 - MO is registered literal MORGR$K_OBJ_REG_STS_DREGISTERED = 2; ! 2 - MO is deregistered literal MORGR$K_OBJ_REG_STS_UNUSED = 3; ! Add new constants before here literal MORGR$K_OBJ_RUN_STS_RESERVED = 0; ! 0 - Reserved (for debugging) literal MORGR$K_OBJ_RUN_STS_REQ_ON = 1; ! 1 - MO is processing requests literal MORGR$K_OBJ_RUN_STS_REQ_OFF = 2; ! 2 - MO is not processing requests literal MORGR$K_OBJ_RUN_STS_UNUSED = 3; ! Add new constants before here literal MORGR$K_OBJ_REG_LENGTH = 48; ! MO registration data length literal MORGR$C_OBJ_REG_LENGTH = 48; ! Old VAX style length literal MORGR$S_MORGR = 48; macro MORGR$T_OBJ_NAME = 0,0,0,0 %; literal MORGR$S_OBJ_NAME = 32; ! Managed Object name macro MORGR$L_OBJ_HANDLE = 32,0,32,0 %; ! Managed Object handle macro MORGR$W_OBJ_TYPE = 36,0,16,0 %; ! Managed Object type (e.g. user, kernel) macro MORGR$B_OBJ_REG_STATUS = 38,0,8,0 %; ! Registration status macro MORGR$B_OBJ_RUN_STATUS = 39,0,8,0 %; ! Run status macro MORGR$B_OBJ_MINOR = 40,0,8,0 %; ! Managed Object minor version macro MORGR$B_OBJ_MAJOR = 41,0,8,0 %; ! Managed Object major version ! ! Managed Object registration data from GET_MO_STATISTICS request ! ! This structure represents data for Managed Object Parameter version 1.1 ! literal MORGS$K_REG_DATA_LENGTH = 40; ! MO registration data length literal MORGS$C_REG_DATA_LENGTH = 40; ! Old VAX style length literal MORGS$S_MORGS = 40; macro MORGS$L_OBJ_HANDLE = 0,0,32,0 %; ! Managed Object handle macro MORGS$L_REQUESTS = 4,0,32,0 %; ! Number of requests processed macro MORGS$L_ERRORS = 8,0,32,0 %; ! Number of errors in processing requests macro MORGS$L_RESETS = 12,0,32,0 %; ! Number of resets to zero done for these statistics macro MORGS$Q_REG_TIME = 16,0,0,0 %; literal MORGS$S_REG_TIME = 8; ! Time when Managed Object registered macro MORGS$Q_REQUEST_BYTES = 24,0,0,0 %; literal MORGS$S_REQUEST_BYTES = 8; ! Total number of bytes in request packets macro MORGS$Q_RESPONSE_BYTES = 32,0,0,0 %; literal MORGS$S_RESPONSE_BYTES = 8; ! Total number of bytes in response packets ! ! RMDRIVER configuration data from GET_RM_CONFIGURATION request ! ! This structure represents data for Managed Object Parameter version 2.1 ! literal RMCFGS$K_NUM_LAN_DEVICES = 4; ! Number of LAN devices literal RMCFGS$S_RMCFGS_DEV_NAME = 4; macro RMCFGS$T_DEV_NAME_STR = 0,0,32,0 %; literal RMCFGS$S_DEV_NAME_STR = 4; ! Keep length of info and info length to quadword multiple ! Keep length of info and info length to quadword multiple literal RMCFGS$K_RM_CONFIG_DATA_LENGTH = 848; ! RM configuration data length literal RMCFGS$C_RM_CONFIG_DATA_LENGTH = 848; ! Old VAX style length literal RMCFGS$S_RMCFGS = 848; macro RMCFGS$B_OBJ_MINOR = 0,0,8,0 %; ! RMDriver Managed Object minor version macro RMCFGS$B_OBJ_MAJOR = 1,0,8,0 %; ! RMDriver Managed Object major version macro RMCFGS$W_RSVD = 2,0,16,0 %; ! Reserved macro RMCFGS$W_MAX_REG_ENTRIES = 4,0,16,0 %; ! Maximum number of registration entries macro RMCFGS$W_NUM_REG_ENTRIES = 6,0,16,0 %; ! Current number of registration entries macro RMCFGS$R_DEV_NAME = 8,0,0,0 %; literal RMCFGS$S_DEV_NAME = 16; macro RMCFGS$AL_DLL_HDR_SIZE = 24,0,0,1 %; literal RMCFGS$S_DLL_HDR_SIZE = 16; ! DLL header size macro RMCFGS$AL_MAX_NETW_BUF_SIZE = 40,0,0,1 %; literal RMCFGS$S_MAX_NETW_BUF_SIZE = 16; ! Maximum network buffer size macro RMCFGS$AL_DEFAULT_NETW_BUF_SIZE = 56,0,0,1 %; literal RMCFGS$S_DEFAULT_NETW_BUF_SIZE = 16; ! Default network buffer size macro RMCFGS$L_MC_MIN_DEF_SEC = 72,0,32,0 %; ! Minimum default Hello interval macro RMCFGS$L_MC_MAX_DEF_SEC = 76,0,32,0 %; ! Maximum default Hello interval macro RMCFGS$L_MC_DEF_DEF_SEC = 80,0,32,0 %; ! Default default Hello interval macro RMCFGS$L_MC_CUR_DEF_SEC = 84,0,32,0 %; ! Current default Hello interval macro RMCFGS$L_MC_MIN_SCND_SEC = 88,0,32,0 %; ! Minimum secondary Hello interval macro RMCFGS$L_MC_MAX_SCND_SEC = 92,0,32,0 %; ! Maximum secondary Hello interval macro RMCFGS$L_MC_DEF_SCND_SEC = 96,0,32,0 %; ! Default secondary Hello interval macro RMCFGS$L_MC_CUR_SCND_SEC = 100,0,32,0 %; ! Current secondary Hello interval macro RMCFGS$L_MC_SEC = 104,0,32,0 %; ! Current Hello interval macro RMCFGS$L_MC_SIZE = 108,0,32,0 %; ! Size of Hello packet macro RMCFGS$L_MIN_VCRP_BUFFERS = 112,0,32,0 %; ! Minimum VCRP buffers macro RMCFGS$L_MAX_VCRP_BUFFERS = 116,0,32,0 %; ! Maximum VCRP buffers macro RMCFGS$L_DEF_VCRP_BUFFERS = 120,0,32,0 %; ! Default VCRP buffers macro RMCFGS$L_CUR_VCRP_BUFFERS = 124,0,32,0 %; ! Current VCRP buffers macro RMCFGS$L_MIN_MAX_BRANCHES = 128,0,32,0 %; ! Minimum max branches allowed macro RMCFGS$L_MAX_MAX_BRANCHES = 132,0,32,0 %; ! Maximum max branches allowed macro RMCFGS$L_DEF_MAX_BRANCHES = 136,0,32,0 %; ! Default max branches allowed macro RMCFGS$L_CUR_MAX_BRANCHES = 140,0,32,0 %; ! Current max branches allowed macro RMCFGS$T_GROUPNAME = 144,0,0,0 %; literal RMCFGS$S_GROUPNAME = 16; ! AMDS Group name macro RMCFGS$T_CLUNAME = 160,0,0,0 %; literal RMCFGS$S_CLUNAME = 16; ! AMDS Cluster name macro RMCFGS$T_GALAXYNAME = 176,0,0,0 %; literal RMCFGS$S_GALAXYNAME = 16; ! AMDS Galaxy name macro RMCFGS$W_SITE_INFO_LEN = 192,0,16,0 %; ! Length of site-specific information macro RMCFGS$T_SITE_INFO = 194,0,0,0 %; literal RMCFGS$S_SITE_INFO = 518; ! Site-specific information macro RMCFGS$W_NODE_INFO_LEN = 712,0,16,0 %; ! Length of node-specific information macro RMCFGS$T_NODE_INFO = 714,0,0,0 %; literal RMCFGS$S_NODE_INFO = 134; ! Node-specific information ! ! RMDRIVER configuration data from GET_RM_STATISTICS request ! ! This structure represents data for Managed Object Parameter version 1.2 ! literal RMSTTS$K_RM_STAT_DATA_LENGTH = 536; ! RM statistics data length literal RMSTTS$C_RM_STAT_DATA_LENGTH = 536; ! Old VAX style length literal RMSTTS$S_RMSTTS = 536; macro RMSTTS$L_RM_SUCCESS_STARTUPS = 0,0,32,0 %; ! The number of times that RMDriver has been started successfully macro RMSTTS$L_RM_UNSUCCESS_STARTUPS = 4,0,32,0 %; ! The number of times that RMDriver has been started unsuccessfully macro RMSTTS$L_RM_SUCCESS_SHUTDOWNS = 8,0,32,0 %; ! The number of times that RMDriver has been stopped successfully macro RMSTTS$L_RM_UNSUCCESS_SHUTDOWNS = 12,0,32,0 %; ! The number of times that RMDriver has been stopped unsuccessfully macro RMSTTS$L_RM_STARTUP_STATUS = 16,0,32,0 %; ! The last RMDriver startup failure status macro RMSTTS$L_RM_SHUTDOWN_STATUS = 20,0,32,0 %; ! The last RMDriver shutdown failure status macro RMSTTS$L_DRIVER_INITS = 24,0,32,0 %; ! The number of times that RMDriver's control init routine was called macro RMSTTS$L_DRIVER_OPCNT = 28,0,32,0 %; ! RMA0 operation count (UCB$L_OPCNT(UCB), updated when a HELLO is sent) macro RMSTTS$L_RSVD0 = 32,0,32,0 %; ! Reserved for quadword alignment macro RMSTTS$L_STAT_RESETS = 36,0,32,0 %; ! Number of resets to zero on these statistics macro RMSTTS$Q_STAT_RESET_TIME = 40,0,0,0 %; literal RMSTTS$S_STAT_RESET_TIME = 8; ! Time that the stats were reset macro RMSTTS$Q_SYS_BOOT_TIME = 48,0,0,0 %; literal RMSTTS$S_SYS_BOOT_TIME = 8; ! Time the system booted macro RMSTTS$L_XMIT_ERRS = 56,0,32,0 %; ! Number of transmit errors (truncated packet) macro RMSTTS$L_CHK_ERRS = 60,0,32,0 %; ! Checksum error count (UCB$L_RM_CHK_ERR(UCB)) (UCB from L_RM_UCB::) macro RMSTTS$L_UNKNOWN_PKT_TYPE = 64,0,32,0 %; ! Unknown AMDS packet type count macro RMSTTS$L_DROPPED_LOCAL_CLISTS1 = 68,0,32,0 %; ! Number of local CLIST packets dropped due to device not ready (started) macro RMSTTS$L_DROPPED_LOCAL_CLISTS2 = 72,0,32,0 %; ! Number of local CLIST packets dropped due to no pending READS from GUI macro RMSTTS$L_DROPPED_NETW_CRESPS = 76,0,32,0 %; ! Number of network CRESP packets dropped due to no pending READS from GUI or can macro RMSTTS$L_DROPPED_LOCAL_HELLOS = 80,0,32,0 %; ! Number of local HELLO packets dropped due to no pending READS from GUI or canc macro RMSTTS$L_DROPPED_REM_HELLOS = 84,0,32,0 %; ! Number of remote HELLO packets dropped due to no pending READS from GUI or cance ! Dropped packets are not counted in the packet type and bytes process stats macro RMSTTS$L_LAN_DLL_PORT_USABLE = 88,0,32,0 %; ! Account for various LAN events macro RMSTTS$L_LAN_DLL_PORT_UNUSABLE = 92,0,32,0 %; macro RMSTTS$L_LAN_LAN_NEW_ADDRESS = 96,0,32,0 %; macro RMSTTS$L_LAN_LAN_RCV_CONGESTION = 100,0,32,0 %; macro RMSTTS$L_LAN_LAN_RCV_PDU_LOST = 104,0,32,0 %; macro RMSTTS$L_LAN_SYN_STATN_DELETED = 108,0,32,0 %; ! SYN_STATION_DELETED macro RMSTTS$L_LAN_X25_INCOMING_RESET = 112,0,32,0 %; macro RMSTTS$L_LAN_X25_INCOMING_NOCOM = 116,0,32,0 %; macro RMSTTS$L_LAN_LAN_RESTART_FAIL = 120,0,32,0 %; macro RMSTTS$L_LAN_LAN_STATN_RENAMED = 124,0,32,0 %; ! LAN_STATION_RENAMED macro RMSTTS$L_LAN_LAN_RCVBUF_CHANGE = 128,0,32,0 %; macro RMSTTS$L_LAN_DLL_LAST = 132,0,32,0 %; macro RMSTTS$L_LAN_DLL_PREF_CPU_CHNGD = 136,0,32,0 %; ! DLL_PREF_CPU_CHANGED macro RMSTTS$L_LAN_DLL_UNKNOWN_VALUE = 140,0,32,0 %; ! Catch-all for values not defined above macro RMSTTS$L_RSVD1 = 144,0,32,0 %; ! Reserve two cells for later use macro RMSTTS$L_RSVD2 = 148,0,32,0 %; macro RMSTTS$Q_MIN_SCC = 152,0,0,0 %; literal RMSTTS$S_MIN_SCC = 8; ! Minimum number of cycles used in executing a data collector program macro RMSTTS$Q_MAX_SCC = 160,0,0,0 %; literal RMSTTS$S_MAX_SCC = 8; ! Maximum number of cycles used in executing a data collector program macro RMSTTS$Q_AVE_SCC = 168,0,0,0 %; literal RMSTTS$S_AVE_SCC = 8; ! A kind of moving average of the number of cycles used macro RMSTTS$Q_DIF_SCC = 176,0,0,0 %; literal RMSTTS$S_DIF_SCC = 8; ! Current number of cycles used macro RMSTTS$L_FETCHES_IN_QUEUE = 184,0,32,0 %; ! Number of fetches in the queue macro RMSTTS$L_FETCHES_QUEUED = 188,0,32,0 %; ! Number of fetches queued macro RMSTTS$L_FETCHES_EXECUTED = 192,0,32,0 %; ! Number of fetches successfully executed macro RMSTTS$L_FETCHES_INCOMPLETE = 196,0,32,0 %; ! Number of fetches for incompleted TRAPs macro RMSTTS$L_FETCH_TIMEOUTS = 200,0,32,0 %; ! Number of TRAP results that timed out before a FETCH was received for the results macro RMSTTS$L_FETCH_MISMATCHES = 204,0,32,0 %; ! Number of FETCHes received that didn't have a valid FETCH ID macro RMSTTS$L_HELLOS_SENT = 208,0,32,0 %; ! Number of Hello packets sent by local RMDriver macro RMSTTS$L_LOCAL_HELLOS_RECEIVED = 212,0,32,0 %; ! Number of Hello packets by local RMDriver to local GUI macro RMSTTS$L_REM_HELLOS_RECEIVED = 216,0,32,0 %; ! Number of Hello packets by remote RMDriver to local GUI macro RMSTTS$L_HELLO_PACKETS_IN = 220,0,32,0 %; ! Number of Hello packets received by local RMDriver to local GUI macro RMSTTS$Q_HELLO_BYTES_IN = 224,0,0,0 %; literal RMSTTS$S_HELLO_BYTES_IN = 8; ! Number of Hello bytes received by local RMDriver to local GUI macro RMSTTS$L_LOCAL_CLIST_PACKETS = 232,0,32,0 %; ! Number of CLIST packets processed for local GUI (local request) macro RMSTTS$L_NETW_CLIST_PACKETS = 236,0,32,0 %; ! Number of CLIST packets processed for local GUI (remote request) macro RMSTTS$L_REM_CLIST_PACKETS = 240,0,32,0 %; ! Number of CLIST packets processed for remote GUI macro RMSTTS$L_LOCAL_CRESP_PACKETS = 244,0,32,0 %; ! Number of CRESP packets processed for local GUI (local request) macro RMSTTS$L_NETW_CRESP_PACKETS = 248,0,32,0 %; ! Number of CRESP packets processed for local GUI (remote request) macro RMSTTS$L_REM_CRESP_PACKETS = 252,0,32,0 %; ! Number of CRESP packets processed for remote GUI macro RMSTTS$L_CONTROL_PACKETS = 256,0,32,0 %; ! Number of CONTROL packets processed macro RMSTTS$L_RM_EVENTS_SENT = 260,0,32,0 %; ! Number of event notifications sent by RMDriver macro RMSTTS$L_LOCAL_PACKETS_IN = 264,0,32,0 %; ! Number of local packets received by RMDriver for local GUI (including HELLOs rece macro RMSTTS$L_LOCAL_PACKETS_OUT = 268,0,32,0 %; ! Number of local packets transmitted by RMDriver for local GUI macro RMSTTS$Q_LOCAL_BYTES_IN = 272,0,0,0 %; literal RMSTTS$S_LOCAL_BYTES_IN = 8; ! Number of bytes received in local packets for local GUI macro RMSTTS$Q_LOCAL_BYTES_OUT = 280,0,0,0 %; literal RMSTTS$S_LOCAL_BYTES_OUT = 8; ! Number of bytes transmitted in local packets for local GUI macro RMSTTS$L_NETW_PACKETS_IN = 288,0,32,0 %; ! Number of network packets received by RMDriver for local GUI macro RMSTTS$L_NETW_PACKETS_OUT = 292,0,32,0 %; ! Number of network packets transmitted by RMDriver for local GUI macro RMSTTS$Q_NETW_BYTES_IN = 296,0,0,0 %; literal RMSTTS$S_NETW_BYTES_IN = 8; ! Number of bytes received in network packets for local GUI macro RMSTTS$Q_NETW_BYTES_OUT = 304,0,0,0 %; literal RMSTTS$S_NETW_BYTES_OUT = 8; ! Number of bytes transmitted in network packets for local GUI macro RMSTTS$L_REM_PACKETS_IN = 312,0,32,0 %; ! Number of network packets received by RMDriver for remote GUI macro RMSTTS$L_REM_PACKETS_OUT = 316,0,32,0 %; ! Number of network packets transmitted by RMDriver for remote GUI macro RMSTTS$Q_REM_BYTES_IN = 320,0,0,0 %; literal RMSTTS$S_REM_BYTES_IN = 8; ! Number of bytes received in network packets for remote GUI macro RMSTTS$Q_REM_BYTES_OUT = 328,0,0,0 %; literal RMSTTS$S_REM_BYTES_OUT = 8; ! Number of bytes transmitted in network packets for remote GUI macro RMSTTS$L_RM_REQUESTS = 336,0,32,0 %; ! Number of requests via RMDriver interface macro RMSTTS$L_RM_ARG_ERRORS = 340,0,32,0 %; ! Number of argument errors from requests via RMDriver interface macro RMSTTS$L_RM_ALIGN_ERRORS = 344,0,32,0 %; ! Number of alignment errors from requests via RMDriver interface macro RMSTTS$L_RM_FMT_ERRORS = 348,0,32,0 %; ! Number of format errors from requests via RMDriver interface macro RMSTTS$L_RM_PROC_ERRORS = 352,0,32,0 %; ! Number of processing errors from requests via RMDriver interface macro RMSTTS$L_RSVD3 = 356,0,32,0 %; ! Reserved (quadword alignment) macro RMSTTS$Q_RM_REQUEST_BYTES = 360,0,0,0 %; literal RMSTTS$S_RM_REQUEST_BYTES = 8; ! Number of bytes processed for requests via RMDriver interface macro RMSTTS$Q_RM_RESPONSE_BYTES = 368,0,0,0 %; literal RMSTTS$S_RM_RESPONSE_BYTES = 8; ! Number of bytes processed for responses via RMDriver interface macro RMSTTS$L_KMO_REQUESTS = 376,0,32,0 %; ! Number of requests via kernel-mode MO interface macro RMSTTS$L_KMO_ARG_ERRORS = 380,0,32,0 %; ! Number of argument errors from requests via kernel-mode MO interface macro RMSTTS$L_KMO_ALIGN_ERRORS = 384,0,32,0 %; ! Number of alignment errors from requests via kernel-mode MO interface macro RMSTTS$L_KMO_FMT_ERRORS = 388,0,32,0 %; ! Number of format errors from requests via kernel-mode MO interface macro RMSTTS$L_KMO_PROC_ERRORS = 392,0,32,0 %; ! Number of processing errors from requests via kernel-mode MO interface macro RMSTTS$L_RSVD4 = 396,0,32,0 %; ! Reserved (quadword alignment) macro RMSTTS$Q_KMO_REQUEST_BYTES = 400,0,0,0 %; literal RMSTTS$S_KMO_REQUEST_BYTES = 8; ! Number of bytes processed for requests via kernel-mode MO interface macro RMSTTS$Q_KMO_RESPONSE_BYTES = 408,0,0,0 %; literal RMSTTS$S_KMO_RESPONSE_BYTES = 8; ! Number of bytes processed for responses via kernel-mode MO interface macro RMSTTS$L_UMO_REQUESTS = 416,0,32,0 %; ! Number of requests via user-mode MO interface macro RMSTTS$L_UMO_ARG_ERRORS = 420,0,32,0 %; ! Number of argument errors from requests via user-mode MO interface macro RMSTTS$L_UMO_ALIGN_ERRORS = 424,0,32,0 %; ! Number of alignment errors from requests via user-mode MO interface macro RMSTTS$L_UMO_FMT_ERRORS = 428,0,32,0 %; ! Number of format errors from requests via user-mode MO interface macro RMSTTS$L_UMO_PROC_ERRORS = 432,0,32,0 %; ! Number of processing errors from requests via user-mode MO interface macro RMSTTS$L_RSVD5 = 436,0,32,0 %; ! Reserved (quadword alignment) macro RMSTTS$Q_UMO_REQUEST_BYTES = 440,0,0,0 %; literal RMSTTS$S_UMO_REQUEST_BYTES = 8; ! Number of bytes processed for requests via user-mode MO interface macro RMSTTS$Q_UMO_RESPONSE_BYTES = 448,0,0,0 %; literal RMSTTS$S_UMO_RESPONSE_BYTES = 8; ! Number of bytes processed for responses via user-mode MO interface macro RMSTTS$L_NDA_REQUESTS = 456,0,32,0 %; ! Number of requests via network DA interface macro RMSTTS$L_NDA_ARG_ERRORS = 460,0,32,0 %; ! Number of argument errors from requests via network DA interface macro RMSTTS$L_NDA_ALIGN_ERRORS = 464,0,32,0 %; ! Number of alignment errors from requests via network DA interface ! This is not an error in this case, but record the number of adjustments macro RMSTTS$L_NDA_FMT_ERRORS = 468,0,32,0 %; ! Number of format errors from requests via network DA interface macro RMSTTS$L_NDA_PROC_ERRORS = 472,0,32,0 %; ! Number of processing errors from requests via network DA interface macro RMSTTS$L_RSVD6 = 476,0,32,0 %; ! Reserved (quadword alignment) macro RMSTTS$Q_NDA_REQUEST_BYTES = 480,0,0,0 %; literal RMSTTS$S_NDA_REQUEST_BYTES = 8; ! Number of bytes processed for requests via network DA interface macro RMSTTS$Q_NDA_RESPONSE_BYTES = 488,0,0,0 %; literal RMSTTS$S_NDA_RESPONSE_BYTES = 8; ! Number of bytes processed for responses via network DA interface macro RMSTTS$L_LDA_REQUESTS = 496,0,32,0 %; ! Number of requests via local DA interface macro RMSTTS$L_LDA_ARG_ERRORS = 500,0,32,0 %; ! Number of argument errors from requests via local DA interface macro RMSTTS$L_LDA_ALIGN_ERRORS = 504,0,32,0 %; ! Number of alignment errors from requests via local DA interface macro RMSTTS$L_LDA_FMT_ERRORS = 508,0,32,0 %; ! Number of format errors from requests via local DA interface macro RMSTTS$L_LDA_PROC_ERRORS = 512,0,32,0 %; ! Number of processing errors from requests via local DA interface macro RMSTTS$L_RSVD7 = 516,0,32,0 %; ! Reserved (quadword alignment) macro RMSTTS$Q_LDA_REQUEST_BYTES = 520,0,0,0 %; literal RMSTTS$S_LDA_REQUEST_BYTES = 8; ! Number of bytes processed for requests via local DA interface macro RMSTTS$Q_LDA_RESPONSE_BYTES = 528,0,0,0 %; literal RMSTTS$S_LDA_RESPONSE_BYTES = 8; ! Number of bytes processed for responses via local DA interface ! ! RMDRIVER MO and MO status data from GET_STATUS request ! ! This structure represents data for Managed Object Parameter version 1.1 ! literal RMSDT$K_OBJ_REG_STS_RESERVED = 0; ! 0 - Reserved (for debugging) literal RMSDT$K_OBJ_REG_STS_REGISTERED = 1; ! 1 - MO is registered literal RMSDT$K_OBJ_REG_STS_DREGISTERED = 2; ! 2 - MO is deregistered literal RMSDT$K_OBJ_RUN_STS_RESERVED = 0; ! 0 - Reserved (for debugging) literal RMSDT$K_OBJ_RUN_STS_REQ_ON = 1; ! 1 - MO is processing requests literal RMSDT$K_OBJ_RUN_STS_REQ_OFF = 2; ! 2 - MO is not processing requests literal RMSDT$K_V1_1_STSDAT_LEN = 8; ! Reg out data length literal RMSDT$C_V1_1_STSDAT_LEN = 8; ! Old VAX style length literal RMSDT$S_RMSDT = 8; macro RMSDT$B_OBJ_REG_STATUS = 0,0,8,0 %; ! MO Registration status macro RMSDT$B_OBJ_RUN_STATUS = 1,0,8,0 %; ! MO Run status macro RMSDT$B_RM_OBJ_REG_STATUS = 2,0,8,0 %; ! RMDriver MO Registration status macro RMSDT$B_RM_OBJ_RUN_STATUS = 3,0,8,0 %; ! RMDriver MO Run status macro RMSDT$W_RM_DRV_STATUS = 4,0,16,0 %; ! RMDriver run status (RMSTS$ constants) macro RMSDT$W_RSVD = 6,0,16,0 %; ! Quadword alignment ! ! RMDriver action codes ! Note quadword unsigned; /*anaged Object specific codes start at 16 ! Note: Because of early implementations of Managed Object using 0-16, the range of common codes had ! to be moved. Will keep the 1-15 entries for RMDriver open so that the common codes can ! be shifted to the 1-15 space. ! ! Managed Object/Data Analyzer request codes for RMDriver to process literal RMACT$K_RM_REGISTER = 16; ! 16 - Register Managed Object literal RMACT$K_RM_DEREGISTER = 17; ! 17 - Deregister Managed Object literal RMACT$K_RM_ENABLE_REQ = 18; ! 18 - Enable request transfer to Managed Object literal RMACT$K_RM_DISABLE_REQ = 19; ! 19 - Disable request transfer to Managed Object literal RMACT$K_RM_GET_STATUS = 20; ! 20 - Retrieve RMDriver's status (stopped/started, etc.) and ! what RMDriver's status is for the Managed Object literal RMACT$K_RM_GET_REGISTRATION = 21; ! 21 - Retrieve RMDriver's registration data literal RMACT$K_RM_CALLBACK_ROUTINES = 22; ! 22 - Retrieve RMDriver's kernel-mode callback routines literal RMACT$K_RM_GET_RM_CONFIGURATION = 23; ! 23 - Retrieve RMDriver's configuration literal RMACT$K_RM_SET_RM_CONFIGURATION = 24; ! 24 - Set RMDriver's configuration literal RMACT$K_RM_GET_RM_STATISTICS = 25; ! 25 - Get RMDriver-specific statistics literal RMACT$K_RM_RESET_RM_STATISTICS = 26; ! 26 - Reset RMDriver-specific statistics literal RMACT$K_RM_GET_MO_STATISTICS = 27; ! 27 - Get a/all Managed Object's statistics literal RMACT$K_RM_RESET_MO_STATISTICS = 28; ! 28 - Reset a/all Managed Object's statistics literal RMACT$K_RM_FIRST_UNUSED = 29; ! Add new code ahead of this one literal RMACT$K_RM_FIRST_CODE = 16; ! First RM action code literal RMACT$K_RM_LAST_CODE = 28; ! Last RM action code ! ! Action code constants for backward compatibility ! ! Managed Object/Data Analyzer request codes for RMDriver to process literal RMACT$K_RM_GET_CONFIGURATION = 23; ! 23 - Retrieve RMDriver's configuration literal RMACT$K_RM_SET_CONFIGURATION = 24; ! 24 - Set RMDriver's configuration ! ! RMDriver error codes ! Note: Managed Object specific codes start at 128 ! literal RMMGT$K_STS_REG_INSFMEM = 128; ! Can't allocate memory for a registration entry literal RMMGT$K_STS_REG_DB_FULL = 129; ! Registration database is full literal RMMGT$K_STS_OBJ_NAME_NULL = 130; ! Managed Object's name field is null literal RMMGT$K_STS_OBJ_REGISTERED = 131; ! Managed Object is already registered literal RMMGT$K_STS_OBJ_DEREGISTERED = 132; ! Managed Object has deregistered literal RMMGT$K_STS_OBJ_ENABLED_REQ = 133; ! Managed Object has enabled request processing literal RMMGT$K_STS_OBJ_DISABLED_REQ = 134; ! Managed Object has disabled request processing literal RMMGT$K_STS_OBJ_STS_INVALID = 135; ! Managed Object registration status is invalid !*** MODULE $WBMDEF *** literal WBM$K_MAX_BITMAPS = 12; literal WBM$K_MAX_BITMAPS_GROUP1 = 6; literal WBM$K_MAX_BITMAPS_GROUP2 = 12; literal WBM$K_MAX_NAMLEN = 64; literal WBMSG$K_MAX_SET_RQSTS = 9; ! based on the max msg size in cluster.sdl literal WBM$K_LWORDS_PER_BUFF = 27; ! based on the max msg size in cluster.sdl literal WBM$M_VERSION = 15; literal WBM$K_MSG_V1 = 1; literal WBM$K_CLU_FAC_V1 = 127; ! + ! Flags argument to $START_BITMAP ! - literal WBM$M_GROUP1 = %X'1'; literal WBM$M_GROUP2 = %X'2'; literal WBM$M_GROUP3 = %X'4'; literal WBM$M_MINICOPY = %X'100'; literal WBM$M_HBMM = %X'200'; literal WBM$S_STARTDEF = 4; macro WBM$V_GROUP1 = 0,0,1,0 %; ! Use first group of bitmap slots macro WBM$V_GROUP2 = 0,1,1,0 %; ! Use second group of bitmap slots macro WBM$V_GROUP3 = 0,2,1,0 %; ! Use all bitmap slots macro WBM$v_fill_3_to_7 = 0,3,5,0 %; literal WBM$s_fill_3_to_7 = 5; ! unused macro WBM$V_MINICOPY = 0,8,1,0 %; ! This is a minicopy bitmap macro WBM$V_HBMM = 0,9,1,0 %; ! This is a hbmm bitmap macro WBM$V_UNUSED = 0,10,1,0 %; literal WBM$S_UNUSED = 22; ! Reserved flags macro WBM$L_STARTDEF_OVERLAY = 0,0,32,0 %; ! Longword overlay ! + ! POLICY argument to $START_BITMAP ! - literal WBM_POL$S_POLICYDEF = 4; macro WBM_POL$B_SUB_GROUP = 0,0,8,0 %; ! pointer to sub_group macro WBM_POL$B_AMCCNT = 1,0,8,0 %; ! pointer to amccnt macro WBM_POL$B_DMTCNT = 2,0,8,0 %; ! HBMM_DMT macro WBM_POL$B_UNUSED = 3,0,8,0 %; ! Spare macro WBM_POL$L_POLICY_OVERLAY = 0,0,32,0 %; ! Longword overlay ! + ! Get info item codes ! - literal WBM$_BITMAP_NAME = 1; literal WBM$_LOCAL_HANDLE = 2; literal WBM$_CREATE_SYSTIME = 3; literal WBM$_CLUSTER_SIZE = 4; literal WBM$_BITMAP_SIZE = 5; literal WBM$_MASTER_CSID = 6; literal WBM$_DELETE_RQST = 7; literal WBM$_STOPPED = 8; literal WBM$_REFCNT = 9; literal WBM$_MASTER_BITS_SET = 10; literal WBM$_LOCAL_BITS_SET = 11; literal WBM$_SUB_GROUP = 12; literal WBM$_AMCCNT = 13; literal WBM$_UNIT = 14; literal WBM$_INDEX = 15; literal WBM$_DMTCNT = 16; literal WBM$_BITMAP_TYPE = 17; literal WBM$K_MAX_BMI_ITEMS = 17; literal WBM$S_BITMAP_NAME = 64; literal WBM$S_LOCAL_HANDLE = 4; literal WBM$S_CREATE_SYSTIME = 8; literal WBM$S_CLUSTER_SIZE = 2; literal WBM$S_BITMAP_SIZE = 4; literal WBM$S_MASTER_CSID = 4; literal WBM$S_DELETE_RQST = 1; literal WBM$S_STOPPED = 1; literal WBM$S_REFCNT = 2; literal WBM$S_MASTER_BITS_SET = 4; literal WBM$S_LOCAL_BITS_SET = 4; literal WBM$S_SUB_GROUP = 1; literal WBM$S_AMCCNT = 1; literal WBM$S_UNIT = 4; literal WBM$S_INDEX = 1; literal WBM$S_DMTCNT = 1; literal WBM$S_BITMAP_TYPE = 2; ! + ! Msging identifiers ! - literal WBM$K_INIT = 1; literal WBM$K_CREATE = 2; literal WBM$K_DELETE = 3; literal WBM$K_START = 4; literal WBM$K_STOP = 5; literal WBM$K_GET_INFO = 6; literal WBM$K_SCAN = 7; literal WBM$K_CHECK = 8; literal WBM$K_SET = 9; literal WBM$K_SET_NAME = 10; literal WBM$K_PACK_SET = 11; literal WBM$K_INFO = 12; literal WBM$K_WRTLCK = 13; literal WBM$K_UNWRTLCK = 14; literal WBM$K_TEST = 15; literal WBM$K_MSG_MODE = 16; ! + ! Opcom level constants ! - literal WBM$K_OPCOM_LOW = 0; literal WBM$K_OPCOM_MED = 1; ! + ! Deletion flags ! - literal WBM$K_DEL_SING = 1; literal WBM$K_DEL_ALL = 2; literal WBM$K_DEL_RQST = 3; ! + ! Write lock state codes ! - literal WBM$K_CWL_NOLCK = 1; literal WBM$K_CWL_NL = 2; literal WBM$K_CWL_CR = 3; literal WBM$K_CWL_CW = 4; literal WBM$K_CWL_PR = 5; ! + ! WBIL - write bitmap itemlist ! - literal WBIL$S_WBILDEF = 142; literal WBIL$S_WBIL = 144; macro WBIL$B_COUNT = 0,0,8,0 %; ! count of items in the item list macro WBIL$B_FUNC_RQST = 1,0,0,0 %; literal WBIL$S_FUNC_RQST = 7; ! one byte for each of the item codes macro WBIL$W_NAME_LEN = 8,0,16,0 %; ! storage for name length macro WBIL$W_CREATE_SYSTIME_LEN = 10,0,16,0 %; ! storage for time length macro WBIL$W_BITS_SET_LEN = 12,0,16,0 %; ! storage for master bits set field macro WBIL$W_MASTER_CSID_LEN = 14,0,16,0 %; ! storage for master csid length macro WBIL$W_CLUSTER_SIZE_LEN = 16,0,16,0 %; ! storage for cluster size length macro WBIL$W_DELETE_RQST_LEN = 18,0,16,0 %; ! storage for delete request length macro WBIL$W_STOPPED_LEN = 20,0,16,0 %; ! storage for stopped length macro WBIL$B_NAME_BUF = 22,0,0,0 %; literal WBIL$S_NAME_BUF = 64; ! buffer for bitmap name macro WBIL$Q_CREATE_SYSTIME = 86,0,0,0 %; literal WBIL$S_CREATE_SYSTIME = 8; ! storage for timestamp macro WBIL$L_BITS_SET = 94,0,32,0 %; ! storage for number of bits set macro WBIL$L_MASTER_CSID = 98,0,32,0 %; ! storage for csid macro WBIL$W_CLUSTER_SIZE = 102,0,16,0 %; ! storage for cluster size macro WBIL$B_DELETE_RQST = 104,0,8,0 %; ! storage for delete request bit macro WBIL$B_STOPPED = 105,0,8,0 %; ! storage for stopped bit macro WBIL$W_SUB_GROUP_LEN = 106,0,16,0 %; ! storage for subgroup length macro WBIL$W_AMCCNT_LEN = 108,0,16,0 %; ! storage for amccnt length macro WBIL$W_REFCNT_LEN = 110,0,16,0 %; ! storage for refcntlength macro WBIL$W_UNIT_LEN = 112,0,16,0 %; ! storage for unit length macro WBIL$W_INDEX_LEN = 114,0,16,0 %; ! storage for index length macro WBIL$W_DMTCNT_LEN = 116,0,16,0 %; ! storage for dmtcnt length macro WBIL$W_BITMAP_TYPE_LEN = 118,0,16,0 %; ! storage for bitmap_type length macro WBIL$B_SUB_GROUP = 120,0,8,0 %; ! storage for sub_group macro WBIL$B_AMCCNT = 121,0,8,0 %; ! storage for amccnt macro WBIL$L_UNIT = 122,0,32,0 %; ! storage for unit macro WBIL$W_REFCNT = 126,0,16,0 %; ! storage for refcnt macro WBIL$B_INDEX = 128,0,8,0 %; ! storage for index macro WBIL$B_DMTCNT = 129,0,8,0 %; ! storage for dmtcnt macro WBIL$W_BITMAP_TYPE = 130,0,16,0 %; ! storage for bitmap_type macro WBIL$B_FUNC_RQST_EXT = 132,0,0,0 %; literal WBIL$S_FUNC_RQST_EXT = 10; ! one byte for each of the item codes ! + ! BMIL - write bitmap itemlist ! - literal BMIL$S_BMILDEF = 360; literal BMIL$S_BMIL = 360; macro BMIL$R_ITEMLIST_ENTRY = 0,0,0,0 %; literal BMIL$S_ITEMLIST_ENTRY = 216; ! array of item list entries macro BMIL$W_RETLEN_ENTRY = 216,0,0,0 %; literal BMIL$S_RETLEN_ENTRY = 36; ! Array of RETLEN values ! Space for item data macro BMIL$R_DATA = 252,0,0,0 %; literal BMIL$S_DATA = 108; ! + ! WBMH -- WBM Bitmap handle ! - literal WBMH$S_WBMH = 4; macro WBMH$R_HANDLE = 0,0,32,0 %; literal WBMH$S_HANDLE = 4; macro WBMH$L_WBMH = 0,0,32,0 %; macro WBMH$R_OVERLAY = 0,0,32,0 %; literal WBMH$S_OVERLAY = 4; macro WBMH$W_IDX = 0,0,16,0 %; ! index into WBM handle array macro WBMH$W_SEQ = 2,0,16,0 %; ! sequence # for bitmap identification ! + ! WBM_LCK -- WBM lock context block ! - literal WBM_LCK$S_WBM_LCKDEF = 48; literal WBM_LCK$S_WBM_LCK = 48; macro WBM_LCK$R_LKSB = 0,0,0,0 %; literal WBM_LCK$S_LKSB = 24; ! Lock status block for the LVB validation lock macro WBM_LCK$L_SIZE = 24,0,32,0 %; ! size of the allocated context block macro WBM_LCK$L_LCK_SEQ = 28,0,32,0 %; ! sequence counter for the lock state macro WBM_LCK$R_WBMH = 32,0,32,0 %; literal WBM_LCK$S_WBMH = 4; ! handle for associated wbme macro WBM_LCK$R_RES_DSC = 36,0,0,0 %; literal WBM_LCK$S_RES_DSC = 12; ! starting address for the resource name descriptor ! + ! WBMH_ENTRY -- WBM entry in the handle array ! - literal WBMH_ENTRY$S_WBMH_ENTRYDEF = 8; literal WBMH_ENTRY$S_WBMH_ENTRY = 8; macro WBMH_ENTRY$PS_WBMB = 0,0,32,1 %; ! address of a wbmb macro WBMH_ENTRY$W_NEXT_IDX = 0,0,16,0 %; ! contains the idx of the next available entry macro WBMH_ENTRY$L_BM_INFO = 4,0,32,0 %; macro WBMH_ENTRY$W_SEQ = 4,0,16,0 %; ! sequence number of the bitmap macro WBMH_ENTRY$B_IDX = 6,0,8,0 %; ! index idextifying this WBME within its WBMB macro WBMH_ENTRY$b_fill_1 = 7,0,8,1 %; ! fill to next longword macro WBMH_ENTRY$L_WBMH_EN_TYPE = 4,0,32,0 %; macro WBMH_ENTRY$W_SIZE = 4,0,16,0 %; ! Structure size in QUADWORDS macro WBMH_ENTRY$B_TYPE = 6,0,8,0 %; ! WBM structure type macro WBMH_ENTRY$B_SUBTYPE = 7,0,8,0 %; ! WBMH_ARRAY subtype ! + ! WBLVB -- Write Bitmap Lock Value Block Overlay ! - literal WBLVB$S_WBLVBDEF = 15; literal WBLVB$S_WBLVB = 16; macro WBLVB$L_CSID = 0,0,32,0 %; ! cluster system id macro WBLVB$W_CSID_IDX = 0,0,16,0 %; ! slot idx macro WBLVB$W_CSID_SEQ = 2,0,16,0 %; ! sequence number macro WBLVB$R_WBMH = 4,0,32,0 %; literal WBLVB$S_WBMH = 4; ! bitmap handle macro WBLVB$L_MAXBLOCK = 8,0,32,0 %; ! max block from the master's vu ucb macro WBLVB$W_CLUSTER = 12,0,16,0 %; ! Cluster factor macro WBLVB$B_VERSION = 14,0,8,0 %; ! Protocol version (note: only low four bits) ! MAXMSG byte unsigned; maximum message size in quadwords FUTURE VERISON ! + ! WBM -- Actual bitmap structure and header to be allocated from memory (S2 or nonpaged pool) ! - literal WBM$C_LENGTH = 124; literal WBM$K_LENGTH = 124; literal WBM$S_WBMDEF = 124; ! Old size name synonym literal WBM$S_WBM = 128; macro WBM$PQ_BITMAP = 0,0,0,1 %; literal WBM$S_BITMAP = 8; ! longword pointer to address after this structure macro WBM$L_SIZE = 8,0,32,0 %; ! Structure size in bytes macro WBM$B_TYPE = 12,0,8,0 %; ! WBM Structure type macro WBM$B_SUBTYPE = 13,0,8,0 %; ! Bitmap subtype macro WBM$W_CLUSTER = 14,0,16,0 %; ! cluster factor (#blocks/bit) macro WBM$B_NAME = 16,0,0,0 %; literal WBM$S_NAME = 64; ! identification string for the bitmap macro WBM$L_XFER_CNT = 80,0,32,0 %; ! count of longwords transfered for this bitmap macro WBM$L_BITS_SET = 84,0,32,0 %; ! count of bis set in the bitmap macro WBM$R_LKSB = 88,0,0,0 %; literal WBM$S_LKSB = 24; ! lock status block macro WBM$L_NAME_LEN = 112,0,32,0 %; ! length of name buffer macro WBM$B_SUB_GROUP = 116,0,8,0 %; ! Policy sub_group macro WBM$B_AMCCNT = 117,0,8,0 %; ! Policy AMCCNT macro WBM$W_REFCNT = 118,0,16,0 %; ! refcnt macro WBM$B_DMTCNT = 120,0,8,0 %; ! dmtcnt macro WBM$B_SPARE_B = 121,0,8,0 %; ! unused macro WBM$W_BITMAP_TYPE = 122,0,16,0 %; ! bitmap_type ! + ! WBME -- Bitmap entry structure ! - literal WBME$M_SLOT_INUSE = %X'1'; literal WBME$M_EXISTS = %X'2'; literal WBME$M_ACTIVE = %X'4'; literal WBME$M_MASTER = %X'8'; literal WBME$M_DELETE_RQST = %X'10'; literal WBME$M_INIT_PENDING = %X'20'; literal WBME$M_START_PENDING = %X'40'; literal WBME$M_CW_PENDING = %X'80'; literal WBME$S_WBMEDEF = 110; literal WBME$S_WBME = 112; macro WBME$PQ_WBM = 0,0,0,1 %; literal WBME$S_WBM = 8; ! quadword pointer to wbm structure macro WBME$Q_TIME = 8,0,0,0 %; literal WBME$S_TIME = 8; ! timestamp macro WBME$Q_VAPTE = 16,0,0,0 %; literal WBME$S_VAPTE = 8; ! VAPTE for deallocation of S2 macro WBME$L_BITMAP_SIZE = 24,0,32,0 %; ! upward bound of the bitmap array (longwords) macro WBME$L_FPC = 28,0,32,1 %; ! completion routine address macro WBME$R_CTX_OVERLAY = 32,0,0,0 %; ! context parameter for the completion routine macro WBME$Q_CTX1 = 32,0,0,0 %; literal WBME$S_CTX1 = 8; macro WBME$L_CTX1 = 32,0,32,0 %; macro WBME$L_FLAGS = 40,0,32,0 %; ! flags macro WBME$V_SLOT_INUSE = 40,0,1,0 %; ! indicates this wbme is in use macro WBME$V_EXISTS = 40,1,1,0 %; ! indicates that a bitmap has been allocated(no guaranteed local caching) macro WBME$V_ACTIVE = 40,2,1,0 %; ! indicates the state of a bitmap (1 = tracking writes / 0 = no write tracking) macro WBME$V_MASTER = 40,3,1,0 %; ! indicates this WBME masters the bitmap macro WBME$V_DELETE_RQST = 40,4,1,0 %; ! indicates deletion requested but could not be completed as yet macro WBME$V_INIT_PENDING = 40,5,1,0 %; ! indicates WBME in the process of initialization macro WBME$V_START_PENDING = 40,6,1,0 %; ! indicates WBME in the process of activation macro WBME$V_CW_PENDING = 40,7,1,0 %; ! indicates CW conversion outstanding macro WBME$B_LCK_NAME = 44,0,0,1 %; literal WBME$S_LCK_NAME = 32; ! lock name macro WBME$R_LKSB = 76,0,0,0 %; literal WBME$S_LKSB = 24; ! lock status block macro WBME$L_LCK_SEQ = 100,0,32,0 %; ! CW lock sequence counter macro WBME$L_MAXBLOCK = 104,0,32,0 %; ! max block count of the associated device macro WBME$W_WBMH_IDX = 108,0,16,0 %; ! index into the WBM handle array identifying this WBME ! + ! WBMB -- Main tracking structure for Bitmap code ! - literal WBMB$M_IGNORE_GROUP1 = %X'2'; literal WBMB$M_IGNORE_GROUP2 = %X'4'; literal WBMB$M_IGNORE_GROUP3 = %X'8'; literal WBM$K_IGNORE_LOCAL = 1; literal WBM$K_USE_LOCAL = 2; literal WBMB$S_WBMBDEF = 1552; literal WBMB$S_WBMB = 1552; macro WBMB$PS_FLINK = 0,0,32,1 %; ! Flink for master WBMB list macro WBMB$PS_BLINK = 4,0,32,1 %; ! Blink macro WBMB$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro WBMB$B_TYPE = 10,0,8,0 %; ! WBM structure type macro WBMB$B_SUBTYPE = 11,0,8,0 %; ! WBMB subtype macro WBMB$PS_UCB = 12,0,32,1 %; ! Pointer to the associated UCB macro WBMB$W_FLAGS = 16,0,16,0 %; ! flags macro WBMB$B_INIT_OUTSTANDING = 18,0,8,0 %; ! number of outstanding lock transitions macro WBMB$b_fill_1 = 19,0,8,1 %; ! fill to next longword macro WBMB$L_FPC = 20,0,32,1 %; ! completion routine address macro WBMB$L_CTX1 = 24,0,32,0 %; ! context parameter macro WBMB$L_CTX2 = 28,0,32,0 %; ! context parameter macro WBMB$L_DELETE_COUNT = 32,0,32,0 %; ! debug delete counter ??? remove ??? macro WBMB$L_WRITES_IN_PROGRESS_CNT = 36,0,32,1 %; ! Count of outstanding writes macro WBMB$L_WRITELOCKED = 40,0,32,0 %; macro WBMB$B_SYS_WRITELOCK_CNT = 40,0,8,1 %; ! count of writelock requests by trusted system routines macro WBMB$B_DCL_WRITELOCK_CNT = 41,0,8,1 %; ! count of writelock requests from DCL macro WBMB$Q_WRITELOCKED_IRP_LIST = 44,0,0,0 %; literal WBMB$S_WRITELOCKED_IRP_LIST = 8; ! linked list of stalled irps macro WBMB$PS_IRP_FLINK = 44,0,32,1 %; macro WBMB$PS_IRP_BLINK = 48,0,32,1 %; macro WBMB$Q_WRITELOCKED_NOTIFY = 52,0,0,1 %; literal WBMB$S_WRITELOCKED_NOTIFY = 8; ! list of fork blocks to be activated when the write lock request completes macro WBMB$PS_FKB_FLINK = 52,0,32,1 %; macro WBMB$PS_FKB_BLINK = 56,0,32,1 %; macro WBMB$R_CWL_LKSB_LOCAL = 60,0,0,0 %; literal WBMB$S_CWL_LKSB_LOCAL = 24; ! lock status block for CR-CW lock macro WBMB$R_CWL_LKSB_WL = 84,0,0,0 %; literal WBMB$S_CWL_LKSB_WL = 24; ! lock status block for PW lock macro WBMB$B_CWL_LOCKNAME = 108,0,0,1 %; literal WBMB$S_CWL_LOCKNAME = 32; ! write lock resource name macro WBMB$R_CWL_DSC = 140,0,0,0 %; literal WBMB$S_CWL_DSC = 8; ! Descriptor for CWL_LOCKNAME macro WBMB$W_CWL_DSC_LENGTH = 140,0,16,0 %; ! Length in bytes of CWL name string macro WBMB$B_CWL_DSC_DTYPE = 142,0,8,0 %; ! Data type (DSC$K_DTYPE_T) macro WBMB$B_CWL_DSC_CLASS = 143,0,8,0 %; ! Storage class (DSC$K_CLASS_S) macro WBMB$A_CWL_DSC_POINTER = 144,0,32,1 %; ! Address of CWL name string (WBMB$B_CWL_LOCKNAME) macro WBMB$L_CWL_COMPLETION_RTN = 148,0,32,1 %; ! completion routine address macro WBMB$R_CTX_OVERLAY = 152,0,0,0 %; ! completion routine context macro WBMB$Q_CWL_COMPLETION_CONTEXT = 152,0,0,0 %; literal WBMB$S_CWL_COMPLETION_CONTEXT = 8; macro WBMB$Q_TWO_CTX_PARAMS = 152,0,0,0 %; literal WBMB$S_TWO_CTX_PARAMS = 8; macro WBMB$L_CWL_COMPLETION_CONTEXT1 = 152,0,32,0 %; macro WBMB$L_CWL_COMPLETION_CONTEXT2 = 156,0,32,0 %; macro WBMB$B_CWL_LOCAL_STATE = 160,0,8,0 %; ! DLM lock state for the CR-CW progression macro WBMB$B_CWL_WL_STATE = 161,0,8,0 %; ! DLM lock state for the PW lock macro WBMB$L_SET_CNT = 164,0,32,0 %; ! debug counters remove !!! macro WBMB$L_REM_SET_CNT = 168,0,32,0 %; ! debug counters remove !!! macro WBMB$L_CACHE_HIT_CNT = 172,0,32,0 %; ! debug counters remove !!! macro WBMB$L_IGNORE_BITMAP_MASK = 176,0,32,0 %; ! Mask of local bitmap groups to ignore macro WBMB$v_fill_0 = 176,0,1,0 %; ! unused macro WBMB$V_IGNORE_GROUP1 = 176,1,1,0 %; ! Ignore Group 1 local bitmaps macro WBMB$V_IGNORE_GROUP2 = 176,2,1,0 %; ! Ignore Group 2 local bitmaps macro WBMB$V_IGNORE_GROUP3 = 176,3,1,0 %; ! Ignore Group 3 local bitmaps macro WBMB$v_fill_4_to_31 = 176,4,28,0 %; literal WBMB$s_fill_4_to_31 = 28; ! unused macro WBMB$R_BITMAP_ENTRY = 208,0,0,0 %; literal WBMB$S_BITMAP_ENTRY = 1344; ! array of WBME structures identifying bitmaps ! + ! WBML -- head structure for linking WBMB's ! - literal WBML$S_WBMLDEF = 8; literal WBML$S_WBML = 8; macro WBML$PS_FLINK = 0,0,32,1 %; ! Flink for master WBMB list macro WBML$PS_BLINK = 4,0,32,1 %; ! Blink ! + ! WBMCD -- Write bitmap connection descriptor entry ! - literal WBMCD$M_BUFFER_MODE = %X'1'; literal WBMCD$M_NODE_REMOVED = %X'2'; literal WBMCD$M_RES_ALLOC_PENDING = %X'4'; literal WBMCD$S_WBMCDDEF = 96; literal WBMCD$S_WBMCD = 96; macro WBMCD$PS_FLINK = 0,0,32,1 %; ! Flink macro WBMCD$PS_BLINK = 4,0,32,1 %; ! Blink macro WBMCD$L_FLAGS = 8,0,32,0 %; macro WBMCD$V_BUFFER_MODE = 8,0,1,0 %; ! indicates packaging set messages mode macro WBMCD$V_NODE_REMOVED = 8,1,1,0 %; ! node removed from cluster macro WBMCD$V_RES_ALLOC_PENDING = 8,2,1,0 %; ! resource allocation and intialization pending macro WBMCD$L_WBMCD_TYPE = 8,0,32,0 %; macro WBMCD$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro WBMCD$B_TYPE = 10,0,8,0 %; ! WBM macro WBMCD$B_SUBTYPE = 11,0,8,0 %; ! WBMCD_ARRAY macro WBMCD$L_CSID = 12,0,32,0 %; ! cluster system id macro WBMCD$W_CSID_IDX = 12,0,16,0 %; ! slot idx macro WBMCD$W_CSID_SEQ = 14,0,16,0 %; ! sequence number macro WBMCD$PS_IRP_FLINK = 16,0,32,1 %; ! Queue head for IRP's waiting on a resouce CDRP/RSPID/MSGBUF macro WBMCD$PS_IRP_BLINK = 20,0,32,1 %; ! Blink macro WBMCD$Q_INTERVAL_END = 24,0,0,0 %; literal WBMCD$S_INTERVAL_END = 8; ! end of sampling interval for dynamic message switching macro WBMCD$PS_CDRP = 32,0,32,1 %; ! pointer to CDRP for set bitmap macro WBMCD$L_MSG_PER_INT = 36,0,32,0 %; ! count of the total number of messages sent during this interval macro WBMCD$W_RQST_PER_BUF = 40,0,16,0 %; ! count of the number of set request in the buffer macro WBMCD$PS_WBM_CTX_FLINK = 48,0,32,1 %; ! Queue head for wbm_ctx's associated with this connection macro WBMCD$PS_WBM_CTX_BLINK = 52,0,32,1 %; ! Blink macro WBMCD$Q_SETBIT_PER_INT = 56,0,0,0 %; literal WBMCD$S_SETBIT_PER_INT = 8; ! Count of setbit per wbm_msg_interval. macro WBMCD$Q_MSG_SENT_SINGLE = 64,0,0,0 %; literal WBMCD$S_MSG_SENT_SINGLE = 8; ! Messages sent in single mode. macro WBMCD$Q_MSG_SENT_BUF_PARTIAL = 72,0,0,0 %; literal WBMCD$S_MSG_SENT_BUF_PARTIAL = 8; ! Partially populated messages sent in buffered mode macro WBMCD$Q_MSG_SENT_BUF_FULL = 80,0,0,0 %; literal WBMCD$S_MSG_SENT_BUF_FULL = 8; ! Fully populated messages sent in buffered mode macro WBMCD$Q_MODE_TRANS_CNT = 88,0,0,0 %; literal WBMCD$S_MODE_TRANS_CNT = 8; ! No. of Transitions between single and buffered mode ! + ! WBM_CTX -- Write bitmap setbit Send context ! - literal WBM_CTX$S_WBM_CTXDEF = 130; literal WBM_CTX$C_LENGTH = 130; literal WBM_CTX$K_LENGTH = 130; literal WBM_CTX$S_WBM_CTX = 132; macro WBM_CTX$PS_FLINK = 0,0,32,1 %; ! Flink macro WBM_CTX$PS_BLINK = 4,0,32,1 %; ! Blink macro WBM_CTX$L_WBM_CTX = 8,0,32,0 %; macro WBM_CTX$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro WBM_CTX$B_TYPE = 10,0,8,0 %; ! WBM macro WBM_CTX$B_SUBTYPE = 11,0,8,0 %; ! WBM_CTX macro WBM_CTX$PS_CDRP = 12,0,32,1 %; ! pointer to CDRP for set bitmap macro WBM_CTX$L_IRP_COUNT = 16,0,32,0 %; ! count of the number of IRPs associated with this context macro WBM_CTX$PS_IRP_ARRAY = 20,0,0,1 %; literal WBM_CTX$S_IRP_ARRAY = 36; ! Array of IRP's associated with this CDRP/wbm_ctx. macro WBM_CTX$W_SEQIO_FLG = 56,0,16,0 %; ! To store the seqio_flag for each IRP. macro WBM_CTX$L_REM_HANDLE_ARRAY = 58,0,0,0 %; literal WBM_CTX$S_REM_HANDLE_ARRAY = 36; ! Array of remote handles macro WBM_CTX$L_LCL_HANDLE_ARRAY = 94,0,0,0 %; literal WBM_CTX$S_LCL_HANDLE_ARRAY = 36; ! Array of local handles ! + ! WBM_DATA -- Write bitmap global data block ! - literal WBM_DATA$M_SHADOW_CAPABLE = %X'1'; literal WBM_DATA$M_TQE_ENABLED = %X'2'; literal WBM_DATA$S_WBM_DATADEF = 40; literal WBM_DATA$C_LENGTH = 40; literal WBM_DATA$K_LENGTH = 40; literal WBM_DATA$S_WBM_DATA = 40; macro WBM_DATA$L_VERSION = 0,0,32,0 %; ! write bitmap code version (will be accessed directly by shadowing macro WBM_DATA$W_MAJOR_VER = 0,0,16,0 %; ! major version macro WBM_DATA$W_MINOR_VER = 2,0,16,0 %; ! minor version macro WBM_DATA$GL_STATUS = 4,0,32,0 %; macro WBM_DATA$V_SHADOW_CAPABLE = 4,0,1,0 %; ! indicates node capable of performing WBM functionality macro WBM_DATA$V_TQE_ENABLED = 4,1,1,0 %; ! indicates whether a TQE was queued to process the connection list macro WBM_DATA$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro WBM_DATA$B_TYPE = 10,0,8,0 %; ! WBM structure type macro WBM_DATA$B_SUBTYPE = 11,0,8,0 %; ! WBM_DATA subtype macro WBM_DATA$GL_CONNECTIONS = 12,0,32,1 %; ! pointer to an array of connection descriptor entries macro WBM_DATA$GQ_CNXLISTN = 16,0,0,0 %; literal WBM_DATA$S_CNXLISTN = 8; ! Doubly linked list of connection descriptors sending N message macro WBM_DATA$PS_CLN_FLINK = 16,0,32,1 %; macro WBM_DATA$PS_CLN_BLINK = 20,0,32,1 %; macro WBM_DATA$GL_WBMH_ARRAY = 24,0,32,1 %; ! address of the WBM handle array macro WBM_DATA$L_SF_MSG_SENT = 28,0,32,0 %; ! total number of immediate bitmap update messages sent macro WBM_DATA$L_TQE_MSG_SENT = 32,0,32,0 %; ! total number of timer-driven bitmap update messages sent macro WBM_DATA$L_CWCANCEL = 36,0,32,0 %; ! counter for number of times we hit the CW lock cancellation hack !*** MODULE SWISDEF *** ! + ! DEFINITION OF SWIS Data Structure ! - literal SWIS$M_HWPCB_MASK = %X'FF'; literal SWIS$M_ASTEN = %X'F'; literal SWIS$M_ASTSR = %X'F0'; literal SWIS$M_DISABLE_LOG = %X'1'; literal SWIS$M_INHIBIT_LOG = %X'2'; literal SWIS$M_ENABLE_REG_TEST = %X'4'; literal SWIS$M_REG_ERROR_DETECTED = %X'8'; literal SWIS$M_VIRTUAL_MACHINE = %X'10'; literal SWIS$K_CPU_BC_1_LENGTH = 328; literal SWIS$K_CPU_BC_2_LENGTH = 72; literal SWIS$S_SWIS = 4096; macro SWIS$PQ_CUR_KSP = 0,0,0,1 %; literal SWIS$S_CUR_KSP = 8; ! KSP stored here when process current, not using KSP macro SWIS$PQ_CUR_ESP = 8,0,0,1 %; literal SWIS$S_CUR_ESP = 8; ! ESP stored here when process current, not in exec mode macro SWIS$PQ_CUR_SSP = 16,0,0,1 %; literal SWIS$S_CUR_SSP = 8; ! SSP stored here when process current, not in super mode macro SWIS$PQ_CUR_USP = 24,0,0,1 %; literal SWIS$S_CUR_USP = 8; ! USP stored here when process current, not in user mode macro SWIS$PQ_CUR_KBSP = 32,0,0,1 %; literal SWIS$S_CUR_KBSP = 8; ! KBSP stored here when process current, not in kernel mode macro SWIS$PQ_CUR_EBSP = 40,0,0,1 %; literal SWIS$S_CUR_EBSP = 8; ! EBSP stored here when process current, not in exec mode macro SWIS$PQ_CUR_SBSP = 48,0,0,1 %; literal SWIS$S_CUR_SBSP = 8; ! SBSP stored here when process current, not in super mode macro SWIS$PQ_CUR_UBSP = 56,0,0,1 %; literal SWIS$S_CUR_UBSP = 8; ! UBSP stored here when process current, not in user mode macro SWIS$PQ_IDT = 64,0,0,1 %; literal SWIS$S_IDT = 8; ! Interruption dispatch table macro SWIS$L_SISR = 72,0,32,0 %; ! SISR macro SWIS$Q_ASTSR_ASTEN = 80,0,0,0 %; literal SWIS$S_ASTSR_ASTEN = 8; ! ASTSR and ASTEN (quadword because of previous use) macro SWIS$V_SWIS_ASTSR_ASTEN = 80,0,8,0 %; literal SWIS$S_SWIS_ASTSR_ASTEN = 8; ! ASTSR and ASTEN macro SWIS$V_HWPCB_MASK = 80,0,8,0 %; literal SWIS$S_HWPCB_MASK = 8; ! To be removed when we get it out of code. macro SWIS$V_ASTEN = 80,0,4,0 %; literal SWIS$S_ASTEN = 4; ! AST Enable Register macro SWIS$V_ASTSR = 80,4,4,0 %; literal SWIS$S_ASTSR = 4; ! AST Pending Summary Register macro SWIS$L_IPL = 88,0,32,0 %; macro SWIS$L_PREVMODE = 92,0,32,0 %; macro SWIS$L_CURSTACKMODE = 96,0,32,0 %; macro SWIS$L_INTERRUPT_DEPTH = 100,0,32,0 %; macro SWIS$L_KT_ID = 104,0,32,0 %; macro SWIS$L_FLAGS = 108,0,32,1 %; macro SWIS$V_DISABLE_LOG = 108,0,1,0 %; macro SWIS$V_INHIBIT_LOG = 108,1,1,0 %; macro SWIS$V_ENABLE_REG_TEST = 108,2,1,0 %; macro SWIS$V_REG_ERROR_DETECTED = 108,3,1,0 %; macro SWIS$V_VIRTUAL_MACHINE = 108,4,1,0 %; ! This should get same value as exe$v_virtual_machine macro SWIS$Q_PSR_SET_MASK = 112,0,0,0 %; literal SWIS$S_PSR_SET_MASK = 8; ! PSR set template mask macro SWIS$Q_PSR_CLEAR_MASK = 120,0,0,0 %; literal SWIS$S_PSR_CLEAR_MASK = 8; ! PSR clear template mask macro SWIS$Q_CPUID = 128,0,0,0 %; literal SWIS$S_CPUID = 8; ! Current CPU Id macro SWIS$PQ_HWPCB_VA = 136,0,0,1 %; literal SWIS$S_HWPCB_VA = 8; ! pointer to HWPCB ! pad to next 256 byte boundary macro SWIS$Q_SCRATCH = 256,0,0,0 %; literal SWIS$S_SCRATCH = 128; macro SWIS$L_GH_PS = 384,0,0,0 %; literal SWIS$S_GH_PS = 64; ! GH to PS conversions macro SWIS$Q_VPTB = 448,0,0,0 %; literal SWIS$S_VPTB = 128; ! Virtual page table bases macro SWIS$Q_PPN_MASK = 576,0,0,0 %; literal SWIS$S_PPN_MASK = 8; ! Physical page mask (takes PA bits into account) ! - Used in DTLB miss handlers for I/O space only macro SWIS$Q_PT_PA = 584,0,0,0 %; literal SWIS$S_PT_PA = 128; ! Level 1 page table base physical addresses ! - Used by nested TLB miss handler only ! pad to next 128 byte boundary macro SWIS$Q_VHPTFLT = 768,0,0,0 %; literal SWIS$S_VHPTFLT = 8; ! Count of VHPTFLT faults macro SWIS$Q_ITLBFLT = 776,0,0,0 %; literal SWIS$S_ITLBFLT = 8; ! Count of ITLBFLT faults macro SWIS$Q_DTLBFLT = 784,0,0,0 %; literal SWIS$S_DTLBFLT = 8; ! Count of DTLBFLT faults macro SWIS$Q_ALTITLBFLT = 792,0,0,0 %; literal SWIS$S_ALTITLBFLT = 8; ! Count of ALTITLBFLT faults macro SWIS$Q_ALTDTLBFLT = 800,0,0,0 %; literal SWIS$S_ALTDTLBFLT = 8; ! Count of ALTDTLBFLT faults macro SWIS$Q_NESTEDTLBFLT = 808,0,0,0 %; literal SWIS$S_NESTEDTLBFLT = 8; ! Count of NESTEDTLBFLT faults macro SWIS$Q_SPECLNFLT = 816,0,0,0 %; literal SWIS$S_SPECLNFLT = 8; ! Count of SPECLNFLT faults macro SWIS$Q_ITNVFLT = 824,0,0,0 %; literal SWIS$S_ITNVFLT = 8; ! Count of *ITLBFLT -> TNV faults macro SWIS$Q_DTNVFLT = 832,0,0,0 %; literal SWIS$S_DTNVFLT = 8; ! Count of *DTLBFLT -> TNV faults ! pad to next 128 byte boundary macro SWIS$Q_KNV_GOOD_SP = 896,0,0,0 %; literal SWIS$S_KNV_GOOD_SP = 8; ! Here is where we get an SP to use when we get a KSTINV macro SWIS$Q_KNV_GOOD_BSP = 904,0,0,0 %; literal SWIS$S_KNV_GOOD_BSP = 8; ! Here is where we get a BSP to use when we get a KSTINV macro SWIS$Q_KNV_TRAP_TYPE = 912,0,0,0 %; literal SWIS$S_KNV_TRAP_TYPE = 8; ! Trap type we entered with when KSTINV detected macro SWIS$Q_KNV_BSPSTORE = 920,0,0,0 %; literal SWIS$S_KNV_BSPSTORE = 8; ! BSPSTORE at the time of the KSTINV macro SWIS$Q_KNV_KSP = 928,0,0,0 %; literal SWIS$S_KNV_KSP = 8; ! SP at the time of the KSTINV macro SWIS$Q_KNV_IPR_KSP = 936,0,0,0 %; literal SWIS$S_KNV_IPR_KSP = 8; ! The internal processor register for KSP at the time of KSTINV macro SWIS$Q_KNV_IPR_KBSP = 944,0,0,0 %; literal SWIS$S_KNV_IPR_KBSP = 8; ! The internal processor register for KBSP at the time of KSTINV macro SWIS$Q_KNV_COUNT = 952,0,0,0 %; literal SWIS$S_KNV_COUNT = 8; ! Count to detect recursive KSTINV macro SWIS$Q_SLOT_VA = 960,0,0,0 %; literal SWIS$S_SLOT_VA = 8; ! A pointer to the CPU slot macro SWIS$Q_CPUDB_VA = 968,0,0,0 %; literal SWIS$S_CPUDB_VA = 8; ! A pointer to the CPUDB for this CPU macro SWIS$Q_NEXT_TIMER = 976,0,0,0 %; literal SWIS$S_NEXT_TIMER = 8; macro SWIS$Q_INTR_FLAG = 984,0,0,0 %; literal SWIS$S_INTR_FLAG = 8; ! Used only by AMOVRR, AMOVRM, RS macro SWIS$Q_RSE_ERROR_COUNT = 992,0,0,0 %; literal SWIS$S_RSE_ERROR_COUNT = 8; macro SWIS$Q_RSE_PHYS_SIZE = 1000,0,0,0 %; literal SWIS$S_RSE_PHYS_SIZE = 8; ! How many physical registers in the RSE? macro SWIS$PQ_VHPT_VA = 1008,0,0,1 %; literal SWIS$S_VHPT_VA = 8; ! VA of VHPT for this CPU macro SWIS$L_VHPT_TRS = 1016,0,32,1 %; ! Number of TRs used for VHPT macro SWIS$L_VHPT_PS = 1020,0,32,1 %; ! Pagesize used for VHPT ! pad to next 512 byte boundary macro SWIS$IQ_SCRATCH_HWPCB = 1024,0,0,1 %; literal SWIS$S_SCRATCH_HWPCB = 512; ! Scratch area at least the size of a HWPCB ! Note: HWPCB defined in HWRPBDEF.SDL macro SWIS$Q_LOW_LEVEL_TRACE = 1536,0,0,1 %; literal SWIS$S_LOW_LEVEL_TRACE = 2560; literal SWIS$K_LENGTH = 4096; literal SWIS$C_LENGTH = 4096; literal SWIS$C_PAGE_SIZE = 4096; ! Map with 4KB page size !*** MODULE $CRABDEF *** literal CRAB$K_LENGTH = 112; ! Length of base structure (not including allocation array) literal CRAB$S_CRAB = 120; macro CRAB$L_FLINK = 0,0,32,1 %; ! Forward link macro CRAB$L_BLINK = 4,0,32,1 %; ! Backward link macro CRAB$W_SIZE = 8,0,16,0 %; ! Structure size in bytes macro CRAB$B_TYPE = 10,0,8,0 %; ! Structure type macro CRAB$B_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro CRAB$L_SPINLOCK = 12,0,32,1 %; ! Address of dynamic spinlock macro CRAB$L_WQFL = 16,0,32,1 %; ! Wait queue flink--points to links in CRCTX macro CRAB$L_WQBL = 20,0,32,1 %; ! Wait queue blink macro CRAB$PS_ADP = 24,0,32,1 %; ! Address of ADP macro CRAB$L_TOTAL_ITEMS = 28,0,32,0 %; ! Total number of items macro CRAB$L_ALLOC_GRAN_MASK = 32,0,32,0 %; ! Allocation granularity mask macro CRAB$L_NOSYNC_SPINLOCK = 36,0,32,1 %; ! Address of dynamic spinlock macro CRAB$PS_DEALLOC_CB = 40,0,32,1 %; ! Points to a callback routine for dealloc_cnt_Res macro CRAB$PS_RINGBUFFER = 44,0,32,1 %; ! Pointer to a CRCTX debug ring buffer ! base item number managed by macro CRAB$L_BASE_ITEM = 48,0,32,0 %; ! this crab macro CRAB$L_VALID_DESC_CNT = 52,0,32,0 %; ! Count of valid descriptors macro CRAB$L_INSFMAPREG_CNT = 56,0,32,0 %; ! X-13a Number of SS$_INSFMAPREG failures macro CRAB$R_SPARE_UNION = 60,0,32,0 %; literal CRAB$S_SPARE_UNION = 4; ! X-13b Spare field for debug macro CRAB$PS_SPARE = 60,0,32,1 %; macro CRAB$L_SPARE = 60,0,32,1 %; macro CRAB$L_FQFL = 64,0,32,1 %; ! FORK QUEUE FORWARD LINK macro CRAB$L_FQBL = 68,0,32,1 %; ! FORK QUEUE BACKWARD LINK macro CRAB$W_FSIZE = 72,0,16,0 %; ! SIZE OF FKB IN BYTES macro CRAB$B_FTYPE = 74,0,8,0 %; ! STRUCTURE TYPE OF FKB macro CRAB$B_FLCK = 75,0,8,0 %; ! FORK LOCK NUMBER macro CRAB$L_FPC = 76,0,32,1 %; ! FORK PC macro CRAB$Q_FR3 = 80,0,0,1 %; literal CRAB$S_FR3 = 8; ! FORK R3 macro CRAB$Q_FR4 = 88,0,0,1 %; literal CRAB$S_FR4 = 8; ! FORK R4 macro CRAB$L_ALLOC_ARRAY = 112,0,32,0 %; ! Start of Allocation array literal CRAB_ARRAY$S_CRAB_ARRAY = 8; macro CRAB_ARRAY$L_NUM = 0,0,32,0 %; ! Starting item number macro CRAB_ARRAY$L_CNT = 4,0,32,0 %; ! Item count literal CRAB_ARRAY$K_LENGTH = 8; ! Length of CRAB array entry !*** MODULE $CWPSDEF *** ! + ! cwpssrv - Common service structure header ! ! All cwpsxxx$ packets contain the following header information. ! ! Fields marked with ++ must be filled/zeroed by service-specific ! routines (at least for pcntrl services) ! ! - ! ! The CWPSSRV$ structure is exchanged with remote nodes. Any updates to this ! structure must take mixed-version operation into account. ! literal cwpssrv$m_btx_done = %X'1'; literal cwpssrv$m_sec_class = %X'1'; literal cwpssrv$m_jpibuf = %X'2'; literal cwpssrv$m_noquota = %X'4'; literal cwpssrv$m_group_priv = %X'8'; literal cwpssrv$m_world_priv = %X'10'; literal cwpssrv$m_secaudit = %X'20'; literal cwpssrv$m_noaudit = %X'40'; literal cwpssrv$m_oper_priv = %X'80'; literal cwpssrv$k_retry_cnt = 5; ! five retries is about ! 4½ seconds literal cwpssrv$k_length = 112; ! length of data structure common literal cwpssrv$k_srvcode_begin = 0; ! - marker for beginning of codes literal cwpssrv$k_canwak = 1; ! $CANWAK service literal cwpssrv$k_delprc = 2; ! $DELPRC service literal cwpssrv$k_forcex = 3; ! $FORCEX service literal cwpssrv$k_resume = 4; ! $RESUME service literal cwpssrv$k_schdwk = 5; ! $SCHDWK service literal cwpssrv$k_setpri = 6; ! $SETPRI service literal cwpssrv$k_suspnd = 7; ! $SUSPND service literal cwpssrv$k_wake = 8; ! $WAKE service literal cwpssrv$k_srvcode_end = 9; ! - marker for end of SRV codes ! CWPS subtypes for other services literal cwpssrv$k_getjpi = 20; ! $GETJPI service literal cwpssrv$k_creprc = 21; ! $CREPRC service literal cwpssrv$k_termin = 22; ! process termination message ! CWPS subtypes for security service codes literal cwpssrv$k_grantid = 28; ! $GRANTID service literal cwpssrv$k_revokid = 29; ! $WAKE service literal cwpssrv$k_version_1 = 1; ! initial version literal cwpssrv$k_version_2 = 2; literal cwpssrv$k_version_3 = 3; literal cwpssrv$k_version_4 = 4; literal cwpssrv$k_version_5 = 5; literal cwpssrv$k_version_6 = 6; literal cwpssrv$k_version_7 = 7; literal cwpssrv$k_version_8 = 8; literal cwpssrv$k_version_9 = 9; literal cwpssrv$k_version_10 = 10; literal cwpssrv$k_version_11 = 11; literal cwpssrv$k_version_12 = 12; literal cwpssrv$k_initial_maj_vers = 1; literal cwpssrv$k_initial_min_vers = 1; literal cwpssrv$s_$cwpssrvdef = 112; literal cwpssrv$S_cwpssrv = 112; macro cwpssrv$l_send_length = 0,0,32,0 %; ! length sent to partner macro cwpssrv$l_return_length = 4,0,32,0 %; ! length returned from partner macro cwpssrv$w_size = 8,0,16,0 %; ! size of structure ++ macro cwpssrv$b_type = 10,0,8,0 %; ! structure type code ++ macro cwpssrv$b_subtype = 11,0,8,0 %; ! structure subtype and service code ++ macro cwpssrv$w_btx_status = 12,0,16,0 %; ! status of block transfer request macro cwpssrv$b_btx_flags = 14,0,8,0 %; ! state of block transfer macro cwpssrv$v_btx_done = 14,0,1,0 %; ! block transfer is complete macro cwpssrv$b_func = 15,0,8,0 %; ! CLSMSG request function code macro cwpssrv$w_srv_maj_vers = 16,0,16,0 %; ! incompatible version formats macro cwpssrv$w_srv_min_vers = 18,0,16,0 %; ! upwards compatible extensions macro cwpssrv$w_ext_maj_vers = 20,0,16,0 %; ! incompatible version formats macro cwpssrv$w_ext_min_vers = 22,0,16,0 %; ! upwards compatible extensions macro cwpssrv$l_status = 24,0,32,0 %; ! status from remote service macro cwpssrv$l_bxfr_status = 28,0,32,0 %; ! status from block transfer macro cwpssrv$l_maximum_length = 32,0,32,0 %; ! maximum possible return length macro cwpssrv$l_flags = 36,0,32,0 %; ! longword of flags macro cwpssrv$v_sec_class = 36,0,1,0 %; ! sec class present... macro cwpssrv$v_jpibuf = 36,1,1,0 %; ! jpi requests buffered macro cwpssrv$v_noquota = 36,2,1,0 %; ! quota has not been charged macro cwpssrv$v_group_priv = 36,3,1,0 %; ! requestor running image with GROUP privilege macro cwpssrv$v_world_priv = 36,4,1,0 %; ! requestor running image with WORLD privilege macro cwpssrv$v_secaudit = 36,5,1,0 %; ! requestor running with mandatory process auditing macro cwpssrv$v_noaudit = 36,6,1,0 %; ! requestor is part of TCB macro cwpssrv$v_oper_priv = 36,7,1,0 %; ! requestor has OPER privilege macro cwpssrv$l_ext_offset = 40,0,32,0 %; ! offset to service-specific extension macro cwpssrv$a_post_routine = 44,0,32,0 %; ! address of post-processing routine ++ macro cwpssrv$l_rqstr_csid = 48,0,32,0 %; ! CSID of the requestor's node macro cwpssrv$l_rqstr_pid = 52,0,32,0 %; ! IPID of the requestor macro cwpssrv$l_rqstr_epid = 56,0,32,0 %; ! EPID of the requestor macro cwpssrv$l_rqstr_imgcnt = 60,0,32,0 %; ! image count of requestor macro cwpssrv$l_rqstr_rightslen = 64,0,32,0 %; ! length of process rights info macro cwpssrv$l_rqstr_rightsoff = 68,0,32,0 %; ! offset to start of rights info macro cwpssrv$l_rqstr_pidadr = 72,0,32,1 %; ! original pid address from user macro cwpssrv$l_partner_csid = 76,0,32,0 %; ! CSID of the partner node macro cwpssrv$l_sought_epid = 80,0,32,0 %; ! epid for target process macro cwpssrv$l_return_epid = 84,0,32,0 %; ! actual epid from target process macro cwpssrv$w_prcnamlen = 88,0,16,0 %; ! length of target process name macro cwpssrv$w_prcnamoff = 90,0,16,0 %; ! offset to start of target process name macro cwpssrv$l_free_offset = 92,0,32,0 %; ! offset to free data area macro cwpssrv$l_spare1 = 96,0,32,0 %; ! zero if unused macro cwpssrv$w_spare2 = 100,0,16,0 %; ! zero if unused macro cwpssrv$b_spare3 = 102,0,8,0 %; ! zero if unused macro cwpssrv$b_retries_left = 103,0,8,0 %; ! number of retries remaining macro cwpssrv$q_time = 104,0,0,0 %; literal cwpssrv$s_time = 8; ! time structure allocated literal cwps$_enabled = 1; ! assemble the code literal cwps$_nervous = 0; ! do reasonable checking literal cwps$_scared = 0; ! do a lot of consistency checking literal cwps$_paranoid = 0; ! do excessive checking literal cwps$_statistics = 1; ! collect statistics literal cwpscan$k_length = 0; ! length of $CANWAK literal cwpsres$k_length = 0; ! length of $RESUME literal cwpssus$k_length = 0; ! length of $SUSPND literal cwpswak$k_length = 0; ! length of $WAKE ! ! The CWPSDEL$ structure is exchanged with remote nodes. Any updates ! to this structure must take mixed-version operation into account. ! Sender stores delprc flags argument (longword) in flags extension. literal cwpsdel$k_length = 4; ! length of data structure literal cwpsdel$s_$cwpsdeldef = 4; ! Old size name - synonym literal cwpsdel$S_cwpsdel = 4; macro cwpsdel$l_flags = 0,0,32,0 %; ! flags to pass to remote literal cwpssrv$k_delprc_ext_min_vers = 2; ! ! The CWPSFEX$ structure is exchanged with remote nodes. Any updates to this ! structure must take mixed-version operation into account. ! literal cwpsfex$k_length = 4; ! length of data structure literal cwpsfex$s_$cwpsfexdef = 4; ! Old size name - synonym literal cwpsfex$S_cwpsfex = 4; macro cwpsfex$l_code = 0,0,32,0 %; ! code to pass to remote ! Version # of 6-cell SETPRI extension literal cwpssrv$k_setpri_min_vers2 = 2; ! ! The CWPSPRI$ structure is exchanged with remote nodes. Any updates to this ! structure must take mixed-version operation into account. ! literal cwpspri$k_length = 24; ! length of data structure literal cwpspri$s_$cwpspridef = 24; ! Old size name - synonym literal cwpspri$S_cwpspri = 24; macro cwpspri$l_user_prvpri = 0,0,32,1 %; ! address of user's prvpri cell macro cwpspri$l_pri = 4,0,32,0 %; ! priority we send to remote macro cwpspri$l_prvpri = 8,0,32,0 %; ! priority we receive from remote macro cwpspri$l_user_prvpol = 12,0,32,1 %; ! address of user's prvpol cell macro cwpspri$l_pol = 16,0,32,0 %; ! policy we send to remote (or -1) macro cwpspri$l_prvpol = 20,0,32,0 %; ! prev policy we receive from remote ! ! The CWPSSWK$ structure is exchanged with remote nodes. Any updates to this ! structure must take mixed-version operation into account. ! literal cwpsswk$k_length = 16; ! length of data structure literal cwpsswk$s_$cwpsswkdef = 16; ! Old size name - synonym literal cwpsswk$S_cwpsswk = 16; macro cwpsswk$q_daytim = 0,0,0,0 %; literal cwpsswk$s_daytim = 8; ! time to wake up macro cwpsswk$q_reptim = 8,0,0,0 %; literal cwpsswk$s_reptim = 8; ! time to repeat wake up ! ! The CWPSJPI$ structure is exchanged with remote nodes. Any updates to this ! structure must take mixed-version operation into account. ! literal cwpsjpi$k_length = 60; ! length of data structure literal cwpsjpi$s_$cwpsjpidef = 60; ! Old size name - synonym literal cwpsjpi$S_cwpsjpi = 60; macro cwpsjpi$l_pscan_off = 0,0,32,0 %; ! offset to start of pscanctx macro cwpsjpi$l_itmoff = 4,0,32,0 %; ! offset to item list in structure macro cwpsjpi$l_bufoff = 8,0,32,0 %; ! offset to return buffer macro cwpsjpi$l_vecoff = 12,0,32,0 %; ! offset to vector for item addr macro cwpsjpi$l_acboff = 16,0,32,0 %; ! offset to acb structure macro cwpsjpi$l_itmlst = 20,0,32,1 %; ! address of original item list macro cwpsjpi$l_buflen = 24,0,32,0 %; ! length of user's buffers macro cwpsjpi$l_iosbadr = 28,0,32,1 %; ! user's I/O status address macro cwpsjpi$q_iosb = 32,0,0,0 %; literal cwpsjpi$s_iosb = 8; ! return iosb contents macro cwpsjpi$l_astadr = 40,0,32,1 %; ! AST address macro cwpsjpi$l_astprm = 44,0,32,0 %; ! AST parameter macro cwpsjpi$l_pscanctx_addr = 48,0,32,1 %; ! PSCANCTX record address macro cwpsjpi$w_pscan_seqnum = 52,0,16,0 %; ! sequence number of PSCANCTX macro cwpsjpi$b_efn = 54,0,8,0 %; ! event flag to set macro cwpsjpi$b_acmode = 55,0,8,0 %; ! access mode of original call macro cwpsjpi$w_ctlflags = 56,0,16,0 %; ! JPI$_GETJPI_CONTROL_FLAGS bits macro cwpsjpi$w_spare0 = 58,0,16,0 %; ! spare, align literal cwpsjpi_64$k_length = 40; ! length of data structure literal cwpsjpi_64$S_cwpsjpi_64 = 40; macro cwpsjpi_64$pq_rqstr_pidadr = 0,0,0,1 %; literal cwpsjpi_64$s_rqstr_pidadr = 8; ! user's address for PID argument: cwpssrv$l_rqstr_pid for $GETJPI will be -1. macro cwpsjpi_64$pq_itmlst = 8,0,0,1 %; literal cwpsjpi_64$s_itmlst = 8; ! user's item list address: cwpsjpi$l_itmlst for $GETJPI will be -1. macro cwpsjpi_64$pq_iosbadr = 16,0,0,1 %; literal cwpsjpi_64$s_iosbadr = 8; ! user's IOSB address: cwpsjpi$l_iosbadr for $GETJPI will be -1. macro cwpsjpi_64$pq_astadr = 24,0,0,1 %; literal cwpsjpi_64$s_astadr = 8; ! user's AST address: cwpsjpi$l_astadr will be -1. macro cwpsjpi_64$pq_astprm = 32,0,0,1 %; literal cwpsjpi_64$s_astprm = 8; ! user's AST parameter: cwpsjpi$l_astprm will be -1. ! ! The CWPSCRE$ structure is exchanged with remote nodes. Any updates to this ! structure must take mixed-version operation into account. ! literal cwpscre$M_IMGDMP = %X'1'; literal cwpscre$M_DEBUG = %X'2'; literal cwpscre$M_DBGTRU = %X'4'; literal cwpscre$M_PARSE_EXTENDED = %X'8'; literal cwpscre$M_CASE_SENSITIVE = %X'10'; literal cwpscre$k_length = 2100; ! length of data structure literal cwpscre$s_$cwpscredef = 2100; ! Old size name - synonym literal cwpscre$S_cwpscreprc = 2100; macro cwpscre$L_BASE_OFFSET = 0,0,32,0 %; ! Offset of CWPSCRE from CWPSSRV base macro cwpscre$L_ACBOFF = 4,0,32,0 %; ! Offset of embedded ACB from CWPSCRE macro cwpscre$Q_PRVMSK = 8,0,0,0 %; literal cwpscre$S_PRVMSK = 8; ! Privileges of new process macro cwpscre$Q_IOSB = 16,0,0,0 %; literal cwpscre$S_IOSB = 8; ! Transaction status block macro cwpscre$L_PRIORITY = 24,0,32,0 %; ! Priority of new process macro cwpscre$L_UIC = 28,0,32,0 %; ! UIC of new process macro cwpscre$L_DEFPROT = 32,0,32,0 %; ! Default protection of new process macro cwpscre$L_TMBU = 36,0,32,0 %; ! Termination MB unit number of creator macro cwpscre$l_spare1 = 40,0,32,0 %; ! zero if unused macro cwpscre$l_spare2 = 44,0,32,0 %; ! zero if unused macro cwpscre$W_MAXJOBS = 48,0,16,0 %; ! Maximum jobs limit macro cwpscre$W_MAXDETACH = 50,0,16,0 %; ! Maximum detached jobs limit macro cwpscre$L_ASTLM = 52,0,32,0 %; ! AST LIMIT macro cwpscre$L_BIOLM = 56,0,32,0 %; ! BUFFERED I/O LIMIT macro cwpscre$L_BYTLM = 60,0,32,0 %; ! BUFFERED I/O LIMIT macro cwpscre$L_CPULM = 64,0,32,0 %; ! CPU TIME LIMIT macro cwpscre$L_DIOLM = 68,0,32,0 %; ! DIRECT I/O LIMIT macro cwpscre$L_FILLM = 72,0,32,0 %; ! OPEN FILE LIMIT macro cwpscre$L_PGFLQUOTA = 76,0,32,0 %; ! PAGING FILE QUOTA macro cwpscre$L_PRCLM = 80,0,32,0 %; ! SUB-PROCESS LIMIT macro cwpscre$L_TQELM = 84,0,32,0 %; ! TIMER QUEUE ENTRY LIMIT macro cwpscre$L_WSQUOTA = 88,0,32,0 %; ! WORKING SET QUOTA macro cwpscre$L_WSDEFAULT = 92,0,32,0 %; ! WORKING SET DEFAULT macro cwpscre$L_ENQLM = 96,0,32,0 %; ! ENQUEUE LIMIT macro cwpscre$L_WSEXTENT = 100,0,32,0 %; ! MAXIMUM WORKING SET SIZE macro cwpscre$L_JTQUOTA = 104,0,32,0 %; ! JOB-WIDE LOGICAL NAME TABLE CREATION QUOTA macro cwpscre$L_SPARE_QUOTA1 = 108,0,32,0 %; ! Spare field in case a new quota is added macro cwpscre$L_SPARE_QUOTA2 = 112,0,32,0 %; ! Spare field in case a new quota is added macro cwpscre$L_INPUT_ATT = 116,0,32,0 %; ! SYS$INPUT attributes macro cwpscre$L_OUTPUT_ATT = 120,0,32,0 %; ! SYS$OUTPUT attributes macro cwpscre$L_ERROR_ATT = 124,0,32,0 %; ! SYS$ERROR attributes macro cwpscre$L_MSGMASK = 128,0,32,0 %; ! MESSAGE FLAGS macro cwpscre$L_UAF_FLAGS = 132,0,32,0 %; ! FLAGS FROM UAF RECORD macro cwpscre$L_CREPRC_FLAGS = 136,0,32,0 %; ! Copy of $CREPRC status flags macro cwpscre$L_FLAGS = 140,0,32,0 %; ! Miscellaneous flags for PQB macro cwpscre$V_IMGDMP = 140,0,1,0 %; ! TAKE IMAGE DUMP ON SERIOUS ERROR macro cwpscre$V_DEBUG = 140,1,1,0 %; ! /DEBUG startup desired macro cwpscre$V_DBGTRU = 140,2,1,0 %; ! debugger present macro cwpscre$V_PARSE_EXTENDED = 140,3,1,0 %; ! Use PARSE_STYLE = EXTENDED macro cwpscre$V_CASE_SENSITIVE = 140,4,1,0 %; ! Use CASE_LOOKUP = SENSITIVE macro cwpscre$T_INPUT = 144,0,0,0 %; literal cwpscre$S_INPUT = 256; ! LOGICAL NAME FOR INPUT macro cwpscre$T_OUTPUT = 400,0,0,0 %; literal cwpscre$S_OUTPUT = 256; ! LOGICAL NAME FOR OUTPUT macro cwpscre$T_ERROR = 656,0,0,0 %; literal cwpscre$S_ERROR = 256; ! LOGICAL NAME FOR ERROR OUTPUT macro cwpscre$T_DISK = 912,0,0,0 %; literal cwpscre$S_DISK = 256; ! LOGICAL NAME FOR SYS$DISK macro cwpscre$T_IMAGE = 1168,0,0,0 %; literal cwpscre$S_IMAGE = 256; ! IMAGE NAME FOR NEW PROCESS macro cwpscre$T_DDSTRING = 1424,0,0,0 %; literal cwpscre$S_DDSTRING = 256; ! DEFAULT DIRECTORY STRING macro cwpscre$T_USERNAME = 1680,0,0,0 %; literal cwpscre$S_USERNAME = 12; ! User name of new process for JIB macro cwpscre$T_ACCOUNT = 1692,0,0,0 %; literal cwpscre$S_ACCOUNT = 8; ! Account name of new process for JIB macro cwpscre$T_PQB_ACCOUNT = 1700,0,0,0 %; literal cwpscre$S_PQB_ACCOUNT = 8; ! Account name for new process for PQB macro cwpscre$R_MIN_CLASS = 1708,0,0,0 %; literal cwpscre$S_MIN_CLASS = 20; ! MINIMUM AUTHORIZED SECURITY CLEARANCE macro cwpscre$R_MAX_CLASS = 1728,0,0,0 %; literal cwpscre$S_MAX_CLASS = 20; ! MAXIMUM AUTHORIZED SECURITY CLEARANCE macro cwpscre$T_CLI_NAME = 1748,0,0,0 %; literal cwpscre$S_CLI_NAME = 32; ! CLI name macro cwpscre$T_CLI_TABLE = 1780,0,0,0 %; literal cwpscre$S_CLI_TABLE = 32; ! CLI table name macro cwpscre$T_SPAWN_CLI = 1812,0,0,0 %; literal cwpscre$S_SPAWN_CLI = 32; ! Spawn CLI name macro cwpscre$T_SPAWN_TABLE = 1844,0,0,0 %; literal cwpscre$S_SPAWN_TABLE = 256; ! Spawn CLI table name ! ! The CWPSTERM$ structure is exchanged with remote nodes. Any updates to this ! structure must take mixed-version operation into account. ! literal cwpsterm$k_length = 108; ! length of data structure literal cwpsterm$s_$cwpstermdef = 108; ! Old size name - synonym literal cwpsterm$S_cwpsterm = 108; macro cwpsterm$L_BASE_OFFSET = 0,0,32,0 %; ! Offset of CWPSTERM from CWPSSRV base macro cwpsterm$L_ACBOFF = 4,0,32,0 %; ! Offset of embedded ACB from CWPSTERM macro cwpsterm$Q_IOSB = 8,0,0,0 %; literal cwpsterm$S_IOSB = 8; ! Transaction status block macro cwpsterm$L_DELETED_PROC_EPID = 16,0,32,0 %; ! EPID of process whose termination message this is macro cwpsterm$L_SPARE = 20,0,32,0 %; ! Spare field macro cwpsterm$T_TERM_MSG = 24,0,0,0 %; literal cwpsterm$S_TERM_MSG = 84; ! termination message ! ! The CWPSVEC$ structure is a local structure. If modified, you do not need ! to take mixed-version operation into account, however you must be sure that ! all modules and images which reference the structure are updated together. ! Code that utilizes this structure assumes it resides at a quadword-aligned ! VA. The structure must always contain an integral number of quadwords. ! literal cwpsvec$M_64_bit_ile = %X'1'; literal cwpsvec$k_length = 24; ! length of data structure literal cwpsvec$s_$cwpsvecdef = 24; ! Old size name - synonym literal cwpsvec$S_cwpsvec = 24; macro cwpsvec$pq_usr_bufadr = 0,0,0,1 %; literal cwpsvec$s_usr_bufadr = 8; ! user's address for buffer items macro cwpsvec$pq_usr_lenadr = 8,0,0,1 %; literal cwpsvec$s_usr_lenadr = 8; ! user's address for returned length macro cwpsvec$l_flags = 16,0,32,0 %; macro cwpsvec$V_64_bit_ile = 16,0,1,0 %; ! ! The CWPSACB$ structure is a local structure. If modified, you do not need ! to take mixed-version operation into account, however you must be sure that ! all modules and images which reference the structure are updated together. ! literal cwpsacb$k_acb_length = 36; ! length of embedded block literal cwpsacb$k_length = 92; ! length of data structure (less PCB) literal cwpsacb$S_$cwpsacbdef = 97; ! Old size name - synonym literal cwpsacb$S_cwpsacb = 97; macro cwpsacb$B_CWPSACB_FKB = 0,0,0,1 %; literal cwpsacb$S_CWPSACB_FKB = 48; macro cwpsacb$l_astqfl = 0,0,32,1 %; ! ast queue forward link macro cwpsacb$l_astqbl = 4,0,32,1 %; ! ast queue backward link macro cwpsacb$w_size = 8,0,16,0 %; ! structure size in bytes macro cwpsacb$b_type = 10,0,8,0 %; ! structure type code macro cwpsacb$b_rmod = 11,0,8,0 %; ! request access mode macro cwpsacb$l_pid = 12,0,32,0 %; ! process id of request macro cwpsacb$l_ast = 16,0,32,1 %; ! ast routine address macro cwpsacb$l_astprm = 20,0,32,0 %; ! ast parameter macro cwpsacb$l_kast = 32,0,32,1 %; ! internal kernel mode xfer address macro cwpsacb$l_bufadr = 48,0,32,1 %; ! address of buffer macro cwpsacb$l_buflen = 52,0,32,0 %; ! length of the buffer macro cwpsacb$l_msgbuf = 56,0,32,1 %; ! message buffer address macro cwpsacb$l_csb = 60,0,32,1 %; ! csb address macro cwpsacb$l_cdrp = 64,0,32,1 %; ! cdrp address macro cwpsacb$l_read_length = 68,0,32,0 %; ! length of bxfr read request macro cwpsacb$l_write_length = 72,0,32,0 %; ! length of bxfr write request macro cwpsacb$l_rightsdesc = 76,0,0,0 %; literal cwpsacb$s_rightsdesc = 8; ! descriptor for rightslist macro cwpsacb$b_func = 84,0,8,0 %; ! function code from message macro cwpsacb$b_spare0 = 85,0,8,0 %; macro cwpsacb$w_spare1 = 86,0,16,0 %; macro cwpsacb$AR_remote_psb = 88,0,32,1 %; ! address of remote process security profile ! trojan PCB should be octaword aligned macro cwpsacb$b_trojan_pcb = 96,0,8,0 %; ! start of false PCB ! ! The CWPSSQH$ structure is a local structure. If modified, you do not need ! to take mixed-version operation into account, however you must be sure that ! all modules and images which reference the structure are updated together. ! literal cwpssqh$k_length = 32; ! length of data structure literal cwpssqh$S_$cwpssqhdef = 32; ! Old size name - synonym literal cwpssqh$S_cwpssqh = 32; macro cwpssqh$l_flink = 0,0,32,1 %; ! forward link macro cwpssqh$l_blink = 4,0,32,1 %; ! back link macro cwpssqh$w_size = 8,0,16,0 %; ! size of structure (SQH only) macro cwpssqh$b_type = 10,0,8,0 %; ! structure type code macro cwpssqh$b_subtype = 11,0,8,0 %; ! structure subtype macro cwpssqh$l_alloc_length = 12,0,32,0 %; ! actual length of allocation macro cwpssqh$l_mpid = 16,0,32,0 %; ! master pid macro cwpssqh$l_spare0 = 20,0,32,0 %; ! enough to make it octaword macro cwpssqh$l_spare1 = 24,0,32,0 %; ! aligned... macro cwpssqh$l_spare3 = 28,0,32,0 %; ! ! The CWPSNODI*$ structures are local structures. If modified, you do not need ! to take mixed-version operation into account, however you must be sure that ! all modules and images which reference the structures are updated together. ! literal cwpsnodih$k_header = 16; ! length of data structure literal cwpsnodih$S_$cwpsnodihdef = 17; ! Old size name - synonym literal cwpsnodih$S_cwpsnodih = 17; macro cwpsnodih$l_flink = 0,0,32,1 %; ! forward link macro cwpsnodih$l_blink = 4,0,32,1 %; ! back link macro cwpsnodih$w_size = 8,0,16,0 %; ! size of structure macro cwpsnodih$b_type = 10,0,8,0 %; ! structure type code macro cwpsnodih$b_subtype = 11,0,8,0 %; ! structure subtype macro cwpsnodih$l_count = 12,0,32,0 %; ! count of nodes macro cwpsnodih$b_node_list = 16,0,8,0 %; ! start of list of node blocks literal cwpsnodi$k_length = 32; ! length of data structure literal cwpsnodi$S_$cwpsnodidef = 32; ! Old size name - synonym literal cwpsnodi$S_cwpsnodi = 32; macro cwpsnodi$l_hwtype = 0,0,32,0 %; ! hardware type (and flink) macro cwpsnodi$w_hw_model = 4,0,16,0 %; ! integer model code macro cwpsnodi$l_csid = 8,0,32,0 %; ! node's csid macro cwpsnodi$b_name = 12,0,0,0 %; literal cwpsnodi$s_name = 16; ! node's name (ASCIC) macro cwpsnodi$l_sb = 28,0,32,1 %; ! sb address !*** MODULE $KPBDEF *** ! + ! KPB - Kernel Process Block ! ! The Kernel Process Block contains the saved registers, state and ! stack pointer for a kernel process. ! ! The KPB consists of 5 areas: ! ! 1 Base, ! 2a Scheduling, ! 2b VMS Special Parameters, ! 3 Spinlock, ! 4 Debug, and ! 5 General Parameters ! ! The KPB can be used in one of two general types: the VMS executive sofware ! type (VEST) and the fully general type (FGT). ! ! In the VEST KPB, the relationship of KPB sections 1 thru 3 are fixed into ! the relationship shown in this structure defintion file. Since the ! relationships between the VEST KPB fields are fixed, all major fields ! can be addressed relative to a single pointer register. This reduces ! the number of indirect reference operations and increases performance. ! The penality for the improved performance is a non-dynamic structure ! format. In VEST KPBs, the Spinlock area is optional. This causes the ! Debug area to be variably located. Typically, VEST KPBs do not use the ! General Parameters area. ! ! In the FGT KPB, only the KPB Base section has the format described in ! this structure definition file. In addition, the KPB VMS Special ! Parameters section is not present in FGT KPBs. Since the KPB Base size ! is fixed, the KPB Scheduling section can be referenced using offsets from ! the KPB base pointer register. All other sections are variable sized, ! and must be referenced through the pointers provided in the KPB Base. ! ! *NB* - The length of each integer numbered area above is rounded to an ! integral number of quadwords. ! ! This module also symbolically defines the flags parameter value calls ! to EXE$KP_ALLOCATE_KPB. ! ! - literal KPBDBG$K_PC_VEC_CNT = 8; ! Size of PC vector literal KPBDBG$S_KPBDBG = 48; macro KPBDBG$IS_START_TIME = 0,0,32,0 %; ! Time of last start/restart macro KPBDBG$IS_START_COUNT = 4,0,32,0 %; ! Count of STARTs macro KPBDBG$IS_RESTART_COUNT = 8,0,32,0 %; ! Count of RESTARTs macro KPBDBG$IS_VEC_INDEX = 12,0,32,0 %; ! PC vector index macro KPBDBG$IS_PC_VEC = 16,0,0,1 %; literal KPBDBG$S_PC_VEC = 32; ! PC trace vector literal KPBDBG$K_LENGTH = 48; ! Length of KPB Debug section literal KPBDBG$S_KPBDBGDEF = 48; ! Old size name, synonym for KPBDBG$S_KPBDBG literal KPBSPL$S_KPBSPL = 40; macro KPBSPL$PS_SPL_STALL_RTN = 0,0,32,1 %; ! Spinlock STALL handling routine pointer macro KPBSPL$PS_SPL_RESTRT_RTN = 4,0,32,1 %; ! Spinlock RESTART handling routine pointer ! X-28 macro KPBSPL$PS_SPL_FORK = 8,0,32,1 %; ! Fork spinlock address macro KPBSPL$PS_SPL_PORT = 12,0,32,1 %; ! Port spinlock address macro KPBSPL$PS_SPL_DYN = 16,0,32,1 %; ! Dynamic spinlock address macro KPBSPL$L_IPL = 20,0,32,1 %; ! IPL of all spinlocks as longword macro KPBSPL$B_IPL = 20,0,8,0 %; ! IPL of all spinlocks as byte ! End IPL union macro KPBSPL$L_SAVED_SPL_CTX = 24,0,32,1 %; ! Re/starter's spinlock context macro KPBSPL$L_ARCHIVED_SPL_CTX = 28,0,32,1 %; ! X-30 Spinlock contexts archived since re/start macro KPBSPL$L_REQ_SPL_CTX = 32,0,32,1 %; ! Requested spinlock context macro KPBSPL$L_FORK_OWN_CNT = 36,0,32,1 %; ! Fork SPL$L_OWN_COUNT on re/start literal KPBSPL$K_LENGTH = 40; ! Length of KPB Spinlock section literal KPBSPL$S_KPBSPLDEF = 40; ! Old size name, synonym for KPBSPL$S_KPBSPL literal KPBSCH$S_KPBSCH = 80; macro KPBSCH$PS_SCH_STALL_RTN = 0,0,32,1 %; ! Scheduling STALL handling routine pointer macro KPBSCH$PS_SCH_RESTRT_RTN = 4,0,32,1 %; ! Scheduling RESTART handling routine pointer macro KPBSCH$PS_FKBLK = 8,0,32,1 %; ! pointer to a fork BLOCK macro KPBSCH$PS_SCH_END_RTN = 12,0,32,1 %; ! Scheduling END handling routine pointer macro KPBSCH$PS_FQFL = 16,0,32,1 %; ! fork queue flink macro KPBSCH$PS_FQBL = 20,0,32,1 %; ! fork queue blink macro KPBSCH$IW_FKB_SIZE = 24,0,16,0 %; ! fork block size macro KPBSCH$IB_FKB_TYPE = 26,0,8,0 %; ! fork block type macro KPBSCH$IB_FLCK = 27,0,8,0 %; ! fork lock macro KPBSCH$PS_FPC = 28,0,32,1 %; ! fork PC macro KPBSCH$Q_FR3 = 32,0,0,1 %; literal KPBSCH$S_FR3 = 8; ! fork R3 macro KPBSCH$Q_FR4 = 40,0,0,1 %; literal KPBSCH$S_FR4 = 8; ! fork R4 macro KPBSCH$PS_TQFL = 16,0,32,1 %; ! timer queue flink macro KPBSCH$PS_TQBL = 20,0,32,1 %; ! timer queue blink macro KPBSCH$IW_TQE_SIZE = 24,0,16,0 %; ! TQE size macro KPBSCH$IB_TQE_TYPE = 26,0,8,0 %; ! TQE type macro KPBSCH$IB_RQTYPE = 27,0,8,0 %; ! timer request type macro KPBSCH$PS_TQE_FPC = 28,0,32,1 %; ! timer routine pointer macro KPBSCH$Q_TQE_FR3 = 32,0,0,1 %; literal KPBSCH$S_TQE_FR3 = 8; ! timer routine R3 macro KPBSCH$Q_TQE_FR4 = 40,0,0,1 %; literal KPBSCH$S_TQE_FR4 = 8; ! timer routine R4 macro KPBSCH$IQ_TIME = 48,0,0,1 %; literal KPBSCH$S_TIME = 8; ! timer due time literal KPBSCH$K_LENGTH = 80; ! Length of KPB Scheduling section literal KPBSCH$S_KPBSCHDEF = 80; ! Old size name, synonym for KPBSCH$S_KPBSCH literal KP$M_VEST = %X'4'; literal KP$M_SPLOCK = %X'20'; literal KP$M_DEBUG = %X'40'; literal KP$M_DEALLOC_AT_END = %X'100'; literal KP$M_SAVE_FP = %X'1000'; literal KP$M_SET_STACK_LIMITS = %X'8000'; literal KP$M_IO = 292; ! The right flags for I/O literal KP$M_LKMGR = 4; ! The right flags for the lock manager literal KP$S_KPFLAGS = 4; macro KP$V_VEST = 0,2,1,0 %; ! KPB VEST format required macro KP$V_SPLOCK = 0,5,1,0 %; ! Spinlock (3) area required macro KP$V_DEBUG = 0,6,1,0 %; ! Debug (4) area present macro KP$V_DEALLOC_AT_END = 0,8,1,0 %; ! KP_END should call KP_DEALLOCATE macro KP$V_SAVE_FP = 0,12,1,0 %; ! Save FP registers on context switch (IA64 only) macro KP$V_SET_STACK_LIMITS = 0,15,1,0 %; ! Call SETSTK_64 on every stack switch literal KP$S_KPDEF = 4; ! Old size name, synonym for KP$S_KPFLAGS literal KP$M_LOCK_MEM_STACK = %X'1'; literal KP$M_LOCK_RSE_STACK = %X'2'; literal KP$m_BOTH_STACKS = 3; literal KP$S_KPLCKFLAGS = 4; macro KP$V_LOCK_MEM_STACK = 0,0,1,0 %; ! Lock main or memory stack macro KP$V_LOCK_RSE_STACK = 0,1,1,0 %; ! Lock RSE stack (IA64) literal KPB$K_MIN_IO_STACK = 49152; ! Minimum I/O stack size in bytes IA64 literal KPB$K_MAX_MPW_STACK = 8192; ! Maximum stack needed for page writes literal KPB$M_VALID = %X'1'; literal KPB$M_ACTIVE = %X'2'; literal KPB$M_VEST = %X'4'; literal KPB$M_DELETING = %X'8'; literal KPB$M_SCHED = %X'10'; literal KPB$M_SPLOCK = %X'20'; literal KPB$M_DEBUG = %X'40'; literal KPB$M_PARAM = %X'80'; literal KPB$M_DEALLOC_AT_END = %X'100'; literal KPB$M_BYPASS_CACHE = %X'200'; literal KPB$M_HLL_MASK = %X'400'; literal KPB$M_RESERVED_CACHE = %X'800'; literal KPB$M_SAVE_FP = %X'1000'; literal KPB$M_MEM_STACK_LOCKED = %X'2000'; literal KPB$M_RSE_STACK_LOCKED = %X'4000'; literal KPB$M_SET_STACK_LIMITS = %X'8000'; literal KPB$M_TQE_WAIT = %X'10000'; literal KPB$M_FORK = %X'20000'; literal KPB$M_FORK_WAIT = %X'40000'; literal KPB$M_SAVED_DEALLOC_AT_END = %X'80000'; literal KPB$M_SPL_CTX = %X'100000'; literal KPB$M_RSVD = %X'3FE00000'; literal KPB$M_ACMODE = %X'C0000000'; literal KPB$M_STALL_CTX_BITS = 458752; literal KPREG$K_MIN_REG_MASK = 738258944; ! Minimum register mask literal KPREG$K_MIN_IO_REG_MASK = 738259004; ! Min I/O register mask literal KPREG$K_ERR_REG_MASK = -738263037; ! Error mask literal KPREG$K_HLL_REG_MASK = 738263036; ! Default HLL mask literal KPB$K_LENGTH = 192; ! Length of KPB base section literal KPB$K_TQE_LENGTH = 64; ! length of TQE block literal KPB$K_NON_VEST_LENGTH = 272; ! End of NON_VEST KPB offsets ! Begin VMS Special Parameters Area literal KPB$K_KEEP = 1; literal KPB$K_RELEASE = 2; literal KPB$K_LOW = 3; literal KPB$K_HIGH = 4; literal KPB$K_SCH_LENGTH = 320; ! Length of KPB + SCH literal KPB$S_KPB = 360; macro KPB$PS_FLINK = 0,0,32,1 %; ! Forward link macro KPB$PS_BLINK = 4,0,32,1 %; ! Backward link macro KPB$IW_SIZE = 8,0,16,0 %; ! Structure size in bytes macro KPB$IB_TYPE = 10,0,8,0 %; ! Structure type macro KPB$IB_SUBTYPE = 11,0,8,0 %; ! Structure subtype macro KPB$IS_STACK_SIZE = 12,0,32,0 %; ! Stack size in bytes macro KPB$IS_FLAGS = 16,0,32,0 %; ! Flags bitmask macro KPB$V_VALID = 16,0,1,0 %; ! KPB is valid macro KPB$V_ACTIVE = 16,1,1,0 %; ! KPB is in active use macro KPB$V_VEST = 16,2,1,0 %; ! KPB is VEST format macro KPB$V_DELETING = 16,3,1,0 %; ! KPB is being deleted macro KPB$V_SCHED = 16,4,1,0 %; ! Scheduling (2) area present macro KPB$V_SPLOCK = 16,5,1,0 %; ! Spinlock (3) area present macro KPB$V_DEBUG = 16,6,1,0 %; ! Debug (4) area present macro KPB$V_PARAM = 16,7,1,0 %; ! Parameter (5) area present macro KPB$V_DEALLOC_AT_END = 16,8,1,0 %; ! KP_END should call KP_DEALLOCATE macro KPB$V_BYPASS_CACHE = 16,9,1,0 %; ! Don't cache KPB on deallocation macro KPB$V_HLL_MASK = 16,10,1,0 %; ! Register mask is HLL_REG_MASK macro KPB$V_RESERVED_CACHE = 16,11,1,0 %; ! Use reserved KPB cache macro KPB$V_SAVE_FP = 16,12,1,0 %; ! Caller requires FP state saved (IA64 only) macro KPB$V_MEM_STACK_LOCKED = 16,13,1,0 %; ! Stack pages locked in WS macro KPB$V_RSE_STACK_LOCKED = 16,14,1,0 %; ! Stack pages locked in WS macro KPB$V_SET_STACK_LIMITS = 16,15,1,0 %; ! Call SETSTK_64 on every stack switch macro KPB$V_TQE_WAIT = 16,16,1,0 %; ! X-28 Stalled by EXE$KP_TQE_WAIT macro KPB$V_FORK = 16,17,1,0 %; ! X-28 Stalled by EXE$KP_FORK macro KPB$V_FORK_WAIT = 16,18,1,0 %; ! X-28 Stalled by EXE$KP_FORK_WAIT macro KPB$V_SAVED_DEALLOC_AT_END = 16,19,1,0 %; ! X-28 Bit saved & cleared to force execution of KPB$PS_SCH_END macro KPB$V_SPL_CTX = 16,20,1,0 %; ! X-28 KPB has been SPL_CTX-initialized macro KPB$V_RSVD = 16,21,9,0 %; literal KPB$S_RSVD = 9; ! Reserved for future flags macro KPB$V_ACMODE = 16,30,2,0 %; literal KPB$S_ACMODE = 2; ! Original mode of KP macro KPB$IS_REG_MASK = 20,0,32,0 %; ! Register save mask macro KPB$PS_SAVED_SP = 24,0,32,1 %; ! Previous stack pointer macro KPB$PQ_SAVED_SP = 24,0,0,1 %; literal KPB$S_SAVED_SP = 8; ! Previous stack pointer macro KPB$PS_STACK_BASE = 32,0,32,1 %; ! Stack base address macro KPB$PQ_STACK_BASE = 32,0,0,1 %; literal KPB$S_STACK_BASE = 8; ! Stack base address macro KPB$PS_STACK_SP = 40,0,32,1 %; ! Current SP macro KPB$PQ_STACK_SP = 40,0,0,1 %; literal KPB$S_STACK_SP = 8; ! Current SP macro KPB$PS_SCH_PTR = 48,0,32,1 %; ! Address of SCH area macro KPB$PS_SPL_PTR = 52,0,32,1 %; ! Address of SPL area macro KPB$PS_DBG_PTR = 56,0,32,1 %; ! Address of DBG area macro KPB$PS_PRM_PTR = 60,0,32,1 %; ! Address of PRM area macro KPB$IS_PRM_LENGTH = 64,0,32,0 %; ! Length of PRM area macro KPB$IS_RSE_STACK_LENGTH = 68,0,32,0 %; ! Size of RSE backing store (bytes) macro KPB$PQ_RSE_STACK_BASE = 72,0,0,1 %; literal KPB$S_RSE_STACK_BASE = 8; ! RSE backing store pointer macro KPB$Q_REGION_ID = 80,0,0,0 %; literal KPB$S_REGION_ID = 8; ! Used for p2 allocations macro KPB$PQ_PRV_MEM_BASE = 88,0,0,1 %; literal KPB$S_PRV_MEM_BASE = 8; ! returned by SETSTK_64 macro KPB$Q_PRV_MEM_LEN = 96,0,0,0 %; literal KPB$S_PRV_MEM_LEN = 8; ! returned by SETSTK_64 macro KPB$PQ_PRV_RSE_BASE = 104,0,0,1 %; literal KPB$S_PRV_RSE_BASE = 8; ! returned by SETSTK_64 macro KPB$Q_PRV_RSE_LEN = 112,0,0,0 %; literal KPB$S_PRV_RSE_LEN = 8; ! returned by SETSTK_64 macro KPB$Q_MEM_REGION_ID = 120,0,0,0 %; literal KPB$S_MEM_REGION_ID = 8; ! Used for mem stack regions macro KPB$q_RSRVD_FUTURE = 128,0,0,1 %; literal KPB$S_RSRVD_FUTURE = 64; ! Cells for future use macro KPB$PS_SCH_STALL_RTN = 192,0,32,1 %; ! Scheduling STALL handling routine pointer macro KPB$PS_SCH_RESTRT_RTN = 196,0,32,1 %; ! Scheduling RESTART handling routine pointer macro KPB$PS_FKBLK = 200,0,32,1 %; ! pointer to a fork block macro KPB$PS_SCH_END_RTN = 204,0,32,1 %; ! Scheduling END handling routine pointer macro KPB$PS_FQFL = 208,0,32,1 %; ! fork queue flink macro KPB$PS_FQBL = 212,0,32,1 %; ! fork queue blink macro KPB$IW_FKB_SIZE = 216,0,16,0 %; ! fork block size macro KPB$IB_FKB_TYPE = 218,0,8,0 %; ! fork block type macro KPB$IB_FLCK = 219,0,8,0 %; ! fork lock macro KPB$PS_FPC = 220,0,32,1 %; ! fork PC macro KPB$Q_FR3 = 224,0,0,1 %; literal KPB$S_FR3 = 8; ! fork R3 macro KPB$Q_FR4 = 232,0,0,1 %; literal KPB$S_FR4 = 8; ! fork R4 macro KPB$PS_TQFL = 208,0,32,1 %; ! timer queue flink macro KPB$PS_TQBL = 212,0,32,1 %; ! timer queue blink macro KPB$IW_TQE_SIZE = 216,0,16,0 %; ! TQE size macro KPB$IB_TQE_TYPE = 218,0,8,0 %; ! TQE type macro KPB$IB_RQTYPE = 219,0,8,0 %; ! timer request type macro KPB$PS_TQE_FPC = 220,0,32,1 %; ! timer routine pointer macro KPB$Q_TQE_FR3 = 224,0,0,1 %; literal KPB$S_TQE_FR3 = 8; ! timer routine R3 macro KPB$Q_TQE_FR4 = 232,0,0,1 %; literal KPB$S_TQE_FR4 = 8; ! timer routine R4 macro KPB$IQ_TIME = 240,0,0,1 %; literal KPB$S_TIME = 8; ! timer due time ! (VEST KPB's only) macro KPB$PS_UCB = 272,0,32,1 %; ! UCB address macro KPB$PS_IRP = 276,0,32,1 %; ! IRP address ! vestioblks union fill; macro KPB$IS_TIMEOUT_TIME = 280,0,32,0 %; ! WFI%%CH time out time macro KPB$IS_RESTORE_IPL = 284,0,32,0 %; ! WFI%%CH IPL to restore macro KPB$IS_CHANNEL_DATA = 288,0,32,0 %; ! WFI%%CH/REQCHN channel data macro KPB$PS_SCSI_PTR1 = 292,0,32,1 %; ! SCSI gen. struc ptr #1 macro KPB$PS_SCSI_PTR2 = 296,0,32,1 %; ! SCSI gen. struc ptr #2 macro KPB$PS_SCSI_SCDRP = 300,0,32,1 %; ! SCSI transfer SCDRP addr. macro KPB$IS_TIMEOUT = 304,0,32,0 %; ! time out time macro KPB$IS_NEWIPL = 308,0,32,0 %; ! IPL to restore macro KPB$PS_DLCK = 312,0,32,1 %; ! device spin lock ! end vestio; macro KPB$PS_LKB = 272,0,32,1 %; ! LKB address macro KPB$PS_SPL_STALL_RTN = 320,0,32,1 %; ! Spinlock STALL handling routine pointer macro KPB$PS_SPL_RESTRT_RTN = 324,0,32,1 %; ! Spinlock RESTART handling routine pointer ! X-28 macro KPB$PS_SPL_FORK = 328,0,32,1 %; ! Fork spinlock address macro KPB$PS_SPL_PORT = 332,0,32,1 %; ! Port spinlock address macro KPB$PS_SPL_DYN = 336,0,32,1 %; ! Dynamic spinlock address macro KPB$L_IPL = 340,0,32,1 %; ! IPL of all spinlocks as longword macro KPB$B_IPL = 340,0,8,0 %; ! IPL of all spinlocks as byte ! End IPL union macro KPB$L_SAVED_SPL_CTX = 344,0,32,1 %; ! Re/starter's spinlock context macro KPB$L_ARCHIVED_SPL_CTX = 348,0,32,1 %; ! X-30 Spinlock contexts archived since re/start macro KPB$L_REQ_SPL_CTX = 352,0,32,1 %; ! Requested spinlock context macro KPB$L_FORK_OWN_CNT = 356,0,32,1 %; ! Fork SPL$L_OWN_COUNT on re/start literal KPB$K_SPL_LENGTH = 360; ! Length of KPB + SCH + SPL literal KPB$S_KPBDEF = 360; ! Old size name, synonym for KPB$S_KPB !*** MODULE $VCCDEF *** ! ! CFCB - Cache File Control Block ! ! There is one CFCB for each cacheable file. The Cache File Control ! Block contains the information necessary for consistent data caching ! in a VAXcluster. The FCB contains the address of the CFCB. ! literal CFCB$M_SEQ = %X'1'; literal CFCB$M_CONFLICT = %X'2'; literal CFCB$M_WRITE = %X'4'; literal CFCB$M_NOLOCK = %X'8'; literal CFCB$M_BUSY = %X'10'; literal CFCB$M_DELAYBLKAST = %X'20'; literal CFCB$M_DELAYCMPLAST = %X'40'; literal CFCB$M_DISBLKFRK = %X'80'; literal CFCB$M_DISCMPLFRK = %X'100'; literal CFCB$M_LIMBO = %X'200'; literal CFCB$M_BYPASS = %X'400'; literal CFCB$M_TRUNCATE = %X'800'; literal CFCB$M_DELETE = %X'1000'; literal CFCB$M_NOPRESERVE = %X'2000'; literal CFCB$K_LENGTH = 168; literal CFCB$S_CFCBDEF = 168; ! Old size name - synonym literal CFCB$S_CFCB = 168; ! head of CFCB is an ACB which we use as a FKB macro CFCB$L_ASTQFL = 0,0,32,1 %; ! AST queue FLINK macro CFCB$L_ASTQBL = 4,0,32,1 %; ! AST queue BLINK macro CFCB$W_SIZE = 8,0,16,0 %; ! size of CFCB in bytes macro CFCB$B_TYPE = 10,0,8,0 %; ! type is VCC, a subtypable structure macro CFCB$B_SUBTYPE = 11,0,8,0 %; ! subtype for CFCB and RMODE for ACB macro CFCB$L_AST_PID = 12,0,32,0 %; ! either accesser/deacceser or server macro CFCB$L_AST_ADDR = 16,0,32,1 %; ! address to resume process macro CFCB$L_AST_PRM = 20,0,32,0 %; ! the parameter ! no KAST field needed ! end of ACB ! cells to control access to and type of cache mode lock macro CFCB$Q_LKSB = 48,0,0,0 %; literal CFCB$S_LKSB = 8; ! whole LKSB macro CFCB$W_LKSB_STATUS = 48,0,16,0 %; ! completion status macro CFCB$W_RESERVED = 50,0,16,0 %; macro CFCB$L_LOCKID = 52,0,32,0 %; ! lockid of cache mode lock macro CFCB$L_WAIT_PID = 56,0,32,0 %; ! PID waiting for cache mode lock access macro CFCB$L_WAIT_ADDR = 60,0,32,1 %; ! address at which to resume process macro CFCB$L_WAIT_PRM = 64,0,32,0 %; ! AST parameter for waiting process macro CFCB$L_WRITERS = 68,0,32,0 %; ! number of reasons to keep write lock macro CFCB$L_HASHTABLE = 72,0,32,1 %; ! address of hash table data structure macro CFCB$L_STATUS = 76,0,32,0 %; ! macro CFCB$V_SEQ = 76,0,1,0 %; ! file is being accessed sequentially ! these next 3 bits must be together ! they indicate the current cache mode macro CFCB$V_CONFLICT = 76,1,1,0 %; ! this node's access conflicts with another node macro CFCB$V_WRITE = 76,2,1,0 %; ! set for read/write, clear read only macro CFCB$V_NOLOCK = 76,3,1,0 %; ! no cache mode lock held ! status bits for accessing the cache mode lock macro CFCB$V_BUSY = 76,4,1,0 %; ! cache mode lock is being modified macro CFCB$V_DELAYBLKAST = 76,5,1,0 %; ! BLKAST arrived while CFCB busy macro CFCB$V_DELAYCMPLAST = 76,6,1,0 %; ! CMPLAST arrived while CFCB busy macro CFCB$V_DISBLKFRK = 76,7,1,0 %; ! disable future blocking forks macro CFCB$V_DISCMPLFRK = 76,8,1,0 %; ! disable future completion forks ! OTHER STATUS BITS macro CFCB$V_LIMBO = 76,9,1,0 %; ! set if CFCB in LIMBO macro CFCB$V_BYPASS = 76,10,1,0 %; ! If set don't cache IO requests macro CFCB$V_TRUNCATE = 76,11,1,0 %; ! If set, need to truncate cache macro CFCB$V_DELETE = 76,12,1,0 %; macro CFCB$V_NOPRESERVE = 76,13,1,0 %; ! If set delete cache at $DEACCESS ! counts of interesting things macro CFCB$L_VREAD = 80,0,32,0 %; ! virtual reads to this file macro CFCB$L_READHIT = 84,0,32,0 %; ! read hits to this file macro CFCB$L_VWRITE = 88,0,32,0 %; ! virtual writes to this file macro CFCB$L_WRITEHIT = 92,0,32,0 %; ! write hits to this file macro CFCB$L_AROUND = 96,0,32,0 %; ! read or writes "around" this cache macro CFCB$L_BLOCKCNT = 100,0,32,0 %; ! data blocks allocated to this file macro CFCB$L_CLCNT = 104,0,32,0 %; ! cache lines allocated to this file macro CFCB$L_IOERRORS = 108,0,32,0 %; ! number of I/O errors for this file macro CFCB$L_LASTVBN = 112,0,32,0 %; ! last VBN read/written macro CFCB$L_HIVBN = 116,0,32,0 %; ! largest VBN ever cached for this file macro CFCB$L_FCB = 120,0,32,1 %; ! FCB associated with this CFCB macro CFCB$L_OCNT = 124,0,32,0 %; ! Count of Reasons not to delete CFCB macro CFCB$L_DISABLE = 128,0,32,0 %; ! number of reasons to disable caching ! of this file even if cache mode lock ! will allow caching ! zero means caching is enabled macro CFCB$L_LKQ_STATUS = 132,0,32,0 %; ! status of ENQ/DEQ request (not final) macro CFCB$L_TIME = 136,0,32,0 %; ! Time put CFCB put in LIMBO macro CFCB$Q_LIMBO = 140,0,0,0 %; literal CFCB$S_LIMBO = 8; ! Queue of CFCB that are in LIMBO macro CFCB$L_CID = 148,0,32,0 %; ! Cache ID macro CFCB$L_CVCB = 152,0,32,1 %; ! VCB address for this file macro CFCB$T_LOCKNAME = 156,0,0,0 %; literal CFCB$S_LOCKNAME = 12; ! XQP lockname ! ! HT - Hash Table ! ! There is one hash table for each cacheable file. The Cache File Control ! Block contains the address of the hash table. Access requires owning the ! cache spin lock. literal HT$Q_HASHTABLE = 24; ! start of hash table literal HT$S_HTDEF = 24; ! Old size name - synonym literal HT$S_HT = 24; ! The cache line and hash table sizes are not constants. They may vary for ! different files. The size of each must be a power of two. The VBN is ! subdivided into bitfields based on the cache line size and the size of ! the hash table. The lowest bits, <0,CLSIZE-1> represent the offset in ! the cache line. Bits are the hash index. These ! fields are accessed via bitfield instructions and the values of CLSIZE ! and HASHSIZE are encoded to define bitfields NOT the actual size of the ! entity. macro HT$L_CLSIZE = 0,0,32,0 %; ! encoded cache line size (see above) macro HT$L_HASHSIZE = 4,0,32,0 %; ! encoded hash table size (see above) macro HT$W_SIZE = 8,0,16,0 %; ! size of hash table strcuture in bytes macro HT$B_TYPE = 10,0,8,0 %; ! type is VCC, a subtypable structure macro HT$B_SUBTYPE = 11,0,8,0 %; ! subtype for HT macro HT$L_ENTRIES = 12,0,32,0 %; ! Entries in HT (if expansion ne 0 ! then actual number is ENTRIES*2) macro HT$L_EXPANSION = 16,0,32,0 %; ! Highest Hash currently being ! expanded ! ! CL - Cache Line ! ! A Cache Line is used by the VAXcluster Cache to track per VBN information. ! The hash table in the CFCB points to cache lines. ! literal CL$M_WRITE = %X'10000'; literal CL$M_DELAYTRUNC = %X'20000'; literal CL$K_LENGTH = 64; literal CL$S_CLDEF = 64; ! Old size name - synonym literal CL$S_CL = 64; macro CL$L_FLINK = 0,0,32,1 %; ! Equivalence class forward link macro CL$L_BLINK = 4,0,32,1 %; ! Equivalence class back link macro CL$W_SIZE = 8,0,16,0 %; ! size of CL in bytes macro CL$B_TYPE = 10,0,8,0 %; ! type is VCC, a subtypable structure macro CL$B_SUBTYPE = 11,0,8,0 %; ! subtype for CL macro CL$L_ENTRIES = 12,0,32,0 %; ! Number of Entries in Use macro CL$L_EXPANSION = 16,0,32,0 %; ! Buckets being split macro CL$L_TIME = 20,0,32,0 %; ! Time CL last referenced macro CL$L_FIRSTVBN = 24,0,32,0 %; ! first VBN in this cache line macro CL$L_CFCB = 28,0,32,1 %; ! address of corresponding CFCB macro CL$Q_LRUENTRY = 32,0,0,0 %; literal CL$S_LRUENTRY = 8; ! absolute queue entry in VCC$Q_LRULINE macro CL$Q_VALID = 40,0,0,0 %; literal CL$S_VALID = 8; ! set if corresponding VBN data valid macro CL$Q_DIRTY = 48,0,0,0 %; literal CL$S_DIRTY = 8; ! set if corresponding VBN data ! needs to be written before block ! is reused macro CL$L_LOCK = 56,0,32,0 %; ! looks just like mutex macro CL$W_COUNT = 56,0,16,0 %; ! Count of current accessers macro CL$V_WRITE = 56,16,1,0 %; ! write in progress or pending macro CL$V_DELAYTRUNC = 56,17,1,0 %; ! delete this line during unlock macro CL$L_VA = 60,0,32,1 %; ! virtual addresses for data blocks ! ! CPT - Cache I/O Page Table ! ! A range of sequential VBNs is not guarenteed to be virtually contiguous ! in the cache. Physical I/O requires the SVAPTE which maps the buffer. ! The cache builds a "fake" page table in this data structure and passes ! its virtual address as the SVAPTE. In addition some per I/O cache ! information is stored here rather than enlarge the IRP. ! literal CPT$L_PTE = 32; ! start of PTEs(Must be QUAD Aligned) literal CPT$K_LENGTH = 32; ! not counting size of VA array ! which is run time dependent literal CPT$S_CPTDEF = 32; ! Old size name - synonym literal CPT$S_IOCPT = 32; macro CPT$Q_IOVA = 0,0,0,1 %; literal CPT$S_IOVA = 8; ! Cache IO VA (64 Bits) macro CPT$L_SVA = 0,0,32,1 %; ! Page IO SVAPTE macro CPT$W_SIZE = 8,0,16,0 %; ! size of CPT in bytes macro CPT$B_TYPE = 10,0,8,0 %; ! type is VCC, a subtypable structure macro CPT$B_SUBTYPE = 11,0,8,0 %; ! subtype for CPT macro CPT$L_IOEXTRA = 12,0,32,0 %; ! read ahead byte count macro CPT$L_IOVBN = 16,0,32,0 %; ! cache I/O VBN macro CPT$L_IOBCNT = 20,0,32,0 %; ! cache I/O byte count macro CPT$L_CFCB = 24,0,32,1 %; ! CFCB address for this I/O macro CPT$L_RHBCNT = 28,0,32,0 %; ! read hit byte count ! real length equals IRP length ! ! CVCB - Cache Volume Control Block ! ! There is one of these structures for each ODS2 volume currently ! mounted by this node. It is used to permit detection of users ! that perform writes to volumes around the cache, so that the ! file caches concerned may be flushed. ! literal CVCB$M_ON = %X'1'; literal CVCB$M_MISMTCH = %X'2'; literal CVCB$M_DELETE = %X'4'; literal CVCB$M_BSY = %X'8'; literal CVCB$M_CONFLICT = %X'10'; literal CVCB$M_QIRP = %X'20'; literal CVCB$M_XFCLK = %X'40'; literal CVCB$K_LENGTH = 152; literal CVCB$S_CVCBDEF = 152; ! Old size name - synonym literal CVCB$S_CVCB = 152; macro CVCB$L_FLINK = 0,0,32,1 %; macro CVCB$L_BLINK = 4,0,32,1 %; macro CVCB$W_SIZE = 8,0,16,0 %; macro CVCB$B_TYPE = 10,0,8,0 %; macro CVCB$B_SUBTYPE = 11,0,8,0 %; macro CVCB$L_FRK1 = 16,0,32,1 %; ! Fork Block macro CVCB$L_FRK2 = 20,0,32,1 %; ! Fork Block macro CVCB$L_FRK3 = 24,0,32,1 %; ! Fork Block macro CVCB$L_FRK4 = 28,0,32,1 %; ! Fork Block macro CVCB$L_FRK5 = 32,0,32,1 %; ! Fork Block macro CVCB$L_FRK6 = 36,0,32,1 %; ! Fork Block macro CVCB$L_FRK7 = 40,0,32,1 %; ! Fork Block macro CVCB$L_FRK8 = 44,0,32,1 %; ! Fork Block macro CVCB$L_VCB = 64,0,32,1 %; ! VCB address macro CVCB$L_CID = 68,0,32,0 %; ! Cache ID (monatonicaly increasing) macro CVCB$L_CLUID = 72,0,32,0 %; ! Cluster ID (similar to CID) macro CVCB$L_STATE = 76,0,32,0 %; macro CVCB$V_ON = 76,0,1,0 %; ! Set if cache enabled this Volume macro CVCB$V_MISMTCH = 76,1,1,0 %; ! Set if not CACHE SAFE Driver macro CVCB$V_DELETE = 76,2,1,0 %; ! Set if Deleteing this CVCB macro CVCB$V_BSY = 76,3,1,0 %; ! Set if State change in progress macro CVCB$V_CONFLICT = 76,4,1,0 %; ! Set if MISMTCH Set somewhere in ! Cluster macro CVCB$V_QIRP = 76,5,1,0 %; ! Set if IRP's Q'd waiting for ! Cluster Invalidate macro CVCB$V_XFCLK = 76,6,1,0 %; ! Set if have Volume Interest Lock macro CVCB$L_OCNT = 80,0,32,0 %; ! Count of Reasons not to Delete CVCB macro CVCB$L_MNTCT = 84,0,32,0 %; ! VCB$W_MNTCT at last State Change macro CVCB$Q_IRP = 88,0,0,0 %; literal CVCB$S_IRP = 8; ! Q for IRP's macro CVCB$Q_LKSB = 96,0,0,0 %; literal CVCB$S_LKSB = 8; ! whole LKSB macro CVCB$W_LKSB_STATUS = 96,0,16,0 %; ! completion status macro CVCB$W_RESERVED = 98,0,16,0 %; macro CVCB$L_LOCKID = 100,0,32,0 %; ! lockid of Cache volume lock macro CVCB$Q_INTLKSB = 104,0,0,0 %; literal CVCB$S_INTLKSB = 8; ! whole LKSB macro CVCB$W_INTLKSB_STATUS = 104,0,16,0 %; ! completion status macro CVCB$W_INT_RESERVED = 106,0,16,0 %; macro CVCB$L_INTLOCKID = 108,0,32,0 %; ! lockid of Volume Interest lock macro CVCB$L_POOL = 112,0,32,0 %; ! Address for Pool in GET_VOL_LOCK macro CVCB$L_SEQ = 116,0,32,0 %; ! Cluster MEMSEQ for Node Bits macro CVCB$L_BITS = 120,0,32,0 %; ! Node bits macro CVCB$L_BITS1 = 124,0,32,0 %; macro CVCB$L_BITS2 = 128,0,32,0 %; macro CVCB$L_BITS3 = 132,0,32,0 %; macro CVCB$L_BITS4 = 136,0,32,0 %; macro CVCB$L_BITS5 = 140,0,32,0 %; macro CVCB$L_BITS6 = 144,0,32,0 %; macro CVCB$L_BITS7 = 148,0,32,0 %; ! ! CACHE$GL_FLAGS is now used to select the cache type to be loaded. ! As such the previous flags definitions which only apply to VIOC ! should be considered obsolete. Only use the flags definition if you ! know what you are doing. ! ! Bits in SYSGEN parameter CACHE$GL_FLAGS ! This is actually 4 one byte sysgen parameters. ! CACHE$GB_FLAGS0 - user "visible" static prefix CACHE_TYPE$C ! CACHE$GB_FLAGS1 - user "visible" static prefix CACHE_FLAGS$V ! CACHE$GB_FLAGS2 ! CACHE$GB_FLAGS3 ! literal CACHE_TYPE$C_NOCACHE = 0; ! No cache is loaded literal CACHE_TYPE$C_VIOC = 1; ! Cache type is VIOC, Virtual I/O Cache (aka VCC) literal CACHE_TYPE$C_XFC = 2; ! Cache type is XFC, Extended File Cache ! Define XFC control flag bits in CACHE$GL_FLAGS as flags and not constants. ! These are not present in V7.3 and below... ! The CACHE_TYPE$C values above remain for historical reasons. In future please use the ! bitfield values below... ! literal CACHE_FLAGS$M_VIOC = %X'1'; literal CACHE_FLAGS$M_XFC = %X'2'; literal CACHE_FLAGS$M_FLAG_NOT_USED = %X'FC'; literal CACHE_FLAGS$M_XFC_PER_RAD_CACHE = %X'100'; literal CACHE_FLAGS$S_CACHEFLAGS1 = 2; macro CACHE_FLAGS$V_VIOC = 0,0,1,0 %; ! Load VIOC macro CACHE_FLAGS$V_XFC = 0,1,1,0 %; ! Load XFC execlet macro CACHE_FLAGS$V_XFC_PER_RAD_CACHE = 0,8,1,0 %; ! Use XFC per RAD caching literal CACHE$M_ON = %X'1'; literal CACHE$M_PROTOCOL_ONLY = %X'2'; literal CACHE$M_READ_AHEAD = %X'4'; literal CACHE$M_UPDATE_ON_WRTE = %X'8'; literal CACHE$S_CACHEDEF = 1; ! Old size name - synonym literal CACHE$S_CACHEFLAGS = 1; macro CACHE$V_ON = 0,0,1,0 %; ! Turn on caching macro CACHE$V_PROTOCOL_ONLY = 0,1,1,0 %; ! Run the cache protocal, but ! don't cache anything. macro CACHE$V_READ_AHEAD = 0,2,1,0 %; ! Allow Read Ahead macro CACHE$V_UPDATE_ON_WRTE = 0,3,1,0 %; ! Update on Write Alogrithm ! Define bits in CACHE$GL_STATE ! literal CACHE_STATE$M_LBSY = %X'1'; literal CACHE_STATE$M_MBSY = %X'2'; literal CACHE_STATE$M_LOCK = %X'4'; literal CACHE_STATE$M_PAK = %X'8'; literal CACHE_STATE$M_ON = %X'10'; literal CACHE_STATE$M_IMG = %X'20'; literal CACHE_STATE$M_HETERO = %X'40'; literal CACHE_STATE$M_FLUSH = %X'80'; literal CACHE_STATE$M_UPDWRT = %X'100'; literal CACHE_STATE$M_RDAHD = %X'200'; literal CACHE_STATE$M_SAFE = %X'400'; literal CACHE_STATE$M_DATA = %X'800'; literal CACHE_STATE$M_USERSIZE = %X'1000'; literal CACHE_STATE$M_ENABLED = %X'2000'; literal CACHE_STATE$M_REDUCED = %X'4000'; literal CACHE_STATE$M_FULL = %X'8000'; literal CACHE_STATE$S_CACHESTATEDEF = 2; ! Old size name - synonym literal CACHE_STATE$S_CACHESTATE = 2; macro CACHE_STATE$V_LBSY = 0,0,1,0 %; ! Cache master lock busy macro CACHE_STATE$V_MBSY = 0,1,1,0 %; ! macro CACHE_STATE$V_LOCK = 0,2,1,0 %; ! Cache master lock acquired macro CACHE_STATE$V_PAK = 0,3,1,0 %; ! VCC PAK enabled macro CACHE_STATE$V_ON = 0,4,1,0 %; ! Cache enabled macro CACHE_STATE$V_IMG = 0,5,1,0 %; ! Image cache enabled macro CACHE_STATE$V_HETERO = 0,6,1,0 %; ! Heterogenous cluster macro CACHE_STATE$V_FLUSH = 0,7,1,0 %; ! Flush cache contents macro CACHE_STATE$V_UPDWRT = 0,8,1,0 %; ! Populate on update write only macro CACHE_STATE$V_RDAHD = 0,9,1,0 %; ! Read ahead enabled macro CACHE_STATE$V_SAFE = 0,10,1,0 %; ! Cache safe derivers present macro CACHE_STATE$V_DATA = 0,11,1,0 %; ! Data cache enabled macro CACHE_STATE$V_USERSIZE = 0,12,1,0 %; ! User has sized cache macro CACHE_STATE$V_ENABLED = 0,13,1,0 %; ! Caching enabled macro CACHE_STATE$V_REDUCED = 0,14,1,0 %; ! XFC is using Reduced Mode macro CACHE_STATE$V_FULL = 0,15,1,0 %; ! XFC is using Full Mode ! Define item codes for GET_STAT ! literal CACHE_ITEM$_LISTEND = 0; ! List terminator literal CACHE_ITEM$_STATE = 1; ! State flags literal CACHE_ITEM$_CACHE_MEMORY = 2; ! Pages of cache memory literal CACHE_ITEM$_FREE_CACHE = 3; ! Free page of cache memory literal CACHE_ITEM$_READ_HITS = 4; ! Read hits literal CACHE_ITEM$_VIRT_READS = 5; ! Virtual reads to cacheable files literal CACHE_ITEM$_VIRT_WRITES = 6; ! Virtual writes to cacheable files literal CACHE_ITEM$_R_ARND_MOD = 7; ! Read arounds du to modifier bits literal CACHE_ITEM$_R_ARND_SIZ = 8; ! Read arounds due to size too large literal CACHE_ITEM$_W_ARND_MOD = 9; ! Write arounds due to modifier bits literal CACHE_ITEM$_W_ARND_SIZ = 10; ! Write arounds due to size too large literal CACHE_ITEM$_LIMBO_LEN = 11; ! Length of limbo queue literal CACHE_ITEM$_MIN_CACHE_SIZE = 12; ! Current lower bound on size of cache literal CACHE_ITEM$_MAX_CACHE_SIZE = 13; ! Current upper bound on size of cache literal CACHE_ITEM$_MAX_CACHE_LIMIT = 14; ! Upper limit set by boot-time PTE allocation literal CACHE_ITEM$_MAX_IO_SIZE = 15; ! Largest IO XFC will cache literal CACHE_ITEM$_MAX_LOCKS = 16; ! Maximum number of locks XFC can acquire locally literal CACHE_ITEM$_READAHEAD = 17; ! Current value of VCC_READAHEAD SYSGEN param literal CACHE_ITEM$_WRITEBEHIND = 18; ! Current value of VCC_WRITEBEHIND SYSGEN param literal CACHE_ITEM$_WRITE_DELAY = 19; ! Current value of VCC_WRITE_DELAY SYSGEN param literal CACHE_ITEM$_VOLS_FXFC_MODE = 20; ! Count of volumes currently in full XFC mode literal CACHE_ITEM$_VOLS_RXFC_MODE = 21; ! Count of volumes currently in reduced XFC mode literal CACHE_ITEM$_VOLS_NC_MODE = 22; ! Count of volumes currently in no-caching mode literal CACHE_ITEM$_OPEN_FILES = 23; ! Count of open files with valid data in cache literal CACHE_ITEM$_UNSYNCHED_IOS = 24; ! Count of IO's not synchronised with XFC cache literal CACHE_ITEM$_DELAYED_WRITES = 25; ! Count of delayed writes since system startup literal CACHE_ITEM$_LOST_WRITES = 26; ! Count of delayed writes discarded since system startup literal CACHE_ITEM$_FULL_BARRIERS = 27; ! Count of outstanding full barriers currently in cache literal CACHE_ITEM$_PARTIAL_BARRIERS = 28; ! Count of outstanding full barriers currently in cache literal CACHE_ITEM$_READS_AROUND = 29; ! Count of all reads bypassing cache literal CACHE_ITEM$_WRITES_AROUND = 30; ! Count of all writes bypassing cache literal CACHE_ITEM$_CURRENT_LOCKS = 31; ! Count of locks held by cache literal CACHE_ITEM$_BARRIER_COUNT = 32; ! Count of barriers inserted into cache since boot literal CACHE_ITEM$_SUPER_WRITES = 33; ! Count of writes that supersede dirty data literal CACHE_ITEM$_NON_PAGED_POOL = 34; ! Amount of non-paged pool cuurrently held by the cache literal CACHE_ITEM$_VOLS_PNC_MODE = 35; ! Count of volumes in permanent no-caching mode literal CACHE_ITEM$_IOSIZE_ARRAYS = 36; ! Arrays of IOs by size literal CACHE_ITEM$_TIME_LAST_RESET = 37; ! Time since last reset of stats literal CACHE_ITEM$_TRACE_ENTRY = 38; ! to get trace buffer record(s) literal CACHE_ITEM$_SET_TRACE_MASK = 39; ! to set trace include/exclude mask literal CACHE_ITEM$_TRACE_RESET = 40; ! to empty trace buffer literal CACHE_ITEM$_BLOCKS_READ = 41; ! Total of blocks read from cache (hits + misses) literal CACHE_ITEM$_BLOCKS_FROM_CACHE = 42; ! Total blocks satisfied from cache literal CACHE_ITEM$_BLOCKS_WRITTEN = 43; ! Total blocks written (includes writethroughs + writearounds literal CACHE_ITEM$_MAX_VCC_ITEM = 11; literal CACHE_ITEM$_MAX_XFC_ITEM = 43; literal CACHE_ITEM$_MAX_ITEM = 43; ! Values for item codes for CACHE$SET_STATVOL() and ! CACHE$SET_STATFILE(). literal CACHE_CONTROL$_RESET_STATISTICS = 1; ! Reset statistics to zero literal CACHE_CONTROL$_SIZE_DISABLE = 2; ! Disable extended statistics collection literal CACHE_CONTROL$_SIZE_ENABLE = 3; ! Enable extended statistics collection literal CACHE_CONTROL$_FORCE_DEPOSE = 4; ! Force depose of volume or file literal CACHE_CONTROL$_FORCE_NOCACHE = 5; ! Force file to no cache state ! Define CVS (Cache Volume Statistics) for obtaining per volume statistics from XFC ! Values for CVS$L_CACHE_STATE: ! NOTE: coordinate changes with [XFC]XFCDEF.H literal CVS$C_NOCACHING = 4096; ! Volume not cached literal CVS$C_REDUCEDXFC = 4097; ! Volume in reduced XFC mode literal CVS$C_FULLXFC = 4098; ! Volume in Full XFC mode literal CVS$C_PERMNOCACHING = 4099; ! Volume permanently not cached literal CVS$K_VOLNAM_LEN = 12; literal CVS$C_VOLNAM_LEN = 12; literal CVS$K_HDRLEN = 52; ! Length of header literal CVS$C_HDRLEN = 52; ! ! NOTE: any changes or additions to the following fields or literal CVS$C_XFC_ARRAYSIZE = 128; ! Size of array literal CVS$K_ORIG_ITEM_COUNT = 31; literal CVS$C_ORIG_ITEM_COUNT = 31; literal CVS$K_ITEM_COUNT = 37; literal CVS$C_ITEM_COUNT = 37; literal CVS$K_BASE_SIZE = 348; literal CVS$C_BASE_SIZE = 348; literal CVS$K_IO_ARRAY_SIZE = 3112; literal CVS$C_IO_ARRAY_SIZE = 3112; literal CVS$S_CVS = 3464; macro CVS$Q_RESERVED1 = 0,0,0,0 %; literal CVS$S_RESERVED1 = 8; ! unused; aligns type to byte 11 macro CVS$W_MBO = 8,0,16,0 %; ! must be one macro CVS$B_TYPE = 10,0,8,0 %; ! type is VCC, a subtypable structure macro CVS$B_SUBTYPE = 11,0,8,0 %; ! subtype is VCC_CVS macro CVS$L_VERSION = 12,0,32,0 %; ! version of Cache Volume Statistics used by XFC macro CVS$L_STATUS = 16,0,32,0 %; ! return status macro CVS$L_CACHE_STATE = 20,0,32,0 %; ! Volume caching state macro CVS$L_VCB = 24,0,32,1 %; ! address of Volume Control Block macro CVS$L_ITM_CNT = 28,0,32,0 %; ! Number of quadword items to return macro CVS$L_IOSIZE_BUFFER_SIZE = 32,0,32,0 %; ! Size (bytes) of IO size stat buffer (0 if none requested) macro CVS$L_IOSIZE_BUFFER = 36,0,32,1 %; ! Address of IO size stat buffer macro CVS$T_VOLNAM = 40,0,0,0 %; literal CVS$S_VOLNAM = 12; ! blank filled volume name ! values MUST also be reflected in the CVB_STATS structure in [XFC]XFCDEF.H macro CVS$Q_OPEN_FILES = 52,0,0,0 %; literal CVS$S_OPEN_FILES = 8; ! Open cached files macro CVS$Q_CLOSED_FILES = 60,0,0,0 %; literal CVS$S_CLOSED_FILES = 8; ! Closed cached files macro CVS$Q_FILES_EVER_OPENED = 68,0,0,0 %; literal CVS$S_FILES_EVER_OPENED = 8; ! Files ever opened macro CVS$Q_FILES_EVER_DEPOSED = 76,0,0,0 %; literal CVS$S_FILES_EVER_DEPOSED = 8; ! Files ever deposed macro CVS$Q_PAGES_ALLOCATED = 84,0,0,0 %; literal CVS$S_PAGES_ALLOCATED = 8; ! Pages of memory currently held for the volume macro CVS$Q_LOCKS_ACQUIRED = 92,0,0,0 %; literal CVS$S_LOCKS_ACQUIRED = 8; ! Number of locks currently held for the volume macro CVS$Q_TOTALQIOS = 100,0,0,0 %; literal CVS$S_TOTALQIOS = 8; ! Total QIOs against this volume macro CVS$Q_READ_HITS = 108,0,0,0 %; literal CVS$S_READ_HITS = 8; ! read cache hits macro CVS$Q_VIRTUAL_READS = 116,0,0,0 %; literal CVS$S_VIRTUAL_READS = 8; ! virtual reads macro CVS$Q_VIRTUAL_WRITES = 124,0,0,0 %; literal CVS$S_VIRTUAL_WRITES = 8; ! " writes macro CVS$Q_READ_AHEADS = 132,0,0,0 %; literal CVS$S_READ_AHEADS = 8; ! Read aheads macro CVS$Q_READ_THROUGHS = 140,0,0,0 %; literal CVS$S_READ_THROUGHS = 8; ! Read throughs macro CVS$Q_WRITE_THROUGHS = 148,0,0,0 %; literal CVS$S_WRITE_THROUGHS = 8; ! Write throughs macro CVS$Q_READ_AROUND_COUNT = 156,0,0,0 %; literal CVS$S_READ_AROUND_COUNT = 8; ! Read arounds macro CVS$Q_WRITE_AROUND_COUNT = 164,0,0,0 %; literal CVS$S_WRITE_AROUND_COUNT = 8; ! Write arounds macro CVS$Q_READ_AROUND_MOD = 172,0,0,0 %; literal CVS$S_READ_AROUND_MOD = 8; ! Read arounds due to modifier bits macro CVS$Q_WRITE_AROUND_MOD = 180,0,0,0 %; literal CVS$S_WRITE_AROUND_MOD = 8; ! Write arounds due to modifier bits macro CVS$Q_READ_AROUND_SIZE = 188,0,0,0 %; literal CVS$S_READ_AROUND_SIZE = 8; ! Read arounds due to size too large macro CVS$Q_WRITE_AROUND_SIZE = 196,0,0,0 %; literal CVS$S_WRITE_AROUND_SIZE = 8; ! Write arounds due to size too large macro CVS$Q_WRITE_BEHINDS = 204,0,0,0 %; literal CVS$S_WRITE_BEHINDS = 8; ! Write behinds macro CVS$Q_FULL_BARRIERS = 212,0,0,0 %; literal CVS$S_FULL_BARRIERS = 8; ! Number of full barriers in dep graph macro CVS$Q_LOST_WRITES = 220,0,0,0 %; literal CVS$S_LOST_WRITES = 8; ! Writes lost due to disk errors macro CVS$Q_UNSYNCHED_IO_COUNT = 228,0,0,0 %; literal CVS$S_UNSYNCHED_IO_COUNT = 8; ! Count of unsynced I/Os macro CVS$Q_PARTIAL_BARRIERS = 236,0,0,0 %; literal CVS$S_PARTIAL_BARRIERS = 8; ! Number of partial barriers in dep graph macro CVS$Q_BARRIER_COUNT = 244,0,0,0 %; literal CVS$S_BARRIER_COUNT = 8; ! Number of barrier calls made since boot-time macro CVS$Q_SYNCH_RESPONSE_MISS = 252,0,0,0 %; literal CVS$S_SYNCH_RESPONSE_MISS = 8; ! Count of response time I/O misses macro CVS$Q_ASYNCH_RESPONSE_MISS = 260,0,0,0 %; literal CVS$S_ASYNCH_RESPONSE_MISS = 8; ! Count of response time I/O misses macro CVS$Q_SYNCH_RESPONSE_TICS = 268,0,0,0 %; literal CVS$S_SYNCH_RESPONSE_TICS = 8; ! Sum of ticks for synch response time macro CVS$Q_ASYNCH_RESPONSE_TICS = 276,0,0,0 %; literal CVS$S_ASYNCH_RESPONSE_TICS = 8; ! Sum of ticks for asynch response time macro CVS$Q_RESPONSE_TIME = 284,0,0,0 %; literal CVS$S_RESPONSE_TIME = 8; ! Overall Disk I/O response time macro CVS$Q_CVB_LAST_RESET = 292,0,0,0 %; literal CVS$S_CVB_LAST_RESET = 8; ! Time this array was last reset macro CVS$Q_BLOCKS_READ = 300,0,0,0 %; literal CVS$S_BLOCKS_READ = 8; ! Total of blocks read from cache (hits + misses) macro CVS$Q_BLOCKS_FROM_CACHE = 308,0,0,0 %; literal CVS$S_BLOCKS_FROM_CACHE = 8; ! Total blocks satisfied from cache macro CVS$Q_BLOCKS_WRITTEN = 316,0,0,0 %; literal CVS$S_BLOCKS_WRITTEN = 8; ! Total blocks written (includes writethroughs + writearounds macro CVS$Q_FILES_TRUNCATED = 324,0,0,0 %; literal CVS$S_FILES_TRUNCATED = 8; ! Number of files truncated macro CVS$Q_LOGICAL_IO_COUNT = 332,0,0,0 %; literal CVS$S_LOGICAL_IO_COUNT = 8; ! Number of logical IOs macro CVS$Q_VCML_BLOCKING_ASTS = 340,0,0,0 %; literal CVS$S_VCML_BLOCKING_ASTS = 8; ! Number for volume deposes from a VCML blocking AST (logical IO in cluster) ! Add new individual stat fields above this line ! ! IO size array: macro CVS$Q_READ_BLOCKSIZE = 348,0,0,0 %; literal CVS$S_READ_BLOCKSIZE = 1024; ! Read Size stat array macro CVS$Q_BLOCK_READ_HITS = 1372,0,0,0 %; literal CVS$S_BLOCK_READ_HITS = 1024; ! Read Hits stat array macro CVS$Q_WRITE_BLOCKSIZE = 2396,0,0,0 %; literal CVS$S_WRITE_BLOCKSIZE = 1024; ! Write Size stat array macro CVS$Q_WRITES128TO255 = 3420,0,0,0 %; literal CVS$S_WRITES128TO255 = 8; ! Number of writes in 128-255 block range macro CVS$Q_READS128TO255 = 3428,0,0,0 %; literal CVS$S_READS128TO255 = 8; ! Number of reads in 128-255 block range macro CVS$Q_LARGE_WRITES = 3436,0,0,0 %; literal CVS$S_LARGE_WRITES = 8; ! Number of writes greater than 255 blocks macro CVS$Q_LARGE_READS = 3444,0,0,0 %; literal CVS$S_LARGE_READS = 8; ! Number of reads greater than 255 blocks macro CVS$Q_TIME_LAST_RESET = 3452,0,0,0 %; literal CVS$S_TIME_LAST_RESET = 8; ! Time this array was last reset ! New CVS fields should be accompanied by an increment of the value of CACHE_VERSION$C_VCC_CVS ! below. literal CACHE_VERSION$_VCC_CVS = 65536; ! Version number of CVS interface ! Define CFS (Cache File Statistics) for obtaining per file statistics from XFC ! Values for FILE_STATE (also on input to CACHE$GET_FIDS): literal CFS$K_OPEN = 1; ! CFS$K_OPEN - file is open literal CFS$C_OPEN = 1; ! CFS$C_OPEN - file is open literal CFS$K_CLOSED = 2; ! CFS$K_CLOSED - file is closed literal CFS$C_CLOSED = 2; ! CFS$C_CLOSED - file is closed ! Values for CFS$L_CACHE_STATE: ! NOTE: coordinate changes with [XFC]XFCDEF.H literal CFS$C_DEFAULT = 8192; ! No active mode specified literal CFS$C_WRITETHROUGH = 8193; ! File in writethrough mode literal CFS$C_WRITEBEHIND = 8194; ! File in writebehind mode literal CFS$C_NOCACHING = 8195; ! File is not cached literal CFS$K_HDRLEN = 56; ! Length of header literal CFS$C_HDRLEN = 56; ! ! NOTE: any changes or additions to the following stats fields literal CFS$C_XFC_ARRAYSIZE = 128; ! Size of array literal CFS$K_ITEM_COUNT = 20; literal CFS$C_ITEM_COUNT = 20; literal CFS$K_BASE_SIZE = 216; literal CFS$C_BASE_SIZE = 216; literal CFS$K_IO_ARRAY_SIZE = 3112; literal CFS$C_IO_ARRAY_SIZE = 3112; literal CFS$S_CFS = 3328; macro CFS$Q_RESERVED1 = 0,0,0,0 %; literal CFS$S_RESERVED1 = 8; ! unused; aligns type to byte 11 macro CFS$W_MBO = 8,0,16,0 %; ! must be one macro CFS$B_TYPE = 10,0,8,0 %; ! type is VCC, a subtypable structure macro CFS$B_SUBTYPE = 11,0,8,0 %; ! subtype is VCC_CVS macro CFS$L_VERSION = 12,0,32,0 %; ! version of Cache File Statistics used by XFC macro CFS$L_STATUS = 16,0,32,0 %; ! return status macro CFS$L_CACHE_STATE = 20,0,32,0 %; ! File active caching state macro CFS$L_FILE_STATE = 24,0,32,0 %; ! Open/closed state macro CFS$L_CACHING_DISABLED = 28,0,32,0 %; ! Boolean macro CFS$L_VCB = 32,0,32,1 %; ! address of Volume Control Block macro CFS$Q_FID = 36,0,0,0 %; literal CFS$S_FID = 8; ! FID (last word unused) macro CFS$L_ITM_CNT = 44,0,32,0 %; ! Number of quadword items to return macro CFS$L_IOSIZE_BUFFER_SIZE = 48,0,32,0 %; ! Size (bytes) of IO size stat buffer (0 if none requested) macro CFS$L_IOSIZE_BUFFER = 52,0,32,1 %; ! Address of IO size stat buffer ! MUST also be reflected in the CFB_STATS structure in [XFC]XFCDEF.H ! macro CFS$Q_PAGES_ALLOCATED = 56,0,0,0 %; literal CFS$S_PAGES_ALLOCATED = 8; ! Pages of memory currently held for the file macro CFS$Q_TOTALQIOS = 64,0,0,0 %; literal CFS$S_TOTALQIOS = 8; ! Total QIOs against this file macro CFS$Q_READ_HITS = 72,0,0,0 %; literal CFS$S_READ_HITS = 8; ! read cache hits macro CFS$Q_VIRTUAL_READS = 80,0,0,0 %; literal CFS$S_VIRTUAL_READS = 8; ! virtual reads macro CFS$Q_VIRTUAL_WRITES = 88,0,0,0 %; literal CFS$S_VIRTUAL_WRITES = 8; ! " writes macro CFS$Q_READ_AHEADS = 96,0,0,0 %; literal CFS$S_READ_AHEADS = 8; ! Read aheads macro CFS$Q_READ_THROUGHS = 104,0,0,0 %; literal CFS$S_READ_THROUGHS = 8; ! Read throughs macro CFS$Q_WRITE_THROUGHS = 112,0,0,0 %; literal CFS$S_WRITE_THROUGHS = 8; ! Write throughs macro CFS$Q_READ_AROUND_COUNT = 120,0,0,0 %; literal CFS$S_READ_AROUND_COUNT = 8; ! Read arounds macro CFS$Q_WRITE_AROUND_COUNT = 128,0,0,0 %; literal CFS$S_WRITE_AROUND_COUNT = 8; ! Write arounds macro CFS$Q_READ_AROUND_MOD = 136,0,0,0 %; literal CFS$S_READ_AROUND_MOD = 8; ! Read arounds due to modifier bits macro CFS$Q_WRITE_AROUND_MOD = 144,0,0,0 %; literal CFS$S_WRITE_AROUND_MOD = 8; ! Write arounds due to modifier bits macro CFS$Q_READ_AROUND_SIZE = 152,0,0,0 %; literal CFS$S_READ_AROUND_SIZE = 8; ! Read arounds due to size too large macro CFS$Q_WRITE_AROUND_SIZE = 160,0,0,0 %; literal CFS$S_WRITE_AROUND_SIZE = 8; ! Write arounds due to size too large macro CFS$Q_WRITE_BEHINDS = 168,0,0,0 %; literal CFS$S_WRITE_BEHINDS = 8; ! Write behinds macro CFS$Q_UNSYNCHED_IO_COUNT = 176,0,0,0 %; literal CFS$S_UNSYNCHED_IO_COUNT = 8; ! Count of unsynced I/Os macro CFS$Q_LOST_WRITES = 184,0,0,0 %; literal CFS$S_LOST_WRITES = 8; ! Writes lost due to disk errors macro CFS$Q_FULL_BARRIERS = 192,0,0,0 %; literal CFS$S_FULL_BARRIERS = 8; ! Number of full barriers in dep graph macro CFS$Q_PARTIAL_BARRIERS = 200,0,0,0 %; literal CFS$S_PARTIAL_BARRIERS = 8; ! Number of partial barriers in dep graph macro CFS$Q_BARRIER_COUNT = 208,0,0,0 %; literal CFS$S_BARRIER_COUNT = 8; ! Number of barrier calls made since boot-time ! Add new individual stat fields above this line ! ! IO Size array: macro CFS$Q_READ_BLOCKSIZE = 216,0,0,0 %; literal CFS$S_READ_BLOCKSIZE = 1024; ! Read Size stat array macro CFS$Q_BLOCK_READ_HITS = 1240,0,0,0 %; literal CFS$S_BLOCK_READ_HITS = 1024; ! Read Hits stat array macro CFS$Q_WRITE_BLOCKSIZE = 2264,0,0,0 %; literal CFS$S_WRITE_BLOCKSIZE = 1024; ! Write Size stat array macro CFS$Q_WRITES128TO255 = 3288,0,0,0 %; literal CFS$S_WRITES128TO255 = 8; ! Number of writes in 128-255 block range macro CFS$Q_READS128TO255 = 3296,0,0,0 %; literal CFS$S_READS128TO255 = 8; ! Number of reads in 128-255 block range macro CFS$Q_LARGE_WRITES = 3304,0,0,0 %; literal CFS$S_LARGE_WRITES = 8; ! Number of writes greater than 255 blocks macro CFS$Q_LARGE_READS = 3312,0,0,0 %; literal CFS$S_LARGE_READS = 8; ! Number of reads greater than 255 blocks macro CFS$Q_TIME_LAST_RESET = 3320,0,0,0 %; literal CFS$S_TIME_LAST_RESET = 8; ! Time this array was last reset ! New CFS fields should be accompanied by an increment of the value of CACHE_VERSION$C_VCC_CFS ! below. literal CACHE_VERSION$_VCC_CFS = 65536; ! Version number of CFS interface ! ! The following values should be loaded into the global cell ! CACHE$GL_PROTOCOL_VER to indicate which level of locking ! protocol is going to be used by the cache loaded at boot ! time. The protocol level being used by other members of ! the cluster can be found in the CSB's of the respective ! nodes. ! ! Note that the default value of CACHE$GL_PROTOCOL_VER is ! zero so that pre-XFC aware versions of the OS 'acquire' ! the correct value in their remote CSB's ! literal CACHE_VERSION$_NOCACHE = 0; ! No or unknown locking protocol literal CACHE_VERSION$_VCC_V01_00 = 65536; ! VIOC with no XFC compatibility literal CACHE_VERSION$_VCC_V01_01 = 65537; ! VIOC with XFC compatible protocol literal CACHE_VERSION$_XFC_V01_00 = 131072; ! Fully XFC V1.0 compliant protocol !*** MODULE $MUTEXDEF *** ! + ! QUADWORD MUTEX DEFINITIONS ! - literal MUTEX$M_WRT = %X'1'; literal MUTEX$M_PRERLS_CBK = %X'2'; literal MUTEX$M_INTERLOCK = %X'1'; literal MUTEX$S_MUTEXDEF = 8; ! Old size name, synonym for MUTEX$S_MUTEX literal MUTEX$S_MUTEX = 8; macro MUTEX$Q_QUADWORD = 0,0,0,0 %; literal MUTEX$S_QUADWORD = 8; macro MUTEX$W_STS = 0,0,16,0 %; ! STATUS BITS macro MUTEX$V_WRT = 0,0,1,0 %; ! WRITE PENDING OR IN PROGRESS macro MUTEX$V_PRERLS_CBK = 0,1,1,0 %; ! Pre release call back macro MUTEX$V_INTERLOCK = 0,0,1,0 %; ! INTERLOCK ACCESS TO MUTEX macro MUTEX$L_OWNCNT = 4,0,32,0 %; ! OWNERSHIP COUNT literal MTXDBG$K_REV1 = 1; literal MTXDBG$K_REV2 = 2; literal MTXDBG$K_REVISION = 2; literal MTXDBG$K_MUTEX = 1; literal MTXDBG$K_INFO = 2; literal MTXDBG$K_MAX_FLAG = 2; literal MTXDBG$K_LOCKR = 1; literal MTXDBG$K_LOCKW = 2; literal MTXDBG$K_UNLOCK = 3; literal MTXDBG$K_LOCKREXEC = 4; literal MTXDBG$K_LOCKWEXEC = 5; literal MTXDBG$K_UNLOCKEXEC = 6; literal MTXDBG$K_LOCKR_QUAD = 7; literal MTXDBG$K_LOCKW_QUAD = 8; literal MTXDBG$K_UNLOCK_QUAD = 9; literal MTXDBG$K_LOCKREXEC_QUAD = 10; literal MTXDBG$K_LOCKWEXEC_QUAD = 11; literal MTXDBG$K_UNLOCKEXEC_QUAD = 12; literal MTXDBG$K_LOCKWNOWAIT = 13; literal MTXDBG$K_LOCKWNOWAIT_QUAD = 14; literal MTXDBG$K_LOCKR_WAIT = 15; literal MTXDBG$K_LOCKW_WAIT = 16; literal MTXDBG$K_UNLOCK_REL = 17; literal MTXDBG$K_LOCKREXEC_INUSE = 18; literal MTXDBG$K_LOCKWEXEC_INUSE = 19; literal MTXDBG$K_UNLOCKEXEC_REL = 20; literal MTXDBG$K_LOCKR_QUAD_WAIT = 21; literal MTXDBG$K_LOCKW_QUAD_WAIT = 22; literal MTXDBG$K_UNLOCK_QUAD_REL = 23; literal MTXDBG$K_LOCKREXEC_QUAD_INUSE = 24; literal MTXDBG$K_LOCKWEXEC_QUAD_INUSE = 25; literal MTXDBG$K_UNLOCKEXEC_QUAD_REL = 26; literal MTXDBG$K_LOCKWNOWAIT_INUSE = 27; literal MTXDBG$K_LOCKWNOWAIT_QUAD_INUSE = 28; literal MTXDBG$K_MAX_MODE = 28; literal MTXDBG$M_MUTEX = %X'1'; literal MTXDBG$M_MUTEX_WAIT = %X'2'; literal MTXDBG$K_LENGTH = 108; ! Structure size literal MTXDBG$C_LENGTH = 108; ! Structure size literal MTXDBG$S_MTXDBG = 112; macro MTXDBG$Q_TRACE_BUFFER = 0,0,0,1 %; literal MTXDBG$S_TRACE_BUFFER = 8; ! pointer to trace buffer macro MTXDBG$W_MBO = 8,0,16,0 %; ! must-be-one field macro MTXDBG$B_TYPE = 10,0,8,0 %; ! Structure type macro MTXDBG$B_SUBTYPE = 11,0,8,0 %; ! and subtype macro MTXDBG$L_REVISION = 12,0,32,0 %; ! revision field macro MTXDBG$Q_SIZE = 16,0,0,1 %; literal MTXDBG$S_SIZE = 8; ! Size macro MTXDBG$L_START_TRACE = 24,0,32,1 %; ! ptr to start trace routine macro MTXDBG$L_STOP_TRACE = 28,0,32,1 %; ! ptr to stop trace routine macro MTXDBG$L_TRACE_MUTEX = 32,0,32,1 %; ! ptr to mutex trace routine macro MTXDBG$L_TRACE_MUTEX_WAIT = 36,0,32,1 %; ! ptr to mutex wait trace routine macro MTXDBG$L_DEBUG_PRINT = 40,0,32,1 %; macro MTXDBG$L_TRACE_FLAGS = 44,0,32,0 %; ! trace flags macro MTXDBG$V_MUTEX = 44,0,1,0 %; macro MTXDBG$V_MUTEX_WAIT = 44,1,1,0 %; macro MTXDBG$L_MTX_FLAGS = 48,0,32,0 %; ! trace specific mutex macro MTXDBG$L_CPU_FLAGS = 52,0,32,1 %; ! trace specific CPU macro MTXDBG$L_TRACE_RUN = 56,0,32,0 %; ! trace run index macro MTXDBG$Q_RESERVED1 = 64,0,0,0 %; literal MTXDBG$S_RESERVED1 = 8; macro MTXDBG$Q_RESERVED2 = 72,0,0,0 %; literal MTXDBG$S_RESERVED2 = 8; macro MTXDBG$Q_RESERVED3 = 80,0,0,0 %; literal MTXDBG$S_RESERVED3 = 8; macro MTXDBG$Q_RESERVED4 = 88,0,0,0 %; literal MTXDBG$S_RESERVED4 = 8; macro MTXDBG$PQ_SCC = 96,0,32,1 %; ! pointer to array of cycle counts per possible CPU macro MTXDBG$PQ_SYSTIME = 100,0,32,1 %; ! pointer to array of systime info per possible CPU macro MTXDBG$L_MAX_CPUS = 104,0,32,1 %; literal MTXTRE$K_LENGTH = 40; ! Structure size literal MTXTRE$S_MTXTRE = 40; macro MTXTRE$Q_TIMESTAMP = 0,0,0,0 %; literal MTXTRE$S_TIMESTAMP = 8; ! timestamp in system cycle counts macro MTXTRE$Q_PC = 8,0,0,0 %; literal MTXTRE$S_PC = 8; ! callers PC macro MTXTRE$L_CPUID = 16,0,32,0 %; ! current CPU id or address of CPU db macro MTXTRE$L_MODE = 20,0,32,0 %; ! general trace category macro MTXTRE$L_FLAG = 24,0,32,0 %; ! which event was traced macro MTXTRE$L_MUTEX = 28,0,32,0 %; ! address of mutex macro MTXTRE$L_PCB = 32,0,32,1 %; ! current process during trace macro MTXTRE$L_SPARE1 = 36,0,32,0 %; literal MTXTRH$K_LENGTH = 72; ! Structure size literal MTXTRH$S_MTXTRH = 72; macro MTXTRH$L_IDX = 0,0,32,1 %; ! current index into trace buffer macro MTXTRH$L_MAX_IDX = 4,0,32,0 %; ! maximum trace index macro MTXTRH$W_MBO = 8,0,16,0 %; ! must-be-one field macro MTXTRH$B_TYPE = 10,0,8,0 %; ! Structure type macro MTXTRH$B_SUBTYPE = 11,0,8,0 %; ! and subtype macro MTXTRH$L_FILL1 = 12,0,32,0 %; macro MTXTRH$Q_SIZE = 16,0,0,1 %; literal MTXTRH$S_SIZE = 8; ! Size macro MTXTRH$Q_ENTRY_PTR = 24,0,0,1 %; literal MTXTRH$S_ENTRY_PTR = 8; ! pointer to first trace entry macro MTXTRH$R_ENTRY = 32,0,0,0 %; literal MTXTRH$S_ENTRY = 40; ! array of trace entries !*** MODULE $MTXDEF *** ! + ! LONGWORD MUTEX DEFINITIONS (OLD STYLE) ! - literal MTX$S_MTXDEF = 4; ! Old size name, synonym for MTX$S_MTX literal MTX$S_MTX = 4; macro MTX$R_MTX_OVERLAY = 0,0,32,0 %; macro MTX$V_WRT = 0,16,1,0 %; ! WRITE PENDING OR IN PROGRESS macro MTX$V_INTERLOCK = 0,17,1,0 %; ! INTERLOCK ACCESS TO MUTEX macro MTX$W_OWNCNT = 0,0,16,0 %; ! OWNERSHIP COUNT macro MTX$W_STS = 2,0,16,0 %; ! STATUS BITS !*** MODULE $PDBDEF *** ! + ! DEFINE DEVICE PERFORMANCE DATA BLOCK ! - literal PDB$K_ABORT_RQ = 1; literal PDB$K_END_IO = 2; literal PDB$K_END_RQ = 3; literal PDB$K_START_IO = 4; literal PDB$K_START_RQ = 5; literal PDB$K_DIRIO = 6; literal PDB$K_BUFIO = 7; literal PDB$K_MAX_MODE = 7; literal PDB$M_ALL = %X'1'; literal PDB$M_ABORT_RQ = %X'2'; literal PDB$M_END_IO = %X'4'; literal PDB$M_END_RQ = %X'8'; literal PDB$M_START_IO = %X'10'; literal PDB$M_START_RQ = %X'20'; literal PDB$M_XFER = %X'40'; literal PDB$M_DIRIO = %X'80'; literal PDB$M_BUFIO = %X'100'; literal PDB$M_XQP = %X'200'; literal PDB$K_LENGTH = 156; ! LENGTH OF DATA CONTROL BLOCK literal PDB$C_LENGTH = 156; ! LENGTH OF DATA CONTROL BLOCK literal PDB$S_PDBDEF = 156; literal PDB$S_PDB = 160; macro PDB$L_FREEFL = 0,0,32,1 %; ! FREE BUFFER LISTHEAD FORWARD LINK macro PDB$L_FREEBL = 4,0,32,1 %; ! FREE BUFFER LISTHEAD BACKLINK macro PDB$W_SIZE = 8,0,16,0 %; ! SIZE OF DATA STRUCTURE macro PDB$B_TYPE = 10,0,8,0 %; ! TYPE OF DATA STRUCTURE macro PDB$B_OVERRUN = 11,0,8,0 %; ! OVERRUN INDICATOR macro PDB$L_FILLFL = 12,0,32,1 %; ! FILLED BUFFER LISTHEAD FORWARD LINK macro PDB$L_FILLBL = 16,0,32,1 %; ! FILLED BUFFER LISTHEAD BACKWARD LINK macro PDB$L_CURBUF = 20,0,32,1 %; ! ADDRESS OF CURRENT BUFFER macro PDB$L_NXTBUF = 24,0,32,1 %; ! ADDRESS OF NEXT LOCATION IN BUFFER macro PDB$L_ENDBUF = 28,0,32,1 %; ! ADDRESS OF END OF BUFFER macro PDB$L_PID = 32,0,32,0 %; ! PROCESS ID OF DATA COLLECTION PROCESS macro PDB$B_DEVCLASS = 36,0,8,0 %; ! DEVICE CLASS SELECTION macro PDB$B_DEVTYPE = 37,0,8,0 %; ! DEVICE TYPE SELECTION macro PDB$W_ANDM = 38,0,16,0 %; ! STATUS SELECTION 'AND' MASK macro PDB$W_XORM = 40,0,16,0 %; ! STATUS SELECTION 'XOR' MASK macro PDB$W_BUFCNT = 42,0,16,0 %; ! COUNT OF FILLED BUFFERS macro PDB$Q_FUNC = 44,0,0,0 %; literal PDB$S_FUNC = 8; ! SELECTION FUNCTION MASK macro PDB$Q_DATA = 56,0,0,1 %; literal PDB$S_DATA = 8; ! pointer to data area macro PDB$Q_TRACE_BUFFER = 64,0,0,1 %; literal PDB$S_TRACE_BUFFER = 8; ! pointer to trace buffer macro PDB$L_FLAGS = 72,0,32,0 %; ! trace flags macro PDB$V_ALL = 72,0,1,0 %; macro PDB$V_ABORT_RQ = 72,1,1,0 %; macro PDB$V_END_IO = 72,2,1,0 %; macro PDB$V_END_RQ = 72,3,1,0 %; macro PDB$V_START_IO = 72,4,1,0 %; macro PDB$V_START_RQ = 72,5,1,0 %; macro PDB$V_XFER = 72,6,1,0 %; macro PDB$V_DIRIO = 72,7,1,0 %; macro PDB$V_BUFIO = 72,8,1,0 %; macro PDB$V_XQP = 72,9,1,0 %; macro PDB$L_START_TRACE = 76,0,32,1 %; ! ptr to start trace routine macro PDB$L_STOP_TRACE = 80,0,32,1 %; ! ptr to stop trace routine macro PDB$L_ABORT_RQ = 84,0,32,1 %; ! abort I/O request macro PDB$L_END_IO = 88,0,32,1 %; ! end I/O transaction macro PDB$L_END_RQ = 92,0,32,1 %; ! end I/O request macro PDB$L_START_IO = 96,0,32,1 %; ! start I/O transaction macro PDB$L_START_RQ = 100,0,32,1 %; ! start I/O request macro PDB$L_DIO_BIO = 104,0,32,1 %; ! direct and buffered I/O macro PDB$Q_RESERVED1 = 112,0,0,1 %; literal PDB$S_RESERVED1 = 8; ! reserved macro PDB$Q_RESERVED2 = 120,0,0,1 %; literal PDB$S_RESERVED2 = 8; ! reserved macro PDB$Q_RESERVED3 = 128,0,0,1 %; literal PDB$S_RESERVED3 = 8; ! reserved macro PDB$Q_LAST_WAKE = 136,0,0,1 %; literal PDB$S_LAST_WAKE = 8; ! The ABSTIM_TIC value when collector last woken macro PDB$PQ_SCC = 144,0,32,1 %; ! pointer to array of cycle counts per possible CPU macro PDB$PQ_SYSTIME = 148,0,32,1 %; ! pointer to array of systime info per possible CPU macro PDB$L_MAX_CPUS = 152,0,32,1 %; literal IOTRE$K_LENGTH = 56; ! Structure size literal IOTRE$S_IOTRE = 56; macro IOTRE$Q_TIMESTAMP = 0,0,0,0 %; literal IOTRE$S_TIMESTAMP = 8; ! timestamp in system cycle counts macro IOTRE$L_CPUID = 8,0,32,0 %; ! current CPU id macro IOTRE$L_MODE = 12,0,32,0 %; ! general trace category macro IOTRE$L_SEQNUM = 16,0,32,0 %; ! sequence number macro IOTRE$L_FUNC = 20,0,32,0 %; ! function code macro IOTRE$L_IRP = 24,0,32,1 %; ! address of IRP macro IOTRE$L_UCB = 28,0,32,1 %; ! address of UCB macro IOTRE$L_BCNT = 32,0,32,0 %; ! byte count macro IOTRE$L_LBN = 36,0,32,0 %; ! starting LBN macro IOTRE$L_PCB = 40,0,32,1 %; ! address of PCB macro IOTRE$L_RESERVED1 = 44,0,32,0 %; ! reserved macro IOTRE$L_RESERVED2 = 48,0,32,0 %; ! reserved macro IOTRE$L_RESERVED3 = 52,0,32,0 %; ! reserved literal IOTRH$K_LENGTH = 88; ! Structure size literal IOTRH$S_IOTRH = 88; macro IOTRH$L_IDX = 0,0,32,1 %; ! current index into trace buffer macro IOTRH$L_MAX_IDX = 4,0,32,0 %; ! maximum trace index macro IOTRH$W_MBO = 8,0,16,0 %; ! must-be-one field macro IOTRH$B_TYPE = 10,0,8,0 %; ! Structure type macro IOTRH$B_SUBTYPE = 11,0,8,0 %; ! subtype macro IOTRH$L_FILL1 = 12,0,32,0 %; macro IOTRH$Q_SIZE = 16,0,0,1 %; literal IOTRH$S_SIZE = 8; ! Size macro IOTRH$Q_ENTRY_PTR = 24,0,0,1 %; literal IOTRH$S_ENTRY_PTR = 8; ! pointer to first trace entry macro IOTRH$R_ENTRY = 32,0,0,0 %; literal IOTRH$S_ENTRY = 56; ! array of trace entries !*** MODULE $PSHDEF *** ! ! Pshared Data Tag Structure ! literal PSHDAT$S_PSHARED_DATA = 8; macro PSHDAT$B_TYPE = 0,0,8,0 %; ! data tag type macro PSHDAT$B_OP = 1,0,8,0 %; ! data tag operation macro PSHDAT$W_OFFSET = 2,0,16,0 %; ! offset macro PSHDAT$L_MODIFIERS = 4,0,32,0 %; ! modifiers ! ! Pshared Lock Structure ! literal PSHLCK$S_PSHARED_LOCK = 8; macro PSHLCK$Q_LOCK_STATE = 0,0,0,1 %; literal PSHLCK$S_LOCK_STATE = 8; ! lock state macro PSHLCK$V_MUTEX_LOCK = 0,0,1,0 %; ! mutex lock bit macro PSHLCK$V_MUTEX_WAITERS = 0,1,31,0 %; literal PSHLCK$S_MUTEX_WAITERS = 31; ! mutex waiters count macro PSHLCK$V_MUTEX_WAITERS_HIGH = 4,0,32,0 %; literal PSHLCK$S_MUTEX_WAITERS_HIGH = 32; ! not used macro PSHLCK$V_WRITE_LOCK = 0,0,1,0 %; ! write lock bit macro PSHLCK$V_WRITE_WAITERS = 0,1,31,0 %; literal PSHLCK$S_WRITE_WAITERS = 31; ! number of writers macro PSHLCK$V_READERS_WAITING = 4,0,1,0 %; ! number of readers waiting macro PSHLCK$V_READERS = 4,1,31,0 %; literal PSHLCK$S_READERS = 31; ! number of readers ! ! Pshared State Structure ! literal PSHSTA$S_PSHARED_STATE = 24; macro PSHSTA$Q_LOCK = 0,0,0,0 %; literal PSHSTA$S_LOCK = 8; ! macro PSHSTA$L_COUNT = 8,0,32,1 %; ! macro PSHSTA$L_STATUS = 12,0,32,1 %; ! macro PSHSTA$Q_VM_OBJECT = 16,0,0,0 %; literal PSHSTA$S_VM_OBJECT = 8; ! ! ! Pshared Owner Structure ! literal PSHOWN$S_PSHARED_OWNER = 16; macro PSHOWN$L_OWNER_PID = 0,0,32,1 %; ! process identification (PID) of process macro PSHOWN$L_OWNER_TYPE = 4,0,32,1 %; ! owner type macro PSHOWN$Q_OWNER_ID = 8,0,0,0 %; literal PSHOWN$S_OWNER_ID = 8; ! thread environment block (TEB) ! ! Pshared Global Structure ! literal PSHGBL$S_PSHARED_GBL = 32; macro PSHGBL$Q_FLINK = 0,0,0,1 %; literal PSHGBL$S_FLINK = 8; ! flink to next pshared global structure macro PSHGBL$Q_BLINK = 8,0,0,1 %; literal PSHGBL$S_BLINK = 8; ! blink to previous pshared global structure macro PSHGBL$L_PID = 16,0,32,1 %; ! process identification of this process macro PSHGBL$L_IMGCNT = 20,0,32,1 %; ! image count for this process macro PSHGBL$Q_START_VA = 24,0,0,0 %; literal PSHGBL$S_START_VA = 8; ! starting VA of global section in process space ! ! Pshared Wait Structure ! literal PSHWT$S_PSHARED_WAIT = 56; macro PSHWT$Q_FLINK = 0,0,0,1 %; literal PSHWT$S_FLINK = 8; ! flink to next wait structure macro PSHWT$Q_BLINK = 8,0,0,1 %; literal PSHWT$S_BLINK = 8; ! blink to previous wait structure macro PSHWT$L_TYPE = 16,0,32,1 %; ! wait type macro PSHWT$L_PRIORITY = 20,0,32,1 %; ! thread priority macro PSHWT$L_PID = 24,0,32,1 %; ! process or thread identification macro PSHWT$L_PCB = 28,0,32,1 %; ! short pointer to process control block macro PSHWT$L_CTX = 32,0,32,1 %; ! thread context pointer macro PSHWT$L_IMGCNT = 36,0,32,1 %; ! image count for this process macro PSHWT$Q_TIMEOUT_ELE = 40,0,0,1 %; literal PSHWT$S_TIMEOUT_ELE = 8; ! pointer to timeout structure macro PSHWT$Q_MASTER = 48,0,0,1 %; literal PSHWT$S_MASTER = 8; ! pointer to pshared master ! ! Pshared Timout Structure ! literal PSHTIM$S_PSHARED_TIMOUT = 56; macro PSHTIM$Q_FLINK = 0,0,0,1 %; literal PSHTIM$S_FLINK = 8; ! flink to next timeout structure macro PSHTIM$Q_BLINK = 8,0,0,1 %; literal PSHTIM$S_BLINK = 8; ! blink to previous timeout structure macro PSHTIM$L_TYPE = 16,0,32,1 %; ! timeout type macro PSHTIM$L_SPARE1 = 20,0,32,1 %; ! spare field macro PSHTIM$Q_TIMEOUT = 24,0,0,0 %; literal PSHTIM$S_TIMEOUT = 8; ! timeout value for this structure macro PSHTIM$Q_OBJECT = 32,0,0,1 %; literal PSHTIM$S_OBJECT = 8; ! pointer to pshared object (CV or mutex) macro PSHTIM$Q_WAIT_ELE = 40,0,0,1 %; literal PSHTIM$S_WAIT_ELE = 8; ! pointer to wait structure macro PSHTIM$Q_MASTER = 48,0,0,1 %; literal PSHTIM$S_MASTER = 8; ! pointer to pshared master ! ! Pshared Object Structure ! literal PSHOBJ$S_PSHARED_OBJECT = 112; macro PSHOBJ$Q_FLINK = 0,0,0,1 %; literal PSHOBJ$S_FLINK = 8; ! flink to next pshared object macro PSHOBJ$Q_BLINK = 8,0,0,1 %; literal PSHOBJ$S_BLINK = 8; ! blink to previous pshared object macro PSHOBJ$Q_STATE = 16,0,0,1 %; literal PSHOBJ$S_STATE = 8; ! state of pshared object macro PSHOBJ$L_TYPE = 24,0,32,1 %; ! pshared object type (CV or mutex) macro PSHOBJ$L_STATUS = 28,0,32,1 %; ! status of this pshared object macro PSHOBJ$L_WAITERS = 32,0,32,1 %; ! count number of waiters macro PSHOBJ$L_RECC = 36,0,32,1 %; ! recursion depth macro PSHOBJ$Q_NAME = 40,0,0,0 %; literal PSHOBJ$S_NAME = 8; ! pointer to name macro PSHOBJ$R_OWNER = 48,0,0,0 %; literal PSHOBJ$S_OWNER = 16; ! embedded owner structure macro PSHOBJ$Q_CV_FRIEND = 64,0,0,1 %; literal PSHOBJ$S_CV_FRIEND = 8; ! pointer to associated pshared object macro PSHOBJ$Q_OBJ_REF = 64,0,0,0 %; literal PSHOBJ$S_OBJ_REF = 8; ! reference counter macro PSHOBJ$L_ABANDONED = 72,0,32,1 %; ! abandoned flag macro PSHOBJ$L_GSTX = 76,0,32,1 %; ! global section table index (GSTX) macro PSHOBJ$Q_GSTX_OFFSET = 80,0,0,0 %; literal PSHOBJ$S_GSTX_OFFSET = 8; ! offset within global section table (GST) macro PSHOBJ$Q_WAIT_FLINK = 88,0,0,1 %; literal PSHOBJ$S_WAIT_FLINK = 8; ! flink to queue of waiters on this pshared object macro PSHOBJ$Q_WAIT_BLINK = 96,0,0,1 %; literal PSHOBJ$S_WAIT_BLINK = 8; ! blink to queue of waiters on this pshared object macro PSHOBJ$Q_MASTER = 104,0,0,1 %; literal PSHOBJ$S_MASTER = 8; ! pointer to pshared master ! ! Pshared Hash Structure ! literal PSHHSH$S_PSHARED_HASH = 16; macro PSHHSH$Q_FLINK = 0,0,0,1 %; literal PSHHSH$S_FLINK = 8; ! flink to pshared object macro PSHHSH$Q_BLINK = 8,0,0,1 %; literal PSHHSH$S_BLINK = 8; ! blink to pshared object ! ! Pshared Master Structure ! literal PSHMAS$S_PSHARED_MASTER = 520; macro PSHMAS$L_STATUS = 0,0,32,1 %; ! pshared master status macro PSHMAS$L_GSTX = 4,0,32,1 %; ! global section table index macro PSHMAS$W_MBO = 8,0,16,0 %; ! must-be-one field macro PSHMAS$B_TYPE = 10,0,8,0 %; ! structure type (DYN$C_PSH) macro PSHMAS$B_SUBTYPE = 11,0,8,0 %; ! structure subtype (DYN$C_PSH_MAS) macro PSHMAS$L_OBJ_COUNT = 12,0,32,1 %; ! total number of pshared objects macro PSHMAS$Q_SIZE = 16,0,0,1 %; literal PSHMAS$S_SIZE = 8; ! size macro PSHMAS$L_CV_COUNT = 24,0,32,1 %; ! number of pshared CV's macro PSHMAS$L_MUTEX_COUNT = 28,0,32,1 %; ! number of pshared mutexes macro PSHMAS$R_POOLZONE = 32,0,0,0 %; literal PSHMAS$S_POOLZONE = 176; ! embedded poolzone region structure (includes 1 poolzone) macro PSHMAS$R_ZONE = 208,0,0,0 %; literal PSHMAS$S_ZONE = 192; ! embedded additional poolzone structures (two) macro PSHMAS$R_TQE = 400,0,0,0 %; literal PSHMAS$S_TQE = 64; ! embedded TQE structure macro PSHMAS$Q_OBJ_FLINK = 464,0,0,1 %; literal PSHMAS$S_OBJ_FLINK = 8; ! flink to pshared object queue macro PSHMAS$Q_OBJ_BLINK = 472,0,0,1 %; literal PSHMAS$S_OBJ_BLINK = 8; ! blink to pshared object queue macro PSHMAS$Q_TIMOUT_FLINK = 480,0,0,1 %; literal PSHMAS$S_TIMOUT_FLINK = 8; ! flink to timeout queue macro PSHMAS$Q_TIMOUT_BLINK = 488,0,0,1 %; literal PSHMAS$S_TIMOUT_BLINK = 8; ! blink to timeout queue macro PSHMAS$Q_GBL_FLINK = 496,0,0,1 %; literal PSHMAS$S_GBL_FLINK = 8; ! flink to queue of pshared global structures macro PSHMAS$Q_GBL_BLINK = 504,0,0,1 %; literal PSHMAS$S_GBL_BLINK = 8; ! blink to queue of pshared global structures macro PSHMAS$Q_OBJ_HASH_TBL = 512,0,0,1 %; literal PSHMAS$S_OBJ_HASH_TBL = 8; ! pointer to object hash table ! ! Pshared Array Structure ! literal PSHARY$S_PSHARED_ARRAY = 16; macro PSHARY$Q_MASTER = 0,0,0,1 %; literal PSHARY$S_MASTER = 8; ! long pointer to pshared master structure macro PSHARY$L_SPINLOCK = 8,0,32,1 %; ! short pointer to dynamic spinlock structure macro PSHARY$L_SPARE = 12,0,32,1 %; ! spare field ! ! Pshared Constant Definitions ! literal PSH$C_BAD = 0; literal PSH$C_MUTEX = 1; literal PSH$C_CV = 2; literal PSH$C_RWL = 3; literal PSH$C_STATE_BAD = 0; literal PSH$C_STATE_ACTIVE = 1; literal PSH$C_STATE_DELETING = 2; literal PSH$C_THREAD_AWAKENED = 0; literal PSH$C_THREAD_INTERRUPTED = 1; literal PSH$C_THREAD_SHOULD_TERMINATE = 2; literal PSH$C_THREAD_TIMED_OUT = 3; literal PSH$C_THREAD_RESTART = 4; literal PSH$C_THREAD_FIRST_ATTEMPT = 5; literal PSH$C_HOLDER_BAD = 0; literal PSH$C_HOLDER_MUTEX = 1; literal PSH$C_HOLDER_READ = 2; literal PSH$C_HOLDER_WRITE = 3; literal PSH$C_HOLDER_MUTEXWAIT = 4; literal PSH$C_HOLDER_WRITEWAIT = 5; literal PSH$C_HOLDER_CONDWAIT = 6; literal PSH$C_RWM_LOCK = 0; literal PSH$C_RWM_UNLOCK = 0; literal PSH$C_RWM_TRY = 1; literal PSH$C_RWM_READ = 2; literal PSH$C_RWM_WRITE = 4; literal PSH$C_RWM_FORCE = 8; literal PSH$C_CV_WAIT = 0; literal PSH$C_CV_SIGNAL = 0; literal PSH$C_CV_BROADCAST = 1; literal PSH$C_MOD_ABSTIME = 1; literal PSH$C_MOD_FASTPATH = 2; literal PSH$C_MOD_RECURSIVE = 4; literal PSH$C_MOD_ERRORCHECK = 8; literal PSH$C_OBJ_HASH_ENTRIES = 1024; literal PSH$M_OBJ_HASH_MASK = 1023; !*** MODULE $imsemdef *** ! ! Inner mode semaphore Definitions ! literal imsem_hist$K_LENGTH = 16; literal imsem_hist$S_imsem_hist = 16; macro imsem_hist$q_pc = 0,0,0,0 %; literal imsem_hist$s_pc = 8; macro imsem_hist$q_semaphore = 8,0,0,0 %; literal imsem_hist$s_semaphore = 8; literal imsem$m_kast_pending = %X'1'; literal imsem$m_east_pending = %X'2'; literal imsem$m_rs_waitrs = %X'4'; literal imsem$m_tm_waitrs = %X'8'; literal imsem$m_check_upcall = %X'10'; literal imsem$m_exclusive = %X'20'; literal imsem$k_hist_buf_cnt = 255; ! number of octaword history buffer entries literal IMSEM$C_ACQ = 1; literal IMSEM$C_SPIN = 2; literal IMSEM$C_REL = 3; literal imsem$S_imsem = 4096; macro imsem$r_imsem_union = 0,0,0,0 %; literal imsem$s_imsem_union = 8; macro imsem$q_imsem_quad = 0,0,0,0 %; literal imsem$s_imsem_quad = 8; ! First quad of semaphore macro imsem$w_owner_depth = 0,0,16,0 %; ! depth of nested acquisitions macro imsem$w_owner = 2,0,16,0 %; ! IM semaphore owner macro imsem$w_tolerant_count = 4,0,16,0 %; ! count of tolerant thread-safe activity macro imsem$w_flags = 6,0,16,0 %; ! Semaphore flags macro imsem$v_kast_pending = 6,0,1,0 %; macro imsem$v_east_pending = 6,1,1,0 %; macro imsem$v_rs_waitrs = 6,2,1,0 %; macro imsem$v_tm_waitrs = 6,3,1,0 %; macro imsem$v_check_upcall = 6,4,1,0 %; macro imsem$v_exclusive = 6,5,1,0 %; macro imsem$il_history_idx = 8,0,32,0 %; macro imsem$r_hist_buf = 16,0,0,0 %; literal imsem$s_hist_buf = 4080; !*** MODULE $PXMLDEF *** ! ! PXML structures: Data needed to define localities on Integrity cell-based ! systems, the underlying uinformation for setting up RADs. ! The structures must be defined in "reverse" order because ! of the way they reference each other. ! ! PXML_MEMORY: One per memory fragment within each locality. Contains ! start and end address of the fragment. ! literal PXML$S_PXML_MEMORY = 16; macro PXML$Q_BASE = 0,0,0,0 %; literal PXML$S_BASE = 8; ! Physical base address of fragment macro PXML$Q_END = 8,0,0,0 %; literal PXML$S_END = 8; ! Physical end address of fragment ! ! PXML_LOCALITY: One per populated locality. Contains locality and RAD ! numbers, count of CPUs (both real and ghost) and memory ! fragments, bitmap of CPUs, plus the calculated average ! & best costs and spread/variance (across all localities ! that contain CPUs) for access to memory in this fragment. ! ! An array of memory fragments is appended to each ! locality structure (first fragment is built in to the ! structure). ! ! Note 1: The spread is not a true standard deviation: no ! square root is taken and a multiplier (32) is used to ! increase accuracy because all calculations are performed ! on unsigned 32-bit integer values. ! ! Note 2: The MEM_COUNT quadword must immediately precede ! the first MEM_FRAGMENTS quadword pair and must be quadword ! aligned. ! ! Note 3: "Real" CPUs are those that actually exist in the ! locality. "Ghost" CPUs are those considered part of a ! locality because its memory is interleaved (CLM or ILM) ! and the CPU exists in one of the contributing localities. ! literal PXML$S_PXML_LOCALITY = 216; macro PXML$L_LOCALITY = 0,0,32,0 %; ! The locality number macro PXML$L_COST = 4,0,32,0 %; ! Offset of this locality in the LOCALITIES_BY_COST array macro PXML$L_RAD = 8,0,32,0 %; ! The RAD number macro PXML$L_LOCALITY_LENGTH = 12,0,32,0 %; ! Length of this structure (including all memory fragments) macro PXML$L_AVERAGE = 16,0,32,0 %; ! Average cost to access memory in this locality macro PXML$L_SPREAD = 20,0,32,0 %; ! Spread of costs to access memory in this locality macro PXML$L_CHEAPEST = 24,0,32,0 %; ! Cheapest cost to access memory in this non-CPU locality macro PXML$L_CPU_COUNT = 28,0,32,0 %; ! Count of actual CPUs in this locality macro PXML$L_GHOST_CPUS = 32,0,32,0 %; ! Count of CPUs considered as part of this non-CPU locality macro PXML$L_RAD_LIST_OFFSET = 36,0,32,0 %; ! Offset (from PXML base) to RAD preference array macro PXML$L_FRAGMENT_OFFSET = 40,0,32,0 %; ! Offset (from PXML base) to optimized fragment list ! (Where holes are ignored unless there's an ! intervening fragment from another locality) ! Also used to count the number of fragments in optimized list macro PXML$L_BASE_RADS = 44,0,0,1 %; literal PXML$S_BASE_RADS = 8; ! Best ILM or CLM RADs to be used by this RAD macro PXML$T_FILL_1 = 52,0,32,0 %; literal PXML$S_FILL_1 = 4; ! Remaining fields must be quadword aligned macro PXML$T_CPU_BITMAP = 56,0,0,0 %; literal PXML$S_CPU_BITMAP = 128; ! Bitmap of all CPUs (actual & ghost) in this locality macro PXML$Q_MEM_TOTAL = 184,0,0,0 %; literal PXML$S_MEM_TOTAL = 8; ! Total memory in this locality ! Keep the next two lines together **** macro PXML$Q_MEM_COUNT = 192,0,0,0 %; literal PXML$S_MEM_COUNT = 8; ! Number of memory fragments in this locality macro PXML$T_MEM_FRAGMENTS = 200,0,0,0 %; literal PXML$S_MEM_FRAGMENTS = 16; ! First memory fragment in this locality ! Keep the last two lines together **** ! ! PXML: The main structure containing pointers to the saved SLIT, ! SRAT, and LID array, various counts and internal pointers. ! One or more pages are allocated (in S2 space) for the ! structure, the saved SLIT, SRAT, and LID array, and all ! the additional bitmaps, arrays of pointers, the ! PXML_LOCALITY and their PXML_MEMORY substructures, ! and the PA-to-RAD conversion array. All the pointers in ! this structure point to locations following the structure. ! literal PXML$C_LENGTH = 104; ! Length of base PXML structure literal PXML$S_PXML = 104; macro PXML$L_SLIT_OFFSET = 0,0,32,0 %; ! Offset to saved SLIT macro PXML$L_SRAT_OFFSET = 4,0,32,0 %; ! Offset to saved SRAT macro PXML$L_LID_OFFSET = 8,0,32,0 %; ! Offset to LID array macro PXML$L_LOCALITY_BITMAP = 12,0,32,0 %; ! Offset to bitmap of all populated localities macro PXML$L_LOCALITY_CPUMAP = 16,0,32,0 %; ! Offset to bitmap of localities that contain CPUs macro PXML$L_LOCALITY_MEMMAP = 20,0,32,0 %; ! Offset to bitmap of localities that contain memory macro PXML$L_LOCALITIES_BY_LOC = 24,0,32,0 %; ! Three offsets to arrays of offsets to PXML_LOCALITY structures macro PXML$L_LOCALITIES_BY_COST = 28,0,32,0 %; ! ... first ordered by locality, second by spread/cost, macro PXML$L_LOCALITIES_BY_RAD = 32,0,32,0 %; ! ... third in best RAD order (localities with CPUs then increasing ! ... spread/cost for the remainder) macro PXML$L_PA_RAD_ARRAY = 36,0,32,0 %; ! Offset to array of PA-to-RAD conversions macro PXML$L_NEXT_FREE = 40,0,32,0 %; ! Offset to next free location in page(s) macro PXML$L_PXML_LENGTH = 44,0,32,0 %; ! Length of available area allocated (rounded up to a complete page) macro PXML$L_SLIT_SIZE = 48,0,32,0 %; ! Size of saved SLIT macro PXML$L_SRAT_SIZE = 52,0,32,0 %; ! Size of saved SRAT macro PXML$L_LID_COUNT = 56,0,32,0 %; ! Number of entries in LID array (from HWRPB$IQ_NPROC) macro PXML$L_LOCALITIES = 60,0,32,0 %; ! Total number of localities (from SLIT) macro PXML$L_RADS = 64,0,32,0 %; ! Number of populated localities macro PXML$L_CPUS = 68,0,32,0 %; ! Total number of CPUs macro PXML$L_FRAGMENTS = 72,0,32,0 %; ! Total number of memory fragments macro PXML$L_BITMAP_LENGTH = 76,0,32,0 %; ! Length of each of the three locality bitmaps macro PXML$L_CPU_RAD_SHIFT = 80,0,32,0 %; ! CPU-to-RAD shift value (or 0xFFFFFFFF) macro PXML$L_PA_RAD_ENTRIES = 84,0,32,0 %; ! Eventual number of entries in the PA-to-RAD array macro PXML$L_SYIMAP_OFFSET = 88,0,32,0 %; ! Offset to the saved copy of the SYI memory map macro PXML$L_SYIMAP_ENTRIES = 92,0,32,0 %; ! Number of entries in the SYI memory map macro PXML$L_BASE_RAD = 96,0,32,1 %; ! Best ILM or CLM RAD (first in cost list) macro PXML$L_ALT_BASE_RAD = 100,0,32,1 %; ! Second base RAD (if same spread as first) macro PXML$T_FILL_2 = 104,0,0,0 %; ! Ensure the base structure is an exact number of quadwords ! All calculations of average and spread/deviation are done as 32-bit ! unsigned integers. Therefore, in order to improve the accuracy ! (or granularity) we apply a shift factor to the raw values. If set ! too low, we don't gain enough accuracy. If set too large, the squared ! sums will exceed a longword. Right now we're using 5 (i.e. multiply ! by 32). literal PXML$C_SPREAD_SHIFT = 5; ! The initial space used to build the PXML and its substructures is ! allocated within the module that initializes it (in SYSBOOT or ! EXEC_INIT). Later it is copied to pages in "fair" memory for use ! by the running system. Right now we're allocating eight pages. literal PXML$C_PXML_SIZE = 65536; ! If a RAD has little memory (less than or equal to PXML$C_MINIMUM_RAD_MEMORY) ! then it probably only has firmware-reserved space. If there's only one RAD ! with more than this amount of memory, consider the system to be all-ILM ! and don't set up RADs. PXML$C_MINIMUM_RAD_MEMORY is currently set at 256MB. literal PXML$C_MINIMUM_RAD_MEMORY = 268435456; !*** MODULE $ACMEAGENT_DATA_DEF IDENT X-1 *** ! + ! ! Miscellaneous constants ! ! - literal acme$k_maxchar_acme_ident = 64; ! Maximum length (in characters) of ! ACME ident literal acme$k_maxchar_acme_activity = 64; ! Maximum length (in characters) of ! ACME activity (status) information ! + ! ! ACMEWQE - ACM Work Queue Entry. ! ! - literal acmewqeflg$k_min_acme_flag = 0; literal acmewqeflg$m_acme_flags = %X'FFFF'; literal acmewqeflg$k_max_acme_flag = 15; literal acmewqeflg$m_dispatcher_flags = %X'FFFF0000'; literal acmewqeflg$m_dialogue_possible = %X'10000'; literal acmewqeflg$m_ast_received = %X'20000'; literal acmewqeflg$m_report_phase_event = %X'40000'; literal acmewqeflg$m_mask_status = %X'80000'; literal acmewqeflg$m_trace_enabled = %X'100000'; literal acmewqeflg$m_abort_request = %X'40000000'; literal acmewqeflg$m_failed_request = %X'80000000'; literal acmewqeflg$k_min_fi_flag = 0; literal acmewqeflg$k_phase_done = 0; literal acmewqeflg$m_phase_done = %X'1'; literal acmewqeflg$k_no_retry = 1; literal acmewqeflg$m_no_retry = %X'2'; literal acmewqeflg$k_max_fi_flag = 1; literal acmewqeflg$k_min_auth_flag = 12; literal acmewqeflg$k_preauthenticated = 12; literal acmewqeflg$m_preauthenticated = %X'1000'; literal acmewqeflg$k_no_external_auth = 13; literal acmewqeflg$m_no_external_auth = %X'2000'; literal acmewqeflg$k_skip_new_password = 14; literal acmewqeflg$m_skip_new_password = %X'4000'; literal acmewqeflg$k_null_net_user = 15; literal acmewqeflg$m_null_net_user = %X'8000'; literal acmewqeflg$k_max_auth_flag = 15; literal acmewqeflg$S_acmewqeflg = 4; ! ! Overall flags structure ! macro acmewqeflg$l_flags_struct = 0,0,32,0 %; ! Composite field ! ! Bits [15:0] = ACME settable ! Function independent flags are assigned upward. ! Function dependent flags are assigned downward. ! macro acmewqeflg$v_acme_flags = 0,0,16,0 %; literal acmewqeflg$s_acme_flags = 16; ! ! Bits [31:16] = ACM Dispatcher controlled ! macro acmewqeflg$v_dispatcher_flags = 0,16,16,0 %; literal acmewqeflg$s_dispatcher_flags = 16; ! ! ACM Dispatcher controlled flags ! macro acmewqeflg$v_dialogue_possible = 0,16,1,0 %; ! Dialogue possible macro acmewqeflg$v_ast_received = 0,17,1,0 %; ! AST recieved macro acmewqeflg$v_report_phase_event = 0,18,1,0 %; ! Phase transition event ! processing has already been ! requested for this WQE. macro acmewqeflg$v_mask_status = 0,19,1,0 %; ! Indicates $ACM[W] service will mask ! the reporting of privileged status macro acmewqeflg$v_trace_enabled = 0,20,1,0 %; ! Server tracing is enabled macro acmewqeflg$v_abort_request = 0,30,1,0 %; ! Abort request macro acmewqeflg$v_failed_request = 0,31,1,0 %; ! An ACME returned a non-success status ! (failed request processing should occur) ! ! ACME setable, function independent flags ! macro acmewqeflg$v_phase_done = 0,0,1,0 %; ! Phase completed macro acmewqeflg$v_no_retry = 0,1,1,0 %; ! Retry not possible ! ! Flags applicable to AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD ! macro acmewqeflg$v_preauthenticated = 0,12,1,0 %; ! Pre-authenticated macro acmewqeflg$v_no_external_auth = 0,13,1,0 %; ! Authenticate natively macro acmewqeflg$v_skip_new_password = 0,14,1,0 %; ! Skip new password processing macro acmewqeflg$v_null_net_user = 0,15,1,0 %; ! Special no-username request literal acmewqeflg$k_length = 4; literal acmewqeval$S_acmewqeval = 12; macro acmewqeval$l_acme_id = 0,0,32,0 %; literal acmewqeval$s_acme_id = 4; ! ID of ACME which set the value macro acmewqeval$l_phase = 4,0,32,0 %; ! Phase during which value was set macro acmewqeval$L_VALUE = 8,0,32,0 %; ! Value literal acmewqeval$k_length = 12; literal acmewqeitm$S_acmewqeitm = 16; macro acmewqeitm$l_acme_id = 0,0,32,0 %; literal acmewqeitm$s_acme_id = 4; ! ID of ACME which set the item macro acmewqeitm$l_phase = 4,0,32,0 %; ! Phase during which item was set macro acmewqeitm$l_length = 8,0,32,0 %; ! Size, in bytes, of data macro acmewqeitm$ps_pointer = 12,0,32,1 %; ! Address of data literal acmewqeitm$k_length = 16; ! ! Function independent WQE extension ! ! Note: ! ! The function independent WQE extension contains no fields ! at present, the structure declaration is specified simply ! to declare the applicable datatype. ! literal acmewqefix$k_length = 0; literal acmewqefix$S_acmewqefix = 4; ! ! WQE extension applicable to AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD ! literal acmewqe$k_min_auth_param = 256; literal acmewqe$k_system_password = 256; literal acmewqe$k_principal_name = 257; literal acmewqe$k_principal_name_out = 258; literal acmewqe$k_vms_username = 259; literal acmewqe$k_password_1 = 260; literal acmewqe$k_password_2 = 261; literal acmewqe$k_new_password_1 = 262; literal acmewqe$k_new_password_2 = 263; literal acmewqe$k_max_auth_param = 263; literal acmewqeax$S_acmewqeax = 296; macro acmewqeax$l_new_password_flags = 0,0,32,0 %; literal acmewqeax$s_new_password_flags = 4; ! Password change request flags macro acmewqeax$l_logon_flags = 4,0,32,0 %; literal acmewqeax$s_logon_flags = 4; ! Logon flags macro acmewqeax$r_logon_stats_vms = 8,0,0,0 %; literal acmewqeax$s_logon_stats_vms = 48; ! Native (OpenVMS) logon statistics macro acmewqeax$r_logon_stats_doi = 56,0,0,0 %; literal acmewqeax$s_logon_stats_doi = 112; ! Non-native (non-OpenVMS) logon statistics macro acmewqeax$r_system_password = 168,0,0,0 %; literal acmewqeax$s_system_password = 16; ! System password macro acmewqeax$r_principal_name = 184,0,0,0 %; literal acmewqeax$s_principal_name = 16; ! Raw (unprocessed) principal name macro acmewqeax$r_principal_name_out = 200,0,0,0 %; literal acmewqeax$s_principal_name_out = 16; ! Principal name macro acmewqeax$r_vms_username = 216,0,0,0 %; literal acmewqeax$s_vms_username = 16; ! Mapped OpenVMS username macro acmewqeax$r_password_1 = 232,0,0,0 %; literal acmewqeax$s_password_1 = 16; ! Password 1 macro acmewqeax$r_password_2 = 248,0,0,0 %; literal acmewqeax$s_password_2 = 16; ! Password 2 macro acmewqeax$r_new_password_1 = 264,0,0,0 %; literal acmewqeax$s_new_password_1 = 16; ! New password 1 macro acmewqeax$r_new_password_2 = 280,0,0,0 %; literal acmewqeax$s_new_password_2 = 16; ! New password 2 literal acmewqeax$k_length = 296; ! ! WQE extension applicable to Agent Initialization ! literal acmewqeaix$S_acmewqeaix = 4; macro acmewqeaix$ps_agent_name = 0,0,32,1 %; ! address of string descriptor literal acmewqeaix$k_length = 4; ! ! WQE extension applicable to Agent startup (Enabling) ! literal acmewqeaex$S_acmewqeaex = 4; macro acmewqeaex$l_concurrent_requests = 0,0,32,0 %; ! maximum at a time literal acmewqeaex$k_length = 4; ! ! WQE extension applicable to Agent shutdown (Disabling) ! literal acmewqeadx$S_acmewqeadx = 4; literal acmewqeadx$k_length = 4; ! ! WQE extension applicable to Agent Standby ! literal acmewqeasx$S_acmewqeasx = 4; literal acmewqeasx$k_length = 4; ! ! Function dependent WQE extension ! literal acmewqefdx$S_acmewqefdx = 296; macro acmewqefdx$r_auth_pwd = 0,0,0,0 %; literal acmewqefdx$s_auth_pwd = 296; ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD literal acmewqefdx$k_length = 296; literal acmewqe$k_minor_id_000 = 0; ! original V7.2-1 WQE supporting only COM literal acmewqe$k_minor_id_001 = 1; ! subsequent extension of the WQE literal acmewqe$k_minor_id = 0; literal acmewqe$k_major_id_001 = 1; literal acmewqe$k_major_id = 1; literal acmewqe$k_revision = 256; literal acmewqe$S_acmewqe = 152; macro acmewqe$ps_flink = 0,0,32,1 %; ! WQE list forward link macro acmewqe$ps_blink = 4,0,32,1 %; ! WQE list backward link ! ! ACME visible fields ! macro acmewqe$w_size = 8,0,16,0 %; ! Structure size, in bytes macro acmewqe$w_revision_level = 10,0,16,0 %; literal acmewqe$s_revision_level = 2; ! Structure revision level ! ! WQE Data Structure minor versions ! macro acmewqe$l_flags = 12,0,32,0 %; literal acmewqe$s_flags = 4; ! Status/control flags macro acmewqe$l_function = 16,0,32,0 %; literal acmewqe$s_function = 4; ! Function code/modifiers macro acmewqe$l_dialogue_flags = 20,0,32,0 %; literal acmewqe$s_dialogue_flags = 4; ! Dialogue support flags macro acmewqe$l_requestor_profile = 24,0,32,0 %; ! Requestor's security profile ! (Persona ID) macro acmewqe$l_requestor_mode = 28,0,32,0 %; ! Requestor's mode macro acmewqe$l_requestor_pid = 32,0,32,0 %; ! Requestor's PID macro acmewqe$l_target_acme_id = 36,0,32,0 %; literal acmewqe$s_target_acme_id = 4; ! Agent id of ACME at which ! this request is directed macro acmewqe$l_designated_acme_id = 40,0,32,0 %; literal acmewqe$s_designated_acme_id = 4; ! Agent id of ACME that ! assumed processing control macro acmewqe$l_designated_cred = 44,0,32,0 %; ! Type of credentials associated ! with the designated ACME macro acmewqe$l_current_acme_id = 48,0,32,0 %; literal acmewqe$s_current_acme_id = 4; ! Agent id of current ACME macro acmewqe$r_status = 52,0,0,0 %; literal acmewqe$s_status = 12; ! First non-success status returned by an ACME macro acmewqe$r_secondary_status = 64,0,0,0 %; literal acmewqe$s_secondary_status = 12; ! Secondary (protected) status macro acmewqe$r_acme_status = 76,0,0,0 %; literal acmewqe$s_acme_status = 12; ! ACME specific status macro acmewqe$ps_func_ind_params = 88,0,32,1 %; ! Function independent extension macro acmewqe$ps_func_dep_params = 92,0,32,1 %; ! Function dependent extension macro acmewqe$ps_itemlist = 96,0,32,1 %; ! ACME independent item list macro acmewqe$ps_acme_itemlist = 100,0,32,1 %; ! ACME specific item list macro acmewqe$q_ast_context = 104,0,0,0 %; literal acmewqe$s_ast_context = 8; ! AST context for which the ! AST has been recieved macro acmewqe$r_locale = 112,0,0,0 %; literal acmewqe$s_locale = 16; ! Locale specifier macro acmewqe$r_service_name = 128,0,0,0 %; literal acmewqe$s_service_name = 16; ! Service (client) specifier macro acmewqe$l_timeout_seconds = 144,0,32,0 %; ! seconds since system boot ! at which this request can ! be timed out. literal acmewqe$k_length = 152; ! Length of fixed portion ! + ! ! ACMEOUTITM - Item list output item data buffer ! ! - literal acmeoutitm$k_length = 16; ! Length of fixed portion literal acmeoutitm$S_acmeoutitm = 20; macro acmeoutitm$l_acme_id = 0,0,32,0 %; literal acmeoutitm$s_acme_id = 4; ! ID of ACME which set the item entry macro acmeoutitm$l_phase = 4,0,32,0 %; ! Phase during which item was set macro acmeoutitm$w_size = 8,0,16,0 %; ! Structure size, in bytes macro acmeoutitm$w_length = 12,0,16,0 %; ! Actual size, in bytes, of data macro acmeoutitm$w_max_length = 14,0,16,0 %; ! Size, in bytes, of data buffer macro acmeoutitm$b_data = 16,0,8,0 %; literal acmeoutitm$s_data = 1; ! Data ! + ! ! ACMERSRC - ACME Agent Resource Requirements Block ! ! - literal acmepq$S_acmepq = 32; ! Process quota requirements macro acmepq$l_memory = 0,0,32,0 %; ! Virtual address space use macro acmepq$l_channel = 4,0,32,0 %; ! I/O channels macro acmepq$l_direct_io = 8,0,32,0 %; ! Direct I/O count macro acmepq$l_buffer_io = 12,0,32,0 %; ! Buffered I/O count macro acmepq$l_buffer_io_mem = 16,0,32,0 %; ! Buffered I/O memory usage macro acmepq$l_ast = 20,0,32,0 %; ! AST count macro acmepq$l_tqe = 24,0,32,0 %; ! TQE count macro acmepq$l_lock = 28,0,32,0 %; ! Lock count literal acmersrc$k_minor_id_000 = 0; literal acmersrc$k_minor_id = 0; literal acmersrc$k_major_id_001 = 1; ! VMS V7.2-1 literal acmersrc$k_major_id = 1; literal acmersrc$k_revision = 256; literal acmersrc$S_acmersrc = 80; ! ! General resource requirements ! macro acmersrc$q_privileges = 0,0,0,0 %; literal acmersrc$s_privileges = 8; ! Operating privilege macro acmersrc$w_size = 8,0,16,0 %; ! Structure size, in bytes macro acmersrc$w_revision_level = 10,0,16,0 %; literal acmersrc$s_revision_level = 2; ! Structure revision level macro acmersrc$l_stack_size = 12,0,32,0 %; ! Maximum operating stack macro acmersrc$r_agent_quotas = 16,0,0,0 %; literal acmersrc$s_agent_quotas = 32; ! General process quotas ! ! Per-request resource requirements ! macro acmersrc$r_request_quotas = 48,0,0,0 %; literal acmersrc$s_request_quotas = 32; ! Per-request process quotas literal acmersrc$k_length = 80; ! + ! ! ACMEDTFLG - Formatting control flags for ACME$CB_FORMAT_DATE_TIME callback ! ! - literal acmedtflg$m_time_fields = %X'1'; literal acmedtflg$m_date_fields = %X'2'; literal acmedtflg$m_local = %X'40000000'; literal acmedtflg$m_ucs = %X'80000000'; literal acmedtflg$S_acmedtflg = 4; macro acmedtflg$l_control_flags = 0,0,32,0 %; ! Composite field macro acmedtflg$v_time_fields = 0,0,1,0 %; ! Include time fields macro acmedtflg$v_date_fields = 0,1,1,0 %; ! Include date fields macro acmedtflg$v_local = 0,30,1,0 %; ! Use default locale for the local ! system in lieu of WQE locale macro acmedtflg$v_ucs = 0,31,1,0 %; ! Convert to UCS-4 encoding literal acmedtflg$k_length = 4; ! + ! ! ACMEKCV - ACM Kernel Callback Vector ! ! - literal acme$k_minor_id_000 = 0; literal acme$k_minor_id_001 = 0; literal acme$k_minor_id = 0; ! The default is still 000 literal acme$k_major_id_001 = 1; literal acme$k_major_id = 1; literal acme$k_revision = 256; literal acmekcv$k_minor_id_000 = 0; ! original V7.2-1 callback list literal acmekcv$k_minor_id_001 = 1; ! supporting Latin1<->UCS conversion literal acmekcv$k_minor_id = 1; literal acmekcv$k_major_id_001 = 1; literal acmekcv$k_major_id = 1; literal acmekcv$k_revision = 257; literal acme$k_report_attributes = 0; literal acme$k_send_operator = 1; literal acme$k_send_logfile = 2; literal acme$k_allocate_acme_vm = 3; literal acme$k_deallocate_acme_vm = 4; literal acme$k_allocate_wqe_vm = 5; literal acme$k_deallocate_wqe_vm = 6; literal acme$k_set_designated_doi = 7; literal acme$k_set_2nd_status = 8; literal acme$k_set_acme_status = 9; literal acme$k_set_wqe_flag = 10; literal acme$k_set_wqe_parameter = 11; literal acme$k_set_output_item = 12; literal acme$k_set_logon_flag = 13; literal acme$k_set_logon_stats_vms = 14; literal acme$k_set_logon_stats_doi = 15; literal acme$k_set_phase_event = 16; literal acme$k_queue_dialogue = 17; literal acme$k_cancel_dialogue = 18; literal acme$k_acquire_acme_ast = 19; literal acme$k_release_acme_ast = 20; literal acme$k_acquire_wqe_ast = 21; literal acme$k_release_wqe_ast = 22; literal acme$k_acquire_acme_rmsast = 23; literal acme$k_release_acme_rmsast = 24; literal acme$k_acquire_wqe_rmsast = 25; literal acme$k_release_wqe_rmsast = 26; literal acme$k_acquire_resource = 27; literal acme$k_release_resource = 28; literal acme$k_issue_credentials = 29; literal acme$k_format_date_time = 30; literal acme$k_report_activity = 31; literal acme$k_ucs_to_latin1 = 32; literal acme$k_latin1_to_ucs = 33; literal acme$k_set_new_pwd_flags = 34; literal acme$k_kcv_count = 35; literal acmekcv$S_acmekcv = 144; macro acmekcv$w_acm_revision_level = 0,0,16,0 %; literal acmekcv$s_acm_revision_level = 2; ! ACM kernel revision level macro acmekcv$w_revision_level = 2,0,16,0 %; literal acmekcv$s_revision_level = 2; ! Structure revision level macro acmekcv$cb_report_attributes = 4,0,32,1 %; ! Report resource requirements macro acmekcv$cb_send_operator = 8,0,32,1 %; ! Send a message to the operator macro acmekcv$cb_send_logfile = 12,0,32,1 %; ! Write a message in the log file macro acmekcv$cb_allocate_acme_vm = 16,0,32,1 %; ! Allocate a block of memory macro acmekcv$cb_deallocate_acme_vm = 20,0,32,1 %; ! Deallocate a block of memory macro acmekcv$cb_allocate_wqe_vm = 24,0,32,1 %; ! Allocate a block of memory macro acmekcv$cb_deallocate_wqe_vm = 28,0,32,1 %; ! Deallocate a block of memory macro acmekcv$cb_set_designated_doi = 32,0,32,1 %; ! Declare DOI accepting request macro acmekcv$cb_set_2nd_status = 36,0,32,1 %; ! Report secondary (protected) status macro acmekcv$cb_set_acme_status = 40,0,32,1 %; ! Report ACME specific status macro acmekcv$cb_set_wqe_flag = 44,0,32,1 %; ! Set WQE status/control flag macro acmekcv$cb_set_wqe_parameter = 48,0,32,1 %; ! Set WQE data item macro acmekcv$cb_set_output_item = 52,0,32,1 %; ! Set output item macro acmekcv$cb_set_logon_flag = 56,0,32,1 %; ! Set logon status flag macro acmekcv$cb_set_logon_stats_vms = 60,0,32,1 %; ! Report native (OpenVMS) logon statistics macro acmekcv$cb_set_logon_stats_doi = 64,0,32,1 %; ! Reprot non-native (non-OpenVMS) logon statistics macro acmekcv$cb_set_phase_event = 68,0,32,1 %; ! Set phase transition notification macro acmekcv$cb_queue_dialogue = 72,0,32,1 %; ! Queue a dialogue item set macro acmekcv$cb_cancel_dialogue = 76,0,32,1 %; ! Dismiss pending dialogue macro acmekcv$cb_acquire_acme_ast = 80,0,32,1 %; ! Establish a non-RMS AST context macro acmekcv$cb_release_acme_ast = 84,0,32,1 %; ! Dismiss non-RMS AST context macro acmekcv$cb_acquire_wqe_ast = 88,0,32,1 %; ! Establish a non-RMS AST context macro acmekcv$cb_release_wqe_ast = 92,0,32,1 %; ! Dismiss non-RMS AST context macro acmekcv$cb_acquire_acme_rmsast = 96,0,32,1 %; ! Establish an RMS AST context macro acmekcv$cb_release_acme_rmsast = 100,0,32,1 %; ! Dismiss RMS AST context macro acmekcv$cb_acquire_wqe_rmsast = 104,0,32,1 %; ! Establish an RMS AST context macro acmekcv$cb_release_wqe_rmsast = 108,0,32,1 %; ! Dismiss RMS AST context macro acmekcv$cb_acquire_resource = 112,0,32,1 %; ! Acquire an ACME specific resource macro acmekcv$cb_release_resource = 116,0,32,1 %; ! Release an ACME specific resource macro acmekcv$cb_issue_credentials = 120,0,32,1 %; ! Issue security credentials macro acmekcv$cb_format_date_time = 124,0,32,1 %; ! Format date and time macro acmekcv$cb_report_activity = 128,0,32,1 %; ! Report resource requirements ! ! The following cells are only meaningful if ACMEKCV$W_REVISION_LEVEL ! contains ACMEKCV$K_MAJOR_ID_001/ACMEKCV$K_MINOR_ID_001 or higher. ! macro acmekcv$cb_ucs_to_latin1 = 132,0,32,1 %; ! Convert UCS2_4 to Latin1 macro acmekcv$cb_latin1_to_ucs = 136,0,32,1 %; ! Convert Latin1 to UCS2_4 macro acmekcv$cb_set_new_pwd_flags = 140,0,32,1 %; ! Set new password flag literal acmekcv$k_length = 144; !*** MODULE $ACMEAGENT_CO_DEF IDENT X-1 *** ! + ! ! ACME Agent Callout Routines Prototypes ! ! - ! ! acme$ast_routine kcb_vector, acme_context, wqe, wqe_context, ! ast_context, ast_parameter ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! ast_context = address of quadword containing the AST context id ! (parameter) returned to the agent when acquiring ! the AST context ! ast_parameter = addesss of quadword containing ACME specific value ! specified by the agent when acquiring the AST context ! KEYWORDMACRO $acme_ast_routine (kcb_vector,acme_context,wqe,wqe_context ,ast_context,ast_parameter) = BEGIN EXTERNAL ROUTINE acme$ast_routine : BLISS ADDRESSING_MODE (GENERAL); acme$ast_routine (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(ast_context, %QUOTE ast_context) , SDL$$ACMEAGENT_CO_DEF_REQ(ast_parameter, %QUOTE ast_parameter) )) END %; ! ! acme$ast_routine kcb_vector, acme_context, wqe, wqe_context, ! ast_context, rms_parameter ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! ast_context = address of longword containing the AST context id ! (parameter) returned to the agent when acquiring ! the AST context ! rms_context = addesss of RMS structure associated with this AST ! (the ...$L_CTX field contains the AST parameter ! specified by the agent when acquiring the AST context) ! KEYWORDMACRO $acme_rmsast_routine (kcb_vector,acme_context,wqe ,wqe_context,ast_context,rms_context) = BEGIN EXTERNAL ROUTINE acme$rmsast_routine : BLISS ADDRESSING_MODE (GENERAL); acme$rmsast_routine (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(ast_context, %QUOTE ast_context) , SDL$$ACMEAGENT_CO_DEF_REQ(rms_context, %QUOTE rms_context) )) END %; ! ! Agent Initialize ! ! acme$co_agent_initialize kcb_vector, acme_context, wqe ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! KEYWORDMACRO $acme_co_agent_initialize (kcb_vector,acme_context ,wqe) = BEGIN EXTERNAL ROUTINE acme$co_agent_initialize : BLISS ADDRESSING_MODE (GENERAL); acme$co_agent_initialize (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) )) END %; ! ! Agent Shutdown ! ! acme$co_agent_shutdown kcb_vector, acme_context, wqe ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! KEYWORDMACRO $acme_co_agent_shutdown (kcb_vector,acme_context ,wqe) = BEGIN EXTERNAL ROUTINE acme$co_agent_shutdown : BLISS ADDRESSING_MODE (GENERAL); acme$co_agent_shutdown (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) )) END %; ! ! Agent Standby ! ! acme$co_agent_standby kcb_vector, acme_context, wqe ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! KEYWORDMACRO $acme_co_agent_standby (kcb_vector,acme_context,wqe) = BEGIN EXTERNAL ROUTINE acme$co_agent_standby : BLISS ADDRESSING_MODE (GENERAL); acme$co_agent_standby (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) )) END %; ! ! Agent Startup ! ! acme$co_agent_startup kcb_vector, acme_context, wqe ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! concurrency_factor = number indicating extent of parallelism ! KEYWORDMACRO $acme_co_agent_startup (kcb_vector,acme_context,wqe ,x_factor) = BEGIN EXTERNAL ROUTINE acme$co_agent_startup : BLISS ADDRESSING_MODE (GENERAL); acme$co_agent_startup (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(x_factor, %QUOTE x_factor) )) END %; ! ! EVENT function ! ! acme$co_event kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_event (kcb_vector,acme_context,wqe,wqe_context ,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_event : BLISS ADDRESSING_MODE (GENERAL); acme$co_event (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! QUERY function ! ! acme$co_query kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_query (kcb_vector,acme_context,wqe,wqe_context ,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_query : BLISS ADDRESSING_MODE (GENERAL); acme$co_query (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD ACCEPT_PASSWORDS phase processing ! ! acme$co_accept_passwords kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_accept_passwords (kcb_vector,acme_context ,wqe,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_accept_passwords : BLISS ADDRESSING_MODE (GENERAL); acme$co_accept_passwords (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD ACCEPT_PRINCIPAL phase processing ! ! acme$co_accept_principal kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_accept_principal (kcb_vector,acme_context ,wqe,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_accept_principal : BLISS ADDRESSING_MODE (GENERAL); acme$co_accept_principal (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD ANCILLARY_MECH_1 phase processing ! ! acme$co_ancillary_mech_1 kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_ancillary_mech_1 (kcb_vector,acme_context ,wqe,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_ancillary_mech_1 : BLISS ADDRESSING_MODE (GENERAL); acme$co_ancillary_mech_1 (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD ANCILLARY_MECH_2 phase processing ! ! acme$co_ancillary_mech_2 kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_ancillary_mech_2 (kcb_vector,acme_context ,wqe,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_ancillary_mech_2 : BLISS ADDRESSING_MODE (GENERAL); acme$co_ancillary_mech_2 (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD ANCILLARY_MECH_3 phase processing ! ! acme$co_ancillary_mech_3 kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_ancillary_mech_3 (kcb_vector,acme_context ,wqe,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_ancillary_mech_3 : BLISS ADDRESSING_MODE (GENERAL); acme$co_ancillary_mech_3 (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD ANNOUNCE phase processing ! ! acme$co_announce kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_announce (kcb_vector,acme_context,wqe,wqe_context ,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_announce : BLISS ADDRESSING_MODE (GENERAL); acme$co_announce (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD AUTHENTICATE phase processing ! ! acme$co_authenticate kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_authenticate (kcb_vector,acme_context,wqe ,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_authenticate : BLISS ADDRESSING_MODE (GENERAL); acme$co_authenticate (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD AUTHORIZE phase processing ! ! acme$co_authorize kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_authorize (kcb_vector,acme_context,wqe,wqe_context ,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_authorize : BLISS ADDRESSING_MODE (GENERAL); acme$co_authorize (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD AUTOLOGON phase processing ! ! acme$co_autologon kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_autologon (kcb_vector,acme_context,wqe,wqe_context ,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_autologon : BLISS ADDRESSING_MODE (GENERAL); acme$co_autologon (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD CREDENTIALS phase processing ! ! acme$co_credentials kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_credentials (kcb_vector,acme_context,wqe ,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_credentials : BLISS ADDRESSING_MODE (GENERAL); acme$co_credentials (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD FINISH phase processing ! ! acme$co_finish kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_finish (kcb_vector,acme_context,wqe,wqe_context ,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_finish : BLISS ADDRESSING_MODE (GENERAL); acme$co_finish (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD INITIALIZE phase processing ! ! acme$co_initialize kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_initialize (kcb_vector,acme_context,wqe ,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_initialize : BLISS ADDRESSING_MODE (GENERAL); acme$co_initialize (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD MAP_PRINCIPAL phase processing ! ! acme$co_map_principal kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_map_principal (kcb_vector,acme_context,wqe ,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_map_principal : BLISS ADDRESSING_MODE (GENERAL); acme$co_map_principal (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD LOGON_INFORMATION phase processing ! ! acme$co_logon_information kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_logon_information (kcb_vector,acme_context ,wqe,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_logon_information : BLISS ADDRESSING_MODE (GENERAL); acme$co_logon_information (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD MESSAGES phase processing ! ! acme$co_messages kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_messages (kcb_vector,acme_context,wqe,wqe_context ,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_messages : BLISS ADDRESSING_MODE (GENERAL); acme$co_messages (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD NEW_PASSWORD_1 phase processing ! ! acme$co_new_password_1 kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_new_password_1 (kcb_vector,acme_context ,wqe,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_new_password_1 : BLISS ADDRESSING_MODE (GENERAL); acme$co_new_password_1 (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD NEW_PASSWORD_2 phase processing ! ! acme$co_new_password_2 kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_new_password_2 (kcb_vector,acme_context ,wqe,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_new_password_2 : BLISS ADDRESSING_MODE (GENERAL); acme$co_new_password_2 (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD NOTICES phase processing ! ! acme$co_notices kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_notices (kcb_vector,acme_context,wqe,wqe_context ,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_notices : BLISS ADDRESSING_MODE (GENERAL); acme$co_notices (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD PASSWORD_1 phase processing ! ! acme$co_password_1 kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_password_1 (kcb_vector,acme_context,wqe ,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_password_1 : BLISS ADDRESSING_MODE (GENERAL); acme$co_password_1 (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD PASSWORD_2 phase processing ! ! acme$co_password_2 kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_password_2 (kcb_vector,acme_context,wqe ,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_password_2 : BLISS ADDRESSING_MODE (GENERAL); acme$co_password_2 (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD PRINCIPAL_NAME phase processing ! ! acme$co_principal_name kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_principal_name (kcb_vector,acme_context ,wqe,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_principal_name : BLISS ADDRESSING_MODE (GENERAL); acme$co_principal_name (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD QUALIFY_PASSWORD_1 phase processing ! ! acme$co_qualify_password_1 kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_qualify_password_1 (kcb_vector,acme_context ,wqe,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_qualify_password_1 : BLISS ADDRESSING_MODE (GENERAL); acme$co_qualify_password_1 (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD QUALIFY_PASSWORD_2 phase processing ! ! acme$co_qualify_password_2 kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_qualify_password_2 (kcb_vector,acme_context ,wqe,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_qualify_password_2 : BLISS ADDRESSING_MODE (GENERAL); acme$co_qualify_password_2 (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD SET_PASSWORDS phase processing ! ! acme$co_set_passwords kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_set_passwords (kcb_vector,acme_context,wqe ,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_set_passwords : BLISS ADDRESSING_MODE (GENERAL); acme$co_set_passwords (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD SYSTEM_PASSWORD phase processing ! ! acme$co_system_password kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_system_password (kcb_vector,acme_context ,wqe,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_system_password : BLISS ADDRESSING_MODE (GENERAL); acme$co_system_password (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; ! ! AUTHENTICATE_PRINCIPAL/CHANGE_PASSWORD VALIDATE_MAPPING phase processing ! ! acme$co_validate_mapping kcb_vector, acme_context, wqe, wqe_context, ! item_list, acme_item_list ! ! kcb_vector = address of ACM Kernel Callback Vector ! acme_context = address of agent specific context ! wqe = address of ACM Work Queue Entry ! wqe_context = address of agent specific request context ! item_list = address of agent independent item list ! acme_item_list = address of agent specific item list ! KEYWORDMACRO $acme_co_validate_mapping (kcb_vector,acme_context ,wqe,wqe_context,item_list,acme_item_list) = BEGIN EXTERNAL ROUTINE acme$co_validate_mapping : BLISS ADDRESSING_MODE (GENERAL); acme$co_validate_mapping (SDL$$ACMEAGENT_CO_DEF_CONCAT( SDL$$ACMEAGENT_CO_DEF_REQ(kcb_vector, %QUOTE kcb_vector) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_context, %QUOTE acme_context) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CO_DEF_REQ(wqe_context, %QUOTE wqe_context) , SDL$$ACMEAGENT_CO_DEF_REQ(item_list, %QUOTE item_list) , SDL$$ACMEAGENT_CO_DEF_REQ(acme_item_list, %QUOTE acme_item_list) )) END %; !*** MODULE $ACMEAGENT_CB_DEF IDENT X-1 *** ! + ! ! ACM Kernel Callback Routines Protypes ! ! - ! ! Acquire ACME Resource ! ! acme$cb_acquire_resource wqe, resource_type, resource_value ! ! wqe = address of ACM Work Queue Entry ! resource_type = type of (ACME defined) resource to allocate ! resource_value = address of quadword to receive the value of resource allocated ! KEYWORDMACRO $acme_cb_acquire_resource (wqe,resource_type,resource_value) = BEGIN EXTERNAL ROUTINE acme$cb_acquire_resource : BLISS ADDRESSING_MODE (GENERAL); acme$cb_acquire_resource (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(resource_type, %QUOTE resource_type) , SDL$$ACMEAGENT_CB_DEF_REQ(resource_value, %QUOTE resource_value) )) END %; ! ! Acquire ACME AST Context ! ! acme$cb_acquire_acme_ast wqe, ast_handler, ast_context, ! ast_routine, ast_parameter ! ! wqe = address of ACM Work Queue Entry ! ast_handler = address of 64-bit pointer to receive AST handler ! (interceptor procedure) address ! ast_context = address of quadword to receive AST parameter value ! ast_routine = address of ACME's AST service routine to invoke upon ! AST delivery ! ast_parameter = address of quadword containing ACME specific value to ! pass to the ACME's AST service routine upon AST delivery ! KEYWORDMACRO $acme_cb_acquire_acme_ast (wqe,ast_handler,ast_context ,ast_routine,ast_parameter) = BEGIN EXTERNAL ROUTINE acme$cb_acquire_acme_ast : BLISS ADDRESSING_MODE (GENERAL); acme$cb_acquire_acme_ast (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_handler, %QUOTE ast_handler) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_context, %QUOTE ast_context) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_routine, %QUOTE ast_routine) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_parameter, %QUOTE ast_parameter) )) END %; ! ! Acquire ACME RMS AST Context ! ! acme$cb_acquire_acme_rmsast wqe, ast_handler, ast_context ! ast_routine, ast_parameter ! ! wqe = address of ACM Work Queue Entry ! ast_handler = address of 64-bit pointer to receive AST handler ! (interceptor procedure) address ! ast_context = address of quadword to receive AST parameter value ! ast_routine = address of ACME's AST service routine to invoke upon ! AST delivery ! ast_parameter = address of longword containing ACME specific value to ! pass to the ACME's AST service routine upon AST delivery ! KEYWORDMACRO $acme_cb_acquire_acme_rmsast (wqe,ast_handler,ast_context ,ast_routine,ast_parameter) = BEGIN EXTERNAL ROUTINE acme$cb_acquire_acme_rmsast : BLISS ADDRESSING_MODE (GENERAL); acme$cb_acquire_acme_rmsast (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_handler, %QUOTE ast_handler) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_context, %QUOTE ast_context) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_routine, %QUOTE ast_routine) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_parameter, %QUOTE ast_parameter) )) END %; ! ! Acquire WQE AST Context ! ! acme$cb_acquire_wqe_ast wqe, ast_handler, ast_context, ! ast_routine, ast_parameter ! ! wqe = address of ACM Work Queue Entry ! ast_handler = address of 64-bit pointer to receive AST handler ! (interceptor procedure) address ! ast_context = address of quadword to receive AST parameter value ! ast_routine = address of ACME's AST service routine to invoke upon ! AST delivery ! ast_parameter = address of quadword containing ACME specific value to ! pass to the ACME's AST service routine upon AST delivery ! KEYWORDMACRO $acme_cb_acquire_wqe_ast (wqe,ast_handler,ast_context ,ast_routine,ast_parameter) = BEGIN EXTERNAL ROUTINE acme$cb_acquire_wqe_ast : BLISS ADDRESSING_MODE (GENERAL); acme$cb_acquire_wqe_ast (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_handler, %QUOTE ast_handler) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_context, %QUOTE ast_context) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_routine, %QUOTE ast_routine) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_parameter, %QUOTE ast_parameter) )) END %; ! ! Acquire WQE RMS AST Context ! ! acme$cb_acquire_wqe_rmsast wqe, ast_handler, ast_context ! ast_routine, ast_parameter ! ! wqe = address of ACM Work Queue Entry ! ast_handler = address of 64-bit pointer to receive AST handler ! (interceptor procedure) address ! ast_context = address of quadword to receive AST parameter value ! ast_routine = address of ACME's AST service routine to invoke upon ! AST delivery ! ast_parameter = address of longword containing ACME specific value to ! pass to the ACME's AST service routine upon AST delivery ! KEYWORDMACRO $acme_cb_acquire_wqe_rmsast (wqe,ast_handler,ast_context ,ast_routine,ast_parameter) = BEGIN EXTERNAL ROUTINE acme$cb_acquire_wqe_rmsast : BLISS ADDRESSING_MODE (GENERAL); acme$cb_acquire_wqe_rmsast (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_handler, %QUOTE ast_handler) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_context, %QUOTE ast_context) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_routine, %QUOTE ast_routine) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_parameter, %QUOTE ast_parameter) )) END %; ! ! Allocate ACME VM ! ! acme$cb_allocate_acme_vm wqe, segment_size, segment_address ! ! wqe = address of ACM Work Queue Entry ! segment_size = number of bytes to allocated ! segment_address = address of first byte allocated ! KEYWORDMACRO $acme_cb_allocate_acme_vm (wqe,segment_size,segment_address) = BEGIN EXTERNAL ROUTINE acme$cb_allocate_acme_vm : BLISS ADDRESSING_MODE (GENERAL); acme$cb_allocate_acme_vm (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(segment_size, %QUOTE segment_size) , SDL$$ACMEAGENT_CB_DEF_REQ(segment_address, %QUOTE segment_address) )) END %; ! ! Allocate WQE VM ! ! acme$cb_allocate_wqe_vm wqe, segment_size, segment_address ! ! wqe = address of ACM Work Queue Entry ! segment_size = number of bytes to allocated ! segment_address = address of first byte allocated ! KEYWORDMACRO $acme_cb_allocate_wqe_vm (wqe,segment_size,segment_address) = BEGIN EXTERNAL ROUTINE acme$cb_allocate_wqe_vm : BLISS ADDRESSING_MODE (GENERAL); acme$cb_allocate_wqe_vm (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(segment_size, %QUOTE segment_size) , SDL$$ACMEAGENT_CB_DEF_REQ(segment_address, %QUOTE segment_address) )) END %; ! ! Cancel Dialogue ! ! acme$cb_cancel_dialogue wqe ! ! wqe = address of ACM Work Queue Entry ! KEYWORDMACRO $acme_cb_cancel_dialogue (wqe) = BEGIN EXTERNAL ROUTINE acme$cb_cancel_dialogue : BLISS ADDRESSING_MODE (GENERAL); acme$cb_cancel_dialogue (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) )) END %; ! ! Deallocate ACME VM ! ! acme$cb_deallocate_acme_vm wqe, segment_size, segment_address ! ! wqe = address of ACM Work Queue Entry ! segment_size = number of bytes to deallocate ! segment_address = address of first byte to deallocate ! KEYWORDMACRO $acme_cb_deallocate_acme_vm (wqe,segment_size,segment_address) = BEGIN EXTERNAL ROUTINE acme$cb_deallocate_acme_vm : BLISS ADDRESSING_MODE (GENERAL); acme$cb_deallocate_acme_vm (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(segment_size, %QUOTE segment_size) , SDL$$ACMEAGENT_CB_DEF_REQ(segment_address, %QUOTE segment_address) )) END %; ! ! Deallocate WQE VM ! ! acme$cb_deallocate_wqe_vm wqe, segment_size, segment_address ! ! wqe = address of ACM Work Queue Entry ! segment_size = number of bytes to deallocate ! segment_address = address of first byte to deallocate ! KEYWORDMACRO $acme_cb_deallocate_wqe_vm (wqe,segment_size,segment_address) = BEGIN EXTERNAL ROUTINE acme$cb_deallocate_wqe_vm : BLISS ADDRESSING_MODE (GENERAL); acme$cb_deallocate_wqe_vm (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(segment_size, %QUOTE segment_size) , SDL$$ACMEAGENT_CB_DEF_REQ(segment_address, %QUOTE segment_address) )) END %; ! ! Format Date and Time ! ! acme$cb_format_date_time wqe, dt_value, dt_string, dt_len, flags ! ! wqe = address of ACM Work Queue Entry ! dt_value = address of UTC date/time value ! dt_string = address of descriptor describing buffer to ! receive the formatted date/time string ! dt_len = address of word to receive the length (in bytes) ! of the formatted date/time string ! flags = formatting control flags ! KEYWORDMACRO $acme_cb_format_date_time (wqe,dt_value=0,dt_string ,dt_len=0,flags=0) = BEGIN EXTERNAL ROUTINE acme$cb_format_date_time : BLISS ADDRESSING_MODE (GENERAL); acme$cb_format_date_time (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , dt_value, SDL$$ACMEAGENT_CB_DEF_REQ(dt_string, %QUOTE dt_string) , dt_len, flags)) END %; ! ! Issue Credentials ! ! acme$cb_issue_credentials wqe, type, credentials ! ! wqe = address of ACM Work Queue Entry ! type = type of security credentials ! credentials = address of descriptor describing security credentials ! KEYWORDMACRO $acme_cb_issue_credentials (wqe,type,credentials) = BEGIN EXTERNAL ROUTINE acme$cb_issue_credentials : BLISS ADDRESSING_MODE (GENERAL); acme$cb_issue_credentials (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(type, %QUOTE type) , SDL$$ACMEAGENT_CB_DEF_REQ(credentials, %QUOTE credentials) )) END %; ! ! Convert a Latin1 string to a UCS string ! ! acme$cb_latin1_to_ucs wqe, latin1_string, ucs_string, ucs_bytes ! ! wqe = address of ACM Work Queue Entry ! latin1_string = address of descriptor for buffer ! holding the Latin-1 encoded string ! ucs_string = address of descriptor for buffer ! to receive the UCS encoded string ! ucs_bytes = length of ucs string (in bytes) ! KEYWORDMACRO $acme_cb_latin1_to_ucs (wqe,latin1_string,ucs_string ,ucs_bytes) = BEGIN EXTERNAL ROUTINE acme$cb_latin1_to_ucs : BLISS ADDRESSING_MODE (GENERAL); acme$cb_latin1_to_ucs (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(latin1_string, %QUOTE latin1_string) , SDL$$ACMEAGENT_CB_DEF_REQ(ucs_string, %QUOTE ucs_string) , SDL$$ACMEAGENT_CB_DEF_REQ(ucs_bytes, %QUOTE ucs_bytes) )) END %; ! ! Queue Dialogue ! ! acme$cb_queue_dialogue wqe, flags, item_code, max_length, ! data_1, data_2 ! ! wqe = address of ACM Work Queue Entry ! flags = dialogue control flags ! item_code = item code to use to tag response ! max_length = maximum length of response data ! data_1 = prompt/message text ! data_2 = prompt/response/message text ! KEYWORDMACRO $acme_cb_queue_dialogue (wqe,flags=0,item_code=0 ,max_length=0,data_1=0,data_2=0) = BEGIN EXTERNAL ROUTINE acme$cb_queue_dialogue : BLISS ADDRESSING_MODE (GENERAL); acme$cb_queue_dialogue (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , flags, item_code, max_length, data_1, data_2)) END %; ! ! Release ACME AST Context ! ! acme$cb_release_acme_ast wqe, ast_context ! ! wqe = address of ACM Work Queue Entry ! ast_context = AST parameter value ! KEYWORDMACRO $acme_cb_release_acme_ast (wqe,ast_context) = BEGIN EXTERNAL ROUTINE acme$cb_release_acme_ast : BLISS ADDRESSING_MODE (GENERAL); acme$cb_release_acme_ast (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_context, %QUOTE ast_context) )) END %; ! ! Release ACME RMS AST Context ! ! acme$cb_release_acme_rmsast wqe, ast_context ! ! wqe = address of ACM Work Queue Entry ! ast_context = AST parameter value ! KEYWORDMACRO $acme_cb_release_acme_rmsast (wqe,ast_context) = BEGIN EXTERNAL ROUTINE acme$cb_release_acme_rmsast : BLISS ADDRESSING_MODE (GENERAL); acme$cb_release_acme_rmsast (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_context, %QUOTE ast_context) )) END %; ! ! Release ACME Resource ! ! acme$cb_release_resource wqe, resource_type, resource_value ! ! wqe = address of ACM Work Queue Entry ! resource_type = type of (ACME defined) resource to allocate ! resource_value = address of quadword to receive the value of resource allocated ! KEYWORDMACRO $acme_cb_release_resource (wqe,resource_type,resource_value) = BEGIN EXTERNAL ROUTINE acme$cb_release_resource : BLISS ADDRESSING_MODE (GENERAL); acme$cb_release_resource (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(resource_type, %QUOTE resource_type) , SDL$$ACMEAGENT_CB_DEF_REQ(resource_value, %QUOTE resource_value) )) END %; ! ! Release WQE AST Context ! ! acme$cb_release_wqe_ast wqe, ast_context ! ! wqe = address of ACM Work Queue Entry ! ast_context = AST parameter value ! KEYWORDMACRO $acme_cb_release_wqe_ast (wqe,ast_context) = BEGIN EXTERNAL ROUTINE acme$cb_release_wqe_ast : BLISS ADDRESSING_MODE (GENERAL); acme$cb_release_wqe_ast (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_context, %QUOTE ast_context) )) END %; ! ! Release WQE RMS AST Context ! ! acme$cb_release_wqe_rmsast wqe, ast_context ! ! wqe = address of ACM Work Queue Entry ! ast_context = AST parameter value ! KEYWORDMACRO $acme_cb_release_wqe_rmsast (wqe,ast_context) = BEGIN EXTERNAL ROUTINE acme$cb_release_wqe_rmsast : BLISS ADDRESSING_MODE (GENERAL); acme$cb_release_wqe_rmsast (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(ast_context, %QUOTE ast_context) )) END %; ! ! Report ACME Activity ! ! acme$cb_report_activity wqe, activity ! ! wqe = address of ACM Work Queue Entry ! activity = address of ACME activity (status information) string ! KEYWORDMACRO $acme_cb_report_activity (wqe,activity) = BEGIN EXTERNAL ROUTINE acme$cb_report_activity : BLISS ADDRESSING_MODE (GENERAL); acme$cb_report_activity (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(activity, %QUOTE activity) )) END %; ! ! Report ACME Attributes ! ! acme$cb_report_attributes wqe, ident, resource_req ! ! wqe = address of ACM Work Queue Entry ! ident = address of descriptor describing ident string ! resource_req = address of ACME resource requirements structure ! KEYWORDMACRO $acme_cb_report_attributes (wqe,IDENT,resource_req) = BEGIN EXTERNAL ROUTINE acme$cb_report_attributes : BLISS ADDRESSING_MODE (GENERAL); acme$cb_report_attributes (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(IDENT, %QUOTE IDENT) , SDL$$ACMEAGENT_CB_DEF_REQ(resource_req, %QUOTE resource_req) )) END %; ! ! Send to Log File ! ! acme$cb_send_logfile wqe, msgvec ! ! wqe = address of ACM Work Queue Entry ! msgvec = address of $PUTMSG style message vector ! actrtn = address of action routine ! actprm = parameter to pass to action routine ! KEYWORDMACRO $acme_cb_send_logfile (wqe,msgvec,actrtn=0,actprm=0) = BEGIN EXTERNAL ROUTINE acme$cb_send_logfile : BLISS ADDRESSING_MODE (GENERAL); acme$cb_send_logfile (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(msgvec, %QUOTE msgvec) , actrtn, actprm)) END %; ! ! Send to Operator ! ! acme$cb_send_operator wqe, msgtxt ! ! wqe = address of ACM Work Queue Entry ! msgtxt = address of descriptor describing message text ! KEYWORDMACRO $acme_cb_send_operator (wqe,msgtxt) = BEGIN EXTERNAL ROUTINE acme$cb_send_operator : BLISS ADDRESSING_MODE (GENERAL); acme$cb_send_operator (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(msgtxt, %QUOTE msgtxt) )) END %; ! ! Set Secondary (Proctected) Status ! ! acme$cb_set_2nd_status wqe, status_value ! ! wqe = address of ACM Work Queue Entry ! status_value = specific status value/condition code ! KEYWORDMACRO $acme_cb_set_2nd_status (wqe,status_value) = BEGIN EXTERNAL ROUTINE acme$cb_set_2nd_status : BLISS ADDRESSING_MODE (GENERAL); acme$cb_set_2nd_status (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(status_value, %QUOTE status_value) )) END %; ! ! Set ACME Status ! ! acme$cb_set_acme_status wqe, status_value ! ! wqe = address of ACM Work Queue Entry ! status_value = ACME specific status value/condition code ! KEYWORDMACRO $acme_cb_set_acme_status (wqe,status_value) = BEGIN EXTERNAL ROUTINE acme$cb_set_acme_status : BLISS ADDRESSING_MODE (GENERAL); acme$cb_set_acme_status (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(status_value, %QUOTE status_value) )) END %; ! ! Set Designated DOI (Accept Request) ! ! acme$cb_set_designated_doi wqe ! ! wqe = address of ACM Work Queue Entry ! KEYWORDMACRO $acme_cb_set_designated_doi (wqe) = BEGIN EXTERNAL ROUTINE acme$cb_set_designated_doi : BLISS ADDRESSING_MODE (GENERAL); acme$cb_set_designated_doi (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) )) END %; ! ! Set Logon Flag ! ! acme$cb_set_logon_flag wqe, flag ! ! wqe = address of ACM Work Queue Entry ! flag = flag number to set ! KEYWORDMACRO $acme_cb_set_logon_flag (wqe,flag) = BEGIN EXTERNAL ROUTINE acme$cb_set_logon_flag : BLISS ADDRESSING_MODE (GENERAL); acme$cb_set_logon_flag (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(flag, %QUOTE flag) )) END %; ! ! Set Non-Native (non-OpenVMS) Logon Statistics ! ! acme$cb_set_logon_stats_doi wqe, logon_data ! ! wqe = address of ACM Work Queue Entry ! logon_data = address of OpenVMS logon statistics buffer ! KEYWORDMACRO $acme_cb_set_logon_stats_doi (wqe,logon_data) = BEGIN EXTERNAL ROUTINE acme$cb_set_logon_stats_doi : BLISS ADDRESSING_MODE (GENERAL); acme$cb_set_logon_stats_doi (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(logon_data, %QUOTE logon_data) )) END %; ! ! Set Native (OpenVMS) Logon Statistics ! ! acme$cb_set_logon_stats_vms wqe, logon_data ! ! wqe = address of ACM Work Queue Entry ! logon_data = address of OpenVMS logon statistics buffer ! KEYWORDMACRO $acme_cb_set_logon_stats_vms (wqe,logon_data) = BEGIN EXTERNAL ROUTINE acme$cb_set_logon_stats_vms : BLISS ADDRESSING_MODE (GENERAL); acme$cb_set_logon_stats_vms (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(logon_data, %QUOTE logon_data) )) END %; ! ! Set Output Item ! ! acme$cb_set_output_item wqe, entry, data ! ! wqe = address of ACM Work Queue Entry ! entry = address of the item list entry to set ! data = address of descriptor describing data for field ! KEYWORDMACRO $acme_cb_set_output_item (wqe,ENTRY,data) = BEGIN EXTERNAL ROUTINE acme$cb_set_output_item : BLISS ADDRESSING_MODE (GENERAL); acme$cb_set_output_item (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(ENTRY, %QUOTE ENTRY) , SDL$$ACMEAGENT_CB_DEF_REQ(data, %QUOTE data) )) END %; ! ! Set Phase Notification Event ! ! acme$cb_set_phase_event wqe, event_data ! ! wqe = address of ACM Work Queue Entry ! event_data = prompt/message text ! KEYWORDMACRO $acme_cb_set_phase_event (wqe,event_data=0) = BEGIN EXTERNAL ROUTINE acme$cb_set_phase_event : BLISS ADDRESSING_MODE (GENERAL); acme$cb_set_phase_event (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , event_data)) END %; ! ! Set WQE Flag ! ! acme$cb_set_wqe_flag wqe, flag ! ! wqe = address of ACM Work Queue Entry ! flag = flag number to set ! KEYWORDMACRO $acme_cb_set_wqe_flag (wqe,flag) = BEGIN EXTERNAL ROUTINE acme$cb_set_wqe_flag : BLISS ADDRESSING_MODE (GENERAL); acme$cb_set_wqe_flag (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(flag, %QUOTE flag) )) END %; ! ! Set WQE Parameter (Item) ! ! acme$cb_set_wqe_parameter wqe, id, data ! ! wqe = address of ACM Work Queue Entry ! id = id number of parameter (item) field to set ! data = address of descriptor describing data for field ! KEYWORDMACRO $acme_cb_set_wqe_parameter (wqe,id,data) = BEGIN EXTERNAL ROUTINE acme$cb_set_wqe_parameter : BLISS ADDRESSING_MODE (GENERAL); acme$cb_set_wqe_parameter (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(id, %QUOTE id) , SDL$$ACMEAGENT_CB_DEF_REQ(data, %QUOTE data) )) END %; ! ! Convert a UCS string to a Latin1 string ! ! acme$cb_ucs_to_latin1 wqe, ucs_string, latin1_string, latin1_bytes ! ! wqe = address of ACM Work Queue Entry ! ucs_string = address of descriptor for buffer ! holding the UCS encoded string ! latin1_string = address of descriptor for buffer ! to receive the Latin-1 encoded string ! latin1_bytes = length of latin1 string (in bytes) ! KEYWORDMACRO $acme_cb_ucs_to_latin1 (wqe,ucs_string,latin1_string ,latin1_bytes) = BEGIN EXTERNAL ROUTINE acme$cb_ucs_to_latin1 : BLISS ADDRESSING_MODE (GENERAL); acme$cb_ucs_to_latin1 (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(ucs_string, %QUOTE ucs_string) , SDL$$ACMEAGENT_CB_DEF_REQ(latin1_string, %QUOTE latin1_string) , SDL$$ACMEAGENT_CB_DEF_REQ(latin1_bytes, %QUOTE latin1_bytes) )) END %; ! ! Set New Password Flags ! ! acme$cb_set_new_pwd_flags wqe, flag ! ! wqe = address of ACM Work Queue Entry ! flag = flag number to set ! KEYWORDMACRO $acme_cb_set_new_pwd_flags (wqe,flag) = BEGIN EXTERNAL ROUTINE acme$cb_set_new_pwd_flags : BLISS ADDRESSING_MODE (GENERAL); acme$cb_set_new_pwd_flags (SDL$$ACMEAGENT_CB_DEF_CONCAT( SDL$$ACMEAGENT_CB_DEF_REQ(wqe, %QUOTE wqe) , SDL$$ACMEAGENT_CB_DEF_REQ(flag, %QUOTE flag) )) END %; ! ! ---- < End of module SYSDEF.R32 - 30-MAR-2010 16:38:40.50 > - ! ! ! ************************************************************************* ! * * ! * © Copyright 2010, Hewlett-Packard Development Company, L.P. * ! * * ! * Confidential computer software. Valid license from HP and/or * ! * its subsidiaries required for possession, use, or copying. * ! * * ! * Consistent with FAR 12.211 and 12.212, Commercial Computer Software, * ! * Computer Software Documentation, and Technical Data for Commercial * ! * Items are licensed to the U.S. Government under vendor's standard * ! * commercial license. * ! * * ! * Neither HP nor any of its subsidiaries shall be liable for technical * ! * or editorial errors or omissions contained herein. The information * ! * in this document is provided "as is" without warranty of any kind and * ! * is subject to change without notice. The warranties for HP products * ! * are set forth in the express limited warranty statements accompanying * ! * such products. Nothing herein should be construed as constituting an * ! * additional warranty. * ! * * ! ************************************************************************* ! ******************************************************************************************************************************** ! Created: 30-Mar-2010 16:11:12 by OpenVMS SDL EV3-3 ! Source: 13-MAY-1993 14:02:07 $1$DGA7374:[LIB.SRC]F11CDEF.SDL;1 ! ******************************************************************************************************************************** !*** MODULE $F11CDEF IDENT X-3 *** ! ! File sections shall be recorded in the Data Area. The following types of ! descriptors shall be record in the data area of a volume. ! ! o Volume Descriptors ! o Boot Record (BOOT) ! o Volume Descriptor Set Terminator (VDST) ! o Primary Volume Descriptor (PVD) ! o Supplementary Volume Descriptor (SVD) ! o Volume Partition Descriptor (VPD) ! o File Descriptors ! o Directory Descriptors ! o Path Tables ! ! ! ISO 9660 standard constants ! literal ISO$K_LOGICAL_BLOCK_SIZE = 2048; ! Current Volume Descriptor Block Size literal ISO$K_SYSTEM_AREA = 0; ! Logical Block number of System Area literal ISO$K_DATA_AREA = 16; ! Logical Block number of Data Area literal ISO$K_ISO_9660_VERSION_1988 = 1; ! Volume Descriptor Version # for ISO 9660 (1988) ! ! Character set coding ! literal ISO$K_SPACE = 32; ! ' ' fill character literal ISO$K_SEPARATOR_1 = 46; ! '.'-filename.extension break literal ISO$K_SEPARATOR_2 = 59; ! ';'-extension;version break literal ISO$K_FILE_ID = 95; ! '_' file identifier character literal ISO$K_ROOT_DIRECTORY_ID = 0; ! Root Directory Identifier literal ISO$K_PARENT_DIRECTORY_ID = 1; ! Parent Directory Identifier ! + ! FILE_ID ! ! A File Identifier consist of the following sequence: ! - File name : A sequence of 0 -> 30 'D' or 'D1' characters ! - SEPARATOR_1 ! - Extension : A sequence of 0 -> 30 'D' or 'D1' characters ! - SEPARATOR_2 ! - Version # : A sequence of 1 to 5 digits; up to "32767" ! If 'File Name' length equals 0, then Extension must be 1 or greater ! If 'Extension' length equals 0, then File Name must be 1 or greater ! The length of 'File Name' + 'Extension' must not exceed 30. ! - literal ISO$FNAME$S_FILE_ID = 37; ! Old size name- synonym literal ISO$FNAME$S_F11C_FILE_ID = 37; macro ISO$FNAME$T_FILE_NAME_EXT = 0,0,0,0 %; literal ISO$FNAME$S_FILE_NAME_EXT = 37; ! filename.ext;version ! + ! Identifier ! ! This descriptor shall specify an identifier. If the first byte is equal ! to a %X05F, the remaining bytes of this field shall specific an ! identifier for a file containing the identification text. This file ! shall be described in the Root Directory. The File Name shall not ! contain more than 8 D_CHARACTERS and the File Extension shall not ! contain more than 3 D_CHARACTERS. If all bytes in this field are set to ! %X20, it shall mean that no such identifier is defined. ! - literal ISO$ID$S_IDENTIFIER = 128; ! Old size name - synonym literal ISO$ID$S_F11C_IDENTIFIER = 128; macro ISO$ID$R_ENCODED_ID = 0,0,0,0 %; literal ISO$ID$S_ENCODED_ID = 38; macro ISO$ID$B_FLAG = 0,0,8,0 %; ! File specific flag macro ISO$ID$T_FILE_NAME_EXT = 1,0,0,0 %; literal ISO$ID$S_FILE_NAME_EXT = 37; ! File Identifier (filename.ext;version) macro ISO$ID$B_DATA = 0,0,0,1 %; literal ISO$ID$S_DATA = 128; ! Text Identifier ! + ! ASCII_DATE_TIME ! ! The date and time shall be represented by a 17-byte field. ! If Byte positions 1-16 are the digit '0', and BP 17 equals 0, then ! it shall mean that date and time are not specified. ! - literal ISO$AUTC$S_ASCII_DATE_TIME = 17; ! Old size name - synonym literal ISO$AUTC$S_F11C_ASCII_DATE = 17; macro ISO$AUTC$T_YEAR = 0,0,32,0 %; literal ISO$AUTC$S_YEAR = 4; ! year (1-9999) macro ISO$AUTC$T_MONTH = 4,0,16,0 %; literal ISO$AUTC$S_MONTH = 2; ! month (1-12) macro ISO$AUTC$T_DAY = 6,0,16,0 %; literal ISO$AUTC$S_DAY = 2; ! day (1-31) macro ISO$AUTC$T_HOUR = 8,0,16,0 %; literal ISO$AUTC$S_HOUR = 2; ! hour (0-23) macro ISO$AUTC$T_MINUTE = 10,0,16,0 %; literal ISO$AUTC$S_MINUTE = 2; ! minute (0-59) macro ISO$AUTC$T_SECOND = 12,0,16,0 %; literal ISO$AUTC$S_SECOND = 2; ! second (0-59) macro ISO$AUTC$T_HUNDREDTH = 14,0,16,0 %; literal ISO$AUTC$S_HUNDREDTH = 2; ! hundredth (0-99) macro ISO$AUTC$B_OFFSET_GMT = 16,0,8,1 %; ! ¼ hr. intervals (-48:+52)) ! + ! BINARY_DATE_TIME ! ! The data and time shall be represented by seven 8-bit numbers ! - literal ISO$BUTC$S_BINARY_DATE_TIME = 7; ! Old size name - synonym literal ISO$BUTC$S_F11C_BINARY_DATE = 7; macro ISO$BUTC$B_YEAR = 0,0,8,0 %; ! year since 1900 (1-99) macro ISO$BUTC$B_MONTH = 1,0,8,0 %; ! month (1-12) macro ISO$BUTC$B_DAY = 2,0,8,0 %; ! day (1-31) macro ISO$BUTC$B_HOUR = 3,0,8,0 %; ! hour (0-23) macro ISO$BUTC$B_MINUTE = 4,0,8,0 %; ! minute (0-59) macro ISO$BUTC$B_SECOND = 5,0,8,0 %; ! second (0-59) macro ISO$BUTC$B_OFFSET_GMT = 6,0,8,1 %; ! ¼ hr. intervals from -48(west) to +52(east) ! + ! PATH_TABLE_RECORD ! ! A Path Table contain a set of records describing a directory hierarchy ! for those volume of a Volume Set the sequence numbers of which are less ! than, or equal to, the assigned Volume Set size of the volume. ! ! For each directory in the directory hierarchy other then the Root ! Directory, the Path Table shall contain a record which identifies ! the directory, its Parent Directory and its location. The records ! in a Path Table shall be number starting at 1. The first record in ! the Path Table shall identify the Root Directory and it location. ! ! - literal ISO$PTBL$S_PATH_TABLE_RECORD = 45; ! Old size name - synonym literal ISO$PTBL$S_F11C_PATH_TABLE_REC = 45; macro ISO$PTBL$B_DIRECTORY_ID_LENGTH = 0,0,8,0 %; ! Length of directory Identifier macro ISO$PTBL$B_XAR_LENGTH = 1,0,8,0 %; ! Extended Attribute Record length macro ISO$PTBL$L_EXTENT_LOCATION = 2,0,32,0 %; ! Location of Extent macro ISO$PTBL$W_PARENT_DIRECTORY = 6,0,16,0 %; ! Parent Directory Number macro ISO$PTBL$T_DIRECTORY_ID = 8,0,0,0 %; literal ISO$PTBL$S_DIRECTORY_ID = 37; ! Directory Identifier (dirname) ! + ! DIRECTORY ! This descriptor shall define a directory record. A directory record ! contains information to locate a File Section; an Extended Attribute ! Record associated with a File Section; the identification of a file; ! attributes of a file and file section. ! - literal ISO$DREC$M_EXISTENCE = %X'1'; literal ISO$DREC$M_DIRECTORY = %X'2'; literal ISO$DREC$M_ASSOCIATED = %X'4'; literal ISO$DREC$M_RECORD = %X'8'; literal ISO$DREC$M_PROTECTION = %X'10'; literal ISO$DREC$M_RESERVED = %X'60'; literal ISO$DREC$M_MULTI_EXTENT = %X'80'; literal ISO$DREC$A_PADDING = 34; ! Pad byte literal ISO$DREC$A_SYSTEM_USE = 34; ! System use literal ISO$DREC$S_DIRECTORY = 512; ! Old size name - synonym literal ISO$DREC$S_F11C_DIRECTORY = 512; macro ISO$DREC$B_DIRECTORY_LENGTH = 0,0,8,0 %; ! Length of directory record macro ISO$DREC$B_XAR_LENGTH = 1,0,8,0 %; ! Extended Attribute Length macro ISO$DREC$L_EXTENT_LOCATION = 2,0,32,0 %; ! Location of Extent (LBN) macro ISO$DREC$L_EXTENT_LOCATION_M = 6,0,32,0 %; ! Location of Extent (LBN) macro ISO$DREC$L_DATA_LENGTH = 10,0,32,0 %; ! Data Length of File Section macro ISO$DREC$L_DATA_LENGTH_M = 14,0,32,0 %; ! Data Length of File Section macro ISO$DREC$B_FILE_RECORDING = 18,0,0,1 %; literal ISO$DREC$S_FILE_RECORDING = 7; ! Recording Date/Time of extent macro ISO$DREC$B_FILE_FLAGS = 25,0,8,0 %; ! File characteristics macro ISO$DREC$V_EXISTENCE = 25,0,1,0 %; ! If set; nonexistent macro ISO$DREC$V_DIRECTORY = 25,1,1,0 %; ! If set; directory record macro ISO$DREC$V_ASSOCIATED = 25,2,1,0 %; ! If set; associated file macro ISO$DREC$V_RECORD = 25,3,1,0 %; ! If set; record format via XAR.RFM macro ISO$DREC$V_PROTECTION = 25,4,1,0 %; ! If set; enforce protection macro ISO$DREC$V_MULTI_EXTENT = 25,7,1,0 %; ! If set; extend record macro ISO$DREC$B_FILE_UNIT_SIZE = 26,0,8,0 %; ! Interleave File Unit size macro ISO$DREC$B_INTERLEAVE_GAP = 27,0,8,0 %; ! Interleave Gap size macro ISO$DREC$W_VOLUME_NUMBER = 28,0,16,0 %; ! Volume Sequence # of extent macro ISO$DREC$W_VOLUME_NUMBER_M = 30,0,16,0 %; ! Volume Sequence # of extent macro ISO$DREC$B_FILE_ID_LENGTH = 32,0,8,0 %; ! File Identifier Field Length macro ISO$DREC$B_FILE_ID = 33,0,8,1 %; ! File Identifier ! + ! XAR_RECORD ! This descriptor shall define an Extended Attribute Record. An ! extended attribute record contains addition information which ! is associated to a File Section. ! ! - literal ISO$XAR$M_SYS_NO_READ = %X'1'; literal ISO$XAR$M_FILL_1 = %X'2'; literal ISO$XAR$M_SYS_NO_EXECUTE = %X'4'; literal ISO$XAR$M_FILL_2 = %X'8'; literal ISO$XAR$M_OWN_NO_READ = %X'10'; literal ISO$XAR$M_FILL_3 = %X'20'; literal ISO$XAR$M_OWN_NO_EXECUTE = %X'40'; literal ISO$XAR$M_FILL_4 = %X'80'; literal ISO$XAR$M_GRP_NO_READ = %X'100'; literal ISO$XAR$M_FILL_5 = %X'200'; literal ISO$XAR$M_GRP_NO_EXECUTE = %X'400'; literal ISO$XAR$M_FILL_6 = %X'800'; literal ISO$XAR$M_WLD_NO_READ = %X'1000'; literal ISO$XAR$M_FILL_7 = %X'2000'; literal ISO$XAR$M_WLD_NO_EXECUTE = %X'4000'; literal ISO$XAR$M_FILL_8 = %X'8000'; literal ISO$XAR$RFM$K_UNDEFINED = 0; literal ISO$XAR$RFM$K_FIXED = 1; literal ISO$XAR$RFM$K_LSB_VARIABLE = 2; literal ISO$XAR$RFM$K_MSB_VARIABLE = 3; literal ISO$XAR$RFM$SYS$K_UNDEFINED = 128; literal ISO$XAR$RFM$SYS$K_FIXED = 129; literal ISO$XAR$RFM$SYS$K_VARIABLE = 130; literal ISO$XAR$RFM$SYS$K_VFC = 131; literal ISO$XAR$RFM$SYS$K_STREAM = 132; literal ISO$XAR$RFM$SYS$K_STREAMLF = 133; literal ISO$XAR$RFM$SYS$K_STREAMCR = 134; literal ISO$XAR$ATR$K_CRLF = 0; literal ISO$XAR$ATR$K_FTN = 1; literal ISO$XAR$ATR$K_STM = 2; literal ISO$XAR$A_ESCAPE_SEQUENCE = 250; ! Escape Sequences literal ISO$XAR$S_XAR_RECORD = 512; ! Old size name - synonym literal ISO$XAR$S_F11C_XAR_RECORD = 512; macro ISO$XAR$W_OWNER_ID = 0,0,16,0 %; ! Owner Identification macro ISO$XAR$W_OWNER_ID_M = 2,0,16,0 %; ! Owner Identification macro ISO$XAR$W_GROUP_ID = 4,0,16,0 %; ! Group Identification macro ISO$XAR$W_GROUP_ID_M = 6,0,16,0 %; ! Group Identification macro ISO$XAR$W_PERMISSIONS = 8,0,16,0 %; ! Access permission for classes of users macro ISO$XAR$V_SYS_NO_READ = 8,0,1,0 %; ! If set; ~(S:R) macro ISO$XAR$V_SYS_NO_EXECUTE = 8,2,1,0 %; ! If set; ~(S:E) macro ISO$XAR$V_OWN_NO_READ = 8,4,1,0 %; ! If set; ~(O:R) macro ISO$XAR$V_OWN_NO_EXECUTE = 8,6,1,0 %; ! If set; ~(O:E) macro ISO$XAR$V_GRP_NO_READ = 8,8,1,0 %; ! If set; ~(G:R) macro ISO$XAR$V_GRP_NO_EXECUTE = 8,10,1,0 %; ! If set; ~(G:E) macro ISO$XAR$V_WLD_NO_READ = 8,12,1,0 %; ! If set; ~(W:R) macro ISO$XAR$V_WLD_NO_EXECUTE = 8,14,1,0 %; ! If set; ~(W:E) macro ISO$XAR$B_FILE_CREATION = 10,0,0,1 %; literal ISO$XAR$S_FILE_CREATION = 17; ! File Creation Date/Time macro ISO$XAR$B_FILE_MODIFICATION = 27,0,0,1 %; literal ISO$XAR$S_FILE_MODIFICATION = 17; ! File Modification Date/Time macro ISO$XAR$B_FILE_EXPIRATION = 44,0,0,1 %; literal ISO$XAR$S_FILE_EXPIRATION = 17; ! File Expiration Date/Time macro ISO$XAR$B_FILE_EFFECTIVE = 61,0,0,1 %; literal ISO$XAR$S_FILE_EFFECTIVE = 17; ! File Effective Date/Time macro ISO$XAR$B_RECORD_FORMAT = 78,0,8,0 %; ! Record Format macro ISO$XAR$B_RECORD_ATTRIBUTES = 79,0,8,0 %; ! Record Attributes macro ISO$XAR$W_RECORD_LENGTH = 80,0,16,0 %; ! Record Length macro ISO$XAR$W_RECORD_LENGTH_M = 82,0,16,0 %; ! Record Length macro ISO$XAR$T_SYSTEM_ID = 84,0,0,0 %; literal ISO$XAR$S_SYSTEM_ID = 32; ! System Identifier macro ISO$XAR$B_SYSTEM_USE = 116,0,0,1 %; literal ISO$XAR$S_SYSTEM_USE = 64; ! System Used macro ISO$XAR$B_XAR_VERSION = 180,0,8,0 %; ! Extended Attribute Version macro ISO$XAR$B_ESCAPE_SEQ_LENGTH = 181,0,8,0 %; ! Escape Sequence record length macro ISO$XAR$W_APPLICATION_USE = 246,0,16,0 %; ! Application Use Length macro ISO$XAR$W_APPLICATION_USE_M = 248,0,16,0 %; ! Application Use Length macro ISO$XAR$B_APPLICATION_USE = 250,0,0,1 %; literal ISO$XAR$S_APPLICATION_USE = 262; ! Application Use ! + ! Volume Descriptor ! ! The Volume Descriptor shall Identify the volume, the partitions recorded ! on the volume, the volume creator(s), certain attributes of the volume, ! the location of other recorded descriptors and the version of the ! standard which applies to the volume descriptor. ! ! - literal ISO$VD$K_BOOT = 0; ! Boot Record Descriptor literal ISO$VD$K_PVD = 1; ! Primary Volume Descriptor literal ISO$VD$K_SVD = 2; ! Supplementary Volume Descriptor literal ISO$VD$K_VPD = 3; ! Volume Partition Descriptor ! (Values 4 to 254 are reserved) literal ISO$VD$K_VDST = 255; ! Volume Descriptor Set Terminator literal ISO$VD$S_VD = 2048; ! Old size name - synonym literal ISO$VD$S_F11C_VD = 2048; macro ISO$VD$B_VOLUME_DESCRIPTOR_TYPE = 0,0,8,0 %; ! Volume Descriptor Type macro ISO$VD$T_STANDARD_IDENTIFIER = 1,0,0,0 %; literal ISO$VD$S_STANDARD_IDENTIFIER = 5; ! International Standard Id. (CD001) macro ISO$VD$B_VOLUME_DESCRIPTOR_VERS = 6,0,8,0 %; ! Volume Descriptor Version macro ISO$VD$B_VOLUME_DATA = 7,0,0,1 %; literal ISO$VD$S_VOLUME_DATA = 2041; ! Volume Descriptor Data ! + ! Boot Record (BOOT) ! ! The Boot Record shall Identify a system which can recognize and act upon ! the content of the field reserved for boot system use in the Boot ! Record, and shall contain information which is used to achieve a ! specific state for a system or for an application. ! ! - literal ISO$BOOT$S_BOOT = 2048; ! Old size name - synonym literal ISO$BOOT$S_F11C_BOOT = 2048; macro ISO$BOOT$B_BOOT_VOLUME = 0,0,0,1 %; literal ISO$BOOT$S_BOOT_VOLUME = 7; ! Boot Volume Descriptor macro ISO$BOOT$T_SYSTEM_IDENTIFIER = 7,0,0,0 %; literal ISO$BOOT$S_SYSTEM_IDENTIFIER = 32; ! Boot System Identifier macro ISO$BOOT$T_IDENTIFIER = 39,0,0,0 %; literal ISO$BOOT$S_IDENTIFIER = 32; ! Boot Identifier macro ISO$BOOT$B_SYSTEM_USE = 71,0,0,1 %; literal ISO$BOOT$S_SYSTEM_USE = 1977; ! Boot System Use ! + ! Volume Descriptor Set Terminator ! ! The recorded set of Volume Descriptors shall be terminated by a sequence ! of one or more Volume Descriptor Set Terminators ! ! - literal ISO$VDST$S_VDST = 2048; ! Old size name - synonym literal ISO$VDST$S_F11C_VDST = 2048; macro ISO$VDST$B_TERMINATOR_VOLUME = 0,0,0,1 %; literal ISO$VDST$S_TERMINATOR_VOLUME = 7; ! Volume Descriptor Set ! + ! Primary Volume Descriptor ! ! The Primary Volume Descriptor shall Identify the volume, a system which ! can recognize and act upon the content of the Logical Sectors with ! Logical Sector Number 0 to 15, the size of the Volume Space, the version ! of the standard which applies to the Volume Descriptor, the version of ! the specification which applies to the Directory Records and the Path ! Table Records and certain attributes of the volume. ! ! - literal ISO$PVD$S_PVD = 2048; ! Old size name - synonym literal ISO$PVD$S_F11C_PVD = 2048; macro ISO$PVD$B_PRIMARY_VOLUME = 0,0,0,1 %; literal ISO$PVD$S_PRIMARY_VOLUME = 7; ! Primary Volume Descriptor macro ISO$PVD$T_SYSTEM_IDENTIFIER = 8,0,0,0 %; literal ISO$PVD$S_SYSTEM_IDENTIFIER = 32; ! System Identifier macro ISO$PVD$T_VOLUME_IDENTIFIER = 40,0,0,0 %; literal ISO$PVD$S_VOLUME_IDENTIFIER = 32; ! Volume Identifier macro ISO$PVD$L_VOLUME_SPACE_SIZE = 80,0,32,0 %; ! Volume Space Size macro ISO$PVD$L_VOLUME_SPACE_SIZE_M = 84,0,32,0 %; ! Volume Space Size macro ISO$PVD$W_VOLUME_SET_SIZE = 120,0,16,0 %; ! Volume Set Size macro ISO$PVD$W_VOLUME_SET_SIZE_M = 122,0,16,0 %; ! Volume Set Size macro ISO$PVD$W_VOLUME_NUMBER = 124,0,16,0 %; ! Volume Sequence Number macro ISO$PVD$W_VOLUME_NUMBER_M = 126,0,16,0 %; ! Volume Sequence Number macro ISO$PVD$W_LOGICAL_BLOCK_SIZE = 128,0,16,0 %; ! Logical Block Size macro ISO$PVD$W_LOGICAL_BLOCK_SIZE_M = 130,0,16,0 %; ! Logical Block Size macro ISO$PVD$L_PATH_TABLE_SIZE = 132,0,32,0 %; ! Path Table Size macro ISO$PVD$L_PATH_TABLE_SIZE_M = 136,0,32,0 %; ! Path Table Size macro ISO$PVD$L_PATH_TABLE = 140,0,32,0 %; ! Path Table Logical Block # macro ISO$PVD$L_OPT_PATH_TABLE = 144,0,32,0 %; ! Optional Path Table Logical Block # macro ISO$PVD$L_PATH_TABLE_M = 148,0,32,0 %; ! Path Table Logical Block # macro ISO$PVD$L_OPT_PATH_TABLE_M = 152,0,32,0 %; ! Optional Path Table Logical Block # macro ISO$PVD$B_ROOT_DIRECTORY = 156,0,0,1 %; literal ISO$PVD$S_ROOT_DIRECTORY = 34; ! Root Directory Record macro ISO$PVD$T_VOLUME_SET_IDENTIFIER = 190,0,0,0 %; literal ISO$PVD$S_VOLUME_SET_IDENTIFIER = 128; ! Volume Set Identifier macro ISO$PVD$B_PUBLISHER_ID = 318,0,0,1 %; literal ISO$PVD$S_PUBLISHER_ID = 128; ! Publisher Identifier macro ISO$PVD$B_DATA_PREPARER_ID = 446,0,0,1 %; literal ISO$PVD$S_DATA_PREPARER_ID = 128; ! Data Preparer Identifier macro ISO$PVD$B_APPLICATION_ID = 574,0,0,1 %; literal ISO$PVD$S_APPLICATION_ID = 128; ! Application Identifier macro ISO$PVD$B_COPYRIGHT_FILE_ID = 702,0,0,1 %; literal ISO$PVD$S_COPYRIGHT_FILE_ID = 37; ! Copyright File Identifier macro ISO$PVD$B_ABSTRACT_FILE_ID = 739,0,0,1 %; literal ISO$PVD$S_ABSTRACT_FILE_ID = 37; ! Abstract File Identifier macro ISO$PVD$B_BIBLIOGRAPHIC_ID = 776,0,0,1 %; literal ISO$PVD$S_BIBLIOGRAPHIC_ID = 37; ! Bibliographic File Identifier macro ISO$PVD$B_VOLUME_CREATION = 813,0,0,1 %; literal ISO$PVD$S_VOLUME_CREATION = 17; ! Volume Creation Date/Time macro ISO$PVD$B_VOLUME_MODIFIY = 830,0,0,1 %; literal ISO$PVD$S_VOLUME_MODIFIY = 17; ! Volume Modification Date/Time macro ISO$PVD$B_VOLUME_EXPIRATION = 847,0,0,1 %; literal ISO$PVD$S_VOLUME_EXPIRATION = 17; ! Volume Expiration Date/Time macro ISO$PVD$B_VOLUME_EFFECTIVE = 864,0,0,1 %; literal ISO$PVD$S_VOLUME_EFFECTIVE = 17; ! Volume Effective Date/Time macro ISO$PVD$B_FILE_STRUCTURE_VERS = 881,0,8,0 %; ! File Structure Version macro ISO$PVD$B_APPLICATION_USE = 883,0,0,1 %; literal ISO$PVD$S_APPLICATION_USE = 512; ! Application Use field ! + ! Supplementary Volume Descriptor ! ! The Supplementary Volume Descriptor shall Identify the volume, a system ! which can recognize and act upon the content of the Logical Sectors with ! Logical Sector Number 0 to 15, the size of the Volume Space, the version ! of the standard which applies to the Volume Descriptor, the version of ! the specification which applies to the Directory Records and the Path ! Table Records, certain attributes of the volume and the coded graphic ! character sets used to interpret descriptor fields that contain ! characters. ! ! - literal ISO$SVD$M_NON_ISO_2375 = %X'1'; literal ISO$SVD$S_SVD = 2048; ! Old size name - synonym literal ISO$SVD$S_F11C_SVD = 2048; macro ISO$SVD$B_SUPPLEMENTARY_VOLUME = 0,0,0,1 %; literal ISO$SVD$S_SUPPLEMENTARY_VOLUME = 7; ! Supplementary Volume Descriptor macro ISO$SVD$B_VOLUME_FLAGS = 7,0,8,0 %; ! Volume characteristics macro ISO$SVD$V_NON_ISO_2375 = 7,0,1,0 %; ! If set; Escape Sequence is non ISO-2375 compliant macro ISO$SVD$T_SYSTEM_IDENTIFIER = 8,0,0,0 %; literal ISO$SVD$S_SYSTEM_IDENTIFIER = 32; ! System Identifier macro ISO$SVD$T_VOLUME_IDENTIFIER = 40,0,0,0 %; literal ISO$SVD$S_VOLUME_IDENTIFIER = 32; ! Volume Identifier macro ISO$SVD$L_VOLUME_SPACE_SIZE = 80,0,32,0 %; ! Volume Space Size macro ISO$SVD$L_VOLUME_SPACE_SIZE_M = 84,0,32,0 %; ! Volume Space Size macro ISO$SVD$B_ESCAPE_SEQUENCES = 88,0,0,1 %; literal ISO$SVD$S_ESCAPE_SEQUENCES = 32; ! Escape Sequences ISO 2022 for G0, G1 macro ISO$SVD$W_VOLUME_SET_SIZE = 120,0,16,0 %; ! Volume Set Size macro ISO$SVD$W_VOLUME_SET_SIZE_M = 122,0,16,0 %; ! Volume Set Size macro ISO$SVD$W_VOLUME_NUMBER = 124,0,16,0 %; ! Volume Sequence Number macro ISO$SVD$W_VOLUME_NUMBER_M = 126,0,16,0 %; ! Volume Sequence Number macro ISO$SVD$W_LOGICAL_BLOCK_SIZE = 128,0,16,0 %; ! Logical Block Size macro ISO$SVD$W_LOGICAL_BLOCK_SIZE_M = 130,0,16,0 %; ! Logical Block Size macro ISO$SVD$L_PATH_TABLE_SIZE = 132,0,32,0 %; ! Path Table Size macro ISO$SVD$L_PATH_TABLE_SIZE_M = 136,0,32,0 %; ! Path Table Size macro ISO$SVD$L_PATH_TABLE = 140,0,32,0 %; ! Path Table Logical Block # macro ISO$SVD$L_OPT_PATH_TABLE = 144,0,32,0 %; ! Optional Path Table Logical Block # macro ISO$SVD$L_PATH_TABLE_M = 148,0,32,0 %; ! Path Table Logical Block # macro ISO$SVD$L_OPT_PATH_TABLE_M = 152,0,32,0 %; ! Optional Path Table Logical Block # macro ISO$SVD$B_ROOT_DIRECTORY = 156,0,0,1 %; literal ISO$SVD$S_ROOT_DIRECTORY = 34; ! Root Directory Record macro ISO$SVD$T_VOLUME_SET_IDENTIFIER = 190,0,0,0 %; literal ISO$SVD$S_VOLUME_SET_IDENTIFIER = 128; ! Volume Set Identifier macro ISO$SVD$B_PUBLISHER_ID = 318,0,0,1 %; literal ISO$SVD$S_PUBLISHER_ID = 128; ! Publisher Identifier macro ISO$SVD$B_DATA_PREPARER_ID = 446,0,0,1 %; literal ISO$SVD$S_DATA_PREPARER_ID = 128; ! Data Preparer Identifier macro ISO$SVD$B_APPLICATION_ID = 574,0,0,1 %; literal ISO$SVD$S_APPLICATION_ID = 128; ! Application Identifier macro ISO$SVD$B_COPYRIGHT_FILE_ID = 702,0,0,1 %; literal ISO$SVD$S_COPYRIGHT_FILE_ID = 37; ! Copyright File Identifier macro ISO$SVD$B_ABSTRACT_FILE_ID = 739,0,0,1 %; literal ISO$SVD$S_ABSTRACT_FILE_ID = 37; ! Abstract File Identifier macro ISO$SVD$B_BIBLIOGRAPHIC_ID = 776,0,0,1 %; literal ISO$SVD$S_BIBLIOGRAPHIC_ID = 37; ! Bibliographic File Identifier macro ISO$SVD$B_VOLUME_CREATION = 813,0,0,1 %; literal ISO$SVD$S_VOLUME_CREATION = 17; ! Volume Creation Date/Time macro ISO$SVD$B_VOLUME_MODIFIY = 830,0,0,1 %; literal ISO$SVD$S_VOLUME_MODIFIY = 17; ! Volume Modification Date/Time macro ISO$SVD$B_VOLUME_EXPIRATION = 847,0,0,1 %; literal ISO$SVD$S_VOLUME_EXPIRATION = 17; ! Volume Expiration Date/Time macro ISO$SVD$B_VOLUME_EFFECTIVE = 864,0,0,1 %; literal ISO$SVD$S_VOLUME_EFFECTIVE = 17; ! Volume Effective Date/Time macro ISO$SVD$B_FILE_STRUCTURE_VERS = 881,0,8,0 %; ! File Structure Version macro ISO$SVD$B_APPLICATION_USE = 883,0,0,1 %; literal ISO$SVD$S_APPLICATION_USE = 512; ! Application Use field ! + ! Volume Partition Descriptor ! ! The Volume Partition Descriptor shall identify a volume partition with ! the Volume Space, a system which can recognize and act upon the content ! of fields reserved for system use in the Volume Descriptor, the position ! and size of the volume partition, the version of the standard which ! applies to the Volume Descriptor. ! ! - literal ISO$VPD$S_VPD = 2048; ! Old size name - synonym literal ISO$VPD$S_F11C_VPD = 2048; macro ISO$VPD$B_VOLUME_PARTITION = 0,0,0,1 %; literal ISO$VPD$S_VOLUME_PARTITION = 7; ! Volume Partition Descriptor macro ISO$VPD$T_SYSTEM_IDENTIFIER = 8,0,0,0 %; literal ISO$VPD$S_SYSTEM_IDENTIFIER = 32; ! System Identifier macro ISO$VPD$T_PARTITION_IDENTIFIER = 40,0,0,0 %; literal ISO$VPD$S_PARTITION_IDENTIFIER = 32; ! Volume Partition Identifier macro ISO$VPD$L_PARTITION_LOCATION = 72,0,32,0 %; ! Location of Partition (LBN) macro ISO$VPD$L_PARTITION_LOCATION_M = 76,0,32,0 %; ! Location of Partition (LBN) macro ISO$VPD$L_PARTITION_SIZE = 80,0,32,0 %; ! Volume Partition Size macro ISO$VPD$L_PARTITION_SIZE_M = 84,0,32,0 %; ! Volume Partition Size macro ISO$VPD$B_SYSTEM_USE = 88,0,0,1 %; literal ISO$VPD$S_SYSTEM_USE = 1960; ! System Used ! ! ---- < End of module F11CDEF.R32 - 30-MAR-2010 16:38:42.01 > - ! ! ! ************************************************************************* ! * * ! * © Copyright 2010, Hewlett-Packard Development Company, L.P. * ! * * ! * Confidential computer software. Valid license from HP and/or * ! * its subsidiaries required for possession, use, or copying. * ! * * ! * Consistent with FAR 12.211 and 12.212, Commercial Computer Software, * ! * Computer Software Documentation, and Technical Data for Commercial * ! * Items are licensed to the U.S. Government under vendor's standard * ! * commercial license. * ! * * ! * Neither HP nor any of its subsidiaries shall be liable for technical * ! * or editorial errors or omissions contained herein. The information * ! * in this document is provided "as is" without warranty of any kind and * ! * is subject to change without notice. The warranties for HP products * ! * are set forth in the express limited warranty statements accompanying * ! * such products. Nothing herein should be construed as constituting an * ! * additional warranty. * ! * * ! ************************************************************************* ! ******************************************************************************************************************************** ! Created: 30-Mar-2010 16:11:25 by OpenVMS SDL EV3-3 ! Source: 13-MAY-1993 10:46:37 $1$DGA7374:[LIB.SRC]F11DDEF.SDL;1 ! ******************************************************************************************************************************** !*** MODULE $F11DDEF IDENT X-3 *** ! ! File sections shall be recorded in the Data Area. The following types of ! descriptors shall be record in the data area of a volume. ! ! o Volume Descriptors ! o Boot Record (BOOT) ! o Volume Descriptor Set Terminator (VDST) ! o Primary Volume Descriptor (PVD) ! o Supplementary Volume Descriptor (SVD) ! o Volume Partition Descriptor (VPD) ! o File Descriptors ! o Directory Descriptors ! o Path Tables ! ! ! ISO 9660 standard constants ! literal HS$K_LOGICAL_BLOCK_SIZE = 2048; ! Current Volume Descriptor Block Size literal HS$K_SYSTEM_AREA = 0; ! Logical Block number of System Area literal HS$K_DATA_AREA = 16; ! Logical Block number of Data Area literal HS$K_ISO_9660_VERSION_1988 = 1; ! Volume Descriptor Version # for ISO 9660 (1988) ! ! Character set coding ! literal HS$K_SPACE = 32; ! ' ' fill character literal HS$K_FULL_STOP = 46; ! '.'-filename.extension break literal HS$K_SEMICOLON = 59; ! ';'-extension;version break literal HS$K_ROOT_DIRECTORY_ID = 0; ! Root Directory Identifier literal HS$K_PARENT_DIRECTORY_ID = 1; ! Parent Directory Identifier ! + ! FILE_ID ! ! A File Identifier consist of the following sequence: ! - File name : A sequence of 0 -> 30 'D' or 'D1' characters ! - FULL_STOP ! - Extension : A sequence of 0 -> 30 'D' or 'D1' characters ! - SEMICOLON ! - Version # : A sequence of 1 to 5 digits; up to "32767" ! If 'File Name' length equals 0, then Extension must be 1 or greater ! If 'Extension' length equals 0, then File Name must be 1 or greater ! if 'Version' length equals 0, then Version is assumed to be 1 ! The length of 'File Name' + 'Extension' must not exceed 30. ! - literal HS$FNAME$S_FILE_ID = 32; ! Old size name - synonym literal HS$FNAME$S_F11D_FILE_ID = 32; ! + ! Identifier ! ! This descriptor shall specify an identifier. If all bytes in this ! field are set to %X20, it shall mean that no such identifier is defined. ! - literal HS$ID$S_IDENTIFIER = 128; ! Old size name - synonym literal HS$ID$S_F11D_IDENTIFIER = 128; macro HS$ID$B_DATA = 0,0,0,1 %; literal HS$ID$S_DATA = 128; ! Text Identifier ! + ! ASCII_DATE_TIME ! ! The date and time shall be represented by a 16-byte field. ! If Byte positions 1-16 are the digit '0' then ! it shall mean that date and time are not specified. ! - literal HS$AUTC$S_ASCII_DATE_TIME = 16; ! Old size name - synonym literal HS$AUTC$S_F11D_ASCII_DATE = 16; macro HS$AUTC$T_YEAR = 0,0,32,0 %; literal HS$AUTC$S_YEAR = 4; ! year (1-9999) macro HS$AUTC$T_MONTH = 4,0,16,0 %; literal HS$AUTC$S_MONTH = 2; ! month (1-12) macro HS$AUTC$T_DAY = 6,0,16,0 %; literal HS$AUTC$S_DAY = 2; ! day (1-31) macro HS$AUTC$T_HOUR = 8,0,16,0 %; literal HS$AUTC$S_HOUR = 2; ! hour (0-23) macro HS$AUTC$T_MINUTE = 10,0,16,0 %; literal HS$AUTC$S_MINUTE = 2; ! minute (0-59) macro HS$AUTC$T_SECOND = 12,0,16,0 %; literal HS$AUTC$S_SECOND = 2; ! second (0-59) macro HS$AUTC$T_HUNDREDTH = 14,0,16,0 %; literal HS$AUTC$S_HUNDREDTH = 2; ! hundredth (0-99) ! + ! BINARY_DATE_TIME ! ! The data and time shall be represented by six 8-bit numbers ! - literal HS$BUTC$S_BINARY_DATE_TIME = 6; ! Old size name - synonym literal HS$BUTC$S_F11D_BINARY_DATE = 6; macro HS$BUTC$B_YEAR = 0,0,8,0 %; ! year since 1900 (1-99) macro HS$BUTC$B_MONTH = 1,0,8,0 %; ! month (1-12) macro HS$BUTC$B_DAY = 2,0,8,0 %; ! day (1-31) macro HS$BUTC$B_HOUR = 3,0,8,0 %; ! hour (0-23) macro HS$BUTC$B_MINUTE = 4,0,8,0 %; ! minute (0-59) macro HS$BUTC$B_SECOND = 5,0,8,0 %; ! second (0-59) ! + ! PATH_TABLE_RECORD ! ! A Path Table contain a set of records describing a directory hierarchy ! for those volume of a Volume Set the sequence numbers of which are less ! than, or equal to, the assigned Volume Set size of the volume. ! ! For each directory in the directory hierarchy other then the Root ! Directory, the Path Table shall contain a record which identifies ! the directory, its Parent Directory and its location. The records ! in a Path Table shall be number starting at 1. The first record in ! the Path Table shall identify the Root Directory and it location. ! ! - literal HS$PTBL$S_PATH_TABLE_RECORD = 40; ! Old size name - synonym literal HS$PTBL$S_F11D_PATH_TABLE_REC = 40; macro HS$PTBL$L_EXTENT_LOCATION = 0,0,32,0 %; ! Location of Extent macro HS$PTBL$B_XAR_LENGTH = 4,0,8,0 %; ! Extended Attribute Record length macro HS$PTBL$B_DIRECTORY_ID_LENGTH = 5,0,8,0 %; ! Length of directory Identifier macro HS$PTBL$W_PARENT_DIRECTORY = 6,0,16,0 %; ! Parent Directory Number macro HS$PTBL$T_DIRECTORY_ID = 8,0,0,0 %; literal HS$PTBL$S_DIRECTORY_ID = 32; ! Directory Identifier (dirname) ! + ! DIRECTORY ! This descriptor shall define a directory record. A directory record ! contains information to locate a File Section; an Extended Attribute ! Record associated with a File Section; the identification of a file; ! attributes of a file and file section. ! - literal HS$DREC$M_EXISTENCE = %X'1'; literal HS$DREC$M_DIRECTORY = %X'2'; literal HS$DREC$M_ASSOCIATED = %X'4'; literal HS$DREC$M_RECORD = %X'8'; literal HS$DREC$M_PROTECTION = %X'10'; literal HS$DREC$M_RESERVED = %X'60'; literal HS$DREC$M_MULTI_EXTENT = %X'80'; literal HS$DREC$A_PADDING = 34; ! Pad byte literal HS$DREC$A_SYSTEM_USE = 34; ! System use literal HS$DREC$S_DIRECTORY = 512; ! Old size name - synonym literal HS$DREC$S_F11D_DIRECTORY = 512; macro HS$DREC$B_DIRECTORY_LENGTH = 0,0,8,0 %; ! Length of directory record macro HS$DREC$B_XAR_LENGTH = 1,0,8,0 %; ! Extended Attribute Length macro HS$DREC$L_EXTENT_LOCATION = 2,0,32,0 %; ! Location of Extent (LBN) macro HS$DREC$L_EXTENT_LOCATION_M = 6,0,32,0 %; ! Location of Extent (LBN) macro HS$DREC$L_DATA_LENGTH = 10,0,32,0 %; ! Data Length of File Section macro HS$DREC$L_DATA_LENGTH_M = 14,0,32,0 %; ! Data Length of File Section macro HS$DREC$B_FILE_RECORDING = 18,0,0,1 %; literal HS$DREC$S_FILE_RECORDING = 6; ! Recording Date/Time of extent macro HS$DREC$B_FILE_FLAGS = 24,0,8,0 %; ! File characteristics macro HS$DREC$V_EXISTENCE = 24,0,1,0 %; ! If set; nonexistent macro HS$DREC$V_DIRECTORY = 24,1,1,0 %; ! If set; directory record macro HS$DREC$V_ASSOCIATED = 24,2,1,0 %; ! If set; associated file macro HS$DREC$V_RECORD = 24,3,1,0 %; ! If set; record format via XAR.RFM macro HS$DREC$V_PROTECTION = 24,4,1,0 %; ! If set; enforce protection macro HS$DREC$V_MULTI_EXTENT = 24,7,1,0 %; ! If set; extend record macro HS$DREC$B_FILE_UNIT_SIZE = 26,0,8,0 %; ! Interleave File Unit Size macro HS$DREC$B_INTERLEAVE_GAP = 27,0,8,0 %; ! Interleave gap size macro HS$DREC$W_VOLUME_NUMBER = 28,0,16,0 %; ! Volume Sequence # of extent macro HS$DREC$W_VOLUME_NUMBER_M = 30,0,16,0 %; ! Volume Sequence # of extent macro HS$DREC$B_FILE_ID_LENGTH = 32,0,8,0 %; ! File Identifier Field Length macro HS$DREC$B_FILE_ID = 33,0,8,1 %; ! File Identifier ! + ! XAR_RECORD ! This descriptor shall define an Extended Attribute Record. An ! extended attribute record contains addition information which ! is associated to a File Section. ! ! - literal HS$XAR$M_SYS_NO_READ = %X'1'; literal HS$XAR$M_FILL_1 = %X'2'; literal HS$XAR$M_SYS_NO_EXECUTE = %X'4'; literal HS$XAR$M_FILL_2 = %X'8'; literal HS$XAR$M_OWN_NO_READ = %X'10'; literal HS$XAR$M_FILL_3 = %X'20'; literal HS$XAR$M_OWN_NO_EXECUTE = %X'40'; literal HS$XAR$M_FILL_4 = %X'80'; literal HS$XAR$M_GRP_NO_READ = %X'100'; literal HS$XAR$M_FILL_5 = %X'200'; literal HS$XAR$M_GRP_NO_EXECUTE = %X'400'; literal HS$XAR$M_FILL_6 = %X'800'; literal HS$XAR$M_WLD_NO_READ = %X'1000'; literal HS$XAR$M_FILL_7 = %X'2000'; literal HS$XAR$M_WLD_NO_EXECUTE = %X'4000'; literal HS$XAR$M_FILL_8 = %X'8000'; literal HS$XAR$RFM$K_UNDEFINED = 0; literal HS$XAR$RFM$K_FIXED = 1; literal HS$XAR$RFM$K_LSB_VARIABLE = 2; literal HS$XAR$RFM$K_MSB_VARIABLE = 3; literal HS$XAR$RFM$SYS$K_UNDEFINED = 128; literal HS$XAR$RFM$SYS$K_FIXED = 129; literal HS$XAR$RFM$SYS$K_VARIABLE = 130; literal HS$XAR$RFM$SYS$K_VFC = 131; literal HS$XAR$RFM$SYS$K_STREAM = 132; literal HS$XAR$RFM$SYS$K_STREAMLF = 133; literal HS$XAR$RFM$SYS$K_STREAMCR = 134; literal HS$XAR$ATR$K_CRLF = 0; literal HS$XAR$ATR$K_FTN = 1; literal HS$XAR$ATR$K_STM = 2; literal HS$XAR$S_XAR_RECORD = 512; ! Old size name - synonym literal HS$XAR$S_F11D_XAR_RECORD = 512; macro HS$XAR$W_OWNER_ID = 0,0,16,0 %; ! Owner Identification macro HS$XAR$W_OWNER_ID_M = 2,0,16,0 %; ! Owner Identification macro HS$XAR$W_GROUP_ID = 4,0,16,0 %; ! Group Identification macro HS$XAR$W_GROUP_ID_M = 6,0,16,0 %; ! Group Identification macro HS$XAR$W_PERMISSIONS = 8,0,16,0 %; ! Access permission for classes of users macro HS$XAR$V_SYS_NO_READ = 8,0,1,0 %; ! If set; ~(S:R) macro HS$XAR$V_SYS_NO_EXECUTE = 8,2,1,0 %; ! If set; ~(S:E) macro HS$XAR$V_OWN_NO_READ = 8,4,1,0 %; ! If set; ~(O:R) macro HS$XAR$V_OWN_NO_EXECUTE = 8,6,1,0 %; ! If set; ~(O:E) macro HS$XAR$V_GRP_NO_READ = 8,8,1,0 %; ! If set; ~(G:R) macro HS$XAR$V_GRP_NO_EXECUTE = 8,10,1,0 %; ! If set; ~(G:E) macro HS$XAR$V_WLD_NO_READ = 8,12,1,0 %; ! If set; ~(W:R) macro HS$XAR$V_WLD_NO_EXECUTE = 8,14,1,0 %; ! If set; ~(W:E) macro HS$XAR$B_FILE_CREATION = 10,0,0,1 %; literal HS$XAR$S_FILE_CREATION = 16; ! File Creation Date/Time macro HS$XAR$B_FILE_MODIFICATION = 26,0,0,1 %; literal HS$XAR$S_FILE_MODIFICATION = 16; ! File Modification Date/Time macro HS$XAR$B_FILE_EXPIRATION = 42,0,0,1 %; literal HS$XAR$S_FILE_EXPIRATION = 16; ! File Expiration Date/Time macro HS$XAR$B_FILE_EFFECTIVE = 58,0,0,1 %; literal HS$XAR$S_FILE_EFFECTIVE = 16; ! File Effective Date/Time macro HS$XAR$B_RECORD_FORMAT = 74,0,8,0 %; ! Record Format macro HS$XAR$B_RECORD_ATTRIBUTES = 75,0,8,0 %; ! Record Attributes macro HS$XAR$W_RECORD_LENGTH = 76,0,16,0 %; ! Record Length macro HS$XAR$W_RECORD_LENGTH_M = 78,0,16,0 %; ! Record Length macro HS$XAR$T_SYSTEM_ID = 80,0,0,0 %; literal HS$XAR$S_SYSTEM_ID = 32; ! System Identifier macro HS$XAR$B_SYSTEM_USE = 112,0,0,1 %; literal HS$XAR$S_SYSTEM_USE = 64; ! System Used macro HS$XAR$B_XAR_VERSION = 176,0,8,0 %; ! Extended Attribute Version macro HS$XAR$W_PARENT_DIRECTORY = 241,0,16,0 %; ! Parent Directory Number macro HS$XAR$W_PARENT_DIRECTORY_M = 243,0,16,0 %; ! Parent Directory Number macro HS$XAR$W_APPLICATION_LENGTH = 245,0,16,0 %; ! Application Use Length macro HS$XAR$W_APPLICATION_LENGTH_M = 247,0,16,0 %; ! Application Use Length macro HS$XAR$B_ROOT_DIRECTORY = 249,0,0,1 %; literal HS$XAR$S_ROOT_DIRECTORY = 34; ! Root Directory Record macro HS$XAR$B_APPLICATION_USE = 283,0,0,1 %; literal HS$XAR$S_APPLICATION_USE = 229; ! Application Use ! + ! Volume Descriptor ! ! The Volume Descriptor shall Identify the volume, the partitions recorded ! on the volume, the volume creator(s), certain attributes of the volume, ! the location of other recorded descriptors and the version of the ! standard which applies to the volume descriptor. ! ! - literal HS$VD$K_BOOT = 0; ! Boot Record Descriptor literal HS$VD$K_PVD = 1; ! Primary Volume Descriptor literal HS$VD$K_SVD = 2; ! Supplementary Volume Descriptor literal HS$VD$K_VPD = 3; ! Volume Partition Descriptor ! (Values 4 to 254 are reserved) literal HS$VD$K_VDST = 255; ! Volume Descriptor Set Terminator literal HS$VD$S_VD = 2048; ! Old size name - synonym literal HS$VD$S_F11D_VD = 2048; macro HS$VD$L_DESCRIPTOR_LBN = 0,0,32,0 %; ! LBN of first logical block macro HS$VD$L_DESCRIPTOR_LBN_M = 4,0,32,0 %; ! LBN of first logical block macro HS$VD$B_VOLUME_DESCRIPTOR_TYPE = 8,0,8,0 %; ! Volume Descriptor Type macro HS$VD$T_STANDARD_IDENTIFIER = 9,0,0,0 %; literal HS$VD$S_STANDARD_IDENTIFIER = 5; ! International Standard Id. (CDROM) macro HS$VD$B_VOLUME_DESCRIPTOR_VERS = 14,0,8,0 %; ! Volume Descriptor Version macro HS$VD$B_VOLUME_DATA = 15,0,0,1 %; literal HS$VD$S_VOLUME_DATA = 2033; ! Volume Descriptor Data ! + ! Boot Record ! ! The Boot Record shall Identify a system which can recognize and act upon ! the content of the field reserved for boot system use in the Boot ! Record, and shall contain information which is used to achieve a ! specific state for a system or for an application. ! ! - literal HS$BOOT$S_BOOT = 2048; ! Old size name - synonym literal HS$BOOT$S_F11D_BOOT = 2048; macro HS$BOOT$B_BOOT_VOLUME = 0,0,0,1 %; literal HS$BOOT$S_BOOT_VOLUME = 15; ! Boot Volume Descriptor macro HS$BOOT$T_SYSTEM_IDENTIFIER = 15,0,0,0 %; literal HS$BOOT$S_SYSTEM_IDENTIFIER = 32; ! Boot System Identifier macro HS$BOOT$T_IDENTIFIER = 47,0,0,0 %; literal HS$BOOT$S_IDENTIFIER = 32; ! Boot Identifier macro HS$BOOT$B_SYSTEM_USE = 79,0,0,1 %; literal HS$BOOT$S_SYSTEM_USE = 1969; ! Boot System Use ! + ! Volume Descriptor Sequence Terminator ! ! The recorded set of Volume Descriptors shall be terminated by a sequence ! of one or more Volume Descriptor Set Terminators ! ! - literal HS$VDST$S_VDST = 2048; ! Old size name - synonym literal HS$VDST$S_F11D_VDST = 2048; macro HS$VDST$B_TERMINATOR_VOLUME = 0,0,0,1 %; literal HS$VDST$S_TERMINATOR_VOLUME = 15; ! Volume Descriptor Set ! + ! Standard File Structure Volume Descriptor ! ! The Standard File Structure Volume Descriptor shall Identify the volume, a system which ! can recognize and act upon the content of the Logical Sectors with ! Logical Sector Number 0 to 15, the size of the Volume Space, the version ! of the standard which applies to the Volume Descriptor, the version of ! the specification which applies to the Directory Records and the Path ! Table Records and certain attributes of the volume. ! ! - literal HS$PVD$S_PVD = 2048; ! Old size name - synonym literal HS$PVD$S_F11D_PVD = 2048; macro HS$PVD$B_PRIMARY_VOLUME = 0,0,0,1 %; literal HS$PVD$S_PRIMARY_VOLUME = 15; ! Standard File Structure Volume Descriptor macro HS$PVD$T_SYSTEM_IDENTIFIER = 16,0,0,0 %; literal HS$PVD$S_SYSTEM_IDENTIFIER = 32; ! System Identifier macro HS$PVD$T_VOLUME_IDENTIFIER = 48,0,0,0 %; literal HS$PVD$S_VOLUME_IDENTIFIER = 32; ! Volume Identifier macro HS$PVD$L_VOLUME_SPACE_SIZE = 88,0,32,0 %; ! Volume Space Size macro HS$PVD$L_VOLUME_SPACE_SIZE_M = 92,0,32,0 %; ! Volume Space Size macro HS$PVD$W_VOLUME_SET_SIZE = 128,0,16,0 %; ! Volume Set Size macro HS$PVD$W_VOLUME_SET_SIZE_M = 130,0,16,0 %; ! Volume Set Size macro HS$PVD$W_VOLUME_NUMBER = 132,0,16,0 %; ! Volume Sequence Number macro HS$PVD$W_VOLUME_NUMBER_M = 134,0,16,0 %; ! Volume Sequence Number macro HS$PVD$W_LOGICAL_BLOCK_SIZE = 136,0,16,0 %; ! Logical Block Size macro HS$PVD$W_LOGICAL_BLOCK_SIZE_M = 138,0,16,0 %; ! Logical Block Size macro HS$PVD$L_PATH_TABLE_SIZE = 140,0,32,0 %; ! Path Table Size macro HS$PVD$L_PATH_TABLE_SIZE_M = 144,0,32,0 %; ! Path Table Size macro HS$PVD$L_PATH_TABLE = 148,0,32,0 %; ! Path Table Logical Block # macro HS$PVD$L_OPT_PATH_TABLE = 152,0,32,0 %; ! Optional Path Table Logical Block # macro HS$PVD$L_OPT_PATH_TABLE_1 = 156,0,32,0 %; ! Optional Path Table Logical Block # macro HS$PVD$L_OPT_PATH_TABLE_2 = 160,0,32,0 %; ! Optional Path Table Logical Block # macro HS$PVD$L_PATH_TABLE_M = 164,0,32,0 %; ! Path Table Logical Block # macro HS$PVD$L_OPT_PATH_TABLE_M = 168,0,32,0 %; ! Optional Path Table Logical Block # macro HS$PVD$L_OPT_PATH_TABLE_M1 = 172,0,32,0 %; ! Optional Path Table Logical Block # macro HS$PVD$L_OPT_PATH_TABLE_M2 = 176,0,32,0 %; ! Optional Path Table Logical Block # macro HS$PVD$B_ROOT_DIRECTORY = 180,0,0,1 %; literal HS$PVD$S_ROOT_DIRECTORY = 34; ! Root Directory Record macro HS$PVD$T_VOLUME_SET_IDENTIFIER = 214,0,0,0 %; literal HS$PVD$S_VOLUME_SET_IDENTIFIER = 128; ! Volume Set Identifier macro HS$PVD$B_PUBLISHER_ID = 342,0,0,1 %; literal HS$PVD$S_PUBLISHER_ID = 128; ! Publisher Identifier macro HS$PVD$B_DATA_PREPARER_ID = 470,0,0,1 %; literal HS$PVD$S_DATA_PREPARER_ID = 128; ! Data Preparer Identifier macro HS$PVD$B_APPLICATION_ID = 598,0,0,1 %; literal HS$PVD$S_APPLICATION_ID = 128; ! Application Identifier macro HS$PVD$B_COPYRIGHT_FILE_ID = 726,0,0,1 %; literal HS$PVD$S_COPYRIGHT_FILE_ID = 32; ! Copyright File Identifier macro HS$PVD$B_ABSTRACT_FILE_ID = 758,0,0,1 %; literal HS$PVD$S_ABSTRACT_FILE_ID = 32; ! Abstract File Identifier macro HS$PVD$B_VOLUME_CREATION = 790,0,0,1 %; literal HS$PVD$S_VOLUME_CREATION = 16; ! Volume Creation Date/Time macro HS$PVD$B_VOLUME_MODIFIY = 806,0,0,1 %; literal HS$PVD$S_VOLUME_MODIFIY = 16; ! Volume Modification Date/Time macro HS$PVD$B_VOLUME_EXPIRATION = 822,0,0,1 %; literal HS$PVD$S_VOLUME_EXPIRATION = 16; ! Volume Expiration Date/Time macro HS$PVD$B_VOLUME_EFFECTIVE = 838,0,0,1 %; literal HS$PVD$S_VOLUME_EFFECTIVE = 16; ! Volume Effective Date/Time macro HS$PVD$B_FILE_STRUCTURE_VERS = 854,0,8,0 %; ! File Structure Version macro HS$PVD$B_APPLICATION_USE = 856,0,0,1 %; literal HS$PVD$S_APPLICATION_USE = 512; ! Application Use field ! + ! Coded Character Set File Structure Volume Descriptor ! ! The Coded Character Set File Structure Volume Descriptor Supplementary shall ! Identify the volume, a system which can recognize and act upon the content of ! the Logical Sectors with Logical Sector Number 0 to 15, the size of the ! Volume Space, the version of the standard which applies to the Volume ! Descriptor, the version of the specification which applies to the Directory ! Records and the Path Table Records, certain attributes of the volume and the ! coded graphic character sets used to interpret descriptor fields that contain ! characters. ! ! - literal HS$SVD$M_NON_ISO_2375 = %X'1'; literal HS$SVD$S_SVD = 2048; ! Old size name - synonym literal HS$SVD$S_F11D_SVD = 2048; macro HS$SVD$B_SUPPLEMENTARY_VOLUME = 0,0,0,1 %; literal HS$SVD$S_SUPPLEMENTARY_VOLUME = 15; ! Coded Character Set File Structure Volume Descriptor macro HS$SVD$B_VOLUME_FLAGS = 15,0,8,0 %; ! Volume characteristics macro HS$SVD$V_NON_ISO_2375 = 15,0,1,0 %; ! If set; Escape Sequence is non ISO-2375 compliant macro HS$SVD$T_SYSTEM_IDENTIFIER = 16,0,0,0 %; literal HS$SVD$S_SYSTEM_IDENTIFIER = 32; ! System Identifier macro HS$SVD$T_VOLUME_IDENTIFIER = 48,0,0,0 %; literal HS$SVD$S_VOLUME_IDENTIFIER = 32; ! Volume Identifier macro HS$SVD$L_VOLUME_SPACE_SIZE = 88,0,32,0 %; ! Volume Space Size macro HS$SVD$L_VOLUME_SPACE_SIZE_M = 92,0,32,0 %; ! Volume Space Size macro HS$SVD$B_ESCAPE_SEQUENCES = 96,0,0,1 %; literal HS$SVD$S_ESCAPE_SEQUENCES = 32; ! Coded Character Set for Descriptor Id macro HS$SVD$W_VOLUME_SET_SIZE = 128,0,16,0 %; ! Volume Set Size macro HS$SVD$W_VOLUME_SET_SIZE_M = 130,0,16,0 %; ! Volume Set Size macro HS$SVD$W_VOLUME_NUMBER = 132,0,16,0 %; ! Volume Sequence Number macro HS$SVD$W_VOLUME_NUMBER_M = 134,0,16,0 %; ! Volume Sequence Number macro HS$SVD$W_LOGICAL_BLOCK_SIZE = 136,0,16,0 %; ! Logical Block Size macro HS$SVD$W_LOGICAL_BLOCK_SIZE_M = 138,0,16,0 %; ! Logical Block Size macro HS$SVD$L_PATH_TABLE_SIZE = 140,0,32,0 %; ! Path Table Size macro HS$SVD$L_PATH_TABLE_SIZE_M = 144,0,32,0 %; ! Path Table Size macro HS$SVD$L_PATH_TABLE = 148,0,32,0 %; ! Path Table Logical Block # macro HS$SVD$L_OPT_PATH_TABLE = 152,0,32,0 %; ! Optional Path Table Logical Block # macro HS$SVD$L_OPT_PATH_TABLE_1 = 156,0,32,0 %; ! Optional Path Table Logical Block # macro HS$SVD$L_OPT_PATH_TABLE_2 = 160,0,32,0 %; ! Optional Path Table Logical Block # macro HS$SVD$L_PATH_TABLE_M = 164,0,32,0 %; ! Path Table Logical Block # macro HS$SVD$L_OPT_PATH_TABLE_M = 168,0,32,0 %; ! Optional Path Table Logical Block # macro HS$SVD$L_OPT_PATH_TABLE_M1 = 172,0,32,0 %; ! Optional Path Table Logical Block # macro HS$SVD$L_OPT_PATH_TABLE_M2 = 176,0,32,0 %; ! Optional Path Table Logical Block # macro HS$SVD$B_ROOT_DIRECTORY = 180,0,0,1 %; literal HS$SVD$S_ROOT_DIRECTORY = 34; ! Root Directory Record macro HS$SVD$T_VOLUME_SET_IDENTIFIER = 214,0,0,0 %; literal HS$SVD$S_VOLUME_SET_IDENTIFIER = 128; ! Volume Set Identifier macro HS$SVD$B_PUBLISHER_ID = 342,0,0,1 %; literal HS$SVD$S_PUBLISHER_ID = 128; ! Publisher Identifier macro HS$SVD$B_DATA_PREPARER_ID = 470,0,0,1 %; literal HS$SVD$S_DATA_PREPARER_ID = 128; ! Data Preparer Identifier macro HS$SVD$B_APPLICATION_ID = 598,0,0,1 %; literal HS$SVD$S_APPLICATION_ID = 128; ! Application Identifier macro HS$SVD$B_COPYRIGHT_FILE_ID = 726,0,0,1 %; literal HS$SVD$S_COPYRIGHT_FILE_ID = 32; ! Copyright File Identifier macro HS$SVD$B_ABSTRACT_FILE_ID = 758,0,0,1 %; literal HS$SVD$S_ABSTRACT_FILE_ID = 32; ! Abstract File Identifier macro HS$SVD$B_VOLUME_CREATION = 790,0,0,1 %; literal HS$SVD$S_VOLUME_CREATION = 16; ! Volume Creation Date/Time macro HS$SVD$B_VOLUME_MODIFIY = 806,0,0,1 %; literal HS$SVD$S_VOLUME_MODIFIY = 16; ! Volume Modification Date/Time macro HS$SVD$B_VOLUME_EXPIRATION = 822,0,0,1 %; literal HS$SVD$S_VOLUME_EXPIRATION = 16; ! Volume Expiration Date/Time macro HS$SVD$B_VOLUME_EFFECTIVE = 838,0,0,1 %; literal HS$SVD$S_VOLUME_EFFECTIVE = 16; ! Volume Effective Date/Time macro HS$SVD$B_FILE_STRUCTURE_VERS = 854,0,8,0 %; ! File Structure Version macro HS$SVD$B_APPLICATION_USE = 856,0,0,1 %; literal HS$SVD$S_APPLICATION_USE = 512; ! Application Use field ! + ! Unspecified Partition Descriptor ! ! The Unspecified Volume Partition Descriptor shall identify a volume partition with ! the Volume Space, a system which can recognize and act upon the content ! of fields reserved for system use in the Volume Descriptor, the position ! and size of the volume partition, the version of the standard which ! applies to the Volume Descriptor. ! ! - literal HS$VPD$S_VPD = 2048; ! Old size name - synonym literal HS$VPD$S_F11D_VPD = 2048; macro HS$VPD$B_VOLUME_PARTITION = 0,0,0,1 %; literal HS$VPD$S_VOLUME_PARTITION = 15; ! Unspecified Volume Partition Descriptor macro HS$VPD$T_SYSTEM_IDENTIFIER = 16,0,0,0 %; literal HS$VPD$S_SYSTEM_IDENTIFIER = 32; ! System Identifier macro HS$VPD$T_PARTITION_IDENTIFIER = 48,0,0,0 %; literal HS$VPD$S_PARTITION_IDENTIFIER = 32; ! Volume Partition Identifier macro HS$VPD$L_PARTITION_LOCATION = 80,0,32,0 %; ! Location of Partition (LBN) macro HS$VPD$L_PARTITION_LOCATION_M = 84,0,32,0 %; ! Location of Partition (LBN) macro HS$VPD$L_PARTITION_SIZE = 88,0,32,0 %; ! Volume Partition Size macro HS$VPD$L_PARTITION_SIZE_M = 92,0,32,0 %; ! Volume Partition Size macro HS$VPD$B_SYSTEM_USE = 96,0,0,1 %; literal HS$VPD$S_SYSTEM_USE = 1952; ! System Use ! ! ---- < End of module F11DDEF.R32 - 30-MAR-2010 16:38:43.82 > - ! ! ! ************************************************************************* ! * * ! * © Copyright 2010, Hewlett-Packard Development Company, L.P. * ! * * ! * Confidential computer software. Valid license from HP and/or * ! * its subsidiaries required for possession, use, or copying. * ! * * ! * Consistent with FAR 12.211 and 12.212, Commercial Computer Software, * ! * Computer Software Documentation, and Technical Data for Commercial * ! * Items are licensed to the U.S. Government under vendor's standard * ! * commercial license. * ! * * ! * Neither HP nor any of its subsidiaries shall be liable for technical * ! * or editorial errors or omissions contained herein. The information * ! * in this document is provided "as is" without warranty of any kind and * ! * is subject to change without notice. The warranties for HP products * ! * are set forth in the express limited warranty statements accompanying * ! * such products. Nothing herein should be construed as constituting an * ! * additional warranty. * ! * * ! ************************************************************************* ! ******************************************************************************************************************************** ! Created: 30-Mar-2010 16:10:59 by OpenVMS SDL EV3-3 ! Source: 14-NOV-2008 16:48:53 $1$DGA7374:[LIB.SRC]F11DEF.SDL;1 ! ******************************************************************************************************************************** !*** MODULE $FH1DEF *** literal FH1$C_LEVEL1 = 257; ! 401 octal = structure level 1 literal FH1$K_LENGTH = 46; ! length of header area literal FH1$C_LENGTH = 46; ! length of header area literal FH1$S_FH1DEF = 512; ! Old size name - synonym literal FH1$S_FH1 = 512; macro FH1$B_IDOFFSET = 0,0,8,0 %; ! ident area offset in words macro FH1$B_MPOFFSET = 1,0,8,0 %; ! map area offset in words macro FH1$W_FID = 2,0,32,0 %; literal FH1$S_FID = 4; ! file ID macro FH1$W_FID_NUM = 2,0,16,0 %; ! file number macro FH1$W_FID_SEQ = 4,0,16,0 %; ! file sequence number macro FH1$W_STRUCLEV = 6,0,16,0 %; ! file structure level macro FH1$W_FILEOWNER = 8,0,16,0 %; ! file owner UIC macro FH1$B_UICMEMBER = 8,0,8,0 %; ! UIC member number macro FH1$B_UICGROUP = 9,0,8,0 %; ! UIC group number macro FH1$W_FILEPROT = 10,0,16,0 %; ! file protection macro FH1$V_SYSPRO = 10,0,4,0 %; literal FH1$S_SYSPRO = 4; ! system protection macro FH1$V_OWNPRO = 10,4,4,0 %; literal FH1$S_OWNPRO = 4; ! owner protection macro FH1$V_GROUPPRO = 10,8,4,0 %; literal FH1$S_GROUPPRO = 4; ! group protection macro FH1$V_WORLDPRO = 10,12,4,0 %; literal FH1$S_WORLDPRO = 4; ! world protection macro FH1$W_FILECHAR = 12,0,16,0 %; ! file characteristics macro FH1$B_USERCHAR = 12,0,8,0 %; ! user controlled characteristics macro FH1$V_WASCONTIG = 12,0,1,0 %; ! file was (and should be) contiguous macro FH1$V_NOBACKUP = 12,1,1,0 %; ! file is not to be backed up macro FH1$V_READCHECK = 12,3,1,0 %; ! verify all read operations macro FH1$V_WRITCHECK = 12,4,1,0 %; ! verify all write operations macro FH1$V_CONTIGB = 12,5,1,0 %; ! keep file as contiguous as possible macro FH1$V_LOCKED = 12,6,1,0 %; ! file is deaccess locked macro FH1$V_CONTIG = 12,7,1,0 %; ! file is contiguous macro FH1$B_SYSCHAR = 13,0,8,0 %; ! system controlled characteristics macro FH1$V_SPOOL = 13,4,1,0 %; ! intermediate spool file macro FH1$V_BADBLOCK = 13,6,1,0 %; ! file contains bad blocks macro FH1$V_MARKDEL = 13,7,1,0 %; ! file is marked for delete macro FH1$W_RECATTR = 14,0,0,0 %; literal FH1$S_RECATTR = 32; ! file record attributes macro FH1$W_CHECKSUM = 510,0,16,0 %; ! file header checksum !*** MODULE $FI1DEF *** literal FI1$K_LENGTH = 46; ! length of ident area literal FI1$C_LENGTH = 46; ! length of ident area literal FI1$S_FI1DEF = 286; ! Old size name - synonym literal FI1$S_FI1 = 286; macro FI1$W_FILENAME = 0,0,0,0 %; literal FI1$S_FILENAME = 6; ! file name (RAD-50) macro FI1$W_FILETYPE = 6,0,16,0 %; ! file type (RAD-50) macro FI1$W_VERSION = 8,0,16,0 %; ! version number (binary) macro FI1$W_REVISION = 10,0,16,0 %; ! revision number (binary) macro FI1$T_REVDATE = 12,0,0,0 %; literal FI1$S_REVDATE = 7; ! revision date (ASCII DDMMMYY) macro FI1$T_REVTIME = 19,0,0,0 %; literal FI1$S_REVTIME = 6; ! revision time (ASCII HHMMSS) macro FI1$T_CREDATE = 25,0,0,0 %; literal FI1$S_CREDATE = 7; ! creation date (ASCII DDMMMYY) macro FI1$T_CRETIME = 32,0,0,0 %; literal FI1$S_CRETIME = 6; ! creation time (ASCII HHMMSS) macro FI1$T_EXPDATE = 38,0,0,0 %; literal FI1$S_EXPDATE = 7; ! expiration date (ASCII DDMMMYY) macro FI1$T_MTHDR1 = 46,0,0,0 %; literal FI1$S_MTHDR1 = 80; ! HDR1 of ANSI magnetic tape file macro FI1$T_MTHDR2 = 126,0,0,0 %; literal FI1$S_MTHDR2 = 80; ! HDR2 of ANSI magnetic tape file macro FI1$T_MTHDR3 = 206,0,0,0 %; literal FI1$S_MTHDR3 = 80; ! HDR3 of ANSI magnetic tape file !*** MODULE $FM1DEF *** literal FM1$K_POINTERS = 10; ! start of retrieval pointers literal FM1$C_POINTERS = 10; ! start of retrieval pointers literal FM1$K_LENGTH = 10; ! length of map area literal FM1$C_LENGTH = 10; ! length of map area ! retrieval pointer format literal FM1$S_FM1DEF = 10; ! Old size name - synonym literal FM1$S_FM1 = 10; macro FM1$B_EX_SEGNUM = 0,0,8,0 %; ! extension segment number of this header macro FM1$B_EX_RVN = 1,0,8,0 %; ! extension relative volume number macro FM1$W_EX_FILNUM = 2,0,16,0 %; ! extension file number macro FM1$W_EX_FILSEQ = 4,0,16,0 %; ! extension file sequence number macro FM1$B_COUNTSIZE = 6,0,8,0 %; ! retrieval pointer count field size macro FM1$B_LBNSIZE = 7,0,8,0 %; ! retrieval pointer LBN field size macro FM1$B_INUSE = 8,0,8,0 %; ! number of retrieval words in use macro FM1$B_AVAIL = 9,0,8,0 %; ! number of retrieval words available literal FM1$S_FM1DEF1 = 4; ! Old size name - synonym literal FM1$S_FM1_1 = 4; macro FM1$B_HIGHLBN = 0,0,8,0 %; ! high order LBN macro FM1$B_COUNT = 1,0,8,0 %; ! block count macro FM1$W_LOWLBN = 2,0,16,0 %; ! low order LBN literal FM1$S_FM1DEF2 = 5; ! Old size name - synonym literal FM1$S_FM1_2 = 5; macro FM1$B_PREVHLBN = -4,0,8,0 %; macro FM1$B_PREVCOUNT = -3,0,8,0 %; macro FM1$W_PREVLLBN = -2,0,16,0 %; ! previous retrieval pointer !*** MODULE $FH2DEF *** ! + ! ! File header definitions for Files-11 Structure Level 2 ! ! - literal FH2$C_LEVEL1 = 257; ! 401 octal = structure level 1 literal FH2$C_LEVEL2 = 512; ! 1000 octal = structure level 2 literal FH2$C_LEVEL5 = 1280; ! 2400 octal = structure level 5 literal FH2$M_VCC_STATE = %X'700'; literal FH2$M_ALM_STATE = %X'C0000'; literal FH2$M_WASCONTIG = %X'1'; literal FH2$M_NOBACKUP = %X'2'; literal FH2$M_WRITEBACK = %X'4'; literal FH2$M_READCHECK = %X'8'; literal FH2$M_WRITCHECK = %X'10'; literal FH2$M_CONTIGB = %X'20'; literal FH2$M_LOCKED = %X'40'; literal FH2$M_CONTIG = %X'80'; literal FH2$M_BADACL = %X'800'; literal FH2$M_SPOOL = %X'1000'; literal FH2$M_DIRECTORY = %X'2000'; literal FH2$M_BADBLOCK = %X'4000'; literal FH2$M_MARKDEL = %X'8000'; literal FH2$M_NOCHARGE = %X'10000'; literal FH2$M_ERASE = %X'20000'; literal FH2$M_ALM_AIP = %X'40000'; literal FH2$M_SHELVED = %X'80000'; literal FH2$M_SCRATCH = %X'100000'; literal FH2$M_NOMOVE = %X'200000'; literal FH2$M_NOSHELVABLE = %X'400000'; literal FH2$M_PRESHELVED = %X'800000'; literal FH2$M_ALM_ARCHIVED = %X'80000'; literal FH2$M_SHELVING_RESERVED = %X'800000'; literal FH2$M_ONLY_RU = %X'1'; literal FH2$M_RUJNL = %X'2'; literal FH2$M_BIJNL = %X'4'; literal FH2$M_AIJNL = %X'8'; literal FH2$M_ATJNL = %X'10'; literal FH2$M_NEVER_RU = %X'20'; literal FH2$M_JOURNAL_FILE = %X'40'; literal FH2$C_RU_FACILITY_RMS = 1; ! RMS literal FH2$C_RU_FACILITY_DBMS = 2; ! DBMS literal FH2$C_RU_FACILITY_RDB = 3; ! Rdb/VMS literal FH2$C_RU_FACILITY_CHKPNT = 4; ! Checkpoint/Restart literal FH2$C_MAX_LINKS = 32760; ! maximum link count literal FH2$K_LENGTH = 80; ! length of header area literal FH2$C_LENGTH = 80; ! length of header area literal FH2$K_SUBSET0_LENGTH = 88; ! length of header area literal FH2$C_SUBSET0_LENGTH = 88; ! length of header area literal FH2$K_FULL_LENGTH = 108; ! length of full header literal FH2$C_FULL_LENGTH = 108; ! length of full header literal FH2$S_FH2DEF = 512; ! Old size name - synonym literal FH2$S_FH2 = 512; macro FH2$B_IDOFFSET = 0,0,8,0 %; ! ident area offset in words macro FH2$B_MPOFFSET = 1,0,8,0 %; ! map area offset in words macro FH2$B_ACOFFSET = 2,0,8,0 %; ! access control list offset in words macro FH2$B_RSOFFSET = 3,0,8,0 %; ! reserved area offset in words macro FH2$W_SEG_NUM = 4,0,16,0 %; ! file segment number macro FH2$W_STRUCLEV = 6,0,16,0 %; ! file structure level macro FH2$B_STRUCVER = 6,0,8,0 %; ! file structure version macro FH2$B_STRUCLEV = 7,0,8,0 %; ! principal file structure level macro FH2$W_FID = 8,0,0,0 %; literal FH2$S_FID = 6; ! file ID macro FH2$W_FID_NUM = 8,0,16,0 %; ! file number macro FH2$W_FID_SEQ = 10,0,16,0 %; ! file sequence number macro FH2$W_FID_RVN = 12,0,16,0 %; ! relative volume number macro FH2$B_FID_RVN = 12,0,8,0 %; ! alternate format RVN macro FH2$B_FID_NMX = 13,0,8,0 %; ! alternate format file number extension macro FH2$W_EXT_FID = 14,0,0,0 %; literal FH2$S_EXT_FID = 6; ! extension file ID macro FH2$W_EX_FIDNUM = 14,0,16,0 %; ! extension file number macro FH2$W_EX_FIDSEQ = 16,0,16,0 %; ! extension file sequence number macro FH2$W_EX_FIDRVN = 18,0,16,0 %; ! extension relative volume number macro FH2$B_EX_FIDRVN = 18,0,8,0 %; ! alternate format extension RVN macro FH2$B_EX_FIDNMX = 19,0,8,0 %; ! alternate format extension file number extension macro FH2$W_RECATTR = 20,0,0,0 %; literal FH2$S_RECATTR = 32; ! file record attributes macro FH2$L_FILECHAR = 52,0,32,0 %; ! file characteristics macro FH2$V_VCC_STATE = 52,8,3,0 %; literal FH2$S_VCC_STATE = 3; ! VCC state bits ! **********The following line is different from FH2 macro FH2$V_ALM_STATE = 52,18,2,0 %; literal FH2$S_ALM_STATE = 2; ! ALM state bits macro FH2$V_WASCONTIG = 52,0,1,0 %; ! file was (and should be) contiguous macro FH2$V_NOBACKUP = 52,1,1,0 %; ! file is not to be backed up macro FH2$V_WRITEBACK = 52,2,1,0 %; ! file may be write-back cached macro FH2$V_READCHECK = 52,3,1,0 %; ! verify all read operations macro FH2$V_WRITCHECK = 52,4,1,0 %; ! verify all write operations macro FH2$V_CONTIGB = 52,5,1,0 %; ! keep file as contiguous as possible macro FH2$V_LOCKED = 52,6,1,0 %; ! file is deaccess locked macro FH2$V_CONTIG = 52,7,1,0 %; ! file is contiguous macro FH2$V_BADACL = 52,11,1,0 %; ! ACL is invalid macro FH2$V_SPOOL = 52,12,1,0 %; ! intermediate spool file macro FH2$V_DIRECTORY = 52,13,1,0 %; ! file is a directory macro FH2$V_BADBLOCK = 52,14,1,0 %; ! file contains bad blocks macro FH2$V_MARKDEL = 52,15,1,0 %; ! file is marked for delete macro FH2$V_NOCHARGE = 52,16,1,0 %; ! file space is not to be charged macro FH2$V_ERASE = 52,17,1,0 %; ! erase file contents before deletion ! **********The following two lines are different from FCH macro FH2$V_ALM_AIP = 52,18,1,0 %; ! Archive in progress - ALM proj cancelled macro FH2$V_SHELVED = 52,19,1,0 %; ! File is shelved macro FH2$V_SCRATCH = 52,20,1,0 %; ! Scratch Header used by movefile macro FH2$V_NOMOVE = 52,21,1,0 %; ! Disable movefile on this file macro FH2$V_NOSHELVABLE = 52,22,1,0 %; ! File is not allowed to be shelved macro FH2$V_PRESHELVED = 52,23,1,0 %; ! File is shelved but also kept online ! Note: The high 8 bits of this longword ! are reserved for user and CSS use. macro FH2$V_ALM_ARCHIVED = 52,19,1,0 %; ! File archived - ALM proj cancelled macro FH2$V_SHELVING_RESERVED = 52,23,1,0 %; ! Original placeholder name for PRESHELVED macro FH2$W_RECPROT = 56,0,16,0 %; ! record protection macro FH2$B_MAP_INUSE = 58,0,8,0 %; ! number of map area words in use macro FH2$B_ACC_MODE = 59,0,8,0 %; ! least privileged access mode macro FH2$L_FILEOWNER = 60,0,32,0 %; ! file owner UIC macro FH2$W_UICMEMBER = 60,0,16,0 %; ! UIC member number macro FH2$W_UICGROUP = 62,0,16,0 %; ! UIC group number macro FH2$W_FILEPROT = 64,0,16,0 %; ! file protection macro FH2$W_BACKLINK = 66,0,0,0 %; literal FH2$S_BACKLINK = 6; ! back link pointer macro FH2$W_BK_FIDNUM = 66,0,16,0 %; ! back link file number macro FH2$W_BK_FIDSEQ = 68,0,16,0 %; ! back link file sequence number macro FH2$W_BK_FIDRVN = 70,0,16,0 %; ! back link relative volume number macro FH2$B_BK_FIDRVN = 70,0,8,0 %; ! alternate format back link RVN macro FH2$B_BK_FIDNMX = 71,0,8,0 %; ! alternate format back link file number extension macro FH2$B_JOURNAL = 72,0,8,0 %; ! journal control flags macro FH2$V_ONLY_RU = 72,0,1,0 %; ! file is accessible only in recovery unit macro FH2$V_RUJNL = 72,1,1,0 %; ! enable recovery unit journal macro FH2$V_BIJNL = 72,2,1,0 %; ! enable before image journal macro FH2$V_AIJNL = 72,3,1,0 %; ! enable after image journal macro FH2$V_ATJNL = 72,4,1,0 %; ! enable audit trail journal macro FH2$V_NEVER_RU = 72,5,1,0 %; ! file is never accessible in recovery unit macro FH2$V_JOURNAL_FILE = 72,6,1,0 %; ! this is a journal file macro FH2$B_RU_ACTIVE = 73,0,8,0 %; ! If non-zero, file has active recovery units ! (value is recoverable facility id number) ! 1-99 reserved to DEC, 100-127 reserved for ! CSS, 128-255 reserved for customers. macro FH2$W_LINKCOUNT = 74,0,16,1 %; ! (count of links) macro FH2$L_HIGHWATER = 76,0,32,0 %; ! high-water mark in file macro FH2$R_CLASS_PROT = 88,0,0,0 %; literal FH2$S_CLASS_PROT = 20; ! security classification mask macro FH2$W_CHECKSUM = 510,0,16,0 %; ! file header checksum !*** MODULE $FI2DEF *** literal FI2$K_LENGTH = 120; ! length of ident area literal FI2$C_LENGTH = 120; ! length of ident area literal FI2$S_FI2DEF = 200; ! Old size name - synonym literal FI2$S_FI2 = 200; macro FI2$T_FILENAME = 0,0,0,0 %; literal FI2$S_FILENAME = 20; ! file name, type, and version (ASCII) macro FI2$W_REVISION = 20,0,16,0 %; ! revision number (binary) macro FI2$Q_CREDATE = 22,0,0,0 %; literal FI2$S_CREDATE = 8; ! creation date and time macro FI2$Q_REVDATE = 30,0,0,0 %; literal FI2$S_REVDATE = 8; ! revision date and time macro FI2$Q_EXPDATE = 38,0,0,0 %; literal FI2$S_EXPDATE = 8; ! expiration date and time macro FI2$Q_BAKDATE = 46,0,0,0 %; literal FI2$S_BAKDATE = 8; ! backup date and time macro FI2$T_FILENAMEXT = 54,0,0,0 %; literal FI2$S_FILENAMEXT = 66; ! extension file name area macro FI2$T_USERLABEL = 120,0,0,0 %; literal FI2$S_USERLABEL = 80; ! optional user file label !*** MODULE $FI5DEF *** ! ! ODS-5 format ident area. This is the only structural ! difference between ODS-2 and ODS-5. ! literal FI5$C_ODS2 = 0; ! ODS-2 legal ASCII literal FI5$C_ISL1 = 1; ! ODS-2 illegal ASCII or ISO LATIN-1 literal FI5$$_TYPE_RESERVED = 2; literal FI5$C_UCS2 = 3; ! Unicode USC-2 (16 bit characters) literal FI5$M_FIXED_LENGTH = %X'10'; literal FI5$C_MIN_LENGTH = 120; ! Minimum length of ident area literal FI5$C_MAX_LENGTH = 324; ! Maximum length of ident area literal FI5$S_FI5DEF = 324; ! Old size name - synonym literal FI5$S_FI5 = 324; macro FI5$B_CONTROL = 0,0,8,0 %; ! Control flags and name encoding macro FI5$V_NAMETYPE = 0,0,2,0 %; literal FI5$S_NAMETYPE = 2; ! Encoding of the filename macro FI5$V_FIXED_LENGTH = 0,4,1,0 %; ! If set, ident area may not be contracted ! NOTE - The values of FI5$C_ODS2 et al. must be the same as the corresponding ! values for name encoding in DIRDEF and FIBDEF. All undefined fields ! in FI5$B_CONTROL are REQUIRED to be zero. macro FI5$B_NAMELEN = 1,0,8,0 %; ! Length of name in bytes macro FI5$W_REVISION = 2,0,16,0 %; ! revision number (binary) macro FI5$Q_CREDATE = 4,0,0,0 %; literal FI5$S_CREDATE = 8; ! creation date and time macro FI5$Q_REVDATE = 12,0,0,0 %; literal FI5$S_REVDATE = 8; ! revision date and time macro FI5$Q_EXPDATE = 20,0,0,0 %; literal FI5$S_EXPDATE = 8; ! expiration date and time macro FI5$Q_BAKDATE = 28,0,0,0 %; literal FI5$S_BAKDATE = 8; ! backup date and time macro FI5$Q_ACCDATE = 36,0,0,0 %; literal FI5$S_ACCDATE = 8; ! last accessed time macro FI5$Q_ATTDATE = 44,0,0,0 %; literal FI5$S_ATTDATE = 8; ! last attribute modification time macro FI5$Q_EX_RECATTR = 52,0,0,0 %; literal FI5$S_EX_RECATTR = 8; ! extended RMS attributes macro FI5$R_LENGTH_HINT = 60,0,0,0 %; literal FI5$S_LENGTH_HINT = 16; ! File length & record count hint macro FI5$Q_HINT_LO_QW = 60,0,0,0 %; literal FI5$S_HINT_LO_QW = 8; macro FI5$Q_HINT_HI_QW = 68,0,0,0 %; literal FI5$S_HINT_HI_QW = 8; macro FI5$T_FILENAME = 76,0,0,0 %; literal FI5$S_FILENAME = 44; ! file name text macro FI5$T_FILENAMEXT = 120,0,0,0 %; literal FI5$S_FILENAMEXT = 204; ! extension file name area !*** MODULE $FM2DEF *** ! retrieval pointer type codes literal FM2$C_PLACEMENT = 0; ! 00 = placement control data literal FM2$C_FORMAT1 = 1; ! 01 = format 1 literal FM2$C_FORMAT2 = 2; ! 10 = format 2 literal FM2$C_FORMAT3 = 3; ! 11 = format 3 ! format of retrieval pointer literal FM2$K_LENGTH0 = 2; ! length of format 0 (placement) literal FM2$C_LENGTH0 = 2; ! length of format 0 (placement) literal FM2$K_LENGTH1 = 4; ! length of format 1 literal FM2$C_LENGTH1 = 4; ! length of format 1 literal FM2$S_FM2DEF = 4; ! Old size name - synonym literal FM2$S_FM2 = 4; macro FM2$W_WORD0 = 0,0,16,0 %; ! first word, of many uses macro FM2$V_FORMAT = 0,14,2,0 %; literal FM2$S_FORMAT = 2; ! format type code macro FM2$V_EXACT = 0,0,1,0 %; ! exact placement specified macro FM2$V_ONCYL = 0,1,1,0 %; ! on cylinder allocation desired macro FM2$V_LBN = 0,12,1,0 %; ! use LBN of next map pointer macro FM2$V_RVN = 0,13,1,0 %; ! place on specified RVN macro FM2$V_HIGHLBN = 0,8,6,0 %; literal FM2$S_HIGHLBN = 6; ! high order LBN macro FM2$V_COUNT2 = 0,0,14,0 %; literal FM2$S_COUNT2 = 14; ! format 2 & 3 count field macro FM2$B_COUNT1 = 0,0,8,0 %; ! format 1 count field macro FM2$W_LOWLBN = 2,0,16,0 %; ! format 1 low order LBN literal FM2$K_LENGTH2 = 6; ! length of format 2 literal FM2$C_LENGTH2 = 6; ! length of format 2 literal FM2$S_FM2DEF1 = 6; ! Old size name - synonym literal FM2$S_FM2_1 = 6; macro FM2$L_LBN2 = 2,0,32,0 %; ! format 2 LBN (longword) literal FM2$K_LENGTH3 = 8; ! length of format 3 literal FM2$C_LENGTH3 = 8; ! length of format 3 literal FM2$S_FM2DEF2 = 8; ! Old size name - synonym literal FM2$S_FM2_2 = 8; macro FM2$W_LOWCOUNT = 2,0,16,0 %; ! format 3 low order count macro FM2$L_LBN3 = 4,0,32,0 %; ! format 3 LBN (longword) !*** MODULE $FCHDEF *** ! + ! ! File characteristics bit definitions. These are identical to, and must ! track, the bits in FILECHAR above, but are defined relative to the file ! characteristics longword instead of relative to the file header. ! ! - literal FCH$M_VCC_STATE = %X'700'; literal FCH$M_ASSOCIATED = %X'100000'; literal FCH$M_EXISTENCE = %X'200000'; literal FCH$M_WASCONTIG = %X'1'; literal FCH$M_NOBACKUP = %X'2'; literal FCH$M_WRITEBACK = %X'4'; literal FCH$M_READCHECK = %X'8'; literal FCH$M_WRITCHECK = %X'10'; literal FCH$M_CONTIGB = %X'20'; literal FCH$M_LOCKED = %X'40'; literal FCH$M_CONTIG = %X'80'; literal FCH$M_BADACL = %X'800'; literal FCH$M_SPOOL = %X'1000'; literal FCH$M_DIRECTORY = %X'2000'; literal FCH$M_BADBLOCK = %X'4000'; literal FCH$M_MARKDEL = %X'8000'; literal FCH$M_NOCHARGE = %X'10000'; literal FCH$M_ERASE = %X'20000'; literal FCH$M_SHELVED = %X'80000'; literal FCH$M_SCRATCH = %X'100000'; literal FCH$M_NOMOVE = %X'200000'; literal FCH$M_NOSHELVABLE = %X'400000'; literal FCH$M_PRESHELVED = %X'800000'; literal FCH$S_FCHDEF = 4; ! Old size name - synonym literal FCH$S_FCH = 4; macro FCH$V_VCC_STATE = 0,8,3,0 %; literal FCH$S_VCC_STATE = 3; ! VCC state bits ! **********The following line is different from FH2 macro FCH$V_ASSOCIATED = 0,20,1,0 %; ! ISO 9660 Associated file macro FCH$V_EXISTENCE = 0,21,1,0 %; ! ISO 9660 Existence file macro FCH$V_WASCONTIG = 0,0,1,0 %; ! file was (and should be) contiguous macro FCH$V_NOBACKUP = 0,1,1,0 %; ! file is not to be backed up macro FCH$V_WRITEBACK = 0,2,1,0 %; ! file may be write-back cached macro FCH$V_READCHECK = 0,3,1,0 %; ! verify all read operations macro FCH$V_WRITCHECK = 0,4,1,0 %; ! verify all write operations macro FCH$V_CONTIGB = 0,5,1,0 %; ! keep file as contiguous as possible macro FCH$V_LOCKED = 0,6,1,0 %; ! file is deaccess locked macro FCH$V_CONTIG = 0,7,1,0 %; ! file is contiguous macro FCH$V_BADACL = 0,11,1,0 %; ! ACL is invalid macro FCH$V_SPOOL = 0,12,1,0 %; ! intermediate spool file macro FCH$V_DIRECTORY = 0,13,1,0 %; ! file is a directory macro FCH$V_BADBLOCK = 0,14,1,0 %; ! file contains bad blocks macro FCH$V_MARKDEL = 0,15,1,0 %; ! file is marked for delete macro FCH$V_NOCHARGE = 0,16,1,0 %; ! file space is not to be charged macro FCH$V_ERASE = 0,17,1,0 %; ! erase file contents before deletion ! **********The following line is different from FH2 macro FCH$V_SHELVED = 0,19,1,0 %; ! File shelved macro FCH$V_SCRATCH = 0,20,1,0 %; ! Scratch Header used by movefile macro FCH$V_NOMOVE = 0,21,1,0 %; ! Disable movefile on this file macro FCH$V_NOSHELVABLE = 0,22,1,0 %; ! File is not allowed to be shelved macro FCH$V_PRESHELVED = 0,23,1,0 %; ! File is shelved but also kept online ! Note: The high 8 bits of this longword ! are reserved for user and CSS use. !*** MODULE $FJNDEF *** ! + ! ! File journal control bit definitions. These are identical to, and must ! track, the bits in JOURNAL above, but are defined relative to the journal ! control byte instead of relative to the file header. ! ! - literal FJN$M_ONLY_RU = %X'1'; literal FJN$M_RUJNL = %X'2'; literal FJN$M_BIJNL = %X'4'; literal FJN$M_AIJNL = %X'8'; literal FJN$M_ATJNL = %X'10'; literal FJN$M_NEVER_RU = %X'20'; literal FJN$M_JOURNAL_FILE = %X'40'; literal FJN$S_FJNDEF = 1; ! Old size name - synonym literal FJN$S_FJN = 1; macro FJN$V_ONLY_RU = 0,0,1,0 %; ! file is accessible only in recovery unit macro FJN$V_RUJNL = 0,1,1,0 %; ! enable recovery unit journal macro FJN$V_BIJNL = 0,2,1,0 %; ! enable before image journal macro FJN$V_AIJNL = 0,3,1,0 %; ! enable after image journal macro FJN$V_ATJNL = 0,4,1,0 %; ! enable audit trail journal macro FJN$V_NEVER_RU = 0,5,1,0 %; ! file is never accessible in recovery unit macro FJN$V_JOURNAL_FILE = 0,6,1,0 %; ! this is a journal file !*** MODULE $FATDEF *** ! + ! ! Record attributes area as used by FCS and RMS. ! ! - literal FAT$C_UNDEFINED = 0; ! undefined record type literal FAT$C_FIXED = 1; ! fixed record type literal FAT$C_VARIABLE = 2; ! variable length literal FAT$C_VFC = 3; ! variable + fixed control literal FAT$C_STREAM = 4; ! RMS-11 (DEC traditional) stream format literal FAT$C_STREAMLF = 5; ! LF-terminated stream format literal FAT$C_STREAMCR = 6; ! CR-terminated stream format literal FAT$C_SEQUENTIAL = 0; ! sequential organization literal FAT$C_RELATIVE = 1; ! relative organization literal FAT$C_INDEXED = 2; ! indexed organization literal FAT$C_DIRECT = 3; ! direct organization literal FAT$C_SPECIAL = 4; ! Special file organization literal FAT$M_FORTRANCC = %X'1'; literal FAT$M_IMPLIEDCC = %X'2'; literal FAT$M_PRINTCC = %X'4'; literal FAT$M_NOSPAN = %X'8'; literal FAT$M_MSBRCW = %X'10'; literal FAT$C_FIFO = 1; ! FIFO special file literal FAT$C_CHAR_SPECIAL = 2; ! character special file literal FAT$C_BLOCK_SPECIAL = 3; ! block special file literal FAT$C_SYMLINK = 4; ! symbolic link special file for pre-V8.2 literal FAT$C_SYMBOLIC_LINK = 5; ! symbolic link special file for V8.2 and beyond literal FAT$M_GBC_PERCENT = %X'1'; literal FAT$M_GBC_DEFAULT = %X'2'; literal FAT$K_LENGTH = 32; literal FAT$C_LENGTH = 32; literal FAT$S_FATDEF = 32; ! Old size name - synonym literal FAT$S_FAT = 32; macro FAT$B_RTYPE = 0,0,8,0 %; ! record type macro FAT$V_RTYPE = 0,0,4,0 %; literal FAT$S_RTYPE = 4; ! record type subfield macro FAT$V_FILEORG = 0,4,4,0 %; literal FAT$S_FILEORG = 4; ! file organization macro FAT$B_RATTRIB = 1,0,8,0 %; ! record attributes macro FAT$V_FORTRANCC = 1,0,1,0 %; ! Fortran carriage control macro FAT$V_IMPLIEDCC = 1,1,1,0 %; ! implied carriage control macro FAT$V_PRINTCC = 1,2,1,0 %; ! print file carriage control macro FAT$V_NOSPAN = 1,3,1,0 %; ! no spanned records macro FAT$V_MSBRCW = 1,4,1,0 %; ! Format of RCW (0=LSB, 1=MSB) macro FAT$B_SPECIAL_TYPE = 1,0,8,0 %; ! type of special file ! (record attributes are ! meaningless for special files) macro FAT$W_RSIZE = 2,0,16,0 %; ! record size in bytes macro FAT$L_HIBLK = 4,0,32,0 %; ! highest allocated VBN macro FAT$W_HIBLKH = 4,0,16,0 %; ! high order word macro FAT$W_HIBLKL = 6,0,16,0 %; ! low order word macro FAT$L_EFBLK = 8,0,32,0 %; ! end of file VBN macro FAT$W_EFBLKH = 8,0,16,0 %; ! high order word macro FAT$W_EFBLKL = 10,0,16,0 %; ! low order word macro FAT$W_FFBYTE = 12,0,16,0 %; ! first free byte in EFBLK macro FAT$B_BKTSIZE = 14,0,8,0 %; ! bucket size in blocks macro FAT$B_VFCSIZE = 15,0,8,0 %; ! size in bytes of fixed length control for VFC records macro FAT$W_MAXREC = 16,0,16,0 %; ! maximum record size in bytes macro FAT$W_DEFEXT = 18,0,16,0 %; ! default extend quantity macro FAT$W_GBC = 20,0,16,0 %; ! global buffer count (original word) macro FAT$W_GBC16 = 20,0,16,0 %; ! Alias macro FAT$B_RECATTR_FLAGS = 22,0,8,0 %; ! flags for record attribute area macro FAT$V_GBC_PERCENT = 22,0,1,0 %; ! Interpret value in GBC32 as percent instead of count macro FAT$V_GBC_DEFAULT = 22,1,1,0 %; ! RMS should set default for GBC at runtime and ignore ! any values in GBC16 or GBC32 macro FAT$L_GBC32 = 24,0,32,0 %; ! longword implementation of global buffer count macro FAT$W_VERSIONS = 30,0,16,0 %; ! default version limit for directory file !*** MODULE $HM1DEF *** ! + ! ! Home block definitions for Files-11 Structure Level 1 ! ! - literal HM1$C_LEVEL1 = 257; ! 401 octal = structure level 1 literal HM1$C_LEVEL2 = 258; ! 402 octal = structure level 1, version 2 literal HM1$S_HM1DEF = 512; ! Old size name - synonym literal HM1$S_HM1 = 512; macro HM1$W_IBMAPSIZE = 0,0,16,0 %; ! index file bitmap size, blocks macro HM1$L_IBMAPLBN = 2,0,32,0 %; ! index file bitmap starting LBN macro HM1$W_MAXFILES = 6,0,16,0 %; ! maximum ! files on volume macro HM1$W_CLUSTER = 8,0,16,0 %; ! storage bitmap cluster factor macro HM1$W_DEVTYPE = 10,0,16,0 %; ! disk device type macro HM1$W_STRUCLEV = 12,0,16,0 %; ! volume structure level macro HM1$T_VOLNAME = 14,0,0,0 %; literal HM1$S_VOLNAME = 12; ! volume name (ASCII) macro HM1$W_VOLOWNER = 30,0,16,0 %; ! volume owner UIC macro HM1$W_PROTECT = 32,0,16,0 %; ! volume protection macro HM1$V_SYSPRO = 32,0,4,0 %; literal HM1$S_SYSPRO = 4; ! system protection macro HM1$V_OWNPRO = 32,4,4,0 %; literal HM1$S_OWNPRO = 4; ! owner protection macro HM1$V_GROUPPRO = 32,8,4,0 %; literal HM1$S_GROUPPRO = 4; ! group protection macro HM1$V_WORLDPRO = 32,12,4,0 %; literal HM1$S_WORLDPRO = 4; ! world protection macro HM1$W_VOLCHAR = 34,0,16,0 %; ! volume characteristics macro HM1$W_FILEPROT = 36,0,16,0 %; ! default file protection macro HM1$B_WINDOW = 44,0,8,0 %; ! default window size macro HM1$B_EXTEND = 45,0,8,0 %; ! default file extend macro HM1$B_LRU_LIM = 46,0,8,0 %; ! default LRU limit macro HM1$W_CHECKSUM1 = 58,0,16,0 %; ! first checksum macro HM1$T_CREDATE = 60,0,0,0 %; literal HM1$S_CREDATE = 14; ! volume creation date macro HM1$L_SERIALNUM = 456,0,32,0 %; ! pack serial number macro HM1$T_VOLNAME2 = 472,0,0,0 %; literal HM1$S_VOLNAME2 = 12; ! 2nd copy of volume name macro HM1$T_OWNERNAME = 484,0,0,0 %; literal HM1$S_OWNERNAME = 12; ! volume owner name macro HM1$T_FORMAT = 496,0,0,0 %; literal HM1$S_FORMAT = 12; ! volume format type macro HM1$W_CHECKSUM2 = 510,0,16,0 %; ! second checksum !*** MODULE $HM2DEF *** ! + ! ! Home block definitions for Files-11 Structure Level 2 ! ! - literal HM2$C_LEVEL1 = 257; ! 401 octal = structure level 1 literal HM2$C_LEVEL2 = 512; ! 1000 octal = structure level 2 literal HM2$C_LEVEL5 = 1280; ! 2400 octal = structure level 5 literal HM2$C_LEVEL6 = 1536; ! 3000 octal = structure level 6 literal HM2$M_READCHECK = %X'1'; literal HM2$M_WRITCHECK = %X'2'; literal HM2$M_ERASE = %X'4'; literal HM2$M_NOHIGHWATER = %X'8'; literal HM2$M_CLASS_PROT = %X'10'; literal HM2$M_ACCESSTIMES = %X'20'; literal HM2$M_HARDLINKS = %X'40'; literal HM2$M_NO_SPECIAL_FILES = %X'80'; literal HM2$S_HM2DEF = 512; ! Old size name - synonym literal HM2$S_HM2 = 512; macro HM2$L_HOMELBN = 0,0,32,0 %; ! LBN of home (i.e., this) block macro HM2$L_ALHOMELBN = 4,0,32,0 %; ! LBN of alternate home block macro HM2$L_ALTIDXLBN = 8,0,32,0 %; ! LBN of alternate index file header macro HM2$W_STRUCLEV = 12,0,16,0 %; ! volume structure level macro HM2$B_STRUCVER = 12,0,8,0 %; ! structure version number macro HM2$B_STRUCLEV = 13,0,8,0 %; ! main structure level macro HM2$W_CLUSTER = 14,0,16,0 %; ! storage bitmap cluster factor macro HM2$W_HOMEVBN = 16,0,16,0 %; ! VBN of home (i.e., this) block macro HM2$W_ALHOMEVBN = 18,0,16,0 %; ! VBN of alternate home block macro HM2$W_ALTIDXVBN = 20,0,16,0 %; ! VBN of alternate index file header macro HM2$W_IBMAPVBN = 22,0,16,0 %; ! VBN of index file bitmap macro HM2$L_IBMAPLBN = 24,0,32,0 %; ! LBN of index file bitmap macro HM2$L_MAXFILES = 28,0,32,0 %; ! maximum ! files on volume macro HM2$W_IBMAPSIZE = 32,0,16,0 %; ! index file bitmap size, blocks macro HM2$W_RESFILES = 34,0,16,0 %; ! ! reserved files on volume macro HM2$W_DEVTYPE = 36,0,16,0 %; ! disk device type macro HM2$W_RVN = 38,0,16,0 %; ! relative volume number of this volume macro HM2$W_SETCOUNT = 40,0,16,0 %; ! count of volumes in set macro HM2$W_VOLCHAR = 42,0,16,0 %; ! volume characteristics macro HM2$V_READCHECK = 42,0,1,0 %; ! verify all read operations macro HM2$V_WRITCHECK = 42,1,1,0 %; ! verify all write operations macro HM2$V_ERASE = 42,2,1,0 %; ! erase all files on delete macro HM2$V_NOHIGHWATER = 42,3,1,0 %; ! turn off high-water marking macro HM2$V_CLASS_PROT = 42,4,1,0 %; ! enable classification checks on the volume macro HM2$V_ACCESSTIMES = 42,5,1,0 %; ! enable access time macro HM2$V_HARDLINKS = 42,6,1,0 %; ! enable hardlinks macro HM2$V_NO_SPECIAL_FILES = 42,7,1,0 %; ! disable special files macro HM2$L_VOLOWNER = 44,0,32,0 %; ! volume owner UIC macro HM2$L_SEC_MASK = 48,0,32,0 %; ! volume security mask macro HM2$W_PROTECT = 52,0,16,0 %; ! volume protection macro HM2$W_FILEPROT = 54,0,16,0 %; ! default file protection macro HM2$W_RECPROT = 56,0,16,0 %; ! default file record protection macro HM2$W_CHECKSUM1 = 58,0,16,0 %; ! first checksum macro HM2$Q_CREDATE = 60,0,0,0 %; literal HM2$S_CREDATE = 8; ! volume creation date macro HM2$B_WINDOW = 68,0,8,0 %; ! default window size macro HM2$B_LRU_LIM = 69,0,8,0 %; ! default LRU limit macro HM2$W_EXTEND = 70,0,16,0 %; ! default file extend macro HM2$Q_RETAINMIN = 72,0,0,0 %; literal HM2$S_RETAINMIN = 8; ! minimum file retention period macro HM2$Q_RETAINMAX = 80,0,0,0 %; literal HM2$S_RETAINMAX = 8; ! maximum file retention period macro HM2$Q_REVDATE = 88,0,0,0 %; literal HM2$S_REVDATE = 8; ! volume revision date macro HM2$R_MIN_CLASS = 96,0,0,0 %; literal HM2$S_MIN_CLASS = 20; ! volume minimum security class macro HM2$R_MAX_CLASS = 116,0,0,0 %; literal HM2$S_MAX_CLASS = 20; ! volume maximum security class macro HM2$W_FILETAB_FID = 136,0,0,0 %; literal HM2$S_FILETAB_FID = 6; ! file lookup table FID macro HM2$W_LOWSTRUCLEV = 142,0,16,0 %; ! lowest struclev on volume macro HM2$B_LOWSTRUCVER = 142,0,8,0 %; ! structure version number macro HM2$B_LOWSTRUCLEV = 143,0,8,0 %; ! main structure level macro HM2$W_HIGHSTRUCLEV = 144,0,16,0 %; ! highest struclev on volume macro HM2$B_HIGHSTRUCVER = 144,0,8,0 %; ! structure version number macro HM2$B_HIGHSTRUCLEV = 145,0,8,0 %; ! main structure level macro HM2$Q_COPYDATE = 146,0,0,0 %; literal HM2$S_COPYDATE = 8; ! volume copy date macro HM2$Q_ACCESSDELTA = 154,0,0,0 %; literal HM2$S_ACCESSDELTA = 8; ! granularity for access time macro HM2$W_VIBOFFSET = 162,0,16,0 %; ! Offset in bytes to VIB (ODS6 Volume Information Block) macro HM2$W_VIBSIZE = 164,0,16,0 %; ! Size in bytes of VIB macro HM2$L_SERIALNUM = 456,0,32,0 %; ! pack serial number macro HM2$T_STRUCNAME = 460,0,0,0 %; literal HM2$S_STRUCNAME = 12; ! structure (volume set name) macro HM2$T_VOLNAME = 472,0,0,0 %; literal HM2$S_VOLNAME = 12; ! volume name macro HM2$T_OWNERNAME = 484,0,0,0 %; literal HM2$S_OWNERNAME = 12; ! volume owner name macro HM2$T_FORMAT = 496,0,0,0 %; literal HM2$S_FORMAT = 12; ! volume format type macro HM2$W_CHECKSUM2 = 510,0,16,0 %; ! second checksum ! Type of homeblock placement deltas. ! Code assumes these are zero-based and increase monotonically ! literal HM2$C_REQ_DELTA_GEOM_DEPEND = 0; ! dependent on disk geometry literal HM2$C_REQ_DELTA_GEOM_INDEPEND = 1; ! independent of disk geometry literal HM2$C_REQ_DELTA_FIXED_CONTIG = 2; ! fixed so index file will be contig (for Dollar) literal HM2$C_GEOM_INDEPEND_DELTA = 1033; ! actual geometry independent delta ! this is a prime > 1000 literal HM2$C_FIXED_CONTIG_DELTA = 1; ! fixed delta for contiguous index file literal HM2$C_LIMITED_SEARCH_LENGTH = 255; ! number of blocks to check in a limited search !*** MODULE $DIRDEF *** ! + ! ! Directory entry structure for Files-11 Structure Level 2 ! ! - literal DIR$C_FID = 0; ! normal file ID literal DIR$C_LINKNAME = 1; ! symbolic name (obsolete, not used) ! Filename encoding codes. literal DIR$C_ODS2 = 0; ! ODS-2 legal ASCII literal DIR$C_ISL1 = 1; ! ODS-2 illegal ASCII or ISO LATIN-1 literal DIR$$_TYPE_RESERVED = 2; literal DIR$C_UCS2 = 3; ! Unicode USC-2 (16 bit characters) ! NOTE - The values of DIR$C_ODS2 et al. must be the same as the corresponding literal DIR$K_LENGTH = 6; ! length of directory entry overhead literal DIR$C_LENGTH = 6; ! length of directory entry overhead literal DIR$S_NAME = 80; ! maximum length of name string literal DIR$S_ODS5_NAME = 236; ! maximum length of name string (ODS-5) literal DIR$S_DIRDEF = 6; ! Old size name - synonym literal DIR$S_DIR = 6; macro DIR$W_SIZE = 0,0,16,0 %; ! size of directory record in bytes macro DIR$W_VERLIMIT = 2,0,16,0 %; ! maximum number of versions macro DIR$B_FLAGS = 4,0,8,0 %; ! status flags macro DIR$V_TYPE = 4,0,3,0 %; literal DIR$S_TYPE = 3; ! directory entry type macro DIR$V_NAMETYPE = 4,3,3,0 %; literal DIR$S_NAMETYPE = 3; ! Filename encoding type macro DIR$V_SPECIAL = 4,6,1,0 %; ! directory entry points to a special file macro DIR$V_NEXTREC = 4,6,1,0 %; ! another record of same name & type follows macro DIR$V_PREVREC = 4,7,1,0 %; ! another record of same name & type precedes ! directory entry type codes ! values for name encoding in FI5DEF and FIBDEF. macro DIR$B_NAMECOUNT = 5,0,8,0 %; ! byte count of name string macro DIR$T_NAME = 6,0,0,0 %; ! name string ! the version numbers and file ID's follow the ! variable length name area in the form of a ! blockvector. Each entry is as follows: literal DIR$K_VERSION = 8; ! size of each version entry literal DIR$C_VERSION = 8; ! size of each version entry literal DIR$S_DIRDEF1 = 8; ! Old size name - synonym literal DIR$S_DIR1 = 8; macro DIR$W_VERSION = 0,0,16,1 %; ! version number macro DIR$W_FID = 2,0,0,0 %; literal DIR$S_FID = 6; ! file ID macro DIR$W_FID_NUM = 2,0,16,0 %; ! file number macro DIR$W_FID_SEQ = 4,0,16,0 %; ! file sequence number macro DIR$W_FID_RVN = 6,0,16,0 %; ! relative volume number macro DIR$B_FID_RVN = 6,0,8,0 %; ! alternate format RVN macro DIR$B_FID_NMX = 7,0,8,0 %; ! alternate format file number extension literal DIR$S_DIRDEF2 = 1; ! Old size name - synonym literal DIR$S_DIR2 = 1; macro DIR$T_LINKNAME = 0,0,8,0 %; ! symbolic link name (counted string) !*** MODULE $SCBDEF *** ! + ! ! Format of storage control block, Files-11 Structure Level 2 ! ! - literal SCB$C_LEVEL2 = 512; ! 1000 octal = structure level 2 literal SCB$C_LEVEL5 = 1280; ! 2400 octal = structure level 5 literal SCB$C_LEVEL6 = 1536; ! 3000 octal = structure level 6 literal SCB$M_MAPDIRTY = %X'1'; literal SCB$M_MAPALLOC = %X'2'; literal SCB$M_FILALLOC = %X'4'; literal SCB$M_QUODIRTY = %X'8'; literal SCB$M_HDRWRITE = %X'10'; literal SCB$M_CORRUPT = %X'20'; literal SCB$M_MAPDIRTY2 = %X'1'; literal SCB$M_MAPALLOC2 = %X'2'; literal SCB$M_FILALLOC2 = %X'4'; literal SCB$M_QUODIRTY2 = %X'8'; literal SCB$M_HDRWRITE2 = %X'10'; literal SCB$M_CORRUPT2 = %X'20'; literal SCB$M_NORMAL = %X'1'; literal SCB$M_NEW = %X'2'; literal SCB$M_COPYING = %X'20'; literal SCB$M_MERGING = %X'40'; literal SCB$M_MINIMRG = %X'80'; literal SCB$M_COPY_RESET = %X'100'; literal SCB$M_BOOTING = %X'200'; literal SCB$M_SCB_WLG = %X'400'; literal SCB$M_MUST_MRG = %X'4000'; literal SCB$M_FAILED = %X'8000'; literal SCB$M_CPY_RESET = %X'100'; literal SCB$M_WLG = %X'400'; literal SCB$M_MBR_FCPY = %X'1'; literal SCB$M_MBR_MERGE = %X'2'; literal SCB$M_MBR_CIP = %X'4'; literal SCB$M_MBR_SRC = %X'20'; literal SCB$M_MBR_MFCPY = %X'40'; literal SCB$M_MBR_VALID = %X'80'; literal SCB$M_INIT_NO_ERASE = %X'1'; literal SCB$M_DVE_ENABLED = %X'2'; literal SCB$M_HBVS_MEMBERS_MAY_DIFFER = %X'4'; literal SCB$K_LENGTH = 512; ! Length of Structure literal SCB$C_LENGTH = 512; ! Length of Structure literal SCB$S_SCBDEF = 512; macro SCB$W_STRUCLEV = 0,0,16,0 %; ! file structure level macro SCB$B_STRUCVER = 0,0,8,0 %; ! file structure version macro SCB$B_STRUCLEV = 1,0,8,0 %; ! principal file structure level macro SCB$W_CLUSTER = 2,0,16,0 %; ! storage map cluster factor macro SCB$L_VOLSIZE = 4,0,32,0 %; ! volume size in logical blocks macro SCB$L_BLKSIZE = 8,0,32,0 %; ! number of physical blocks per logical block macro SCB$L_SECTORS = 12,0,32,0 %; ! number of sectors per track macro SCB$L_TRACKS = 16,0,32,0 %; ! number of tracks per cylinder macro SCB$L_CYLINDER = 20,0,32,0 %; ! number of cylinders macro SCB$L_STATUS = 24,0,32,0 %; ! volume status flags macro SCB$V_MAPDIRTY = 24,0,1,0 %; ! storage map is dirty (partially updated) macro SCB$V_MAPALLOC = 24,1,1,0 %; ! storage map is preallocated (lost blocks) macro SCB$V_FILALLOC = 24,2,1,0 %; ! file numbers are preallocated (lost header slots) macro SCB$V_QUODIRTY = 24,3,1,0 %; ! quota file is dirty (partially updated) macro SCB$V_HDRWRITE = 24,4,1,0 %; ! file headers are write back cached macro SCB$V_CORRUPT = 24,5,1,0 %; ! file structure is corrupt macro SCB$L_STATUS2 = 28,0,32,0 %; ! backup status - bits must match those above macro SCB$V_MAPDIRTY2 = 28,0,1,0 %; ! storage map is dirty (partially updated) macro SCB$V_MAPALLOC2 = 28,1,1,0 %; ! storage map is preallocated (lost blocks) macro SCB$V_FILALLOC2 = 28,2,1,0 %; ! file numbers are preallocated (lost header slots) macro SCB$V_QUODIRTY2 = 28,3,1,0 %; ! quota file is dirty (partially updated) macro SCB$V_HDRWRITE2 = 28,4,1,0 %; ! file headers are write back cached macro SCB$V_CORRUPT2 = 28,5,1,0 %; ! file structure is corrupt macro SCB$W_WRITECNT = 32,0,16,0 %; ! count of write access mounters. macro SCB$T_VOLOCKNAME = 34,0,0,0 %; literal SCB$S_VOLOCKNAME = 12; ! name used for file system serialization on volume. macro SCB$Q_MOUNTTIME = 46,0,0,0 %; literal SCB$S_MOUNTTIME = 8; ! time of last initial mount. macro SCB$W_BACKREV = 54,0,16,0 %; ! BACKUP revision number. macro SCB$Q_GENERNUM = 56,0,0,0 %; literal SCB$S_GENERNUM = 8; ! shadow set revision number. macro SCB$Q_UNIT_ID = 64,0,0,0 %; literal SCB$S_UNIT_ID = 8; ! Virtual Unit specifier macro SCB$W_SHADOW_STATUS = 72,0,16,0 %; ! Volume status: macro SCB$W_STATUS = 72,0,16,0 %; ! Duplicate pointer to status macro SCB$V_NORMAL = 72,0,1,0 %; ! Shadow set populated and online macro SCB$V_NEW = 72,1,1,0 %; ! Newly created, no members yet macro SCB$V_COPYING = 72,5,1,0 %; ! Copy State macro SCB$V_MERGING = 72,6,1,0 %; ! Merge State macro SCB$V_MINIMRG = 72,7,1,0 %; ! Mini Merge in progress macro SCB$V_COPY_RESET = 72,8,1,0 %; ! Reset Shadow Server Copy mode macro SCB$V_BOOTING = 72,9,1,0 %; ! System Disk shadow set in booting state macro SCB$V_SCB_WLG = 72,10,1,0 %; ! Write Logging Phase 1 enabled macro SCB$V_MUST_MRG = 72,14,1,0 %; ! This set requires a full merge macro SCB$V_FAILED = 72,15,1,0 %; ! Shadow set not populated macro SCB$V_CPY_RESET = 72,8,1,0 %; ! Copy mode is reset macro SCB$V_WLG = 72,10,1,0 %; ! Write logging macro SCB$B_MEMBER_STATUS = 74,0,8,0 %; ! Member status bytes macro SCB$V_MBR_FCPY = 74,0,1,0 %; ! Member involved in copy macro SCB$V_MBR_MERGE = 74,1,1,0 %; ! Member requires a merge macro SCB$V_MBR_CIP = 74,2,1,0 %; ! Copy (or merge) in progress on this SSM macro SCB$V_MBR_SRC = 74,5,1,0 %; ! Member can be used as a source member macro SCB$V_MBR_MFCPY = 74,6,1,0 %; ! Minimum copy target member macro SCB$V_MBR_VALID = 74,7,1,0 %; ! SSM status information is valid macro SCB$W_SCB_MBZ = 78,0,16,0 %; ! Historically cleared by UPDATE_DISKS macro SCB$Q_MEMBER_IDS = 80,0,0,0 %; literal SCB$S_MEMBER_IDS = 24; ! Unit ID for member macro SCB$L_SCB_LBN = 104,0,32,0 %; ! Unit Control Block for VU macro SCB$B_DEVICES = 108,0,8,0 %; ! Number of devices in SS macro SCB$B_MEMBERS = 109,0,8,0 %; ! Number of source members macro SCB$B_MAST_INDX = 110,0,8,0 %; ! Array index to Master SSM macro SCB$B_MRG_TARGETS = 111,0,8,0 %; ! Active Merge Targets macro SCB$B_FC_TARGETS = 112,0,8,0 %; ! Active Copy Targets macro SCB$B_DECram_MBRS = 113,0,8,0 %; ! Number of DECram devices macro SCB$Q_MBZ_V731_PlaceHolder = 124,0,0,0 %; literal SCB$S_MBZ_V731_PlaceHolder = 8; ! WHL_FILE_START quadword unsigned; was the old name ! N.B. The low longword of this cell MUST remain ! defined to prevent latent (HSG80MM) support ! that shipped in MOUNT96 for V73-1 from making ! the wrong decision macro SCB$Q_HBVS_WRITE_COUNT = 132,0,0,0 %; literal SCB$S_HBVS_WRITE_COUNT = 8; ! Count of systems that have set enabled for write macro SCB$L_VALBLK_OFFSET = 140,0,32,0 %; ! Offset for MOS VALBLK macro SCB$Q_CONSISTENCY_TIMESTAMP = 144,0,0,0 %; literal SCB$S_CONSISTENCY_TIMESTAMP = 8; ! HBVS - SYSTIME value when a multiple member virtual unit ! is considered to be in that state macro SCB$Q_HBMC_ORIGINAL_GN = 152,0,0,0 %; literal SCB$S_HBMC_ORIGINAL_GN = 8; ! Mini Copy initial Generation Number macro SCB$B_XMEMBER_STATUS = 160,0,8,0 %; ! XMBRS Project macro SCB$Q_XMEMBER_IDS = 176,0,0,0 %; literal SCB$S_XMEMBER_IDS = 128; macro SCB$W_SHADOWING_STATUS = 508,0,16,0 %; ! Volume status: macro SCB$V_INIT_NO_ERASE = 508,0,1,0 %; ! Shadow set created without INIT /ERASE macro SCB$V_DVE_ENABLED = 508,1,1,0 %; ! Volume is DVE capable macro SCB$V_HBVS_MEMBERS_MAY_DIFFER = 508,2,1,0 %; ! HBVS virtual unit VOLSIZE has been increased macro SCB$W_CHECKSUM = 510,0,16,0 %; ! block checksum !*** MODULE $BBMDEF *** ! + ! ! Bad block map (generated by bad block scan program) ! ! - literal BBM$K_POINTERS = 4; ! start of retrieval pointers literal BBM$C_POINTERS = 4; ! start of retrieval pointers literal BBM$S_BBMDEF = 512; ! Old size name - synonym /* retrieval pointer format literal BBM$S_BBM = 512; macro BBM$B_COUNTSIZE = 0,0,8,0 %; ! retrieval pointer count field size macro BBM$B_LBNSIZE = 1,0,8,0 %; ! retrieval pointer LBN field size macro BBM$B_INUSE = 2,0,8,0 %; ! number of retrieval words in use macro BBM$B_AVAIL = 3,0,8,0 %; ! number of retrieval words available macro BBM$W_CHECKSUM = 510,0,16,0 %; ! block checksum literal BBM$S_BBMDEF1 = 4; ! Old size name - synonym literal BBM$S_BBM1 = 4; macro BBM$B_HIGHLBN = 0,0,8,0 %; ! high order LBN macro BBM$B_COUNT = 1,0,8,0 %; ! block count macro BBM$W_LOWLBN = 2,0,16,0 %; ! low order LBN literal BBM$S_BBMDEF2 = 5; ! Old size name - synonym literal BBM$S_BBM2 = 5; macro BBM$B_PREVHLBN = -4,0,8,0 %; macro BBM$B_PREVCOUNT = -3,0,8,0 %; macro BBM$W_PREVLLBN = -2,0,16,0 %; ! previous retrieval pointer !*** MODULE $BBDDEF *** ! + ! ! Bad block descriptor (generated by formatters for RK06, RM03, et al) ! ! - literal BBD$K_DESCRIPT = 8; ! start of bad block descriptors literal BBD$C_DESCRIPT = 8; ! start of bad block descriptors literal BBD$S_BBDDEF = 512; ! Old size name - synonym literal BBD$S_BBD = 512; macro BBD$L_SERIAL = 0,0,32,0 %; ! pack serial number macro BBD$W_RESERVED = 4,0,16,0 %; ! reserved area (MBZ) macro BBD$W_FLAGS = 6,0,16,0 %; ! pack status flags (zero for normal use) macro BBD$L_LASTWORD = 508,0,32,0 %; ! last longword of block literal BBD$K_ENTRY = 4; literal BBD$C_ENTRY = 4; literal BBD$S_BBDDEF1 = 4; ! Old size name - synonym literal BBD$S_BBD1 = 4; macro BBD$L_BADBLOCK = 0,0,32,0 %; ! individual bad block entry macro BBD$V_CYLINDER = 0,0,15,0 %; literal BBD$S_CYLINDER = 15; ! cylinder number of bad block macro BBD$V_SECTOR = 0,16,8,0 %; literal BBD$S_SECTOR = 8; ! sector number of bad block macro BBD$V_TRACK = 0,24,7,0 %; literal BBD$S_TRACK = 7; ! track number of bad block !*** MODULE $VSLDEF *** ! + ! ! Structure of a volume set list file entry. Record 1 contains the volume ! set name. Record n+1 contains the volume label of RVN n in the volume set. ! ! - literal VSL$K_LENGTH = 64; literal VSL$C_LENGTH = 64; literal VSL$S_VSLDEF = 64; ! Old size name - synonym literal VSL$S_VSL = 64; macro VSL$T_NAME = 0,0,0,0 %; literal VSL$S_NAME = 12; ! volume name !*** MODULE $PBBDEF *** ! + ! ! Pending bad block file record format. Each record describes a disk block ! on which an error has occurred which has not been turned over to the bad ! block file. ! ! - literal PBB$M_READERR = %X'1'; literal PBB$M_WRITERR = %X'2'; literal PBB$K_LENGTH = 16; ! length of entry literal PBB$C_LENGTH = 16; ! length of entry literal PBB$S_PBBDEF = 16; ! Old size name - synonym literal PBB$S_PBB = 16; macro PBB$W_FID = 0,0,0,0 %; literal PBB$S_FID = 6; ! File ID of containing file macro PBB$B_FLAGS = 6,0,8,0 %; ! status flags macro PBB$V_READERR = 6,0,1,0 %; ! read error occurred macro PBB$V_WRITERR = 6,1,1,0 %; ! write error occurred macro PBB$B_COUNT = 7,0,8,0 %; ! error count macro PBB$L_VBN = 8,0,32,0 %; ! virtual block in file macro PBB$L_LBN = 12,0,32,0 %; ! logical block number !*** MODULE $DQFDEF *** ! + ! ! Structure of disk quota file record. Each record contains the authorization ! and usage of a particular UIC for this volume set. ! ! - literal DQF$M_ACTIVE = %X'1'; literal DQF$K_LENGTH = 32; literal DQF$C_LENGTH = 32; literal DQF$S_DQFDEF = 32; ! Old size name - synonym literal DQF$S_DQF = 32; macro DQF$L_FLAGS = 0,0,32,0 %; ! flags longword, containing... macro DQF$V_ACTIVE = 0,0,1,0 %; ! record contains an active entry macro DQF$L_UIC = 4,0,32,0 %; ! UIC of this record macro DQF$L_USAGE = 8,0,32,0 %; ! number of blocks in use macro DQF$L_PERMQUOTA = 12,0,32,0 %; ! permanent disk quota macro DQF$L_OVERDRAFT = 16,0,32,0 %; ! overdraft limit ! ! ---- < End of module F11DEF.R32 - 30-MAR-2010 16:38:45.52 > - ! ! ! ************************************************************************* ! * * ! * © Copyright 2010, Hewlett-Packard Development Company, L.P. * ! * * ! * Confidential computer software. Valid license from HP and/or * ! * its subsidiaries required for possession, use, or copying. * ! * * ! * Consistent with FAR 12.211 and 12.212, Commercial Computer Software, * ! * Computer Software Documentation, and Technical Data for Commercial * ! * Items are licensed to the U.S. Government under vendor's standard * ! * commercial license. * ! * * ! * Neither HP nor any of its subsidiaries shall be liable for technical * ! * or editorial errors or omissions contained herein. The information * ! * in this document is provided "as is" without warranty of any kind and * ! * is subject to change without notice. The warranties for HP products * ! * are set forth in the express limited warranty statements accompanying * ! * such products. Nothing herein should be construed as constituting an * ! * additional warranty. * ! * * ! ************************************************************************* ! ******************************************************************************************************************************** ! Created: 30-Mar-2010 16:34:41 by OpenVMS SDL EV3-3 ! Source: 08-APR-2008 05:03:11 $1$DGA7374:[LIB.SRC]PDTDEF.SDL;1 ! ******************************************************************************************************************************** !*** MODULE $PDTDEF *** ! + ! DEFINE PORT-INDEPENDENT OFFSETS IN A PORT DESCRIPTOR TABLE. ! ! THERE IS ONE PDT PER PORT ACCESSED VIA SCS. THESE PORTS INCLUDE ! CI'S AND UDA'S. THE PDT CONTAINS A PORT-INDEPENDENT PIECE (DEFINED ! HERE) FOLLOWED BY AN OPTIONAL PORT-SPECIFIC PIECE DEFINED IN THE ! PORT DRIVER. PDT'S ARE CREATED BY THE CONTROLLER INIT ROUTINES ! OF THE INDIVIDUAL PORT DRIVERS. ! - literal PDT$M_SNGLHOST = %X'1'; literal PDT$C_PA = 1; ! CI PORT literal PDT$C_PU = 2; ! UDA PORT literal PDT$C_PE = 3; ! NI PORT literal PDT$C_PS = 4; ! PASSTHRU PORT ! constant PB equals 5 prefix PDT tag $C; /* VAX:BVP storage port literal PDT$C_PI = 6; ! DSSI PORT literal PDT$C_PL = 7; ! Gapless tape port literal PDT$C_PW = 8; ! SWIFT port literal PDT$C_PN = 9; ! NPORT literal PDT$C_PC = 10; ! PCI-NPORT literal PDT$C_PB = 11; ! Galaxy SMCI Port literal PDT$C_PM = 12; ! Memory Channel Port literal PDT$M_CNTBSY = %X'1'; literal PDT$M_CNTRLS = %X'2'; literal PDT$M_XCNTRS = %X'4'; literal PDT$M_NON_CI_BHANDLE = %X'8'; literal PDT$M_AFFINITY = %X'10'; literal PDT$C_BASEVER = 0; ! V4.0 drivers literal PDT$C_LISTENVER = 1; ! V5.0 redesigned listener connection state transitions literal PDT$C_BALANCEVER = 2; ! Dynamic load balancing version literal PDT$C_REORGVER = 1; ! V5.0 reorganized PDT format literal PDT$C_CREDITVER = 2; ! Optimistic credit allocation format literal PDT$C_NI_CLASS = 10; ! NI/SCA performance level port/interconnect literal PDT$C_DSSI_MEDIUM_CLASS = 48; ! DSSI performance level port/interconnect literal PDT$C_CI_CLASS = 140; ! CI performance level port/interconnect literal PDT$C_MC_CLASS = 800; ! MC performance level port/interconnect literal PDT$C_SM_CLASS = 32767; ! Shared Memory performance level port/interconnect ! literal PDT$C_YELLOW = 4; ! Port is in YELLOW zone literal PDT$C_RED = 6; ! Port is in RED zone literal PDT$C_UNEQUAL_PATH = 7; ! Unequal path load sharing (i.e. NI->CI) literal PDT$C_CTRSTART = 636; ! start of pdt counter area a literal PDT$C_STD_CTREND = 668; ! end of standard pdt counter area a literal PDT$C_STDNO_CTR = 7; ! 7 standard counters literal PDT$C_EXT_CTRSTART = 668; ! start of pdt extended counter area a literal PDT$C_EXT_CTREND = 776; ! end of standard pdt counter area a literal PDT$C_EXTNO_CTR = 26; ! 26 extended counters literal SCS$C_EB_MAX_INDEX = 9; literal PDT$K_LENGTH = 1064; ! SIZE OF PORT-INDEPENDENT PIECE literal PDT$C_LENGTH = 1064; ! SIZE OF PORT-INDEPENDENT PIECE ! OF PDT. literal PDT$S_PDTDEF = 1064; ! Old size name - synonym literal PDT$S_PDT = 1064; macro PDT$L_FLINK = 0,0,32,0 %; ! LINK TO NEXT SCS PDT macro PDT$W_PORTCHAR = 4,0,16,0 %; ! Port Characteristics macro PDT$V_SNGLHOST = 4,0,1,0 %; ! Port to single host bus macro PDT$B_PDT_TYPE = 7,0,8,0 %; ! TYPE OF PDT macro PDT$W_SIZE = 8,0,16,0 %; ! STRUCTURE SIZE IN BYTES macro PDT$B_TYPE = 10,0,8,0 %; ! STRUCTURE TYPE = SCS macro PDT$B_SUBTYP = 11,0,8,0 %; ! STRUCTURE SUBTYPE ! ! SCS accesses routines in the port driver via dispatch vectors in the PDT. ! There are two sets of vectors, Required entries (must be supplied by every ! port driver) and Optional entries (allow port drivers that must do so ! to supplant SCS supplied routines). ! ! The required entries are defined below, they must have the prefix ! PDTVEC and tag L for the INIT_PORT_VECTORS macro to work correctly macro PDTVEC$L_ALLOCDG = 12,0,32,1 %; ! ALLOCATE A DG BUFFER macro PDTVEC$L_ALLOCMSG = 16,0,32,1 %; ! ALLOCATE A MESSAGE BUFFER macro PDTVEC$L_DEALLOCDG = 20,0,32,1 %; ! DEALLOCATE DG BUFFER macro PDTVEC$L_DEALLOMSG = 24,0,32,1 %; ! DEALLOCATE MSG BUFFER macro PDTVEC$L_INS_PES_MFREEQ = 28,0,32,1 %; ! return MSG buf to port free buffer supply macro PDTVEC$L_INS_OPT_MFREEQ = 32,0,32,1 %; ! return MSG buf to port free buffer supply (optimistic) macro PDTVEC$L_REM_OPT_MFREEQ = 36,0,32,1 %; ! take MSG buf from port free buffer supply (optimistic) macro PDTVEC$L_REM_PES_MFREEQ = 40,0,32,1 %; ! take MSG buf from port free buffer supply (pessimistic) macro PDTVEC$L_ADD_FREE_DG = 44,0,32,1 %; ! Give Receive DG buffer to port driver macro PDTVEC$L_REM_FREE_DG = 48,0,32,1 %; ! take receive DG buffer to port driver macro PDTVEC$L_QUEUE_DG = 52,0,32,1 %; ! Queue DG buffer to port driver macro PDTVEC$L_REQDATA = 56,0,32,1 %; ! REQUEST BLK DATA XFER macro PDTVEC$L_SENDDATA = 60,0,32,1 %; ! SEND BLK DATA XFER macro PDTVEC$L_SENDDATAWMSG = 64,0,32,1 %; ! send data w/piggyback message macro PDTVEC$L_SENDDG = 68,0,32,1 %; ! SEND A DATAGRAM macro PDTVEC$L_SENDMSG = 72,0,32,1 %; ! SEND A MESSAGE macro PDTVEC$L_SENDMSGL = 76,0,32,1 %; ! SEND A MESSAGE (low priority) macro PDTVEC$L_TRNMSGH = 80,0,32,1 %; ! return message to sender (high priority) macro PDTVEC$L_TRNMSGL = 84,0,32,1 %; ! return message to sender (low priority) macro PDTVEC$L_READCOUNT = 88,0,32,1 %; ! READ COUNTERS (FMT PORT SPECIFIC) macro PDTVEC$L_RLSCOUNT = 92,0,32,1 %; ! RELEASE COUNTERS (FMT PORT SPECIFIC) macro PDTVEC$L_MRESET = 96,0,32,1 %; ! MAINT RESET OF REMOTE macro PDTVEC$L_MSTART = 100,0,32,1 %; ! MAINT START OF REMOTE macro PDTVEC$L_STOP_VCS = 104,0,32,1 %; ! SEND STOP DGS ON ALL VCS macro PDTVEC$L_SHUT_ALL_VC = 108,0,32,1 %; ! Shutdown all VCs on a port macro PDTVEC$L_CRASH_VC = 112,0,32,1 %; ! Crash (Shut off) a single VC macro PDTVEC$L_CRASH_PORT = 116,0,32,1 %; ! Shutdown the port macro PDTVEC$L_REINIT_PORT = 120,0,32,1 %; ! REINIT A PORT macro PDTVEC$L_FLUSH_VC = 124,0,32,1 %; ! complete outstanding requests on a VC macro PDTVEC$L_LOG_ERROR_SCS = 128,0,32,1 %; ! log Packet error for SCS macro PDTVEC$L_CLEANUP_PKT = 132,0,32,1 %; ! return outstanding pakcets to SCS macro PDTVEC$L_PB_FROM_MSG = 136,0,32,1 %; ! return PB for message macro PDTVEC$L_CHK_LOST_ACK = 140,0,32,1 %; ! check if circuit handshake could complete macro PDTVEC$L_REMOVE_PB = 144,0,32,1 %; ! Remove PB if no connections ! Optional port driver entry point vectors (and reserved vectors). ! If these entries are not set by the port driver SCS defaults are used. macro PDT$L_CONNECT = 148,0,32,1 %; ! REQUEST CONNECTION TO REMOTE macro PDT$L_DCONNECT = 152,0,32,1 %; ! BREAK CONNECTION macro PDT$L_ADD_SCS_HDR = 156,0,32,1 %; ! Add SCS session header to a send message macro PDT$L_CANCEL_WAIT = 160,0,32,1 %; ! Cancel a stalled CDRP waiting for a SCS resource. This vector is required ! if port driver stalls for any resource. macro PDT$L_MAP = 164,0,32,1 %; ! Port-dependent Mapping of a Buffer for a Block Transfer macro PDT$L_UNMAP = 168,0,32,1 %; ! Port-dependent Unmapping of a Buffer for a Block Transfer macro PDT$L_FAST_SENDMSG_REQUEST = 172,0,32,1 %; ! Port routine to check if Fast Path can be used to send a message macro PDT$L_FAST_SENDMSG_ASS_RES_PM = 176,0,32,1 %; ! Port routine to associate allocated resources to a Fast Path send message macro PDT$L_FAST_SENDMSG_PM = 180,0,32,1 %; ! Port routine to send a message via Fast Path macro PDT$L_ALLOC_RBUN = 184,0,32,1 %; ! Port routine to create port-specific RBUN resources macro PDT$L_DEALLOC_RBUN = 188,0,32,1 %; ! Port routine to deallocate port-specific RBUN resources macro PDT$L_FAST_RECVMSG_CHK_RES = 192,0,32,1 %; ! Port routine to check port-specific resources to see ! if Fast Path can be used for a received message macro PDT$L_TEST_CRASH_PORT = 196,0,32,1 %; ! Port-dependent Crash Port routine macro PDT$L_TEST_INS_COMQH = 200,0,32,1 %; ! Port-dependent Command Queue Insertion macro PDT$L_TEST_1_PORT = 204,0,32,1 %; ! Port-dependent Test 1 vector macro PDT$L_TEST_2_PORT = 208,0,32,1 %; ! Port-dependent Test 2 vector macro PDT$L_WAITQFL = 240,0,32,1 %; ! LISTHEAD FOR FORK BLOCKS WAITING macro PDT$L_WAITQBL = 244,0,32,1 %; ! FOR NONPAGED POOL macro PDT$L_PM_PORTLOCK = 248,0,32,1 %; ! PM portlock data structure macro PDT$L_RBUN_LIST = 252,0,32,1 %; ! Singly linked list of resource bundles macro PDT$L_RBUN_LENGTH = 256,0,32,0 %; ! Port-specific length of a RBUN macro PDT$L_RBUN_POOLTYPE = 260,0,32,0 %; ! Port-specific pooltype for RBUN ! allocation/deallocation macro PDT$L_NON_FP_SENDMSGS = 264,0,32,0 %; ! Counter of number of non-Fast Path send messages macro PDT$L_NON_FP_RCVDMSGS = 268,0,32,0 %; ! Counter of number of non-Fast Path receive messages ! FILL_10 longword fill prefix PDTDEF tag $$; /* Filler for quadword alignment ! Keep QUADWORD aligned: macro PDT$L_DGHDRSZ = 272,0,32,0 %; ! DATAGRAM HEADER SIZE macro PDT$L_MSGHDRSZ = 272,0,32,0 %; ! MESSAGE HEADER SIZE macro PDT$L_DGOVRHD = 276,0,32,0 %; ! DATAGRAM HEADER SIZE ! ^^^ Obsolete field macro PDT$L_MAXBCNT = 280,0,32,0 %; ! MAXIMUM TRANSFER BCNT macro PDT$W_FLAGS = 284,0,16,0 %; ! PORT FLAGS macro PDT$V_CNTBSY = 284,0,1,0 %; ! COUNTERS IN USE macro PDT$V_CNTRLS = 284,1,1,0 %; ! RELEASE COUNTERS macro PDT$V_XCNTRS = 284,2,1,0 %; ! port supports block xfer counters macro PDT$V_NON_CI_BHANDLE = 284,3,1,0 %; ! Port uses non-CI buffer handles macro PDT$V_AFFINITY = 284,4,1,0 %; ! Set if user has specified affinity for this port macro PDT$T_CNTOWNER = 288,0,0,0 %; literal PDT$S_CNTOWNER = 16; ! NAME OF SYSAP USING COUNTERS macro PDT$L_CNTCDRP = 304,0,32,1 %; ! CDRP OF SYSAP READING COUNTERS macro PDT$L_POLLSWEEP = 308,0,32,0 %; ! # SECONDS TO DO A POLLER SWEEP macro PDT$L_UCB0 = 312,0,32,1 %; ! ADDR OF UCB. macro PDT$L_ADP = 316,0,32,1 %; ! ADDR OF ADP. macro PDT$L_MAX_VCTMO = 320,0,32,0 %; ! Maximum VC timeout macro PDT$W_SCSVERSION = 324,0,16,0 %; ! SCSLOA version macro PDT$W_PPDVERSION = 326,0,16,0 %; ! PPD driver version macro PDT$L_LOAD_VECTOR = 328,0,32,1 %; ! Load vector macro PDT$W_LOAD_CLASS = 332,0,16,0 %; ! Load class (higher arbitrary numbers for higher interconnect performance) ! class = 0 for default lowest performance level ! Interconnect specific load class values (~= Raw HW BW in Mb/S): ! (TYC 15-Feb-89) Dynamic Load Sharing Specific Counters and Fields ! macro PDT$Q_PB = 336,0,0,0 %; literal PDT$S_PB = 8; ! Queue header for path blocks macro PDT$Q_CONN_WAIT = 344,0,0,0 %; literal PDT$S_CONN_WAIT = 8; ! Queue header for CDTs in Load Share Wait Queue macro PDT$Q_YELLOW = 352,0,0,0 %; literal PDT$S_YELLOW = 8; ! Queue header for CDTs in Load Share Yellow Queue macro PDT$Q_RED = 360,0,0,0 %; literal PDT$S_RED = 8; ! Queue header for CDTs in Load Share Red Queue macro PDT$Q_DISABLED = 368,0,0,0 %; literal PDT$S_DISABLED = 8; ! Queue header for CDTs in Load Share Disabled Queue macro PDT$L_PORT_MAP = 376,0,32,0 %; ! 32-bit load sharing domain bit map macro PDT$L_AVAIL_THRUPUT = 380,0,32,1 %; ! Port's available throughput macro PDT$L_LOAD_RATING = 384,0,32,0 %; ! Port load share rating macro PDT$L_TIME_STAMP = 388,0,32,0 %; ! Load sharing port time stamp ! Load share thresholds macro PDT$L_SATURATION_PT = 392,0,32,0 %; ! Port saturation point macro PDT$L_MAX_THRUPUT_THRESHOLD = 396,0,32,0 %; ! Port maximum throughput threshold macro PDT$L_MIN_THRUPUT_THRESHOLD = 400,0,32,0 %; ! Port minimum throughput threshold macro PDT$L_TOLERANCE_THRESHOLD = 404,0,32,0 %; ! Port load tolerance threshold ! Filler for quadword alignment: ! Load sharing data transfer counters macro PDT$L_BYTES_DG_XMT = 408,0,32,0 %; ! Total bytes xmitted by port for DG only macro PDT$L_BYTES_DG_RCV = 412,0,32,0 %; ! Total bytes rcv'd by port for DG only macro PDT$L_BYTES_MSG_XMT = 416,0,32,0 %; ! Total bytes xmitted by port for MSG only macro PDT$L_BYTES_MSG_RCV = 420,0,32,0 %; ! Total bytes rcv'd by port for MSG only macro PDT$L_BYTES_MAPPED = 424,0,32,0 %; ! Total bytes mapped by port for BT only macro PDT$L_DG_XMT = 428,0,32,0 %; ! Total DGs xmitted by port macro PDT$L_DG_RCV = 432,0,32,0 %; ! Total DGs rcv'd by port macro PDT$L_MSG_XMT = 436,0,32,0 %; ! Total MSGs xmitted by port macro PDT$L_MSG_RCV = 440,0,32,0 %; ! Total MSGs rcv'd by port macro PDT$Q_BYTES_XFER = 444,0,0,0 %; literal PDT$S_BYTES_XFER = 8; ! Total bytes xferred by port (both XMIT and RCV) macro PDT$L_NUM_MAP = 452,0,32,0 %; ! (TYC0001) # of map operations completed macro PDT$L_PORT_CMD = 456,0,32,0 %; ! Total # of port commands placed on ! queue when the queue is not empty ! (this is a conditional counter) ! Filler for quadword alignment: macro PDT$L_BYTES_DG_XMT_LAST = 464,0,32,0 %; ! Total bytes xmitted by port for DG only ! up to last load sharing interval macro PDT$L_BYTES_DG_RCV_LAST = 468,0,32,0 %; ! Total bytes rcv'd by port for DG only ! up to last load sharing interval macro PDT$L_BYTES_MSG_XMT_LAST = 472,0,32,0 %; ! Total bytes xmitted by port for MSG only ! up to last load sharing interval macro PDT$L_BYTES_MSG_RCV_LAST = 476,0,32,0 %; ! Total bytes rcv'd by port for MSG only ! up to last load sharing interval macro PDT$L_BYTES_MAPPED_LAST = 480,0,32,0 %; ! Total bytes mapped by port for BT only ! up to last load sharing interval macro PDT$L_DG_XMT_LAST = 484,0,32,0 %; ! Total DGs xmitted by port ! up to last load sharing interval macro PDT$L_DG_RCV_LAST = 488,0,32,0 %; ! Total DGs rcv'd by port ! up to last load sharing interval macro PDT$L_MSG_XMT_LAST = 492,0,32,0 %; ! Total MSGs xmitted by port ! up to last load sharing interval macro PDT$L_MSG_RCV_LAST = 496,0,32,0 %; ! Total MSGs rcv'd by port ! up to last load sharing interval macro PDT$Q_BYTES_XFER_LAST = 500,0,0,0 %; literal PDT$S_BYTES_XFER_LAST = 8; ! Total bytes xferred by port ! up to last load sharing interval macro PDT$L_NUM_MAP_LAST = 508,0,32,0 %; ! (TYC0001) # of map operations completed ! by port up to last load sharing interval macro PDT$L_PORT_CMD_LAST = 512,0,32,0 %; ! Total # of port commands placed on ! queue when the queue is not empty ! up to last load sharing interval ! (this is a conditional counter) macro PDT$L_BYTES_XFER_INT = 520,0,32,0 %; ! (TYC 31-AUG-89) TOTAL BYTES XFERRED ! DURING LAST LOAD SHARING INTERVAL macro PDT$L_EQUAL_PATH_CALL_COUNT = 524,0,32,0 %; ! Number of equal path move requests made ! to connections on this port macro PDT$L_UNEQUAL_PATH_CALL_COUNT = 528,0,32,0 %; ! Number of unequal path move requests made ! to connections on this port macro PDT$L_CONNECTION_MOVE_COUNT = 532,0,32,0 %; ! Number of connection moves from this port ! ! (TYC 27-Feb-89) peak counters used with conditional assembly macro PDT$L_BYTES_DG_XMT_PEAK = 536,0,32,0 %; ! Peak value of total bytes xmitted ! by port for DG only macro PDT$L_BYTES_DG_RCV_PEAK = 540,0,32,0 %; ! Peak value of total bytes rcv'd ! by port for DG only macro PDT$L_BYTES_MSG_XMT_PEAK = 544,0,32,0 %; ! Peak value of total bytes xmitted ! by port for MSG only macro PDT$L_BYTES_MSG_RCV_PEAK = 548,0,32,0 %; ! Peak value of total bytes rcv'd ! by port for MSG only macro PDT$L_BYTES_MAPPED_PEAK = 552,0,32,0 %; ! Peak value of total bytes mapped ! by port for BT only macro PDT$L_DG_XMT_PEAK = 556,0,32,0 %; ! Peak value of total DGs xmitted by port macro PDT$L_DG_RCV_PEAK = 560,0,32,0 %; ! Peak value of total DGs rcv'd by port macro PDT$L_MSG_XMT_PEAK = 564,0,32,0 %; ! Peak value of total MSGs xmitted by port macro PDT$L_MSG_RCV_PEAK = 568,0,32,0 %; ! Peak value of total MSGs rcv'd by port macro PDT$Q_BYTES_XFER_PEAK = 572,0,0,0 %; literal PDT$S_BYTES_XFER_PEAK = 8; ! Peak value of total bytes xferred ! by port (both XMIT and RCV) macro PDT$L_PORT_CMD_PEAK = 580,0,32,0 %; ! Peak value of total # of port commands placed on ! queue when the queue is not empty ! ! (TYC 27-Feb-89) average counters used with conditional assembly macro PDT$L_BYTES_DG_XMT_AVG = 584,0,32,0 %; ! Average value of total bytes xmitted ! by port for DG only macro PDT$L_BYTES_DG_RCV_AVG = 588,0,32,0 %; ! Average value of total bytes rcv'd ! by port for DG only macro PDT$L_BYTES_MSG_XMT_AVG = 592,0,32,0 %; ! Average value of total bytes xmitted ! by port for MSG only macro PDT$L_BYTES_MSG_RCV_AVG = 596,0,32,0 %; ! Average value of total bytes rcv'd ! by port for MSG only macro PDT$L_BYTES_MAPPED_AVG = 600,0,32,0 %; ! Average value of total bytes mapped ! by port for BT only macro PDT$L_DG_XMT_AVG = 604,0,32,0 %; ! Average value of total DGs xmitted by port macro PDT$L_DG_RCV_AVG = 608,0,32,0 %; ! Average value of total DGs rcv'd by port macro PDT$L_MSG_XMT_AVG = 612,0,32,0 %; ! Average value of total MSGs xmitted by port macro PDT$L_MSG_RCV_AVG = 616,0,32,0 %; ! Average value of total MSGs rcv'd by port macro PDT$Q_BYTES_XFER_AVG = 620,0,0,0 %; literal PDT$S_BYTES_XFER_AVG = 8; ! Average value of total bytes xferred ! by port (both XMIT and RCV) macro PDT$L_PORT_CMD_AVG = 628,0,32,0 %; ! Average value of total # of port commands placed on ! queue when the queue is not empty ! (TYC 22-Jun-89) Moved down here to longword-align macro PDT$B_LS_FLAG = 632,0,8,0 %; ! Load share flag, if set, load sharing disabled for now macro PDT$T_FILL_0 = 633,0,24,0 %; literal PDT$S_FILL_0 = 3; ! align long. macro PDT$L_STDNO_CTR = 636,0,32,0 %; ! Total number of standard of counters macro PDT$L_PATH0_ACK = 640,0,32,0 %; ! Total Acks received on path 0. macro PDT$L_PATH0_NAK = 644,0,32,0 %; ! Total Naks received on path 0. macro PDT$L_PATH0_NRSP = 648,0,32,0 %; ! Total NRSPs received on path 0. macro PDT$L_PATH1_ACK = 652,0,32,0 %; ! Total Acks received on path 1. macro PDT$L_PATH1_NAK = 656,0,32,0 %; ! Total Naks received on path 1. macro PDT$L_PATH1_NRSP = 660,0,32,0 %; ! Total NRSPs received on path 1. macro PDT$L_DG_DISC = 664,0,32,0 %; ! Total Datagrams discarded. macro PDT$L_EXTNO_CTR = 668,0,32,0 %; ! Total number of port extended macro PDT$L_SPARE1_CNT = 672,0,32,0 %; ! Spare counter 1. macro PDT$L_SPARE2_CNT = 676,0,32,0 %; ! Spare counter 2. macro PDT$L_SPARE3_CNT = 680,0,32,0 %; ! Spare counter 3. macro PDT$L_SPARE4_CNT = 684,0,32,0 %; ! Spare counter 4. macro PDT$L_SNDDAT_OPER_SNT = 688,0,32,0 %; ! Send Data operations completed. macro PDT$L_SNDDAT_DATA_SNT = 692,0,32,0 %; ! Bytes of SNDDAT sent by Send Data commands. macro PDT$L_SNDDAT_BODIES_SNT = 696,0,32,0 %; ! SNDDAT Data bodies sent from host. macro PDT$L_REQDAT_OPER_SNT = 700,0,32,0 %; ! REQDAT operations completed. macro PDT$L_RETDAT_DATA_RCV = 704,0,32,0 %; ! Bytes of data received by host in RETDAT bodies. macro PDT$L_RETDAT_BODIES_RCV = 708,0,32,0 %; ! RETDAT Data bodies received by host. macro PDT$L_SNTDAT_BODIES_REC = 712,0,32,0 %; ! SNTDAT bodies received and delivered to host. macro PDT$L_SNTDAT_DATA_REC = 716,0,32,0 %; ! Bytes of 'DATA' received in SNTDAT bodies. macro PDT$L_CNF_SNT = 720,0,32,0 %; ! Block Data confirmations sent. macro PDT$L_DATREQ_BODIES_RCV = 724,0,32,0 %; ! DATREQ bodies received. macro PDT$L_RETDAT_BODIES_SNT = 728,0,32,0 %; ! RETDAT Data bodies sent from host. macro PDT$L_RETDAT_DATA_SNT = 732,0,32,0 %; ! Bytes of data sent by RETDAT. macro PDT$L_NP_SNTDAT_BODIES_SNT = 688,0,32,0 %; ! Sent Data bodies sent macro PDT$L_NP_SNTDAT_DATA_SNT = 692,0,32,0 %; ! No. of data bytes via SNDDAT macro PDT$L_NP_CNF_BODIES_RCV = 696,0,32,0 %; ! No. Confirm bodies received macro PDT$L_NP_REQDAT_OPER_CMP = 700,0,32,0 %; ! REQDAT operations completed. macro PDT$L_NP_RETDAT_BODIES_RCV = 704,0,32,0 %; ! RETDAT Data bodies received by host. macro PDT$L_NP_RETDAT_DATA_RCV = 708,0,32,0 %; ! Bytes of data received by host in RETDAT bodies. macro PDT$L_NP_SNTDAT_BODIES_RCV = 712,0,32,0 %; ! SNTDAT bodies received and delivered to host. macro PDT$L_NP_SNTDAT_DATA_RCV = 716,0,32,0 %; ! Bytes of 'DATA' received in SNTDAT bodies. macro PDT$L_NP_CNF_BODIES_SNT = 720,0,32,0 %; ! Block Data confirmations sent. macro PDT$L_NP_REQDAT_BODIES_RCV = 724,0,32,0 %; ! DATREQ bodies received. macro PDT$L_NP_RETDAT_BODIES_SNT = 728,0,32,0 %; ! RETDAT Data bodies sent from host. macro PDT$L_NP_RETDAT_DATA_SNT = 732,0,32,0 %; ! Bytes of data sent by RETDAT. macro PDT$L_DGSNT = 736,0,32,0 %; ! DG bodies sent macro PDT$L_DG_TXT_SNT = 740,0,32,0 %; ! Bytes of DG TEXT Sent macro PDT$L_MSG_SNT = 744,0,32,0 %; ! MSG bodies sent macro PDT$L_MSG_TXT_SNT = 748,0,32,0 %; ! Bytes of MSG TEXT Sent macro PDT$L_MISC_SNT = 752,0,32,0 %; ! All other opcode bodies sent macro PDT$L_DG_REC = 756,0,32,0 %; ! DG bodies received and delivered to host. macro PDT$L_DG_TXTREC = 760,0,32,0 %; ! Bytes of dg received and delivered to host. macro PDT$L_MSG_REC = 764,0,32,0 %; ! MSG bodies received. macro PDT$L_MSG_TXT_REC = 768,0,32,0 %; ! Bytes of msg text received and delivered to host. macro PDT$L_MISC_REC = 772,0,32,0 %; ! All other bodies received. macro PDT$L_SNDDAT_DATA_SNT_LAST = 776,0,32,0 %; ! Bytes of SNDDAT sent by Send ! Data commands up to last load ! sharing interval macro PDT$L_SNDDAT_OPER_SNT_LAST = 780,0,32,0 %; ! # of Send Data operations from host ! up to last load sharing interval macro PDT$L_RETDAT_DATA_RCV_LAST = 784,0,32,0 %; ! Bytes of data received by host in ! RETDAT bodies up to last load ! sharing interval macro PDT$L_REQDAT_OPER_SNT_LAST = 788,0,32,0 %; ! # of REQDAT operations completed by ! host up to last load share interval macro PDT$L_CNF_SNT_LAST = 792,0,32,0 %; ! # of Block Data confirmations sent ! up to last load share interval macro PDT$L_SNTDAT_DATA_REC_LAST = 796,0,32,0 %; ! Bytes of 'DATA' received in SNTDAT bodies ! up to last load sharing interval macro PDT$L_DATREQ_BODIES_RCV_LAST = 800,0,32,0 %; ! # of DATREQ bodies received ! up to last load sharing interval macro PDT$L_RETDAT_DATA_SNT_LAST = 804,0,32,0 %; ! Bytes of data sent by RETDAT up to ! last load sharing interval macro PDT$L_AVG_XFER_SIZE = 808,0,32,0 %; ! Average transfer size used in ! calculating port's effective bandwidth macro PDT$L_EB_TABLE = 812,0,32,0 %; ! address of Ports Effec. Bandwidth table macro PDT$Q_FORMPB = 820,0,0,0 %; literal PDT$S_FORMPB = 8; ! Listhead of formative PB's from this port macro PDT$W_PBCOUNT = 828,0,16,0 %; ! # PB's (non-formative) associated with this PDT macro PDT$B_PORT_NUM = 832,0,8,0 %; ! Local port number macro PDT$T_PORT_NUM = 832,0,0,0 %; literal PDT$S_PORT_NUM = 6; macro PDT$B_MAX_PORT = 838,0,8,0 %; ! Maximum port number macro PDT$T_MAX_PORT = 838,0,0,0 %; literal PDT$S_MAX_PORT = 6; macro PDT$L_CURCNT = 844,0,32,0 %; ! time (secs) till next RDCNT macro PDT$L_POOLDUE = 848,0,32,0 %; ! time when message buffer should be available macro PDT$L_BDLT = 852,0,32,1 %; ! addr. or port independent portion of ports BDLT ! be quadword aligned: macro PDT$B_SCS_MAINT_BLOCK = 856,0,0,0 %; literal PDT$S_SCS_MAINT_BLOCK = 16; ! Add a Maintenance block to the CDT ! which must be quadword aligned macro PDT$L_TQEADDR = 872,0,32,0 %; ! Address store for VC check TQE macro PDT$L_TIMVCFAIL = 876,0,32,0 %; ! Value for previous value of G^SGN$TIMVCFAIL macro PDT$Q_MGT_HANDLES = 880,0,0,0 %; literal PDT$S_MGT_HANDLES = 8; ! Managed & Managing object handles. macro PDT$L_MGT_HANDLE = 880,0,32,0 %; ! Managed object handle macro PDT$L_MGT_MGR_HANDLE = 884,0,32,0 %; ! Managing object handle macro PDT$L_MGT_PRIORITY = 888,0,32,1 %; ! Management assigned port priority value. macro PDT$L_MGT_REQ = 892,0,32,0 %; ! Count of management requests macro PDT$L_MGT_REQ_BYTES = 896,0,32,0 %; ! Cout of management request bytes macro PDT$L_MGT_ERR = 900,0,32,0 %; ! Mgt error count macro PDT$L_MGT_RSP = 904,0,32,0 %; ! Mgt responses macro PDT$L_MGT_RSP_BYTES = 908,0,32,0 %; ! Bytes of response data macro PDT$L_MGT_CONT = 912,0,32,0 %; ! Continuation flag macro PDT$A_LAST_RSP_HDR = 916,0,32,0 %; ! Address of last management response macro PDT$L_RETURN_FUNC = 920,0,32,0 %; ! Function code returned in a response macro PDT$L_NUM_RET = 924,0,32,0 %; macro PDT$L_RETURN_MAJOR = 928,0,32,0 %; macro PDT$L_RETURN_MINOR = 932,0,32,0 %; macro PDT$L_CONT_TRACE = 936,0,32,0 %; macro PDT$L_CONT_SEQ = 940,0,32,0 %; macro PDT$R_TRACE = 944,0,0,0 %; literal PDT$S_TRACE = 120; ! TRACE CONTEXT literal PDT$C_PAMAC_VER = 2; ! literal PDT$M_PWF_CLNUP = %X'1'; literal PDT$M_PUP = %X'2'; literal PDT$M_LBDG = %X'4'; literal PDT$M_NEW_RSP = %X'8'; literal PDT$M_REQID_SNT = %X'10'; literal PDT$M_INSTR_SNT = %X'20'; literal PDT$M_CLSCKT = %X'40'; literal PDT$M_LOCAL = %X'80'; literal PDT$M_LOOK_ASIDE = %X'100'; literal PDT$C_PQB = 1096; ! Base of PQB literal PDT$Q_COMQBASE = 1096; ! Base of queue headers literal PDT$C_QELOGEND = 1480; literal PDT$C_PAPQBEND = 1608; literal PDT$C_RESP_CNT = 100; literal PDT$C_MFQ_THRESHOLD = -100; literal PDT$C_MFQ_INCREMENT = 30; literal PDT$C_HSHUT_SIZ = 28; ! Shutdown DG itself literal PDT$C_LASTGASP_DG = 1784; literal PDT$C_SETCKT_SIZ = 36; ! SETCKT DG itself literal PDT$M_M = %X'70000000'; literal PDT$C_DEFCNTR = 60; literal PDT$C_ERLCNTR = 86400; literal PDT$C_SPEC_CTRSTART = 2164; literal PDT$C_SPECNO_CTR = 14; literal PDT$C_SPEC_CTREND = 2224; literal PDT$C_SPEC_CTR_LENGTH = 60; literal PDT$C_SCSLENGTH = 2224; literal PDT$C_PAREGBASE = 2224; literal PDT$C_PAREGEND = 2340; literal PDT$C_PALENGTH = 2352; literal PDT$S_PAPDTDEF = 2352; ! Old size name - synonym literal PDT$S_PAPDT = 2352; ! ! Skip the common PDT ! ! ! Define private PA fields ! ! All bits in PDT$L_IPORT_STS and PDT$W_LPORT_STS are uniquely defined ! to test for coding errors! ! macro PDT$V_PWF_CLNUP = 1064,0,1,0 %; ! Power fail cleanup in progress macro PDT$V_PUP = 1064,1,1,0 %; ! Power up has occurred macro PDT$L_IPORT_STS = 1064,0,32,0 %; macro PDT$V_LBDG = 1068,2,1,0 %; ! 0/1 for LB dg's disabled/ ! enabled on this port macro PDT$V_NEW_RSP = 1068,3,1,0 %; ! New Response timeout check ! Cleared every polling ! interval and set when a ! response is dequeued from ! the response queue. macro PDT$V_REQID_SNT = 1068,4,1,0 %; ! Polling activity check -- ! Set when the poller sends ! a REQID to enable the port ! timeout mechanism. macro PDT$V_INSTR_SNT = 1068,5,1,0 %; ! BVP instruction in progress macro PDT$V_CLSCKT = 1068,6,1,0 %; ! PB stalled because a close ! circuit datagram is in use macro PDT$V_LOCAL = 1068,7,1,0 %; ! This is a local (BVP) port ! This bit is used for ! interpretation of the MSTART ! and MRESET functions. macro PDT$V_LOOK_ASIDE = 1068,8,1,0 %; ! This port can allocate message ! packets directly from the ! lookaside list macro PDT$W_LPORT_STS = 1068,0,16,0 %; macro PDT$L_CLSCKT_DG = 1072,0,32,0 %; ! Close circuit datagram ! stored here to guarantee ! circuit shutdown even though ! there is no pool. macro PDT$L_ADAPTER = 1076,0,32,0 %; ! Base of register space -- ! used because the CNF is ! not at the base for the ! BCI750. ! be quadword aligned: ! be quadword aligned: macro PDT$Q_DFREEQ = 1080,0,0,0 %; literal PDT$S_DFREEQ = 8; ! Datagram free queue header macro PDT$L_DFREEQ_FLINK = 1080,0,32,1 %; macro PDT$L_DFREEQ_BLINK = 1084,0,32,1 %; macro PDT$Q_MFREEQ = 1088,0,0,0 %; literal PDT$S_MFREEQ = 8; ! Message free queue header macro PDT$L_MFREEQ_FLINK = 1088,0,32,1 %; macro PDT$L_MFREEQ_BLINK = 1092,0,32,1 %; macro PDT$Q_COMQL = 1096,0,0,0 %; literal PDT$S_COMQL = 8; ! Listhead for command ! queue 0, low priority macro PDT$Q_COMQH = 1104,0,0,0 %; literal PDT$S_COMQH = 8; ! Listhead for command ! queue 1, high priority macro PDT$Q_COMQ2 = 1112,0,0,0 %; literal PDT$S_COMQ2 = 8; ! Listhead for command ! queue 2 macro PDT$Q_COMQ3 = 1120,0,0,0 %; literal PDT$S_COMQ3 = 8; ! Listhead for command ! queue 3 macro PDT$Q_RSPQ = 1128,0,0,0 %; literal PDT$S_RSPQ = 8; ! Listhead for response ! queue macro PDT$L_DFQHDR = 1136,0,32,1 %; ! Addr of DG free queue ! listhead macro PDT$L_MFQHDR = 1140,0,32,1 %; ! Addr of MSG free queue ! listhead macro PDT$W_DQELEN = 1144,0,16,0 %; ! DG free Q entry length macro PDT$W_MQELEN = 1148,0,16,0 %; ! MSG free Q entry length macro PDT$L_VPQB = 1152,0,32,1 %; ! VA of PQB base macro PDT$L_VBDT = 1156,0,32,1 %; ! VA of BDT base macro PDT$W_BDTLEN = 1160,0,16,0 %; ! # of entries in BDT macro PDT$L_SPTBASE = 1164,0,32,1 %; ! PA of base of SPT macro PDT$L_SPTLEN = 1168,0,32,0 %; ! # of entries in SPT macro PDT$L_GPTBASE = 1172,0,32,1 %; ! VA of base of GPT macro PDT$L_GPTLEN = 1176,0,32,0 %; ! # of entries in GPT macro PDT$L_KEEPALIVE = 1180,0,32,0 %; ! Port keepalive interval macro PDT$L_VC_CHECK = 1180,0,32,0 %; ! Virtual circuit checking ! interval macro PDT$L_FUNC_MASK = 1184,0,32,0 %; ! Function mask macro PDT$L_DQELOGOUT = 1352,0,0,0 %; literal PDT$S_DQELOGOUT = 64; ! DGs held by port on ! powerfailure macro PDT$L_MQELOGOUT = 1416,0,0,0 %; literal PDT$S_MQELOGOUT = 64; ! MSGs held by port on ! powerfailure macro PDT$Q_UNINIT_TIMEOUT = 1608,0,0,0 %; literal PDT$S_UNINIT_TIMEOUT = 8; ! Timeout value to use during ! intialization sequeunces macro PDT$Q_CRRR_CACHE_QUE = 1616,0,0,0 %; literal PDT$S_CRRR_CACHE_QUE = 8; ! Carrier queue cache macro PDT$Q_QBUF_CACHE_QUE = 1624,0,0,0 %; literal PDT$S_QBUF_CACHE_QUE = 8; ! QBufqueue cache macro PDT$Q_TYPE1_CACHE_QUE = 1632,0,0,0 %; literal PDT$S_TYPE1_CACHE_QUE = 8; ! Type 1 array queue cache macro PDT$L_INS_COMQL = 1640,0,32,0 %; ! Notify port of non-empty CMDQ0 macro PDT$L_INS_COMQH = 1644,0,32,0 %; ! Notify port of non-empty CMDQ1 macro PDT$L_INS_DFREQ = 1648,0,32,0 %; ! Notify port of non-empty DFQ macro PDT$L_INS_MFREQ = 1652,0,32,0 %; ! Notify port of non-empty MFQ macro PDT$L_TRC_FLAG = 1656,0,32,0 %; ! Control bits for tracing macro PDT$L_TRC_BUF = 1660,0,32,1 %; ! Pointer to allocated trace ! buffer macro PDT$L_TRC_CMDQL = 1664,0,32,1 %; ! Vector for tracing CMDQL macro PDT$L_TRC_CMDQM = 1668,0,32,1 %; ! Vector for tracing CMDQM macro PDT$L_TRC_CMDQH = 1672,0,32,1 %; ! Vector for tracing CMDQH macro PDT$L_TRC_RSP = 1676,0,32,1 %; ! Vector for tracing PROC_RSP macro PDT$L_PROC_RSP = 1680,0,32,1 %; ! Runtime vector for processing ! responses. macro PDT$L_DEBUGCHECK = 1684,0,32,0 %; ! Debugging bugcheck flags macro PDT$L_RESP_CNT = 1688,0,32,0 %; ! Number of responses to be ! removed from the response ! queue before reforking macro PDT$L_MFQ_DEFICIT = 1692,0,32,0 %; ! Dynamic message free queue ! deficit. If negative, one ! message free queue entry has ! been allocated for each SCA ! credit. If positive, then ! represents the number of ! SCA-required credits which ! have not been allocated to ! the message free queue. macro PDT$L_MFQ_THRESHOLD = 1696,0,32,0 %; ! Dynamic message threshold ! increment. This value ! is the change in ! PDT$L_MFQ_THRESHOLD whenever ! a message free queue empty ! interrupt indicates that the ! optimistic credit allocation ! has been too optimistic. macro PDT$L_MFQ_INCREMENT = 1700,0,32,0 %; ! Number to change the threshold ! by. Make this large to ! avoid a cascade of MFQE ! interrupts and a possible ! port timeout during the ! handling of these interrupts macro PDT$L_MFQE_COUNT = 1704,0,32,0 %; ! Count of MFQE interrupts macro PDT$L_DGNETHD = 1708,0,32,0 %; ! Network header size macro PDT$L_DGALLOCSZ = 1712,0,32,0 %; ! Datagram allocation size macro PDT$L_SCS_OFFSET = 1716,0,32,0 %; ! Offset of SCS header macro PDT$L_SPRT_OFFSET = 1720,0,32,0 %; ! Offset into PPD of source port address macro PDT$L_DPRT_OFFSET = 1724,0,32,0 %; ! Offset into PPD of destination port address ! Normally zero except for ports ! which support subnode addressing macro PDT$L_PPD_SUB = 1728,0,32,0 %; ! Extension for subnode addressing ! Zero for nonsubnode type ports ! ! Host shutdown datagram fields -- used by both CI and BVP ports to short- ! circuit cluster and disk timeouts. As part of shutting down a system ! all VCs must be closed with a setckt DG before issuing the last gasp DG. ! This prevents data corruption problems from occurring in a multiple port ! system. The setckt DG and last gasp DG use the same area of memory to ! guarantee they are sent out ! macro PDT$Q_TEMP_RSPQ = 1732,0,0,0 %; literal PDT$S_TEMP_RSPQ = 8; ! Temporary response queue to ! hold responses dequeued ! during send of host ! shutdown datagram macro PDT$B_HSHUT_DG = 1744,0,0,0 %; literal PDT$S_HSHUT_DG = 28; macro PDT$B_SETCKT_DG = 1784,0,0,0 %; literal PDT$S_SETCKT_DG = 36; ! ! Maximum packet multiple which may be used by the local port. This field ! is minimized with the maximum packet multiple supported by the remote port. ! For performance reasons, the actual packet multiple is shifted to bits ! 30:28 to correspond with their positions in the message body. ! macro PDT$V_M = 1820,28,3,0 %; literal PDT$S_M = 3; macro PDT$L_LPORT_MULT = 1820,0,32,0 %; macro PDT$L_VC_CHKDUE = 1864,0,32,0 %; ! Next due time for VC checking macro PDT$L_POLLERDUE = 1868,0,32,0 %; ! Due time for configuration ! poller macro PDT$B_PORTMAP = 1872,0,0,0 %; literal PDT$S_PORTMAP = 32; ! Bitmap of ports ! we've heard from macro PDT$B_PLOGMAP = 1904,0,0,0 %; literal PDT$S_PLOGMAP = 32; ! Bitmap of ports we've logged ! with improper nodename and/or ! SYSID, to whom we won't talk macro PDT$B_DQIMAP = 1936,0,0,0 %; literal PDT$S_DQIMAP = 32; ! Datagram inhibit mask macro PDT$B_FSNMAP = 1968,0,0,0 %; literal PDT$S_FSNMAP = 32; ! Full sequence number mask macro PDT$B_SAMAP = 2000,0,0,0 %; literal PDT$S_SAMAP = 32; ! Subnode addressing mask macro PDT$B_NADPMAP = 2032,0,0,0 %; literal PDT$S_NADPMAP = 32; ! Non Alternating Dual Path mask macro PDT$B_RDPMAP = 2064,0,0,0 %; literal PDT$S_RDPMAP = 32; ! RDP mask macro PDT$L_SETCKTMSK = 2096,0,32,0 %; ! SETCKT bit mask macro PDT$B_NXT_PORT = 2100,0,8,0 %; ! # of next port to poll macro PDT$B_REQIDPS = 2101,0,8,0 %; ! Path select value for ! configuration poller macro PDT$B_P0_LBSTS = 2102,0,8,0 %; ! Status of current macro PDT$B_P1_LBSTS = 2103,0,8,0 %; ! and previous LB DG ! tests for paths 0/1 ! FILL13 word fill; ! Keep QW aligned: macro PDT$L_LBDG = 2104,0,32,1 %; ! Addr of template loopback ! datagram macro PDT$W_STDGDYN = 2108,0,16,0 %; ! # DGs queued for IDREQc ! used in start handshakes and ! finding out about bad paths macro PDT$W_STDGUSED = 2110,0,16,0 %; ! # ports that we know of that ! will be sending IDRECs macro PDT$L_RDCNTDG = 2120,0,32,1 %; ! Address of RDCNT Datagram macro PDT$L_SPARE5 = 2124,0,32,0 %; ! Spare entry macro PDT$L_DEFCNTR = 2128,0,32,0 %; ! Default Counter update rate in seconds macro PDT$L_CURCNTR = 2132,0,32,0 %; ! Current Counter update rate in seconds macro PDT$L_ERLCNTR = 2136,0,32,0 %; ! Errorlog Counter update rate in seconds macro PDT$L_CURERLCNT = 2140,0,32,0 %; ! Current Error log count (how many sec left till report counters to error log) macro PDT$L_CNTUSERS = 2144,0,32,0 %; ! Number of users requesting counters addr macro PDT$Q_LAST_ERR = 2148,0,0,0 %; literal PDT$S_LAST_ERR = 8; ! Time of last port corrected error macro PDT$Q_TIME_RDCNT = 2156,0,0,0 %; literal PDT$S_TIME_RDCNT = 8; ! Time of last RDCNT response returned ! ! CIXCD port-specific counters ! macro PDT$L_SPECNO_CTR = 2164,0,32,0 %; ! Total number of port specific of counters macro PDT$L_PCKT_RCRC = 2168,0,32,0 %; ! Total number of packets received with CRC errors macro PDT$L_PORT_IDLE = 2172,0,32,0 %; ! Amount of time time port is idle (seconds) macro PDT$L_RSPR_WPE = 2176,0,32,0 %; ! Responder Register write PEs macro PDT$L_MBPB_WPE = 2180,0,32,0 %; ! Mover B Packet Buffer PEs macro PDT$L_CMDR_WPE = 2184,0,32,0 %; ! Commander Register write PEs macro PDT$L_INTR_WPE = 2188,0,32,0 %; ! Interrupt Register write PEs macro PDT$L_MAR_WPE = 2192,0,32,0 %; ! Mover A Register write PEs macro PDT$L_MBR_WPE = 2196,0,32,0 %; ! Mover B Register write PEs macro PDT$L_MPB_RPE = 2200,0,32,0 %; ! MCWI Packet Buffer Read PEs macro PDT$L_TBUF_PE = 2204,0,32,0 %; ! Transmit Buffer parity error macro PDT$L_MIB_PE = 2208,0,32,0 %; ! MCDP Internal Bus PEs macro PDT$L_MCWI_PE = 2212,0,32,0 %; ! MCWI PEs macro PDT$L_YREG_PE = 2216,0,32,0 %; ! MCDP YREG PEs macro PDT$L_XREG_PE = 2220,0,32,0 %; ! MCDP XREG PEs macro PDT$L_CNF = 2224,0,32,0 %; ! Configuration register macro PDT$L_PMC = 2228,0,32,0 %; ! Port maintenance/control register macro PDT$L_MADR = 2232,0,32,0 %; ! Port maintenance address register macro PDT$L_MDATR = 2236,0,32,0 %; ! Port maintenance data register macro PDT$L_PS = 2240,0,32,0 %; ! Port status register macro PDT$L_PQBBR = 2244,0,32,0 %; ! Port queue block base register macro PDT$L_CQ0 = 2248,0,32,0 %; ! Command queue 0 control register macro PDT$L_CQ1 = 2252,0,32,0 %; ! Command queue 1 control register macro PDT$L_PSR = 2256,0,32,0 %; ! Port status release register macro PDT$L_PEC = 2260,0,32,0 %; ! Port enable control register macro PDT$L_PIC = 2264,0,32,0 %; ! Port initialize control register macro PDT$L_DFQ = 2268,0,32,0 %; ! DG free queue control register macro PDT$L_MFQ = 2272,0,32,0 %; ! MSG free queue control register macro PDT$L_MTC = 2276,0,32,0 %; ! Maintenance timer control register macro PDT$L_PFAR = 2280,0,32,0 %; ! Port failing address register macro PDT$L_PPR = 2284,0,32,0 %; ! Port parameter register macro PDT$L_PSNR = 2288,0,32,0 %; ! Port serial number register macro PDT$L_FADRL = 2292,0,32,0 %; ! Failing address low register macro PDT$L_FADRH = 2296,0,32,0 %; ! Failing address high register macro PDT$L_PESR = 2300,0,32,0 %; ! Port error status register macro PDT$L_PIDR = 2304,0,32,0 %; ! Port interrupt destination register macro PDT$L_PVR = 2308,0,32,0 %; ! Port vector register macro PDT$L_PEVR = 2312,0,32,0 %; ! Port error vector register macro PDT$L_PRVR = 2316,0,32,0 %; ! Port response vector register macro PDT$L_XCOMM = 2320,0,32,0 %; ! XMI command register macro PDT$L_PDCSR = 2324,0,32,0 %; ! Port diagnostic control register macro PDT$L_PSCR = 2328,0,32,0 %; ! Port scan control register macro PDT$L_PSDR = 2332,0,32,0 %; ! Port scan data register macro PDT$L_PSERNUM = 2336,0,32,0 %; ! Port serial number macro PDT$L_ALTADP = 2340,0,32,1 %; ! The other port's ADP macro PDT$L_ALTPDT = 2344,0,32,1 %; ! The other port's PDT macro PDT$B_PORT1 = 2348,0,8,0 %; ! 1 if port 1, 0 if port 2 literal PDT$M_PI_CQ3 = %X'1'; literal PDT$M_PI_CQ2 = %X'2'; literal PDT$M_PI_CQ1 = %X'4'; literal PDT$M_PI_CQ0 = %X'8'; literal PDT$C_PILENGTH = 2488; literal PDT$S_PIPDTDEF = 2488; ! Old size name - synonym literal PDT$S_PIPDT = 2488; ! ! Skip the common PDT plus the PA extension ! ! ! Define private PI fields ! macro PDT$Q_PI_CMDQ0 = 2352,0,0,0 %; literal PDT$S_PI_CMDQ0 = 8; macro PDT$L_PI_CMDQ0_FLINK = 2352,0,32,1 %; macro PDT$L_PI_CMDQ0_BLINK = 2356,0,32,1 %; macro PDT$Q_PI_CMDQ1 = 2360,0,0,0 %; literal PDT$S_PI_CMDQ1 = 8; macro PDT$L_PI_CMDQ1_FLINK = 2360,0,32,1 %; macro PDT$L_PI_CMDQ1_BLINK = 2364,0,32,1 %; macro PDT$Q_PI_CMDQ2 = 2368,0,0,0 %; literal PDT$S_PI_CMDQ2 = 8; macro PDT$L_PI_CMDQ2_FLINK = 2368,0,32,1 %; macro PDT$L_PI_CMDQ2_BLINK = 2372,0,32,1 %; macro PDT$Q_PI_CMDQ3 = 2376,0,0,0 %; literal PDT$S_PI_CMDQ3 = 8; macro PDT$L_PI_CMDQ3_FLINK = 2376,0,32,1 %; macro PDT$L_PI_CMDQ3_BLINK = 2380,0,32,1 %; macro PDT$Q_PI_RIPQ = 2384,0,0,0 %; literal PDT$S_PI_RIPQ = 8; macro PDT$L_PI_RIPQ_FLINK = 2384,0,32,1 %; macro PDT$L_PI_RIPQ_BLINK = 2388,0,32,1 %; macro PDT$L_PI_SVA = 2392,0,32,1 %; macro PDT$L_PI_PPD = 2396,0,32,0 %; macro PDT$L_PI_INI = 2400,0,32,0 %; macro PDT$L_PI_RANDOM = 2404,0,32,0 %; macro PDT$L_PI_DG_MAX = 2408,0,32,0 %; macro PDT$L_PI_MSG_MAX = 2412,0,32,0 %; macro PDT$L_PI_NR = 2416,0,0,0 %; literal PDT$S_PI_NR = 32; macro PDT$L_PI_NS = 2448,0,0,0 %; literal PDT$S_PI_NS = 32; macro PDT$B_PI_CSTMAP = 2480,0,8,0 %; macro PDT$B_PI_RIPMAP = 2481,0,8,0 %; macro PDT$B_PI_PIPMAP = 2482,0,8,0 %; macro PDT$V_PI_CQ3 = 2483,0,1,0 %; macro PDT$V_PI_CQ2 = 2483,1,1,0 %; macro PDT$V_PI_CQ1 = 2483,2,1,0 %; macro PDT$V_PI_CQ0 = 2483,3,1,0 %; macro PDT$B_PI_WORK = 2483,0,8,0 %; literal PDT$M_CUR_LBS = %X'1'; literal PDT$M_PRV_LBS = %X'2'; literal PDT$M_X_LBS = %X'4'; literal PDT$S_LBSTS = 1; macro PDT$V_CUR_LBS = 0,0,1,0 %; ! Current LB status macro PDT$V_PRV_LBS = 0,1,1,0 %; ! Previous LB status macro PDT$V_X_LBS = 0,2,1,0 %; ! Previous LB crossed status macro PDT$B_LBSTS = 0,0,8,0 %; literal PDT$L_CRCTXWQFL = 2352; ! CRCTX wait queue literal PDT$L_CRCTXWQBL = 2356; ! literal PDT$L_CRCTX_WAITS = 2360; ! count CRCTX waits literal PDT$C_CUNIN = 0; ! Channel in UNINITIALIZED state literal PDT$C_CIC = 1; ! Channel Initialization Completed/DISABLED state literal PDT$C_CEC = 2; ! Channel Enable Completed/ENABLED state literal PDT$M_ONLINE = %X'40000000'; literal PDT$M_CHNL_CLNUP = %X'80000000'; literal PDT$C_TQE_IOTO_TIMEOUT = 100000000; ! 10 sec t/o (100ns) literal PDT$C_TQE_INIT_TIMEOUT = 10000; ! 1 msec t/o (100ns) literal PDT$C_PNLENGTH = 3032; literal PDT$S_PNPDTDEF = 3032; ! Old size name - synonym literal PDT$S_PNPDT = 3032; ! ! Skip the common and PA PDT to define NPORT-specific PDT fields ! ! multiplex one wait queue for either type0 Arrays or CRCTXs ! this is justified because map routines useing two resources are ! mutually exclusive. macro PDT$L_TYP1WAITQFL = 2352,0,32,1 %; ! Listhead for Fork Block waiting for TYP1 Arrays macro PDT$L_TYP1WAITQBL = 2356,0,32,1 %; ! macro PDT$L_FREETYP1 = 2360,0,32,1 %; ! Free Type 1 array list macro PDT$L_DLCK = 2364,0,32,0 %; ! Fork Lock macro PDT$Q_ABLK = 2368,0,0,0 %; literal PDT$S_ABLK = 8; ! Address of adpater block - virtual macro PDT$Q_ABLKP = 2376,0,0,0 %; literal PDT$S_ABLKP = 8; ! Address of adpater block - physical macro PDT$Q_CRRR = 2384,0,0,0 %; literal PDT$S_CRRR = 8; ! Carriers used with channel queue header macro PDT$Q_QBUF = 2392,0,0,0 %; literal PDT$S_QBUF = 8; ! Queue buffers used with channel queue header macro PDT$L_CRRR_CACHEQFL = 2400,0,32,1 %; ! Carriers Cache Queue macro PDT$L_CRRR_CACHEQBL = 2404,0,32,1 %; ! Carriers Cache Queue macro PDT$L_QBUF_CACHEQFL = 2408,0,32,1 %; ! QBuffers Cache Queue macro PDT$L_QBUF_CACHEQBL = 2412,0,32,1 %; ! QBuffers Cache Queue macro PDT$Q_SPARE1 = 2416,0,0,0 %; literal PDT$S_SPARE1 = 8; ! Spare quadword macro PDT$Q_SPARE2 = 2424,0,0,0 %; literal PDT$S_SPARE2 = 8; ! Spare quadword macro PDT$Q_SPARE3 = 2432,0,0,0 %; literal PDT$S_SPARE3 = 8; ! Spare quadword macro PDT$Q_SPARE4 = 2440,0,0,0 %; literal PDT$S_SPARE4 = 8; ! Spare quadword macro PDT$L_RSRVD_FOR_FT_1 = 2440,0,32,0 %; ! Reserved Test 1 macro PDT$L_RSRVD_FOR_FT_2 = 2444,0,32,0 %; ! Reserved Test 2 macro PDT$L_CNTDIS = 2448,0,32,0 %; ! RDCNT dispatch macro PDT$L_HSHUT_QBUF = 2452,0,32,1 %; ! Address of Host Shutdown QBUF macro PDT$L_SETCKT_QBUF = 2456,0,32,1 %; ! Address of SETCKT QBUF macro PDT$L_SPARE_QBUF = 2460,0,32,1 %; ! Address of spare QBUF macro PDT$L_INITIALIZE = 2464,0,32,0 %; ! Initialize adapter macro PDT$L_ENABLE = 2468,0,32,0 %; ! Enable adapter macro PDT$L_INIT_ABLK = 2472,0,32,0 %; ! Init adapter block macro PDT$L_INS_COMQM = 2476,0,32,0 %; ! Notify port of non-empty CMDQ1 macro PDT$L_ABBR = 2480,0,32,1 %; ! adapter block CRAM Address macro PDT$L_CQ2 = 2484,0,32,1 %; ! Command que 2 CRAM Address macro PDT$L_NRE = 2488,0,32,1 %; ! emulation CRAM Address macro PDT$L_QIR = 2492,0,32,1 %; ! QIR CRAM Address macro PDT$L_XBER = 2496,0,32,1 %; ! XBER CRAM Address macro PDT$L_XDEV = 2500,0,32,1 %; ! XDEV CRAM Address macro PDT$L_R_AFAR0 = 2504,0,32,1 %; ! Read CRAM mailbox address - AFAR0 macro PDT$L_R_AFAR1 = 2508,0,32,1 %; ! Read CRAM mailbox address - AFAR1 macro PDT$L_R_AMCSR = 2512,0,32,1 %; ! Read CRAM mailbox address - AMCSR macro PDT$L_R_ASR = 2516,0,32,1 %; ! Read CRAM mailbox address - ASR macro PDT$L_R_CASR = 2520,0,32,1 %; ! Read CRAM mailbox address - CASR macro PDT$L_R_PESR = 2524,0,32,1 %; ! Read CRAM mailbox address - PESR macro PDT$L_R_PFAR = 2528,0,32,1 %; ! Read CRAM mailbox address - PFAR macro PDT$L_R_SPARE = 2532,0,32,1 %; ! Read CRAM mailbox address - SPARE macro PDT$L_R_XBE = 2536,0,32,1 %; ! Read CRAM mailbox address - XBE macro PDT$L_R_XDEV = 2540,0,32,1 %; ! Read CRAM mailbox address - XDEV macro PDT$L_R_XFADR = 2544,0,32,1 %; ! Read CRAM mailbox address - XFADR macro PDT$L_R_XFAER = 2548,0,32,1 %; ! Read CRAM mailbox address - XFAER macro PDT$L_R_XPD1 = 2552,0,32,1 %; ! Read CRAM mailbox address - XPD1 macro PDT$L_W_ABBR = 2556,0,32,1 %; ! Write CRAM mailbox address - ABBR macro PDT$L_W_ACIVR = 2560,0,32,1 %; ! Write CRAM mailbox address - ACIVR macro PDT$L_W_AIDR = 2564,0,32,1 %; ! Write CRAM mailbox address - AIDR macro PDT$L_W_AMCSR = 2568,0,32,1 %; ! Write CRAM mailbox address - AMCSR macro PDT$L_W_AMIVR = 2572,0,32,1 %; ! Write CRAM mailbox address - AMIVR macro PDT$L_W_AMTCR = 2576,0,32,1 %; ! Write CRAM mailbox address - AMTCR macro PDT$L_W_CASRCR = 2580,0,32,1 %; ! Write CRAM mailbox address - CASRCR macro PDT$L_W_COMPIRR = 2584,0,32,1 %; ! Write CRAM mailbox address - COMPIRR macro PDT$L_W_CQ0 = 2588,0,32,1 %; ! Write CRAM mailbox address - CQ0 macro PDT$L_W_CQ1 = 2592,0,32,1 %; ! Write CRAM mailbox address - CQ1 macro PDT$L_W_CQ2 = 2596,0,32,1 %; ! Write CRAM mailbox address - CQ2 macro PDT$L_W_DFQ = 2600,0,32,1 %; ! Write CRAM mailbox address - DFQ macro PDT$L_W_INIT = 2604,0,32,1 %; ! Write CRAM mailbox address - INIT macro PDT$L_W_CICR = 2608,0,32,1 %; ! Write CRAM mailbox address - CICR macro PDT$L_W_CECR = 2612,0,32,1 %; ! Write CRAM mailbox address - CECR macro PDT$L_W_MFQ = 2616,0,32,1 %; ! Write CRAM mailbox address - MFQ macro PDT$L_W_NRE = 2620,0,32,1 %; ! Write CRAM mailbox address - NRE macro PDT$L_W_QIR = 2624,0,32,1 %; ! Write CRAM mailbox address - QIR macro PDT$L_W_XBE = 2628,0,32,1 %; ! Write CRAM mailbox address - XBE macro PDT$L_W_XPD1 = 2632,0,32,1 %; ! Write CRAM mailbox address - XPD1 macro PDT$L_W_XPD2 = 2636,0,32,1 %; ! Write CRAM mailbox address - XPD2 macro PDT$L_R_QCMDF = 2640,0,32,1 %; ! Fwd link of currently outstanding Cmd qbuffs macro PDT$L_R_QCMDB = 2644,0,32,1 %; ! Bkd link of currently outstanding Cmd qbuffs macro PDT$L_R_RSPF = 2648,0,32,1 %; ! Fwd link of response qbuffs to be processed macro PDT$L_R_RSPB = 2652,0,32,1 %; ! Bkd link of response qbuffs to be processed macro PDT$L_R_DAFQF = 2656,0,32,1 %; ! Fwd link of free qbuffs in the Driver-Adapter Free Queue macro PDT$L_R_DAFQB = 2660,0,32,1 %; ! Bkd link of free qbuffs in the Driver-Adapter Free Queue macro PDT$L_R_WCMDFL = 2664,0,32,1 %; ! DSSI command completion wait queue forward link macro PDT$L_R_WCMDBL = 2668,0,32,1 %; ! DSSI command completion wait queue backward link macro PDT$L_R_PCMDFL = 2672,0,32,1 %; ! Port command completion wait queue forward link macro PDT$L_R_PCMDBL = 2676,0,32,1 %; ! Port command completion wait queue backward link macro PDT$L_R_AB = 2680,0,32,1 %; ! Pointer to the shared Adapter Block *already defined, may use this one* macro PDT$L_R_PDT = 2684,0,32,1 %; ! PDT address of the other channel macro PDT$PS_GCQIR = 2688,0,32,1 %; ! Mailbox address of Channel's "greased" command queue insertion register macro PDT$L_CHANSTATE = 2692,0,32,0 %; ! Channel specific state transition code macro PDT$L_R_DCCQ2T = 2696,0,32,1 %; ! Driver-Adapter Command queue 2 tail pointer macro PDT$L_R_DCCQ1T = 2700,0,32,1 %; ! Driver-Adapter Command queue 1 tail pointer macro PDT$L_R_DCCQ0T = 2704,0,32,1 %; ! Driver-Adapter Command queue 0 tail pointer macro PDT$L_R_CNTRS = 2708,0,32,1 %; ! Pointer to the port counter block area ! in the Adapter Block free memory space macro PDT$IL_INITMR = 2712,0,32,0 %; ! Port initialization timeout value macro PDT$IL_ENABTMR = 2716,0,32,0 %; ! Port re-enable timeout value macro PDT$L_R_KPB = 2720,0,32,1 %; ! Adapter-wide Kernel Process Block address macro PDT$IB_BUSRESET_FKBLK = 2728,0,0,1 %; literal PDT$S_BUSRESET_FKBLK = 32; ! Fork block used for getting KPB for BUS RESET macro PDT$L_R_BUSRESET_KPB = 2760,0,32,1 %; ! KPB used for SCSI BUS RESET operation which ! is triggered by the port driver macro PDT$L_R_CHNL_KPB = 2764,0,32,1 %; ! KPB used for cleaning up resources and re-enabling ! a channel macro PDT$IB_CHNL_FKBLK = 2768,0,0,1 %; literal PDT$S_CHNL_FKBLK = 32; ! Fork block used for getting KPB for re-enabling macro PDT$IB_CHNL_INT_FKBLK = 2800,0,0,1 %; literal PDT$S_CHNL_INT_FKBLK = 32; ! Fork block used for channel specific error macro PDT$IL_CHNL_INT_FKLCK = 2832,0,32,0 %; ! CHNL_INT fork block lock field macro PDT$IL_CHANNEL = 2836,0,32,0 %; ! Channel number (0 or 1) of this port macro PDT$L_R_PORT_CRAM = 2840,0,32,1 %; macro PDT$L_STS = 2844,0,32,0 %; ! port device status macro PDT$V_ONLINE = 2844,30,1,0 %; ! ONLINE bit is used when we are cleaning ! up the adapter buffers after powerfail/crash macro PDT$V_CHNL_CLNUP = 2844,31,1,0 %; ! This bit is used when we are cleaning up the ! channel resources after the BUS RESET macro PDT$B_DIPL = 2848,0,8,1 %; literal PDT$S_DIPL = 1; macro PDT$B_TQE_IOTO = 2856,0,0,1 %; literal PDT$S_TQE_IOTO = 64; ! TQE for I/O timeout macro PDT$B_TQE_INIT = 2920,0,0,1 %; literal PDT$S_TQE_INIT = 64; ! TQE for init forks macro PDT$L_KNOWN_NODES = 2984,0,32,0 %; ! Map of known nodes macro PDT$L_PB_MAP = 2988,0,32,0 %; ! Map of nodes to track failed VCs macro PDT$Q_DMA_BASE = 2992,0,0,0 %; literal PDT$S_DMA_BASE = 8; ! DDMA window base BA macro PDT$Q_DDMA_BASE_PA = 3000,0,0,0 %; literal PDT$S_DDMA_BASE_PA = 8; ! PA DDMA window base maps to macro PDT$Q_MONSTER_WIN_BASE = 3008,0,0,0 %; literal PDT$S_MONSTER_WIN_BASE = 8; ! MONSTER_WINDOW base BA macro PDT$Q_DMA_SIZE = 3016,0,0,0 %; literal PDT$S_DMA_SIZE = 8; ! DDMA window size in bytes macro PDT$Q_MEM_SIZE = 3024,0,0,0 %; literal PDT$S_MEM_SIZE = 8; ! system memory size in bytes literal PDT$L_ARG = 3080; ! scratch LW/QW literal PDT$L_CFG_VENDOR_ID = 3120; literal PDT$L_CFG_COMMAND = 3124; literal PDT$L_CFG_REVISION_ID = 3128; literal PDT$L_CFG_CACHE_LINE_SIZE = 3132; literal PDT$R_CIPCA_CTRS = 3384; literal PDT$S_CIPCA_CTRS = 80; literal PDT$C_CIPCA_CTRS_MAX = 20; literal PDT$C_PCLENGTH = 3464; literal PDT$S_PCPDTDEF = 3464; ! Old size name - synonym literal PDT$S_PCPDT = 3464; ! ! Skip the common, PA and PN PDT to define PCI-specific PDT fields ! macro PDT$L_NUMRESETS = 3032,0,32,0 %; ! count resets macro PDT$L_CRAB = 3036,0,32,1 %; ! pointer to PCI CRAB macro PDT$L_DLINK = 3040,0,32,0 %; ! datalink ID info (fr. ABLK) macro PDT$L_RSPQ_SEQUENCE = 3044,0,32,0 %; ! dbg: sequence check rspq macro PDT$L_MAP_WAITS = 3048,0,32,0 %; ! count of map register waits macro PDT$L_CRCTXFQFL = 3056,0,32,1 %; ! Listhead for free CRCTXs macro PDT$L_CRCTXFQBL = 3060,0,32,1 %; ! (dbl-linked-list for dbg) ! multiplex the Typ1 (Typ0 Array) wait queue rather than create 2nd wait Q ! CRCTXWQFL,BL,WAITS defined above (in PN PDT extension) macro PDT$L_CRCTX_RESERVE = 3064,0,32,0 %; ! no. CRCTXs currently in FQ macro PDT$L_CRCTX_RESLIM = 3068,0,32,0 %; ! max length of CRCTXFQ macro PDT$L_CRCTX_COUNT = 3072,0,32,0 %; ! no. currently in use macro PDT$L_CRCTX_HIGH = 3076,0,32,0 %; ! highwater mark for RESERVE ! rpn: assume 8KB pages ! NPPG_OFFSET_MASK longword unsigned ; /* NPort Page offset in Phys pg macro PDT$Q_ARG = 3080,0,0,0 %; literal PDT$S_ARG = 8; ! for CALL ret'd values macro PDT$Q_MISSED_INTS = 3088,0,0,0 %; literal PDT$S_MISSED_INTS = 8; ! count of 'missed' interrupts macro PDT$L_IOHANDLE_BR0 = 3096,0,32,0 %; ! IO Handle for Base Reg 0 macro PDT$L_IOHANDLE_BR1 = 3100,0,32,0 %; ! IO Handle for Base Reg 1 macro PDT$L_IOHANDLE_BR2 = 3104,0,32,0 %; ! IO Handle for Base Reg 2 macro PDT$L_IOHANDLE_BR3 = 3108,0,32,0 %; ! IO Handle for Base Reg 3 macro PDT$L_IOHANDLE_BR4 = 3112,0,32,0 %; ! IO Handle for Base Reg 4 macro PDT$L_IOHANDLE_BR5 = 3116,0,32,0 %; ! IO Handle for Base Reg 5 ! PCI Register Copies for staging register I/O ! Configuration Space Registers (Ref: NPort Spec) macro PDT$W_CFG_VENDOR_ID = 3120,0,16,0 %; macro PDT$W_CFG_DEVICE_ID = 3122,0,16,0 %; macro PDT$W_CFG_COMMAND = 3124,0,16,0 %; macro PDT$W_CFG_STATUS = 3126,0,16,0 %; macro PDT$B_CFG_REVISION_ID = 3128,0,8,0 %; macro PDT$B_CFG_PROGRAMMING_IF = 3129,0,8,0 %; macro PDT$B_CFG_SUB_CLASS = 3130,0,8,0 %; macro PDT$B_CFG_BASE_CLASS = 3131,0,8,0 %; macro PDT$B_CFG_CACHE_LINE_SIZE = 3132,0,8,0 %; macro PDT$B_CFG_LATENCY_TIMER = 3133,0,8,0 %; macro PDT$B_CFG_HEADER_TYPE = 3134,0,8,0 %; macro PDT$B_CFG_BIST = 3135,0,8,0 %; macro PDT$L_CFG_BASE_ADDRESS_0 = 3136,0,32,0 %; macro PDT$L_CFG_BASE_ADDRESS_0H = 3140,0,32,0 %; macro PDT$L_CFG_BASE_ADDRESS_1 = 3144,0,32,0 %; macro PDT$L_CFG_BASE_ADDRESS_1H = 3148,0,32,0 %; macro PDT$L_CFG_BASE_ADDRESS_2 = 3152,0,32,0 %; macro PDT$L_CFG_BASE_ADDRESS_2H = 3156,0,32,0 %; macro PDT$L_CFG_BASE_ADDRESS_3 = 3160,0,32,0 %; macro PDT$L_CFG_BASE_ADDRESS_3H = 3164,0,32,0 %; macro PDT$L_CFG_BASE_ADDRESS_4 = 3168,0,32,0 %; macro PDT$L_CFG_BASE_ADDRESS_4H = 3172,0,32,0 %; macro PDT$L_CFG_BASE_ADDRESS_5 = 3176,0,32,0 %; macro PDT$L_CFG_BASE_ADDRESS_5H = 3180,0,32,0 %; macro PDT$L_MIO_ADPRST = 3184,0,32,0 %; ! Adapter Reset macro PDT$L_MIO_ADPRST2 = 3188,0,32,0 %; ! macro PDT$L_MIO_CLRINTA = 3192,0,32,0 %; ! Clear Interrupt A macro PDT$L_MIO_CLRINTA2 = 3196,0,32,0 %; ! macro PDT$L_MIO_CLRINTB = 3200,0,32,0 %; ! Clear Interrupt B macro PDT$L_MIO_CLRINTB2 = 3204,0,32,0 %; ! macro PDT$L_MIO_AITCR = 3208,0,32,0 %; ! Interrupt Holdoff macro PDT$L_MIO_AITCR2 = 3212,0,32,0 %; ! macro PDT$L_MIO_NODESTS = 3216,0,32,0 %; ! Node Status macro PDT$L_MIO_NODESTS2 = 3220,0,32,0 %; ! macro PDT$L_MIO_INTENA = 3224,0,32,0 %; ! Interrupt Enable macro PDT$L_MIO_INTENA2 = 3228,0,32,0 %; ! macro PDT$Q_MIO_ABBR = 3232,0,0,0 %; literal PDT$S_MIO_ABBR = 8; ! 64 bit Adapter Block Base Register macro PDT$L_MIO_ABBR = 3232,0,32,0 %; ! Adapter Block Base Register macro PDT$L_MIO_ABBR2 = 3236,0,32,0 %; macro PDT$Q_MIO_CCQ2IR = 3240,0,0,0 %; literal PDT$S_MIO_CCQ2IR = 8; ! 64 bit Chan Cmd Q 2 Insertion macro PDT$L_MIO_CCQ2IR = 3240,0,32,0 %; ! Chan Cmd Queue 2 Insertion macro PDT$L_MIO_CCQ2IR2 = 3244,0,32,0 %; ! macro PDT$Q_MIO_CCQ1IR = 3248,0,0,0 %; literal PDT$S_MIO_CCQ1IR = 8; ! 64 bit Chan Cmd Q 1 Insertion macro PDT$L_MIO_CCQ1IR = 3248,0,32,0 %; ! Chan Cmd Queue 1 Insertion macro PDT$L_MIO_CCQ1IR2 = 3252,0,32,0 %; ! macro PDT$Q_MIO_CCQ0IR = 3256,0,0,0 %; literal PDT$S_MIO_CCQ0IR = 8; ! 64 bit Chan Cmd Q 0 Insertion macro PDT$L_MIO_CCQ0IR = 3256,0,32,0 %; ! Chan Cmd Queue 0 Insertion macro PDT$L_MIO_CCQ0IR2 = 3260,0,32,0 %; ! macro PDT$Q_MIO_ADFQIR = 3264,0,0,0 %; literal PDT$S_MIO_ADFQIR = 8; ! 64 bit D.gram Fr. Q Insertion macro PDT$L_MIO_ADFQIR = 3264,0,32,0 %; ! Adap D.gram Fr.Queue Insertion macro PDT$L_MIO_ADFQIR2 = 3268,0,32,0 %; ! macro PDT$Q_MIO_AMFQIR = 3272,0,0,0 %; literal PDT$S_MIO_AMFQIR = 8; ! 64 bit Message Fr. Q Insertion macro PDT$L_MIO_AMFQIR = 3272,0,32,0 %; ! Adap Message Fr.Queue Insertion macro PDT$L_MIO_AMFQIR2 = 3276,0,32,0 %; ! macro PDT$L_MIO_CASR = 3280,0,32,0 %; ! Chan/Adap Status (low LW) macro PDT$L_MIO_CASR2 = 3284,0,32,0 %; ! macro PDT$Q_MIO_CAFAR = 3288,0,0,0 %; literal PDT$S_MIO_CAFAR = 8; ! 64 bit Chan/Adap Failing Address macro PDT$L_MIO_CAFAR = 3288,0,32,0 %; ! Chan/Adap Failing Address macro PDT$L_MIO_CAFAR2 = 3292,0,32,0 %; ! macro PDT$L_MIO_CASRCR = 3296,0,32,0 %; ! Channel/Adapter Status Release Ctrl macro PDT$L_MIO_CASRCR2 = 3300,0,32,0 %; ! macro PDT$L_MIO_CICR = 3304,0,32,0 %; ! Channel Initialize Control macro PDT$L_MIO_CICR2 = 3308,0,32,0 %; ! macro PDT$L_MIO_CECR = 3312,0,32,0 %; ! Channel Enable Control macro PDT$L_MIO_CECR2 = 3316,0,32,0 %; ! macro PDT$L_MIO_AMTCR = 3320,0,32,0 %; ! Adapter Maintenance/Sanity Timer Ctrl macro PDT$L_MIO_AMTCR2 = 3324,0,32,0 %; ! macro PDT$L_MIO_AMTECR = 3328,0,32,0 %; ! Adapter Maintenance/Sanity Timer Expr macro PDT$L_MIO_AMTECR2 = 3332,0,32,0 %; ! macro PDT$L_MIO_AMCSR = 3336,0,32,0 %; ! Adapter Maintenance Control & Status macro PDT$L_MIO_AMCSR2 = 3340,0,32,0 %; ! macro PDT$L_MIO_ACCX = 3344,0,32,0 %; ! Abnormal Condition Code eXtension macro PDT$L_MIO_ACCX2 = 3348,0,32,0 %; ! macro PDT$L_MIO_MREV = 3352,0,32,0 %; ! Microcode Revision macro PDT$L_MIO_MREV2 = 3356,0,32,0 %; ! macro PDT$L_MIO_MUSR = 3360,0,32,0 %; ! Microcode Update Status macro PDT$L_MIO_MUSR2 = 3364,0,32,0 %; ! macro PDT$L_MIO_MUCR = 3368,0,32,0 %; ! Microcode Update Control & Addr macro PDT$L_MIO_MUCR2 = 3372,0,32,0 %; ! macro PDT$L_MIO_ALTINTENA = 3376,0,32,0 %; ! Alternate Interrupt Enable macro PDT$L_MIO_ALTINTENA2 = 3380,0,32,0 %; ! ! CIPCA port-dependent counters macro PDT$L_P0_RXCRC = 3384,0,32,0 %; ! Receive packet CRC error macro PDT$L_P1_RXCRC = 3388,0,32,0 %; ! Receive packet CRC error macro PDT$L_P0_RXDSTMISMATCH = 3392,0,32,0 %; ! DEST matched but DESTC did not macro PDT$L_P1_RXDSTMISMATCH = 3396,0,32,0 %; ! DEST matched but DESTC did not macro PDT$L_P0_RXBUFFULL = 3400,0,32,0 %; ! Fifo went full during receive macro PDT$L_P1_RXBUFFULL = 3404,0,32,0 %; ! Fifo went full during receive macro PDT$L_P0_RXDATTRUNC = 3408,0,32,0 %; ! RX pkt length greater than DMA count macro PDT$L_P1_RXDATTRUNC = 3412,0,32,0 %; ! RX pkt length greater than DMA count macro PDT$L_P0_IDREQNORSP = 3416,0,32,0 %; ! NORSP cnt from IDREQs to closed VC's macro PDT$L_P1_IDREQNORSP = 3420,0,32,0 %; ! NORSP cnt from IDREQs to closed VC's macro PDT$L_P0_TOTAL_RX_PKTS = 3424,0,32,0 %; ! Total Received Packets Path A macro PDT$L_P1_TOTAL_RX_PKTS = 3428,0,32,0 %; ! Total Received Packets Path B macro PDT$L_P0_IMPL_CTR_RSV1 = 3432,0,32,0 %; ! reserved macro PDT$L_P1_IMPL_CTR_RSV1 = 3436,0,32,0 %; ! reserved macro PDT$L_P0_IMPL_CTR_RSV2 = 3440,0,32,0 %; ! reserved macro PDT$L_P1_IMPL_CTR_RSV2 = 3444,0,32,0 %; ! reserved macro PDT$L_P0_IMPL_CTR_RSV3 = 3448,0,32,0 %; ! reserved macro PDT$L_P1_IMPL_CTR_RSV3 = 3452,0,32,0 %; ! reserved macro PDT$L_P0_IMPL_CTR_RSV4 = 3456,0,32,0 %; ! reserved macro PDT$L_P1_IMPL_CTR_RSV4 = 3460,0,32,0 %; ! reserved literal PDT$m_workq_busy = %X'1'; literal PDT$S_PBPDT = 2688; macro PDT$r_fill_pb_10 = 2488,0,0,0 %; literal PDT$s_fill_pb_10 = 8; macro PDT$q_pb_comql = 2488,0,0,0 %; literal PDT$s_pb_comql = 8; macro PDT$r_fill_pb_11 = 2488,0,0,0 %; literal PDT$s_fill_pb_11 = 8; macro PDT$l_pb_comql_flink = 2488,0,32,0 %; macro PDT$l_pb_comql_blink = 2492,0,32,0 %; macro PDT$r_fill_pb_8 = 2496,0,0,0 %; literal PDT$s_fill_pb_8 = 8; macro PDT$q_pb_comqh = 2496,0,0,0 %; literal PDT$s_pb_comqh = 8; macro PDT$r_fill_pb_9 = 2496,0,0,0 %; literal PDT$s_fill_pb_9 = 8; macro PDT$l_pb_comqh_flink = 2496,0,32,0 %; macro PDT$l_pb_comqh_blink = 2500,0,32,0 %; macro PDT$v_pb_comqh = 2504,0,32,0 %; macro PDT$v_pb_comql = 2508,0,32,0 %; macro PDT$v_pb_online = 2512,0,32,0 %; macro PDT$v_pb_stall = 2516,0,32,0 %; macro PDT$l_pb_stall_counter = 2520,0,32,0 %; macro PDT$l_pb_cumulative_stall_ctr = 2524,0,32,0 %; macro PDT$l_pb_was_online = 2528,0,32,0 %; macro PDT$l_pb_blk_data_xfer_size = 2532,0,32,0 %; macro PDT$l_pb_max_msg_size = 2536,0,32,0 %; macro PDT$q_adapter_version = 2540,0,0,0 %; literal PDT$s_adapter_version = 8; macro PDT$l_outbufs = 2548,0,32,1 %; macro PDT$l_crash = 2552,0,32,0 %; macro PDT$l_attempts = 2556,0,32,0 %; macro PDT$l_sendcopy = 2560,0,32,0 %; macro PDT$l_sendnocopy = 2564,0,32,0 %; macro PDT$l_fud = 2568,0,32,0 %; macro PDT$l_fud1 = 2572,0,32,0 %; macro PDT$l_fud2 = 2576,0,32,0 %; macro PDT$l_fud3 = 2580,0,32,0 %; macro PDT$l_ppd_bdxfer_maxlen = 2584,0,32,0 %; ! ppd block data transfer max. len macro PDT$q_pfn_bdxfer_maxlen = 2588,0,0,0 %; literal PDT$s_pfn_bdxfer_maxlen = 8; ! pfn block data transfer max. len. macro PDT$q_bdxfer_maxlen = 2596,0,0,0 %; literal PDT$s_bdxfer_maxlen = 8; ! pfn block data transfer max. len. macro PDT$l_poller_tqe = 2604,0,32,0 %; ! poller tqe ! If you add a bit, please update the bit symbols just bellow macro PDT$v_workq_busy = 2608,0,1,0 %; ! work queue fork block busy bit macro PDT$l_pb_flags = 2608,0,32,0 %; ! flag longword macro PDT$b_wq_fkb = 2612,0,0,0 %; literal PDT$s_wq_fkb = 48; ! work queue fork block macro PDT$l_workq = 2660,0,0,0 %; literal PDT$s_workq = 8; ! local end work queue pointer macro PDT$l_maxpfnpkt = 2668,0,32,0 %; ! max number of pfn packets macro PDT$pq_pktsva = 2672,0,0,1 %; literal PDT$s_pktsva = 8; ! pfn pass buffer macro PDT$pl_pktsva = 2672,0,32,1 %; ! pfn pass buffer macro PDT$pq_pktpte = 2680,0,0,1 %; literal PDT$s_pktpte = 8; ! pfn pte address ! ! PORT Structure ! -------------- ! !*** MODULE $PORTDEF *** literal PORT$C_INIT_LBUF_MAX = 1024; ! Initial large buffer MAX value literal PORT$C_INIT_SBUF_MAX = 2048; ! Initial small buffer MAX value literal PORT$C_INIT_LBUF_QUO = 8; ! Only keep a few, NON-paged pool already maintains lookaside lists. literal PORT$C_INIT_SBUF_QUO = 8; literal PORT$C_SBUF_QUO_INCR = 1; ! The port begins at the end of the SCS area of the PDT (after the emulated registers) literal PDT$C_PEM = 2224; ! Registers Begin here literal PDT$C_PEREGEND = 2280; literal PORT$M_AUTHORIZE = %X'1'; literal PORT$M_NEED_LBUF = %X'4'; literal PORT$M_NEED_SBUF = %X'8'; literal PORT$M_NEED_MFQ = %X'10'; literal PORT$M_NEED_DFQ = %X'20'; literal PORT$M_DISABLED = %X'40'; literal PORT$M_SYNCH = %X'80'; literal PORT$M_MARK_SECOND = %X'100'; literal PORT$M_BIT_9 = %X'200'; literal PORT$M_BIT_10 = %X'400'; literal PORT$M_BIT_11 = %X'800'; literal PORT$M_BIT_12 = %X'1000'; literal PORT$M_BIT_13 = %X'2000'; literal PORT$M_BIT_14 = %X'4000'; literal PORT$M_BIT_15 = %X'8000'; literal PORT$M_FKB_INUSE = %X'2'; literal PORT$C_QUE_NUMBER = 11; ! Number of queue listheads literal PORT$K_FIRST_WRK = 0; literal PORT$M_WRK_RWAITQ = %X'1'; literal PORT$K_FIRST_CYCL_WRK = 1; literal PORT$M_WRK_VCQ = %X'2'; literal PORT$M_WRK_INTR = %X'4'; literal PORT$M_WRK_LDL = %X'8'; literal PORT$M_WRK_TIMER = %X'10'; literal PORT$K_LAST_WRK = 4; literal PORT$C_PORT_COUNTER_SIZE = 52; ! Size in bytes of PORT counter block literal PORT$C_ERRLOG_THRES = 10; ! Rate threshold - maximum errors of each type logged in error interval literal PORT$C_ERR_RATE_INT = 3; ! Interval for rate based error logging literal PORT$M_MAINT_ID = %X'7FFFFFFF'; literal PORT$M_D = %X'80000000'; literal PORT$M_M = %X'100'; literal PORT$M_PS = %X'600'; literal PORT$M_SYS_STATE = %X'FFFFF800'; literal PORT$C_VC_MAX = 256; ! Max number of VC slots in PORT literal PORT$V_HASH = 32; ! Define field for hash function literal PORT$S_HASH = 6; ! - bits 32-38 of the remote SYSID literal PORT$C_LENGTH = 3096; ! Length of PORT$ literal PORT$K_LENGTH = 3096; ! Length of PORT$ ! literal PDT$C_PELENGTH = 4128; literal PDT$K_PELENGTH = 4128; ! Include room needed for VC slots literal PORT$C_PORT_EXTENSION = 1848; literal PORT$S_PORTDEF = 4128; ! ! Pool use control constants. ! ! Default max unacked msgs allowed ! Number of PEM registers ! Space for PEM registers macro PDT$R_PEM = 2224,0,0,0 %; literal PDT$S_PEM = 56; ! Extension amount prior to ! Merging in the PDT. macro PORT$A_PORTQB = 2280,0,32,0 %; ! Pointer to PORT queue block macro PORT$A_INTR_SRV = 2284,0,32,0 %; ! Pointer to Port's interrupt routine macro PORT$W_SIZE = 2288,0,16,0 %; ! Bytes used for PORT macro PORT$B_TYPE = 2290,0,8,0 %; ! Block class macro PORT$B_SUB_TYPE = 2291,0,8,0 %; ! Block type ! PORT Status: macro PORT$W_STS = 2292,0,16,0 %; macro PORT$V_AUTHORIZE = 2292,0,1,0 %; ! Set if node authentication required macro PORT$V_NEED_LBUF = 2292,2,1,0 %; ! Set if large buffer queue is empty macro PORT$V_NEED_SBUF = 2292,3,1,0 %; ! Set if small buffer queue is empty macro PORT$V_NEED_MFQ = 2292,4,1,0 %; ! Set if MFQ queue is empty macro PORT$V_NEED_DFQ = 2292,5,1,0 %; ! Set if DFQ queue is empty macro PORT$V_DISABLED = 2292,6,1,0 %; ! Set if port is disabled macro PORT$V_SYNCH = 2292,7,1,0 %; ! Set if in the middle of a direct call from the driver ! (use to suppress unnecessary interrupts) macro PORT$V_MARK_SECOND = 2292,8,1,0 %; ! Mark the passing of this second macro PORT$V_BIT_9 = 2292,9,1,0 %; ! 9 Not in use macro PORT$V_BIT_10 = 2292,10,1,0 %; ! 10 Not in use macro PORT$V_BIT_11 = 2292,11,1,0 %; ! 11 Not in use macro PORT$V_BIT_12 = 2292,12,1,0 %; ! 12 Not in use macro PORT$V_BIT_13 = 2292,13,1,0 %; ! 13 Not in use macro PORT$V_BIT_14 = 2292,14,1,0 %; ! 14 Not in use macro PORT$V_BIT_15 = 2292,15,1,0 %; ! 15 Not in use ! Interlocked Status: macro PORT$L_INTLK_STS = 2296,0,32,0 %; macro PORT$V_FKB_INUSE = 2296,1,1,0 %; ! Set if PORT fork block is in use ! VC Slot Array State: macro PORT$B_VC_NUM = 2300,0,8,0 %; ! Number of VC slots macro PORT$B_VC_CNT = 2301,0,8,0 %; ! Current count of VC slots used ! Note: W_STS +B_VC_NUM + B_VC_CNT complete an LW, thus LW aligning A_VCVEC0 w/o needing fill: macro PORT$A_VCVEC0 = 2304,0,32,0 %; ! Pointer to VC (0 indexed) slot array macro PORT$B_VC_LAST = 2308,0,8,0 %; ! Last VC slot used ! Embedded Fork block ! macro PORT$R_FORK_QW_FILL = 2309,0,24,1 %; literal PORT$S_FORK_QW_FILL = 3; ! Ensure QW alignment macro PORT$R_FKB = 2312,0,0,0 %; literal PORT$S_FKB = 48; ! Embedded FKB$ macro PORT$Q_FORK = 2312,0,0,1 %; literal PORT$S_FORK = 8; ! Fork Queue linkage macro PORT$W_FKB_SIZE = 2320,0,16,0 %; ! Fork block SIZE field macro PORT$B_FKB_TYPE = 2322,0,8,0 %; ! Fork block TYPE field macro PORT$B_FLCK = 2323,0,8,0 %; ! Fork block index macro PORT$A_FPC = 2324,0,32,0 %; ! Fork PC macro PORT$Q_FR3 = 2328,0,0,0 %; literal PORT$S_FR3 = 8; ! Fork R3 ! LW cells for PRE-V7.3 VAX SDA COMPATIBILITY: macro PORT$L_FR3 = 2328,0,32,0 %; ! Fork R3 macro PORT$L_FR4 = 2332,0,32,0 %; ! Fork R4 macro PORT$Q_FR4 = 2336,0,0,0 %; literal PORT$S_FR4 = 8; ! Fork R4 ! END of embedded fork block ! Port Queues: ! macro PORT$Q_QUE_FIRST = 2360,0,0,1 %; literal PORT$S_QUE_FIRST = 8; ! Start of queue list macro PORT$Q_VC_WORK = 2360,0,0,1 %; literal PORT$S_VC_WORK = 8; ! VC work queue header macro PORT$Q_SBUF_FREE = 2368,0,0,1 %; literal PORT$S_SBUF_FREE = 8; ! Small buffer free queue macro PORT$Q_LBUF_FREE = 2376,0,0,1 %; literal PORT$S_LBUF_FREE = 8; ! Large buffer free queue macro PORT$Q_DFQ = 2384,0,0,1 %; literal PORT$S_DFQ = 8; ! Emergency DFREEQ element macro PORT$Q_MFQ = 2392,0,0,1 %; literal PORT$S_MFQ = 8; ! Emergency MFREEQ element macro PORT$Q_XMT_LDL = 2400,0,0,1 %; literal PORT$S_XMT_LDL = 8; ! "Local-datalink" transmit buffer queue macro PORT$Q_RWAITQ = 2408,0,0,1 %; literal PORT$S_RWAITQ = 8; ! Queue of VCs waiting for a resource macro PORT$Q_DELAYQ = 2416,0,0,1 %; literal PORT$S_DELAYQ = 8; ! Queue of VC's random waiting macro PORT$Q_RSPQ = 2424,0,0,1 %; literal PORT$S_RSPQ = 8; ! PPD response queue (non-interlocked) macro PORT$Q_BUS_LIST = 2432,0,0,1 %; literal PORT$S_BUS_LIST = 8; ! List of BUSses used by this port macro PORT$Q_UDP_RECV_VCRP = 2440,0,0,1 %; literal PORT$S_UDP_RECV_VCRP = 8; ! List of recv VCRPs released macro PORT$L_SECS_ZEROED = 2448,0,32,0 %; ! Seconds since last zeroed macro PORT$L_WRK = 2452,0,32,0 %; ! Bit position of first work bit: macro PORT$V_WRK_RWAITQ = 2452,0,1,0 %; ! Set if PORT$Q_RWAITQ needs processing ! Bit position of first work bit eligible for cyclic servicing: macro PORT$V_WRK_VCQ = 2452,1,1,0 %; ! Set if PORT$Q_VC_WORK is ! non-empty macro PORT$V_WRK_INTR = 2452,2,1,0 %; ! Set if port interrupt needs ! to be sent to the SCS layer macro PORT$V_WRK_LDL = 2452,3,1,0 %; ! Set if buffers on ! local-datalink list macro PORT$V_WRK_TIMER = 2452,4,1,0 %; ! Set to process internal ! clock tick macro PORT$Q_AUTHORIZE = 2456,0,0,1 %; literal PORT$S_AUTHORIZE = 8; ! Key used for node authentication macro PORT$L_SERVICES = 2464,0,32,0 %; ! Requested protocol services mask macro PORT$W_MAX_LNGMSG = 2468,0,16,0 %; ! Max MSG length (including count field) macro PORT$W_MAX_LNGDG = 2470,0,16,0 %; ! Max DG length (including count field) macro PORT$L_ACK_DELAY = 2472,0,32,0 %; ! Ticks allowed for ACK delay macro PORT$T_NODENAME = 2476,0,0,0 %; literal PORT$S_NODENAME = 8; ! Local system node name macro PORT$W_LBUF_SIZE = 2484,0,16,0 %; ! Total size of a large buffer macro PORT$W_SBUF_SIZE = 2486,0,16,0 %; ! Total size of a small buffer ! Large buffer resource utilization quotas & counters: macro PORT$W_LBUF_CNT = 2488,0,16,0 %; ! Count of currently allocated large buffers macro PORT$W_LBUF_QUO = 2490,0,16,0 %; ! Number of large buffers to keep in private pool macro PORT$W_LBUF_MAX = 2492,0,16,0 %; ! Max large buffers allowed to be similtaneously allocated macro PORT$L_TOT_LBUF_ALLOCS = 2496,0,32,0 %; ! Large buffer total "allocation" counter macro PORT$W_LBUF_LOOKASIDE_MISS = 2500,0,16,0 %; ! Large buffer allocations forced to goto pool macro PORT$W_LBUF_INUSE_CNT = 2502,0,16,0 %; ! Count of large buffers not on FREE q macro PORT$W_LBUF_INUSE_PEAK = 2504,0,16,0 %; ! Max large buffers inuse cnt seen macro PORT$W_PCI_LBUF_EMPTY = 2506,0,16,0 %; ! Port Cmd. Inter. - LBUF_FREE was empty ! Small buffer resource utilization quotas & counters: macro PORT$W_SBUF_CNT = 2508,0,16,0 %; ! Count of currently allocated small buffers macro PORT$W_SBUF_QUO = 2510,0,16,0 %; ! Number of small buffers to keep in private pool macro PORT$W_SBUF_MAX = 2512,0,16,0 %; ! Max small buffers allowed to be similtaneously allocated macro PORT$L_TOT_SBUF_ALLOCS = 2516,0,32,0 %; ! Small buffer total "allocation" counter macro PORT$W_SBUF_LOOKASIDE_MISS = 2520,0,16,0 %; ! Small buffer allocations forced to goto pool macro PORT$W_SBUF_INUSE_CNT = 2522,0,16,0 %; ! Count of small buffers not on FREE q macro PORT$W_SBUF_INUSE_PEAK = 2524,0,16,0 %; ! Max small buffers inuse cnt seen macro PORT$W_PCI_SBUF_EMPTY = 2526,0,16,0 %; ! Port Cmd. Inter. - SBUF_FREE was empty macro PORT$W_TR_SBUF_EMPTY = 2528,0,16,0 %; ! Transport - SBUF_FREE was empty ! Size Probe Nonpaged Pool Buffers counters: macro PORT$L_TOT_NPPBUF_ALLOCS = 2532,0,32,0 %; ! Total variable size nonpaged pool buffer ! allocations since port started macro PORT$W_NPPBUF_INUSE_CNT = 2536,0,16,0 %; ! Count of variable size nonpaged pool ! buffers currently owned by port macro PORT$W_NPPBUF_INUSE_PEAK = 2538,0,16,0 %; ! Maximum variable size nonpaged ! pool buffers in use count seen macro PORT$W_BUS_COUNT = 2540,0,16,0 %; ! Count of attached BUSses macro PORT$B_TIM_ERR_LOG = 2542,0,8,0 %; ! Timer for rate based error logging macro PORT$A_LINK = 2544,0,32,0 %; ! PORT linked list linkage macro PORT$B_SCAN_XACK = 2548,0,8,0 %; ! Last bit scanned for sending ACK's macro PORT$B_SCAN_XSEQ = 2549,0,8,0 %; ! Last bit scanned for resending SEQ msg macro PORT$B_SCAN_SBUF = 2550,0,8,0 %; ! Last bit scanned for acquiring small buffer macro PORT$B_NEED_SACK = 2551,0,8,0 %; ! Number of VC's waiting for small buffers macro PORT$L_HALF_TICKLEN = 2552,0,32,0 %; ! Pre-computed 1/2 System clock time tick interval ! Located here because it's close to ! (same cacheline as) MAX_REXMT & both are ! referenced by receive MAINLINE path. macro PORT$L_MAX_REXMT = 2556,0,32,0 %; ! Max consecutive rexmt's macro PORT$B_MAX_REXMT = 2556,0,8,0 %; ! Max consecutive rexmt's ! allowed before giving up & ! closing the VC macro PORT$L_SYSID_LO = 2560,0,32,0 %; ! Low order bits of 48 bit system id macro PORT$W_SYSID_HI = 2564,0,16,0 %; ! High order bits of 48 bit system id macro PORT$W_GROUP = 2566,0,16,0 %; ! Port's group number macro PORT$L_MCAST_LO = 2568,0,32,0 %; ! Low order bits of 48 bit multicast id macro PORT$W_MCAST_HI = 2572,0,16,0 %; ! High order bits of 48 bit multicast id macro PORT$L_MAINT = 2576,0,32,0 %; macro PORT$V_MAINT_ID = 2576,0,31,0 %; literal PORT$S_MAINT_ID = 31; ! Remote port type macro PORT$V_D = 2576,31,1,0 %; ! Set if remote port supports multi-rails macro PORT$B_MINOR = 2580,0,8,0 %; ! Remote NI-SCA protocol minor version # macro PORT$B_MAJOR = 2581,0,8,0 %; ! Remote NI-SCA protocol major version # macro PORT$W_ECO = 2582,0,16,0 %; ! Remote NI-SCA protocol e.c.o. level macro PORT$L_PORT_FCN = 2584,0,32,0 %; ! Remote Port functionality mask macro PORT$L_STA_INFO = 2588,0,32,0 %; macro PORT$V_M = 2588,8,1,0 %; ! Set for remote maintenance states macro PORT$V_PS = 2588,9,2,0 %; literal PORT$S_PS = 2; ! Remote port state macro PORT$V_SYS_STATE = 2588,11,21,0 %; literal PORT$S_SYS_STATE = 21; ! Remote implementation specific system state macro PORT$T_RST_PORT = 2592,0,0,0 %; literal PORT$S_RST_PORT = 6; ! System id of port which caused the last reset of this port ! Max number of VC slots in PORT macro PORT$T_MASK_SBUF = 2600,0,0,0 %; literal PORT$S_MASK_SBUF = 32; ! Bit-mask of VC needing a small buffer for ACK transmission macro PORT$T_MASK_XACK = 2632,0,0,0 %; literal PORT$S_MASK_XACK = 32; ! Bit-mask of VC's with ticking ACK clocks macro PORT$T_MASK_XSEQ = 2664,0,0,0 %; literal PORT$S_MASK_XSEQ = 32; ! Bit-mask of VC needing Sequenced message retransmission macro PORT$AL_VEC0_HASH = 2696,0,0,0 %; literal PORT$S_VEC0_HASH = 256; ! 64 slots for VC hash table -- first entry has index 0 (and lw align) macro PORT$A_PDT = 2952,0,32,0 %; ! Address of PDT macro PORT$A_UCB = 2956,0,32,0 %; ! Address of UCB ! ! Define the work counters and the refork time. ! macro PORT$L_REFORK_TIME = 2960,0,32,0 %; ! Time in ticks at which to re-fork macro PORT$L_CNT_FORK = 2964,0,32,0 %; ! Number of times that a fork was done macro PORT$L_CNT_REFORK = 2968,0,32,0 %; ! Number of times that a re-fork was necessary macro PORT$L_LAST_REFORK = 2972,0,32,0 %; ! Last time in ticks that a re-fork happened ! ! Counters for each type of work. ! macro PORT$L_CNT_SCS_MSGS = 2976,0,32,0 %; ! Number of messages delivered to SCS macro PORT$L_CNT_VCQ = 2980,0,32,0 %; ! Number of VCQ entries processed macro PORT$L_CNT_TQE = 2984,0,32,0 %; ! Number of times TQE was processed macro PORT$L_CNT_TIMER = 2988,0,32,0 %; ! Number of clock ticks requested macro PORT$L_CNT_RWAITQ = 2992,0,32,0 %; ! Number of RWAITQ entries processed macro PORT$L_CNT_LDL = 2996,0,32,0 %; ! Number of buffers processed for the local datalink ! ! Define a pointer for the ROOT. ! macro PORT$A_ROOT = 3000,0,32,0 %; ! Pointer to the ROOT ! ! Add support for the variable clock. ! macro PORT$L_PE4_VALUE = 3004,0,32,0 %; ! Timer control value from PE4 macro PORT$L_CLOCK = 3008,0,32,0 %; ! Decrementing TQE ticks per second counter, underflow = 1 sec. macro PORT$L_TICKS_PER_SECOND = 3012,0,32,0 %; ! Number of TQE ticks per second macro PORT$L_LISTEN_TIMEOUT = 3016,0,32,0 %; ! Number of seconds for a listen timeout macro PORT$L_HELLO_INTERVAL = 3020,0,32,0 %; ! Number of ticks in the HELLO message interval macro PORT$L_HELLO_VARIANCE = 3024,0,32,0 %; ! Maximum number of ticks of variance allowed for the HELLO timer macro PORT$L_CC_CLOCK = 3028,0,32,0 %; ! Decrementing TQE ticks per cc tick counter, underflow = 1 CC tick. ! PORT Trace buffer's address. ! 0 - tracing deselected for this port ! 1 - trace buffer to be allocated ! Address of allocated and selected buffer. macro PORT$A_TRACE_BUFFER = 3032,0,32,0 %; ! Trace buffer adddress ! Trace response continuation context macro PORT$L_CONT_ID = 3036,0,32,0 %; ! Current continuation ID mask ! IPCI Cluster over IP Communications cells: macro PORT$L_IP_INITIALIZED = 3040,0,32,0 %; ! IP Initialziation status macro PORT$A_IP_CONFIG_DATA = 3044,0,32,0 %; ! IP cluster config data macro PORT$PS_KVCIB = 3048,0,32,1 %; ! Global IP KVCI VCIB macro PORT$PS_IPVEC = 3052,0,32,1 %; ! Global IP Vector block macro PORT$Q_IPMREQ_NODE = 3056,0,0,1 %; literal PORT$S_IPMREQ_NODE = 8; ! List of IP interfaces. macro PORT$Q_DEAD_IP_BUS_LIST = 3064,0,0,1 %; literal PORT$S_DEAD_IP_BUS_LIST = 8; ! List of uninitialized IP bus. ! Unix style pool for IPCI Support: macro PORT$PS_POOL_QFL = 3072,0,32,1 %; macro PORT$PS_POOL_QBL = 3076,0,32,1 %; macro PORT$L_POOL_DEALLOC_OPS = 3080,0,32,0 %; macro PORT$L_POOL_ALLOC_OPS = 3084,0,32,0 %; macro PORT$L_POOL_OWNED = 3088,0,32,0 %; ! Fill to QW multiple ! VC Vector Array (appended to PORT$) ! macro PORT$R_VCVEC0 = 3092,0,0,0 %; literal PORT$S_VCVEC0 = 1032; ! Array of VC vectors. macro PORT$L_VCVECTERM = 4124,0,32,1 %; ! end of array marker ! ! ---- < End of module PDTDEF.R32 - 30-MAR-2010 16:38:47.11 > - ! ! ! ************************************************************************* ! * * ! * © Copyright 2010, Hewlett-Packard Development Company, L.P. * ! * * ! * Confidential computer software. Valid license from HP and/or * ! * its subsidiaries required for possession, use, or copying. * ! * * ! * Consistent with FAR 12.211 and 12.212, Commercial Computer Software, * ! * Computer Software Documentation, and Technical Data for Commercial * ! * Items are licensed to the U.S. Government under vendor's standard * ! * commercial license. * ! * * ! * Neither HP nor any of its subsidiaries shall be liable for technical * ! * or editorial errors or omissions contained herein. The information * ! * in this document is provided "as is" without warranty of any kind and * ! * is subject to change without notice. The warranties for HP products * ! * are set forth in the express limited warranty statements accompanying * ! * such products. Nothing herein should be construed as constituting an * ! * additional warranty. * ! * * ! ************************************************************************* ! ******************************************************************************************************************************** ! Created: 30-Mar-2010 16:12:09 by OpenVMS SDL EV3-3 ! Source: 09-JUN-1993 15:42:57 $1$DGA7374:[LIB.SRC]RMSFILSTR.SDL;1 ! ******************************************************************************************************************************** !*** MODULE $PLGDEF *** literal PLG$M_NOEXTEND = %X'1'; literal PLG$C_VER_NO = 1; ! current prolog version number literal PLG$C_VER_IDX = 2; ! new plg for indexed files literal PLG$C_VER_3 = 3; ! new plg for compression, space reclamation (plg 3) literal PLG$K_BLN = 122; literal PLG$C_BLN = 122; literal PLG$S_PLGDEF = 122; ! Old size name - synonym literal PLG$S_PLG = 122; macro PLG$B_DBKTSIZ = 11,0,8,0 %; ! data bucket size macro PLG$B_FLAGS = 16,0,8,0 %; ! flag bits macro PLG$V_NOEXTEND = 16,0,1,0 %; ! no extend allowed (rel) macro PLG$B_AVBN = 102,0,8,0 %; ! vbn of first area descriptor macro PLG$B_AMAX = 103,0,8,0 %; ! maximum number of areas macro PLG$W_DVBN = 104,0,16,0 %; ! first data bucket vbn macro PLG$L_MRN = 108,0,32,0 %; ! maximum record number (rel) macro PLG$L_EOF = 112,0,32,0 %; ! eof vbn (rel) macro PLG$W_VER_NO = 116,0,16,0 %; ! version number macro PLG$W_GBC = 118,0,16,0 %; ! default global buffer count macro PLG$W_COLVBN = 120,0,16,0 %; ! VBN where collate tables begin (if any) !*** MODULE $DLCDEF *** ! ! ! relative file deletion control byte bit definitions ! literal DLC$M_DELETED = %X'4'; literal DLC$M_REC = %X'8'; literal DLC$S_DLCDEF = 1; ! Old size name - synonym literal DLC$S_DLC = 1; macro DLC$R_DLCDEF_BITS = 0,0,8,0 %; macro DLC$V_DELETED = 0,2,1,0 %; ! record deleted macro DLC$V_REC = 0,3,1,0 %; ! record exists (but may have been deleted) !*** MODULE $BKTDEF *** ! ! index bucket definition ! ! this is the bucket format for RMS-11/RMS-32 index files. ! literal BKT$K_OVERHDSZ = 14; ! length of bucket overhead literal BKT$C_OVERHDSZ = 14; ! length of bucket overhead literal BKT$M_LASTBKT = %X'1'; literal BKT$M_ROOTBKT = %X'2'; literal BKT$M_PTR_SZ = %X'18'; literal BKT$C_ENDOVHD = 4; ! end of bucket overhead literal BKT$C_DATBKTOVH = 2; ! end of bucket overhead for data buckets literal BKT$C_DUPBKTOVH = 4; ! additional end of data bucket overhead ! when duplicates are allowed (LCB pointer literal BKT$C_MAXBKTSIZ = 63; ! maximum bucket size literal BKT$S_BKTDEF = 14; ! Old size name - synonym literal BKT$S_BKT = 14; macro BKT$B_CHECKCHAR = 0,0,8,0 %; ! bucket check character macro BKT$R_AREANO_OVERLAY = 1,0,8,0 %; macro BKT$B_AREANO = 1,0,8,0 %; ! area number form which bucket was allocated macro BKT$B_INDEXNO = 1,0,8,0 %; ! index to which this bucket belongs (plg 3) macro BKT$W_ADRSAMPLE = 2,0,16,0 %; ! address sample - low 16 bits of first vbn in bucket macro BKT$R_FREESPACE_OVERLAY = 4,0,16,0 %; macro BKT$W_FREESPACE = 4,0,16,0 %; ! displacement in bucket of first free byte macro BKT$W_KEYFRESPC = 4,0,16,0 %; ! pointer to key's free space (plg 3) macro BKT$R_NXTRECID_OVERLAY = 6,0,16,0 %; macro BKT$W_NXTRECID = 6,0,16,0 %; ! next available word record id (plg 3) macro BKT$R_NXTRECID_FIELDS = 6,0,16,0 %; macro BKT$B_NXTRECID = 6,0,8,0 %; ! next available record id macro BKT$B_LSTRECID = 7,0,8,0 %; ! last id in range macro BKT$L_NXTBKT = 8,0,32,0 %; ! vbn of next bucket macro BKT$B_LEVEL = 12,0,8,0 %; ! bucket level number macro BKT$R_BKTCB_OVERLAY = 13,0,8,0 %; macro BKT$B_BKTCB = 13,0,8,0 %; ! bucket control bits macro BKT$R_BKTCB_BITS = 13,0,8,0 %; macro BKT$V_LASTBKT = 13,0,1,0 %; ! last bucket in horizontal chain macro BKT$V_ROOTBKT = 13,1,1,0 %; ! root bucket macro BKT$V_PTR_SZ = 13,3,2,0 %; literal BKT$S_PTR_SZ = 2; ! size of vbn pointers in this bucket !*** MODULE $IRCDEF *** ! ! index record definition ! ! this is the definition of RMS-11/RMS-32 index file record formats ! literal IRC$M_PTRSZ = %X'3'; literal IRC$M_RECORDCB = %X'FC'; literal IRC$M_DELETED = %X'4'; literal IRC$M_NOPTRSZ = %X'10'; literal IRC$M_FIRST_KEY = %X'80'; literal IRC$M_RRV = %X'8'; literal IRC$M_NODUPCNT = %X'10'; literal IRC$M_RU_DELETE = %X'20'; literal IRC$M_RU_UPDATE = %X'40'; literal IRC$C_IDXPTRBAS = 2; ! used to determine size of pointer in index literal IRC$C_IDXOVHDSZ = 1; ! includes record control byte ! literal IRC$S_IRCDEF = 1; ! Old size name - synonym literal IRC$S_IRC = 1; macro IRC$B_CONTROL = 0,0,8,0 %; ! record control byte macro IRC$R_CONTROL_BITS0 = 0,0,8,0 %; macro IRC$V_PTRSZ = 0,0,2,0 %; literal IRC$S_PTRSZ = 2; ! size of pointer macro IRC$V_RECORDCB = 0,2,6,0 %; literal IRC$S_RECORDCB = 6; ! record control bits ! ! record control bits used only in primary data record and SIDR array element ! control bytes ! macro IRC$R_CONTROL_BITS1 = 0,0,8,0 %; macro IRC$V_DELETED = 0,2,1,0 %; ! record is deleted macro IRC$V_NOPTRSZ = 0,4,1,0 %; ! no RRV macro IRC$V_FIRST_KEY = 0,7,1,0 %; ! ! record control bits used only in primary data record control bytes ! macro IRC$R_CONTROL_BITS2 = 0,0,8,0 %; macro IRC$V_RRV = 0,3,1,0 %; ! rrv record ! ! record control bits used only in prologue 2 SIDR record control bytes ! macro IRC$R_CONTROL_BITS3 = 0,0,8,0 %; macro IRC$V_NODUPCNT = 0,4,1,0 %; ! DUP_CNT field absent ! ! record control bits used only in prologue 3 RRV, UDR and SIDR record control ! bytes of RU journalled files. (RU_UPDATE is set only in UDR record control ! bytes) ! macro IRC$R_CONTROL_BITS4 = 0,0,8,0 %; macro IRC$V_RU_DELETE = 0,5,1,0 %; ! record is RU deleted macro IRC$V_RU_UPDATE = 0,6,1,0 %; ! record is RU updated ! ! record control bits reserved for RMS-11 use only (these may not be re-defined ! except for prologue 3 records) ! ! Bit number 5 ! Bit number 6 ! ! ! index bucket record ! macro IRC$R_CONTROL_FIELDS4 = 0,0,8,0 %; macro IRC$T_BUCKETPTR = 1,0,0,0 %; ! bucket pointer (not referenced in the code, ! just present for consistency) ! data bucket record ! literal IRC$S_IRCDEF1 = 3; ! Old size name - synonym literal IRC$S_IRC1 = 3; macro IRC$B_ID = 1,0,8,0 %; ! record id macro IRC$B_RRV_ID = 2,0,8,0 %; ! rrv's id -- always in the same place ! ! prologue 3 data bucket record ! literal IRC$C_DATSZFLD = 2; ! size of size field in variable length records literal IRC$C_DATPTRBAS = 3; ! used to determine size of RRV in data buckets literal IRC$C_DCNTSZFLD = 4; ! size of duplicate count field in Plg 2 SIDRs literal IRC$C_DATOVHDSZ = 2; ! includes the record control byte, and the id literal IRC$C_FIXOVHDSZ = 7; ! the record overhead for fixed record literal IRC$C_VAROVHDSZ = 9; ! record overhead for variable records literal IRC$C_RRVOVHDSZ = 7; ! size of RRV ! literal IRC$C_DATPTRBS3 = 4; ! used to determine size of RRV in data buckets literal IRC$C_DATOVHSZ3 = 3; ! record control byte, and id literal IRC$C_FIXOVHSZ3 = 9; ! record overhead for fixed length records literal IRC$C_VAROVHSZ3 = 11; ! record overhead for variable length records literal IRC$C_RRVOVHSZ3 = 9; ! size of RRV literal IRC$C_SDROVHSZ3 = 2; ! record overhead for SIDRs literal IRC$C_KEYCMPOVH = 2; ! key compression overhead literal IRC$C_DATCMPOVH = 3; ! data compression overhead literal IRC$S_IRCDEF2 = 5; ! Old size name - synonym literal IRC$S_IRC2 = 5; macro IRC$W_ID = 1,0,16,0 %; ! record id macro IRC$W_RRV_ID = 3,0,16,0 %; ! rrv's id -- always in the same place ! ! constants ! ! prologue 3 constants ! !*** MODULE $KEYDEF *** ! ! definitions for the key descriptors in the prologue ! ! these definitions are associated w/ the plg and area definitions ! literal KEY$M_DUPKEYS = %X'1'; literal KEY$M_CHGKEYS = %X'2'; literal KEY$M_NULKEYS = %X'4'; literal KEY$M_IDX_COMPR = %X'8'; literal KEY$M_INITIDX = %X'10'; literal KEY$M_KEY_COMPR = %X'40'; literal KEY$M_REC_COMPR = %X'80'; literal KEY$C_MAX_DAT = 10; ! (PLG3) Maximum size of a non-compressed data ! record literal KEY$C_MAX_PRIMARY = 6; ! (PLG3) Maximum size of a non-compressed ! primary key literal KEY$C_MAX_INDEX = 6; ! (PLG3) Maximum size of a non-compressed ! index and SIDR key literal KEY$C_STRING = 0; ! string data type literal KEY$C_SGNWORD = 1; ! signed binary word literal KEY$C_UNSGNWORD = 2; ! unsigned binary word literal KEY$C_SGNLONG = 3; ! signed binary long word literal KEY$C_UNSGNLONG = 4; ! unsigned binary long word literal KEY$C_PACKED = 5; ! packed decimal literal KEY$C_SGNQUAD = 6; ! signed binary quadword literal KEY$C_UNSGNQUAD = 7; ! unsigned binary quadword literal KEY$C_COLLATED = 8; ! collated literal KEY$C_MAX_ASCEND = 8; ! maximum ASCENDING data type literal KEY$C_DSTRING = 32; ! descending string data type literal KEY$C_DSGNWORD = 33; ! " signed binary word literal KEY$C_DUNSGNWORD = 34; ! " unsigned binary word literal KEY$C_DSGNLONG = 35; ! " signed binary long word literal KEY$C_DUNSGNLONG = 36; ! " unsigned binary long word literal KEY$C_DPACKED = 37; ! " packed decimal literal KEY$C_DSGNQUAD = 38; ! " signed binary quadword literal KEY$C_DUNSGNQUAD = 39; ! " unsigned binary quadword literal KEY$C_DCOLLATED = 40; ! " collated literal KEY$C_MAX_DATA = 40; ! maximum data type value allowed literal KEY$K_BLN = 96; ! length of key descriptor in the prologue (plg 3) literal KEY$C_BLN = 96; ! length of key descriptor in the prologue (plg 3) literal KEY$C_SPARE = 6; ! these are spare words in key block (plg 3) literal KEY$S_KEYDEF = 96; ! Old size name - synonym literal KEY$S_PROLOGUE_KEY = 96; macro KEY$L_IDXFL = 0,0,32,0 %; ! vbn for next key descriptor macro KEY$W_NOFF = 4,0,16,0 %; ! offset to next key descriptor macro KEY$B_IANUM = 6,0,8,0 %; ! index area number macro KEY$B_LANUM = 7,0,8,0 %; ! level 1 area number macro KEY$B_DANUM = 8,0,8,0 %; ! data area number macro KEY$B_ROOTLEV = 9,0,8,0 %; ! root level macro KEY$B_IDXBKTSZ = 10,0,8,0 %; ! index bucket size macro KEY$B_DATBKTSZ = 11,0,8,0 %; ! data bucket size macro KEY$L_ROOTVBN = 12,0,32,0 %; ! root bucket pointer macro KEY$R_FLAGS_OVERLAY = 16,0,8,0 %; macro KEY$B_FLAGS = 16,0,8,0 %; ! flag bits macro KEY$R_FLAGS_BITS0 = 16,0,8,0 %; macro KEY$V_DUPKEYS = 16,0,1,0 %; ! duplicate key values allowed macro KEY$V_CHGKEYS = 16,1,1,0 %; ! key value may change on $update operation macro KEY$V_NULKEYS = 16,2,1,0 %; ! null key character enabled macro KEY$V_IDX_COMPR = 16,3,1,0 %; ! index is compressed macro KEY$V_INITIDX = 16,4,1,0 %; ! index must be initialized macro KEY$V_KEY_COMPR = 16,6,1,0 %; ! (PLG3) key is compressed in data record macro KEY$R_FLAGS_BITS1 = 16,0,8,0 %; macro KEY$V_REC_COMPR = 16,7,1,0 %; ! (PLG3) Data record is compressed macro KEY$B_DATATYPE = 17,0,8,0 %; ! data type for key macro KEY$B_SEGMENTS = 18,0,8,0 %; ! number of segments in key macro KEY$B_NULLCHAR = 19,0,8,0 %; ! "null" character macro KEY$B_KEYSZ = 20,0,8,0 %; ! total key size macro KEY$B_KEYREF = 21,0,8,0 %; ! key of reference macro KEY$W_MINRECSZ = 22,0,16,0 %; ! minimum record length macro KEY$W_IDXFILL = 24,0,16,0 %; ! index fill quantity macro KEY$W_DATFILL = 26,0,16,0 %; ! data fill quantity macro KEY$R_POSITION_OVERLAY = 28,0,16,0 %; macro KEY$W_POSITION = 28,0,16,0 %; ! key seg position macro KEY$W_POSITION0 = 28,0,16,0 %; ! another name for position 0 macro KEY$W_POSITION1 = 30,0,16,0 %; ! position 1 macro KEY$W_POSITION2 = 32,0,16,0 %; ! position 2 macro KEY$W_POSITION3 = 34,0,16,0 %; ! position 3 macro KEY$W_POSITION4 = 36,0,16,0 %; ! position 4 macro KEY$W_POSITION5 = 38,0,16,0 %; macro KEY$W_POSITION6 = 40,0,16,0 %; macro KEY$W_POSITION7 = 42,0,16,0 %; macro KEY$R_SIZE_OVERLAY = 44,0,8,0 %; macro KEY$B_SIZE = 44,0,8,0 %; ! key segment size macro KEY$B_SIZE0 = 44,0,8,0 %; ! another name for size macro KEY$B_SIZE1 = 45,0,8,0 %; ! size 1 macro KEY$B_SIZE2 = 46,0,8,0 %; macro KEY$B_SIZE3 = 47,0,8,0 %; macro KEY$B_SIZE4 = 48,0,8,0 %; macro KEY$B_SIZE5 = 49,0,8,0 %; macro KEY$B_SIZE6 = 50,0,8,0 %; macro KEY$B_SIZE7 = 51,0,8,0 %; macro KEY$T_KEYNAM = 52,0,0,0 %; literal KEY$S_KEYNAM = 32; ! key name macro KEY$L_LDVBN = 84,0,32,0 %; ! first data bucket macro KEY$R_TYPE_OVERLAY = 88,0,8,0 %; macro KEY$B_TYPE = 88,0,8,0 %; ! key segment datatype (plg 3) macro KEY$B_TYPE0 = 88,0,8,0 %; ! another name for first datatype (plg 3) macro KEY$B_TYPE1 = 89,0,8,0 %; ! (plg 3) macro KEY$B_TYPE2 = 90,0,8,0 %; ! (plg 3) macro KEY$B_TYPE3 = 91,0,8,0 %; ! (plg 3) macro KEY$B_TYPE4 = 92,0,8,0 %; ! (plg 3) macro KEY$B_TYPE5 = 93,0,8,0 %; ! (plg 3) macro KEY$B_TYPE6 = 94,0,8,0 %; ! (plg 3) macro KEY$B_TYPE7 = 95,0,8,0 %; ! (plg 3) !*** MODULE $AREADEF *** ! ! ! definitions for the area descriptor in the prologue ! ! literal AREA$C_CYL = 1; ! cylinded alignment literal AREA$C_LBN = 2; ! logical block alignment literal AREA$C_VBN = 3; ! virtual block alignment literal AREA$C_RFI = 4; ! allocate close to related file by fid literal AREA$M_HARD = %X'1'; literal AREA$M_ONC = %X'2'; literal AREA$M_CBT = %X'20'; literal AREA$M_CTG = %X'80'; literal AREA$K_BLN = 64; ! length of area descriptor in the prologue literal AREA$C_BLN = 64; ! length of area descriptor in the prologue literal AREA$S_AREADEF = 64; ! Old size name - synonym literal AREA$S_PROLOGUE_AREA = 64; macro AREA$B_FLAGS = 1,0,8,0 %; ! not currently used macro AREA$B_AREAID = 2,0,8,0 %; ! area id macro AREA$B_ARBKTSZ = 3,0,8,0 %; ! bucket size for area macro AREA$W_VOLUME = 4,0,16,0 %; ! relative volume number macro AREA$B_ALN = 6,0,8,0 %; ! extend allocation alignment macro AREA$R_AOP_OVERLAY = 7,0,8,0 %; macro AREA$B_AOP = 7,0,8,0 %; ! alignment options macro AREA$R_AOP_BITS = 7,0,8,0 %; macro AREA$V_HARD = 7,0,1,0 %; ! absolute alignment or nothing macro AREA$V_ONC = 7,1,1,0 %; ! locate on cylinder macro AREA$V_CBT = 7,5,1,0 %; ! contiguous best try macro AREA$V_CTG = 7,7,1,0 %; ! contiguous macro AREA$L_AVAIL = 8,0,32,0 %; ! available (returned) buckets macro AREA$L_CVBN = 12,0,32,0 %; ! start vbn for current extent macro AREA$L_CNBLK = 16,0,32,0 %; ! number of blocks in current extent macro AREA$L_USED = 20,0,32,0 %; ! number of blocks used macro AREA$L_NXTVBN = 24,0,32,0 %; ! next vbn to use macro AREA$L_NXT = 28,0,32,0 %; ! start vbn for next extent macro AREA$L_NXBLK = 32,0,32,0 %; ! number of blocks in next extent macro AREA$W_DEQ = 36,0,16,0 %; ! default extend quantity macro AREA$L_LOC = 40,0,32,0 %; ! start lbn on volume macro AREA$W_RFI = 44,0,0,0 %; literal AREA$S_RFI = 6; ! related file id macro AREA$L_TOTAL_ALLOC = 50,0,32,0 %; ! total block allocation macro AREA$W_CHECK = 62,0,16,0 %; ! checksum !*** MODULE $RJRDEF *** ! ! ! definitions for the journal records in RMS journal files ! ! literal RJR$C_RMS_AI = 1; ! after-image journal literal RJR$C_RMS_BI = 2; ! before-image journal literal RJR$C_RMS_RU = 3; ! recovery unit literal RJR$C_RMS_AT = 4; ! audit trail literal RJR$C_MAXJNL = 4; ! jnl type limit literal RJR$C_VER1 = 1; ! journal version 1 literal RJR$C_CURVER = 1; ! current version literal RJR$C_NULL = 0; ! No entry follows the header literal RJR$C_LEADER = 1; ! leader entry literal RJR$C_TRAILER = 2; ! trailer entry literal RJR$C_RECORD = 3; ! record entry (AI, BI, RU) literal RJR$C_BLOCK = 4; ! block entry (AI, BI, RU) literal RJR$C_EXTEND = 5; ! extend entry (AI, AT) literal RJR$C_CREATE = 6; ! create entry (AI, AT) literal RJR$C_AT_RECORD = 7; ! audit trail record (AT) literal RJR$C_DEFINE_JNL = 8; ! Journal creation record literal RJR$C_BACKUP = 9; ! Backup done entry (AI, BI) literal RJR$C_COMMIT = 10; ! RU commit entry (AI, BI) literal RJR$C_ABORT = 11; ! RU abort entry (AI, BI) literal RJR$C_PREPARE = 12; ! RU prepare entry (AI, BI, RU) literal RJR$C_FORCED_COMMIT = 13; ! RU forced commit for AI jnls literal RJR$C_MAXTYP = 13; ! entry-type limit literal RJR$C_SEQ = 0; ! sequential file org literal RJR$C_REL = 1; ! relative file org literal RJR$C_IDX = 2; ! indexed file org literal RJR$C_HSH = 3; ! hashed file org literal RJR$C_MAXORG = 3; ! org limit literal RJR$_CLOSE = 1; ! close literal RJR$_CONNECT = 2; ! connect literal RJR$_CREATE = 3; ! create literal RJR$_DELETE = 4; ! delete literal RJR$_DISCONNECT = 5; ! disconnect literal RJR$_DISPLAY = 6; ! display literal RJR$_ENTER = 7; ! enter literal RJR$_ERASE = 8; ! erase literal RJR$_EXTEND = 9; ! extend literal RJR$_FIND = 10; ! find literal RJR$_FLUSH = 11; ! flush literal RJR$_FREE = 12; ! free literal RJR$_GET = 13; ! get literal RJR$_MODIFY = 14; ! modify literal RJR$_NXTVOL = 15; ! next volume literal RJR$_OPEN = 16; ! open literal RJR$_PARSE = 17; ! parse literal RJR$_PUT = 18; ! put literal RJR$_READ = 19; ! block I/O read literal RJR$_RELEASE = 20; ! release literal RJR$_REMOVE = 21; ! remove literal RJR$_RENAME = 22; ! rename literal RJR$_REWIND = 23; ! rewind literal RJR$_SEARCH = 24; ! search literal RJR$_SPACE = 25; ! block I/O space literal RJR$_TRUNCATE = 26; ! truncate literal RJR$_UPDATE = 27; ! update literal RJR$_WAIT = 28; ! wait literal RJR$_WRITE = 29; ! block I/O write literal RJR$_TPT = 30; ! truncate on PUT literal RJR$_MAXOPER = 30; ! oper limit literal RJR$C_HDRLEN = 72; ! common header len literal RJR$K_HDRLEN = 72; ! common header len literal RJR$C_COMMITLEN = 72; ! commit entry len literal RJR$K_COMMITLEN = 72; ! commit entry len literal RJR$C_ABORTLEN = 72; ! abort entry len literal RJR$K_ABORTLEN = 72; ! abort entry len literal RJR$C_FORCED_COMMITLEN = 72; ! forced commit entry len literal RJR$K_FORCED_COMMITLEN = 72; ! forced commit entry len ! literal RJR$C_LDRLEN = 169; ! leader entry len literal RJR$K_LDRLEN = 169; ! leader entry len ! the 3 filespec strings above appear here literal RJR$C_TRLLEN = 107; ! trailer entry len literal RJR$K_TRLLEN = 107; ! trailer entry len ! filespec of next journal file appears here literal RJR$C_RECLEN = 100; ! record entry len literal RJR$K_RECLEN = 100; ! record entry len literal RJR$C_BLKLEN = 96; ! block i/o entry len literal RJR$K_BLKLEN = 96; ! block i/o entry len literal RJR$M_EXT_USE_XAB = %X'1'; literal RJR$C_EXTLEN = 114; ! extend entry len literal RJR$K_EXTLEN = 114; ! extend entry len literal RJR$M_ATR_UCHAR = %X'1'; literal RJR$M_ATR_PROT = %X'2'; literal RJR$M_ATR_UIC = %X'4'; literal RJR$M_ATR_REC = %X'8'; literal RJR$M_ATR_EXPIRE = %X'10'; literal RJR$C_FIBLEN = 64; literal RJR$K_FIBLEN = 64; literal RJR$C_RECATRLEN = 32; literal RJR$K_RECATRLEN = 32; literal RJR$C_CRELEN = 226; literal RJR$K_CRELEN = 226; literal RJR$C_AT_RECLEN = 104; literal RJR$K_AT_RECLEN = 104; literal RJR$C_BACKUPLEN = 92; literal RJR$K_BACKUPLEN = 92; literal RJR$C_PREPARELEN = 112; ! prepare entry len literal RJR$K_PREPARELEN = 112; ! prepare entry len ! actual node name string follows here literal RJR$C_BLN = 226; ! length of RJR descriptor in the prologue literal RJR$K_BLN = 226; ! length of RJR descriptor in the prologue literal RJR$S_RJRDEF = 226; ! Old size name - synonym literal RJR$S_RJR = 226; macro RJR$W_FACILITY = 0,0,16,0 %; ! facility code (=1) macro RJR$W_FLAGS = 2,0,16,0 %; ! flags macro RJR$V_FIRST_RU_RECORD = 2,0,1,0 %; ! first journal record for this RU macro RJR$V_RUJ_IN_LTJ = 2,1,1,0 %; ! this is a RU record written to a LTJ macro RJR$V_WRITTEN_BY_RECOVER = 2,2,1,0 %; ! written during detached reocvery macro RJR$V_FIRST_STREAM_RU_RECORD = 2,3,1,0 %; ! first journal record for this stream and RU macro RJR$V_RECOVERED = 2,4,1,0 %; ! entries for leader record already recovered macro RJR$V_NOPAD = 2,5,1,0 %; ! Do not pad AI record macro RJR$L_JNLIDX = 4,0,32,0 %; ! journal stream index macro RJR$B_JNL_TYPE = 8,0,8,0 %; ! journaling type macro RJR$B_VERSION = 9,0,8,0 %; ! RMS journal version # macro RJR$B_ENTRY_TYPE = 10,0,8,0 %; ! journal entry type macro RJR$B_ORG = 11,0,8,0 %; ! file organization macro RJR$B_OPER = 12,0,8,0 %; ! RMS operation id macro RJR$T_RUID = 16,0,0,0 %; literal RJR$S_RUID = 16; ! RUID (if operation performed in an RU) macro RJR$T_TID = 16,0,0,0 %; literal RJR$S_TID = 16; ! TID is the RUID under DDTM macro RJR$L_EPID = 32,0,32,0 %; ! EPID of the process writing the entry macro RJR$Q_DATE = 36,0,0,0 %; literal RJR$S_DATE = 8; ! date/time of record macro RJR$L_AT_STS = 44,0,32,0 %; ! status of operation (AT) macro RJR$L_AT_STV = 48,0,32,0 %; ! secondary status (AT) macro RJR$L_AT_CTX = 52,0,32,0 %; ! user FAB/RAB CTX field (AT) ! End of common RJR header. Begin entry-specific definitions. ! ! ! Leader record. First record in each journal file. ! macro RJR$W_FILESPEC_OFF = 72,0,16,0 %; ! offset to filespec of file being journaled (from top of RJR) macro RJR$W_FILESPEC_LEN = 74,0,16,0 %; ! length of filespec of file being journaled macro RJR$B_VOLNAM_LEN = 76,0,8,0 %; ! length of volume name string macro RJR$T_VOLNAM = 77,0,0,0 %; literal RJR$S_VOLNAM = 12; ! volume name of file being journaled macro RJR$T_FID = 89,0,0,0 %; literal RJR$S_FID = 6; ! FID of file being journaled macro RJR$Q_CDATE = 95,0,0,0 %; literal RJR$S_CDATE = 8; ! creation date of file being journaled macro RJR$W_J_FILESPEC_OFF = 103,0,16,0 %; ! offset to filespec of journal file (from top of RJR) macro RJR$W_J_FILESPEC_LEN = 105,0,16,0 %; ! length of filespec of journal file macro RJR$B_J_VOLNAM_LEN = 107,0,8,0 %; ! length of volume name string macro RJR$T_J_VOLNAM = 108,0,0,0 %; literal RJR$S_J_VOLNAM = 12; ! volume name of journal file macro RJR$T_J_FID = 120,0,0,0 %; literal RJR$S_J_FID = 6; ! FID of journal file macro RJR$Q_J_CDATE = 126,0,0,0 %; literal RJR$S_J_CDATE = 8; ! creation date of journal file macro RJR$W_PJ_FILESPEC_OFF = 134,0,16,0 %; ! offset to filespec of previous journal file (from top of RJR) macro RJR$W_PJ_FILESPEC_LEN = 136,0,16,0 %; ! length of filespec of previous journal file macro RJR$B_PJ_VOLNAM_LEN = 138,0,8,0 %; ! length of volume name string macro RJR$T_PJ_VOLNAM = 139,0,0,0 %; literal RJR$S_PJ_VOLNAM = 12; ! volume name of previous journal file macro RJR$T_PJ_FID = 151,0,0,0 %; literal RJR$S_PJ_FID = 6; ! FID of previous journal file macro RJR$Q_PJ_CDATE = 157,0,0,0 %; literal RJR$S_PJ_CDATE = 8; ! creation date of previous journal file macro RJR$L_PJ_JNLIDX = 165,0,32,0 %; ! journal stream index of the previous journal file ! ! Trailer record. This record is only present in AI or BI journal files that ! have newer versions. It is written to the old journal file when a file that ! was already marked for journaling is re-marked for journaling to point to ! a newer version of a journal file. ! macro RJR$W_NJ_FILESPEC_OFF = 72,0,16,0 %; ! offset to filespec of next journal file (from top of RJR) macro RJR$W_NJ_FILESPEC_LEN = 74,0,16,0 %; ! length of filespec of next journal file macro RJR$B_NJ_VOLNAM_LEN = 76,0,8,0 %; ! length of volume name string macro RJR$T_NJ_VOLNAM = 77,0,0,0 %; literal RJR$S_NJ_VOLNAM = 12; ! volume name of next journal file macro RJR$T_NJ_FID = 89,0,0,0 %; literal RJR$S_NJ_FID = 6; ! FID of next journal file macro RJR$Q_NJ_CDATE = 95,0,0,0 %; literal RJR$S_NJ_CDATE = 8; ! creation date of next journal file macro RJR$L_NJ_JNLIDX = 103,0,32,0 %; ! Journal stream index of the next journal file ! ! Record entry. Used for AI, BI, and RU to journal record operations. ! macro RJR$L_CHKSUM = 88,0,32,0 %; ! checksum of old record macro RJR$W_RFA = 92,0,0,0 %; literal RJR$S_RFA = 6; ! RFA of record macro RJR$L_RFA0 = 92,0,32,0 %; ! alternate RFA def macro RJR$W_RFA4 = 96,0,16,0 %; macro RJR$L_RRN = 92,0,32,0 %; ! relative record number macro RJR$W_RSIZE = 98,0,16,0 %; ! record size macro RJR$T_RIMAGE = 100,0,0,0 %; ! record data ! ! The block entry is used for ISAM AI/BI bucket entries, $WRITEs, and AT. ! macro RJR$L_BLOCK_VBN = 88,0,32,0 %; ! vbn of block macro RJR$W_BLOCK_SIZE = 92,0,16,0 %; ! transfer size macro RJR$W_JBLOCK_SIZE = 94,0,16,0 %; ! actual size of ! journaled data macro RJR$T_BLOCK = 96,0,0,0 %; ! block data ! ! RJR$C_BLKLEN must be a quadword multiple or indexed data buffers ! will not be quadword aligned!!! This constant is used to size ! indexed data buffers which have imbedded AI and BI RJR headers ! when long term journaling is used. ! ! ! The extend entry is common to both AT and AI journaling. ! macro RJR$L_EXT_FLAGS = 88,0,32,0 %; macro RJR$V_EXT_USE_XAB = 88,0,1,0 %; ! ALL XAB fields present ! ! Fields EXT_AOP (unused) through EXT_RFI are in same relative locations as ! the same fields in allocation XAB. ! macro RJR$B_EXT_AOP = 92,0,8,0 %; ! align options macro RJR$B_EXT_ALN = 93,0,8,0 %; ! alignment boundary macro RJR$W_EXT_VOL = 94,0,16,0 %; ! relative volume number macro RJR$L_EXT_LOC = 96,0,32,0 %; ! location macro RJR$L_EXT_ALQ = 100,0,32,0 %; ! allocation quantity macro RJR$W_EXT_DEQ = 104,0,16,0 %; ! default extension macro RJR$B_EXT_BKZ = 106,0,8,0 %; ! bucket size macro RJR$B_EXT_AID = 107,0,8,0 %; ! area ID macro RJR$W_EXT_RFI = 108,0,0,0 %; literal RJR$S_EXT_RFI = 6; ! related file IFI macro RJR$T_EXT_ENDALL = 114,0,0,0 %; ! end of all info ! ! The CREATE entry is used to record the information required to re-create ! a file for AI journaling, and to record a create for AT journaling. ! macro RJR$L_ATR_FLAGS = 88,0,32,0 %; macro RJR$V_ATR_UCHAR = 88,0,1,0 %; ! UCHAR attribute present macro RJR$V_ATR_PROT = 88,1,1,0 %; ! PROT attribute present macro RJR$V_ATR_UIC = 88,2,1,0 %; ! UIC attribute present macro RJR$V_ATR_REC = 88,3,1,0 %; ! RECORD attributes present macro RJR$V_ATR_EXPIRE = 88,4,1,0 %; ! EXPIRATION present macro RJR$L_UIC = 92,0,32,0 %; ! owner UIC macro RJR$L_PROT = 96,0,32,0 %; ! prot mask macro RJR$L_ALLOC = 100,0,32,0 %; ! initial allocation (audit) macro RJR$L_UCHAR = 104,0,32,0 %; ! user characteristics (create) macro RJR$Q_EXPIRE = 108,0,0,0 %; literal RJR$S_EXPIRE = 8; ! expiration date (create) macro RJR$B_FAC = 116,0,8,0 %; ! file access (audit) macro RJR$B_SHR = 117,0,8,0 %; ! sharing allowed (audit) macro RJR$W_DID = 118,0,0,0 %; literal RJR$S_DID = 6; ! directory ID (create, volume recovery) macro RJR$T_FIB = 126,0,0,0 %; literal RJR$S_FIB = 64; ! FIB (create) macro RJR$T_REC_ATTR = 190,0,0,0 %; literal RJR$S_REC_ATTR = 32; ! record attributes (create) macro RJR$W_C_FILESPEC_OFF = 222,0,16,0 %; ! offset to full filespec (from top of RJR) macro RJR$W_C_FILESPEC_LEN = 224,0,16,0 %; ! length of full filespec ! ! The AT record is used for audit-trail journaling. ! macro RJR$L_AT_ROP = 88,0,32,0 %; ! record options macro RJR$B_AT_KRF = 92,0,8,0 %; ! key of reference macro RJR$B_AT_KSZ = 93,0,8,0 %; ! key size macro RJR$B_AT_RAC = 94,0,8,0 %; ! record access mode macro RJR$W_AT_RFA = 96,0,0,0 %; literal RJR$S_AT_RFA = 6; ! RFA of record macro RJR$L_AT_RFA0 = 96,0,32,0 %; ! alternate RFA def macro RJR$W_AT_RFA4 = 100,0,16,0 %; macro RJR$L_AT_RRN = 96,0,32,0 %; ! relative record number macro RJR$T_AT_KEY = 104,0,0,0 %; ! key if used ! ! The BACKUP_ENTRY record is used to flag that a backup has been taken on the ! data file being journaled. It provides a known starting point for rollforward. ! macro RJR$L_BACKUP_SEQNO = 88,0,32,0 %; ! Backup sequence number ! ! The prepare record is written to RU, AI, and BI journals for transactions ! that required a two-phase commit protocol. ! macro RJR$T_DDTM_LOG_ID = 72,0,0,0 %; literal RJR$S_DDTM_LOG_ID = 16; ! DDTM log id macro RJR$T_RUJ_LOG_ID = 88,0,0,0 %; literal RJR$S_RUJ_LOG_ID = 16; ! RMS RUJ log id macro RJR$W_NODE_NAME_OFF = 104,0,16,0 %; ! offset to node name string macro RJR$W_NODE_NAME_LEN = 106,0,16,0 %; ! length of node name string macro RJR$W_RM_NAME_OFF = 108,0,16,0 %; ! offset to resource manager name string macro RJR$W_RM_NAME_LEN = 110,0,16,0 %; ! length of resource manager name string ! ! ---- < End of module RMSFILSTR.R32 - 30-MAR-2010 16:38:48.59 > - ! ! ! ************************************************************************* ! * * ! * © Copyright 2010, Hewlett-Packard Development Company, L.P. * ! * * ! * Confidential computer software. Valid license from HP and/or * ! * its subsidiaries required for possession, use, or copying. * ! * * ! * Consistent with FAR 12.211 and 12.212, Commercial Computer Software, * ! * Computer Software Documentation, and Technical Data for Commercial * ! * Items are licensed to the U.S. Government under vendor's standard * ! * commercial license. * ! * * ! * Neither HP nor any of its subsidiaries shall be liable for technical * ! * or editorial errors or omissions contained herein. The information * ! * in this document is provided "as is" without warranty of any kind and * ! * is subject to change without notice. The warranties for HP products * ! * are set forth in the express limited warranty statements accompanying * ! * such products. Nothing herein should be construed as constituting an * ! * additional warranty. * ! * * ! ************************************************************************* ! ******************************************************************************************************************************** ! Created: 30-Mar-2010 16:12:18 by OpenVMS SDL EV3-3 ! Source: 23-JUN-2004 13:16:13 $1$DGA7374:[LIB.SRC]RMSPUBSTR.SDL;1 ! ******************************************************************************************************************************** !*** MODULE $FSBDEF *** ! ! FSB field definitions ! ! File statistics block (fsb) ! ! An FSB is associated with a file when the ACE$V_STATISTICS ! bit is set in the RMS attributes ACE. It is used to keep track ! of RMS file statistics. ! literal FSB$M_PRIVATE = %X'1'; literal FSB$M_RMSDEV = %X'2'; literal FSB$C_BID = 25; ! fsb id code literal FSB$K_STANDARD_BLN = 276; ! Length of FSB without RMS development specific fields literal FSB$C_STANDARD_BLN = 276; ! Length of FSB without RMS development specific fields ! Reserved for RMS development private monitoring literal FSBFLG$_GET = 0; ! Flags used for keeping track of relative file statistics updates literal FSBFLG$_FIND = 1; literal FSBFLG$_PUT = 2; literal FSBFLG$_UPDATE = 3; literal FSBFLG$_DELETE = 4; literal FSBFLG$_MAX = 5; literal FSB$K_VERSION = 1; ! Current version of FSB literal FSB$C_VERSION = 1; ! Current version of FSB literal FSB$C_SEQ = 1; literal FSB$C_REL = 2; literal FSB$C_IDX = 3; ! File organization constants literal FSB$K_BLN = 384; ! Length of FSB literal FSB$C_BLN = 384; ! Length of FSB literal FSB$S_FSBDEF = 384; ! Old size name - synonym literal FSB$S_FSB = 384; macro FSB$W_FLAGS = 6,0,16,0 %; ! fsb flags macro FSB$V_PRIVATE = 6,0,1,0 %; ! FSB is for only one stream macro FSB$V_RMSDEV = 6,1,1,0 %; ! Reserved RMS fields being used macro FSB$B_BID = 8,0,8,0 %; ! block id macro FSB$B_BLN = 9,0,8,0 %; ! block length in longwords macro FSB$B_ORG = 10,0,8,0 %; ! file organization macro FSB$B_VERSION = 11,0,8,0 %; ! current version of FSB macro FSB$L_SEQGETS = 12,0,32,0 %; ! # of sequential gets to file macro FSB$L_KEYGETS = 16,0,32,0 %; ! # of keyed gets to file macro FSB$L_RFAGETS = 20,0,32,0 %; ! # of gets by RFA to file macro FSB$Q_GETBYTES = 24,0,0,0 %; literal FSB$S_GETBYTES = 8; ! Total size of all gets in bytes macro FSB$L_SEQPUTS = 32,0,32,0 %; ! # of sequential puts macro FSB$L_KEYPUTS = 36,0,32,0 %; ! # of puts by key macro FSB$Q_PUTBYTES = 40,0,0,0 %; literal FSB$S_PUTBYTES = 8; ! Total size of all puts in bytes macro FSB$L_UPDATES = 48,0,32,0 %; ! # of updates macro FSB$Q_UPDATEBYTES = 52,0,0,0 %; literal FSB$S_UPDATEBYTES = 8; ! Total size of all updates in bytes macro FSB$L_DELETES = 60,0,32,0 %; ! # of deletes macro FSB$L_TRUNCATES = 64,0,32,0 %; ! # of truncates macro FSB$L_TRUNCBLKS = 68,0,32,0 %; ! Total size in blocks of all truncates macro FSB$L_SEQFINDS = 72,0,32,0 %; ! # of sequential finds macro FSB$L_KEYFINDS = 76,0,32,0 %; ! # of keyed finds macro FSB$L_RFAFINDS = 80,0,32,0 %; ! # of finds by RFA macro FSB$L_READS = 84,0,32,0 %; ! # of $READs to file macro FSB$Q_READBYTES = 88,0,0,0 %; literal FSB$S_READBYTES = 8; ! # of bytes of all $READs macro FSB$L_CONNECTS = 96,0,32,0 %; ! # of connects to this file macro FSB$L_DISCONNECTS = 100,0,32,0 %; ! # of disconnects from file macro FSB$L_EXTENDS = 104,0,32,0 %; ! # of extends of file macro FSB$L_EXTBLOCKS = 108,0,32,0 %; ! # of blocks file has been extended macro FSB$L_FLUSHES = 112,0,32,0 %; ! # of flushes of file macro FSB$L_REWINDS = 116,0,32,0 %; ! # of rewinds of file macro FSB$L_WRITES = 120,0,32,0 %; ! # of $WRITEs to file macro FSB$Q_WRITEBYTES = 124,0,0,0 %; literal FSB$S_WRITEBYTES = 8; ! # of bytes of all $WRITEs to file macro FSB$L_FLCKENQS = 132,0,32,0 %; ! # of file lock ENQ's macro FSB$L_FLCKDEQS = 136,0,32,0 %; ! # of file lock DEQ's macro FSB$L_FLCKCNVS = 140,0,32,0 %; ! # of file lock conversions macro FSB$L_LBLCKENQS = 144,0,32,0 %; ! # of local buffer lock ENQ's macro FSB$L_LBLCKDEQS = 148,0,32,0 %; ! # of local buffer lock DEQ's macro FSB$L_LBLCKCNVS = 152,0,32,0 %; ! # of local buffer lock conversions macro FSB$L_GBLCKENQS = 156,0,32,0 %; ! # of global buffer lock ENQ's macro FSB$L_GBLCKDEQS = 160,0,32,0 %; ! # of global buffer lock DEQ's macro FSB$L_GBLCKCNVS = 164,0,32,0 %; ! # of global buffer lock conversions macro FSB$L_GSLCKENQS = 168,0,32,0 %; ! # of global section lock ENQ's macro FSB$L_GSLCKDEQS = 172,0,32,0 %; ! # of global section lock DEQ's macro FSB$L_GSLCKCNVS = 176,0,32,0 %; ! # of global section lock conversions macro FSB$L_RLCKENQS = 180,0,32,0 %; ! # of record lock ENQ's macro FSB$L_RLCKDEQS = 184,0,32,0 %; ! # of record lock DEQ's macro FSB$L_RLCKCNVS = 188,0,32,0 %; ! # of record lock conversions macro FSB$L_APPLCKENQS = 192,0,32,0 %; ! # of append lock ENQ's macro FSB$L_APPLCKDEQS = 196,0,32,0 %; ! # of append lock DEQ's macro FSB$L_APPLCKCNVS = 200,0,32,0 %; ! # of append lock conversions macro FSB$L_FLBLKASTS = 204,0,32,0 %; ! # of file lock blocking ASTs queued macro FSB$L_LBLBLKASTS = 208,0,32,0 %; ! # of local buffer lock blocking ASTs queued macro FSB$L_GBLBLKASTS = 212,0,32,0 %; ! # of global buffer lock blocking ASTs queued macro FSB$L_APPBLKASTS = 216,0,32,0 %; ! # of shared append lock blocking ASTs queued macro FSB$L_LCACHEHITS = 220,0,32,0 %; ! # of cache hits on local buffers macro FSB$L_LCACHE_ATTEMPTS = 224,0,32,0 %; ! # of attempts to use the local buffer cache macro FSB$L_GCACHEHITS = 228,0,32,0 %; ! # of cache hits on global buffers macro FSB$L_GCACHE_ATTEMPTS = 232,0,32,0 %; ! # of attempts to use the global buffer cache macro FSB$L_GBRDIRIOS = 236,0,32,0 %; ! # of direct io's due to global buffer reads macro FSB$L_GBWDIRIOS = 240,0,32,0 %; ! # of direct io's due to global buffer writes macro FSB$L_LBRDIRIOS = 244,0,32,0 %; ! # of direct io's due to local buffer reads macro FSB$L_LBWDIRIOS = 248,0,32,0 %; ! # of direct io's due to local buffer writes macro FSB$L_BKTSPLT = 252,0,32,0 %; ! # of 2 bucket splits macro FSB$L_MBKTSPLT = 256,0,32,0 %; ! # of multi-bucket splits macro FSB$L_OPENS = 260,0,32,0 %; ! # of times the file is opened macro FSB$L_CLOSES = 264,0,32,0 %; ! # of times the file is closed macro FSB$L_GSBLKASTS = 268,0,32,0 %; ! # of global section lock blocking ASTs queued macro FSB$L_XQPQIOS = 272,0,32,0 %; ! Count of XQP QIOs requested by RMS macro FSB$L_FLWAITS = 276,0,32,0 %; ! # of waits forced by getting the file lock macro FSB$L_LBWAITS = 280,0,32,0 %; ! # of waits forced by getting local buffer locks macro FSB$L_GBWAITS = 284,0,32,0 %; ! # of waits forced by getting global buffer locks macro FSB$L_GSWAITS = 288,0,32,0 %; ! # of waits forced by getting the global section lock macro FSB$L_RLWAITS = 292,0,32,0 %; ! # of waits forced by getting record locks macro FSB$L_APWAITS = 296,0,32,0 %; ! # of waits forced by getting the Append lock macro FSB$L_TOTWAITS = 300,0,32,0 %; ! Total # of waits (or stalls) performed by RMS. macro FSB$L_OUTBUFQUO = 304,0,32,0 %; ! Number of times a process runs out of global buffer quota macro FSB$L_RMSDEV1 = 308,0,32,0 %; ! Reserved for RMS development private monitoring macro FSB$L_RMSDEV2 = 312,0,32,0 %; ! Reserved for RMS development private monitoring macro FSB$L_RMSDEV3 = 316,0,32,0 %; ! Reserved for RMS development private monitoring macro FSB$L_RMSDEV4 = 320,0,32,0 %; ! Reserved for RMS development private monitoring macro FSB$L_RMSDEV5 = 324,0,32,0 %; ! Reserved for RMS development private monitoring macro FSB$L_RMSDEV6 = 328,0,32,0 %; ! Reserved for RMS development private monitoring macro FSB$L_RMSDEV7 = 332,0,32,0 %; ! Reserved for RMS development private monitoring macro FSB$L_RMSDEV8 = 336,0,32,0 %; ! Reserved for RMS development private monitoring macro FSB$L_RMSDEV9 = 340,0,32,0 %; ! Reserved for RMS development private monitoring macro FSB$L_RMSDEV10 = 344,0,32,0 %; ! Reserved for RMS development private monitoring macro FSB$L_RMSDEV11 = 348,0,32,0 %; ! Reserved for RMS development private monitoring macro FSB$L_RMSDEV12 = 352,0,32,0 %; ! Reserved for RMS development private monitoring macro FSB$L_RMSDEV13 = 356,0,32,0 %; ! Reserved for RMS development private monitoring macro FSB$L_RMSDEV14 = 360,0,32,0 %; ! Reserved for RMS development private monitoring macro FSB$L_RMSDEV15 = 364,0,32,0 %; ! Reserved for RMS development private monitoring macro FSB$L_INTCOL_GBHSH = 368,0,32,0 %; ! Interlock collision on global buffer hash table macro FSB$L_INTCOL_HSHTBL = 368,0,32,0 %; ! Old field name for compatibility macro FSB$L_INTCOL_GBH = 372,0,32,0 %; ! Interlock Collision on global buffer header macro FSB$L_INTRNDWN_GBHSH = 376,0,32,0 %; ! Interlock still held at rundown on GBHSH macro FSB$L_INTRES_SETIMR = 376,0,32,0 %; ! Old field name for compatibility macro FSB$L_INTRNDWN_GBH = 380,0,32,0 %; ! Interlock still held at rundown on GBH macro FSB$L_INTNOTRES = 380,0,32,0 %; ! Old field name for compatibility !*** MODULE $RMSEDTDEF *** ! ! RMS Extension Dispatch Table ! ! The RMS extension dispatch table defines the vector area for RMS processing ! callouts. ! literal RMSEDT$K_CURVER = 1; literal RMSEDT$C_CURVER = 1; literal RMSEDT$K_XAB_DISPLAY = 63; literal RMSEDT$K_LENGTH = 180; literal RMSEDT$C_LENGTH = 180; literal RMSEDT$S_RMSEDTDEF = 180; ! Old size name - synonym literal RMSEDT$S_RMSEDT = 180; macro RMSEDT$W_SIZE = 0,0,16,0 %; macro RMSEDT$B_VERSION = 2,0,8,0 %; macro RMSEDT$B_FLAGS = 3,0,8,0 %; macro RMSEDT$A_CLOSE = 4,0,32,0 %; macro RMSEDT$A_CONNECT = 8,0,32,0 %; macro RMSEDT$A_CREATE = 12,0,32,0 %; macro RMSEDT$A_IMPLIED_CREATE = 16,0,32,0 %; macro RMSEDT$A_DELETE = 20,0,32,0 %; macro RMSEDT$A_DISCONNECT = 24,0,32,0 %; macro RMSEDT$A_DISPLAY = 28,0,32,0 %; macro RMSEDT$A_ERASE = 32,0,32,0 %; macro RMSEDT$A_IMPLIED_ERASE = 36,0,32,0 %; macro RMSEDT$A_EXTEND = 40,0,32,0 %; macro RMSEDT$A_AUTOEXTEND = 44,0,32,0 %; macro RMSEDT$A_FIND = 48,0,32,0 %; macro RMSEDT$A_FLUSH = 52,0,32,0 %; macro RMSEDT$A_GET = 56,0,32,0 %; macro RMSEDT$A_OPEN = 60,0,32,0 %; macro RMSEDT$A_PUT = 64,0,32,0 %; macro RMSEDT$A_READ = 68,0,32,0 %; macro RMSEDT$A_RENAME = 72,0,32,0 %; macro RMSEDT$A_IMPLIED_RENAME = 76,0,32,0 %; macro RMSEDT$A_REWIND = 80,0,32,0 %; macro RMSEDT$A_INIT_WCC_SEARCH = 84,0,32,0 %; macro RMSEDT$A_NEXT_ECXT_SEARCH = 88,0,32,0 %; macro RMSEDT$A_DELETE_WCC_SEARCH = 92,0,32,0 %; macro RMSEDT$A_SPACE = 96,0,32,0 %; macro RMSEDT$A_TRUNCATE = 100,0,32,0 %; macro RMSEDT$A_UPDATE = 104,0,32,0 %; macro RMSEDT$A_WRITE = 108,0,32,0 %; macro RMSEDT$A_OPEN_LTJ = 112,0,32,0 %; macro RMSEDT$A_CLOSE_LTJ = 116,0,32,0 %; macro RMSEDT$A_FORMAT_JOURNAL = 120,0,32,0 %; macro RMSEDT$A_WRITE_JOURNAL = 124,0,32,0 %; macro RMSEDT$A_FLUSH_JOURNAL = 128,0,32,0 %; macro RMSEDT$A_CREATE_RUJ = 132,0,32,0 %; macro RMSEDT$A_CLOSE_RUJ = 136,0,32,0 %; macro RMSEDT$A_DISPOSE_RU = 140,0,32,0 %; macro RMSEDT$A_WRITE_RUJ = 144,0,32,0 %; macro RMSEDT$A_FLUSH_RUJ = 148,0,32,0 %; macro RMSEDT$A_LOCK_RECORD = 152,0,32,0 %; macro RMSEDT$A_UNLOCK_RECORD = 156,0,32,0 %; macro RMSEDT$A_UNLOCK_ALL_RECORDS = 160,0,32,0 %; macro RMSEDT$A_IS_RECORD_LOCKED = 164,0,32,0 %; macro RMSEDT$A_IS_RECORD_WRITE_LOCKED = 168,0,32,0 %; macro RMSEDT$A_IS_RECORD_LOCK_HELD = 172,0,32,0 %; macro RMSEDT$A_XAB_DISPATCH = 176,0,32,0 %; !*** MODULE $DISPLAY_WILDEF *** ! ! $DISPLAY_WILD ! ! Display File ! ! $DISPLAY_WILD fab, [err], [suc], ctx ! ! fab_rab = address of fab or rab ! ! err = address of user error completion routine ! ! suc = address of user success completion routine ! ctx = address of a longword used to hold the next ifi. ! %if not %declared(%quote SDL$$DISPLAY_WILDEF_REQ) %then ! MACRO to emit warning and default to 0 if required argument is missing ! macro SDL$$DISPLAY_WILDEF_REQ(ARG1, arg2) = %IF not %NULL(ARG1) %THEN ARG1 %else %warn(%string('REQUIRED ARGUMENT ', %NAME(ARG2), ' MISSING')) 0 %FI %; %fi %if not %declared(%quote SDL$$DISPLAY_WILDEF_OPT) %then ! Defaults omitted arguments to 0 if followed by additional arguments ! macro SDL$$DISPLAY_WILDEF_OPT[ARG] = %IF %NULL(ARG) %THEN %IF NOT %NULL(%REMAINING) %THEN 0 %FI %ELSE ARG %FI %; %fi %if not %declared(%quote SDL$$DISPLAY_WILDEF_LIST_0_REQ) %then ! Handles LIST parameters that are also OPTIONAL ! macro SDL$$DISPLAY_WILDEF_LIST_0_REQ(ARG) = %IF NOT %NULL(ARG) %THEN %REMOVE(ARG) %FI %; %fi %if not %declared(%quote SDL$$DISPLAY_WILDEF_LIST_1_REQ) %then ! Handles LIST parameters that are not OPTIONAL ! Emits warning and defaults to 0 if required argument is missing ! macro SDL$$DISPLAY_WILDEF_LIST_1_REQ(ARG, ARG2) = %IF %NULL(ARG) %THEN %warn(%string('REQUIRED ARGUMENT ', %NAME(ARG2), ' MISSING')) 0 %ELSE SDL$$DISPLAY_WILDEF_LIST_0_REQ(ARG) %FI %; %fi %if not %declared(%quote SDL$$DISPLAY_WILDEF_CONCAT) %then ! Eliminates trailing null arguments ! macro SDL$$DISPLAY_WILDEF_CONCAT[ARG] = %IF NOT %NULL(ARG) %THEN ARG %FI %; %fi ! *********************************** KEYWORDMACRO $DISPLAY_WILD (FAB_RAB,ERR=0,SUC=0,CTX) = BEGIN EXTERNAL ROUTINE SYS$DISPLAY : BLISS ADDRESSING_MODE (GENERAL); SYS$DISPLAY (SDL$$DISPLAY_WILDEF_CONCAT( SDL$$DISPLAY_WILDEF_REQ(FAB_RAB, %QUOTE FAB_RAB) , ERR, SUC, SDL$$DISPLAY_WILDEF_REQ(CTX, %QUOTE CTX) )) END %; !*** MODULE $MODDEF *** ! ! RMS MODify definitions ! ! The following values identify various requests for non-standard rms ! functions. They are currently input to the $modify function in the ! ctx field of the fab only if the esc bit is set in fop (rab functions ! are also accepted). Incorrect use of these capabilties could cause ! RMS to fail, hence great caution should be exercised in their use. ! ! These functions are also called RME$C_xxxx. They are defined ! in the public module [STARLET]RMSUSR.SDL and cannot be changed. ! Any addition made to $MODDEF in this module should also be made to ! $RMEDEF in that module. ! ! FAB function calls literal MOD$C_SETRFM = 1; ! change rfm, mrs, and fsz (if vfc) in ifab only literal MOD$C_PPFECHO = 2; ! enable echo of SYS$INPUT to SYS$OUTPUT literal MOD$C_SETRCF = 3; ! change recovery mode literal MOD$C_KEEP_LOCK_ON = 4; ! Turn on Keep Lock behavior literal MOD$C_KEEP_LOCK_OFF = 5; ! Turn off Keep Lock behavior literal MOD$C_RU_ACE_ON = 6; ! Turn on RU ACE locking literal MOD$C_RU_ACE_OFF = 7; ! Turn off RU ACE locking literal MOD$C_SET_RECATTR = 8; ! change rfm, org, rat, mrs, and fsz (if vfc) in ifab only ! RAB function calls literal MOD$C_LOCK_RECORD = 1; ! Lock a record literal MOD$C_ASSOCIATE = 2; ! Associate a stream with a transaction ! ! ---- < End of module RMSPUBSTR.R32 - 30-MAR-2010 16:38:50.42 > - ! ! ! ************************************************************************* ! * * ! * © Copyright 2010, Hewlett-Packard Development Company, L.P. * ! * * ! * Confidential computer software. Valid license from HP and/or * ! * its subsidiaries required for possession, use, or copying. * ! * * ! * Consistent with FAR 12.211 and 12.212, Commercial Computer Software, * ! * Computer Software Documentation, and Technical Data for Commercial * ! * Items are licensed to the U.S. Government under vendor's standard * ! * commercial license. * ! * * ! * Neither HP nor any of its subsidiaries shall be liable for technical * ! * or editorial errors or omissions contained herein. The information * ! * in this document is provided "as is" without warranty of any kind and * ! * is subject to change without notice. The warranties for HP products * ! * are set forth in the express limited warranty statements accompanying * ! * such products. Nothing herein should be construed as constituting an * ! * additional warranty. * ! * * ! ************************************************************************* ! ******************************************************************************************************************************** ! Created: 30-Mar-2010 16:11:58 by OpenVMS SDL EV3-3 ! Source: 30-MAR-2010 16:11:57 $1$DGA7374:[LIB.SRC]SDAMSG.SDL;1 ! ******************************************************************************************************************************** !*** MODULE $SDA_MSGDEF *** ! ! This SDL File Generated by VAX-11 Message V04-00 on 30-MAR-2010 16:11:57.25 ! ! ! VERSION: 'X-39' ! ! ************************************************************************* ! * * ! * © COPYRIGHT 2008 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. * ! * * ! * CONFIDENTIAL COMPUTER SOFTWARE. VALID LICENSE FROM HP AND/OR * ! * ITS SUBSIDIARIES REQUIRED FOR POSSESSION, USE, OR COPYING. * ! * * ! * CONSISTENT WITH FAR 12.211 AND 12.212, COMMERCIAL COMPUTER SOFTWARE, * ! * COMPUTER SOFTWARE DOCUMENTATION, AND TECHNICAL DATA FOR COMMERCIAL * ! * ITEMS ARE LICENSED TO THE U.S. GOVERNMENT UNDER VENDOR'S STANDARD * ! * COMMERCIAL LICENSE. * ! * * ! * NEITHER HP NOR ANY OF ITS SUBSIDIARIES SHALL BE LIABLE FOR TECHNICAL * ! * OR EDITORIAL ERRORS OR OMISSIONS CONTAINED HEREIN. THE INFORMATION * ! * IN THIS DOCUMENT IS PROVIDED "as is" WITHOUT WARRANTY OF ANY KIND AND * ! * IS SUBJECT TO CHANGE WITHOUT NOTICE. THE WARRANTIES FOR HP PRODUCTS * ! * ARE SET FORTH IN THE EXPRESS LIMITED WARRANTY STATEMENTS ACCOMPANYING * ! * SUCH PRODUCTS. NOTHING HEREIN SHOULD BE CONSTRUED AS CONSTITUTING AN * ! * ADDITIONAL WARRANTY. * ! * * ! ************************************************************************* ! ! ++ ! ! FACILITY ! ! LIB ! ! ABSTRACT ! ! SYSTEM DUMP ANALYZER MESSAGE FILE DEFINITIONS ! ! ENVIRONMENT ! ! NATIVE MODE, USER MODE ! ! AUTHOR ! RICHARD BISHOP MARCH 1997 ! BASED ON ORIGINAL: ! MIKE RHODES JUNE 1981 ! SEE [SDA]EVAX_SDAMSG.MSG FOR PRIOR AUDIT TRAIL. ! ! MODIFIED BY ! ! X-39 RAB RICHARD A. BISHOP 15-OCT-2008 ! ADD TOOFRAGMENTED (DUMP FILE TOO FRAGMENTED). IT ! REPLACES HEADEXT WHICH IS NO LONGER NEEDED. ! ! X-38 RAB RICHARD A. BISHOP 22-MAY-2008 ! TWEAK TEXT OF NOTSAVED, MAKE DUPLICATE A WARNING ! INSTEAD OF INFO, ADD PROCNOACC FOR FILE-ID/UNWIND ! DATA COLLECTION ! ! X-37 RAB RICHARD A. BISHOP 26-MAR-2008 ! ADD SEVERAL NEW MESSAGES FOR PARTIAL DUMP COPIES ! (AND THEREFORE SDA OPENING MULTIPLE INPUT FILES AT ! THE SAME TIME) ! ! X-36 RAB RICHARD A. BISHOP 16-MAR-2007 ! ADD NOLMBSFOUND FOR PARTIAL DUMP COPIES AND BADCPU ! FOR SET|SHOW CPU/NEXT ! ! X-35 RAB RICHARD A. BISHOP 23-MAR-2006 ! ADD ZEROSYM FOR CORRUPTED SYMBOL VECTOR ENTRIES ! ! X-34 RAB RICHARD A. BISHOP 03-FEB-2006 ! ADD NOTACOLL FOR SHOW DUMP/COLLECTION DRILL-DOWN ! ! X-33 RAB RICHARD A. BISHOP 27-OCT-2005 ! ADD NEW MESSAGES FOR THE SEPARATE COLLECTION FILE, ! TWEAK A COUPLE OF OTHERS ! ! X-32 RAB RICHARD A. BISHOP 29-SEP-2005 ! ADD SPLNOTFOUND, MORE CORRECT THAN NOSPLOWNED IF ! /OWNED NOT SPECIFIED. ! ! X-31 RAB RICHARD A. BISHOP 10-MAY-2005 ! ANOTHER COLLECTION MESSAGE...NONEWCOLLECT...OUTPUT ! IF A COLLECT COMMAND IS DONE WHEN THERE'S ALREADY ! A COLLECTION IN THE DUMP BEING ANALYZED. ! ! X-30 RAB RICHARD A. BISHOP 11-MAR-2005 ! ADD A COUPLE MORE COLLECTION MESSAGES ! ! X-29 RAB RICHARD A. BISHOP 10-FEB-2005 ! ADD VARIOUS NEW MESSAGES FOR FILE AND/OR UNWIND ! DATA COLLECTIONS ! ! X-28 RAB RICHARD A. BISHOP 04-NOV-2004 ! CHANGE "spin lock" TO "spinlock" IN BADSPLNAME AND ! NOSPLOWNED ! ! X-27 RAB RICHARD A. BISHOP 08-OCT-2004 ! CHANGE PDRANGE_INVALID TO FDPDRANGE_INVAL TO REFLECT ! FUNCTION DESCRIPTORS ON IA64. ! ! X-26 RAB RICHARD A. BISHOP 23-AUG-2004 ! INITIAL CPU NAMESPACE CHANGES ! ! X-25 RAB RICHARD A. BISHOP 26-FEB-2004 ! TWEAK TEXT OF BADHWM ! ! X-24 RAB RICHARD A. BISHOP 09-OCT-2003 ! CHANGE LOSTPROCESS TEXT ! ! X-23 RAB RICHARD A. BISHOP 01-MAY-2003 ! CHANGE IT TO NOTI64DUMP ! ! X-22 RAB RICHARD A. BISHOP 06-DEC-2002 ! ADD NOTIA64DUMP ! ! X-21 RAB RICHARD A. BISHOP 14-NOV-2001 ! ADD LOSTPROCESS WARNING FOR WHEN CURRENTLY SET ! PROCESS GOES AWAY. ! ! X-20 RAB RICHARD A. BISHOP 31-OCT-2001 ! ADD WRONGCPU WARNING FOR WHEN A SET CPU DOESN'T END ! UP AT THE RIGHT CPU. ! ! X-19 RAB RICHARD A. BISHOP 09-AUG-2001 ! ADD NEW MESSAGES FOR SHADOW SET PROCESSING ! ! X-18 RAB RICHARD A. BISHOP 28-SEP-2000 ! CHANGE TEXT OF NOSTATS - NOW ONLY FOR LACK OF RING BUFFER ! ! X-17 RAB RICHARD A. BISHOP 13-SEP-2000 ! CHANGE NOSUCHPOOL FROM !AC TO !AZ FOR POOL TYPE ! ! X-16 RAB RICHARD A. BISHOP 30-MAR-2000 ! ADD NOPRCDMP AND NODEBUG ! ! X-15 RAB RICHARD A. BISHOP 21-FEB-2000 ! ADD BADHWM AND NOHWMCHECK ! ! X-14 RAB RICHARD A. BISHOP 18-FEB-2000 ! REINSTATE SHOW POOL/TYPE=UNKNOWN ! ! X-13 RAB RICHARD A. BISHOP 28-JAN-2000 ! ADD REGNOTACC FOR PROCESSOR REGISTERS THAT AREN'T ON ! ALL PLATFORMS. ! ! X-12 RAB RICHARD A. BISHOP 14-DEC-1999 ! ADD EXCLUDED DATA MESSAGE FOR PROCESS DUMPS ! ! X-11 RAB RICHARD A. BISHOP 17-DEC-1998 ! ADD NOTATQE FOR SHOW TQE AND NOTAUCB FOR THE EXTENSION ! ROUTINE SDA$GET_DEVICE_NAME. ! ! X-10 RAB RICHARD A. BISHOP 11-JUN-1998 ! ADD NOIOMEMMAP FOR WHEN SHOW PAGE/INVALID_PFN IS ! USED ON A SYSTEM THAT CAN'T SUPPORT IT. ! ! X-9 RAB RICHARD A. BISHOP 8-JUN-1998 ! ADD CPUNOTAVAIL & PROCNOTAVAIL, TO BE OUTPUT WHEN ! A SET CPU OR SET PROCESS (EXPLICIT OR IMPLICIT) IS ! ENTERED AND SDA HAS BEEN INVOKED WITHIN SCD/SDD, ! WHERE SUCH SWITCHING IS NOT CURRENTLY POSSIBLE. ! ! X-8 RAB RICHARD A. BISHOP 12-MAY-1998 ! MAKE ADDRESSES IN UNALIGNED AND NOTINIMAGE BE 64-BIT. ! ADD FOUR MORE GALAXY MESSAGES (NOTNODEB, NODEBNOTFND, ! NOTGCTTYPE, NOTGCTNODE) ! ! X-7 RAB RICHARD A. BISHOP 29-APR-1998 ! REDO PREVIOUS. X-5 CHECKED BACK IN BY MISTAKE. ! ! X-6 RAB RICHARD A. BISHOP 23-APR-1998 ! ANOTHER GALAXY MESSAGE - NOGCT ! ! X-5 RAB RICHARD A. BISHOP 9-APR-1998 ! ANOTHER GALAXY MESSAGE - NOGMDB ! ! X-4 RAB RICHARD A. BISHOP 15-JAN-1998 ! MORE GALAXY MESSAGES ! ! X-3 RAB RICHARD A. BISHOP 18-DEC-1997 ! ADD FIRST CROP OF GALAXY-RELATED MESSAGES FOR SHARED ! MEMORY DUMPS AND FOR THE NEW SHOW SHM_CPP COMMAND ! ! X-2 RAB RICHARD A. BISHOP 24-MAR-1997 ! MERGE IN RMS AND TPPSDA MESSAGES. ENSURE ALL MESSAGES ! HAVE TEXT ! ! X-1 RAB RICHARD A. BISHOP 20-MAR-1997 ! INITIAL VERSION ! ! -- literal SDA$_FACILITY = 244; ! ! BEGIN SYMBOL DEFINITIONS... ! ! NOTE: PLEASE ADD ALL NEW MESSAGES AT THE END OF THIS FILE AND ! INSERT PLACEHOLDERS FOR ALL MESSAGES WHICH ARE REMOVED. ! THIS WILL PREVENT INCORRECT MESSAGES FROM BEING DISPLAYED ! WHEN USING OLD VERSIONS OF SDA TO ANALYZE CRASH DUMPS FROM ! PREVIOUS BASELEVELS. ! literal SDA$_SUCCESS = 16023561; ! NOTE: THIS IS AN INTERNALLY USED SIGNAL ! AND SHOULD NEVER BE OUTPUT literal SDA$_NORESOURC = 16023571; literal SDA$_NOLOCKS = 16023579; literal SDA$_NOPRLOCK = 16023587; literal SDA$_SHORTDUMP = 16023592; literal SDA$_NOREQ = 16023600; literal SDA$_BADGSD = 16023608; literal SDA$_NOLDRIMG = 16023616; literal SDA$_NOREAD = 16023624; literal SDA$_NOREADLDRIMG = 16023632; literal SDA$_INSKIPPED = 16023640; literal SDA$_SYNTAX = 16023648; literal SDA$_NOIMGRMS = 16023656; literal SDA$_NOTCOPIED = 16023664; ! ! NOTE: THE FOLLOWING WARNING MESSAGES ARE INTERNALLY SIGNALLED ! CONDITIONS AND SHOULD NEVER BE OUTPUT ! literal SDA$_BACKUP = 16023672; literal SDA$_EOF = 16023680; literal SDA$_EXITCMD = 16023688; literal SDA$_NOTVALID = 16023698; literal SDA$_DUMPEMPTY = 16023706; literal SDA$_BADSYM = 16023714; literal SDA$_NOTINPHYS = 16023722; literal SDA$_BADPROC = 16023730; literal SDA$_INVBLKTYP = 16023738; literal SDA$_NOSYMBOLS = 16023746; literal SDA$_NOACCESS = 16023754; literal SDA$_SPTNOTFND = 16023762; literal SDA$_NOINSTRAN = 16023770; literal SDA$_RMSTERM = 16023778; literal SDA$_LOCKIDZER = 16023786; literal SDA$_OUTOFRANG = 16023794; literal SDA$_NOLKB = 16023802; literal SDA$_INVRANGE = 16023810; literal SDA$_NOQUEUE = 16023818; literal SDA$_OUTSIDPT = 16023826; literal SDA$_PFNNOTMPD = 16023834; literal SDA$_BLKSNRLSD = 16023842; literal SDA$_EXPTOOLRG = 16023850; literal SDA$_ATTFAIL = 16023858; literal SDA$_SPWNFAIL = 16023866; literal SDA$_OPENIN = 16023876; literal SDA$_NOTPAGFIL = 16023882; literal SDA$_NOTFOUND = 16023888; literal SDA$_HDRERRS = 16023896; literal SDA$_MEMERRS = 16023904; literal SDA$_OBSOLETE_2 = 16023912; literal SDA$_DUMPERRS = 16023920; literal SDA$_SCSNODNFND = 16023928; literal SDA$_CPUNOTVLD = 16023938; literal SDA$_CMDNOTVLD = 16023946; literal SDA$_NOBUGCHK = 16023954; literal SDA$_BADSPLNAME = 16023962; literal SDA$_BADSPLINDEX = 16023970; literal SDA$_NOTSPLADDR = 16023978; literal SDA$_DUMPINCOMPL = 16023988; literal SDA$_INSUFFMEM = 16023996; literal SDA$_INCDUMPFORM = 16024004; literal SDA$_NOREQSYM = 16024012; literal SDA$_READSYM = 16024019; literal SDA$_CPUIDLE = 16024027; literal SDA$_SYMFILENOTSTB = 16024035; literal SDA$_NOSPLOWNED = 16024043; literal SDA$_FMTACLERR = 16024048; literal SDA$_BDBLNKBRK = 16024056; literal SDA$_NOITMTRM = 16024064; literal SDA$_FAOERR = 16024072; literal SDA$_INVLDPEPORT = 16024080; literal SDA$_NOTSAVED = 16024088; literal SDA$_INCOMPL = 16024096; literal SDA$_MEMNOTSVD = 16024104; literal SDA$_INCCTXT = 16024112; literal SDA$_INVLDADR = 16024122; literal SDA$_RESTOOBIG = 16024130; literal SDA$_NORSBNAM = 16024138; literal SDA$_NOLKBNAM = 16024146; literal SDA$_REGNOTVLD = 16024154; literal SDA$_NOMCHKFRAME = 16024163; literal SDA$_BADCPUTYPE = 16024170; literal SDA$_BADMCHKFRAMEREV = 16024178; literal SDA$_INVSUBTYP = 16024186; literal SDA$_MINVERMIS = 16024192; literal SDA$_IMGNOTACT = 16024200; literal SDA$_VERSMISM = 16024210; literal SDA$_FORMATDS = 16024219; literal SDA$_NOSUCHTP = 16024226; literal SDA$_CNFLTARGS = 16024234; literal SDA$_SUPPNOTINS = 16024242; literal SDA$_NOSTATS = 16024250; ! ! ! NOTE : THE FOLLOWING MESSAGE AREA IS RESERVED FOR THE DEFINITION OF ! MESSAGES DEFINED WITHIN THE TP SERVICES SDA SUPPORT SHAREABLE IMAGE. ! ! CURRENTLY THE PRECEEDING MESSAGES NUMBER SOME 100 IN TOTAL, HENCE THE ! MESSAGES FOR TP SERVICES SDA SUPPORT HAVE BEEN BASED AT 100 WITH SPACE ! FOR SOME 50 ERROR/WARNING/INFORMATION AND SUCCESS MESSAGES. ! literal SDA$_NOSYSTPS = 16024352; literal SDA$_NOPROCTPS = 16024360; literal SDA$_NOSYSCLF = 16024368; literal SDA$_NOSYSIPC = 16024376; literal SDA$_NOTIDSTRUC = 16024384; literal SDA$_TPSFAOERR = 16024392; literal SDA$_TPSACLERR = 16024400; literal SDA$_TPSNOTRM = 16024408; literal SDA$_TPSUTCERR = 16024416; literal SDA$_TPSTERM = 16024514; literal SDA$_TPSINVBLK = 16024522; ! MESSAGES FROM LIB$ASCII_TO_UID, LIB$COMPARE_UID, LIB$UID_TO_ASCII ! literal SDA$_UNSUPVER = 16024530; ! MESSAGE FROM LIB$ASCII_TO_UID ! literal SDA$_BADFORMAT = 16024538; ! FORCE A BUFFER ZONE ! ! NOTE: THE FOLLOWING MESSAGE AREA IS RESERVED FOR THE DEFINITIONS OF ! MESSAGES DEFINED WITHING THE RMS SDA SUPPORT SHAREABLE IMAGE. ! ! CURRENTLY THE PRECEEDING MESSAGES NUMBER SOME 150 IN TOTAL, HENCE ! THE MESSAGES FOR RMS SDA SUPPORT HAVE BEEN BASED AT 150 WITH SPACE ! FOR SOME 50 ERROR/WARNING/INFORMATION AND SUCCESS MESSAGES. ! literal SDA$_NORMSSHARE = 16024752; ! FORCE A BUFFER ZONE ! ! ! *************************** ! ALL NEW SDA MESSAGES SHOULD BE ADDED FOLLOWING THE ".BASE 200" DIRECTIVE. ! *************************** ! ! literal SDA$_EMPTYNEST = 16025152; literal SDA$_OBSOLETE_1 = 16025160; literal SDA$_UNALIGNED = 16025168; literal SDA$_STACKNTFND = 16025176; literal SDA$_INVSTACK = 16025184; literal SDA$_IDENTMISMATCH = 16025192; literal SDA$_FDPDRANGE_INVAL = 16025202; literal SDA$_OBSOLETE_3 = 16025210; literal SDA$_NOSYMVECT = 16025218; literal SDA$_NOPAGESIZE = 16025226; literal SDA$_NOTINIMAGE = 16025234; literal SDA$_HWRPB_NF = 16025242; literal SDA$_RD_SYSIMG_ERR = 16025250; literal SDA$_RD_IMAGE_ERR = 16025258; literal SDA$_IMAGENF = 16025266; literal SDA$_INCONPOOL = 16025274; literal SDA$_NOCLUSTER = 16025282; literal SDA$_BADPAGE = 16025288; literal SDA$_INVALID_HWRPB = 16025296; literal SDA$_CTRLC_ACK = 16025307; literal SDA$_NOIMSEM = 16025315; literal SDA$_INVREGID = 16025320; ! TEMPORARY MESSAGE literal SDA$_GLOBNOTIMPL = 16025330; literal SDA$_FPNOTFOUND = 16025338; literal SDA$_NOLOCKID = 16025346; literal SDA$_NOFILENAME = 16025352; literal SDA$_REGNOTAVAIL = 16025360; literal SDA$_NOCBMAP = 16025372; literal SDA$_ALRDYCOMP = 16025379; literal SDA$_ALRDYDCMP = 16025387; literal SDA$_DEFLATE = 16025395; literal SDA$_INFLATE = 16025403; literal SDA$_COPYFAIL = 16025408; literal SDA$_OPENOUT = 16025416; literal SDA$_HWRPB_SUSPECT = 16025424; literal SDA$_NOSAVEDUMP = 16025434; literal SDA$_NOTALPHADUMP = 16025442; literal SDA$_BADOVER4GB = 16025448; literal SDA$_BADPSBARRAY = 16025456; literal SDA$_LINKTIMEMISM = 16025464; literal SDA$_SDALINKMISM = 16025472; literal SDA$_ERRLOGSONLY = 16025482; literal SDA$_BADCHKSUM = 16025488; literal SDA$_PROCNOTDUMPED = 16025496; literal SDA$_PROCPARTDUMPED = 16025504; literal SDA$_NOSUCHPOOL = 16025512; literal SDA$_NOPOOLTYPE = 16025522; literal SDA$_MISSINGQUALS = 16025530; literal SDA$_MEMNOTACC = 16025538; literal SDA$_CNFLTQUALS = 16025546; literal SDA$_NOCHANGE = 16025554; literal SDA$_NOMATCH = 16025562; literal SDA$_NOTANLMB = 16025570; literal SDA$_TOOMANYERLBUF = 16025576; literal SDA$_ERLBUFTOOBIG = 16025584; literal SDA$_DUMPMOD = 16025592; literal SDA$_CBLOCKMAPTOOBIG = 16025600; literal SDA$_PHYNOTIMPL = 16025610; literal SDA$_NOMODIFY = 16025618; literal SDA$_SHORTERLDUMP = 16025624; literal SDA$_STUBNOCOMP = 16025632; literal SDA$_DUMPBLKSREL = 16025642; literal SDA$_DMPRELEXIT = 16025651; literal SDA$_VECNOTINIT = 16025658; literal SDA$_SHMDUMP = 16025666; literal SDA$_NOTSHMDUMP = 16025674; literal SDA$_NOTSHMCPP = 16025682; literal SDA$_NOSHMCPP = 16025690; literal SDA$_NOTSHMREG = 16025698; literal SDA$_NOSHMREG = 16025706; literal SDA$_SHMREGNOTFND = 16025714; literal SDA$_NOGMDB = 16025722; literal SDA$_NOGCT = 16025730; literal SDA$_NOTNODEB = 16025738; literal SDA$_NODEBNOTFND = 16025746; literal SDA$_NOTGCTTYPE = 16025754; literal SDA$_NOTGCTNODE = 16025762; literal SDA$_CPUNOTAVAIL = 16025770; literal SDA$_PROCNOTAVAIL = 16025778; literal SDA$_NOIOMEMMAP = 16025786; literal SDA$_NOTATQE = 16025794; literal SDA$_NOTAUCB = 16025802; literal SDA$_REGNOTACC = 16025810; literal SDA$_EXCLDATA = 16025816; literal SDA$_BADHWM = 16025824; literal SDA$_NOHWMCHECK = 16025832; literal SDA$_NOPRCDMP = 16025842; literal SDA$_NODEBUG = 16025850; literal SDA$_NOTMEMBER = 16025858; literal SDA$_SHADFAIL = 16025866; literal SDA$_NEEDPHYIO = 16025874; literal SDA$_NOPHYIO = 16025883; literal SDA$_SINGLEMEM = 16025891; literal SDA$_TOOFRAGMENTED = 16025899; literal SDA$_USEMASTER = 16025907; literal SDA$_NOTSYSERLDMP = 16025912; literal SDA$_WRONGCPU = 16025920; literal SDA$_LOSTPROCESS = 16025928; literal SDA$_NOTI64DUMP = 16025938; literal SDA$_NOCOLLECT = 16025946; literal SDA$_BADELF = 16025954; literal SDA$_STUBNOCOLL = 16025960; literal SDA$_DISKNOACC = 16025968; literal SDA$_FILENOACC = 16025976; literal SDA$_COLLECTING = 16025987; literal SDA$_COLLECTION = 16025995; literal SDA$_NONETCOLLECT = 16026003; literal SDA$_NOTCOLLECTED = 16026011; literal SDA$_NONEWCOLLECT = 16026019; literal SDA$_SPLNOTFOUND = 16026027; literal SDA$_WRONGCRASH = 16026035; literal SDA$_COLLECTONLY = 16026042; literal SDA$_NOCOLLECTFILE = 16026050; literal SDA$_BADCOLLECT = 16026056; literal SDA$_NOTACOLL = 16026066; literal SDA$_ZEROSYM = 16026072; literal SDA$_NOLMBSFOUND = 16026080; literal SDA$_BADCPU = 16026090; literal SDA$_PARTIALDUMP = 16026098; literal SDA$_TOOMANYFILES = 16026106; literal SDA$_BADFILENUM = 16026114; literal SDA$_PRIMARYDUMP = 16026120; literal SDA$_OPENTWICE = 16026128; literal SDA$_NOTSAMECRASH = 16026136; literal SDA$_NOTSAMECOMP = 16026144; literal SDA$_UNEXPECTED = 16026152; literal SDA$_CORRUPT = 16026160; literal SDA$_LMBEMPTY = 16026168; literal SDA$_LMBMISSING = 16026176; literal SDA$_OPENED = 16026187; literal SDA$_DUPLICATE = 16026192; literal SDA$_PROCNOACC = 16026200; ! ! END SYMBOL DEFINITIONS...AND THIS MESSAGE FILE! ! ! ! ---- < End of module SDAMSG.R32 - 30-MAR-2010 16:38:52.03 > - ! ! This file was created by [LIB]VMS$DEFS_LIB.COM ! for the IA64 build. MACRO VMS$PFNBITS_32 = 0%; MACRO VMS$PFNBITS_64 = 1%; MACRO NMSP$64P = 1%; ! ! ---- < End of module VMS$DEFS.REQ - 30-MAR-2010 16:38:53.66 > - ! !Version: X-7 ! !**************************************************************************** !* Copyright 2002 Compaq Information Technologies Group, L.P. !* !* Compaq and the Compaq logo are trademarks of Compaq Information !* Technologies Group, L.P. in the U.S. and/or other countries. !* !* Confidential computer software. Valid license from Compaq required for !* possession, use or copying. Consistent with FAR 12.211 and 12.212, !* Commercial Computer Software, Computer Software Documentation, and !* Technical Data for Commercial Items are licensed to the U.S. Government !* under vendor's standard commercial license. !**************************************************************************** ! !++ ! FACILITY: ! ! VMSLIB -- BIGPAGE_MACROS_LIB.REQ ! ! ABSTRACT: ! ! The macros defined in this file are used by privileged applications ! to provide commonality in varying page size implementations. ! ! AUTHORS: ! ! Robert F. Hoffman ! ! CREATION DATE: 20 June 1990 ! ! MODIFICATION HISTORY: ! ! X-7 KLN3023 Karen L. Noel 25-Feb-2002 ! Remove $is_pt_space_va and $is_process_pte_va macros. ! No one is using them and I don't want to port them to ! IA64. ! ! X-6 Karen L. Noel KLN1396 24-Feb-1995 ! Add $is_shared_va and $is_private_va macros. ! ! X-5 Karen L. Noel KLN1322 20-Sep-1994 ! 64-Bit project: internal programming ! Add PT space macros. ! ! X-3,4 Karen L. Noel KLN1322 12-Sep-1994 ! Add PT_SPACE. ! ! X-2 Robert F. Hoffman RFH002 23-Apr-1991 ! Fix conditionalization on VAXPAGE/BIGPAGE ! ! X-1 Robert F. Hoffman RFH001 20-Jun-1990 ! Create module. !-- KEYWORDMACRO $EXTRACT_VPN (VA, VPN, VA_SPACE=SYSTEM, INDEPENDENT=NO, PT_SPACE=NO)= ! ! VA - source virtual address ! VPN - destination for VPN ! VA_SPACE - SYSTEM, P0, or P1, masks appropriate high bits ! INDEPENDENT - if YES, always do page-size independent code, even ! on a VAX ! PT_SPACE - If YES, uses PT space instead of SPT "window". ! **VA and VPN arguments are treated as quadwords** ! If NO, uses SPT "window", VA_SPACE must be SYSTEM. ! ! Extracts a VPN from a virtual address ! ! Remove the comments from the following code once the process page tables ! are removed from the PHD. ! !%IF NOT %IDENTICAL(va_space,SYSTEM) !%THEN ! %IF %IDENTICAL(pt_space,NO) %THEN ! %ERROR('Process PTEs only in PT space, must specify PT_SPACE = YES'); ! %FI !%FI ! NOT %IDENTICAL(va_space,SYSTEM) ! ! Also remove all further code which references process address space and ! pt_space = NO. ! %IF %IDENTICAL(pt_space,YES) %THEN %IF %BLISS(BLISS32) %THEN %ERROR('Specifying PT_SPACE = YES requires the Bliss-64 compiler'); %FI %IF %NULL(vpn) %THEN va = (.va AND (NOT .MMG$GQ_NON_VA_MASK)) ^ (-.MMG$GQ_BWP_WIDTH); %ELSE !%NULL(vpn) vpn = (.va AND (NOT .MMG$GQ_NON_VA_MASK)) ^ (-.MMG$GQ_BWP_WIDTH); %FI !%NULL(vpn) %FI !%IDENTICAL(pt_space,YES) %IF %IDENTICAL(pt_space,NO) %THEN %IF %IDENTICAL(INDEPENDENT,YES) %THEN %IF %NULL(vpn) %THEN %IF %IDENTICAL(VA_SPACE,SYSTEM) %THEN va = (.va AND (NOT VA$M_SYSTEM)) ^ .MMG$GL_VA_TO_VPN; %ELSE %IF %IDENTICAL(VA_SPACE,P1) OR %IDENTICAL(VA_SPACE,PROCESS) %THEN va = (.va AND (NOT VA$M_P1)) ^ .MMG$GL_VA_TO_VPN; %ELSE !%IDENTICAL(VA_SPACE,P1) va = .va ^ .MMG$GL_VA_TO_VPN; %FI %FI %ELSE !%NULL(vpn) %IF %IDENTICAL(VA_SPACE,SYSTEM) %THEN vpn = (.va AND (NOT VA$M_SYSTEM)) ^ .MMG$GL_VA_TO_VPN; %ELSE !%IDENTICAL(VA_SPACE,SYSTEM) %IF %IDENTICAL(VA_SPACE,P1) OR %IDENTICAL(VA_SPACE,PROCESS) %THEN vpn = (.va AND (NOT VA$M_P1)) ^ .MMG$GL_VA_TO_VPN; %ELSE !%IDENTICAL(VA_SPACE,P1) vpn = .va ^ .MMG$GL_VA_TO_VPN; %FI !%IDENTICAL(VA_SPACE,P1) %FI !%IDENTICAL(VA_SPACE,SYSTEM) %FI !%NULL(vpn) %ELSE !%IDENTICAL(INDEPENDENT,YES) BEGIN %IF VAXPAGE %THEN %IF %NULL(vpn) %THEN %IF %IDENTICAL(VA_SPACE,SYSTEM) %THEN va = (.va AND (NOT VA$M_SYSTEM)) ^ -VA$V_VPN; %ELSE %IF %IDENTICAL(VA_SPACE,P1) OR %IDENTICAL(VA_SPACE,PROCESS) %THEN va = (.va AND (NOT VA$M_P1)) ^ -VA$V_VPN; %ELSE va = .va ^ -VA$V_VPN; %FI %FI %ELSE !%NULL(vpn) %IF %IDENTICAL(VA_SPACE,SYSTEM) %THEN vpn = (.va AND (NOT VA$M_SYSTEM)) ^ -VA$V_VPN; %ELSE !%IDENTICAL(VA_SPACE,SYSTEM) %IF %IDENTICAL(VA_SPACE,P1) OR %IDENTICAL(VA_SPACE,PROCESS) %THEN vpn = (.va AND (NOT VA$M_P1)) ^ -VA$V_VPN; %ELSE !%IDENTICAL(VA_SPACE,P1) vpn = .va ^ -VA$V_VPN; %FI !%IDENTICAL(VA_SPACE,P1) %FI !%IDENTICAL(VA_SPACE,SYSTEM) %FI !%NULL(vpn) %FI !VAXPAGE %IF BIGPAGE %THEN %IF %NULL(vpn) %THEN %IF %IDENTICAL(VA_SPACE,SYSTEM) %THEN va = (.va AND (NOT VA$M_SYSTEM)) ^ .MMG$GL_VA_TO_VPN; %ELSE %IF %IDENTICAL(VA_SPACE,P1) OR %IDENTICAL(VA_SPACE,PROCESS) %THEN va = (.va AND (NOT VA$M_P1)) ^ .MMG$GL_VA_TO_VPN; %ELSE va = .va ^ .MMG$GL_VA_TO_VPN; %FI %FI %ELSE !%NULL(vpn) %IF %IDENTICAL(VA_SPACE,SYSTEM) %THEN vpn = (.va AND (NOT VA$M_SYSTEM)) ^ .MMG$GL_VA_TO_VPN; %ELSE !%IDENTICAL(VA_SPACE,SYSTEM) %IF %IDENTICAL(VA_SPACE,P1) OR %IDENTICAL(VA_SPACE,PROCESS) %THEN vpn = (.va AND (NOT VA$M_P1)) ^ .MMG$GL_VA_TO_VPN; %ELSE !%IDENTICAL(VA_SPACE,P1) vpn = .va ^ .MMG$GL_VA_TO_VPN; %FI !%IDENTICAL(VA_SPACE,P1) %FI !%IDENTICAL(VA_SPACE,SYSTEM) %FI !%NULL(vpn) %FI !BIGPAGE END %FI !%IDENTICAL(independent) %FI !%IDENTICAL(pt_space,NO) %; KEYWORDMACRO $EXTRACT_PTE_OFFSET (VA, PTE_OFFSET, VA_SPACE=SYSTEM, INDEPENDENT=NO, PT_SPACE=NO)= ! ! VA - source virtual address ! PTE_OFFSET - destination for PTE_OFFSET ! VA_SPACE - SYSTEM, P0, or P1, masks appropriate high bits ! INDEPENDENT - if YES, always do page-size independent code, even ! on a VAX ! PT_SPACE - If YES, uses PT space instead of SPT "window". ! **VA and VPN arguments are treated as quadwords** ! If NO, uses SPT "window", VA_SPACE must be SYSTEM. ! ! Converts a virtual address into an offset into a Page Table. ! ! Remove the comments from the following code once the process page tables ! are removed from the PHD. ! !%IF NOT %IDENTICAL(va_space,SYSTEM) !%THEN ! %IF %IDENTICAL(pt_space,NO) %THEN ! %ERROR('Process PTEs only in PT space, must specify PT_SPACE = YES'); ! %FI !%FI ! NOT %IDENTICAL(va_space,SYSTEM) ! ! Also remove all further code which references process address space and ! pt_space = NO. ! %IF %IDENTICAL(pt_space,YES) %THEN %IF %BLISS(BLISS32) %THEN %ERROR('Specifying PT_SPACE = YES requires the Bliss-64 compiler'); %FI %IF %NULL(pte_offset) %THEN va = (.va AND (NOT .MMG$GQ_NON_VA_MASK)) ^ (-.MMG$GQ_LEVEL_WIDTH); va = .va AND NOT(PTE$C_BYTES_PER_PTE-1); %ELSE !%NULL(pte_offset) pte_offset = (.va AND (NOT .MMG$GQ_NON_VA_MASK)) ^ (-.MMG$GQ_LEVEL_WIDTH); pte_offset = .pte_offset AND NOT(PTE$C_BYTES_PER_PTE-1); %FI !%NULL(pte_offset) %FI !%IDENTICAL(pt_space,YES) %IF %IDENTICAL(pt_space,NO) %THEN %IF %IDENTICAL(independent,YES) %THEN %IF %NULL(PTE_offset) %THEN %IF %IDENTICAL(va_space,SYSTEM) %THEN va = (.va AND (NOT VA$M_SYSTEM)) ^ .MMG$GL_VA_TO_PTE_OFFSET; %ELSE %IF %IDENTICAL(va_space,P1) OR %IDENTICAL(VA_SPACE,PROCESS) %THEN va = (.va AND (NOT VA$M_P1)) ^ .MMG$GL_VA_TO_PTE_OFFSET; %ELSE va = .va ^ .MMG$GL_VA_TO_PTE_OFFSET; %FI %FI %ELSE !%NULL(PTE_offset) %IF %IDENTICAL(va_space,SYSTEM) %THEN PTE_offset = (.va AND (NOT VA$M_SYSTEM)) ^ .MMG$GL_VA_TO_PTE_OFFSET; %ELSE %IF %IDENTICAL(va_space,P1) OR %IDENTICAL(VA_SPACE,PROCESS) %THEN va = (.va AND (NOT VA$M_P1)) ^ .MMG$GL_VA_TO_PTE_OFFSET; %ELSE !%IDENTICAL(va_space,P1) va = .va ^ .MMG$GL_VA_TO_PTE_OFFSET; %FI !%IDENTICAL(va_space,P1) %FI !%IDENTICAL(va_space,SYSTEM) %FI !%NULL(PTE_offset) %ELSE !%IDENTICAL(independent) BEGIN %IF VAXPAGE %THEN %IF %NULL(PTE_offset) %THEN %IF %IDENTICAL(va_space,SYSTEM) %THEN va = (.va AND (NOT VA$M_SYSTEM)) ^ -(VA$V_VPN-2); %ELSE %IF %IDENTICAL(va_space,P1) OR %IDENTICAL(VA_SPACE,PROCESS) %THEN va = (.va AND (NOT VA$M_P1)) ^ -(VA$V_VPN-2); %ELSE va = .va ^ -(VA$V_VPN-2); %FI %FI %ELSE !%NULL(PTE_offset) %IF %IDENTICAL(va_space,SYSTEM) %THEN PTE_offset = (.va AND (NOT VA$M_SYSTEM)) ^ -(VA$V_VPN-2); %ELSE !%IDENTICAL(va_space,SYSTEM) %IF %IDENTICAL(va_space,P1) OR %IDENTICAL(VA_SPACE,PROCESS) %THEN PTE_offset = (.va AND (NOT VA$M_P1)) ^ -(VA$V_VPN-2); %ELSE !%IDENTICAL(va_space,P1) PTE_offset = .va ^ -(VA$V_VPN-2); %FI !%IDENTICAL(va_space,P1) %FI !%IDENTICAL(va_space,SYSTEM) %FI !%NULL(PTE_offset) %FI !VAXPAGE %IF BIGPAGE %THEN %IF %NULL(PTE_offset) %THEN %IF %IDENTICAL(va_space,SYSTEM) %THEN va = (.va AND (NOT VA$M_SYSTEM)) ^ .MMG$GL_VA_TO_PTE_OFFSET; %ELSE %IF %IDENTICAL(va_space,P1) OR %IDENTICAL(VA_SPACE,PROCESS) %THEN va = (.va AND (NOT VA$M_P1)) ^ .MMG$GL_VA_TO_PTE_OFFSET; %ELSE va = .va ^ .MMG$GL_VA_TO_PTE_OFFSET; %FI %FI %ELSE !%NULL(PTE_offset) %IF %IDENTICAL(va_space,SYSTEM) %THEN PTE_offset = (.va AND (NOT VA$M_SYSTEM)) ^ .MMG$GL_VA_TO_PTE_OFFSET; %ELSE !%IDENTICAL(va_space,SYSTEM) %IF %IDENTICAL(va_space,P1) OR %IDENTICAL(VA_SPACE,PROCESS) %THEN PTE_offset = (.va AND (NOT VA$M_P1)) ^ .MMG$GL_VA_TO_PTE_OFFSET; %ELSE !%IDENTICAL(va_space,P1) PTE_offset = .va ^ .MMG$GL_VA_TO_PTE_OFFSET; %FI !%IDENTICAL(va_space,P1) %FI !%IDENTICAL(va_space,SYSTEM) %FI !%NULL(PTE_offset) %FI !BIGPAGE END %FI !%IDENTICAL(independent) %FI !%IDENTICAL(pt_space,NO) %; KEYWORDMACRO $MAKE_VA (VPN, VA, VA_SPACE=SYSTEM, INDEPENDENT=NO, PT_SPACE=NO)= ! ! VPN - source Virtual Page Number ! VA - destination Virtual Address ! VA_SPACE - SYSTEM, P0, or P1, sets appropriate high bits ! INDEPENDENT - if YES, always do page-size independent code, even ! on a VAX ! PT_SPACE - If YES, uses PT space instead of SPT "window". ! **VA and VPN arguments are treated as quadwords** ! If NO, uses SPT "window", VA_SPACE must be SYSTEM. ! ! Converts a VPN to the virtual address of the first byte in that ! page. ! ! Remove the comments from the following code once the process page tables ! are removed from the PHD. ! !%IF NOT %IDENTICAL(va_space,SYSTEM) !%THEN ! %IF %IDENTICAL(pt_space,NO) %THEN ! %ERROR('Process PTEs only in PT space, must specify PT_SPACE = YES'); ! %FI !%FI ! NOT %IDENTICAL(va_space,SYSTEM) ! ! Also remove all further code which references process address space and ! pt_space = NO. ! %IF %IDENTICAL(pt_space,YES) %THEN %IF %BLISS(BLISS32) %THEN %ERROR('Specifying PT_SPACE = YES requires the Bliss-64 compiler'); %FI BEGIN LOCAL non_sext_va: QUAD UNSIGNED, sext_bit: QUAD UNSIGNED; non_sext_va = (.vpn ^ .MMG$GQ_BWP_WIDTH); sext_bit = 1 ^ (.MMG$GQ_VA_BITS-1); IF ((.non_sext_va AND .sext_bit) EQL .sext_bit) THEN %IF %NULL(va) %THEN vpn = .non_sext_va OR .MMG$GQ_NON_VA_MASK %ELSE va = .non_sext_va OR .MMG$GQ_NON_VA_MASK %FI !%NULL(va) ELSE %IF %NULL(va) %THEN vpn = .non_sext_va; %ELSE va = .non_sext_va; %FI end; %FI !%IDENTICAL(pt_space,YES) %IF %IDENTICAL(pt_space,NO) %THEN %IF %IDENTICAL(independent,YES) %THEN %IF %NULL(va) %THEN %IF %IDENTICAL(va_space,SYSTEM) %THEN vpn = (.vpn ^ .MMG$GL_VPN_TO_VA) OR VA$M_SYSTEM; %ELSE %IF %IDENTICAL(va_space,P1) %THEN vpn = (.vpn ^ .MMG$GL_VPN_TO_VA) OR VA$M_P1; %ELSE vpn = .vpn ^ .MMG$GL_VPN_TO_VA; %FI %FI %ELSE !%NULL(va) %IF %IDENTICAL(va_space,SYSTEM) %THEN va = (.vpn ^ .MMG$GL_VPN_TO_VA) OR VA$M_SYSTEM; %ELSE %IF %IDENTICAL(va_space,P1) %THEN va = (.vpn ^ .MMG$GL_VPN_TO_VA) OR VA$M_P1; %ELSE va = .vpn ^ .MMG$GL_VPN_TO_VA; %FI %FI %FI !%NULL(va) %ELSE !%IDENTICAL(independent) BEGIN %IF VAXPAGE %THEN %IF %NULL(va) %THEN %IF %IDENTICAL(va_space,SYSTEM) %THEN vpn = (.vpn ^ VA$V_VPN) OR VA$M_SYSTEM; %ELSE %IF %IDENTICAL(va_space,P1) %THEN vpn = (.vpn ^ VA$V_VPN) OR VA$M_P1; %ELSE vpn = .vpn ^ VA$V_VPN; %FI %FI %ELSE !%NULL(va) %IF %IDENTICAL(va_space,SYSTEM) %THEN va = (.vpn ^ VA$V_VPN) OR VA$M_SYSTEM; %ELSE %IF %IDENTICAL(va_space,P1) %THEN va = (.vpn ^ VA$V_VPN) OR VA$M_P1; %ELSE va = .vpn ^ VA$V_VPN; %FI %FI %FI !%NULL(va) %FI !VAXPAGE %IF BIGPAGE %THEN %IF %NULL(va) %THEN %IF %IDENTICAL(va_space,SYSTEM) %THEN vpn = (.vpn ^ .MMG$GL_VPN_TO_VA) OR VA$M_SYSTEM; %ELSE %IF %IDENTICAL(va_space,P1) %THEN vpn = (.vpn ^ .MMG$GL_VPN_TO_VA) OR VA$M_P1; %ELSE vpn = .vpn ^ .MMG$GL_VPN_TO_VA; %FI %FI %ELSE !%NULL(va) %IF %IDENTICAL(va_space,SYSTEM) %THEN va = (.vpn ^ .MMG$GL_VPN_TO_VA) OR VA$M_SYSTEM; %ELSE %IF %IDENTICAL(va_space,P1) %THEN va = (.vpn ^ .MMG$GL_VPN_TO_VA) OR VA$M_P1; %ELSE va = .vpn ^ .MMG$GL_VPN_TO_VA; %FI %FI %FI !%NULL(va) %FI !BIGPAGE END %FI !%IDENTICAL(independent) %FI !%IDENTICAL(pt_space,NO); %; KEYWORDMACRO $IS_SYSTEM_PTE_VA (VA,SHARED_VA_PTES,SYSTEM_BASE)= ! ! Returns 1 if VA is an system PT space address. ! %IF %NULL (shared_va_ptes) %THEN ((va GEQU .mmg$gq_shared_va_ptes) %ELSE ((va GEQU shared_va_ptes) %FI AND %IF %NULL (system_base) %THEN (va LSSU .mmg$gq_system_virtual_base)) %ELSE (va LSSU system_base)) %FI %; KEYWORDMACRO $IS_SHARED_VA (VA,SHARED_VA_PTES)= ! ! Returns 1 if VA is a shared address. ! %IF %NULL (shared_va_ptes) %THEN (va GEQU .mmg$gq_shared_va_ptes) %ELSE (va GEQU shared_va_ptes) %FI %; KEYWORDMACRO $IS_PRIVATE_VA (VA,SHARED_VA_PTES)= ! ! Returns 1 if VA is a private address. ! %IF %NULL (shared_va_ptes) %THEN (va LSSU .mmg$gq_shared_va_ptes) %ELSE (va LSSU shared_va_ptes) %FI %; ! ! ---- < End of module BIGPAGE_MACROS_LIB.REQ - 30-MAR-2010 16:38:55.07 > - ! ! Ident X-50 ! ************************************************************************* ! * * ! * Copyright 1990 Compaq Computer Corporation * ! * * ! * COMPAQ Registered in U.S. Patent and Trademark Office. * ! * * ! * Confidential computer software. Valid license from Compaq or * ! * authorized sublicensor required for possession, use or copying. * ! * Consistent with FAR 12.211 and 12.212, Commercial Computer Software, * ! * Computer Software Documentation, and Technical Data for Commercial * ! * Items are licensed to the U.S. Government under vendor's standard * ! * commercial license. * ! * * ! * Compaq shall not be liable for technical or editorial errors or * ! * omissions contained herein. The information in this document is * ! * subject to change without notice. * ! * * ! ************************************************************************* !++ ! FACILITY: SYSTEM, BUGCHECK ! ! ABSTRACT: ! This include file contains the macros AND BUGCHECK information ! necessary to create the BUGCHECK codes, a buffer of BUGCHECK ! messages and a lookup table (to match a code to the message). ! ! To define the BUGCHECK codes, table or messages in a Bliss source ! module, use the following macro calls. ! ! GENBUGCHECKMSGS (CODES) ! GENBUGCHECKMSGS (TABLE, ) ! GENBUGCHECKMSGS (MESSAGES, ) ! ! The table and messages are defined by the BUGCHECK.B32 module in ! the SYS facility (in EXCEPTIONS.EXE) ! ! New BUGCHECK codes/messages should be appended at the end of the ! file before the PLACE_HOLDER. The format is: ! ! GENINFO (, %ASCII'') ! !-- ! ! MODIFIED BY: ! ! X-50 RAB0157 Robert A. Brooks 15-Mar-2006 ! Add SHDWREQALLOC for shadowed system disks where no ! no allocation class is set for the specified boot device. ! Prior to this addition, MOUNT would return the error ! code MOUN$_SHDWREQALLOC, which would ultimately ! result in a PROCGONE bug check. This makes the meaning ! of the bug check a bit more obvious. ! ! X-49 WBF Burns Fisher 25-Feb-2004 ! Add AST_INCONSTATE and IMSEM_INCONSTATE for AST and SWIS ! errors. ! ! X-48 JRK396 Jim Kauffman 22-Oct-2003 ! Add CPUINT_INIT for Itanium INIT handler ! ! X-47 JEN2049 Jeff E. Nelson 1-Aug-2003 ! Add DBGCPUEXIT for XDELTA. When one processor ! crashes with DEBUGCRASH, others will crash with ! DBGCPUEXIT. ! ! X-46 DAG Doug Gordon 4-Apr-2003 ! Add KP_INCONSTATE for consistency checks with the ! KP services. ! ! X-45 DEE0817 David E. Eiche 16-Mar-2003 ! Add ACPI_FATAL for fatal ACPI errors in machine ! language byte code stream. ! ! X-44 WBF Burns Fisher 19-Dec-2002 ! Add SWIS_INCONSTATE for SWIS errors. ! ! X-43 RAB Richard A. Bishop 12-Nov-2002 ! Add BUG$_OCLAFAIL for Marvel On-Chip Logic Analyzer ! support routines ! ! X-42 PJB0025 Paul Benoit 28-Oct-2002 ! Add BUG$_FPSWAERROR for IA64 FP SWA errors. These should ! not occur if the FP SWA is driver correctly installed and ! loaded and the FP SWA handler is passed the correct parameters. ! ! X-41 MAS0749 Mark A. Stiles 31-May-2002 ! Add SCSERROR bugcheck for generic SCS layer errors ! or SCS port errors. Much more reasonable than VAXPORT! ! ! X-40 MAS0739 Mark A. Stiles 11-Apr-2002 ! Remove "Digital" from old bugcheck codes which ! are reserved for independent software vendor or ! layered product use. Add TESTING123 as a generic ! bugcheck to be used during code development and testing. ! ! X-39 MAS0677 Mark A. Stiles 24-Aug-2001 ! Add SEPPUCLU for semi-synchronous, semi-sympathetic ! cluster crashes when the stuff hits the fan. ! Update copyright notice. ! ! X-38 GP Genady Perchenko 23-Jun-2000 ! Add MTXRELERR for mutex release error handling ! ! X-37 RAB Richard A. Bishop 06-Apr-2000 ! Add GLXRMTMCHK for remote error handling ! ! X-36 EMW0195 Elinor M. Woods 25-Aug-1999 ! BKT-LOCK enhancements: Add RMS_INCONSTATE system ! bugcheck code. ! ! X-35 JRK390 Jim Kauffman 9-Jul-1998 ! Add GLXCRASH for Galaxy BUGCHK requested from another ! instance ! ! X-34 CEG Clair Grant 02-Apr-1998 ! Add GLXSHUTSHMEM for 'Shared memory still mapped during ! system shutdown' ! ! X-33 GHJ Gregory H. Jordan 24-Feb-1998 ! Add SMCIPORT as a bugcheck for the Shared Memory Cluster ! interconnect. ! ! X-32 PAJ0964 Paul A. Jacobi 24-Feb-1998 ! Add POWEROFF bugcheck code. ! ! X-31 KLN2052 Karen L. Noel 13-Feb-1998 ! Add INVPFN for PTE/PFN checking routines. ! ! X-30 PKH-G006 Paul K. Harter, Jr. 27-Jan-1998 ! Add GLXRMTPFN for Galaxy membership services ! ! X-29 REG Ruth Goldenberg 09-Dec-1997 ! Add INSF_PAGED for clusterwide logical names and general use. ! ! X-28 AHM026 Drew Mason 5-Dec-1997 ! Add GLXALLNODES and GLXFATAL for Galaxy. ! ! X-27 REG Ruth Goldenberg 25-Mar-1997 ! Add CWLNMERR for clusterwide logical names. ! ! X-26 KSG0050 Kevin Greaney 20-Dec-1996 ! Mainline merge of Per-Thread Security support: (gen 24A1) ! ! X-24A1 JMM96078 John M. Molloy 15-Apr-1996 ! Mainline merge of Per-Thread Security. ! Add BUG$_NOTPSBIRP code to represent an invalid PSB ! pointer in the IRP. Add BUG$_INVSECURESTATE for cases ! where GET_CURPSB is invoked with a PCB/KTB that doesn't ! represent the active thread. ! ! ! X-25 Chris Schuetz 29-Jul-1996 ! Add codes for Memory Channel ! MC_FORCEDCRASH, MC_INCONSTATE, PM_VMSPORT ! ! X-24 Andy Kuehnel 9-May-1996 ! Add BUG$_MCHECKPAL ! ! X-23 RAB Richard A. Bishop 14-Feb-1996 ! Restrict total size of bugcheck message (count, name, ! comma, space, text) to 128 bytes. ! ! X-22 RAB Richard A. Bishop 29-Dec-1995 ! More typos (some trailing ">"'s) ! ! X-21 RAB Richard A. Bishop 27-Dec-1995 ! Clean up some typos now that SDA will display them all ! ! X-20 TGC0043 Tom Carr 23-FEB-1995 ! Add BUG$_SHADZEROMBR. ! ! X-19 Nancy Jean Burkholder 12-Oct-1994 ! Add INSF_NONPAGED for Shadowing and DU/TUDRIVER. ! ! X-18 MAH Mark A. Howell 8-Sep-1994 ! Add Dollar specific bug check codes ! ! X-18 RS00474 Richard Sayde 22-Nov-1993 ! Changed VAXCluster to VMSCluster in message text. Also ! removed -VAX portion from DECnet-VAX message. ! ! X-17 RFB001 Ray Boucher 22-Oct-1993 ! Added TMSCP BUGCHECK code. ! ! X-16 RS00465 Richard Sayde 29-Sep-1993 ! Added LASTBUG bugcheck code as an indicator of the ! last possibel bugcheck code. ! ! X-15 SDD Steve DiPirro 10-Sep-1993 ! Add ASSERTFAIL for system C code assert failures. ! ! X-14 DBM0001 David B. Miller 14-Apr-1993 ! Add SYSAPLERR for OPCOM. ! ! X-13 CEG Clair Grant 13-APR-1993 ! Undo previous change. ! ! X-12 CEG Clair Grant 12-APR-1993 ! Add SECAUDERR ! ! X-11 CEG Clair Grant 26-MAR-1993 ! Add NSABLOST, SECAUDTCB, SECIPLHIGH ! ! X-10 TRB Tom Benson 11-Mar-1993 ! Added REGCORDET, "register corruption detected after fork", ! so that INCON_SCHED doesn't have to be used for that purpose ! anymore. ! ! X-8 CEG Clair Grant 12-MAR-1993 ! Add SECOSRERR. ! Match version number with CMS generation. ! ! X-9 EMB0211 Ellen M. Batbouta 17-Sep-1992 ! Add bugcheck code, NOCALLTRANS, to signal that it ! is illegal for inner-mode native code to call ! translated code. ! ! X-8 Sue Lewis 28-Jul-1992 ! Add code for generic I/O induced crashes. ! X-7 RLP001 Ray Pfau 31-Jan-1992 ! Add bugcheck code for CTRLERR (controller error). ! ! X-6 HH0808 Hai Huang 11-Dec-1991 ! Add generic POSIX bugcheck code (POSIXBUG). ! ! X-5 BJT244 Benjamin J. Thomas III 14-Sep-1991 ! Add I/O Mailbox error code (IOMBXERR) ! ! X-4 MSH1158 Michael S. Harvey 29-Aug-1991 ! Replace BADSWPVBN with BADSWPPAG. ! ! X-3 JJA0077 Jeffrey J. Anuszczyk 12-Jun-1991 ! Add codes for new error halt restart bugchecks. ! ! X-2 JTK Jim Klumpp 20-Mar-1991 ! Add bugcheck code for invalid map register parameter. ! ! X-1K11 RS00089 Richard Sayde 6-Mar-1991 ! Remove mention of interrupt stack for BUGCHECK code ! INVEXCEPTN as it no longer exists on Alpha. ! ! X-1K10 SDD Steve DiPirro 28-Feb-1991 ! Add bugcheck code for XDELTA/DELTA-induced BUGCHECKs. ! ! X-1K9 JJA0033 Jeffrey J. Anuszczyk 7-Jan-1991 ! Add bugcheck code for [SYSLOA] OPdriver. ! ! X-1K8 RS00055 Richard Sayde 7-Jan-1991 ! Added BUGCHECK code string to error message. This should ! simplify searching for BUGCHECK codes in listings. ! ! X-1K7 PAJ0335 Paul A. Jacobi 15-Oct-1990 ! Added several new BUGCHECK code for the [APB] and [SYSBOOT] ! facility. ! ! X-1K6 MSH1028 Michael S. Harvey 29-Aug-1990 ! Add INCONMMGST. Delete Polarstar bugchecks and BADPSL. ! ! X-1K5 KLN1038 Karen Noel 24-Aug-1990 ! Add incon_shell ! ! X-1K4 RS00024 Richard Sayde 10-Aug-1990 ! Fix a couple of bugs - change %ASCID to %ASCIC in icon_sched ! BUGCHECK and a bug in how the table is built (Calculated ! alignment incorrectly). ! ! X-1K3 WMC00K3 Wayne Cardoza 02-Aug-1990 ! Remove shared memory bugchecks. ! ! X-1K2 WMC00K2 Wayne Cardoza 26-Jul-1990 ! Delete queuempty, add incon_sched ! ! X-1 RS00010 Richard Sayde 2-Jul-1990 ! Create this module. ! %IF (%DECLARED (BugCheckMacrosDefined) EQL 0) %THEN COMPILETIME BugCheckMacrosDefined = 1, CodeNum = 8, NewBufIndex = 0, BufIndex = 0, BufNum = 0, ZeroBytes = 0, GenTable = 0, GenMessages = 0; MACRO STARTMSG(PsectName) = %ASSIGN (CodeNum, 8) %ASSIGN (NewBufIndex, 0) %ASSIGN (BufIndex, 0) %ASSIGN (BufNum, 0) %ASSIGN (ZeroBytes, 0) %IF (GenTable EQL 1) %THEN GLOBAL BIND BUG$TABLE = UPLIT %IF (%LENGTH EQL 1) %THEN PSECT (PsectName) %FI WORD (0 %ELSE %IF (GenMessages EQL 1) %THEN GLOBAL BIND BUG$MESSAGES = UPLIT %IF (%LENGTH EQL 1) %THEN PSECT (PsectName) %FI BYTE ( %FI %FI %, ENDMSG = %IF (GenTable EQL 1) %THEN ): VECTOR [, WORD]; %ELSE %IF (GenMessages EQL 1) %THEN 0): VECTOR[,BYTE]; %FI %FI %, GENZEROS(Count)[] = %IF (Count GTR 0) %THEN 0, GENZEROS(Count - 1) %FI %, MSGSTRING(CODE,STRING) = %STRING (%CHAR(%CHARCOUNT (%STRING (CODE, ', ', STRING))), CODE, ', ', STRING) %, GENINFO(CODE,STRING) = %IF (GenTable EQL 1) OR (GenMessages EQL 1) %THEN %ASSIGN (NewBufIndex, BufIndex + %CHARCOUNT (MSGSTRING(CODE,STRING))) %IF (%NUMBER(NewBufIndex) GEQ %NUMBER(BlockSize)) %THEN ! this message goes over a block boundary, align it at the next ! boundary %ASSIGN (ZeroBytes, ZeroBytes + BlockSize - BufIndex) %ASSIGN (BufIndex, 0) %ASSIGN (BufNum, BufNum + 1) %FI %IF (GenTable EQL 1) %THEN ! add the table info to the uplit , %NUMBER(BufNum) * %NUMBER(BlockSize) + %NUMBER(BufIndex) %ELSE ! add the messages info to the uplit GENZEROS(ZeroBytes) MSGSTRING(CODE,STRING), %FI ! update BufIndex %IF (%NUMBER(NewBufIndex) LSS %NUMBER(BlockSize)) %THEN %ASSIGN (BufIndex, NewBufIndex) %ELSE %ASSIGN (BufIndex, BufIndex + %CHARCOUNT (MSGSTRING(CODE,STRING))) %FI ! quadword align the buffer index %ASSIGN (NewBufIndex, ((BufIndex + 8) / 8) * 8) %ASSIGN (ZeroBytes, NewBufIndex - BufIndex) %ASSIGN (BufIndex, NewBufIndex) %ELSE %IF (%CHARCOUNT (MSGSTRING(CODE,STRING)) GTR 128) %THEN %ERROR (%ASCII'BUGCHECK message too long: ', CODE) %ELSE GLOBAL LITERAL %NAME ('BUG$_', CODE) = CodeNum; %FI %FI %ASSIGN (CodeNum, CodeNum + 8) %, PLACE_HOLDER = %IF (GenTable EQL 1) %THEN , 0, 0 %FI %, GENBUGCHECKMSGS (GenType, PsectName) = ! determine what to generate, codes, table or message buffer %IF (%IDENTICAL (GenType, CODES)) %THEN %ASSIGN (GenTable, 0) %ASSIGN (GenMessages, 0) %ELSE %IF (%IDENTICAL (GenType, TABLE)) %THEN %ASSIGN (GenTable, 1) %ASSIGN (GenMessages, 0) %ELSE %IF (%IDENTICAL (GenType, MESSAGES)) %THEN %ASSIGN (GenTable, 0) %ASSIGN (GenMessages, 1) %ELSE %ERROR (%ASCII'Invalid bugcheck generate type ', GenType) %EXITMACRO %FI %FI %FI ! do the work %IF (%LENGTH EQL 2) %THEN STARTMSG (PsectName) %ELSE STARTMSG () %FI GENINFO (ACPMBFAIL, %ASCII'ACP failure to read mailbox') GENINFO (ACPVAFAIL, %ASCII'ACP failure to return virtual address space') GENINFO (ALCPHD, %ASCII'Allocate process header error') GENINFO (ALCSMBCLR, %ASCII'ACP tried to allocate space already allocated') GENINFO (APTREFHIGH, %ASCII'Inconsistent active page table reference count') GENINFO (APTWRTERR, %ASCII'Active page table swap write error') GENINFO (ASYNCWRTER, %ASCII'Asynchronous write memory failure') GENINFO (BADALORQSZ, %ASCII'Bad memory allocation request size') GENINFO (BADBUFADR, %ASCII'ACP buffer address out of range of buffer pool') GENINFO (BADBUFTYP, %ASCII'Bad ACP buffer type code') GENINFO (BADDALRQSZ, %ASCII'Bad memory deallocation request size or address') GENINFO (BADFID, %ASCII'ACP file number out of range for this volume') GENINFO (BADFORKIPL, %ASCII'Bad FORK exit interrupt priority level') GENINFO (BADLCKWSLE, %ASCII'Bad locked working set list entry, not a page table') GENINFO (BADMCKCOD, %ASCII'Bad machine check code') GENINFO (BADPAGFILA, %ASCII'Bad page file address allocated') GENINFO (BADPAGFILD, %ASCII'Bad page file address deallocated') GENINFO (BADPAGTYPE, %ASCII'Bad page type') GENINFO (BADRSEIPL, %ASCII'Bad IPL at entrance to report schedule event') GENINFO (BADSBMBLK, %ASCII'ACP tried to reference off end of bitmap') GENINFO (BADSWPPAG, %ASCII'Swap page specified for non-process page') GENINFO (BADWCBPT, %ASCII'Bad WCB pointer in IRP') GENINFO (CHMONIS, %ASCII'Change mode instruction while on interrupt stack') GENINFO (CONTRACT, %ASCII'Contract virtual address space error') GENINFO (DBLERR, %ASCII'Double error halt restart') GENINFO (DECPTREF, %ASCII'Decrement page table reference count error') GENINFO (DELCONPFN, %ASCII'Fatal error in delete contents of PFN') GENINFO (DELGBLSEC, %ASCII'Delete global section error') GENINFO (DELGBLWCB, %ASCII'Delete global section window error') GENINFO (BADBOOTCB, %ASCII'Corrupted Boot Control Block') GENINFO (DELWSLEX, %ASCII'Delete working set list entry index error') GENINFO (DIRENTRY, %ASCII'ACP failed to find same directory entry') GENINFO (DOUBLDALOC, %ASCII'Double deallocation of swap file space') GENINFO (DOUBLDEALO, %ASCII'Double deallocation of memory block') GENINFO (ERRHALT, %ASCII'Halt with error interrupt pending') GENINFO (EXHFUL, %ASCII'File extension header has no room') GENINFO (EXPANDPHD, %ASCII'Expand process header error') GENINFO (FATALEXCPT, %ASCII'Fatal executive or kernel mode exception') GENINFO (FREEPAGREF, %ASCII'Free page reference count is nonzero') GENINFO (FREWSLX, %ASCII'Free working set list index, resource wait') GENINFO (GBLPAGSZRO, %ASCII'Global page share count is zero') GENINFO (GBLWSLXERR, %ASCII'Global working set list entry not found') GENINFO (GPGNULPGFL, %ASCII'Global page has null page file address') GENINFO (HALT, %ASCII'Halt instruction restart') GENINFO (HDRNOTMAP, %ASCII'Allocated file header not mapped') GENINFO (ICONPFNDAT, %ASCII'Inconsistent PFN data base') GENINFO (ICPAGELOC, %ASCII'Inconsistent page location') GENINFO (IFREPAGCNT, %ASCII'Inconsistent free page count') GENINFO (ILLEVTNUM, %ASCII'Illegal event number') GENINFO (ILLVEC, %ASCII'Illegal interrupt or exception vector restart') GENINFO (INCONSTATE, %ASCII'Inconsistent I/O data base') GENINFO (INCPTREF, %ASCII'Increment page table reference count error') GENINFO (INSNFREPAG, %ASCII'Insufficient nonfree pages') GENINFO (INSSWPFIL, %ASCII'Insufficient swap file space') GENINFO (INSWAPERR, %ASCII'Inswap read error') GENINFO (INVCHAN, %ASCII'Invalid ACP channel number') GENINFO (INVEXCEPTN, %ASCII'Exception while above ASTDEL') GENINFO (INVPTEFMT, %ASCII'Invalid page table entry format') GENINFO (INVTQEFMT, %ASCII'Invalid time queue entry format') GENINFO (IVBAKADIO, %ASCII'Invalid backing store address for I/O') GENINFO (IVGBLTYP, %ASCII'Invalid global master PTE type') GENINFO (IVLISTK, %ASCII'Interrupt stack invalid restart') GENINFO (IVSSRVRQST, %ASCII'Invalid system service request') GENINFO (IVWSETLIST, %ASCII'Invalid working set list entry') GENINFO (KRNLSTAKNV, %ASCII'Kernel stack not valid') GENINFO (MACHINECHK, %ASCII'Machine check while in kernel mode') GENINFO (MAKEWSLE, %ASCII'Make working set list entry error') GENINFO (MODRELNBAK, %ASCII'No backing store address for modified page') GENINFO (MFYNULPGFL, %ASCII'FREWSLE - no backing store, page not modified') GENINFO (MPWALCIRP, %ASCII'Modified page writer failed to allocate I/O Packet') GENINFO (MTXCNTNONZ, %ASCII'Mutex count nonzero at system service exit') GENINFO (NETNOBUF, %ASCII'NETACP - buffer allocation failure') GENINFO (NETNOSTATE, %ASCII'NETACP - no state transition') GENINFO (NETRCVPKT, %ASCII'NETACP - no receive I/O packet') GENINFO (NETSYSSRV, %ASCII'NETACP - unexpected system service failure') GENINFO (NETTRANCNT, %ASCII'NETACP - transaction count zero') GENINFO (NOACPCHAN, %ASCII'Failure to assign ACP channel') GENINFO (NOACPMAIL, %ASCII'Failure to create ACP mailbox') GENINFO (NOAQBACP, %ASCII'No AQB for ACP') GENINFO (NOBUFPCKT, %ASCII'Required buffer packet not present') GENINFO (NOBVPVCB, %ASCII'Blocked volume virtual page not found in VCB') GENINFO (NOMULTBK, %ASCII'ACP multiple block buffering not supported yet') GENINFO (NONEXSTACP, %ASCII'Nonexistent ACP process') GENINFO (NORCVBUF, %ASCII'NETACP - no receive buffer available') GENINFO (NOTDDBDDB, %ASCII'Corrupted DDB list') GENINFO (NOTFCBFCB, %ASCII'FCB linkage broken') GENINFO (NOTFCBWCB, %ASCII'Bad FCB pointer in window') GENINFO (NOTFCPWCB, %ASCII'Not FCP window in IRP') GENINFO (NOTIRPAQB, %ASCII'Not IRP pointer in AQB') GENINFO (NOTMTLMTL, %ASCII'Corrupted mounted volume list') GENINFO (NOTPCB, %ASCII'Structure not PCB') GENINFO (NOTRVTVCB, %ASCII'Not RVT pointer in VCB') GENINFO (NOTUCBIRP, %ASCII'Not UCB pointer in IRP') GENINFO (NOTUCBRVT, %ASCII'Not UCB pointer in RVT') GENINFO (NOTUCBUCB, %ASCII'Corrupted UCB list') GENINFO (NOTVCBUCB, %ASCII'Not VCB pointer in UCB') GENINFO (NOTVVPVCB, %ASCII'Not volume virtual page pointer in VCB') GENINFO (NOTWCBIRP, %ASCII'Not WCB Pointer in IRP') GENINFO (NOUSRWCS, %ASCII'No user WCS halt restart') GENINFO (OUTSWPERR, %ASCII'Outswap write error') GENINFO (PAGEREDERR, %ASCII'Page read error') GENINFO (PAGEWRTERR, %ASCII'Page write error') GENINFO (PAGNTRNVAL, %ASCII'Page not in transition or valid') GENINFO (PFNLISTCNT, %ASCII'Inconsistent PFN list count') GENINFO (PFNREFNZRO, %ASCII'PFN reference count nonzero') GENINFO (PGFGBLBAD, %ASCII'Pagefault, global page table entry bad format') GENINFO (PGFIPLHI, %ASCII'Pagefault with IPL too high') GENINFO (PGFLOCBAD, %ASCII'Pagefault, location field has bad value') GENINFO (PROCGONE, %ASCII'Process not in system') GENINFO (PTELENVIOL, %ASCII'Unexpected page table length violation') GENINFO (PTRCNT, %ASCII'ACP block count exceeds retrieval pointer size') GENINFO (PURGWSSCN, %ASCII'Purge working set scan error') GENINFO (INCON_SCHED, %ASCII'Inconsistent scheduling state') GENINFO (RDSNONRES, %ASCII'Read data substitute page nonresident') GENINFO (REFCNTNEG, %ASCII'PFN reference count is negative') GENINFO (RMSBUG, %ASCII'RMS has detected an invalid condition') GENINFO (SCANDEADPT, %ASCII'Scan dead page table error') GENINFO (SECREFNEG, %ASCII'Section reference count went negative') GENINFO (SHRCNTNEG, %ASCII'PFN share count negative') GENINFO (SSRVEXCEPT, %ASCII'Unexpected system service exception') GENINFO (STRNOTWCB, %ASCII'Data structure not window block') GENINFO (SWAPWSLE, %ASCII'Swap working set list entries error') GENINFO (SYSADJWSL, %ASCII'System service adjust working set limit error') GENINFO (SYSTRMERR, %ASCII'SYSINIT-terminal IO error') GENINFO (TIPCUFLOW, %ASCII'NETACP - transmit count underflow') GENINFO (UBMAPEXCED, %ASCII'UNIBUS map register allocation exceeded') GENINFO (UNABLCREVA, %ASCII'Unable to create virtual address space') GENINFO (UNEXPIOINT, %ASCII'Unexpected I/O adapter interrupt') GENINFO (UNKRSTRT, %ASCII'Unknown restart code') GENINFO (UNXINTEXC, %ASCII'Unexpected interrupt or exception') GENINFO (UNXSIGNAL, %ASCII'Unexpected signal name in ACP') GENINFO (VBNMAPFAIL, %ASCII'Virtual block map failure') GENINFO (WACKQEMPTY, %ASCII'NETACP - ack wait queue empty') GENINFO (WRTINVBUF, %ASCII'ACP attempted to write an invalid buffer') GENINFO (WRTINVHDR, %ASCII'ACP attempted to write an invalid file header') GENINFO (WRTPGSBAK, %ASCII'Write pages back - inconsistent data base') GENINFO (WSLENOVAL, %ASCII'Working set list entry not valid') GENINFO (WSLPAGCNT, %ASCII'Working set list page count error') GENINFO (WSLVANVAL, %ASCII'Working set list virtual adr has non-valid PTE') GENINFO (WSLXVANMAT, %ASCII'Working set list entry does not match VA') GENINFO (ZEROPAGE, %ASCII'Zero page table entry from swap map') GENINFO (OPERATOR, %ASCII'Operator requested system shutdown') GENINFO (BADQHDR, %ASCII'Interlocked queue header corrupted') GENINFO (UNKNPRQ, %ASCII'Unknown Inter-processor Request Message') GENINFO (BDPPURGERR, %ASCII'Buffered datapath purge incomplete') GENINFO (BRDMSGLOST, %ASCII'Broadcast queue pointer has no related entry') GENINFO (MBACBHUNG, %ASCII'MBA CBHUNG bit set') GENINFO (ACPRECURS, %ASCII'Attempted recursion in ACP secondary operation') GENINFO (ACPUNSTAK, %ASCII'Attempted unstack in ACP primary context') GENINFO (BADRVNWCB, %ASCII'Inconsistent RVN in window map pointer') GENINFO (ERRCACHFUL, %ASCII'Error cache is full') GENINFO (EXTCACHIV, %ASCII'Contents of extent cache is garbage') GENINFO (MAPCNTZER, %ASCII'Attempted to generate zero length map pointer') GENINFO (NOTUCBWCB, %ASCII'Bad UCB pointer in window') GENINFO (CHMVEC, %ASCII'CHM vector bits <1:0> not 0') GENINFO (FILCNTNONZ, %ASCII'Open file count nonzero after process rundown') GENINFO (WSSIZEERR, %ASCII'Working set size less than pages in use') GENINFO (DEQSUBLCKS, %ASCII'Tried to dequeue lock with sublocks') GENINFO (LKBREFNEG, %ASCII'LKB reference count negative') GENINFO (RSBREFNEG, %ASCII'RSB reference count negative') GENINFO (RSBREFNZRO, %ASCII'Tried to deallocate RSB with non-zero reference count') GENINFO (SCBRDERR, %ASCII'SCB physical read error halt') GENINFO (STATENTSVD, %ASCII'Software state not saved during powerfail') GENINFO (LKBGRANTED, %ASCII'LKB is granted, but shouldnt be') GENINFO (NOTLKB, %ASCII'Structure is not an LKB') GENINFO (INVRSPID, %ASCII'RSPID not valid') GENINFO (WCBFCBMNG, %ASCII'WCB/FCB correspondence broken') GENINFO (NOTWCBWCB, %ASCII'Corrupted WCB list') GENINFO (UDAPORT, %ASCII'Fatal error detected by UDA port driver (PUDRIVER)') GENINFO (DISKCLASS, %ASCII'Fatal error detected by Disk Class driver (DUDRIVER)') GENINFO (CIPORT, %ASCII'Fatal error detected by CI port driver (PADRIVER)') GENINFO (NODEFFONT, %ASCII'Default font not in system font queue') GENINFO (BADDOP, %ASCII'Error in DOP data') GENINFO (VWSNONPOOL, %ASCII'Insufficient nonpaged pool to continue drawing') GENINFO (VWSNOPPOOL, %ASCII'Insufficient paged pool to continue drawing') GENINFO (BADBITMAPID, %ASCII'Invalid bitmap ID specified in DOP') GENINFO (VWS1, %ASCII'Workstation bugcheck code #1') GENINFO (RUF, %ASCII'Fatal error detected by Recovery Unit Facility') GENINFO (TAPECLASS, %ASCII'Fatal error detected by Tape Class driver (TUDRIVER)') GENINFO (LOCKMGRERR, %ASCII'Error detected by Lock Manager') GENINFO (CNXMGRERR, %ASCII'Error detected by VMScluster Connection Manager') GENINFO (XQPERR, %ASCII'Error detected by file system XQP') GENINFO (INVLOCKID, %ASCII'Invalid lock id') GENINFO (SBIAERROR, %ASCII'Fatal SBIA error') GENINFO (WCSCORR, %ASCII'WCS error correction failed') GENINFO (CPUCEASED, %ASCII'CPU ceased execution') GENINFO (CLUEXIT, %ASCII'Node voluntarily exiting VMScluster') GENINFO (UNSUPRTCPU, %ASCII'Unsupported CPU') GENINFO (VWS2, %ASCII'Workstation bugcheck code #2') GENINFO (VWS3, %ASCII'Workstation bugcheck code #3') GENINFO (OUTOFSYNC, %ASCII'Processor clocks out of synch') GENINFO (IVBYTEALGN, %ASCII'Invalid byte alignment for I/O transfer') GENINFO (ACCVIOMCHK, %ASCII'ACV or TNV during machine check exception') GENINFO (ACCVIOKSTK, %ASCII'ACV or TNV during kernel stack not valid exception') GENINFO (MSCPSERV, %ASCII'Fatal error detected by MSCP server') GENINFO (RESEXH, %ASCII'Resources exhausted, system shutting down') GENINFO (CONSOLRX50, %ASCII'Fatal error detected by Console RX50 driver') GENINFO (KRPEMPTY, %ASCII'P1 lookaside list is empty') GENINFO (MSCPCLASS, %ASCII'Fatal error detected by MSCP class driver') GENINFO (ICONCLUDAT, %ASCII'Inconsistent Cluster data base') GENINFO (OPERCRASH, %ASCII'Operator forced system crash') GENINFO (INSFPOOL, %ASCII'Insufficient nonpaged pool to remaster locks on this system') GENINFO (INSFLOCKID, %ASCII'Insufficient lockids to remaster locks on this system') GENINFO (CTERM, %ASCII'Fatal error detected by CTERM driver (CTDRIVER)') GENINFO (IVDSKCONFG, %ASCII'Invalid Disk Configuration') GENINFO (UCODEREV, %ASCII'CPU or CI port microcode rev inadequate for CI activity') GENINFO (MPCPUCEASED, %ASCII'Secondary CPU ceased execution') GENINFO (DUPCLASS, %ASCII'Fatal error detected by FYDRIVER') GENINFO (CWSERR, %ASCII'Error detected while processing cluster-wide service request') GENINFO (VWS4, %ASCII'Workstation bugcheck code #4') GENINFO (VWS5, %ASCII'Workstation bugcheck code #5') GENINFO (VWS6, %ASCII'Workstation bugcheck code #6') GENINFO (CPUEXIT, %ASCII'Shutdown requested by another CPU') GENINFO (SPLACQERR, %ASCII'Spinlock(s) of higher rank already owned by CPU') GENINFO (SPLRELERR, %ASCII'Spinlock to be released is not owned') GENINFO (SPLRSTERR, %ASCII'Spinlock to be conditionally released is not owned') GENINFO (SPLIPLLOW, %ASCII'IPL has fallen below level of owned spinlock(s)') GENINFO (SPLIPLHIGH, %ASCII'Current IPL exceeds synchronization IPL of desired spinlock') GENINFO (SPLNOTSPL, %ASCII'Not a spinlock structure') GENINFO (SPLINVIPL, %ASCII'New spinlock IPL too low') GENINFO (SPLNOTMAP, %ASCII'Spinlock address was not found in rank map') GENINFO (VAXPORT, %ASCII'Fatal error detected by VAX port driver') GENINFO (CLUSWVER, %ASCII'Software version incompatible with existing VMScluster') GENINFO (BADVECTOR, %ASCII'Inconsistency found while loading a system service vector') GENINFO (SSVECFULL, %ASCII'Ran out of system service vector numbers') GENINFO (PFNFIXUP, %ASCII'Instruction mismatch during PFN fixups') GENINFO (BADRTPRI, %ASCII'Real-time current priority not equal to base priority') GENINFO (ILLQBUSCFG, %ASCII'Illegal Qbus configuration detected by interrupt dispatcher') GENINFO (WATCHPOINT, %ASCII'Watchpoint encountered by the watchpoint driver (WPDRIVER)') GENINFO (WPDRVRERR, %ASCII'Fatal error detected in the watchpoint driver (WPDRIVER)') GENINFO (NOTSYSVA, %ASCII'Not a system virtual address') GENINFO (TTDRVR, %ASCII'No more fork blocks') GENINFO (BADPRCPGFLX, %ASCII'PTE contains bad process pagefile index') GENINFO (BADPPFLREFCNT, %ASCII'Process page file reference count is invalid') GENINFO (BADPRCPGFLC, %ASCII'Current process pagefile assignment is invalid') GENINFO (PFLREFNEG, %ASCII'PFL reference count negative') GENINFO (NOPRCPGFL, %ASCII'Failure to assign process pagefile') GENINFO (CPUSANITY, %ASCII'CPU sanity timer expired') GENINFO (CPUBUSYWAIT, %ASCII'CPU miscellaneous busywait timer expired') GENINFO (POOLCHECK, %ASCII'Corruption or inconsistency in pool discovered by pool checker') GENINFO (CPUSPINWAIT, %ASCII'CPU spinwait timer expired') GENINFO (DISKSERVE, %ASCII'Error detected during attempt to MSCP serve disk') GENINFO (VAXCLUSTER, %ASCII'Error detected by VMScluster software') GENINFO (FATMEMERR, %ASCII'Fatal memory error detected') GENINFO (TTDRVR1, %ASCII'TTDRVR bugcheck code #1') GENINFO (CPUNOTPRIMARY, %ASCII'Primary-only operation attempted on secondary CPU') GENINFO (LICENSERR, %ASCII'Fatal software licensing inconsistency') GENINFO (NOCONSBUFF, %ASCII'Unable to allocate console disk data buffers') GENINFO (NETDLLERR, %ASCII'DECnet Datalink Layer detected a fatal error') GENINFO (NETRTGERR, %ASCII'DECnet Routing Layer detected a fatal error') GENINFO (NETECLERR, %ASCII'DECnet End Communication Layer detected a fatal error') GENINFO (NETSESERR, %ASCII'DECnet Session Layer detected a fatal error') GENINFO (MULDEALNPAG, %ASCII'Multiple deallocation of nonpaged pool') GENINFO (PPGFLVANEG, %ASCII'PPGFLVA count in PHD is negative') GENINFO (SECAUDEXH, %ASCII'Security auditing shutdown due to resource exhaustion') GENINFO (SECURITY1, %ASCII'SECURITY bugcheck code #1') GENINFO (SECURITY2, %ASCII'SECURITY bugcheck code #2') GENINFO (MCHKMCHK, %ASCII'Machine check during machine check exception') GENINFO (MCHKSTKNV, %ASCII'Machine check during kernel stack not valid exception') GENINFO (WRONGPRIMARY, %ASCII'Console restarted wrong CPU as primary after power failure') GENINFO (INVPFLMAP, %ASCII'Invalid page file mapping window') GENINFO (SECAUDERR, %ASCII'Fatal error attempting to perform a security audit') GENINFO (DSSIPORT, %ASCII'Fatal error detected by DSSI port driver (PIDRIVER)') GENINFO (DECWINDOWS, %ASCII'DECwindows fatal error') GENINFO (DDTMBUG, %ASCII'DDTM has detected an invalid condition') GENINFO (IPCBUG, %ASCII'IPC has detected an invalid condition') GENINFO (CSLBUG, %ASCII'CSL has detected an invalid condition') GENINFO (LOGFAIL, %ASCII'Fatal write error to system log') GENINFO (VMSTESTERR, %ASCII'VMSTEST fatal error (REF: $HELP @SYS$TEST:VMSTEST BUGCODE)') GENINFO (VPIPLHIGH, %ASCII'IPL too high to use the Vector Facility') GENINFO (VPERR, %ASCII'Fatal error detected by the Vector Facility') GENINFO (BADSETFUNC, %ASCII'Bad SET function detected by CTDRIVER') GENINFO (DCBCNTRBAD, %ASCII'DCB counter not zero when DECnet output task is idle (CTDRIVER)') GENINFO (NOTIDLE, %ASCII'DECnet output task not idle when flag clear (CTDRIVER)') GENINFO (INVCTERMMSG, %ASCII'Invalid CTERM message with matching IRP') GENINFO (SCSIPORT, %ASCII'Fatal error detected by SCSI port driver (PK%DRIVER)') GENINFO (CORRUPTEMB, %ASCII'EMB packet header has been corrupted') GENINFO (SHADDETINCON, %ASCII'SHADOWING detects inconsistent state') GENINFO (GFX_INVTB, %ASCII'Extended Graphics Invalidation Error') GENINFO (TOOMANYUIDS, %ASCII'Too many UIDs generated in one clock tick') GENINFO (SHADBOOTFAIL, %ASCII'SHADOWING failed to boot from system disk shadow set') GENINFO (DECNET, %ASCII'DECnet detected a fatal error') GENINFO (REMOTE_AGENT, %ASCII'Remote privileged agent requested system crash') GENINFO (CUSTOMER, %ASCII'Reserved for customer use') GENINFO (RSVD_ISV, %ASCII'Reserved for independent software vendor use') GENINFO (RSVD_LP, %ASCII'Reserved for layered product use') GENINFO (SEQ_NUM_OVF, %ASCII'Sequence number overflow') GENINFO (INCON_SHELL, %ASCII'Inconsistent SHELL state') GENINFO (INCONMMGST, %ASCII'Inconsistent memory management state') GENINFO (BADHOMEBLK, %ASCII'Bad checksum on home block') GENINFO (BADINDEXHDR, %ASCII'Bad checksum on index file header') GENINFO (BADROOTHDR, %ASCII'Bad checksum on root directory file header') GENINFO (BADFILEHDR, %ASCII'Bad checksum on file header') GENINFO (NOSUCHFILE, %ASCII'Unable to locate bootstrap file') GENINFO (UNABLCREVM, %ASCII'Unable to create virtual memory space') GENINFO (L1PTNOTMAP, %ASCII'Failed to map level 1 page table') GENINFO (L1PTNOTUNMAP, %ASCII'Failed to unmap level 1 page table') GENINFO (L2PTNOTUNMAP, %ASCII'Failed to unmap level 2 page table') GENINFO (INCON_CONSOLE, %ASCII'Inconsistent console terminal state') GENINFO (DEBUGCRASH, %ASCII'Debugger forced system crash') GENINFO (INV_MAPREG_PAR, %ASCII'Invalid map register parameter') GENINFO (INVSCBB, %ASCII'Invalid System Control Block Base') GENINFO (INVPTBR, %ASCII'Invalid Page Table Base Register') GENINFO (IOMBXERR, %ASCII'I/O Mailbox Error') GENINFO (POSIXBUG, %ASCII'Fatal internal error detected in VMS/POSIX') GENINFO (CTRLERR, %ASCII'Controller error') GENINFO (IOMACHINECHK, %ASCII'I/O induced machine check') GENINFO (NOCALLTRANS, %ASCII'Inner mode native code cannot call translated code') GENINFO (SECOSRERR, %ASCII'Fatal error detected by security object support routine') GENINFO (REGCORDET, %ASCII'Register corruption detected after fork') GENINFO (NSABLOST, %ASCII'Security audit block stranded in non-paged pool') GENINFO (SECAUDTCB, %ASCII'Security auditing failure reported by TCB') GENINFO (SECIPLHIGH, %ASCII'Security subsystem detected IPL too high') GENINFO (SYSAPLERR, %ASCII'System process detected fatal error') GENINFO (ASSERTFAIL, %ASCII'System ASSERT failure detected') GENINFO (TMSCPSERV, %ASCII'Fatal error detected by TMSCP server') GENINFO (F64ERR, %ASCII'Fatal error detected by Files-64 file system') GENINFO (LFSERR, %ASCII'Fatal error detected by LFS') GENINFO (XFSCERR, %ASCII'Fatal error detected by XFS client') GENINFO (XFSSERR, %ASCII'Fatal error detected by XFS server') GENINFO (INSF_NONPAGED, %ASCII'Insufficient nonpaged pool') GENINFO (SHADZEROMBR, %ASCII'SHADOWING detects a zero member set') GENINFO (MCHECKPAL, %ASCII'Machine check while in PAL environment') GENINFO (MC_FORCEDCRASH, %ASCII'Remotely-forced crash - non-responsive Memory Channel node') GENINFO (MC_INCONSTATE, %ASCII'Fatal error detected by Memory Channel') GENINFO (PM_VMSPORT, %ASCII'Fatal error detected by Memory Channel port driver') GENINFO (INVSECURESTATE, %ASCII'Invalid state detected by SECURITY subsystem') GENINFO (NOTPSBIRP, %ASCII'Not a PSB pointer in IRP') GENINFO (CWLNMERR, %ASCII'Fatal error in clusterwide logical name support') GENINFO (GLXALLNODES, %ASCII'Crash all nodes signaled from Galaxy support') GENINFO (GLXFATAL, %ASCII'Fatal error in Galaxy support') GENINFO (INSF_PAGED, %ASCII'Insufficient paged pool') GENINFO (GLXRMTPFN, %ASCII'Remote node had PFN of this node mapped for write') GENINFO (INVPFN, %ASCII'Invalid PFN mapped by page table entry') GENINFO (POWEROFF, %ASCII'System power-off requested') GENINFO (SMCIPORT, %ASCII'Fatal error detected by SMCI port driver (SYS$PBDRIVER)') GENINFO (GLXSHUTSHMEM, %ASCII'Shared memory still mapped during system shutdown') GENINFO (GLXCRASH, %ASCII'BUGCHK requested from another Galaxy instance') GENINFO (RMS_INCONSTATE, %ASCII'Inconsistent state detected by RMS') GENINFO (GLXRMTMCHK, %ASCII'Remote node detected machine check in this instance') GENINFO (MTXRELERR, %ASCII'Mutex to be released is not owned') GENINFO (SEPPUCLU, %ASCII'Remote crash request / execution honored for / cluster harmony') GENINFO (TESTING123, %ASCII'Generic bugcheck used to debug privileged code') GENINFO (SCSERROR, %ASCII'Fatal condition detected in SCS layer or SCS port') GENINFO (FPSWAERROR, %ASCII'Floating-Point SoftWare Assistance (FPSWA) error') GENINFO (OCLAFAIL, %ASCII'Unexpected failure in OCLA support routines') GENINFO (SWIS_INCONSTATE,%ASCII'Inconsistent state detected by SWIS') GENINFO (ACPI_FATAL,%ASCII'ACPI fatal error in AML bytecode stream') GENINFO (KP_INCONSTATE,%ASCII'Inconsistent state detected by KP services.') GENINFO (DBGCPUEXIT, %ASCII'Debugger sympathy crash requested by another CPU') GENINFO (CPUINT_INIT, %ASCII'Hardware INIT interrupt received') GENINFO (AST_INCONSTATE,%ASCII'Inconsistent state detected by AST subsystem') GENINFO (KTHD_INCONSTATE,%ASCII'Inconsistent state detected by kernel threads') GENINFO (SHDWREQALLOC, %ASCII'Allocation class is required for shadow set members') !New messages get added before this point. *** PLACE_HOLDER PLACE_HOLDER ! This is a placeholder for the last bugcheck code. This is needed ! so that we can figure out if a bugcheck code is in range or not in ! SDA and other tools. No bugcheck codes should be added after this ! bugcheck code. GENINFO (LASTBUG, %ASCII'Placeholder for last bugcheck code') ENDMSG %; %FI ! ! ---- < End of module BUGCHECK_CODES.REQ - 30-MAR-2010 16:38:56.38 > - ! ! IOGEN_MACROS.REQ ! ! Macros used by autoconfiguration routines ! ! Version: 'X-10' ! !**************************************************************************** !* * !* COPYRIGHT (c) 1991, 1996, 1997, 1998 BY * !* DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS. * !* ALL RIGHTS RESERVED. * !* * !* THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED * !* ONLY IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE AND WITH THE * !* INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR ANY OTHER * !* COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY * !* OTHER PERSON. NO TITLE TO AND OWNERSHIP OF THE SOFTWARE IS HEREBY * !* TRANSFERRED. * !* * !* THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE * !* AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT * !* CORPORATION. * !* * !* DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS * !* SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL. * !* * !* * !**************************************************************************** !++ ! ! FACILITY: System Library ! ! ABSTRACT: ! ! These are common macros used by Alpha autoconfiguration routines. ! ! ENVIRONMENT: ! ! Autoconfigration routines typically run in exec mode at IPL 0. ! ! MODIFICATION HISTORY: ! ! X-10 RTS048 Bob Silver 07-Jan-1998 ! Change config_table's boot_ulp field to avail2. ! ! X-9 RTS037 Bob Silver 18-Dec-1997 ! Add fill longword at end of dummy config table entry to keep ! it quadword aligned. ! ! X-8 RTS029 Bob Silver 02-Dec-1997 ! Add new boot_ulp field to dummy configuration table. ! ! X-7 FGK Fred Kleinsorge 26-Mar-1996 ! Modified to remove the definition of the configuration table - ! it is now defined in CONFIG_TABLE.SDL/R32/R64. ! ! The iogen$build_config_table macro now creates a dummy ! record containing only the hardware ID masks, and a null ! entry. The actual table is now defined in init_io_db from ! a on-disk database of devices, and the dummy table is then ! replaced (in the ADP pointer). ! ! X-6 SWA Scott W. Apgar 24-Aug-1994 ! Add the novector loading flag to the flags longword of the ! config table. ! ! X-5 JPJ James P. Janetos 30-Aug-1993 ! Make the iogen config table a global structure so that ! it can be referenced in modules other than the one in ! which it is declared. ! ! X-4 JPJ James P. Janetos 27-Oct-1992 ! Add num_units field to iogen$build_config_table macro. ! ! X-3 JPJ James P. Janetos 20-Aug-1992 ! Change hw_id_mask in iogen$build_config_table from a longword ! to a quadword. Change the hw_id field in each entry in the ! config table to a quadword. ! ! Reset CMS generation number (reserved as generation 2). ! ! X-4 RWC077 Richard W. Critz, Jr. 11-Mar-1992 ! Remove all support for the MSCP flag in the config table. ! ! X-3 RWC064 Richard W. Critz, Jr. 20-Dec-1991 ! Add IOGEN_CFG_TBL$L_HW_ID_MASK since it was inadvertantly ! omitted. ! ! X-2 RWC060 Richard W. Critz, Jr. 18-Dec-1991 ! Fix IOGEN$CALL_KERNEL_ROUTINE to handle zero arguments ! correctly. Update documentation to reflect what ! IOGEN$BUILD_CONFIG_TABLE actually does. Fix IOGEN$BUILD_ABM to ! handle more than 2 adapter types. Change names associated with ! the config table to fix a build breaker. ! ! X-1 JTK Jim Klumpp 12-Dec-1991 ! Initial version. ! !-- ! ! ! AUTHOR: Jim Klumpp CREATION DATE: 12-Dec-1991 ! IOGEN$CALL_KERNEL_ROUTINE ! ! This macro is used to call a routine in kernel mode. Since autoconfiguration ! routines typically run in exec mode, they can read - but not write - the system ! I/O database. Whenever the I/O database needs to be updated, for example when ! the no reconnect bit is set in a bus array entry, a kernel mode routine must ! be called. This macro simply makes calling the kernel mode routine easier. A ! typical invocation of this macro is: ! ! STATUS = CALL_KERNEL_ROUTINE (SET_NORECONNECT, .BUS_ARRAY_ENTRY); MACRO iogen$call_kernel_routine (routine_name) [] = BEGIN EXTERNAL ROUTINE sys$cmkrnl; LOCAL arglist: VECTOR [%LENGTH, LONG, SIGNED] INITIAL (LONG (%LENGTH-1 %IF %LENGTH GTR 1 %THEN , %REMAINING %FI)); sys$cmkrnl (routine_name, arglist) END %; ! IOGEN$BUILD_ABM ! ! This macro builds an autoconfiguration bus mapping table. This table ! associates adapter types with autoconfiguration routines to invoke ! when an ADP with that type is found. The table has the following format: ! ! +-----------------------+ ! | Adapter type | ! +-----------------------+ ! | Autoconfig routine | ! +-----------------------+ ! | Adapter type | ! +-----------------------+ ! | Autoconfig routine | ! +-----------------------+ ! | . | ! | . | ! +-----------------------+ ! | 0 | ! +-----------------------+ ! | 0 | ! +-----------------------+ ! ! A typical invocation of this macro is: ! ! IOGEN$BUILD_ABM (LASER_ABM, ! ! Adapter type Configuration routine ! ------------ --------------------- ! AT$_XMI, IOGEN$XMI_CONFIG, ! AT$_FBUS, IOGEN$FBUS_CONFIG); MACRO iogen$build_abm (table_name, adap_type, config_routine) [] = %IF %COUNT EQL 0 %THEN bind table_name = uplit long (adap_type, config_routine, iogen$build_abm (table_name, %REMAINING) 0, 0); %ELSE adap_type, config_routine, iogen$build_abm (table_name, %REMAINING) %FI %; ! IOGEN$BUILD_CONFIG_TABLE ! ! The following macros build a dummy autoconfiguration table. It used ! to define the known devices for a bus adapter. Now it defines the ! hardware ID mask, and a single null entry (table termination). The ! actual table is created during init_io_db and the dummy table is ! replaced. See CONFIG_TABLE.SDL/R32/R64 for the table definition ! (it is no longer defined in this file). ! ! The table has a header with the following format: ! ! 31 0 ! +------------------------------+ ! | Hardware ID bitmask (31:0) | ! +------------------------------+ ! | Hardware ID bitmask (63:32) | ! +------------------------------+ ! ! The remainder is a dummy config table entry ! with the hardware ID, Driver name, and device name ! set to zero. It also has the adp type and a flag ! that indicates that the table is a dummy table. ! ! 31 0 ! +-----------------------+ ! | Hardware ID (31:00) | = 0 ! +-----------------------+ ! | Hardware ID (63:32) | = 0 ! +-----------------------+ ! | Driver name (ascid) | = 0 ! +-----------------------+ ! | Device name (ascii) | = 0 ! +-----------------------+ ! | ... | ! +-----------------------+ ! ! A typical invocation of this macro is: ! ! BUILD_CONFIG_TABLE (XMI_CONFIG_TABLE, hw_id_mask_lo, hw_id_mask_hi); ! MACRO iogen$build_config_table ( table_name, hw_id_mask_lo, hw_id_mask_hi, adp_type) = GLOBAL table_name : ALIAS BLOCKVECTOR [1, iogen_cfg_tbl$k_entry_size+iogen_cfg_tbl$k_header_len, BYTE] INITIAL (LONG (hw_id_mask_lo, ! Hardware ID mask lo 32 hw_id_mask_hi, ! hi 32 0, ! 0 hw_id_lo 0, ! 4 hw_id_hi 0, ! 8 driver_name 0, ! 12 devnam 0, ! 16 vector_count 0, ! 20 vector_align 0, ! 24 num_units iogen_cfg_tbl$m_no_table, ! 28 flags 0, ! 32 description adp_type, ! 36 adp_type 0, ! 40 assoc_drv 0, ! 44 dtype 0, ! 48 boot_class 0, ! 52 boot_flags 0, ! 56 private 0, ! 60 avail 0, ! 64 avail2 0)); ! 68 fill %; ! ! ---- < End of module IOGEN_MACROS.REQ - 30-MAR-2010 16:38:57.59 > - ! ! OBJREQMAC.REQ - REQUIRE FILE FOR BLISS-32 INTERFACE TO OBJECT MANAGEMENT ! Version 'X-2' ! !**************************************************************************** !* * !* COPYRIGHT (c) 1978, 1980, 1982, 1984, 1990 BY * !* DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS. * !* ALL RIGHTS RESERVED. * !* * !* THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED * !* ONLY IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE AND WITH THE * !* INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR ANY OTHER * !* COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY * !* OTHER PERSON. NO TITLE TO AND OWNERSHIP OF THE SOFTWARE IS HEREBY * !* TRANSFERRED. * !* * !* THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE * !* AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT * !* CORPORATION. * !* * !* DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS * !* SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL. * !* * !* * !**************************************************************************** ! ! ! !++ ! ! FACILITY: Security Class Registration Interface from BLISS ! ! FUNCTIONAL DESCRIPTION: ! ! This module defines the macros that are used to generate ! the template structures used during the registration of ! a security object class. ! ! ENVIRONMENT: No specific constraints. ! ! AUTHOR: Scott A. Shurts CREATION DATE: 18-Jun-1990 ! ! MODIFIED BY: ! ! X-2 CEG Clair Grant 12-MAR-1993 ! Remove use of obsolete symbol NSA$K_ACC_LENGTH from ! $ACCESS_VECTOR macro. ! ! X-1 CEG Clair Grant 25-JUN-1992 ! Initial port to Alpha, no changes. ! ! X-2 CRB0603 Colin R. Blake 18-DEC-1991 12:50:32.39 ! This is the C2 version being inserted into mainline. ! ! X-1T3A1 SAD0170 Stuart A. Davidson 26-NOV-1991 ! Tranquility OSR support. ! ! T-4 SAD0138 Stuart A. Davidson 4-OCT-1991 ! ORB flags field is a word (not a byte). ! ! T-2 SAD Stuart A. Davidson 13-MAY-1991 ! Make all OSRs but PREPROCESS be optional. ! Use ORB$L_ORIGINAL_ORB for template list. ! ! X-3T1 SAD0109 Stuart A. Davidson 11-MAR-1991 ! remove TLV_TO_ORB ! ! X-3 SAS0233 Scott A. Shurts 7-Oct-1990 ! Add TLV_TO_ORB and FIXUP_BTIME_ORBS to $osr_vector. ! Also make GET_ITEM and SET_ITEM optional. ! ! X-2 SAS0227 Scott A. Shurts 8-Aug-1990 ! Remove embedded ARM$V_ processing to allow any ! symbol/value input (ie. lps or customers) ! Also, include the support for multiple template (default) ! object_rights by adding the NEXT and OBJNAM parameters. ! Add check_access OSR routine and make access_exception ! optional. ! !-- !++ ! $BLD_BITMASK ! Takes a list of bitnames and then constructs their mask name ! based on the PREFIX parameter and creates a mask by a logical ! OR. !-- MACRO $BLD_BITMASK (PREFIX, BIT_NAME) [] = %IF %NULL (PREFIX) %THEN BIT_NAME $BLD_BITMASK_OR (%REMAINING) $BLD_BITMASK (PREFIX, %REMAINING) %ELSE %NAME (PREFIX, '$M_', BIT_NAME) $BLD_BITMASK_OR (%REMAINING) $BLD_BITMASK (PREFIX, %REMAINING) %FI %, $BLD_BITMASK_OR [] = OR %; !++ ! ! $ACCESS_BITNAMES ! Creates the bitname translation table from the list ! access names and address of ASCID strings. The translation table is a ! vector or 32 longwords with the access name symbol used as an ! index into the table of ASCID string addresses. ! !-- MACRO $ACCESS_BITNAMES (ACCESS_PAIR) = VECTOR [32] PRESET ( $ACCESS_BITS (ACCESS_PAIR) %IF %LENGTH-1 GTR 0 %THEN, $ACCESS_BITS (%REMAINING) %FI) %, $ACCESS_BITS (ACCESS_PAIR) [] = $ACCESS_ENTRY (%REMOVE (ACCESS_PAIR)) %IF %LENGTH-1 GTR 0 %THEN, $ACCESS_BITS (%REMAINING) %FI %, $ACCESS_ENTRY (INDEX, STRING_ADDR) = [INDEX] = STRING_ADDR %; !++ ! ! $ACCESS_VECTOR ! Declare an Access Vector for either audits or alarms. ! This vector is used to determine if audits/alarms are generated ! as the result of an access attempt. !-- KEYWORDMACRO $ACCESS_VECTOR ( SUCCESS, FAILURE, SYSPRV, BYPASS, UPGRADE, DOWNGRADE, GRPPRV, READALL, OTHER ) = BLOCK [NSA$K_ACCESS_LENGTH+12, BYTE] PRESET ( [NSA$L_ACC_FAILURE] = %IF %NULL( FAILURE ) %THEN 0 %ELSE $BLD_BITMASK (, %REMOVE (FAILURE)) %FI, [NSA$L_ACC_SUCCESS] = %IF %NULL( SUCCESS ) %THEN 0 %ELSE $BLD_BITMASK (, %REMOVE (SUCCESS)) %FI, [NSA$L_ACC_SYSPRV] = %IF %NULL( SYSPRV ) %THEN 0 %ELSE $BLD_BITMASK (, %REMOVE (SYSPRV)) %FI, [NSA$L_ACC_BYPASS] = %IF %NULL( BYPASS ) %THEN 0 %ELSE $BLD_BITMASK (, %REMOVE (BYPASS)) %FI, [NSA$L_ACC_UPGRADE] = %IF %NULL( UPGRADE ) %THEN 0 %ELSE $BLD_BITMASK (, %REMOVE (UPGRADE)) %FI, [NSA$L_ACC_DOWNGRADE] = %IF %NULL( DOWNGRADE ) %THEN 0 %ELSE $BLD_BITMASK (, %REMOVE (DOWNGRADE)) %FI, [NSA$L_ACC_READALL] = %IF %NULL( READALL ) %THEN 0 %ELSE $BLD_BITMASK (, %REMOVE (READALL)) %FI, [NSA$L_ACC_OTHER] = %IF %NULL( OTHER ) %THEN 0 %ELSE $BLD_BITMASK (, %REMOVE (OTHER)) %FI ) %; !++ ! ! $OBJECT_CLASS ! Creates a template Object Class Block (OCB) used for registration ! requests (EXE$REGISTER_SECURITY_CLASS). ! !-- KEYWORDMACRO $OBJECT_CLASS ( FLAGS, DEFAULT_ORB = 0, CLASS_ORB = 0, ACCESS_BITNAMES = 0, ACCESS_AUDITS = 0, ACCESS_ALARMS = 0 ) = BLOCK [OCB$K_LENGTH, BYTE] PRESET ( [OCB$L_FLAGS] = %IF %NULL( FLAGS ) %THEN 0 %ELSE $BLD_BITMASK (OCB, %REMOVE (FLAGS)) %FI, [OCB$L_DEFAULT_ORB] = DEFAULT_ORB, [OCB$L_CLASS_ORB] = CLASS_ORB, [OCB$L_ACCESS_BITNAMES] = ACCESS_BITNAMES, [OCB$AR_ACC_AUDITS] = ACCESS_AUDITS, [OCB$AR_ACC_ALARMS] = ACCESS_ALARMS ) %; !++ ! ! $OBJECT_RIGHTS ! Creates a template Object Rights Block (ORB) used for registration ! requests (EXE$REGISTER_SECURITY_CLASS). ! !-- KEYWORDMACRO $OBJECT_RIGHTS ( OWNER = 0, FLAGS, SYS_PROT, OWN_PROT, GRP_PROT, WOR_PROT, OBJNAM, NEXT = 0, OBJECT_SPECIFIC = 0 ) = BLOCK [ORB$K_LENGTH, BYTE] PRESET ( [ORB$L_ORIGINAL_ORB] = NEXT, [ORB$L_OBJECT_SPECIFIC] = OBJECT_SPECIFIC, [ORB$L_OWNER] = OWNER, [ORB$W_FLAGS] = %IF %NULL( FLAGS ) %THEN 0 %ELSE $BLD_BITMASK (ORB, %REMOVE (FLAGS)) %FI, [ORB$L_SYS_PROT] = %IF %NULL( SYS_PROT ) %THEN -1 %ELSE NOT ($BLD_BITMASK (ARM, %REMOVE (SYS_PROT))) %FI, [ORB$L_OWN_PROT] = %IF %NULL( OWN_PROT ) %THEN -1 %ELSE NOT ($BLD_BITMASK (ARM, %REMOVE (OWN_PROT))) %FI, [ORB$L_GRP_PROT] = %IF %NULL( GRP_PROT ) %THEN -1 %ELSE NOT ($BLD_BITMASK (ARM, %REMOVE (GRP_PROT))) %FI, [ORB$L_WOR_PROT] = %IF %NULL( WOR_PROT ) %THEN -1 %ELSE NOT ($BLD_BITMASK (ARM, %REMOVE (WOR_PROT))) %FI , [ORB$L_NAME_POINTER] = OBJNAM ) %; !++ ! ! $OSR_VECTOR ! Creates the Object Support Routine Vector for dispatching. The ! OSRV stucture is used by the security subsystem to dispatch to ! various class specific processing routines. ! !-- KEYWORDMACRO $OSR_VECTOR ( ACCESS_EXCEPTION = 0, CLONE_PROFILE, GET_ITEM = 0, PREPROCESS, RUNDOWN = 0, SET_ITEM = 0, UPDATE_PROFILE = 0, CHECK_ACCESS = 0, FIXUP_BTIME_ORBS = 0, RESOLVE_ACL = 0, READ_PROFILE = 0, SET_TRANQUILITY = 0, CLEAR_TRANQUILITY = 0 ) = BLOCK [OSRV$K_LENGTH, BYTE] PRESET ( [OSRV$L_ACCESS_EXCEPTION] = ACCESS_EXCEPTION, [OSRV$L_CLONE_PROFILE] = CLONE_PROFILE, [OSRV$L_GET_ITEM] = GET_ITEM, [OSRV$L_PREPROCESS] = PREPROCESS, [OSRV$L_RUNDOWN] = RUNDOWN, [OSRV$L_SET_ITEM] = SET_ITEM, [OSRV$L_UPDATE_PROFILE] = UPDATE_PROFILE, [OSRV$L_CHECK_ACCESS] = CHECK_ACCESS, [OSRV$L_FIXUP_BTIME_ORBS] = FIXUP_BTIME_ORBS, [OSRV$L_RESOLVE_ACL] = RESOLVE_ACL, [OSRV$L_READ_PROFILE] = READ_PROFILE, [OSRV$L_SET_TRANQUILITY] = SET_TRANQUILITY, [OSRV$L_CLEAR_TRANQUILITY] = CLEAR_TRANQUILITY ) %; ! ! ---- < End of module OBJREGMAC.REQ - 30-MAR-2010 16:38:59.04 > - ! ! Macros used for security support ! ! Version: 'X-2' ! ! Copyright (c) Digital Equipment Corporation, 1995-1997. All Rights Reserved. ! Unpublished rights reserved under the copyright laws of the United States. ! ! The software contained on this media is proprietary to and embodies the ! confidential technology of Digital Equipment Corporation. Possession, use, ! duplication or dissemination of the software and media is authorized only ! pursuant to a valid written license from Digital Equipment Corporation. ! ! RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the U.S. ! Government is subject to restrictions as set forth in Subparagraph ! (c)(1)(ii) of DFARS 252.227-7013, or in FAR 52.227-19, as applicable. !++ ! FACILITY: ! ! LIB ! ! ABSTRACT: ! ! This module contains macros used in support of security. ! ! AUTHOR: Bill Davenport, CREATION DATE: 13-Sep-1995 ! ! MODIFIED BY: ! ! X-2 AJM61706 Andrew J. Moskal 18-Jul-1997 ! Fix type casting in ...AUDIT_ENABLED and ...PRVBIT_ENABLED macros. ! ! X-1 AJM Andrew J. Moskal 25-Feb-1997 ! Add FLAGS parameter to NSA$ASSUME_PERSONA linkage. ! ! Shuan Lin 14-Feb-1997 ! Mainline merge of Per-Thread Security support: (gen 19A6) ! ! X-1A7 Shuan Lin 7-Feb-1997 ! Remove the PARANOID stuff. ! Rewrite macro get_curpsb to call nsa$get_current_psb. ! Rewrite GET_CURPSB to support backward compatibility. ! ! X-1A3 Douglas Fyfe 20-NOV-1996 ! Add NSA$DELETE_PERSONA_LINKAGE ! ! X-1A2 WXD Bill Davenport 20-Aug-1996 ! Add linkages for EXE$CHKxxxACCES routines. ! ! X-1A1 AJM96061 Andrew J. Moskal 1-Jul-1996 ! In GET_CURPSB, don't check mode if persona is already active. ! ! X-1 WXD Bill Davenport 17-Jun-1996 ! Mainline merge of Per-Thread Security. ! Initial creation of module. ! !** !++ ! Routine linkages !-- linkage !+ ! Routines in module ARBS_AND_ORBS !- !+ ! Routines in module CHECK_PRIVILEGE.B32 !- !+ ! Routines in module CLASS_SUPPORT !- !+ ! Routines in module PERSONA_SUPPORT !- NSA$GET_CURRENT_PSB_LINKAGE = ! get the current persona JSB (REGISTER = 0; ! ktb REGISTER = 1), ! psb NSA$ASSUME_PERSONA_LINKAGE = ! Assume a specific persona JSB (REGISTER = 1, ! Persona id REGISTER = 4, ! Ktb REGISTER = 3, ! Acmode REGISTER = 2), ! Flags NSA$CLONE_PSB_LINKAGE = ! Clone a persona block JSB (REGISTER = 5, ! Persona block address REGISTER = 1; ! Access mode of cloned persona block REGISTER = 2), ! Address of cloned persona block NSA$DEREFERENCE_PSB_LINKAGE = ! Dereference a persona block JSB (REGISTER = 5), ! Persona block address NSA$FREE_PSB_LINKAGE = ! Free a persona block JSB (REGISTER = 5), ! Persona block address NSA$GET_PSB_LINKAGE = ! Get a persona block JSB (REGISTER = 0; ! Size REGISTER = 5), ! Address of allocated persona block NSA$EXPAND_PERSONA_ARRAY_LINKAGE = ! Expand P1-space persona array JSB (), NSA$INITIALIZE_PERSONA_ARRAY_LINKAGE = ! Initialize P1-space persona array JSB (REGISTER = 5), ! Address of natural persona block NSA$LAZY_PERSONA_ASSUME_LINKAGE = ! Perform lazy persona assume JSB (), NSA$LOOKUP_PERSONA_LINKAGE = ! Lookup persona by id JSB (REGISTER = 1, ! Persona id REGISTER = 3; ! Acmode REGISTER = 5), ! Address of persona block NSA$REFERENCE_PSB_LINKAGE = ! Reference a persona block JSB (REGISTER = 5), ! Address of persona block NSA$RELEASE_PERSONA_ARRAY_LINKAGE = ! Release P1-space persona array JSB (), NSA$REMOVE_PERSONA_LINKAGE = ! Remove a persona from the persona array JSB (REGISTER = 5), ! Address of persona block NSA$DELETE_PERSONA_LINKAGE = ! Remove a persona from the persona array JSB (REGISTER = 5), ! Address of persona block NSA$STORE_PERSONA_LINKAGE = ! Store a persona in the persona array JSB (REGISTER = 5; ! Address of persona block REGISTER = 1), ! Persona id !+ ! Routines in module RIGHTS_SUPPORT !- NSA$ADD_RIGHTS_IDENTIFIER_LINKAGE = ! Add rights identifier to chain JSB (REGISTER = 6, ! Address of rights chain REGISTER = 1, ! Rights identifier REGISTER = 0; ! Flags REGISTER = 3, ! Previous flags REGISTER = 2), ! Cloned rights chain address NSA$CLONE_RIGHTS_CHAIN_LINKAGE = ! Clone a rights chain JSB (REGISTER = 0; ! Rights chain address REGISTER = 2), ! Cloned rights chain address NSA$DEREFERENCE_RIGHTS_CHAIN_LINKAGE = ! Dereference a rights chain JSB (REGISTER = 6), ! Address of rights chain NSA$FIND_RIGHTS_IDENTIFIER_LINKAGE = ! Find rights identifier in chain JSB (REGISTER = 6, ! Address of rights chain REGISTER = 1; ! Rights identifier REGISTER = 2, ! Address of rights block containing identifier REGISTER = 3, ! Index of identifier in block REGISTER = 4), ! Address of block with free space NSA$FREE_RIGHTS_CHAIN_LINKAGE = ! Free a rights block JSB (REGISTER = 6), ! Address of rights chain NSA$GET_RIGHTS_BLOCK_LINKAGE = ! Get a rights block JSB (REGISTER = 0; REGISTER = 1), NSA$REFERENCE_RIGHTS_CHAIN_LINKAGE = ! Reference a rights chain JSB (REGISTER = 6), ! Address of rights chain NSA$REMOVE_RIGHTS_IDENTIFIER_LINKAGE = ! Remove rights identifier from chain JSB (REGISTER = 6, ! Address of rights chain REGISTER = 1; ! Rights identifier REGISTER = 3, ! Previous flags REGISTER = 2), ! Cloned rights chain address !+ ! Routines in module SYSCHKPRO !- EXE$CHKPRO_INT_LINKAGE = JSB (REGISTER = 0, ! address of ARB REGISTER = 1, ! address of ORB REGISTER = 2, ! address of CHPCTL REGISTER = 3), ! address of CHPRET ! ********* Routines where ? EXE$CLEANUP_ARB_LINKAGE = JSB (REGISTER = 0), ! address of ARB to cleanup EXE$CLEANUP_ORB_LINKAGE= JSB (REGISTER = 0, ! orb REGISTER = 2), ! deallocation routine EXE$CLONE_ARB_LINKAGE = JSB (REGISTER = 0; ! address of source ARB REGISTER = 1), ! address of cloned ARB EXE$COPY_ARB_LINKAGE = JSB (REGISTER = 0; ! address of source ARB REGISTER = 1), ! address of cloned ARB EXE$COPY_ORB_LINKAGE = JSB (REGISTER = 0; ! address of source ORB REGISTER = 1), ! address of cloned ORB EXE$CREATE_ARB_LINKAGE = JSB (; ! no input arguments REGISTER = 1), ! address of new ARB EXE$CREATE_DEFAULT_ORB_LINKAGE = JSB (REGISTER = 0; ! address of OCB REGISTER = 1), ! address of cloned ORB EXE$CREATE_ORB_LINKAGE = JSB (; ! no input arguments REGISTER = 1), ! address of new ORB EXE$DELETE_ARB_LINKAGE = JSB (REGISTER = 0), ! address of ARB to delete EXE$DELETE_ORB_LINKAGE = JSB (REGISTER = 0, ! address of ORB to delete REGISTER = 2), ! deallocation routine EXE$LOCATE_SEC_CLASS_LINKAGE = JSB (REGISTER = 1, ! address of class_name REGISTER = 2), ! address of OCB EXE$REGISTER_SEC_CLASS_LINKAGE = JSB (REGISTER = 1, ! address of class_name REGISTER = 3, ! address of class type REGISTER = 4, ! address of osrv REGISTER = 5, ! address of object_class template REGISTER = 2), ! address of OCB EXE$RESOLVE_ACL_LINKAGE = JSB (REGISTER = 1), ! ORB to resolve EXE$SEARCH_RIGHT_LINKAGE = JSB (REGISTER = 2, ! identifier being sought REGISTER = 4; ! address of the rights segment descriptors REGISTER = 1, ! address of the ID quadword (if found) REGISTER = 5), ! address of the rights segment containing the ID (if found) NSA$ALLOCATE_NSAB_LINKAGE = JSB (REGISTER = 2; ! size of required NSAB REGISTER = 3), ! actual address of NSAB NSA$AUDIT_EVENT_LINKAGE = JSB (REGISTER = 0, ! address of NSAB REGISTER = 4) : ! source PCB PRESERVE (2,3,4,5,6,7,8,9,10,11), NSA$AUDIT_FAILURE_LINKAGE = JSB (REGISTER = 0, ! failing status REGISTER = 1), ! audit flags NSA$CHECK_AUDIT_LINKAGE = JSB (REGISTER = 0, ! protection check status REGISTER = 1, ! event type and subtype REGISTER = 2, ! address of CHPCTL block REGISTER = 3, ! address of CHPRET block REGISTER = 4) : ! address of PCB PRESERVE (4,5,6,7,8,9,10,11), NSA$CHECK_PRIVILEGE_LINKAGE = JSB (REGISTER = 0, ! privilege bit, privilege mask address, or identifier address REGISTER = 1, ! address of control structure ($NSAIFPDEF) REGISTER = 4), ! PCB address of process to check (0 = use current process) NSA$COMPUTE_SUMMARY_LINKAGE = JSB (REGISTER = 4), ! PCB address (0 = use current PCB) NSA$DEACCESS_AUDIT_LINKAGE = JSB (REGISTER = 0, ! deaccess key REGISTER = 2), ! DAP flags NSA$DEALLOCATE_NSAB_LINKAGE = JSB (REGISTER = 0), ! address of NSAB to deallocate NSA$DEVICE_AUDIT_LINKAGE = JSB (REGISTER = 0, ! flags: 0 = creation, 1 = deletion REGISTER = 5), ! UCB address NSA$ITMLST_TO_PKTLST_LINKAGE = JSB (REGISTER = 2, ! address of item list REGISTER = 3, ! address of buffer to receive packet list REGISTER = 4, ! address of NSAS (with journal names) REGISTER = 5), ! address of username descriptor NSA$QUEUE_DEACCESS_LINKAGE = JSB (REGISTER = 1, ! alarm/audit mask REGISTER = 10, ! address of CHPCTL (with deaccess key) REGISTER = 11), ! address of CHPRET (with alarms) NSA$RESOURCE_LINKAGE = JSB (REGISTER = 0, ! reason mask REGISTER = 1) : ! audit flags ($NSADEF) PRESERVE (2,3,4,5,6,7,8,9,10,11), NSA$SIZE_NSAB_LINKAGE = JSB (REGISTER = 2, ! address of item list REGISTER = 3), ! NSAS structure address NSA$STRIP_IMAGE_PRIVS_LINKAGE = JSB (REGISTER = 0, ! address of privilege mask REGISTER = 4), ! associated PCB address NSA$VALIDATE_JOURNAL_LINKAGE = JSB (REGISTER = 2, ! journal type flag REGISTER = 3, ! address of journal name descriptor REGISTER = 4, ! address of username descriptor REGISTER = 5), ! address of journal name descriptor OSR$ACCESS_EXCEPTION_LINKAGE = JSB (REGISTER = 8, ! address of ARB REGISTER = 9, ! address of ORB REGISTER = 10, ! address of CHPCTL REGISTER = 11, ! address of CHPRET REGISTER = 0), ! input status EXE$CHECKCLASS_LINKAGE = JSB ( REGISTER = 2, ! Subject's privilege mask REGISTER = 3, ! Access type REGISTER = 4, ! Subject's classification REGISTER = 5, ! Object's MIN classification REGISTER = 6; ! Object's MAX classification REGISTER = 1 ), ! Privileges used EXE$ARB_TO_PSB_LINKAGE = JSB (REGISTER = 0; ! ARB address passed in REGISTER = 1), ! Pointer location for PSB address being passed back EXE$PSB_TO_ARB_LINKAGE = JSB (REGISTER = 5, ! Pointer to PSB REGISTER = 1), ! Pointer to ARB EXE$SEARCH_RIGHTS_ARRAY_LINKAGE = JSB (REGISTER = 2, ! identifier being sought REGISTER = 4; ! address of PSB to search REGISTER = 1, ! address of the ID quadword (if found) REGISTER = 5), ! address of the rights block containing the ID (if found) ! Check access protection routines (common linkage): ! ! EXE$CHKCREACCES - Check create access ! EXE$CHKDELACCES - Check delete access ! EXE$CHKLOGACCES - Check logical I/O function access ! EXE$CHKPHYACCES - Check physical I/O function access ! EXE$CHKRDACCES - Check read access ! EXE$CHKWRTACCES - Check write access ! EXE$CHKEXEACCES - Check execute access (implied by read access) ! ! These routines may be called in one of two vastly different ways: ! ! Using PSB and ORB (preferred mechanism): ! R0 = Address of subject's persona block (PSB) ! R1 = Address of object's object rights block (ORB) ! R5 = 0 ! ! Using PCB and UCB (old style for backwards compatibility): ! R4 = Address of subject's process control block (PCB) ! R5 = Address of object's unit control block (UCB) ! EXE$CHKACCESS_PSB_LINKAGE = JSB (REGISTER = 0, ! PSB address REGISTER = 1, ! ORB address REGISTER = 5): ! Zero NOPRESERVE (1) PRESERVE (2,3,4,5,6,7,8,9,10,11), EXE$CHKACCESS_LINKAGE = JSB (REGISTER = 4, ! PCB address REGISTER = 5): ! UCB address NOPRESERVE (1) PRESERVE (2,3,4,5,6,7,8,9,10,11); !++ ! D E S C R I P T I O N ! ===================== ! Audit control macros. These macros are used to temporarily disable ! and enable security auditing for the current persona. The SAVAUD ! parameter can be used to capture the current audit state for later ! restoration by the $RESTORE_AUDIT macro. These macros may be called ! in any mode, but require CMKRNL if the caller is in other than EXEC ! or KERNEL mode. ! ! The following is the intended usage style for these macros: ! ! local ! savedAudit : long, ! status : long; ! ! if (status = $psb$disable_audit (savedAudit = savedAudit)) ! then ! begin ! ... ! $psb$restore_audit (savedAudit = savedAudit); ! end ! else ! persona assume error; ! ! N O T E S ! ========= ! These macros operate on the current persona. Failure to take ! appropriate steps to localize this operation (such as first creating ! a cloned persona) will result in leakage of the actions of this macro ! to all other execution threads sharing this persona. ! ! Since these macros operate on the current persona, the most efficient ! argument that can be supplied by a caller is the psb argument. ! If the psb argument is omitted, then the next most efficient ! arguments (in order of preference) are the ktb and pcb arguments. ! ! The acmode argument should be supplied if any lazy assume performed ! by get_curpsb (used if psb is omitted) needs to be performed in the ! context of a different mode other than the previous execution mode. ! ! The currentMode argument should be supplied if a macro is being invoked ! in other than KERNEL mode. Note that not all macros support being ! used in an outer mode. All macros will report an error if they are ! invoked with a currentMode they don't support. ! ! U S A G E ! ========= ! $PSB$DISABLE_AUDIT Increment NOAUDIT count to disable audits ! ! savedAudit longword to store current NOAUDIT value ! psb optional PSB (default is current persona) ! ktb optional KTB (default is current kernel thread) ! pcb optional PCB (default is current process PCB) ! acmode optional access mode for lazy assume (default is PREVIOUS) ! currentMode optional current mode (default is KERNEL) ! ! $PSB$RESTORE_AUDIT Enable or restore NOAUDIT count ! ! savedAudit longword to restore current NOAUDIT value ! psb optional PSB (default is current persona) ! ktb optional KTB (default is current kernel thread) ! pcb optional PCB (default is current process PCB) ! acmode optional access mode for lazy assume (default is PREVIOUS) ! currentMode optional current mode (default is KERNEL) ! ! $PSB$ENABLE_AUDIT Decrement NOAUDIT count to enable audits ! ! savedAudit longword to store current NOAUDIT value ! psb optional PSB (default is current persona) ! ktb optional KTB (default is current kernel thread) ! pcb optional PCB (default is current process PCB) ! acmode optional access mode for lazy assume (default is PREVIOUS) ! currentMode optional current mode (default is KERNEL) !-- keywordmacro $psb$disable_audit (savedAudit, psb, ktb, pcb, acmode, currentMode = KERNEL) = begin ! Save direction of audit restoration savedAudit = -1; ! Perform the modificaton to audit counter $psb$restore_audit (%quote savedAudit = savedAudit, %quote psb = psb, %quote ktb = ktb, %quote pcb = pcb, %quote acmode = acmode, %quote currentMode = currentMode) end %; keywordmacro $psb$restore_audit (savedAudit, psb, ktb, pcb, acmode, currentMode = KERNEL) = begin ! Perform the modificaton to audit counter %if %identical (currentMode, kernel) %then $$$internal$$$action_psb (modify_audit, savedAudit, 0, 0, 0, psb, ktb, pcb, acmode, currentMode) %else %if %identical (currentMode, exec) or %identical (currentMode, supervisor) or %identical (currentMode, user) or %identical (currentMode, unknown) %then external routine NSA$MODIFY_AUDIT : addressing_mode(general); ! Call kernel routine to modify audit counter $kernel_call (NSA$MODIFY_AUDIT, savedAudit) %else %error ('Invalid currentMode argument in $psb$restore_audit macro invocation') %fi %fi end %; keywordmacro $psb$enable_audit (savedAudit, psb, ktb, pcb, acmode, currentMode = KERNEL) = begin ! Save direction of audit restoration savedAudit = 1; ! Perform the modificaton to audit counter $psb$restore_audit (%quote savedAudit = savedAudit, %quote psb = psb, %quote ktb = ktb, %quote pcb = pcb, %quote acmode = acmode, %quote currentMode = currentMode) end %; !++ ! Macros for compatibility with older definitions !-- macro $disable_audit (savedAudit) = $psb$disable_audit (%quote savedAudit = savedAudit, currentMode = UNKNOWN) %; macro $restore_audit (savedAudit) = $psb$restore_audit (%quote savedAudit = savedAudit, currentMode = UNKNOWN) %; macro $enable_audit (savedAudit) = $psb$enable_audit (%quote savedAudit = savedAudit, currentMode = UNKNOWN) %; !++ ! Helper macro for $psb$restore_audit and $$$internal$$$action_psb macros !-- macro $$$internal$$$modify_audit (ktb, psb, currentMode, savedAudit, dummy1, dummy2, dummy3) = begin external CTL$GL_PERSONA_USERCOUNT : long; ! Modify auditing for this persona ! ! The purpose of the following test is to allow only an enable ! of auditing to take place if auditing is currently disabled, ! and to allow a disable of auditing to take place anytime. if (.psb[PSB$L_NOAUDIT] neq 0) or (.savedAudit eql -1) then begin psb[PSB$L_NOAUDIT] = .psb[PSB$L_NOAUDIT] - .savedAudit; ! Set up correct state for corresponding restore savedAudit = -.savedAudit; ! update the ARB if the current PSB is the only one in ! user node if (.CTL$GL_PERSONA_USERCOUNT LEQ 1) and (.psb[PSB$L_MODE] EQL PSL$C_USER) then BEGIN local pcb : ref block [,byte]; pcb = .ktb[KTB$L_PCB]; pcb[PCB$L_NOAUDIT] = .psb[PSB$L_NOAUDIT]; END; end else savedAudit = 0; ! Return successful status code SS$_NORMAL end %; !++ ! D E S C R I P T I O N ! ===================== ! Audit test macro. This macro is used to test the current state of ! auditing for the current persona. Using this test for an invalid ! persona is treated as if auditing were enabled. ! ! The following is the intended usage style for this macro: ! ! if $psb$audit_enabled (...) ! then ! ... ! ! N O T E S ! ========= ! These macros operate on the current persona. ! ! Since these macros operate on the current persona, the most efficient ! argument that can be supplied by a caller is the PSB argument. ! If the PSB argument is omitted, then the next most efficient ! arguments (in order of preference) are the KTB and PCB arguments. ! ! The acmode argument should be supplied if any lazy assume performed ! by get_curpsb (used if psb is omitted) needs to be performed in the ! context of a different mode other than the previous execution mode. ! ! The currentMode argument should be supplied if a macro is being invoked ! in other than KERNEL mode. Note that not all macros support being ! used in an outer mode. All macros will report an error if they are ! invoked with a currentMode they don't support. ! ! U S A G E ! ========= ! $PSB$AUDIT_ENABLED Test for auditing enabled ! ! psb optional PSB (default is current persona) ! ktb optional KTB (default is current kernel thread) ! pcb optional PCB (default is current process PCB) ! acmode optional access mode for lazy assume (default is PREVIOUS) ! currentMode optional current mode (default is KERNEL) !-- keywordmacro $psb$audit_enabled (psb, ktb, pcb, acmode, currentMode = KERNEL) = begin %if %identical (currentMode, kernel) or %identical (currentMode, exec) %then ! Pick up pointer to current persona block %if %null (psb) %then local $$$psb$$$ : ref block[,byte]; if get_curpsb (%quote psb = $$$psb$$$, %quote ktb = ktb, %quote pcb = pcb, %quote acmode = acmode, %quote currentMode = currentMode) then (.$$$psb$$$[PSB$L_NOAUDIT] eql 0) ! On error, claim auditing is enabled else 1 %else (.block[psb, PSB$L_NOAUDIT; , byte] eql 0) %fi %else %error ('Invalid currentMode argument in $psb$audit_enabled macro invocation') %fi end %; !++ ! Macros for compatibility with older definitions !-- keywordmacro $audit_enabled (psb, ktb, acmode, currentMode = KERNEL) = $psb$audit_enabled (%quote psb = psb, %quote ktb = ktb, %quote acmode = acmode, %quote currentMode = currentMode) %; !++ ! Auditing helper macros. !-- macro $$translate_flags_to_nsap(flag)[] = %name ('NSAP$M_',flag) $$flags_or(%remaining) $$translate_flags_to_nsap(%remaining) %, $$translate_flags_to_nsa(flag)[] = %name ('NSA$M_',flag) $$flags_or(%remaining) $$translate_flags_to_nsa(%remaining) %, $$flags_or[] = or %; !++ ! D E S C R I P T I O N ! ===================== ! Privilege control macros. These macros are used for temporary ! enabling and disabling of privileges for the current persona. ! ! The following is the intended usage style for these macros: ! ! local ! savedPrivs : vector [2,long], ! status : long; ! ! if (status = $psb$enable_privileges (priv = CMKRNL, savedPriv = savedPrivs)) ! then ! begin ! ... ! $psb$restore_privileges (savedPriv = savedPriv); ! end ! else ! persona assume error; ! ! N O T E S ! ========= ! These macros operate on the current persona. Failure to take ! appropriate steps to localize this operation (such as first creating ! a cloned persona) will result in leakage of the actions of this macro ! to all other execution threads sharing this persona. ! ! Since these macros operate on the current persona, the most efficient ! argument that can be supplied by a caller is the psb argument. ! If the psb argument is omitted, then the next most efficient ! arguments (in order of preference) are the ktb and pcb arguments. ! ! The acmode argument should be supplied if any lazy assume performed ! by get_curpsb (used if psb is omitted) needs to be performed in the ! context of a different mode other than the previous execution mode. ! ! The currentMode argument should be supplied if a macro is being invoked ! in other than KERNEL mode. Note that not all macros support being ! used in an outer mode. All macros will report an error if they are ! invoked with a currentMode they don't support. ! ! The priv argument (if present) is the name of a set of privilege bits ! to be enabled. Either this argument or the mask argument must be ! specified. ! ! The mask argument (if present) is the address of a quadword privilege ! mask containing bits to be enabled. Either this argument or the priv ! argument must be specified. ! ! The savedPriv argument is the address of a quadword in which to ! save the current privilege bit settings for later restoration. ! ! U S A G E ! ========= ! $PSB$ENABLE_PRIVILEGES Enable privileges ! ! priv optional named privilege bit(s) ! mask optional address of privileges mask ! savedPriv address of quadword to store privileges ! psb optional PSB (default is current persona) ! ktb optional KTB (default is current kernel thread) ! pcb optional PCB (default is current process PCB) ! acmode optional access mode for lazy assume (default is PREVIOUS) ! currentMode optional current mode (default is KERNEL) ! ! $PSB$RESTORE_PRIVILEGES Restore privileges ! ! savedPriv address of privileges being restored ! psb optional PSB (default is current persona) ! ktb optional KTB (default is current kernel thread) ! pcb optional PCB (default is current process PCB) ! acmode optional access mode for lazy assume (default is PREVIOUS) ! currentMode optional current mode (default is KERNEL) !-- keywordmacro $psb$enable_privilege (priv, mask, savedPriv, psb, ktb, pcb, acmode, currentMode = KERNEL) = begin %if %null (priv) and %null (mask) %then %error ('Missing argument in $psb$enable_privilege macro') %fi %if not %null (priv) and not %null (mask) %then %error ('Conflicting arguments in $psb$enable_privilege macro') %fi local $$$mask$$$ : vector[2,long]; ! Make a mask of privileges to be set %if not %null (priv) %then $privs_to_mask (priv, $$$mask$$$); %else $move_quad (mask, $$$mask$$$); %fi %if %identical (currentMode, kernel) %then $$$internal$$$action_psb (enable_privilege, $$$mask$$$, savedPriv, 0, 0, psb, ktb, pcb, acmode, currentMode) %else %error ('Invalid currentMode argument in $psb$enable_privilege macro invocation') %fi end %; keywordmacro $psb$restore_privilege (savedPriv, psb, ktb, pcb, acmode, currentMode = KERNEL) = begin %if %identical (currentMode, kernel) %then $$$internal$$$action_psb (restore_privilege, savedPriv, 0, 0, 0, psb, ktb, pcb, acmode, currentMode) %else %error ('Invalid currentMode argument in $psb$restore_privilege macro invocation') %fi end %; !++ ! Macros for compatibility with older definitions !-- keywordmacro $enable_privilege (priv, mask, savedPriv, psb, ktb, acmode, currentMode = KERNEL) = $psb$enable_privilege (%quote priv = priv, %quote mask = mask, %quote savedPriv = savedPriv, %quote psb = psb, %quote ktb = ktb, %quote acmode = acmode, %quote currentMode = currentMode) %; keywordmacro $restore_privilege (savedPriv, psb, ktb, acmode, currentMode = KERNEL) = $psb$restore_privilege (%quote savedPriv = savedPriv, %quote psb = psb, %quote ktb = ktb, %quote acmode = acmode, %quote currentMode = currentMode) %; !++ ! Helper macro for $psb$enable_privileges and $$$internal$$$action_psb macros !-- macro $$$internal$$$enable_privilege (ktb, psb, currentMode, mask, savedPriv, dummy3, dummy4) = begin external routine EXE$PERSONA_EXPORT_ARB : addressing_mode (general); ! Save a current copy of the privilege mask $move_quad (psb[PSB$Q_WORKPRIV], savedPriv); ! Set the privileges $or_quad (mask, psb[PSB$Q_WORKPRIV], psb[PSB$Q_WORKPRIV]); ! Export ARB if the current PSB is the only one in ! user node EXE$PERSONA_EXPORT_ARB (ISS$C_ARB_UNSPECIFIED); ! Return successful status code SS$_NORMAL end %; !++ ! Helper macro for $psb$restore_privileges and $$$internal$$$action_psb macros !-- macro $$$internal$$$restore_privilege (ktb, psb, currentMode, savedPriv, dummy2, dummy3, dummy4) = begin external routine EXE$PERSONA_EXPORT_ARB : addressing_mode (general); ! Restore the privilege mask from saved copy $move_quad (savedPriv, psb[PSB$Q_WORKPRIV]); ! Export ARB if the current PSB is the only one in ! user node EXE$PERSONA_EXPORT_ARB (ISS$C_ARB_UNSPECIFIED); ! Return successful status code SS$_NORMAL end %; !++ ! D E S C R I P T I O N ! ===================== ! Privilege test macro. This macro is used to test the state of ! privilege bits for the current persona. ! ! This privilege testing macro does not perform auditing of the use ! of privilege and should only be used in circumstances where an ! audit would be inappropriate (which are few). ! ! If more than a single privilege bit is being tested, then this macro ! will return TRUE if any of the privilege bits are enabled. ! ! The following is the intended usage style for this macro: ! ! if $psb$privilege_enabled (...) ! then ! ... ! ! N O T E S ! ========= ! These macros operate on the current persona. Failure to take ! appropriate steps to localize this operation (such as first creating ! a cloned persona) will result in leakage of the actions of this macro ! to all other execution threads sharing this persona. ! ! Since these macros operate on the current persona, the most efficient ! argument that can be supplied by a caller is the psb argument. ! If the psb argument is omitted, then the next most efficient ! arguments (in order of preference) are the ktb and pcb arguments. ! ! The acmode argument should be supplied if any lazy assume performed ! by get_curpsb (used if psb is omitted) needs to be performed in the ! context of a different mode other than the previous execution mode. ! ! The currentMode argument should be supplied if a macro is being invoked ! in other than KERNEL mode. Note that not all macros support being ! used in an outer mode. All macros will report an error if they are ! invoked with a currentMode they don't support. ! ! The priv argument (if present) is the name of the privilege being ! tested. Either this argument or the mask argument must be specified. ! ! The mask argument (if present) is the address of a quadword privilege ! mask containing bits to be tested. Either this argument or the priv ! argument must be specified. ! ! The sense argument specifies the sense of test to be performed when ! multiple privilege bits (via a mask) are specified. If set to ANY ! (the default), then the macro returns TRUE if any of the privilege ! bits in the mask are set. If set to ALL then all of the requested ! privileges bits must be set for the macro to return TRUE. ! ! U S A G E ! ========= ! $PSB$PRIVILEGE_ENABLED Privilege enabled test ! ! priv optional named privilege bit(s) ! mask optional address of privileges mask ! psb optional PSB (default is current persona) ! ktb optional KTB (default is current kernel thread) ! pcb optional PCB (default is current process PCB) ! acmode optional access mode for lazy assume (default is PREVIOUS) ! currentMode optional current mode (default is KERNEL) ! sense optional test sense (default is ANY) !-- keywordmacro $psb$privilege_enabled (priv, mask, psb, ktb, pcb, acmode, currentMode = KERNEL, sense = ANY) = begin %if %null (priv) and %null (mask) %then %error ('Missing argument in $psb$privilege_enabled macro') %fi %if not %null (priv) and not %null (mask) %then %error ('Conflicting arguments in $psb$privilege_enabled macro') %fi compiletime $$$prvmsk$$$ = 0; %if %declared (%quotename ('PRV$V_',priv)) %then %assign ($$$prvmsk$$$, 0) %else %assign ($$$prvmsk$$$, 1) %fi ! If multiple privs (or a mask) then set up a mask of bits %if $$$prvmsk$$$ %then local $$$mask$$$ : vector[2,long]; %if not %null (priv) %then $privs_to_mask (priv, $$$mask$$$); %else $move_quad (mask, $$$mask$$$); %fi %fi %if %identical (currentMode, kernel) or %identical (currentMode, exec) %then begin local $$$psb$$$ : ref block[,byte]; ! Pick up pointer to current persona block %if %null (psb) %then if get_curpsb (%quote psb = $$$psb$$$, %quote ktb = ktb, %quote pcb = pcb, %quote acmode = acmode, %quote currentMode = currentMode) then ! Testing just a single privilege bit? %if not $$$prvmsk$$$ %then $$$internal$$$prvbit_enabled (priv, $$$psb$$$) %else $$$internal$$$prvmsk_enabled ($$$mask$$$, $$$psb$$$, sense) %fi ! On error claim privilege not enabled else 0 %else $$$psb$$$ = psb; ! Testing just a single privilege bit? %if not $$$prvmsk$$$ %then $$$internal$$$prvbit_enabled (priv, $$$psb$$$) %else $$$internal$$$prvmsk_enabled ($$$mask$$$, $$$psb$$$, sense) %fi %fi end %else %if %identical (currentMode, supervisor) or %identical (currentMode, user) or %identical (currentMode, unknown) %then begin local $$$test$$$ : vector[2,long]; ! Pick up current privileges if $setprv (prvprv = $$$test$$$) then ! Testing just a single privilege bit? %if not $$$prvmsk$$$ %then .block[$$$test$$$, %name ('PRV$V_',priv); 8, byte] ! No, checking an entire mask of privilege bits %else begin ! And the mask with the computed privileges $and_quad ($$$mask$$$, $$$test$$$, $$$test$$$); ! If any of specified privileges remaining in mask then done (.$$$test$$$[0] neq 0) or (.$$$test$$$[1] neq 0) end %fi ! On error claim privilege not enabled else 0 end %else %error ('Invalid currentMode argument in $psb$privilege_enabled macro invocation') %fi %fi end %; !++ ! Macros for compatibility with older definitions !-- keywordmacro $privilege_enabled (priv, mask, psb, ktb, acmode, currentMode = KERNEL) = $psb$privilege_enabled (%quote priv = priv, %quote mask = mask, %quote psb = psb, %quote ktb = ktb, %quote acmode = acmode, %quote currentMode = currentMode) %; !++ ! Helper macros for $psb$privilege_enabled !-- macro $$$internal$$$prvbit_enabled (priv, psb) = begin (.block[psb[PSB$Q_WORKPRIV], %name ('PRV$V_',priv); 8, byte]) or (.block[psb[PSB$Q_IMAGE_WORKPRIV], %name ('PRV$V_',priv); 8, byte]) end %; macro $$$internal$$$prvmsk_enabled (mask, psb, sense) = begin local $$$test$$$ : vector[2,long]; ! Or together the work and image work privileges $or_quad (psb[PSB$Q_WORKPRIV], psb[PSB$Q_IMAGE_WORKPRIV], $$$test$$$); ! And the mask with the computed privileges $and_quad (mask, $$$test$$$, $$$test$$$); %if %identical (sense, ANY) %then ! If any of specified privileges remaining in mask then done (.$$$test$$$[0] neq 0) or (.$$$test$$$[1] neq 0) %else %if %identical (sense, ALL) %then ! If all of specified privileges remaining are what were ! requested then done (.$$$test$$$[0] eql .mask[0]) and (.$$$test$$$[1] eql .mask[1]) %else %error ('Invalid sense argument in $psb$privilege_enabled macro') %fi %fi end %; !+ ! Helper macros to construct a quadword privilege mask out of a named privilege list ! ! Usage: local ! privMask : vector[2,long] initial (long(0,0)); ! ! $privs_to_mask (cmkrnl, privMask); ! $privs_to_mask ((world,oper), privMask); !- macro $privs_to_mask (privs, mask) = begin vector[mask,0;,long] = $$set_privs_l (%remove (privs)); vector[mask,1;,long] = $$set_privs_h (%remove (privs)); end %; ! Helper macros for privilege mask contruction macro $$set_privs_l (priv_name)[] = ! If in first longword then or into the mask %if $byteoffset (%name ('PRV$V_', priv_name)) eql 0 %then %name ('PRV$M_', priv_name) $$set_privs_or (%remaining) $$set_privs_l (%remaining) ! otherwise skip privilege bit %else 0 $$set_privs_or (%remaining) $$set_privs_l (%remaining) %fi %, $$set_privs_h (priv_name)[] = ! If in second longword then or into the mask %if $byteoffset (%name ('PRV$V_', priv_name)) eql 4 %then 1 ^ $bitposition (%name ('PRV$V_', priv_name)) $$set_privs_or (%remaining) $$set_privs_h (%remaining) ! otherwise skip privilege bit %else 0 $$set_privs_or (%remaining) $$set_privs_h (%remaining) %fi %, $$set_privs_or [] = or %; !+ ! Macro to declare a data segment as a privilege mask. ! ! Usage: local ! privMask : $priv_mask(cmkrnl), ! twoPrivs : $priv_mask(setprv,security); !- macro $priv_mask (priv) = bitvector [64] %if %null (priv) %then initial (0, 0) %else preset ($$priv_bits (priv %if not %null (%remaining) %then , %remaining %fi)) %fi %, $$priv_bits [bitname] = [$bitposition(%name(prv$v_,bitname)) + $byteoffset(%name(prv$v_,bitname))*8] = 1 %; !+ ! ! Macro to construct an initializer (i.e., plit item) out of a named privilege list. ! ! Usage: ! ! plit ( ! $priv_value (cmkrnl), ! $priv_value (world,oper) ! ); ! !- macro ! $priv_value [] = ! 0 or $$priv_value_l (%remaining), ! 0 or $$priv_value_h (%remaining) ! %, $priv_value [] = $$set_privs_l (%remaining), $$set_privs_h (%remaining) %, $$priv_value_l [priv_name] = %if $byteoffset (%name ('PRV$V_', priv_name)) eql 0 %then 1 ^ $bitposition (%name ('PRV$V_', priv_name)) %else 0 %fi %, $$priv_value_h [priv_name] = %if $byteoffset (%name ('PRV$V_', priv_name)) eql 4 %then 1 ^ $bitposition (%name ('PRV$V_', priv_name)) %else 0 %fi %; !+ ! ! Macro to perform a simple privilege check with auditing. ! ! Usage: ! ! if (status = $has_priv (priv = world, message = world_1, itmlst = audit_list, acmode = exec)) ! then ! begin ! . ! . <> ! . ! end ! else ! return .status; ! !- keywordmacro $has_priv (priv, prvmsk, mask = current, message, msgcod, itmlst, altprv, flags, acmode = unknown) = %if %null (priv) and %null (prvmsk) %then %error ('Privilege name missing from call to $HAS_PRIV'); %fi %if %null (message) and %null (msgcod) %then %error ('Privilege audit message code not supplied to $HAS_PRIV'); %fi %if not %identical (mask, current) and not %identical (mask, process) and not %identical (mask, authorized) %then %error ('Invalid privilege location supplied to $HAS_PRIV - use CURRENT, PROCESS, or AUTHORIZED') %fi %if not %identical (acmode, kernel) and not %identical (acmode, exec) and not %identical (acmode, super) and not %identical (acmode, user) and not %identical (acmode, unknown) %then %error ('Invalid access mode supplied to $HAS_PRIV - use KERNEL, EXEC, SUPER, USER, or UNKNOWN') %fi begin %if not %null (priv) %then local $$$mask$$$ : $priv_mask (%remove(priv)); %fi %if %identical (acmode, unknown) %then local $$$psl$$$ : block[4,byte]; ! Pick up current PSL $$$psl$$$ = $getpsl(); ! If we're in kernel or exec mode just call NSA$CHECK_PRIVILEGE if .$$$psl$$$[PSL$V_CURMOD] lequ PSL$C_EXEC then begin %fi %if not %identical (acmode, super) and not %identical (acmode, user) %then external routine NSA$CHECK_PRIVILEGE : NSA$CHECK_PRIVILEGE_LINKAGE addressing_mode (general); ! Build the privilege check control block from the arguments. ! local nsap : block[nsap$k_length,byte] preset ( [nsap$l_flags] = nsap$m_internal or nsap$m_privmask or nsap$m_noprobe %if not %null (flags) %then or $$translate_flags_to_nsap (%remove (flags)) %fi %if %identical (mask, process) %then or nsap$m_procpriv %fi %if %identical (mask, authorized) %then or nsap$m_authpriv %fi %if not %null (altprv) %then or nsap$m_altpriv %fi %if not %null (message) %then , [nsap$l_message] = %name ('NSA$_',message) %else , [nsap$l_message] = .msgcod %fi %if not %null (itmlst) %then , [nsap$l_audit_list] = itmlst %fi ); %if not %null (altprv) %then $move_quad (altprv, nsap[nsap$q_altpriv]); %fi ! Call NSA$CHECK_PRIVILGE to perform the privilege check. ! nsa$check_privilege (%if not %null (priv) %then $$$mask$$$ %else prvmsk %fi, nsap, 0) %fi %if %identical (acmode, unknown) %then end ! Otherwise, use the $CHECK_PRIVILEGE system service to do the privilege check. ! else begin %fi %if not %identical (acmode, kernel) and not %identical (acmode, exec) %then local i : blockvector[2, itm$s_item, byte] ! a two entry item list preset ( [0, itm$w_itmcod] = nsa$_message, [0, itm$w_bufsiz] = 4, [0, itm$l_bufadr] = %if not %null (message) %then uplit (%name ('NSA$_',message)) %else msgcod %fi %if not %null (itmlst) %then , [1, itm$w_itmcod] = nsa$_chain , [1, itm$l_bufadr] = itmlst %fi ); ! Call the system service to perform the privilege check. ! $check_privilege ( efn = 31, prvadr = %if not %null (priv) %then $$$mask$$$ %else prvmsk %fi, %if not %null (altprv) %then %quote altprv = altprv, %fi %quote flags = nsa$m_internal %if not %null (flags) %then or $$translate_flags_to_nsa (%remove (flags)) %fi %if %identical (mask, authorized) %then or nsa$m_authpriv %fi %if %identical (mask, process) %then or nsa$m_procpriv %fi , %quote itmlst = i) %fi %if %identical (acmode, unknown) %then end %fi end %; !++ ! Account access macros. This macro provides the ability to read ! the account field of the persona block while hiding the overall ! structure of the implementation. ! ! The following is the intended usage style for this macro: ! ! if (status = $psb$get_account (...)) ! then ! ... ! else ! persona assume error; ! ! N O T E S ! ========= ! This macro operates on the current persona. ! ! Since this macro operates on the current persona, the most efficient ! argument that can be supplied by a caller is the psb argument. ! If the psb argument is omitted, then the next most efficient ! arguments (in order of preference) are the ktb and pcb arguments. ! ! The acmode argument should be supplied if any lazy assume performed ! by get_curpsb (used if psb is omitted) needs to be performed in the ! context of a different mode other than the previous execution mode. ! ! The currentMode argument should be supplied if a macro is being invoked ! in other than KERNEL mode. Note that not all macros support being ! used in an outer mode. All macros will report an error if they are ! invoked with a currentMode they don't support. ! ! The account argument is the address of the buffer into which the ! account string should be fetched. ! ! The size argument is the size of the account buffer. ! ! U S A G E ! ========= ! $PSB$GET_ACCOUNT Fetch account string ! ! account address of buffer to receive copy of account string ! size size of buffer for account string ! psb optional PSB (default is current persona) ! ktb optional KTB (default is current kernel thread) ! pcb optional PCB (default is current process PCB) ! acmode optional access mode for lazy assume (default is PREVIOUS) ! currentMode optional current mode (default is KERNEL) !-- keywordmacro $psb$get_account (account, size, psb, ktb, pcb, acmode, currentMode = KERNEL) = %if %identical (currentMode, kernel) or %identical (currentMode, exec) %then $$$internal$$$action_psb (fetch_account, account, size, 0, 0, psb, ktb, pcb, acmode, currentMode) %else %error ('Invalid currentMode argument in $psb$get_account macro invocation') %fi %; !++ ! Account access macros. This macro provides the ability to write ! the account field of the persona block while hiding the overall ! structure of the implementation. ! ! The following is the intended usage style for this macro: ! ! if (status = $psb$set_account (...)) ! then ! ... ! else ! persona assume error; ! ! N O T E S ! ========= ! This macro operates on the current persona. Failure to take ! appropriate steps to localize this operation (such as first creating ! a cloned persona) will result in leakage of the actions of this macro ! to all other execution threads sharing this persona. ! ! Since this macro operates on the current persona, the most efficient ! argument that can be supplied by a caller is the psb argument. ! If the psb argument is omitted, then the next most efficient ! arguments (in order of preference) are the ktb and pcb arguments. ! ! The acmode argument should be supplied if any lazy assume performed ! by get_curpsb (used if psb is omitted) needs to be performed in the ! context of a different mode other than the previous execution mode. ! ! The currentMode argument should be supplied if a macro is being invoked ! in other than KERNEL mode. Note that not all macros support being ! used in an outer mode. All macros will report an error if they are ! invoked with a currentMode they don't support. ! ! The account argument is the address of the buffer into which the ! account string should be fetched. ! ! The size argument is the size of the account buffer. ! ! The context argument is an indication as to which fields should be ! updated with the account string (default is PERSONA). If this argument ! is specified as PERSONA then only the persona block is updated; if ! specified as PROCESS then the JIB and CTL cells are updated in addition ! to the persona block. ! ! U S A G E ! ========= ! $PSB$SET_ACCOUNT Set account string ! ! account address of buffer containing account string ! size size of account string within the buffer ! context context of operation (default is PERSONA) ! psb optional PSB (default is current persona) ! ktb optional KTB (default is current kernel thread) ! pcb optional PCB (default is current process PCB) ! acmode optional access mode for lazy assume (default is PREVIOUS) ! currentMode optional current mode (default is KERNEL) !-- keywordmacro $psb$set_account (account, size, context, psb, ktb, pcb, acmode, currentMode = KERNEL) = %if %identical (currentMode, kernel) %then $$$internal$$$action_psb (store_account, account, size, context, 0, psb, ktb, pcb, acmode, currentMode) %else %error ('Invalid currentMode argument in $psb$set_account macro invocation') %fi %; !++ ! Username access macros. This macro provides the ability to read ! the username field of the persona block while hiding the overall ! structure of the implementation. ! ! The following is the intended usage style for this macro: ! ! if (status = $psb$get_username (...)) ! then ! ... ! else ! persona assume error; ! ! N O T E S ! ========= ! This macro operates on the current persona. ! ! Since this macro operates on the current persona, the most efficient ! argument that can be supplied by a caller is the psb argument. ! If the psb argument is omitted, then the next most efficient ! arguments (in order of preference) are the ktb and pcb arguments. ! ! The acmode argument should be supplied if any lazy assume performed ! by get_curpsb (used if psb is omitted) needs to be performed in the ! context of a different mode other than the previous execution mode. ! ! The currentMode argument should be supplied if a macro is being invoked ! in other than KERNEL mode. Note that not all macros support being ! used in an outer mode. All macros will report an error if they are ! invoked with a currentMode they don't support. ! ! The username argument is the address of the buffer into which the ! username string should be fetched. ! ! The size argument is the size of the username buffer. ! ! U S A G E ! ========= ! $PSB$GET_USERNAME Fetch username string ! ! username address of buffer to receive copy of username string ! size size of buffer for username string ! psb optional PSB (default is current persona) ! ktb optional KTB (default is current kernel thread) ! pcb optional PCB (default is current process PCB) ! acmode optional access mode for lazy assume (default is PREVIOUS) ! currentMode optional current mode (default is KERNEL) !-- keywordmacro $psb$get_username (username, size, psb, ktb, pcb, acmode, currentMode = KERNEL) = %if %identical (currentMode, kernel) or %identical (currentMode, exec) %then $$$internal$$$action_psb (fetch_username, username, size, 0, 0, psb, ktb, pcb, acmode, currentMode) %else %error ('Invalid currentMode argument in $psb$get_username macro invocation') %fi %; !++ ! Username access macros. This macro provides the ability to write ! the username field of the persona block while hiding the overall ! structure of the implementation. ! ! The following is the intended usage style for this macro: ! ! if (status = $psb$set_username (...)) ! then ! ... ! else ! persona assume error; ! ! N O T E S ! ========= ! This macro operates on the current persona. Failure to take ! appropriate steps to localize this operation (such as first creating ! a cloned persona) will result in leakage of the actions of this macro ! to all other execution threads sharing this persona. ! ! Since this macro operates on the current persona, the most efficient ! argument that can be supplied by a caller is the psb argument. ! If the psb argument is omitted, then the next most efficient ! arguments (in order of preference) are the ktb and pcb arguments. ! ! The acmode argument should be supplied if any lazy assume performed ! by get_curpsb (used if psb is omitted) needs to be performed in the ! context of a different mode other than the previous execution mode. ! ! The currentMode argument should be supplied if a macro is being invoked ! in other than KERNEL mode. Note that not all macros support being ! used in an outer mode. All macros will report an error if they are ! invoked with a currentMode they don't support. ! ! The username argument is the address of the buffer into which the ! username string should be fetched. ! ! The size argument is the size of the username buffer. ! ! The context argument is an indication as to which fields should be ! updated with the username string (default is PERSONA). If this argument ! is specified as PERSONA then only the persona block is updated; if ! specified as PROCESS then the JIB and CTL cells are updated in addition ! to the persona block. ! ! U S A G E ! ========= ! $PSB$SET_USERNAME Set username string ! ! username address of buffer containing username string ! size size of username string within the buffer ! context context of operation (default is PERSONA) ! psb optional PSB (default is current persona) ! ktb optional KTB (default is current kernel thread) ! pcb optional PCB (default is current process PCB) ! acmode optional access mode for lazy assume (default is PREVIOUS) ! currentMode optional current mode (default is KERNEL) !-- keywordmacro $psb$set_username (username, size, context, psb, ktb, pcb, acmode, currentMode = KERNEL) = %if %identical (currentMode, kernel) %then $$$internal$$$action_psb (store_username, username, size, context, 0, psb, ktb, pcb, acmode, currentMode) %else %error ('Invalid currentMode argument in $psb$set_username macro invocation') %fi %; !++ ! Privs access macros. This macro provides the ability to read ! the current privs of the persona block while hiding the overall ! structure of the implementation. ! ! The following is the intended usage style for this macro: ! ! if (status = $psb$get_privs (...)) ! then ! ... ! else ! persona assume error; ! ! N O T E S ! ========= ! This macro operates on the current persona. ! ! Since this macro operates on the current persona, the most efficient ! argument that can be supplied by a caller is the psb argument. ! If the psb argument is omitted, then the next most efficient ! arguments (in order of preference) are the ktb and pcb arguments. ! ! The acmode argument should be supplied if any lazy assume performed ! by get_curpsb (used if psb is omitted) needs to be performed in the ! context of a different mode other than the previous execution mode. ! ! The currentMode argument should be supplied if a macro is being invoked ! in other than KERNEL mode. Note that not all macros support being ! used in an outer mode. All macros will report an error if they are ! invoked with a currentMode they don't support. ! ! The privMask argument is the address of a quadword into which the ! privileges mask should be fetched. ! ! U S A G E ! ========= ! $PSB$GET_PRIVS Fetch privileges ! ! privMask address of quadword to receive privileges mask ! psb optional PSB (default is current persona) ! ktb optional KTB (default is current kernel thread) ! pcb optional PCB (default is current process PCB) ! acmode optional access mode for lazy assume (default is PREVIOUS) ! currentMode optional current mode (default is KERNEL) !-- keywordmacro $psb$get_privs (privMask, psb, ktb, pcb, acmode, currentMode = KERNEL) = %if %identical (currentMode, kernel) or %identical (currentMode, exec) %then $$$internal$$$action_psb (fetch_privs, privMask, 0, 0, 0, psb, ktb, pcb, acmode, currentMode) %else %error ('Invalid currentMode argument in $psb$get_privs macro invocation') %fi %; !++ ! UIC access macros. This macro provides the ability to read ! the UIC field of the persona block while hiding the overall ! structure of the implementation. ! ! The following is the intended usage style for this macro: ! ! if (status = $psb$get_uic (...)) ! then ! ... ! else ! persona assume error; ! ! N O T E S ! ========= ! This macro operates on the current persona. ! ! Since this macro operates on the current persona, the most efficient ! argument that can be supplied by a caller is the psb argument. ! If the psb argument is omitted, then the next most efficient ! arguments (in order of preference) are the ktb and pcb arguments. ! ! The acmode argument should be supplied if any lazy assume performed ! by get_curpsb (used if psb is omitted) needs to be performed in the ! context of a different mode other than the previous execution mode. ! ! The currentMode argument should be supplied if a macro is being invoked ! in other than KERNEL mode. Note that not all macros support being ! used in an outer mode. All macros will report an error if they are ! invoked with a currentMode they don't support. ! ! The uic argument is the address of a longword into which the uic ! is stored. ! ! U S A G E ! ========= ! $PSB$GET_UIC Fetch uic ! ! uic address of longword to receive the uic ! psb optional PSB (default is current persona) ! ktb optional KTB (default is current kernel thread) ! pcb optional PCB (default is current process PCB) ! acmode optional access mode for lazy assume (default is PREVIOUS) ! currentMode optional current mode (default is KERNEL) !-- keywordmacro $psb$get_uic (uic, psb, ktb, pcb, acmode, currentMode = KERNEL) = %if %identical (currentMode, kernel) or %identical (currentMode, exec) %then $$$internal$$$action_psb (fetch_uic, uic, 0, 0, 0, psb, ktb, pcb, acmode, currentMode) %else %error ('Invalid currentMode argument in $psb$get_uic macro invocation') %fi %; !++ ! UIC access macros. This macro provides the ability to write ! the UIC field of the persona block while hiding the overall ! structure of the implementation. ! ! The following is the intended usage style for this macro: ! ! if (status = $psb$set_uic (...)) ! then ! ... ! else ! persona assume error; ! ! N O T E S ! ========= ! This macro operates on the current persona. Failure to take ! appropriate steps to localize this operation (such as first creating ! a cloned persona) will result in leakage of the actions of this macro ! to all other execution threads sharing this persona. ! ! Since this macro operates on the current persona, the most efficient ! argument that can be supplied by a caller is the psb argument. ! If the psb argument is omitted, then the next most efficient ! arguments (in order of preference) are the ktb and pcb arguments. ! ! The acmode argument should be supplied if any lazy assume performed ! by get_curpsb (used if psb is omitted) needs to be performed in the ! context of a different mode other than the previous execution mode. ! ! The currentMode argument should be supplied if a macro is being invoked ! in other than KERNEL mode. Note that not all macros support being ! used in an outer mode. All macros will report an error if they are ! invoked with a currentMode they don't support. ! ! The uic argument is the address of a longword which contains the uic ! to be set. ! ! U S A G E ! ========= ! $PSB$SET_UIC Set uic ! ! uic address of longword containing the uic ! psb optional PSB (default is current persona) ! ktb optional KTB (default is current kernel thread) ! pcb optional PCB (default is current process PCB) ! acmode optional access mode for lazy assume (default is PREVIOUS) ! currentMode optional current mode (default is KERNEL) !-- keywordmacro $psb$set_uic (uic, psb, ktb, pcb, acmode, currentMode = KERNEL) = %if %identical (currentMode, kernel) %then $$$internal$$$action_psb (store_uic, uic, 0, 0, 0, psb, ktb, pcb, acmode, currentMode) %else %error ('Invalid currentMode argument in $psb$set_uic macro invocation') %fi %; !+ ! Helper macro for $psb$get_account and $$$internal$$$action_psb macros !- macro $$$internal$$$fetch_account (ktb, psb, currentMode, account, accountSize, dummy3, dummy4) = %if %identical (currentMode, kernel) %then ch$copy (minu (accountSize, PSB$S_ACCOUNT), psb[PSB$T_ACCOUNT], ' ', accountSize, account); %else %error ('Macro not support for other than kernel mode'); %fi %; !+ ! Helper macro for $psb$set_account and $$$internal$$$action_psb macros !- macro $$$internal$$$store_account (ktb, psb, currentMode, account, accountSize, context, dummy4) = %if %identical (currentMode, kernel) %then ch$copy (minu (accountSize, PSB$S_ACCOUNT), account, ' ', PSB$S_ACCOUNT, psb[PSB$T_ACCOUNT]); %if %identical (context, process) %then begin local $$$jib$$$ : ref block[,byte]; external CTL$T_ACCOUNT : ref vector[,byte]; ! Pick up address of JIB $$$jib$$$ = .ktb[KTB$L_JIB]; ! Write data into JIB ch$copy (minu (PSB$S_ACCOUNT, JIB$S_ACCOUNT), psb[PSB$T_ACCOUNT], ' ', JIB$S_ACCOUNT, $$$jib$$$[JIB$T_ACCOUNT]); ! Write data into P1 control region ch$copy (minu (PSB$S_ACCOUNT, JIB$S_ACCOUNT), psb[PSB$T_ACCOUNT], ' ', JIB$S_ACCOUNT, CTL$T_ACCOUNT); end; %else %if not %null (context) %then %error ('Invalid context argument to macro') %fi %fi %else %error ('Macro not support for other than kernel mode'); %fi %; !+ ! Helper macro for $psb$get_username and $$$internal$$$action_psb macros !- macro $$$internal$$$fetch_username (ktb, psb, currentMode, username, usernameSize, dummy3, dummy4) = %if %identical (currentMode, kernel) %then ch$copy (minu (usernameSize, PSB$S_USERNAME), psb[PSB$T_USERNAME], ' ', usernameSize, username); %else %error ('Macro not support for other than kernel mode'); %fi %; !+ ! Helper macro for $psb$set_username and $$$internal$$$action_psb macros !- macro $$$internal$$$store_username (ktb, psb, currentMode, username, usernameSize, context, dummy4) = %if %identical (currentMode, kernel) %then ch$copy (minu (usernameSize, PSB$S_USERNAME), username, ' ', PSB$S_USERNAME, psb[PSB$T_USERNAME]); %if %identical (context, process) %then begin local $$$jib$$$ : ref block[,byte]; external CTL$T_USERNAME : ref vector[,byte]; ! Pick up address of JIB $$$jib$$$ = .ktb[KTB$L_JIB]; ! Write data into JIB ch$copy (minu (PSB$S_USERNAME, JIB$S_USERNAME), psb[PSB$T_USERNAME], ' ', JIB$S_USERNAME, $$$jib$$$[JIB$T_USERNAME]); ! Write data into P1 control region ch$copy (minu (PSB$S_USERNAME, JIB$S_USERNAME), psb[PSB$T_USERNAME], ' ', JIB$S_USERNAME, CTL$T_USERNAME); end; %else %if not %null (context) %then %error ('Invalid context argument to macro') %fi %fi %else %error ('Macro not support for other than kernel mode') %fi %; !+ ! Helper macro for $psb$get_privs and $$$internal$$$action_psb macros !- macro $$$internal$$$fetch_privs (ktb, psb, currentMode, privmask, dummy2, dummy3, dummy4) = %if %identical (currentMode, kernel) %then vector[privMask, 0; ,long] = .vector[psb[PSB$Q_WORKPRIV], 0; ,LONG] or .vector[psb[PSB$Q_IMAGE_WORKPRIV], 0; ,LONG]; vector[privMask, 1; ,long] = .vector[psb[PSB$Q_WORKPRIV], 1; ,LONG] or .vector[psb[PSB$Q_IMAGE_WORKPRIV], 1; ,LONG]; %else %error ('Macro not support for other than kernel mode'); %fi %; !+ ! Helper macro for $psb$get_uic and $$$internal$$$action_psb macros !- macro $$$internal$$$fetch_uic (ktb, psb, currentMode, uic, dummy2, dummy3, dummy4) = %if %identical (currentMode, kernel) %then vector[uic, 0; ,long] = .psb[PSB$L_UIC]; %else %error ('Macro not support for other than kernel mode'); %fi %; !+ ! Helper macro for $psb$set_uic and $$$internal$$$action_psb macros !- macro $$$internal$$$store_uic (ktb, psb, currentMode, uic, dummy2, dummy3, dummy4) = %if %identical (currentMode, kernel) %then begin external routine EXE$PERSONA_EXPORT_ARB : addressing_mode (general); psb[PSB$L_UIC] = uic; ! Export ARB if the current PSB is the only one in ! user node EXE$PERSONA_EXPORT_ARB (ISS$C_ARB_UNSPECIFIED); end %else %error ('Macro not support for other than kernel mode'); %fi %; !+ ! Internal helper macro to perform an action in the context of a ! persona block. The action macro is passed as an argument to this ! helper macro along with up to four data arguments to be supplied ! in the call to the action macro. !- macro $$$internal$$$action_psb (action, datum1, datum2, datum3, datum4, psb, ktb, pcb, acmode, currentMode) = begin local $$$psb$$$ : ref block[,byte], $$$status$$$ : long; %if %null (psb) %then local $$$ktb$$$ : ref block[,byte]; ! Pick up pointer to current kernel thread block %if %null (ktb) %then $$$ktb$$$ = get_curktb; %else $$$ktb$$$ = ktb; %fi ! Pick up pointer to current persona block if ($$$status$$$ = get_curpsb (%quote psb = $$$psb$$$, %quote ktb = .$$$ktb$$$, %quote acmode = acmode, %quote currentMode = currentMode)) then begin ! Perform action %name('$$$internal$$$',action) ($$$ktb$$$, $$$psb$$$, currentMode, datum1, datum2, datum3, datum4); end; %else local $$$ktb$$$ : ref block[,byte]; ! Pick up pointer to current kernel thread block %if %null (ktb) %then $$$ktb$$$ = get_curktb; %else $$$ktb$$$ = ktb; %fi ! Pick up pointer to current persona block $$$psb$$$ = psb; ! Perform action %name('$$$internal$$$',action) ($$$ktb$$$, $$$psb$$$, currentMode, datum1, datum2, datum3, datum4); ! Set status $$$status$$$ = 1; %fi ! Return status of action .$$$status$$$ end %; !++ ! Macro to get address of current persona block. This macro handles ! the need to perform a lazy persona assume if the persona id in the ! per-thread kernel area indicates an implicit persona context switch. ! The value returned by the macro is an indication of a successful or ! failed attempt to assume a persona. The invoker of this macro must ! be in kernel mode. ! ! The following is the intended usage style for this macro: ! ! if (status = get_curpsb (...)) ! then ! ...; ! ! N O T E S ! ========= ! The psb argument is the address of a location into which the current ! persona's persona block address will be written. ! ! The most efficient argument for this macro is the ktb argument, ! with pcb being only slightly usefull. ! ! The acmode argument should be supplied if any lazy assume performed ! by get_curpsb (used if psb is omitted) needs to be performed in the ! context of a different mode other than the previous execution mode. ! ! The currentMode argument should be supplied if a macro is being invoked ! in other than KERNEL mode. Note that not all macros support being ! used in an outer mode. All macros will report an error if they are ! invoked with a currentMode they don't support. ! ! U S A G E ! ========= ! GET_CURPSB Get current psb ! ! psb address of longword to receive persona block address ! ktb optional KTB (default is current kernel thread) ! pcb optional PCB (default is current process PCB) ! acmode optional access mode for lazy assume (default is PREVIOUS) ! currentMode optional current mode (default is KERNEL) !-- keywordmacro get_curpsb (psb, ktb, pcb, acmode, currentMode = KERNEL) = begin %if %null (psb) %then %error ('Missing argument in call to get_curpsb') %fi external routine NSA$GET_CURRENT_PSB : NSA$GET_CURRENT_PSB_LINKAGE; ! Pick up pointer to current kernel thread block %if %null (ktb) %then NSA$GET_CURRENT_PSB (0; psb) %else NSA$GET_CURRENT_PSB (ktb; psb) %fi end %; ! Macros for interlocking access to persona data structures ! ! DebugDBLock Used to interlock system-wide debug chain ! DebugDBUnlock ! ! PersonaArrayLock Used to interlock access to persona array ! PersonaArrayUnlock macro DebugDBLock(x) = %, DebugDBUnlock(x) = %, PersonaArrayLock(x) = %, PersonaArrayUnlock(x) = %; ! ! ---- < End of module SECURITY-MACROS.REQ - 30-MAR-2010 16:39:00.54 > - ! ! ! Macros to lock/unlock SMP SPINLOCKS ! ! Version: 'X-10' ! !**************************************************************************** !* * !* COPYRIGHT (c) 1986, 1987, 1988, 1990, 1992 BY * !* DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS. * !* ALL RIGHTS RESERVED. * !* * !* THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED * !* ONLY IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE AND WITH THE * !* INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR ANY OTHER * !* COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY * !* OTHER PERSON. NO TITLE TO AND OWNERSHIP OF THE SOFTWARE IS HEREBY * !* TRANSFERRED. * !* * !* THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE * !* AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT * !* CORPORATION. * !* * !* DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS * !* SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL. * !* * !* * !**************************************************************************** !++ ! ! FACILITY: System Library ! ! ABSTRACT: ! ! These macros are used to generate SMP locking code. ! ! ENVIRONMENT: ! ! Native mode VAX processor; no operating system facilities are used. ! !-- ! ! ! AUTHOR: Rod Gamache, CREATION DATE: 13-Jan-1986 ! ! MODIFIED BY: ! ! X-10 Clair Grant 12-May-2002 ! Remove extraneous BUILTIN CALL_PAL from $SYS_UNLOCK. ! ! X-9 Clair Grant 10-May-2002 ! Add some %QUOTEs to DEFINE_BUILTIN uses. ! ! X-8 Clair Grant HP merger day ! Use DEFINE_BUILTIN for PAL_xxx ! ! X-7 RAB Richard A. Bishop 1-Feb-1995 ! Fix references to SMP$AR_SPNLKVEC in $SYS_LOCK so it ! can be used from Bliss-64. ! ! Old audit trail follows.... ! ! X-9 JRK361 Jim Kauffman 25-Aug-1992 ! Modify $READ_SYSTIME to eliminate HWCLK spinlock acquisition ! and to call the SYSTEM_PRIMITIVES routine ! ! X-8 KLN1150 Karen L. Noel 17-Jan-1992 ! Remove mutex part of $sys_lock and $sys_unlock macros. ! ! X-7 JRK361 Jim Kauffman 13-Jan-1992 ! Restore LOCKIPL qualifier to DEVICELOCK macro ! ! X-6 JRK361 Jim Kauffman 15-Nov-1991 ! Promote spinlock structure offsets ! ! X-5 JRK361 Jim Kauffman 1-Jul-1991 ! Restore inline checks for SMP support for performance ! Correct DEVICELOCK location for IPL ! ! X-4 ROW0760 Ralph O. Weber 21-MAY-1991 12:02 ! Add END statements to $FORKLOCK, $FORKUNLOCK, and ! $DEVICEUNLOCK that were incorrectly removed in ROW0753. ! Change MTX$W_WRT to MTX$W_OWNCNT. There is no MTX$W_WRT. ! Change comparisons of MXT$W_WRT with -1 to comparisons of ! MXT$W_OWNCNT. MXT$W_OWNCNT is not a sign extended field. ! ! X-3 ROW0757 Ralph O. Weber 16-MAY-1991 16:58 ! MUTEX is not spelled MUXTEX. ! ! X-2 ROW0753 Ralph O. Weber 14-MAY-1991 13:34 ! Update TIMEDWAIT usage to the Alpha/VMS forms. ! Make all macros suitable for usage from Bliss-64, so that ! this file can be included in LIB.L64. Delete $GET_CURPCB. ! It does not apply on Alpha. Eliminage in-line testing of ! SMP$V_ENABLED. Remove FIPL testing in the fork locking ! macros. ! ! ---------- Ident numbering change due to master pack reorg --------- ! ! X-17K7 MAS Mary A. Sullivan 7-Feb-1991 ! Add "PAL_" to PALcode builtins. ! ! X-17K6 RS00071 Richard Sayde 31-Jan-1991 ! MTPR_IPL builtin takes IPL value, not address. Update all ! calls to the builtin. ! ! X-17K5 RWC020 Richard W. Critz, Jr. 19-Dec-1990 ! Fix $DSBINT and $ENBINT to pass new IPL by value rather ! than by reference. ! ! x-17K4 DB0011 Dave Burkey 13-Sept-1990 ! Conditionalize MTPR_IPL use for EVAX to make compatible with ! MTPR_IPL macro which disallows use of %REF. ! ! X-16K4 RS00022 Richard Sayde 2-Aug-1990 ! Add a dummy format to the $FIND_CPU_MACRO so that the ()'s ! in the macro calls are not interpreted as a procedure call. ! ! X-16K3 RS00020 Richard Sayde 1-Aug-1990 ! $FIND_CPU_DATA macro was not returning a value because of a ! semicolon at the end of the PAL call. Also, changed the ! macro to use the BUILTIN MFPR_PRBR instead of he generic ! PAL call. ! ! X-16K2 KLN1013 Karen L. Noel 21-May-1990 ! Partially port to Alpha. I make no promises. ! ! X-15,16 EMB Ellen M. Batbouta 19-Jul-1989 ! Try again to fix $SYS_LOCK. ! ! X-14 EMB0419 Ellen M. Batbouta 17-Jul-1989 ! Fix several of the SMP macros. In the $FORKUNLOCK and ! $FORKLOCK macros, FKB$B_FLCK was misspelled. In the ! $SYS_UNLOCK macro, the mutex count in the per-CPU database ! was being incremented instead of decremented when releasing ! the mutex with read access. In the $SYS_LOCK macro, an extra ! SETIPL is being done on the SMP enabled path. ! ! ! X-13 EMB0381 Ellen M. Batbouta 09-Jan-1989 ! Remove extra SETIPL from KEYWORDMACRO $SYS_LOCK. ! ! X-12 JDC0408 Jon Callas 13-SEP-1988 ! Change references to BUG_CHECK. Not only is there no BUG_CHECK, ! but it really should be $BUG_CHECK. A $BUG_CHECK has been ! added to LIB via VMS-MACROS.REQ with this. ! ! X-11 RNG5011 Rod N. Gamache 21-Dec-1987 ! Fix BLISS macros to use $FIND_CPU_DATA call. ! Fix $FORKUNLOCK to check if FIPL or FLCK. ! ! X-10 RNG5010 Rod N. Gamache 11-Sep-1987 ! Add separate non-keyword macros for SYS_LOCK, SYS_UNLOCK, ! FORKLOCK and FORKUNLOCK. ! ! X-9 BAS5009 Barry A Scott 4-Sep-1987 ! Completely re-write most of the BLISS macros. ! ! X-8 RNG5008 Rod N. Gamache 12-Aug-1987 ! Change refs from SMP$C_xxx to SPL$C_xxx. ! ! X-7 WCT0047 Ward C. Travis 19-Mar-1987 ! Create macros for Bliss system page lockdown ! requests. ! ! X-6 WCT0023 Ward C. Travis 27-Jan-1987 ! Merge in changes by RNG to activate SAVIPL ! parameter in SYS_LOCK macros. ! ! X-5 WCT0021 Ward C. Travis 21-Jan-1987 ! Changes made in WCT0015 updated. LOCK and UNLOCK ! now have the names SYS_LOCK and SYS_UNLOCK. ! ! X-4 WCT0015 Ward C. Travis 14-Jan-1987 ! Bugfix to X-3; renaming SMPLOCK to LOCK caused a ! name conflict with the first parameter to FORKLOCK. ! ! X-3 WCT0015 Ward C. Travis 7-Jan-1987 ! Update outdated SMPLOCK, SMPUNLOCK definitions to ! LOCK, UNLOCK for SMP. ! !** ! ! The KEYWORD SMP MACROS: ! KEYWORDMACRO $DSBINT( NEWIPL, DST, ENVIRON=MULTIPROCESSOR ) = BEGIN DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MFPR_IPL); DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MTPR_IPL); LOCAL $$IPL_VAL; %IF NOT %NULL( DST ) %THEN DST = PAL_MFPR_IPL(); %ELSE %ERROR('DST parameter is mandatory') %FI %IF NOT %NULL( NEWIPL ) %THEN $$IPL_VAL = NEWIPL; PAL_MTPR_IPL( .$$IPL_VAL ); %IF NOT %IDENTICAL( %STRING( ENVIRON ), %STRING( UNIPROCESSOR ) ) %THEN %IF NOT %CTCE( NEWIPL ) OR (%CTCE( NEWIPL ) AND NEWIPL GTR IPL$_ASTDEL) %THEN %WARN('Raising IPL to ',NEWIPL,' provides no multiprocessing synchronization') %FI %FI %ELSE $$IPL_VAL = IPL$_POWER; PAL_MTPR_IPL( .$$IPL_VAL ); %IF NOT %IDENTICAL( %STRING( ENVIRON ), %STRING( UNIPROCESSOR ) ) %THEN %WARN('Raising IPL to 31 provides no multiprocessing synchronization') %FI %FI END %; KEYWORDMACRO $ENBINT( SRC ) = BEGIN DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MTPR_IPL); LOCAL $$IPL_VAL; %IF %NULL( SRC ) %THEN %ERROR('SRC parameter is mandatory') %ELSE $$IPL_VAL = SRC; PAL_MTPR_IPL( .$$IPL_VAL ); %FI END %; KEYWORDMACRO $SYS_LOCK( LOCKNAME, LOCKIPL, SAVIPL, CONDITION ) = BEGIN DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MTPR_IPL); DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MFPR_IPL); EXTERNAL SMP$GL_FLAGS : BLOCK[4,BYTE] ADDRESSING_MODE( GENERAL ), SMP$AR_SPNLKVEC : SIGNED LONG ADDRESSING_MODE( GENERAL ); MAP SMP$AR_SPNLKVEC : REF VECTOR[ , LONG, SIGNED]; LINKAGE SMP_ROUTINE = JSB ( REGISTER = 0 ) : NOTUSED (1,2,3,4,5,6,7,8,9,10,11); EXTERNAL ROUTINE SMP$ACQUIRE : SMP_ROUTINE ADDRESSING_MODE( GENERAL ), SMP$ACQNOIPL : SMP_ROUTINE ADDRESSING_MODE( GENERAL ); LOCAL $$SAVED_IPL; %IF NOT %NULL( LOCKNAME ) %THEN %IF NOT %NULL( SAVIPL ) %THEN SAVIPL = PAL_MFPR_IPL(); %FI %IF %IDENTICAL( %STRING( CONDITION ), %STRING( NOSETIPL ) ) %THEN IF .SMP$GL_FLAGS[ SMP$V_ENABLED ] THEN SMP$ACQNOIPL( .SMP$AR_SPNLKVEC[ %NAME( SPL$C_, LOCKNAME ) ] ); %ELSE IF .SMP$GL_FLAGS[ SMP$V_ENABLED ] THEN SMP$ACQUIRE( %NAME( SPL$C_, LOCKNAME ) ) ELSE $SETIPL( NEWIPL = %NAME( IPL$_, LOCKNAME ), ENVIRON=UNIPROCESSOR ); %FI %FI END %; KEYWORDMACRO $SYS_UNLOCK( LOCKNAME, NEWIPL, CONDITION ) = BEGIN LITERAL MTPR_TBIA = 27; DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MTPR_IPL); EXTERNAL SMP$GL_FLAGS : ADDRESSING_MODE( GENERAL ) BLOCK [ 4, BYTE ]; LINKAGE SMP_ROUTINE = JSB ( REGISTER = 0 ) : NOTUSED (1,2,3,4,5,6,7,8,9,10,11); EXTERNAL ROUTINE SMP$RELEASE : SMP_ROUTINE ADDRESSING_MODE( GENERAL ), SMP$RESTORE : SMP_ROUTINE ADDRESSING_MODE( GENERAL ); LOCAL $$SAVED_IPL, $$IPL_VAL; %IF NOT %NULL( LOCKNAME ) %THEN IF .SMP$GL_FLAGS[ SMP$V_ENABLED ] THEN BEGIN %IF NOT %NULL( CONDITION ) %THEN %IF %IDENTICAL( %STRING( CONDITION ), %STRING( RESTORE ) ) %THEN SMP$RESTORE( %NAME( SPL$C_, LOCKNAME ) ); %ELSE %ERROR( 'Bad argument value - condition' ) %FI %ELSE SMP$RELEASE( %NAME( SPL$C_, LOCKNAME ) ); %FI END; %IF NOT %NULL( NEWIPL ) %THEN $$IPL_VAL = NEWIPL; PAL_MTPR_IPL( .$$IPL_VAL ); %FI %FI END %; KEYWORDMACRO $FIND_CPU_DATA (DUMMY) = BEGIN DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MFPR_PRBR); PAL_MFPR_PRBR () END %; KEYWORDMACRO ! ! LOCK FORK SPINLOCK ! $FORKLOCK ( LOCK = .UCB[ FKB$B_FLCK], LOCKIPL, SAVIPL, PRESERVE = YES, FIPL = NO ) = BEGIN ! ! LINKAGES: ! LINKAGE SMP_ROUTINE = JSB ( REGISTER = 0 ) : NOTUSED (1,2,3,4,5,6,7,8,9,10,11); EXTERNAL ROUTINE SMP$ACQUIRE : SMP_ROUTINE NOVALUE ADDRESSING_MODE (GENERAL); EXTERNAL SMP$GL_FLAGS : ADDRESSING_MODE( GENERAL ) BLOCK [ 4, BYTE ], SMP$AL_IPLVEC : ADDRESSING_MODE( GENERAL ) VECTOR [ , LONG ]; DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MFPR_IPL); %IF NOT %NULL( SAVIPL ) %THEN SAVIPL = PAL_MFPR_IPL(); %FI IF .SMP$GL_FLAGS[ SMP$V_ENABLED ] THEN SMP$ACQUIRE( LOCK ) ELSE $SETIPL ( NEWIPL = .SMP$AL_IPLVEC[ LOCK ], ENVIRON = UNIPROCESSOR ); END % ; ! ! UNLOCK FORK SPINLOCK ! KEYWORDMACRO $FORKUNLOCK ( LOCK = .UCB[ FKB$B_FLCK], NEWIPL, CONDITION, PRESERVE = YES ) = BEGIN ! ! LINKAGES: ! LINKAGE SMP_ROUTINE = JSB ( REGISTER = 0 ) : NOTUSED (1,2,3,4,5,6,7,8,9,10,11); EXTERNAL ROUTINE SMP$RESTORE : SMP_ROUTINE NOVALUE ADDRESSING_MODE (GENERAL), SMP$RELEASE : SMP_ROUTINE NOVALUE ADDRESSING_MODE (GENERAL); EXTERNAL SMP$GL_FLAGS : BLOCK [ 4, BYTE ] ADDRESSING_MODE( GENERAL ); DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MTPR_IPL); LOCAL $$IPL_VAL; IF .SMP$GL_FLAGS[ SMP$V_ENABLED ] THEN %IF %IDENTICAL ( %STRING( CONDITION ), %STRING( RESTORE ) ) %THEN SMP$RESTORE ( LOCK ); %ELSE SMP$RELEASE ( LOCK ); %FI %IF NOT %NULL( NEWIPL ) %THEN $$IPL_VAL = NEWIPL; PAL_MTPR_IPL( .$$IPL_VAL ); %FI END % ; KEYWORDMACRO $DEVICELOCK ( LOCKADDR = .UCB[ UCB$L_DLCK ], LOCKIPL, SAVIPL, CONDITION, PRESERVE = YES ) = BEGIN ! ! LINKAGES: ! LINKAGE SMP_ROUTINE = JSB ( REGISTER = 0 ) : NOTUSED (1,2,3,4,5,6,7,8,9,10,11); EXTERNAL ROUTINE SMP$ACQUIREL : SMP_ROUTINE NOVALUE ADDRESSING_MODE (GENERAL), SMP$ACQNOIPL : SMP_ROUTINE NOVALUE ADDRESSING_MODE (GENERAL); EXTERNAL SMP$GL_FLAGS : ADDRESSING_MODE( GENERAL ) BLOCK [ 4, BYTE ]; LOCAL $$$SPINLOCK : REF BLOCK [, BYTE ]; DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MFPR_IPL); $$$SPINLOCK = LOCKADDR; %IF NOT %NULL( SAVIPL ) %THEN SAVIPL = PAL_MFPR_IPL(); %FI IF .SMP$GL_FLAGS[ SMP$V_ENABLED ] THEN %IF %IDENTICAL (%STRING( CONDITION ), %STRING( NOSETIPL )) %THEN SMP$ACQNOIPL( .$$$SPINLOCK ); %ELSE SMP$ACQUIREL( .$$$SPINLOCK ); %FI %IF NOT %IDENTICAL( %STRING( CONDITION ), %STRING( NOSETIPL ) ) %THEN IF NOT .SMP$GL_FLAGS[ SMP$V_ENABLED ] THEN %IF NOT %NULL( LOCKIPL ) %THEN $SETIPL( NEWIPL = LOCKIPL, ENVIRON = UNIPROCESSOR ); %ELSE $SETIPL( NEWIPL = .$$$SPINLOCK[ SPL$L_IPL ], ENVIRON = UNIPROCESSOR ); %FI %FI END %; ! ! UNLOCK DEVICE SPINLOCK ! KEYWORDMACRO $DEVICEUNLOCK ( LOCKADDR = .UCB[ UCB$L_DLCK ], NEWIPL, CONDITION, PRESERVE = YES ) = BEGIN ! ! LINKAGES: ! LINKAGE SMP_ROUTINE = JSB( REGISTER = 0 ) : NOTUSED( 1,2,3,4,5,6,7,8,9,10,11); EXTERNAL ROUTINE SMP$RESTOREL : SMP_ROUTINE NOVALUE ADDRESSING_MODE( GENERAL), SMP$RELEASEL : SMP_ROUTINE NOVALUE ADDRESSING_MODE( GENERAL); EXTERNAL SMP$GL_FLAGS : BLOCK[ 4, BYTE ] ADDRESSING_MODE( GENERAL ); DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MTPR_IPL); LOCAL $$IPL_VAL; IF .SMP$GL_FLAGS[ SMP$V_ENABLED ] THEN %IF %IDENTICAL( %STRING( CONDITION ), %STRING( RESTORE ) ) %THEN SMP$RESTOREL( LOCKADDR ); %ELSE SMP$RELEASEL( LOCKADDR ); %FI %IF NOT %NULL( NEWIPL ) %THEN $$IPL_VAL = NEWIPL; PAL_MTPR_IPL( .$$IPL_VAL ); %FI END %; KEYWORDMACRO $READ_SYSTIME( DST ) = BEGIN EXTERNAL ROUTINE EXE$GET_SYSTIME; EXE$GET_SYSTIME(DST); END %; KEYWORDMACRO $SETIPL( NEWIPL, ENVIRON=MULTIPROCESSOR ) = BEGIN DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MTPR_IPL); LOCAL $$IPL_VAL; %IF NOT %NULL( NEWIPL ) %THEN $$IPL_VAL = NEWIPL; PAL_MTPR_IPL( .$$IPL_VAL ); %IF NOT %IDENTICAL( %STRING( ENVIRON ), %STRING( UNIPROCESSOR ) ) %THEN %IF NOT %CTCE( NEWIPL ) OR (%CTCE( NEWIPL ) AND NEWIPL GTR IPL$_ASTDEL) %THEN %WARN('Raising IPL to ',NEWIPL,' provides no multiprocessing synchronization') %FI %FI %ELSE $$IPL_VAL=IPL$_POWER; PAL_MTPR_IPL( .$$IPL_VAL ); %IF NOT %IDENTICAL( %STRING( ENVIRON ), %STRING( UNIPROCESSOR ) ) %THEN %WARN( 'Raising ipl to newipl provides no multiprocessing synchronization' ) %FI %FI END %; KEYWORDMACRO $LOCK_SYSTEM_PAGES ( LSP_START, LSP_END, NEWIPL ) = BEGIN LINKAGE MMG_LOCK_SYSTEM_PAGES_CALL = JSB (REGISTER = 0, REGISTER = 1) : NOTUSED (2,3,4,5,6,7,8,9,10,11); EXTERNAL ROUTINE MMG$LOCK_SYSTEM_PAGES_CALL : MMG_LOCK_SYSTEM_PAGES_CALL ADDRESSING_MODE (GENERAL) NOVALUE; DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MTPR_IPL); LOCAL $$IPL_VAL; MMG$LOCK_SYSTEM_PAGES_CALL (LSP_START, LSP_END); %IF NOT %NULL (NEWIPL) %THEN $$IPL_VAL = NEWIPL; PAL_MTPR_IPL (.$$IPL_VAL); %FI END %; KEYWORDMACRO $UNLOCK_SYSTEM_PAGES ( LSP_START, LSP_END, NEWIPL ) = BEGIN LINKAGE MMG_UNLOCK_SYSTEM_PAGES_CALL = JSB (REGISTER = 0, REGISTER = 1) : NOTUSED (2,3,4,5,6,7,8,9,10,11); EXTERNAL ROUTINE MMG$UNLOCK_SYSTEM_PAGES_CALL: MMG_UNLOCK_SYSTEM_PAGES_CALL ADDRESSING_MODE (GENERAL) NOVALUE; DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MTPR_IPL); LOCAL $$IPL_VAL; MMG$UNLOCK_SYSTEM_PAGES_CALL (LSP_START, LSP_END); %IF NOT %NULL (NEWIPL) %THEN $$IPL_VAL=NEWIPL; PAL_MTPR_IPL (.$$IPL_VAL); %FI END %; ! ! The simple SMP MACROS: ! MACRO ! ! Lock SYSTEM SPINLOCK ! SYS_LOCK (LOCKNAME, LOCKIPL, SAVIPL, CONDITION) = BEGIN ! ! LINKAGES: ! LINKAGE SMP_ACQUIRE = JSB ( REGISTER = 0 ) : NOTUSED (1,2,3,4,5,6,7,8,9,10,11) ; EXTERNAL ROUTINE SMP$ACQUIRE : SMP_ACQUIRE NOVALUE ADDRESSING_MODE (GENERAL) ; DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MFPR_IPL); ; %IF NOT %NULL(SAVIPL) %THEN %REF(SAVIPL) = PAL_MFPR_IPL (); %FI SMP$ACQUIRE (%NAME('SPL$C_', LOCKNAME)) END % ; MACRO ! ! Unlock SYSTEM SPINLOCK ! SYS_UNLOCK (LOCKNAME, NEWIPL, CONDITION) = BEGIN ! ! LINKAGES: ! LINKAGE SMP_RESTORE = JSB ( REGISTER = 0 ) : NOTUSED (1,2,3,4,5,6,7,8,9,10,11), SMP_RELEASE = JSB ( REGISTER = 0 ) : NOTUSED (1,2,3,4,5,6,7,8,9,10,11) ; EXTERNAL ROUTINE SMP$RESTORE : SMP_RESTORE NOVALUE ADDRESSING_MODE (GENERAL), SMP$RELEASE : SMP_RELEASE NOVALUE ADDRESSING_MODE (GENERAL) ; DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MTPR_IPL); ; LOCAL $$IPL_VAL; %IF %IDENTICAL (CONDITION,'RESTORE') %THEN SMP$RESTORE (%NAME('SPL$C_', LOCKNAME)); %ELSE SMP$RELEASE (%NAME('SPL$C_', LOCKNAME)); %FI %IF NOT %NULL(NEWIPL) %THEN $$IPL_VAL=NEWIPL; PAL_MTPR_IPL (.$$IPL_VAL) %FI END % ; MACRO ! ! Lock FORK SPINLOCK ! FORKLOCK (LOCKID, LOCKIPL, SAVIPL, CONDITION) = BEGIN ! ! LINKAGES: ! LINKAGE SMP_ACQUIRE = JSB ( REGISTER = 0 ) : NOTUSED (1,2,3,4,5,6,7,8,9,10,11) ; EXTERNAL ROUTINE SMP$ACQUIRE : SMP_ACQUIRE NOVALUE ADDRESSING_MODE (GENERAL) ; SMP$ACQUIRE (LOCKID) END % ; MACRO ! ! Unlock SYSTEM SPINLOCK ! FORKUNLOCK (LOCKID, NEWIPL, CONDITION) = BEGIN ! ! LINKAGES: ! LINKAGE SMP_RESTORE = JSB ( REGISTER = 0 ) : NOTUSED (1,2,3,4,5,6,7,8,9,10,11), SMP_RELEASE = JSB ( REGISTER = 0 ) : NOTUSED (1,2,3,4,5,6,7,8,9,10,11) ; EXTERNAL ROUTINE SMP$RESTORE : SMP_RESTORE NOVALUE ADDRESSING_MODE (GENERAL), SMP$RELEASE : SMP_RELEASE NOVALUE ADDRESSING_MODE (GENERAL) ; DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MTPR_IPL); ; LOCAL $$IPL_VAL; %IF %IDENTICAL (CONDITION,'RESTORE') %THEN SMP$RESTORE (LOCKID); %ELSE SMP$RELEASE (LOCKID); %FI %IF NOT %NULL(NEWIPL) %THEN $$IPL_VAL=NEWIPL; PAL_MTPR_IPL (.$$IPL_VAL) %FI END % ; ! ! ---- < End of module SMPMAC.REQ - 30-MAR-2010 16:39:01.99 > - ! ! Version: X-8 ! !***************************************************************************** ! Copyright 2002 Compaq Information Technologies Group, L.P. ! ! Compaq and the Compaq logo are trademarks of Compaq Information ! Technologies Group, L.P. in the U.S. and/or other countries. ! ! Confidential computer software. Valid license from Compaq required for ! possession, use or copying. Consistent with FAR 12.211 and 12.212, ! Commercial Computer Software, Computer Software Documentation, and ! Technical Data for Commercial Items are licensed to the U.S. Government ! under vendor's standard commercial license. !****************************************************************************/ ! ! FACILITY: ! ! VMSLIB -- THREAD-MACROS.REQ ! ! ABSTRACT: ! ! This module contains macros that are used by Kernel Threads. ! They are of a general sort, and will be included in LIB.REQ and ! LIB.L32 (and LIB.L64); ! ! AUTHORS: ! ! Ellen M. Batbouta ! ! CREATION DATE: 7 February 1995 ! ! MODIFICATION HISTORY: ! ! X-8 Burns Fisher 01-Nov-2002 ! Conditionalize for IA64 ! ! X-7 Clair Grant 03-Jun-2002 ! Change "BUILTIN R0" to "LOCAL PCBB". ! ! X-6 Clair Grant 10-May-2002 ! Add some %QUOTEs to DEFINE_BUILTIN uses. ! ! X-5 Clair Grant HP merger day ! Use DEFINE_BUILTIN for PAL_xxx ! ! X-4 DMB Dave Bernardo 31-Mar-1999 ! Use the results of the ldqp directly. Trying to sign extend ! it doesn't work anyway. ! ! X-3 DMB Dave Bernardo 04-Nov-1996 ! New WTAMI algorithm ! ! X-2 EMB0366 Ellen M. Batbouta 30-March-1995 ! Declare CTL$GL_PCB to be of type signed long to ensure that this ! macro works for BLISS64 as well as BLISS32. ! !-- !++ ! Define macro to get the address of the current kernel thread block (KTB) !-- MACRO get_curktb = ( BEGIN %IF NOT %DECLARED(CTL$GL_PCB) %THEN EXTERNAL CTL$GL_PCB : SIGNED LONG; %FI ! ! The following should be defined in ARCH_DEFS.REQ, but you can't easily include ! that file into a macro, and we don't want to have to change all the modules that ! call this code, so we do this. (BTW, we use literal rather than macro since JR ! says defining a macro within a macro is troublesome). ! %IF NOT %DECLARED(%QUOTE %QUOTE ALPHA) %THEN literal ALPHA = (%BLISS(BLISS32E) OR %BLISS(BLISS64E)); literal IA64 = (%BLISS(BLISS32I) OR %BLISS(BLISS64I)); ! = 0 if compiled /VAX or /Ann %FI %IF ALPHA %THEN DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_MFPR_PCBB); DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_LDQP); %IF NOT %DECLARED(MMG$GL_BWP_MASK) %THEN EXTERNAL MMG$GL_BWP_MASK : UNSIGNED LONG; %FI LOCAL current_ktb: signed long, ktbvec: ref vector[,long,signed], my_id: unsigned long, pcb: ref $bblock, pcbb; ! Get the current PCB ! pcb = .ctl$gl_pcb; ! Does process have more than 1 execution context? ! IF .pcb[pcb$l_kt_count] LSS 2 THEN current_ktb = .pcb ELSE BEGIN ! Get the physical address of the current HWPCB ! pcbb = PAL_MFPR_PCBB(); IF (.pcbb AND (fred$k_length - 1)) NEQ 0 THEN current_ktb = .pcb ELSE BEGIN ! Does process have more than one fred page? ! IF NOT .pcb[pcb$v_fredlock] THEN BEGIN ! Convert to a kernel thread id ! my_id = (.pcbb AND .mmg$gl_bwp_mask) ^ - fred$k_shift; ! Derive KTB address from id. ! ktbvec = .pcb[pcb$l_ktbvec]; current_ktb = .ktbvec[.my_id]; END ELSE BEGIN ! Read the KTB from the FRED block ! current_ktb = PAL_LDQP(.pcbb OR fred$c_ktb); END; END; END; ! Output from this macro is the address of the current KTB %ELSE %IF IA64 %THEN EXTERNAL ROUTINE swis$get_current_kt_id; LOCAL current_ktb: signed long, ktbvec: ref vector[,long,signed], my_id: unsigned long, pcb: ref $bblock ; ! Get the current PCB ! pcb = .ctl$gl_pcb; ! Does process have more than 1 execution context? ! IF .pcb[pcb$l_kt_count] LSS 2 THEN current_ktb = .pcb ELSE BEGIN ! Get the physical address of the current HWPCB ! my_id = swis$get_current_kt_id(); ! Derive KTB address from id. ! ktbvec = .pcb[pcb$l_ktbvec]; current_ktb = .ktbvec[.my_id]; END; ! Output from this macro is the address of the current KTB %ELSE %ERROR('Unknown architecture') %FI %FI .current_ktb END ) %; ! ! ---- < End of module THREAD-MACROS.REQ - 30-MAR-2010 16:39:03.30 > - ! !Version: X-71 ! ! **************************************************************************** ! * * ! * Copyright (c) 1992-2008 Hewlett-Packard Development Company, L.P. * ! * * ! * RESTRICTED RIGHTS LEGEND * ! * * ! * Use, duplication or disclosure by the U.S. Government is subject to * ! * restrictions as set forth in subparagraph (c)(1)(ii) of the Rights * ! * in Technical Data and Computer Software clause in DFARS 252.227-7013. * ! * * ! * Hewlett-Packard Development Company, L.P * ! * 3000 Hanover Street * ! * Palo Alto, CA 94304 * ! * U.S.A. * ! * * ! * Rights for non-DOD U.S. Government Departments and Agencies are as * ! * set forth in FAR 52.227-19(c)(1,2). * ! * * ! **************************************************************************** ! !++ ! FACILITY: ! ! VMSLIB -- VMS-MACROS.REQ ! ! ABSTRACT: ! ! This module contains a lot of handy macros for systems programming in ! BLISS. They are of a general sort, and will be included in LIB.REQ and ! LIB.L32 (and LIB.L64); ! ! AUTHORS: ! ! VMS Development ! ! CREATION DATE: 13 September, 1988 ! ! MODIFICATION HISTORY: ! ! X-71 KSG Kevin Greaney 17-Nov-2008 ! Add optional parameter to $MOVE_QUAD, $OR_QUAD, ! $AND_QUAD, and $NOT_QUAD to specify the kind of ! alignment. This is an effort to fix up some of the ! alignment faults. ! ! X-70 WBF Burns Fisher 03-Jun-2008 ! Remove loop count from interlocked queue macros. We ! never see a badqhdr bug check, and the loop count can ! cause big trouble on fast CPUs and especially under ! HPVM. I could conditionalize it not to loop under HPVM, ! but I don't want to make the macro dependent on a ! system data cell when it was not before. ! ! X-69 KLN3604 Karen L. Noel 28-Sep-2005 ! o Change $probe to use exe_std$prober/w because this ! is now the main routine. The JSB routine calls the ! std routine. ! o Also, maximizing against previous mode is not needed ! when calling the exe routines as these rotuines already ! maximize against previous mode. ! ! X-68 CMOS Christian Moser 23-MAR-2004 ! Add new MAX_UNIT parameter to DPTAB macro. ! ! X-67 CMOS Christian Moser 7-SEP-2003 ! Add EXC_PRINT for xception tracing. ! ! X-66 Andy Kuehnel 13-May-2003 ! Fix exe$instimq linkage. ! ! X-65 Krishnan Venkatramanan 24-Mar-2003 ! Modified EXE$GENERATE_UID_LINKAGE NOTUSED registers to ! PRESERVE for IA64 port. ! ! X-64 Clair Grant 20-Nov-2002 ! Another try. Modules that do require arch_defs are ! confused. Change to %TARGET(%QUOTE %QUOTE ALPHA). ! ! X-63 Clair Grant 19-Nov-2002 ! Use %TARGET(ALPHA) instead of just ALPHA. We don't ! want to force sources to require arch_defs. ! ! X-62 Clair Grant 18-Nov-2002 ! In $BUG_CHECK, make the defining of EVX$PAL_BUGCHK ! Alpha only ! ! X-61 Clair Grant 10-Jun-2002 ! In the TBI_SINGLE, TBI_ALL, and TBI_DATA_64 macros use ! DEFINE_BUILTIN for PAL_MTPR_TBIx. ! ! X-59A1A5 Clair Grant 17-May-2002 ! Fix typo in PAL call ! ! X-59A1A4 ABP Anu Pant 14-May-2002 ! Add support for MPDEV_PATH_SWTCH routine. ! ! X-59A1A3 Clair Grant 16-May-2002 ! In the $bug_check macro, replace CALL_PAL with ! PAL_BUGCHK. Add many DEFINE_BUILTINs. ! ! X-59A1A2 Clair Grant 10-May-2002 ! Add some %QUOTEs to DEFINE_BUILTIN uses. ! Match version number to VDE. ! ! X-61 Clair Grant HP merger day ! Use DEFINE_BUILTIN for PAL_xxx ! ! X-60 CMOS Christian Moser 10-JAN-2002 ! Update comment for TR_PRINT macro to include example ! usage based on popular feedback request. ! ! X-59 CMOS Christian Moser 26-JUN-2001 ! Add new TR_PRINT macro, which can be used as a general ! purpose debug aid in combination with TR$DEBUG and TR$SDA. ! ! X-58 GP Genady Prechenko 15-May-1998 ! Changed DDT$IB_TYPE and DDT$IB_SUBTYPE to DDT$B_TYPE ! DDT$B_SUBTYPE. ! ! X-57 GP Genady Perchenko 12-May-1998 ! Add support for DPT$IL_DSPLYPATH_SIZE and ! DPT$IL_DSPLYPATH_UCB_OFS with following consistency checks: ! ! 1. Both fields should be non zero if ! DPT$M_MULTIPATH_SUP bit is set; ! ! 2. The sum of DPT$IL_DSPLYPATH_SIZE and ! DPT$IL_DSPLYPATH_UCB_OFS must be less then ! DPT$IL_UCBSIZE. ! ! Add initialization for DDT$IB_TYPE and DDT$IB_SUBTYPE fields. ! ! X-56 LJK Lawrence J. Kilgallen 11-May-1998 ! Replace ARG_VECTOR with the more arcane name ! CHANGE_MODE_ARG_VECTOR, so $kernel_call and ! $exec_call do not interfere with use of /CHECK=(REDECLARE). ! ! X-55 CMOS Christian Moser 20-APR-1998 ! Add Fastpath FDT routine and upcall routine to DDTAB macro. ! Changes to DDTDEF.SDL needs to be in lockstep with DDTAB ! macro. ! ! X-54 GP Genady Perchenko 14-Jan-1998 ! QAR 296 EVMS-RAVEN ! Added storing driver's file name within DPTAB. ! ! Added the following consistency checks to the DPTAB macro, ! similar to the checks in driver$ini_dpt_end. ! ! 1. if dpt$v_multipath_sup is set, dpt$v_devpath_sup ! must be set as well; ! ! 2. if dpt$v_devpath_sup is set, dpt$il_devpath_ucb_ofs ! must be non-zero; ! ! 3. if prt$v_devpath_sup is set, then sum of ! dpt$il_devpath_size and dpt$il_devpath_ucb_ofs must ! be less then dpt$il_ucbsize. ! ! X-53 GP Genady Perchenko 12-Dec-1997 ! Fiber Channel Device Naming Project: Add DEVPATH_SIZE and ! DEVPATH_UCB_OFS parameters to the DPTAB. See DPTDEF.SDL ! regarding respected DPT fields. ! ! Add MAKE_DEVPATH parameter to the DDTAB macro. See DDTDEF.SDL ! regarding DDT$PS_MAKE_DEVPATH field. ! ! See the design document in ! STAR::DOCD$:[EVMS.PROJECT_DOCUMENTS]FC_NAMING.PS for more ! details ! ! X-52 KSG0050 Kevin Greaney 20-Dec-1996 ! Mainline merge of Per-Thread Security support: (gen 50A2) ! ! X-50A2 WXD Bill Davenport 20-Aug-1996 ! Move EXE$CHKxxxACCES linkages to [LIB]SECURITY-MACROS.REQ. ! ! X-50A1 WXD Bill Davenport 27-Feb-1996 ! Mainline merge of Per-Thread Security. ! Move all security related definitions to SECURITY-MACROS.REQ. ! ! X-51 DMB Dave Bernardo 18-Dec-1996 ! Extend the FLAGS cability of the SYSTEM_SERVICE ! macro to allow more than 8 bits. ! ! X-50 NYK599 Nitin Y. Karkhanis 21-Mar-1996 ! o $kernel_call and $exec_call macros define a local ! vector for the argument list. This vector must be ! declared as a vector of longwords. Otherwise the ! vector will default to vector of quadwords when ! for Bliss-64 (VMS-MACROS.REQ is included in LIB.R64). ! o $restore_audit has to be aware of the compiler (Bliss-32 vs. ! Bliss-64) when declaring CTL$GL_PCB. For Bliss-64, ! CTL$GL_PCB must be declared as a signed longword, and then ! re-mapped to a block of bytes. If not, a quadword load ! an non-sign-extended %X80000000 address is fetched from ! CTL$GL_PCB which will in turn lead to an access violation. ! ! X-49 WXD Bill Davenport 14-Dec-1995 ! Add back some macros lost during the Per-Thread merge. ! ! X-48 WXD Bill Davenport 13-Dec-1995 ! Per-Thread Security Stage 1 checkin. ! Add linkages for low level persona and rights support ! routines and for the EXE$GENERATE_UID system routine. ! ! X-47 NYK520 Nitin Y. Karkhanis 30-Nov-1995 ! Add macros to fetch contents of item list entry fields. ! ! X-46 EMB0381 Ellen M. Batbouta 03-Oct-1995 ! Add NO_PCB symbol to TBI_DATA_64 and TBI_SINGLE macros. ! NYK503 Nitin Y. Karkhanis 20-Oct-1995 ! Code review comments. ! ! X-45 PJH Paul J. Houlihan 29-Jun-1995 ! Change the Pending I/O routine default. ! ! X-44 LSS0350 Leonard S. Szubowicz 28-Jun-1995 ! Change the Step 2 driver sub-version that is initialized by the ! DPTAB macro to DPT$K_STEP2_V5 for Theta EFT. See edit X-14 ! to DPTDEF.SDL. ! ! X-43 PJH Paul J. Houlihan 22-Jun-1995 ! Add initialization of new DDT routine vector cell to DDTAB ! ! X-42 LSS0345 Leonard S. Szubowicz 27-Apr-1995 ! Change the Step 2 driver sub-version that is initialized by the ! DPTAB macro to DPT$K_STEP2_V4 for Theta IFT. See edit X-13 ! to DPTDEF.SDL. ! ! X-41 EMB0354 Ellen M. Batbouta 24-Feb-1995 ! Add TB invalidate macros, TBI_ALL, TBI_DATA_64, and TBI_SINGLE. ! ! X-40 PAJ0817 Paul A. Jacobi 30-Jan-1995 ! Fix $TIMEDWAIT_10US macro to check the status returned from ! EXE$TIMEDWAIT_SETUP_10US. Merge of X-32U1. ! ! X-39 NYK230 Nitin Y. Karkhanis 27-Jan-1995 ! Remove all code relating to warnings about caller's ! mode services with a non-zero NARG that do not specify ! FLAGS=SSFLAG_K_64_BIT_ARGS. Too many facilities have ! builtin assumptions about what the SYSTEM_SERVICE macro ! does. ! ! X-38 NYK229 Nitin Y. Karkhanis 26-Jan-1995 ! SYSTEM_SERVICE macro was incorrectly displaying a ! warnings for caller's mode service THAT HAD specified ! FLAGS=SSFLAG_K_64_BIT_ARGS. ! ! X-37 JCH703 John C. Hallyburton, Jr. 21-Jan-1995 ! Fix DDTAB FAST_FDT entry to accept a routine name or 0. ! DOCD$:[EVMS.PROJECT_DOCUMENTS]FS-FASTIO.PS ! ! X-36 NYK207 Nitin Y. Karkhanis 18-Jan-1995 ! 64-bit support: SYSTEM_SERVICE macro flags a warning if ! a caller's mode service with NARG > 0 did specify that sign- ! extension checking should be bypassed. See page 175 of the ! OpenVMS 64-Bit Working Design specification. ! ! X-35 LSS0312 Leonard S. Szubowicz 24-Oct-1994 ! Change the Step 2 driver sub-version that is initialized by the ! DPTAB macro to DPT$K_STEP2_V3 because of the various I/O data ! structure changes that are necessary to support 64-bits and ! Fast I/O. See edit X-12 to DPTDEF.SDL. ! ! X-34 LSS0311 Leonard S. Szubowicz 18-Oct-1994 ! Add FDT_64 parameter to FDTAB keyword macro. This parameter ! is used to specify the functions that support a 64-bit $QIO P1 ! parameter. See "Chapter 20: QIO and Device Drivers" in ! DOCD$:[EVMS.CMS_64B]DS-64BITS.PS. ! Also, allow FDT_BUF parameter to be null. ! ! X-33 John C. Hallyburton, Jr. 5-Oct-1994 ! Add Fast-IO DDTAB definitions ! ! X-32 DEE0211 David E. Eiche 02-Jan-1994 ! Add PIC keyword to PSECT declarations so as not to ! generate too many image sections in the execlet. ! Also fix the default DDT name. ! ! X-31 DEE0210 David E. Eiche 30-Dec-1993 ! Fix DDTAB and DPTAB PSECT declarations to work with ! Pathworks drivers. ! ! X-30 SDD Steve DiPirro 28-DEC-1993 ! Change system_service macro to correspond to changes in ! the system service descriptor structure. ! ! X-29 ROW0844 Ralph O. Weber 21-DEC-1993 11:50 ! Update DPT$IW_STEPVER to signal data structure changes ! created in ROW0842. ! ! X-28 ROW0842 Ralph O. Weber 16-DEC-1993 16:28 ! Add DPTAB setup for DPT$IW_IOHANDLES. Add DDTAB setup for ! DDT$PS_CSR_MAPPING. These two new fields are part of driver- ! based PCI bus CSR mapping support. ! ! X-27 WDB:HLL82 Walter D. Blaschuk, Jr. 13-NOV-1993 ! HLLDD Project: Disable $COUNT_ENTRY macro. ! ! X-26 DEE0200 David E. Eiche 08-Oct-1993 ! HLLDD: Add DDTAB, DPTAB, and FDTAB macros to allow ! driver tables to be generated from BLISS. Add FDT ! completion routine macros. ! ! X-25 LSS0291 Leonard S. Szubowicz 9-Sep-1993 ! HLLDD: Remove definition of compiletime variable HLLDD$STEP1 ! as part of removing support for STEP=1 drivers. ! Also, remove obsolete JSB linkages: DEVICEDRIVER_FDT_LINKAGE, ! DEVICEDRIVER_CANCEL_LINKAGE, DEVICEDRIVER_SEL_CANCEL_LINKAGE, ! EXE$ABORTIO_LINKAGE, EXE$FINISHIO_LINKAGE, EXE$FINISHIOC_LINKAGE, ! EXE$IORSNWAIT_LINKAGE, EXE$QIODRVPKT_LINKAGE, EXE$QIORETURN_LINKAGE, ! EXE$READCHK_LINKAGE, EXE$WRITECHK_LINKAGE, IOC$UNLOCK_LINKAGE ! ! X-24 TRB Tom Benson 17-Aug-1993 ! Added linkages required for class scheduler: EXE$INSTIMQ_, ! EXE$RMVTIMQ_, EXE$MAXACMODE_, and SCH$CHSEP_. ! ! X-23 SAD Stuart A. Davidson 16-JUN-1993 ! Add $enable_auditing macro from late Blade change. ! ! X-22 SAD Stuart A. Davidson 24-MAY-1993 ! Fix decalraction scoping problem in $disable_auditing ! and $restore_auditing. ! ! X-21 SAD0279 Stuart A. Davidson 21-MAY-1993 ! Replace PCB$V_NOAUDIT flag with PCB$L_NOAUDIT count. ! ! X-20 CEG Clair Grant 10-MAY-1993 ! Update linkages for NSA$CHECK_AUDIT and NSA$AUDIT_EVENT. ! ! X-19 EMB Ellen M. Batbouta 04-May-1993 ! Preserve the appropriate registers, R3 (and R4, R5 ! for EXE$ALOPAGED) in the linkage declarations for ! EXE$ALOP1IMAG, EXE$ALOP0IMAG, EXE$ALOP1PROC, and ! EXE$ALOPAGED. ! ! X-18 CEG Clair Grant 15-APR-1993 ! Add $FIND_WITH_RETRY ! ! X-17 CEG Clair Grant 5-APR-1993 ! Update EXE$DELETE_ORB_LINKAGE and EXE$CLEANUP_ORB_LINKAGE ! ! X-16 CEG Clair Grant 26-MAR-1993 ! Add linkage for EXE$CVT_IPID_TO_PCB ! ! X-15 CEG Clair Grant 18-MAR-1993 ! Add linkages for: SCH$UNLOCK_QUAD, IOC$UNLOCK, IOC$IOLOCKW, ! NSA$DEVICE_AUDIT, NSA$QUEUE_DEACCESS, SCH$RWAITB, ! EXE$CVT_EPID_TO_PCB ! ! X-14 CEG Clair Grant 11-MAR-1993 ! Add linkages for: EXE$RESOLVE_ACL, IOC$INSTANTIATE_ORB, ! IOC$CREATE_DEVICE_ORB, NSA$STRIP_IMAGE_PRIVS, ! NSA$DEACCESS_AUDIT_LINKAGE ! ! X-13 CEG Clair Grant 8-MAR-1993 ! Remove IOC$VERIFYCHAN_LINKAGE; it's now a call interface. ! ! X-12 CEG Clair Grant 02-Mar-1993 ! Add the following macros: $ADD_ARG, $AND_THEN, $CLONE_ORB, ! $CLONE_TEMPLATE_ORB, $CREATE_ORB, $DISABLE_AUDIT, $EXEC_CALL, ! $HAS_PRIV, $KERNEL_CALL, $NAMELEN, $OR_ELSE, $OR_THEN, ! $PRIVS_TO_MASK, $PROBE_IN_DESCRIPTOR, $PROBE_OUT_DESCRIPTOR, ! $READ_IPL, $RESTORE_AUDIT, $$FLAGS-ORG, $SET_IPL, $$SET_PRIVS_H, ! $$SET_PRIVS_L, $$SET_PRIVS_OR, $$TRANSLATE_FLAGS_TO_NSA, ! $$TRANSLATE_FLAGS_TO_NSAP ! ! Add the following linkages: EXE$CLONE_ARB, EXE$CREDIT_BYTCNT, ! EXE$CREDIT_BYTCNT_BYTLIM, EXE$DEBIT_BYTCNT, ! EXE$DEBIT_BYTCNT_ALO, EXE$DEBIT_BYTCNT_BYTLIM, ! EXE$DEBIT_BYTCNT_BYTLIM_ALO, EXE$DEBIT_BYTCNT_NW, ! EXE$DEBIT_BYTCNT_BYTLIM_NW, EXE$JOIN_SYSTEM_DOMAIN, ! IOC$VERIFYCHAN, LCK$GET_DOMAIN_LCKCNT, NSA$DEALLOCATE_NSAB, ! SCH$CLREF ! ! X-11 LSS0263 Leonard S. Szubowicz 18-Jan-1993 ! Add $COUNT_ENTRY macro and compile-time constants ! SYS$COUNT_ENTRY_ENABLED and HLLDD$STEP1. ! ! NOTE: Ident number changed to reflect current master pack generation. ! ! X-24 KLN1222 Karen L. Noel 18-Nov-1992 ! Fix linkage for SCH$QAST. ! ! X-23 TJH001 Tom Hoey 27-Aug-1992 ! Add BLISS linkages for DECnet Phase V support. ! ! X-22 DMB Dave Bernardo 28-Jul-1992 ! Change handling of mode-of-caller services. ! ! X-21 KLN1208 Karen L. Noel 10-Jul-1992 ! Add flag to system_service macro. ! ! X-20 KLN1195 Karen L. Noel 27-May-1992 ! Move the SYSTEM_SERVICE macro from [SYS]PAGED_PSECTS.R32 ! to here. ! ! X-19 KAB Karen Barth 16-Mar-1992 ! Fix $SAY macro when more than one parameter. ! ! x-18 RS00200 Richard Sayde 15-Nov-1991 ! Fix $aprobe macro to use a set of PAL probes instead of ! EXE$PROBEx because the latter uses the VAX method of ! probes (it does the probe based on the previous mode ! instead of the current mode). ! ! X-17 RS00188 Richard Sayde 7-Nov-1991 ! Add reboot flag to $bug_check macro. ! ! X-16 KAB Karen Barth 30-Oct-1991 ! Fix null expression in $SAY macro. ! ! X-15 KAB Karen Barth 18-Oct-1991 ! Add VOLATILE attribute to OUT_BUF in $SAY macro. ! ! X-14 PAJ0573 Paul A. Jacobi 27-Sep-1991 ! Update $CPUDISP and $SYSDISP to remove possibility of a ! compiler warning if 'CONTINUE=YES' is specified. ! ! X-13 HH0725 Hai Huang 13-Sep-1991 ! Update $INSQ,$REMQ macros. ! ! X-12 CEG Clair Grant 05-Sep-1991 ! Fixes for HI_USE_PAGEABLE..... defs ! ! X-11 CEG Clair Grant 03-Sep-1991 ! Add EXEC$HI_USE_PAGEABLE_DATA option to ! $DECLARE_PSECT macro ! ! X-10 CEG Clair Grant 03-Sep-1991 ! Add EXEC$HI_USE_PAGEABLE_CODE option to ! $DECLARE_PSECT macro ! ! X-9 PAJ0562 Paul A. Jacobi 22-Aug-1991 ! Correct CONTINUE=NO logic of $SYSDISP and $CPUDISP macros. ! ! X-8 CEG Clair Grant 20-Aug-1991 ! EXEC$INIT_00n must be longword aligned. ! ! X-7 CEG Clair Grant 10-Aug-1991 ! Need to remove a %FI from the error conditional ! ! X-6 CEG Clair Grant 08-Aug-1991 ! The psect EXEC$INIT_SSTBL_001 must be longword aligned. ! ! X-5 CEG Clair Grant 08-Aug-1991 ! In $DECLARE_PSECT, make the default for all psects be ! 32-byte alignment. Remove EXEC$INIT_PFNTBL_001; it is not used. ! ! X-4 PAJ0495 Paul A. Jacobi 25-Apr-1991 ! Add optional parameters to $MCHECK_PROTECT macro. ! ! X-3 PAJ0486 Paul A. Jacobi 18-Apr-1991 ! Add $MCHECK_PROTECT macro. ! ! X-2 PAJ0464 Paul A. Jacobi 20-Mar-1991 ! Include new $CPUDISP and $SYSDISP macros. Reset module ! ident. ! ! X-1K11 PAJ0461 Paul A. Jacobi 06-Mar-1991 ! Correct quote level in $TIMEDWAIT_10US macro. ! ! X-1K10 PAJ0454 Paul A. Jacobi 05-Mar-1991 ! Rename TIMEDWAIT_10US to $TIMEDWAIT_10US. ! ! X-1K9 PAJ0451 Paul A. Jacobi 27-Feb-1991 ! Added TIMEDWAIT_10US macro. ! ! X-1K8 TNS Tom Scarpelli 7-Feb-1991 ! Change $PROBE macro to accept run-time mode field for RMS. ! ! X-1K7 TNS Tom Scarpelli 20-Dec-1990 ! Make $PROBE macro use the previous mode field. ! ! X-1K6 SDD Steve DiPirro 26-Oct-1990 ! Fix $MOVE_QUAD to work in cases where block/structure ! addresses passed as parameters too. ! ! X-1K5 SDD Steve DiPirro 18-Oct-1990 ! "Ported" the other macros to Alpha: ! - $PROBE made obsolete because of Alpha/VAX differences. ! - $APROBE replaces $PROBE for Alpha. ! - $INSQHI, $INSQTI updated. ! - $REMQHI, $REMQTI updated but not supported by EBLISS. ! So these merely print out compiler warning messages. ! - $MOVE_QUAD fixed for BLISS-32/BLISS-64. ! - $SAY fixed for BLISS-64. ! - $XDELTA JSB linkage fixed for EBLISS. ! ! X-1K4 SDD Steve DiPirro 15-Oct-1990 ! Added $xxx_PSECT_AT, $DECLARE_PSECT, and ! $INITIALIZATION_ROUTINE macros for building execlets. ! ! X-1K3 RS0018 Richard Sayde 23-Jul-1990 ! Fix typo in $bug_check macro. ! ! X-1K2 RS0011 Richard Sayde 11-Jul-1990 ! Made vms-macros.req architecture specific and ported the ! $bug_check macro to Alpha. No other macros ported. ! ! X-6 CAM0088 Christopher A. Mega 16-Nov-1989 ! Fix $INSQHI, $INSQTI, $REMQHI, $REMQTI macros. Fixes ! provided by Dave Marsh, Reading. Change involves swapping ! parameters to macros, and updating them to return the ! correct status of the actual queue operation. ! Bump version to match CMS generation ! ! X-4 JDC0558 Jon Callas 3-NOV-1989 ! $PROBE is not preserving R1 and R2 properly. ! ! X-3 DDP0393 Derrell D. Piper 28-JUL-1989 14:16 ! Move UTLDEFB to here. Add a couple of new macros: ! $xxx_WITH_RETRY ! $MOVE_QUAD ! $SAY ! $XDELTA ! ! X-2 EMB0423 Ellen M. Batbouta 21-Jul-1989 ! Add $INSQHI, $INSQTI, $REMQHI and $REMQTI. ! ! X-1 JDC0407 Jon Callas 13-SEP-1988 ! Create module. !-- LINKAGE COM$DELATTNAST_lINKAGE = JSB ( REGISTER = 4, ! Attention AST listhead address REGISTER = 5 ) : ! UCB address PRESERVE (0,1,2,3,4,5,6,7) NOTUSED (8,9,10,11), COM$DRVDEALMEM_LINKAGE = JSB (REGISTER = 0): ! Address of block to be deallocated PRESERVE (0,1,2,3,4,5) NOTUSED (6,7,8,9,10,11), COM$FLUSHATTNS_LINKAGE = JSB (REGISTER = 4, ! PCB address REGISTER = 5, ! UCB address REGISTER = 6, ! Number of the assigned I/O channel REGISTER = 7) : ! AST listhead address - destroyed on output PRESERVE (3,4,5,6) NOPRESERVE (0,1,2,7) ! R0 returns SS$_NORMAL, R1 and R2 are scratch. NOTUSED (8,9,10,11), COM$POST_LINKAGE = ! Note: R1 is documented as not being presrved JSB (REGISTER = 3, ! IRP address REGISTER = 5): ! UCB address PRESERVE (1,2,3,4,5) NOPRESERVE (0) ! R0, R1 scratch NOTUSED (6,7,8,9,10,11), COM$SETATTNAST_LINKAGE = JSB (REGISTER = 3, ! IRP address REGISTER = 4, ! PCB address REGISTER = 5, ! UCB address REGISTER = 7 ) : ! AST listhead address - destroyed on output PRESERVE (3,4,5,9,10) NOPRESERVE (0,1,2,6,7,8), ! R1, R2, R8 scratch EXE$ALLOCBUF_LINKAGE = JSB (REGISTER = 1; ! request size REGISTER = 2): ! address of block NOPRESERVE (3,4) PRESERVE (5) NOTUSED (6,7,8,9,10,11), EXE$ALONONPAGED_LINKAGE = JSB (REGISTER = 1; ! size of block required REGISTER = 1, ! actual size of allocated block REGISTER = 2) : ! address of allocated block PRESERVE (3,4,5,6,7,8,9,10,11), ! Use EXE$ALONONPAGED !+ ! EXE$ALO_NPAGE_WAIT_LINKAGE = ! JSB (REGISTER = 0, ! address of cleanup routine (0 = none) ! REGISTER = 1; ! size of block required ! REGISTER = 1, ! actual size of allocated block ! REGISTER = 2) : ! address of allocated block ! NOPRESERVE (3,4,5), ! ! EXE$ALO_NPAGE_WAITS_LINKAGE = ! JSB (REGISTER = 0, ! address of cleanup routine (0 = none) ! REGISTER = 1; ! size of block required ! REGISTER = 1, ! actual size of allocated block ! REGISTER = 2) : ! address of allocated block ! NOPRESERVE (3,4,5), !- EXE$ALOP0IMAG_LINKAGE = JSB (REGISTER = 1; ! size of block required REGISTER = 1, ! actual size of allocated block REGISTER = 2) : ! address of allocated block PRESERVE (3), EXE$ALOP1IMAG_LINKAGE = JSB (REGISTER = 1; ! size of block required REGISTER = 1, ! actual size of allocated block REGISTER = 2) : ! address of allocated block PRESERVE (3), EXE$ALOP1PROC_LINKAGE = JSB (REGISTER = 1; ! size of block required REGISTER = 1, ! actual size of allocated block REGISTER = 2) : ! address of allocated block PRESERVE (3), EXE$ALOPAGED_LINKAGE = JSB (REGISTER = 1; ! size of block required REGISTER = 1, ! actual size of allocated block REGISTER = 2) : ! address of allocated block PRESERVE (3,4,5), EXE$CREDIT_BYTCNT_LINKAGE = ! Add amount to BYTCNT JSB (REGISTER = 0, ! request size REGISTER = 4): ! PCB address PRESERVE (4) NOTUSED (1, 2, 3, 5, 6,7,8,9,10,11), EXE$CREDIT_BYTCNT_BYTLM_LINKAGE = ! Add amount to BYTCNT and BYTLM JSB (REGISTER = 0, ! request size REGISTER = 4): ! PCB address PRESERVE (4) NOTUSED (1, 2, 3, 5, 6,7,8,9,10,11), EXE$CVT_EPID_TO_PCB_LINKAGE = JSB (REGISTER = 0; ! EPID to be converted REGISTER = 0): ! PCB address, or zero if any problems PRESERVE (1,2,3,4,5) NOTUSED (6,7,8,9,10,11), EXE$CVT_IPID_TO_PCB_LINKAGE = JSB (REGISTER = 0; ! IPID to be converted REGISTER = 0): ! PCB address, or zero if any problems PRESERVE (1,2,3,4,5) NOTUSED (6,7,8,9,10,11), EXE$DEANONPAGED_LINKAGE = JSB (REGISTER = 0): ! address of block to deallocate PRESERVE (4,5,6,7,8,9,10,11) NOPRESERVE (1,2,3), ! NOTE: SCH$RAVAIL may be called which is DOCUMENTED as ! destroying R3, however I don't believe it does. In ! the philosophy of "better safe than sorry" however... EXE$DEANONPGDSIZ_LINKAGE = JSB (REGISTER = 0, ! address of block to deallocate REGISTER = 1) : ! size of block to deallocate NOPRESERVE (2,3,4,5), EXE$DEAP1_LINKAGE = JSB (REGISTER = 0, ! address of block to deallocate REGISTER = 1) : ! size of block to deallocate NOPRESERVE (2,3), EXE$DEAPAGED_LINKAGE = JSB (REGISTER = 0) : ! address of block to deallocate NOPRESERVE (2,3,4,5), EXE$DEAPGDSIZ_LINKAGE = JSB (REGISTER = 0, ! address of block to deallocate REGISTER = 1) : ! size of block to deallocate NOPRESERVE (2,3,4,5), EXE$DEBIT_BYTCNT_LINKAGE = ! Debit BYTCNT, do not allocate pool. JSB (REGISTER = 1, ! request size REGISTER = 4): ! PCB address PRESERVE (1, 4) NOTUSED (2, 3, 5, 6,7,8,9,10,11), EXE$DEBIT_BYTCNT_BYTLM_LINKAGE = ! Debit BYTCNT & BYTLM, do not al JSB (REGISTER = 1, ! request size REGISTER = 4): ! PCB address PRESERVE (1, 4) NOTUSED (2, 3, 5, 6,7,8,9,10,11), EXE$DEBIT_BYTCNT_ALO_LINKAGE = ! Debit BYTCNT and allocate pool. JSB (REGISTER = 1, ! request size REGISTER = 4; ! PCB address REGISTER = 2): ! address of block NOPRESERVE (3,4) PRESERVE (5) NOTUSED (6,7,8,9,10,11), EXE$DEBIT_BYTCNT_BYTLM_ALO_LNKG = ! Debit BYTCNT and BYTLM, alloca JSB (REGISTER = 1, ! request size REGISTER = 4; ! PCB address REGISTER = 2): ! address of block NOPRESERVE (3,4) PRESERVE (5) NOTUSED (6,7,8,9,10,11), EXE$DEBIT_BYTCNT_NW_LINKAGE = ! Debit BYTCNT, don't allocate, neve JSB (REGISTER = 1, ! request size REGISTER = 4): ! PCB address PRESERVE (1, 4) NOTUSED (2, 3, 5, 6,7,8,9,10,11), EXE$DEBIT_BYTCNT_BYTLM_NW_LNKG = ! Debit both, don't allocate, nev JSB (REGISTER = 1, ! request size REGISTER = 4): ! PCB address PRESERVE (1, 4) NOTUSED (2, 3, 5, 6,7,8,9,10,11), EXE$EPID_TO_IPID_LINKAGE = JSB (REGISTER = 0; ! EPID to be converted REGISTER = 0): ! IPID or zero if any problems PRESERVE (1,2,3,4,5) NOTUSED (6,7,8,9,10,11), EXE$EPID_TO_PCB_LINKAGE = JSB (REGISTER = 0; ! EPID REGISTER = 0): ! PCB address or zero if any problems PRESERVE (1,2,3,4,5) NOTUSED (6,7,8,9,10,11), EXE$CVT_IPID_TO_EPID_LINKAGE = JSB (REGISTER = 0; ! IPID to be converted REGISTER = 0): ! EPID or zero if any problems PRESERVE (1,2,3,4,5) NOTUSED (6,7,8,9,10,11), EXE$IPID_TO_PCB_LINKAGE = JSB (REGISTER = 0; ! IPID REGISTER = 0): ! PCB address or zero if any problems PRESERVE (1,2,3,4,5) NOTUSED (6,7,8,9,10,11), EXE$JOIN_SYSTEM_DOMAIN_LINKAGE = JSB, ! No arguments EXE$SNDEVMSG_LINKAGE = ! Linkage for EXE$SNDEVMSG routine in Mailbox Driver. ! The parameters, PRESERVE and NOPRESERVEs are as documented below, simply ! for compatibility reasons. JSB(REGISTER = 3, ! Mailbox UCB address REGISTER = 4, ! Message Type REGISTER = 5) : ! Device UCB address NOPRESERVE (0,1,2,3,4) PRESERVE (5,6,7,8,9,10,11), EXE$SENDMSG_LINKAGE = JSB (REGISTER = 3, ! Message size REGISTER = 4, ! Message address REGISTER = 5) : ! UCB address of mailbox NOPRESERVE (2), EXE$WRTMAILBOX_LINKAGE = ! The parameters, PRESERVE and NOPRESERVEs are as documented below, simply ! for compatibility reasons. JSB( REGISTER = 3, ! Message Size REGISTER = 4, ! Message Address REGISTER = 5): ! Mailbox UCB Address PRESERVE (3,4,5,6,7,8,9,10,11) NOPRESERVE (0,1,2), EXE$ACQUIRE_OLCK_LINKAGE = JSB ( REGISTER = 2, ! rsn REGISTER = 3, ! parid REGISTER = 4, ! flags REGISTER = 5 ), ! olck EXE$RELEASE_OLCK_LINKAGE = JSB ( REGISTER = 1, ! flags REGISTER = 4 ), ! olck EXE$RUNDOWN_OLCKS_LINKAGE = JSB, ! Standard Call entry !+ ! INITIALIZATION_RTN_JSB = ! Loadable image init routine ! JSB (REGISTER = 5; ! Inirtn flags ! REGISTER = 0) : ! Return status ! NOPRESERVE(0,1,2,3) ! PRESERVE (4,5,6,7,8,9,10,11), !- IOC$CREATE_DEVICE_ORB_LINKAGE = JSB (REGISTER = 0, ! address of name desc REGISTER = 1; ! device class REGISTER = 1): ! address of new ORB PRESERVE (2,3,4,5,6,7,8,9,10,11), IOC$CVT_DEVNAM_LINKAGE = JSB (REGISTER = 0, ! Input length of output buffer, output final conversion status ! SS$_NORMAL or ! SS$_BUFFEROVF (an alternate success status which ! indicates that the supplied buffer could not ! hold the device name string) REGISTER = 1, ! Input address of output buffer REGISTER = 4, ! Input name string formation mode REGISTER = 5; ! Address of device UCB REGISTER = 1): ! Output Length of conversion string. R1 = 0 if the alternate path name ! was requested, but none exists. NOPRESERVE (0,1) PRESERVE (2,3,4,5,6,7,8,9,10,11), IOC$INSTANTIATE_ORB_LINKAGE = JSB (REGISTER = 1, ! ORB REGISTER = 2), ! UCB IOC$REQCOM_LINKAGE = JSB (REGISTER = 0, ! I/O STATUS first longword REGISTER = 1, ! I/O Status second word REGISTER = 5): ! UCB address PRESERVE (4,5,6,7,8,9,10,11) NOPRESERVE (0,1,2,3), LCK$GET_DOMAIN_LCKCNT_LINKAGE = JSB (REGISTER = 0, ! flags REGISTER = 1, ! resource domain ID REGISTER = 4; ! PCB REGISTER = 1 ) : ! [OUT] count of locks PRESERVE (2,3,4,5,6,7,8,9,10,11), LNM$LOCKR_LINKAGE = JSB (REGISTER = 4) : ! PCB address PRESERVE (1,4,5,6,7,8,9,10,11) NOPRESERVE (0,2,3), LNM$LOCKW_LINKAGE = JSB (REGISTER = 4): ! PCB address PRESERVE (1,4,5,6,7,8,9,10,11) NOPRESERVE (0,2,3), LNM$UNLOCK_LINKAGE = JSB (REGISTER = 4) : ! PCB PRESERVE (4,5,6,7,8,9,10,11) NOPRESERVE (0,1,2,3), ! R0-R3 scratch LNM$DELETELNMB_LINKAGE = JSB ( REGISTER = 1): ! Address of logical name table entry PRESERVE (4,5,6,7,8,9,10,11) NOPRESERVE (0,1,2,3), ! R0 - Status: ! SS$_NORPRIV if logical name table is a directory ! SS$_NORMAL ! SS$_NOLOGNAM if there are o such logical names. SCH$CLREF_LINKAGE = JSB (REGISTER = 3, ! EFN number (low byte, zero filled) REGISTER = 4) : ! PCB address NOPRESERVE (2,3,4,5), SCH$FORCEDEXIT_LINKAGE = JSB (REGISTER = 0, REGISTER = 3, REGISTER = 4) : NOPRESERVE(1,2) PRESERVE(5) NOTUSED(6,7,8,9,10,11), SCH$IOLOCKW_LINKAGE = JSB (REGISTER = 4) : ! address of PCB NOPRESERVE (0), SCH$LOCKR_LINKAGE = JSB (REGISTER = 0, ! address of mutex REGISTER = 4) : ! address of PCB NOPRESERVE (2,3), SCH$LOCKW_LINKAGE = JSB (REGISTER = 0, ! address of mutex REGISTER = 4) : ! address of PCB NOPRESERVE (2,3), SCH$LOCKREXEC_LINKAGE = JSB (REGISTER = 0) : ! address of mutex NOPRESERVE (1, 2, 3), SCH$UNLOCKEXEC_LINKAGE = JSB (REGISTER = 0) : ! address of mutex NOPRESERVE (1, 2, 3), SCH$POSTEF_LINKAGE = JSB (REGISTER = 1, ! PID REGISTER = 2, ! priority increment class number REGISTER = 3; ! EFN number REGISTER = 4) : ! PCB address of process specified by PID PRESERVE (5,6,7,8,9,10,11), SCH$QAST_LINKAGE = JSB (REGISTER = 2, ! Priority boost REGISTER = 5; ! ACB address REGISTER = 4) : ! PCB address NOPRESERVE (1,2,3,4,5) NOTUSED (6,7,8,9,10,11), SCH$RAVAIL_LINKAGE = ! Implicit input: IPL <= SYNCH JSB ( REGISTER = 0 ): ! Resource Number PRESERVE (4,5,6,7,8,9,10,11) NOPRESERVE (0,1,2,3), ! R1-R3 are destroyed ! (NOTE: I think only R2 is actually destroyed, but just to be safe...) SCH$RWAITB_LINKAGE = JSB (REGISTER = 0, ! Resource number REGISTER = 1, ! PSL for return REGISTER = 4) : ! PCB address NOPRESERVE (2,3) PRESERVE (4,5,6,7,8,9,10,11), SCH$UNLOCK_LINKAGE = JSB (REGISTER = 0, ! address of mutex REGISTER = 4) : ! address of PCB NOPRESERVE (2,3), SCH$UNLOCK_QUAD_LINKAGE = JSB (REGISTER = 0, ! address of mutex REGISTER = 4) : ! address of PCB NOPRESERVE (2,3), EXE$INSTIMQ_LINKAGE = JSB (REGISTER = 0, ! Abs due time low half REGISTER = 1, ! Abs due time high half REGISTER = 5; ! Address of TQE REGISTER = 5) : ! Address of PHD returned NOPRESERVE(2,3) NOTUSED(6,7,8,9,10,11), EXE$RMVTIMQ_LINKAGE = JSB (REGISTER = 2, ! ACMODE, access mode REGISTER = 3, ! REQIDT, id # REGISTER = 4, ! TQEADR, address if kn REGISTER = 5) : ! PID NOPRESERVE(1) NOTUSED(6,7,8,9,10,11), EXE$MAXACMODE_LINKAGE = JSB (REGISTER = 0) : ! Mode parameter NOPRESERVE(1) NOTUSED(2,3,4,5,6,7,8,9,10,11), SCH$CHSEP_LINKAGE = JSB (REGISTER = 0, ! priority increment cl REGISTER = 4; ! PCB to make executable REGISTER = 2) : ! per-CPU data block NOPRESERVE(1,2) PRESERVE(3) NOTUSED(5,6,7,8,9,10,11), EXE$GENERATE_UID_LINKAGE = ! Generate a UID JSB (REGISTER = 1) : ! Address of UID storage area NOPRESERVE (2) PRESERVE (3, 4, 5, 6, 7, 8, 9, 10, 11); MACRO $getpsl (x) = !+ ! This macro fetches the current processor status longword ! It is usefull for insulating programmers from Alpha/VAX differences ! when code needs to determine current/previous mode. !- begin define_builtin(%quote %quote %quote pal_rd_ps); pal_rd_ps() end %; MACRO $probe ($$loc, $$len, $$type, $$mode) = !+ ! This macro probes a range using PROBEx or EXE_STD$PROBEx. ! ! $$loc is the starting address of the range. ! $$len is the length of the range ! $$type is the type of probe to be done, allowable values are: ! ! R -- probe for read access. If the probe is a compile-time constant less ! than a page in length, then PROBER is used, otherwise EXE_STD$PROBER is used. ! ! W -- probe for write access as per R above. ! ! RQ -- probe for read access, but always use a PROBER instruction. A Mnemonic ! for the Q is "quick." ! ! WQ -- probe for write access, as per RQ. ! ! $$mode is the mode of the probe, maximized with the previous mode -- ! defaults to 0 if not specified. ! ! The macro returns a value that is either true or false, suitable for use in an ! IF statement. ! ! NOTE: On Alpha, PROBE probes accessability at either the specified mode or ! the current mode, whichever is larger. To emulate VAX PROBEs, this ! macro will do a RD_PS to read the previous mode field (which is one of ! the "reserved to software" fields). It will then take the maximum of ! that and the specified mode. PROBE will then take the maximum of that ! and the current mode for the access check. ! !- BEGIN COMPILETIME quick = 0; %IF %LENGTH LSS 3 %THEN %ERROR('Too few parameters in $PROBE') %FI %IF (NOT %IDENTICAL($$type,r)) AND (NOT %IDENTICAL($$type,w)) AND (NOT %IDENTICAL($$type,rq)) AND (NOT %IDENTICAL($$type,wq)) %THEN %ERROR('Error in $PROBE, ',%STRING(%NAME($$type)),' is an illegal type.') %FI %IF %IDENTICAL($$type,rq) OR %IDENTICAL($$type,wq) %THEN %ASSIGN(quick,1) %FI %IF quick OR (%CTCE($$len) AND ($$len LEQ 8192)) %THEN MACRO pbuiltin = %IF %IDENTICAL($$type,r) or %IDENTICAL($$type,rq) %THEN PAL_PROBER %ELSE PAL_PROBEW %FI %QUOTE % ; DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_RD_PS); BUILTIN pbuiltin; LOCAL PS : BLOCK[8,BYTE] INITIAL(PAL_RD_PS()); %IF %LENGTH GEQ 4 %THEN pbuiltin($$loc,$$len - 1,MAX(.PS[PSL$V_PRVMOD],$$mode)) %ELSE pbuiltin($$loc,$$len - 1,MAX(.PS[PSL$V_PRVMOD],0)) %FI %ELSE EXTERNAL ROUTINE %NAME('EXE_STD$PROBE',$$type); %IF %LENGTH GEQ 4 %THEN %NAME('EXE_STD$PROBE',$$type)($$loc,$$len,$$mode) %ELSE %NAME('EXE_STD$PROBE',$$type)($$loc,$$len,0) %FI %FI END %; MACRO $aprobe ($$loc, $$len, $$type, $$mode) = !+ ! This macro probes a range using PROBEx(s). It has replaced ! the $PROBE macro for Alpha/EVMS since the two are used differently. ! ! $$loc is the starting address of the range. ! $$len is the length of the range ! $$type is the type of probe to be done, allowable values are: ! ! R -- probe for read access. If the probe is a compile-time less than ! 8192 in length (minimum page size), then PROBER is used, otherwise ! a set of PROBERs are used in a loop. ! ! W -- probe for write access as per R above. ! ! RQ -- probe for read access, but always use a PROBER instruction. A Mnemonic ! for the Q is "quick." ! ! WQ -- probe for write access, as per RQ. ! ! $$mode is the mode of the probe, maximized with the current mode -- ! defaults to 0 if not specified. ! ! The macro returns a value that is either true or false, suitable for use in an ! IF statement. ! ! NOTE: On Alpha, PROBE probes accessability at either the specified mode or ! the current mode, whichever is larger. To emulate VAX PROBEs, pass the ! previous mode in the mode argument. It will take the max of that and ! the current mode for the access check. ! !- BEGIN COMPILETIME quick = 0, pmode = 0; EXTERNAL mmg$gl_bwp_mask: LONG, mmg$gl_page_size: LONG; %IF %LENGTH LSS 3 %THEN %ERROR('Too few parameters in $PROBE') %FI %IF %LENGTH GEQ 4 %THEN %IF %CTCE($$mode) %THEN %ASSIGN(pmode,$$mode) %ELSE %ERROR('Error in $PROBE, ',$$mode,' must be a compile-time constant.') %FI %FI %IF (NOT %IDENTICAL($$type,r)) AND (NOT %IDENTICAL($$type,w)) AND (NOT %IDENTICAL($$type,rq)) AND (NOT %IDENTICAL($$type,wq)) %THEN %ERROR('Error in $PROBE, ',$$type,' is an illegal type.') %FI MACRO pbuiltin = %IF %IDENTICAL($$type,r) or %IDENTICAL($$type,rq) %THEN PAL_PROBER %ELSE PAL_PROBEW %FI %QUOTE % ; BUILTIN pbuiltin; %IF %IDENTICAL($$type,rq) OR %IDENTICAL($$type,wq) %THEN %ASSIGN(quick,1) %FI %IF quick OR (%CTCE($$len) AND ($$len LEQ 8192)) %THEN ! Quick method requested or the length is a compile time ! constant less than the minimum page size (8192). pbuiltin($$loc,$$len - 1,pmode) %ELSE ! Not sure if we cross a page boundary or not. Used run time ! code to do a page at a time LOCAL $$probe_addr, $$probe_length, $$length_remaining, $$probe_ok; $$probe_addr = $$loc; $$length_remaining = $$len; $$probe_ok = 1; WHILE .$$probe_ok AND (.$$length_remaining GTR 0) DO BEGIN $$probe_length = MIN (.$$length_remaining, .mmg$gl_page_size - (.$$probe_addr AND .mmg$gl_bwp_mask)); $$length_remaining = .$$length_remaining - .$$probe_length; $$probe_ok = pbuiltin(.$$probe_addr,.$$probe_length-1,pmode); $$probe_addr = .$$probe_addr + .$$probe_length; END; .$$probe_ok %FI END %; MACRO $bug_check ($$name, $$type, $$reboot) = !+ ! This macro generates a bugcheck. It is analogous to the MACRO-32 BUG_CHECK ! macro. You use it with a call like $BUG_CHECK(VAXPORT,FATAL); ! ! Note that this macro generates a reference to an external symbol for the ! BUG$_WHATEVER code. It would be real nice if the BUG$_ codes were in LIB, but ! they're not, so they get resolved at link time. Sorry. ! ! $$name is the name of the of the bugcheck. VAXPORT, KRPEMPTY, etc. ! $$type is the type of the bugcheck. FATAL makes it a fatal bugcheck, ! anything else is a non-fatal bugcheck. Case doesn't matter. ! $$reboot is a flag to do either a warm or cold reboot. It only applies if ! the bugcheck is fatal. !- BEGIN DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_HALT); DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE PAL_BUGCHK); COMPILETIME FatalError = 0, ColdReboot =0; %IF (NOT %DECLARED (%NAME ('bug$_', $$name))) %THEN EXTERNAL LITERAL %NAME ('bug$_', $$name); %FI %IF %TARGET(%QUOTE %QUOTE ALPHA) %THEN %IF (NOT %DECLARED (evx$pal_bugchk)) %THEN EXTERNAL LITERAL evx$pal_bugchk; %FI %FI !++ ! determine if the BUG_CHECK is fatal or not !-- %IF (%LENGTH EQL 0) %THEN ! no parameters passed, error %ERROR (%ASCII 'First parameter of BUG_CHECK macro required') %ELSE %IF (%LENGTH EQL 1) %THEN ! only one parameter, assume Type is NONFATAL %ASSIGN (FatalError, 0) %ELSE ! more than one parameter %IF (%IDENTICAL ($$type,FATAL)) %THEN %ASSIGN (FatalError, 1) %ELSE %ASSIGN (FatalError, 0) %FI %FI %FI !++ ! determine if this is a cold or warm reboot !-- %IF (%LENGTH GTR 2) %THEN %IF (FatalError EQL 0) %THEN %WARN (%ASCII'Reboot qualifier ignored on non-fatal bugchecks') %ASSIGN (ColdReboot, 0) %ELSE %IF (%IDENTICAL ($$reboot,COLD_REBOOT)) %THEN %ASSIGN (ColdReboot, 1) %ELSE %ASSIGN (ColdReboot, 0) %FI %FI %ELSE %ASSIGN (ColdReboot, 0) %FI !++ ! execute the BUG_CHECK !-- %IF (FatalError EQL 1) %THEN %IF (ColdReboot EQL 1) %THEN ! bugcheck is ORed with STS$K_SEVERE and low bit set (= 5) PAL_BUGCHK (5 OR %NAME ('bug$_',$$name)); %ELSE ! bugcheck is ORed with STS$K_SEVERE (= 4) PAL_BUGCHK (4 OR %NAME ('bug$_',$$name)); %FI PAL_HALT(); %ELSE PAL_BUGCHK (%NAME ('bug$_', $$name)); %FI END %; !+ ! $INSQHI - Execute an interlocked queue insert instruction and retry if ! failure. ! $INSQTI ! ! INPUT: ! ! ENTRY - Address of entry to be inserted in queue ! HEAD - Address of queue header ! ! Note: System is bug_checked if queue operation fails because secondary ! interlock bit stays set. !- MACRO $insqhi (entry, head) = BEGIN DEFINE_BUILTIN(%QUOTE %QUOTE %QUOTE PAL_INSQHIL); LOCAL counter : INITIAL (0), status : SIGNED; WHILE (status = pal_insqhil (head, entry)) LSS 0 DO; .status END%; MACRO $insqti (entry, head) = BEGIN DEFINE_BUILTIN(%QUOTE %QUOTE %QUOTE PAL_INSQTIL); LOCAL counter : INITIAL (0), status : SIGNED; WHILE (status = pal_insqtil (head, entry)) LSS 0 DO; .status END%; !+ ! $REMQHI - Execute an interlocked queue remove instruction and retry if failure ! $REMQTI ! ! INPUT: ! ! Head - Address of queue header ! Entry - Address of a longword where the address of the entry removed ! is to be stored ! ! ! Note: System is bug_checked if queue operation fails because secondary ! interlock bit stays set. !- MACRO $remqhi (head, entry) = BEGIN DEFINE_BUILTIN(%QUOTE %QUOTE %QUOTE PAL_REMQHIL); LOCAL counter : INITIAL (0), status : SIGNED; WHILE (status = pal_remqhil (head; entry)) LSS 0 DO; .status END %; MACRO $remqti (head, entry) = BEGIN DEFINE_BUILTIN(%QUOTE %QUOTE %QUOTE PAL_REMQTIL); LOCAL counter : INITIAL (0), status : SIGNED; WHILE (status = pal_remqtil (head; entry)) LSS 0 DO; .status END %; !+ ! $GET_WITH_RETRY perform an RMS $GET with automatic retry ! $FIND_WITH_RETRY perform an RMS $FIND with automatic retry ! $PUT_WITH_RETRY perform an RMS $PUT with automatic retry ! $UPDATE_WITH_RETRY perform an RMS $UPDATE with automatic retry ! $DELETE_WITH_RETRY perform an RMS $DELETE with automatic retry ! ! INPUT: ! ! RAB address of RAB ! SUC address of routine to execute on successful completion ! ERR address of routine to execute on failure !- ! This macro is used by the RMS retry macros. MACRO $$retry (service, r, e, s) = BEGIN LITERAL $$retry_limit = 10, ! number of times to retry $$sleep_rlk = 500; ! 500 ms before retrying BIND $$wakedelta = UPLIT LONG (-10*1000*$$sleep_rlk,-1); LOCAL counter, status; counter = $$retry_limit; WHILE ((status = service (RAB = R %IF NOT %NULL(E) %THEN , ERR = E %FI %IF NOT %NULL(S) %THEN , SUC = S %FI) ) EQL rms$_rlk) AND ((counter = .counter - 1) GEQ 0) DO IF $schdwk (DAYTIM = $$wakedelta) THEN $hiber; .status END %; ! The following four keyword macros mimic the real RMS macro definitions. Each ! of these macros performs the normal RMS operation while providing for ! automatic retry on record-locked errors. Each operation will be retried ten ! times with a retry interval of 500 ms. ! KEYWORDMACRO $get_with_retry (rab, err, suc) = $$retry (%QUOTE %QUOTE $get, rab, err, suc) %, $put_with_retry (rab, err, suc) = $$retry (%QUOTE %QUOTE $put, rab, err, suc) %, $update_with_retry (rab, err, suc) = $$retry (%QUOTE %QUOTE $update, rab, err, suc) %, $find_with_retry (rab, err, suc) = $$retry (%quote %quote $find, rab, err, suc) %, $delete_with_retry (rab, err, suc) = $$retry (%QUOTE %QUOTE $delete, rab, err, suc) %; !+ ! ! Quadword macros: ! ! $MOVE_QUAD (SRC, DST) Move quadword from SRC to DST ! $OR_QUAD (SRC1, SRC2, DST) Store the logical OR of SRC1 and SRC2 into DST ! $AND_QUAD (SRC1, SRC2, DST) Store the logical AND of SRC1 and SRC2 into DST ! $NOT_QUAD (SRC, DST) Store the logical NOT of SRC into DST ! ! An extra parameter has been added to each of these macros called ALGN. ! This provides alignment for the source and destination parameters, and ! resolves a number of alignment faults. The default alignment, if the ALGN ! parameter is not passed in, is set to longword alignment. ! ! These macros should do the exact same thing for both BLISS-32 and BLISS-64. ! !- MACRO $move_quad (src, dst, algn) = BEGIN %if %length eql 2 %then literal algn_ = 2; %else literal algn_ = algn; %fi bind src_ = src : vector[,long] align(algn_), dst_ = dst : vector[,long] align(algn_); dst_[0] = .src_[0]; dst_[1] = .src_[1]; END %, $or_quad (src1, src2, dst, algn) = BEGIN %if %length eql 3 %then literal algn_ = 2; %else literal algn_ = algn; %fi bind src1_ = src1 : vector[,long] align(algn_), src2_ = src2 : vector[,long] align(algn_), dst_ = dst : vector[,long] align(algn_); dst_[0] = .src1_[0] or .src2_[0]; dst_[1] = .src1_[1] or .src2_[1]; END %, $and_quad (src1, src2, dst, algn) = BEGIN %if %length eql 3 %then literal algn_ = 2; %else literal algn_ = algn; %fi bind src1_ = src1 : vector[,long] align(algn_), src2_ = src2 : vector[,long] align(algn_), dst_ = dst : vector[,long] align(algn_); dst_[0] = .src1_[0] and .src2_[0]; dst_[1] = .src1_[1] and .src2_[1]; END %, $not_quad (src, dst, algn) = BEGIN %if %length eql 2 %then literal algn_ = 2; %else literal algn_ = algn; %fi bind src_ = src : vector[,long] align(algn_), dst_ = dst : vector[,long] align(algn_); dst_[0] = not .src_[0]; dst_[1] = not .src_[1]; END %; !+ ! ! Macro to output a formatted string. ! ! Usage: ! ! $SAY ('This is a simple string...'); ! $SAY ('This is a !AS string with a unsigned longword (!XL) in it...', %ascid'formatted', 42); ! !- MACRO $say (string) = BEGIN EXTERNAL ROUTINE lib$put_output, sys$fao; LOCAL out_buf : VOLATILE BLOCK[132,BYTE], out : VECTOR[2,LONG] INITIAL(LONG(%ALLOCATION(out_buf), out_buf)); sys$fao(%ASCID string, out, out %IF %LENGTH GTR 1 %THEN , %REMAINING %FI); lib$put_output(out); END %; !+ ! ! Macro to take an XDELTA breakpoint, if XDELTA is loaded. ! ! Usage: ! ! $XDELTA; ! !- MACRO $xdelta = BEGIN LINKAGE l_ini$brk = JSB; EXTERNAL ROUTINE ini$brk : l_ini$brk; ini$brk(); END %; ! ! $xxx_PSECT_AT ! ! The following macros define the PSECT attributes for the standard ! VMS exec PSECTs. The attribute macro name is the PSECT name prefixed ! with a "$" and suffixed by "_PSECT_AT". These macros can then be ! used in any PSECT declarations with these PSECT names, and the ! attributes are defined in just one place (for BLISS) - here. ! ! The macros defined here are: ! ! $EXEC$NONPAGED_DATA_PSECT_AT ! $EXEC$NONPAGED_CODE_PSECT_AT ! $EXEC$PAGED_DATA_PSECT_AT ! $EXEC$PAGED_CODE_PSECT_AT ! $EXEC$HI_USE_PAGEABLE_D_PSECT_A ! $EXEC$HI_USE_PAGEABLE_C_PSECT_A ! $EXEC$INIT_000_PSECT_AT ! $EXEC$INIT_001_PSECT_AT ! $EXEC$INIT_CODE_PSECT_AT ! $EXEC$INIT_SSTBL_001_PSECT_AT ! $EXEC$UNL_000_PSECT_AT ! $EXEC$UNL_001_PSECT_AT ! $EXEC$NONPAGED_LINKAGE_PSECT_AT ! $EXEC$PAGED_LINKAGE_PSECT_AT ! $EXEC$HI_USE_PAGEABLE_L_PSECT_A ! $EXEC$INIT_LINKAGE_PSECT_AT ! ! Input (to some of them): ! ! ALIGNMENT - If a different alignment than the default is required ! ! MACRO $exec$nonpaged_data_psect_at(alignment) = %if %null(alignment) %then WRITE,NOEXECUTE,PIC,ALIGN(5) %else WRITE,NOEXECUTE,PIC,ALIGN(alignment) %fi %, $exec$nonpaged_code_psect_at(alignment) = %if %null(alignment) %then NOWRITE,EXECUTE,PIC,ALIGN(5) %else NOWRITE,EXECUTE,PIC,ALIGN(alignment) %fi %, $exec$paged_data_psect_at(alignment) = %if %null(alignment) %then WRITE,NOEXECUTE,PIC,ALIGN(5) %else WRITE,NOEXECUTE,PIC,ALIGN(alignment) %fi %, $exec$paged_code_psect_at(alignment) = %if %null(alignment) %then NOWRITE,EXECUTE,PIC,ALIGN(5) %else NOWRITE,EXECUTE,PIC,ALIGN(alignment) %fi %, $exec$hi_use_pageable_d_psect_a(alignment) = %if %null(alignment) %then WRITE,NOEXECUTE,PIC,ALIGN(5) %else WRITE,NOEXECUTE,PIC,ALIGN(alignment) %fi %, $exec$hi_use_pageable_c_psect_a(alignment) = %if %null(alignment) %then NOWRITE,EXECUTE,PIC,ALIGN(5) %else NOWRITE,EXECUTE,PIC,ALIGN(alignment) %fi %, $exec$init_000_psect_at = READ,WRITE,EXECUTE,PIC,ALIGN(2) %, $exec$init_001_psect_at = READ,WRITE,EXECUTE,PIC,ALIGN(2) %, $exec$init_code_psect_at(alignment) = %if %null(alignment) %then READ,WRITE,EXECUTE,PIC,ALIGN(5) %else READ,WRITE,EXECUTE,PIC,ALIGN(alignment) %fi %, $exec$init_sstbl_001_psect_at = READ,WRITE,EXECUTE,PIC,ALIGN(2) %, $exec$unl_000_psect_at = WRITE,NOEXECUTE,PIC,ALIGN(5) %, $exec$unl_001_psect_at = WRITE,NOEXECUTE,PIC,ALIGN(5) %, $exec$nonpaged_linkage_psect_at = READ,WRITE,NOEXECUTE,PIC,NOSHARE,CONCATENATE,ALIGN(5) %, $exec$paged_linkage_psect_at = READ,WRITE,NOEXECUTE,PIC,NOSHARE,CONCATENATE,ALIGN(5) %, $exec$hi_use_pageable_l_psect_a = READ,WRITE,NOEXECUTE,PIC,NOSHARE,CONCATENATE,ALIGN(5) %, $exec$init_linkage_psect_at = READ,WRITE,EXECUTE,PIC,NOSHARE,CONCATENATE,ALIGN(5) %; ! ! $DECLARE_PSECT ! ! This macro is used to declare psects within the loadable images ! of the VMS executive. It makes sure all the psects have ! compatible attributes across all the images. Note that it is NOT ! necessary to explicitly declare LINKage section psect names as ! they are done implicitly for each of the appropriate code PSECTs. ! Also note that these macros redefine all the BLISS data PSECTs ! (PLIT, OWN, GLOBAL) for each data PSECT name. ! ! Inputs: ! PSECT_NAME - PSECT_NAME is one of the standard VMS executive psects: ! EXEC$NONPAGED_DATA ! EXEC$NONPAGED_CODE ! EXEC$PAGED_DATA ! EXEC$PAGED_CODE ! EXEC$HI_USE_PAGEABLE_DATA ! EXEC$HI_USE_PAGEABLE_CODE ! EXEC$INIT_000 ! EXEC$INIT_001 ! EXEC$INIT_CODE ! EXEC$INIT_SSTBL_001 ! EXEC$UNL_000 ! EXEC$UNL_001 ! ! ! ALIGNMENT - If a different alignment than the default is required ! MACRO $declare_psect(psect_name,alignment) = %if %identical(psect_name,exec$nonpaged_data) %then PSECT PLIT = exec$nonpaged_data( $exec$nonpaged_data_psect_at(alignment)), OWN = exec$nonpaged_data( $exec$nonpaged_data_psect_at(alignment)), GLOBAL = exec$nonpaged_data( $exec$nonpaged_data_psect_at(alignment)) %else %if %identical(psect_name,exec$nonpaged_code) %then PSECT LINK = exec$nonpaged_linkage( $exec$nonpaged_linkage_psect_at), CODE = exec$nonpaged_code( $exec$nonpaged_code_psect_at(alignment)) %else %if %identical(psect_name,exec$paged_data) %then PSECT PLIT = exec$paged_data( $exec$paged_data_psect_at(alignment)), OWN = exec$paged_data( $exec$paged_data_psect_at(alignment)), GLOBAL = exec$paged_data( $exec$paged_data_psect_at(alignment)) %else %if %identical(psect_name,exec$paged_code) %then PSECT LINK = exec$paged_linkage( $exec$paged_linkage_psect_at), CODE = exec$paged_code( $exec$paged_code_psect_at(alignment)) %else %if %identical(psect_name,exec$hi_use_pageable_data) %then PSECT PLIT = exec$hi_use_pageable_data( $exec$hi_use_pageable_d_psect_a(alignment)), OWN = exec$hi_use_pageable_data( $exec$hi_use_pageable_d_psect_a(alignment)), GLOBAL = exec$hi_use_pageable_data( $exec$hi_use_pageable_d_psect_a(alignment)) %else %if %identical(psect_name,exec$hi_use_pageable_code) %then PSECT LINK = exec$hi_use_pageable_linkage( $exec$hi_use_pageable_l_psect_a), CODE = exec$hi_use_pageable_code( $exec$hi_use_pageable_c_psect_a(alignment)) %else %if %identical(psect_name,exec$init_000) %then PSECT PLIT = exec$init_000($exec$init_000_psect_at), OWN = exec$init_000($exec$init_000_psect_at), GLOBAL = exec$init_000($exec$init_000_psect_at) %else %if %identical(psect_name,exec$init_001) %then PSECT PLIT = exec$init_001($exec$init_001_psect_at), OWN = exec$init_001($exec$init_001_psect_at), GLOBAL = exec$init_001($exec$init_001_psect_at) %else %if %identical(psect_name,exec$init_code) %then PSECT LINK = exec$init_linkage( $exec$init_linkage_psect_at), CODE = exec$init_code( $exec$init_code_psect_at(alignment)) %else %if %identical(psect_name,exec$init_sstbl_001) %then PSECT PLIT = exec$init_sstbl_001( $exec$init_sstbl_001_psect_at), OWN = exec$init_sstbl_001( $exec$init_sstbl_001_psect_at), GLOBAL = exec$init_sstbl_001( $exec$init_sstbl_001_psect_at) %else %if %identical(psect_name,exec$unl_000) %then PSECT PLIT = exec$unl_000($exec$unl_000_psect_at), OWN = exec$unl_000($exec$unl_000_psect_at), GLOBAL = exec$unl_000($exec$unl_000_psect_at) %else %if %identical(psect_name,exec$unl_001) %then PSECT PLIT = exec$unl_001($exec$unl_001_psect_at), OWN = exec$unl_001($exec$unl_001_psect_at), GLOBAL = exec$unl_001($exec$unl_001_psect_at) %else %error('Unrecognized PSECT declaration') %fi %fi %fi %fi %fi %fi %fi %fi %fi %fi %fi %fi %; ! ! $INITIALIZATION_ROUTINE ! ! This macro declares a routine to be an initialization routine. It ! enters an absolute vector for the routine in the initialization ! routine vector table, guaranteeing that this routine will be called ! when the image is loaded by the VMS linker/loader. ! ! INPUTS: ! ! NAME - name of the initialization OR unload routine. ! SYSTEM_RTN - 1 if the initialization/unload routine is external to this ! image (i.e. in system space). Defaults to 0 and is only valid ! for VAX (ignored for Alpha). ! UNLOAD - 1 if this is an unload routine. Defaults to 0. ! PRIORITY - if 1,then this argument indicates that this entry should ! be placed into the appropriate table as one of the first ! entries. The tables (one for INITIALIZATION routines and ! one for UNLOAD routines) consist of two psects. Routines ! which specify PRIORITY will be placed in the first psect. ! Routines which do not specify this argument will be placed ! in the second psect. The routines in the first psect will ! be called before the routines in the second psect, thus ! giving them priority. Defaults to 0. ! ! OUTPUTS: ! A vector and a flags longword is entered into the initialization ! or unload routine vector table for each routine. ! KEYWORDMACRO $initialization_routine( name, system_rtn=0, ! Ignored for Alpha unload=0, priority=0) = %if unload EQL 0 %then ! Default case %if priority EQL 0 %then PSECT NODEFAULT = exec$init_001($exec$init_001_psect_at); OWN $$tmp_vec: VECTOR[2,LONG] PSECT(exec$init_001) %else PSECT NODEFAULT = exec$init_000($exec$init_000_psect_at); OWN $$tmp_vec: VECTOR[2,LONG] PSECT(exec$init_000) %fi ! in first psect in table %else ! If unload=1 %if priority EQL 0 %then PSECT NODEFAULT = exec$unl_001($exec$unl_001_psect_at); OWN $$tmp_vec: VECTOR[2,LONG] PSECT(exec$unl_001) %else PSECT NODEFAULT = exec$unl_000($exec$unl_000_psect_at); OWN $$tmp_vec: VECTOR[2,LONG] PSECT(exec$unl_000) %fi %fi INITIAL(LONG(name,0)) %; !+ ! TIMEDWAIT_10US ! ! This macro loops around the supplied expression for then specified ! time or until the given expressions returns true (1). The macro returns ! the value of the expression which will be true (1) if the time has ! not been exceeded or false (0) if the time limit has been exceeded. ! ! EXAMPLE: ! ! STATUS = TIMEDWAIT_10US (10*1000*1000, ! Wait 10 seconds or until ! .CSR[BIIC$V_STS]);! self test status bit it set. ! ! IF NOT .STATUS THEN ERROR(); ! ! ! INPUT: ! TIME - Time in 10 microsecond units ! EXPRESSION - Any valid BLISS expression. When true (1) ! will cause TIMEDWAIT_10US macro to exit. ! BUS - (optional parameter) When present indicate ! the BUS type for EXE$BUS_DELAY ! !-- MACRO $TIMEDWAIT_10US (TIME,EXPRESSION,BUS) = BEGIN LOCAL DELTA: VECTOR[2,LONG], END_TIME: VECTOR[2,LONG], REMAINING_TIME, STATUS; %IF NOT %DECLARED (%QUOTE %QUOTE EXE$TIMEDWAIT_SETUP_10US) %THEN EXTERNAL ROUTINE EXE$TIMEDWAIT_SETUP_10US; %FI %IF NOT %DECLARED (%QUOTE %QUOTE EXE$BUS_DELAY) %THEN EXTERNAL ROUTINE EXE$BUS_DELAY; %FI %IF NOT %DECLARED (%QUOTE %QUOTE EXE$TIMEDWAIT_COMPLETE) %THEN EXTERNAL ROUTINE EXE$TIMEDWAIT_COMPLETE; %FI DELTA[0] = TIME; DELTA[1] = 0; STATUS = EXE$TIMEDWAIT_SETUP_10US(DELTA,END_TIME); IF .STATUS THEN BEGIN STATUS = 0; REMAINING_TIME = 1; WHILE ((NOT .STATUS) AND .REMAINING_TIME) DO BEGIN STATUS = EXPRESSION %IF NOT %NULL(BUS) %THEN EXE$BUS_DELAY(BUS) %FI; REMAINING_TIME = EXE$TIMEDWAIT_COMPLETE(END_TIME); END; END; .STATUS END %; !+ ! $CPUDISP ! ! This macro conditionally executes the suppied expressions based upon ! the primary CPU type in EXE$GQ_CPUTYPE, initialized from the HWRPB. See ! [LIB]HWRPBDEF.SDL to add new CPU types which will automatically extend ! this macro. ! ! EXAMPLE: ! ! $CPUDISP('CONTINUE=NO', ! EV3, BEGIN X=2; Y=3; END, ! EV4, ROUT2()); ! ! INPUT: ! ! CONTINUE - If set to 'CONTINUE=NO', this macro will perform a ! $BUG_CHECK if executed on a CPU type that is not ! present in the dispatch list. In most cases it is ! best to specify 'CONTINUE=NO'. ! ! If set to 'CONTINUE=YES', control will pass to the ! next instruction following the macro if executed on ! a CPU type that is not present in the dispatch list. ! ! Note that this argument must be enclosed in single ! quote and in uppercase or a generated compiler error ! will be produced. ! ! DISPATCH LIST - A list of tupples where the first element is a ! CPU type and the second element is any valid BLISS ! expression to be execute only if running on the ! the CPU type indicated by the first element. ! !-- MACRO $CPUDISP (CONTINUE) [] = %IF (NOT %IDENTICAL(%STRING(CONTINUE),'CONTINUE=NO')) AND (NOT %IDENTICAL(%STRING(CONTINUE),'CONTINUE=YES')) %THEN %ERROR('Invalid CONTINUE argument of CPUDISP macro') %ELSE BEGIN %IF NOT %DECLARED(EXE$GQ_CPUTYPE) %THEN EXTERNAL EXE$GQ_CPUTYPE; %FI MACRO CASELINE[SYS,ACTION] = [%NAME('HWRPB_CPU_TYPE$K_',%STRING(SYS))]: ACTION %IF %NULL(%REMAINING) %THEN %QUOTE ; %IF %IDENTICAL(%STRING(CONTINUE),'CONTINUE=NO') %THEN [INRANGE]:$BUG_CHECK(UNSUPRTCPU); [OUTRANGE]:$BUG_CHECK(UNSUPRTCPU); %ELSE [INRANGE]:; [OUTRANGE]:; %FI %FI %QUOTE %; CASE .EXE$GQ_CPUTYPE FROM 1 TO HWRPB_CPU_TYPE$K_MAX_CPU_TYPE OF CASELINE(%REMAINING) END; %FI %; !+ ! $SYSDISP ! ! This macro conditionally executes the suppied expressions based upon ! the system type in EXE$GQ_SYSTYPE, initialized from the HWRPB. See ! [LIB]HWRPBDEF.SDL to add new system types which will automatically ! extend this macro. ! ! EXAMPLE: ! ! $SYSDISP('CONTINUE=NO', ! ADU, BEGIN X=2; Y=3; END, ! COBRA, ROUT2()); ! ! INPUT: ! ! CONTINUE - If set to 'CONTINUE=NO', this macro will perform a ! $BUG_CHECK if executed on a system type that is not ! present in the dispatch list. In most cases it is ! best to specify 'CONTINUE=NO'. ! ! If set to 'CONTINUE=YES', control will pass to the ! next instruction following the macro if executed on ! a CPU type that is not present in the dispatch list. ! Note that this argument must be enclosed in single ! quote and in uppercase or a generated compiler error ! will be produced. ! ! DISPATCH LIST - A list of tupples where the first element is a ! system type and the second element is any valid BLISS ! expression to be execute only if running on the ! the system type indicated by the first element. ! !-- MACRO $SYSDISP (CONTINUE) [] = %IF (NOT %IDENTICAL(%STRING(CONTINUE),'CONTINUE=NO')) AND (NOT %IDENTICAL(%STRING(CONTINUE),'CONTINUE=YES')) %THEN %ERROR('Invalid CONTINUE argument of SYSDISP macro') %ELSE BEGIN %IF NOT %DECLARED(EXE$GQ_SYSTYPE) %THEN EXTERNAL EXE$GQ_SYSTYPE; %FI MACRO CASELINE[SYS,ACTION] = [%NAME('HWRPB_SYSTYPE$K_',%STRING(SYS))]: ACTION %IF %NULL(%REMAINING) %THEN %QUOTE ; %IF %IDENTICAL(%STRING(CONTINUE),'CONTINUE=NO') %THEN [INRANGE]:$BUG_CHECK(UNSUPRTCPU); [OUTRANGE]:$BUG_CHECK(UNSUPRTCPU); %ELSE [INRANGE]:; [OUTRANGE]:; %FI %FI %QUOTE %; CASE .EXE$GQ_SYSTYPE FROM 1 TO HWRPB_SYSTYPE$K_MAX_SYSTYPE OF CASELINE(%REMAINING) END; %FI %; !++ ! $MCHECK_PROTECT ! ! This macro is used to execute an any BLISS expression protected from ! a machine check or other error. ! ! INPUT: ! ! MASK - Mask of errors to protect against ! EXPRESSION - Any BLISS expression to protect from error, limited ! to referencing the four LOCAL storage locations ! supplied in the optional arguments. The expression ! may reference an unlimited amount of OWN storage, ! however, OWN storage will not allow the routine to ! be re-entrant. ! P1, P2, P3, P4 - Optional parameters. Up to four LOCAL storage ! locations referenced by the expression. Required ! only if expression references LOCAL storage. ! ! EXAMPLE ! ! Assume CSR_BASE contains a base CSR address ! !BEGIN ! !OWN Y,CSR_BASE; !LOCAL X,Z; ! ! STATUS = $MCHECK_PROTECT(MCHK$M_NEXM, .X=..Z;, X, Z); ! IF .STATUS EQL SS$_MCHECK THEN ERROR(); ! ! STATUS = $MCHECK_PROTECT(MCHK$M_NEXM, Y=.CSR_BASE[CSR1];); ! IF .STATUS EQL SS$_MCHECK THEN ERROR(); ! !END; ! !-- MACRO $MCHECK_PROTECT (MASK, EXPRESSION) = BEGIN %IF %NULL(%REMAINING) %THEN ROUTINE MCHK$TEMP = %ELSE ROUTINE MCHK$TEMP(%REMAINING) = %FI BEGIN EXPRESSION; RETURN(SS$_NORMAL); END; EXTERNAL ROUTINE EXE$MCHECK_PROTECT; %IF %NULL(%REMAINING) %THEN EXE$MCHECK_PROTECT(MASK, MCHK$TEMP) %ELSE EXE$MCHECK_PROTECT(MASK, MCHK$TEMP, %REMAINING) %FI END %; !++ ! ! SYSTEM_SERVICE ! This macro declares a system service. ! ! MACRO PARAMETERS ! NAME - The name of the system service (less the prefix) ! NARG - The number of arguements for the system_service ! MARG - The mininum number of arguements (optional) ! MODE - The Change Mode (KERNEL, EXEC, or CALLERS_MODE) ! IMASK - The inhibit mask (optional) ! TYPE - Wait form type, some system services have a wait ! form (i.e. QIO and QIOW) (optional depending on ! the system service) ! EXIT - Some system services (RMS) perform their own ! exit code in addition to the normal system ! service exit code. This parameter will define ! the additional exit code to be used. (optional ! depending on the system service) ! PREFIX - Defines the prefix to be used to define the entry ! point, defaults to EXE$ (exec system services) ! FLAGS - (optional) SSFLAG_K_WCM or SSFLAG_K_WCMNO_REEXEC must be set ! if service could return SS$_WAIT_CALLERS_MODE, defaults to 0 ! ! OUTPUTS ! A system service descriptor table entry, used as input to the ! system service loader for inner mode services. ! ! __________________________________________________ ! | System Service Vector Address | ! -------------------------------------------------- ! | Procedure Descriptor of routine | ! -------------------------------------------------- ! | MODE | IMASK | FLAGS (byte) TYPE | ! -------------------------------------------------- ! | FLAGS32 Copy of FLAGS (allows 32 bits) | ! -------------------------------------------------- ! NOTE: EXIT_TYPE is not implemented on Alpha ! The first 8 bits of the FLAGS are stored in the byte field ! for backward compatibilty. A full 32 bit flags field ! is stored in what was previously a longword pad field. !-- KEYWORDMACRO SYSTEM_SERVICE(NAME,NARG,MARG,MODE,IMASK,TYPE,EXIT,PREFIX,FLAGS) = %IF %IDENTICAL(%NAME('MODE_K_',MODE),MODE_K_CALLERS_MODE) %THEN %IF %NULL(PREFIX) %THEN GLOBAL BIND ROUTINE %NAME('SYS$',NAME) = %NAME('EXE$',NAME); %ELSE ! %NULL(PREFIX) GLOBAL BIND ROUTINE %NAME('SYS$',NAME) = %NAME(PREFIX,NAME); %FI %ELSE %IF %NULL(PREFIX) %THEN EXTERNAL ROUTINE %NAME('SYS$',NAME); OWN %NAME('BASE_VECTOR_',NAME): LONG INITIAL(%NAME('SYS$',NAME)) PSECT(EXEC$INIT_SSTBL_001); OWN %NAME('SELF_RELATIVE_',NAME): LONG INITIAL(%NAME('EXE$',NAME)) PSECT(EXEC$INIT_SSTBL_001); %ELSE ! %NULL(PREFIX) EXTERNAL ROUTINE %NAME('SYS$',NAME); OWN %NAME('BASE_VECTOR_',NAME): LONG INITIAL(%NAME('SYS$',NAME)) PSECT(EXEC$INIT_SSTBL_001); OWN %NAME('SELF_RELATIVE_',NAME): LONG INITIAL(%NAME(PREFIX,NAME)) PSECT(EXEC$INIT_SSTBL_001); %FI ! %NULL(PREFIX) %IF %NULL(TYPE) %THEN OWN %NAME('TYPE_',NAME): BYTE INITIAL(TYPE_K_NORMAL) PSECT(EXEC$INIT_SSTBL_001); %ELSE ! %NULL(TYPE) OWN %NAME('TYPE_',NAME): BYTE INITIAL(%NAME('TYPE_K_',TYPE)) PSECT(EXEC$INIT_SSTBL_001); %FI ! %NULL(TYPE) %IF %NULL(FLAGS) %THEN OWN %NAME('FLAGS_',NAME): BYTE INITIAL(0) PSECT(EXEC$INIT_SSTBL_001); %ELSE ! %NULL(FLAGS) OWN %NAME('FLAGS_',NAME): BYTE INITIAL((FLAGS) AND 255) ! byte only PSECT(EXEC$INIT_SSTBL_001); %FI ! %NULL(FLAGS) %IF %NULL(IMASK) %THEN OWN %NAME('IMASK_',NAME): BYTE INITIAL(129) PSECT(EXEC$INIT_SSTBL_001); %ELSE ! %NULL(IMASK) OWN %NAME('IMASK_',NAME): BYTE INITIAL(IMASK) PSECT(EXEC$INIT_SSTBL_001); %FI ! %NULL(IMASK) %IF %NULL(MODE) %THEN %ERROR('NO MODE SPECIFIED FOR SYSTEM SERVICE') %ELSE ! %NULL(MODE) %IF %IDENTICAL(%NAME('MODE_K_',MODE),MODE_K_KERNEL) %THEN OWN %NAME('MODE_',NAME): BYTE INITIAL(MODE_K_KERNEL) PSECT(EXEC$INIT_SSTBL_001); %ELSE %IF %IDENTICAL(SSFLAG_K_WCM,FLAGS) OR %IDENTICAL(SSFLAG_K_WCM_NO_REEXEC,FLAGS) %THEN %ERROR('SS$_WAIT_CALLERS_MODE IN KERNEL_MODE ONLY') %FI %IF %IDENTICAL(%NAME('MODE_K_',MODE),MODE_K_EXEC) %THEN OWN %NAME('MODE_',NAME): BYTE INITIAL(MODE_K_EXEC) PSECT(EXEC$INIT_SSTBL_001); %ELSE %ERROR('ILLEGAL MODE-TYPE') %FI %FI %FI ! %NULL(MODE) %IF %NULL(FLAGS) %THEN OWN %NAME('FLAGS32_',NAME): LONG INITIAL(0) PSECT(EXEC$INIT_SSTBL_001); %ELSE ! %NULL(FLAGS) OWN %NAME('FLAGS32_',NAME): LONG INITIAL(FLAGS) PSECT(EXEC$INIT_SSTBL_001); %FI ! %NULL(FLAGS) %FI !%IDENTICAL(MODE) %IF %NULL(NARG) %THEN %ERROR('NUMBER OF ARGUEMENTS NOT SPECIFIED FOR SYSTEM SERVICE') %FI ! %NULL(NARG) BUILTIN ACTUALCOUNT; %IF %NULL(MARG) %THEN IF ACTUALCOUNT() LSSU NARG !Were enough argument passed? %ELSE ! %NULL(MARG) IF ACTUALCOUNT() LSSU MARG !Were enough argument passed? %FI ! %NULL(MARG) THEN RETURN SS$_INSFARG; %; !++ ! ! $COUNT_ENTRY ! This macro implements a debug-time counter of the number of entries ! into a given system routine. If the compile-time literal ! SYS$COUNT_ENTRY_ENABLED is defined, then this macro will create the ! counter and generate the code necessary to increment it. This macro ! provides equivalent functionality to the Macro-32 $COUNT_ENTRY macro ! which is defined in SYSMAR.MAR. The design documents STDCALLJACKETS.PS, ! JTOC_DESIGN.PS, and INBOUND_DRIVER.PS in EVMS$IO_CMS: rely on this ! macro to help with validation testing. ! ! MACRO PARAMETERS ! NAME - The name of the routine ! ! OUTPUTS ! Generates a global longword counter cell. Usually the counter cells ! are named CNT_'name'. However, if the resultant name is longer than ! 31 characters, then the first four characters of the routine name are ! dropped. The trailing characters of the routine name are much more ! likely to be required for uniqueness than the prefix characters. ! !-- ! DISABLED -- Commented out SYS$K_COUNT_ENTRY_ENABLED = 1 MACRO $COUNT_ENTRY (NAME) = %IF %DECLARED(SYS$K_COUNT_ENTRY_ENABLED) %THEN BEGIN $DECLARE_PSECT (EXEC$NONPAGED_DATA); !Counter is nonpaged GLOBAL $$COUNTER_NAME(NAME): INITIAL (0); $$COUNTER_NAME(NAME) = .$$COUNTER_NAME(NAME) + 1; END %FI %; ! $$COUNTER_NAME ! Helper macro for $COUNT_ENTRY. It expands to a valid counter variable ! name that is at most 31 characters long. ! MACRO $$COUNTER_NAME (NAME) = %IF %CHARCOUNT('CNT_',NAME) LEQ 31 %THEN %NAME('CNT_',NAME) %ELSE %NAME('CNT_',$$DROP4(%EXPLODE(NAME))) !Drop first 4 chars NAME %FI %; ! $$DROP4 ! Helper macro for $$COUNTER_NAME. It expands to a comma separated list ! of input parameters after the first 4 parameters are dropped. ! MACRO $$DROP4 (P1,P2,P3,P4) = %REMAINING % ; !++ ! The definition of the following compiletime variable enables expansion of ! the $$COUNT_ENTRY macro. For Macro-32, see [LIB]SYSMAR.MAR. !-- ! DISABLED -- DISABLED -- DISABLED !COMPILETIME ! SYS$K_COUNT_ENTRY_ENABLED = 1; ! $SET_IPL ! ! Set the process IPL. This (simple) macro should be used only by system ! services which need to raise IPL to IPL$_ASTDEL to block process deletion. ! ! Usage: ! ! $set_ipl (ipl$_astdel); ! $set_ipl (0); ! $set_ipl (.saved_ipl); ! ! $READ_IPL ! ! Read the process IPL. ! ! Usage: ! ! $read_ipl (saved_ipl); macro $set_ipl (level) = begin define_builtin (%quote %quote %quote pal_mtpr_ipl); pal_mtpr_ipl (level); end %, $read_ipl (dst) = begin define_builtin (%quote %quote %quote pal_mfpr_ipl); dst = pal_mfpr_ipl (); end %; ! $KERNEL_CALL ! $EXEC_CALL ! ! Call a routine via $CMKRNL or $CMEXEC. ! ! The following two macros violate the BLISS language definition in that they ! make use of the value of SP while building the argument list. It is the ! opinion of the BLISS maintainers that this usage is safe from planned ! future optimizations. ! ! These routines were taken from the XQP. ! ! Usage: ! ! status = $kernel_call (foo, arg1, argn); ! ! status = $exec_call (bar, arg1, argn); macro $kernel_call ( rtn_name, arguments ) = begin local change_mode_arg_vector : vector [%length, LONG]; compiletime change_mode_arg_vector_idx = 0; %assign (change_mode_arg_vector_idx, 0) change_mode_arg_vector [0] = %length - 1; %if %length - 1 gtr 0 %then $add_arg (arguments %if %length - 2 gtr 0 %then, %remaining %fi); %fi $cmkrnl (routin = rtn_name, arglst = change_mode_arg_vector) end %; macro $exec_call ( rtn_name, arguments ) = begin local change_mode_arg_vector : vector [%length, LONG]; compiletime change_mode_arg_vector_idx = 0; %assign (change_mode_arg_vector_idx, 0) change_mode_arg_vector [0] = %length - 1; %if %length - 1 gtr 0 %then $add_arg (arguments %if %length - 2 gtr 0 %then, %remaining %fi); %fi $cmexec (routin = rtn_name, arglst = change_mode_arg_vector) end %; macro $add_arg (parameter) [] = begin %assign (change_mode_arg_vector_idx, change_mode_arg_vector_idx + 1) change_mode_arg_vector [change_mode_arg_vector_idx] = parameter; %if %length - 1 gtr 0 %then $add_arg (%remaining); %fi end %; !+ ! ! Macro to return the actual length of a blank-filled string. ! ! Usage: ! ! USERNAME[DSC$W_LENGTH] = $NAMELEN (UAF$S_USERNAME, USERNAME_BUF); ! !- MACRO $NAMELEN (X, Y) = BEGIN LOCAL TEMP : REF VECTOR[,BYTE], R : INITIAL(0); TEMP = CH$FIND_CH(X,Y,%C' '); IF NOT CH$FAIL(.TEMP) THEN R = Y + X - .TEMP; X - .R END %; %SBTTL 'ORB processing routine interface macros' !+ ! This is just the temporary location for these macros. !- ! $CLONE_ORB ! ! Clone a Object Rights Block ! ! $CLONE srcorb, [alortn], [deartn], [objnam], flags, [itmlst], orb ! ! KEYWORDMACRO $CLONE_ORB (SRCORB, ALORTN = 0, DEARTN = 0, OBJNAM = 0, FLAGS = 0, ITMLST = 0, ORB ) = BEGIN EXTERNAL ROUTINE EXE$CLONE_ORB : BLISS ADDRESSING_MODE (GENERAL); EXE$CLONE_ORB ( SDL$STARLET_CONCAT ( SDL$STARLET_REQ (SRCORB, %QUOTE SRCORB), ALORTN, DEARTN, OBJNAM, FLAGS, ITMLST, SDL$STARLET_REQ(ORB, %QUOTE ORB) ) ) END %; ! $CREATE_ORB ! ! Create a Object Rights Block ! ! $CREATE_ORB [alortn], [deartn], [objnam], flags, [itmlst], orb ! ! KEYWORDMACRO $CREATE_ORB (ALORTN = 0, DEARTN = 0, OBJNAM, FLAGS = 0, ITMLST = 0, ORB ) = BEGIN EXTERNAL ROUTINE EXE$CREATE_ORB : BLISS ADDRESSING_MODE (GENERAL); EXE$CREATE_ORB ( SDL$STARLET_CONCAT (ALORTN, DEARTN, SDL$STARLET_REQ(OBJNAM, %QUOTE OBJNAM), FLAGS , ITMLST, SDL$STARLET_REQ(ORB, %QUOTE ORB))) END %; ! $CLONE_TEMPLATE_ORB ! ! Clone a Template (default) Object Rights Block ! ! $CLONE_TEMPLATE_ORB ocb, tmpnam, [alortn], [deartn], [objnam], ! [flags], [itmlst], orb ! ! KEYWORDMACRO $CLONE_TEMPLATE_ORB (OCB, TMPNAM, ALORTN = 0, DEARTN = 0, OBJNAM = 0, FLAGS = 0, ITMLST = 0, ORB ) = BEGIN EXTERNAL ROUTINE EXE$CLONE_TEMPLATE_ORB : BLISS ADDRESSING_MODE (GENERAL); EXE$CLONE_TEMPLATE_ORB ( SDL$STARLET_CONCAT ( SDL$STARLET_REQ (OCB, %QUOTE OCB), SDL$STARLET_REQ (TMPNAM, %QUOTE TMPNAM), ALORTN, DEARTN, OBJNAM, FLAGS, ITMLST, SDL$STARLET_REG(ORB, %QUOTE ORB) ) ) END %; ! $PROBE_IN_DESCRIPTOR ! $PROBE_OUT_DESCRIPTOR ! ! Probe a string descriptor and its associated buffer and copy the descriptor ! to local storage. This protocol is required for all system service input ! and output arguments which are passed by descriptor. ! ! Usage: ! ! global routine sys$service (foo) = ! . ! . ! . ! local ! local_foo : block[dsc$k_s_bln,byte]; ! local copy of FOO descriptor ! ! Required parameter: ! ! $probe_in_descriptor (foo, local_foo); ! ! Optional parameter: ! ! if .foo neqa 0 ! then ! $probe_in_descriptor (foo, local_foo); ! ! Returns: ! ! SS$_ACCVIO descriptor or buffer not accessible macro $probe_in_descriptor ($$desc, $$out, $$mode) = begin if not $probe (.$$desc, dsc$k_s_bln, rq) then return ss$_accvio; $$out[dsc$w_length] = .$$desc[dsc$w_length]; $$out[dsc$a_pointer] = .$$desc[dsc$a_pointer]; if not $probe (.$$out[dsc$a_pointer], .$$out[dsc$w_length], r) then return ss$_accvio; end %, $probe_out_descriptor ($$desc, $$out, $$mode) = begin if not $probe (.$$desc, dsc$k_s_bln, wq) then return ss$_accvio; $$out[dsc$w_length] = .$$desc[dsc$w_length]; $$out[dsc$a_pointer] = .$$desc[dsc$a_pointer]; if not $probe (.$$out[dsc$a_pointer], .$$out[dsc$w_length], w) then return ss$_accvio; end %; !+ ! $AND_THEN ! ! Calling: ! ! IF $AND_THEN ( cond1 [ , cond2 [ , cond3 ... ] ] ) THEN ... ! ! This macro accepts any number of conditional statements and returns the result ! of a logical AND of those statements. The difference between this and a ! standard BLISS "IF (COND1) AND (COND2) THEN" is that: ! (a) the order of evaluation is GUARANTEED to be left to right ! (b) as soon as one condition is found to be false, remaining conditions are ! NOT evaluated. ! ! For example, the following code, although it may currently generate the code ! you expect, is not guaranteed to (the BLISS apecification explicitly states ! that conditionals are NOT evaluated in any specific order). Assume that ! BLOCK has previously been declared as a REF BLOCK: ! ! IF (.BLOCK NEQA 0) AND (.BLOCK[BLK$V_FLAG]) THEN ... ! ! Using the $AND_THEN macro, correct code is guaranteed: ! ! IF $AND_THEN ( .BLOCK NEQA 0 , .BLOCK[BLK$V_FLAG] ) THEN ... ! ! Enclosing each conditional in parentheses is optional. !- MACRO $AND_THEN ( C1 )[] = %IF %NULL(%REMAINING) %THEN (C1) %ELSE ( IF (C1) THEN ($AND_THEN(%REMAINING)) ELSE 0 ) %FI % ; !+ ! $OR_ELSE ! $OR_THEN ! ! Calling: ! ! IF $OR_THEN ( cond1 [ , cond2 [ , cond3 ... ] ] ) THEN ... ! ! This macro accepts any number of conditional statements and returns the result ! of a logical OR of those statements. The difference between this and a ! standard BLISS "IF (COND1) AND (COND2) THEN" is that: ! (a) the order of evaluation is GUARANTEED to be left to right ! (b) as soon as one condition is found to be true, remaining conditions are ! NOT evaluated. ! ! For example, the following code, although it may currently generate the code ! you expect, is not guaranteed to (the BLISS apecification explicitly states ! that conditionals are NOT evaluated in any specific order). Assume that ! BLOCK has previously been declared as a REF BLOCK: ! ! IF (.BLOCK EQLA 0) OR (.BLOCK[BLK$V_FLAG]) THEN ... ! ! Using the $OR_THEN macro, correct code is guaranteed: ! ! IF $OR_THEN ( .BLOCK EQLA 0 , .BLOCK[BLK$V_FLAG] ) THEN ... ! ! Enclosing each conditional in parentheses is optional. !- MACRO $OR_THEN ( C1 )[] = %IF %NULL(%REMAINING) %THEN (C1) %ELSE ( IF (C1) THEN 1 ELSE ($OR_THEN(%REMAINING)) ) %FI % ; MACRO $OR_ELSE ( C1 )[] = %IF %NULL(%REMAINING) %THEN (C1) %ELSE ( IF (C1) THEN 1 ELSE ($OR_THEN(%REMAINING)) ) %FI % ; !++ ! ! Driver dispatch table generation macros ! !-- KEYWORDMACRO DDTAB (DEVNAM=DRIVER, ! device name for symbol START=0, ! start I/O routine CTRLINIT=0, ! controller init routine FUNCTB, ! FDT address CANCEL=0, ! cancel I/O routine REGDMP=0, ! register dump routine DIAGBF=0, ! diagnostic buffer size ERLGBF=0, ! error log buffer size UNITINIT=0, ! unit init routine ALTSTART=0, ! alt start I/O routine MNTVER=0, ! mount verification routine CLONEDUCB=0, ! cloned UCB routine MNTV_SSSC=0, ! mount ver rout. for shadow sets MNTV_FOR=0, ! mount ver rout. for /FOREIGN MNTV_SQD=0, ! mount ver rout. for tapes CHANNEL_ASSIGN=0, ! routine to call from $ASSIGN CANCEL_SELECTIVE=0, ! selective cancel routine KP_STACK_SIZE=0, ! KP stack byte count KP_REG_MASK=0, ! KP register save mask KP_STARTIO=0, ! start I/O for KP drivers CSR_MAPPING=0, ! CSR mapping routine MAKE_DEVPATH=0, ! path generation routine SETPRFPATH=0, ! fastpath FDT routine CHANGE_PREFERRED=0, ! fastpath upcall routine AUX_STORAGE=0, ! driver-dependent cell AUX_ROUTINE=0, ! driver-dependent cell PSECT_NAME=$$$110_DATA, ! DDT psect name STEP=2, ! driver step FAST_FDT=0, ! Fast-IO Fast-FDT PENDING_IO=0, ! Pending I/O routine MPDEV_PATH_SWTCH=0 ! Mpdev path switch routine ) = MACRO ! Nested DDTAB macros DDTAB_GENRADDR (RTN_NAME, DEFAULT) = %IF NOT %IDENTICAL (RTN_NAME, 0) %THEN (RTN_NAME) %ELSE %IF NOT %NULL (DEFAULT) %THEN (DEFAULT) %ELSE (ioc$return) %FI %FI %QUOTE %, DDTAB_REG_SPEC (REGISTER_LIST)[] = %IF %IDENTICAL (0, REGISTER_LIST) %THEN 0 %ELSE (1 ^ (REGISTER_LIST)) %IF %LENGTH GTR 1 %THEN OR DDTAB_REG_SPEC (%REMAINING) %FI %FI %QUOTE %; %IF NOT %DECLARED (ioc$return) %THEN EXTERNAL ROUTINE ioc$return; %FI %IF NOT %DECLARED (ioc$return_success) %THEN EXTERNAL ROUTINE ioc$return_success; %FI %IF NOT %DECLARED (ioc$return_unsupported) %THEN EXTERNAL ROUTINE ioc$return_unsupported; %FI %IF NOT %DECLARED (ioc_std$mntver) %THEN EXTERNAL ROUTINE ioc_std$mntver; %FI %IF NOT %DECLARED (exe_std$insert_irp) %THEN EXTERNAL ROUTINE exe_std$insert_irp; %FI PSECT NODEFAULT = PSECT_NAME (PIC, READ, WRITE, NOEXECUTE, ALIGN (5)); GLOBAL %NAME (DEVNAM,'$DDT') : PSECT (PSECT_NAME) BLOCK [ddt$k_length, BYTE] PRESET ( [ddt$iw_size] = DDT$K_LENGTH, [ddt$b_type] = DYN$C_MISC, [ddt$b_subtype] = DYN$C_DDT, [ddt$iw_diagbuf] = DIAGBF, [ddt$iw_errorbuf] = ERLGBF, [ddt$iw_fdtsize] = FDT$K_LENGTH, [ddt$ps_start_2] = DDTAB_GENRADDR (START, ioc$return_success), [ddt$ps_start_jsb] = 0, [ddt$ps_ctrlinit_2] = DDTAB_GENRADDR (CTRLINIT, ioc$return_success), [ddt$ps_unitinit_2] = DDTAB_GENRADDR (UNITINIT, ioc$return_success), [ddt$ps_cloneducb_2] = DDTAB_GENRADDR (CLONEDUCB, ioc$return_success), [ddt$ps_fdt_2] = FUNCTB, [ddt$ps_cancel_2] = DDTAB_GENRADDR (CANCEL, ioc$return_success), [ddt$ps_regdump_2] = DDTAB_GENRADDR (REGDMP, ioc$return_success), [ddt$ps_altstart_2] = DDTAB_GENRADDR (ALTSTART, ioc$return_success), [ddt$ps_altstart_jsb] = 0, [ddt$ps_mntver_2] = DDTAB_GENRADDR (MNTVER, ioc_std$mntver), [ddt$ps_mntv_sssc] = DDTAB_GENRADDR (MNTV_SSSC), [ddt$ps_mntv_for] = DDTAB_GENRADDR (MNTV_FOR), [ddt$ps_mntv_sqd] = DDTAB_GENRADDR (MNTV_SQD), [ddt$ps_aux_storage] = DDTAB_GENRADDR (AUX_STORAGE), [ddt$ps_aux_routine] = DDTAB_GENRADDR (AUX_ROUTINE), [ddt$ps_channel_assign_2] = DDTAB_GENRADDR (CHANNEL_ASSIGN, ioc$return_unsupported), [ddt$ps_cancel_selective_2] = DDTAB_GENRADDR (CANCEL_SELECTIVE, ioc$return_unsupported), [ddt$is_stack_bcnt] = KP_STACK_SIZE, [ddt$is_reg_mask] = %IF %IDENTICAL (0, KP_REG_MASK) %THEN KPREG$K_HLL_REG_MASK %ELSE DDTAB_REG_SPEC (%REMOVE (KP_REG_MASK)) %FI, [ddt$ps_kp_startio] = DDTAB_GENRADDR (KP_STARTIO), [ddt$ps_csr_mapping] = DDTAB_GENRADDR (CSR_MAPPING, ioc$return_success), [ddt$ps_fast_fdt] = DDTAB_GENRADDR (FAST_FDT, 0), [ddt$ps_pending_io] = DDTAB_GENRADDR (PENDING_IO, exe_std$insert_irp), [ddt$ps_customer] = 0, [ddt$ps_make_devpath] = DDTAB_GENRADDR (MAKE_DEVPATH, ioc$return_unsupported), [ddt$ps_setprfpath] = DDTAB_GENRADDR (SETPRFPATH, ioc$return_unsupported), [ddt$ps_change_preferred] = DDTAB_GENRADDR (CHANGE_PREFERRED, ioc$return_unsupported), [ddt$ps_mpdev_path_swtch]= DDTAB_GENRADDR (MPDEV_PATH_SWTCH, ioc$return_unsupported) ) %; !++ ! ! Driver Prologue Table generation macros ! !-- KEYWORDMACRO DPTAB (ADAPTER, ! Adapter type FLAGS=0, ! DPT flags UCBSIZE=0, ! size of UCB UNLOAD=0, ! unload routine MAXUNITS=8, ! max units to configure DEFUNITS=1, ! default units to configure DELIVER=0, ! unit delivery routine VECTOR=0, ! driver-spec address NAME='', ! driver name DECODE=0, ! DECwindows-spec address STEP=0, ! EVMS driver step number IDB_CRAMS=0, ! CRAMs allocated on IDB UCB_CRAMS=0, ! CRAMs allocated on each UCB BT_ORDER=0, ! Boot-time init ordering control IOHANDLES=0, ! IOHANDLES needed by driver DEVPATH_SIZE=0, ! Device path information size DEVPATH_UCB_OFS=0, ! Device path information block offset DSPLYPATH_SIZE=0, ! Displayable device path string size DSPLYPATH_UCB_OFS=0, ! Displayable device path srring offset in UCB MAX_UNIT=0, ! Maximum device unit DDT=DRIVER$DDT, ! STRUC_INIT=DRIVER$STRUC_INIT, ! STRUC_REINIT=DRIVER$STRUC_REINIT, ! PSECT_NAME = $$$105_PROLOGUE, ! DPT psect name DPT=DRIVER$DPT) = ! DPT label MACRO DPTAB_FLAG_SPEC (FLAG_LIST)[] = %IF %IDENTICAL (0, FLAG_LIST) %THEN (dpt$m_smpmod) %ELSE (FLAG_LIST) %IF %LENGTH GTR 1 %THEN OR DPTAB_FLAG_SPEC (%REMAINING) %ELSE OR (dpt$m_smpmod) %FI %FI %QUOTE %, DPTAB_SET_DRIVER_NAME(INDEX, NEXT_CHAR) [] = , [NAME_OFFSET+INDEX, 0, 8, 0] = NEXT_CHAR %IF %LENGTH GTR 2 %THEN %ASSIGN (INDEX, INDEX +1) DPTAB_SET_DRIVER_NAME(INDEX, %REMAINING) %FI %QUOTE %; COMPILETIME INDX = 0, NAME_OFFSET = $BYTEOFFSET(dpt$t_name_str); ! dpt table consistency check ! Check binary devpath fields %IF ((FLAGS) AND DPT$M_DEVPATH_SUP) NEQ 0 %THEN ! if DPT$M_DEVPATH_SUP bit is set. %IF DEVPATH_UCB_OFS EQLU 0 %THEN ! if device path offset is 0 %ERROR ('DPT$IL_DEVPATH_UCB_OFS field requires non-zero value if DPT$M_DEVPATH_SUP bit is set') %FI %IF (DEVPATH_SIZE + DEVPATH_UCB_OFS) GTRU UCBSIZE %THEN ! if device path size too big %ERROR ('Device path falls outside of device UCB') %FI %ELSE %IF ((FLAGS) AND DPT$M_MULTIPATH_SUP) NEQ 0 %THEN ! if multipath bit set and devpath not %ERROR ('Multipath support required DPT$V_DEVPATH_SUP bit to be set') %FI %FI ! Check displayable path fields %IF ((FLAGS) AND DPT$M_MULTIPATH_SUP) NEQ 0 %THEN ! if DPT$M_MULTIPATH_SUP bit is set. %IF DSPLYPATH_SIZE EQLU 0 %THEN ! if the size of the displayable devpath is 0 %ERROR ('DPT$IL_DSPLYPATH_SIZE field requires non-zero value if DPT$M_MULTIPATH_SUP bit is set') %FI %IF DSPLYPATH_UCB_OFS EQLU 0 %THEN ! if DISPLAYABLE device path offset is 0 %ERROR ('DPT$IL_DSPLYPATH_UCB_OFS field requires non-zero value if DPT$M_MULTIPATH_SUP bit is set') %FI %IF (DSPLYPATH_SIZE + DSPLYPATH_UCB_OFS) GTRU UCBSIZE %THEN ! if device path string size too big %ERROR ('Displayable device path string falls outside of the device UCB') %FI %FI PSECT NODEFAULT = PSECT_NAME (PIC, READ, WRITE, NOEXECUTE, ALIGN (5)); GLOBAL DPT : PSECT (PSECT_NAME) BLOCK [dpt$k_base_len + nam$c_maxrss, BYTE] PRESET ( [dpt$iw_size] = dpt$k_base_len + nam$c_maxrss, [dpt$ib_type] = dyn$c_dpt, [dpt$iw_step] = dpt$k_step_2, [dpt$iw_stepver] = dpt$k_step2_v5, [dpt$iw_defunits] = DEFUNITS, [dpt$iw_maxunits] = MAXUNITS, [dpt$iw_ucbsize] = UCBSIZE, [dpt$iw_iohandles] = IOHANDLES, [dpt$iw_idb_crams] = IDB_CRAMS, [dpt$iw_ucb_crams] = UCB_CRAMS, [dpt$il_flags] = DPTAB_FLAG_SPEC (%REMOVE (FLAGS)), [dpt$il_adptype] = %NAME ('AT$_', ADAPTER), [dpt$ps_init_pd] = STRUC_INIT, [dpt$ps_reinit_pd] = STRUC_REINIT, [dpt$ps_deliver_2] = DELIVER, [dpt$ps_unload] = UNLOAD, [dpt$ps_ddt] = DDT, [dpt$is_btorder] = BT_ORDER, [dpt$ps_vector] = VECTOR, ! [dpt$t_name] = ! Not used [dpt$ib_name_len] = %CHARCOUNT(NAME), [dpt$iw_iname_len] = nam$c_maxrss, [dpt$ib_iname_type] = dsc$k_dtype_t, [dpt$ib_iname_class] = dsc$k_class_s, [dpt$ps_iname_ptr] = DPT[dpt$t_image_name], [dpt$ps_decw_sname] = DECODE, [dpt$il_devpath_size] = DEVPATH_SIZE, [dpt$il_devpath_ucb_ofs] = DEVPATH_UCB_OFS, [dpt$l_max_unit] = MAX_UNIT DPTAB_SET_DRIVER_NAME(INDX, %EXPLODE(NAME)) ) %; !++ ! ! Function Decision Table generation macros ! !-- KEYWORDMACRO FDTAB ( FDT_NAME = driver$fdt, ! FDT name FDT_BUF, ! buffered functions FDT_64, ! functions supporting 64-bits FDT_ACT, ! actions PSECT_NAME = $$$110_DATA) = ! FDT psect name MACRO FDTAB_F2M (FUNC, BUMP) = (1 ^ (%NAME ('IO$_',FUNC) - BUMP)) %QUOTE %, FDTAB_BLDBFM (FUNC)[] = %IF NOT %IDENTICAL (0, FUNC) %THEN %IF %NAME ('IO$_',FUNC) LSS 32 %THEN %ASSIGN (FDTAB_BUFLO, FDTAB_BUFLO OR FDTAB_F2M (FUNC, 0)) %ELSE %ASSIGN (FDTAB_BUFHI, FDTAB_BUFHI OR FDTAB_F2M (FUNC, 32)) %FI %IF %LENGTH GTR 1 %THEN FDTAB_BLDBFM (%REMAINING) %ELSE [FDTAB_BUF_O, 0, 32, 0] = FDTAB_BUFLO, [FDTAB_BUF_O + 4, 0, 32, 0] = FDTAB_BUFHI, %FI %FI %QUOTE %, FDTAB_BLD64M (FUNC)[] = %IF NOT %IDENTICAL (0, FUNC) %THEN %IF %NAME ('IO$_',FUNC) LSS 32 %THEN %ASSIGN (FDTAB_64B_LO, FDTAB_64B_LO OR FDTAB_F2M (FUNC, 0)) %ELSE %ASSIGN (FDTAB_64B_HI, FDTAB_64B_HI OR FDTAB_F2M (FUNC, 32)) %FI %IF %LENGTH GTR 1 %THEN FDTAB_BLD64M (%REMAINING) %ELSE , [$BYTEOFFSET(fdt$q_ok64bit), 0, 32, 0] = FDTAB_64B_LO , [$BYTEOFFSET(fdt$q_ok64bit)+4, 0, 32, 0] = FDTAB_64B_HI %FI %FI %QUOTE %, FDTAB_SETACT (ACTRTN, FUNC) = %IF %NAME ('IO$_',FUNC) LSS 32 %THEN %IF (FDTAB_FUNCLO AND FDTAB_F2M (FUNC, 0)) NEQ 0 %THEN %ERROR ('Multiple actions associated with function IO$_FUNC') %ELSE %ASSIGN (FDTAB_FUNCLO, FDTAB_FUNCLO OR FDTAB_F2M (FUNC, 0)) [FDTAB_ACT_O + (4 * %NAME ('IO$_', FUNC)), 0, 32, 0] = ACTRTN %FI %ELSE %IF (FDTAB_FUNCHI AND FDTAB_F2M (FUNC, 32)) NEQ 0 %THEN %ERROR ('Multiple actions associated with function IO$_FUNC') %ELSE %ASSIGN (FDTAB_FUNCHI, FDTAB_FUNCHI OR FDTAB_F2M (FUNC, 32)) [FDTAB_ACT_O + (4 * %NAME ('IO$_', FUNC)), 0, 32, 0] = ACTRTN %FI %FI %QUOTE %, FDTAB_SETDEF (INDEX)[] = %IF INDEX LSS 32 %THEN %IF (FDTAB_FUNCLO AND (1 ^ INDEX)) EQL 0 %THEN , [FDTAB_ACT_O + (4 * INDEX), 0, 32, 0] = EXE$ILLIOFUNC %FI %ELSE %IF (FDTAB_FUNCHI AND (1 ^ (INDEX - 32))) EQL 0 %THEN , [FDTAB_ACT_O + (4 * INDEX), 0, 32, 0] = EXE$ILLIOFUNC %FI %FI %ASSIGN (INDEX, INDEX + 1) %IF INDEX LSS 64 %THEN FDTAB_SETDEF (INDEX) %FI %QUOTE %, FDTAB_DOFUNCLIST (ACTRTN)[FUNCLIST] = FDTAB_SETACT (ACTRTN, FUNCLIST) %QUOTE %, FDTAB_BLDACT (ACTRTN, FUNCLIST)[] = FDTAB_DOFUNCLIST (ACTRTN, %REMOVE (FUNCLIST)) %IF %LENGTH GTR 2 %THEN , FDTAB_BLDACT (%REMAINING) %ELSE FDTAB_SETDEF (FDTAB_INDEX) %FI %QUOTE %; COMPILETIME FDTAB_INDEX = 0, FDTAB_BUFLO = 0, FDTAB_BUFHI = 0, FDTAB_64B_LO = 0, FDTAB_64B_HI = 0, FDTAB_FUNCLO = 0, FDTAB_FUNCHI = 0, FDTAB_BUF_O = $BYTEOFFSET (fdt$q_buffered), FDTAB_ACT_O = $BYTEOFFSET (fdt$ps_func_rtn); %IF NOT %DECLARED (exe$illiofunc) %THEN EXTERNAL ROUTINE exe$illiofunc; %FI PSECT NODEFAULT = PSECT_NAME (PIC, READ, WRITE, NOEXECUTE, ALIGN (5)); GLOBAL FDT_NAME : PSECT (PSECT_NAME) BLOCK [fdt$k_length, BYTE] PRESET ( FDTAB_BLDBFM (%REMOVE (FDT_BUF)) FDTAB_BLDACT (%REMOVE (FDT_ACT)) FDTAB_BLD64M (%REMOVE (FDT_64 ))) %; !++ ! Define FDT completion routine macros !-- MACRO call_abortio (irp, pcb, ucb, status) = exe_std$abortio (irp, pcb, ucb, status) %, call_finishio (irp, ucb, iost1, iost2) = BEGIN %IF NOT %NULL (iost1) %THEN BIND _irp = irp : ref block [irp$k_length, byte]; _irp[ irp$l_iost1 ] = iost1; _irp[ irp$l_iost2 ] = iost2; %FI exe_std$finishio (irp, ucb) END %, call_finishioc (irp, ucb, iost1) = call_finishio (irp, ucb, iost1, 0) %, call_iorsnwait (irp, pcb, ucb, ccb, status, resource) = exe_stdiorsnwait (irp, pcb, ucb, ccb, status, resource)%, call_qioacppkt (irp, pcb, ucb) = exe_std$qioacppkt (irp, pcb, ucb) %, call_qiodrvpkt (irp, ucb) = BEGIN BIND _irp = irp : ref block [irp$k_length, byte]; _irp[ irp$ps_fdt_context ] = 0; exe_std$insioq (irp, ucb); SS$_FDT_COMPL END %; !++ ! ! TB Invalidate All Entries (System and Process) ! ! TBI_ALL ENVIRON ! ! ENVIRON = "THIS_CPU_ONLY" indicates that this invocation of TBIA is ! to be executed strictly within the context of the local ! CPU only. Thus, no attempt is made whatsoever to extend ! the TBIA request to any CPU or other 'processor' that ! might exist within the system. ! = anything other than the above forces the TBIA to be ! extended to all components of the system that may ! have cached PTEs. ! !-- KEYWORDMACRO TBI_ALL (ENVIRON=MP) = BEGIN %if not %declared (mmg$tbi_all) %then external routine mmg$tbi_all; %fi ! NOTE: The DEFINE_BUILTIN macro has an embedded %IF NOT %DECLARED. define_builtin (%quote %quote %quote pal_mtpr_tbia); %if %identical(environ, this_cpu_only) %then pal_mtpr_tbia(); %else mmg$tbi_all(); %fi END %; !++ ! ! TB Invalidate Data Single 64 ! ! TBI_DATA_64 ADDR, ENVIRON, PCBADDR ! ! ADDR = 64-bit Virtual Address to be invalidated. ! ! ENVIRON = "THIS_CPU_ONLY" indicates that this invocation of TBISD is ! to be executed strictly within the context of the local ! CPU only. Thus, no attempt is made whatsoever to extend ! the TBISD request to any CPU or other 'processor' that ! might exist within the system. ! = "ASSUME_PRIVATE" indicates that this is a threads ! environment and that the address should be treated ! as a private address and not checked. Therefore, ! in an SMP environment, we need to do the invalidate ! to other CPUs which are running a kernel thread from ! this process. This argument is used for system space ! addresses which should be treated as private to the ! process (e.g. for L2PTE's which are also mapped in ! "page table space"). ! = "ASSUME_SHARED" indicates that this invocation of TBISD should ! be broadcast to all other CPUs in the system. ASSUME_ ! SHARED is the exact opposite of THIS_CPU_ONLY. ! = anything other than the above forces the TB invalidate to ! be extended to all components of the system that may ! have cached PTEs. ! ! PCBADDR = Address of current process control block. Default is 0. ! This argument must be specified if the address to be ! invalidated is process private (either ENVIRON=ASSUME_ ! PRIVATE or no keyword for the ENVIRON qualifier was specified). ! ! The symbol, NO_PCB (which equates to 0), can be used for ! this argument if the PCB address is not needed. Be careful ! though since a system crash may result if a valid PCB address ! is required but NO_PCB is specified. It cannot always be ! determined at compile time if a valid PCB address is ! required. ! !-- KEYWORDMACRO TBI_DATA_64 (ADDR,ENVIRON=MP,PCBADDR=NO_PCB) = BEGIN %IF NOT %DECLARED (smp$gl_flags) %THEN EXTERNAL smp$gl_flags : block[4,byte]; %FI %IF NOT %DECLARED (mmg$gq_shared_va_ptes) %THEN EXTERNAL mmg$gq_shared_va_ptes; %FI ! NOTE: The DEFINE_BUILTIN macro has an embedded %IF NOT %DECLARED. DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE pal_mtpr_tbisd); %IF NOT %DECLARED (mmg$tbi_data_64) %THEN EXTERNAL ROUTINE mmg$tbi_data_64; %FI %IF NOT %DECLARED (mmg$tbi_data_64_threads) %THEN EXTERNAL ROUTINE mmg$tbi_data_64_threads; %FI ! ! Do local invalidate if THIS_CPU_ONLY is specified. ! %IF %IDENTICAL(environ,this_cpu_only) %THEN pal_mtpr_tbisd(.addr); %ELSE ! ! Do local invalidate if SMP is disabled. ! IF NOT .SMP$GL_FLAGS[SMP$V_ENABLED] THEN BEGIN pal_mtpr_tbisd(.addr); END ELSE BEGIN ! ! If ASSUME_SHARED is specified, do SMP-wide invalidate. ! %IF %IDENTICAL(environ,assume_shared) %THEN mmg$tbi_data_64 (.addr); %ELSE ! ! If ASSUME_PRIVATE is specified, PCBADDR MUST be specified. ! %IF %IDENTICAL(environ,assume_private) %THEN %IF (%NULL(PCBADDR) OR %IDENTICAL(pcbaddr, no_pcb)) %THEN %ERROR('The PCB address must be specified') %ELSE IF .pcbaddr[pcb$l_multithread] LEQ 1 THEN pal_mtpr_tbisd(.addr) ELSE mmg$tbi_data_64_threads(.addr); %FI %ELSE ! ! If ADDR is a shared VA, do SMP-wide invalidate. If ADDR is not a shared VA ! PCBADDR MUST be specified. ! IF ($is_shared_va (va=.addr)) THEN mmg$tbi_data_64(.addr) ELSE BEGIN LOCAL $$temp : ref $bblock; %IF (%NULL(PCBADDR) OR %IDENTICAL(pcbaddr, no_pcb)) %THEN $$temp = 0; %ELSE $$temp = .pcbaddr; %FI IF .$$temp[pcb$l_multithread] LEQ 1 THEN pal_mtpr_tbisd(.addr) ELSE mmg$tbi_data_64_threads(.addr); END; %FI %FI END; %FI END % ; !++ ! ! TB Invalidate Single ! ! TBI_SINGLE ADDR, ENVIRON, PCBADDR ! ! ADDR = Virtual Address to be invalidated. ! ! This address must be passed to this macro via a register. ! No memory reference is allowed. This address may be either ! a 64 bit VA or a sign-extended 32 bit VA. ! ! ENVIRON = "THIS_CPU_ONLY" indicates that this invocation of TBIS is ! to be executed strictly within the context of the local ! CPU only. Thus, no attempt is made whatsoever to extend ! the TBIS request to any CPU or other 'processor' that ! might exist within the system. ! = "ASSUME_PRIVATE" indicates that this is a threads ! environment and that the address should be treated ! as a private address and not checked. Therefore, ! in an SMP environment, we need to do the invalidate ! to other CPUs which are running a kernel thread from ! this process. This argument is used for system space ! addresses which should be treated as private to the ! process (e.g. for L2PTE's which are also mapped in ! "page table space"). ! = "ASSUME_SHARED" indicates that this invocation of TBIS should ! be broadcast to all other CPUs in the system. ASSUME_ ! SHARED is the exact opposite of THIS_CPU_ONLY. ! = anything other than the above forces the TB invalidate to ! be extended to all components of the system that may ! have cached PTEs. ! ! PCBADDR = Address of current process control block. Default is 0. ! This argument must be specified if the address to be ! invalidated is process private (either ENVIRON=ASSUME_ ! PRIVATE or no keyword for the ENVIRON qualifier was specified). ! ! The symbol, NO_PCB (which equates to 0), can be used for ! this argument if the PCB address is not needed. Be careful ! though since a system crash may result if a valid PCB address ! is required but NO_PCB is specified. It cannot always be ! determined at compile time if a valid PCB address is ! required. !-- KEYWORDMACRO TBI_SINGLE(ADDR,ENVIRON=MP,PCBADDR=NO_PCB) = BEGIN %IF NOT %DECLARED (smp$gl_flags) %THEN EXTERNAL smp$gl_flags : block[4,byte]; %FI %IF NOT %DECLARED (mmg$gq_shared_va_ptes) %THEN EXTERNAL mmg$gq_shared_va_ptes; %FI ! NOTE: The DEFINE_BUILTIN macro has an embedded %IF NOT %DECLARED. DEFINE_BUILTIN (%QUOTE %QUOTE %QUOTE pal_mtpr_tbis); %IF NOT %DECLARED (mmg$tbi_single) %THEN EXTERNAL ROUTINE mmg$tbi_single; %FI %IF NOT %DECLARED (mmg$tbi_single_threads) %THEN EXTERNAL ROUTINE mmg$tbi_single_threads; %FI ! ! Do local invalidate if THIS_CPU_ONLY is specified. ! %IF %IDENTICAL(environ,this_cpu_only) %THEN pal_mtpr_tbis(.addr); %ELSE ! ! Do local invalidate if SMP is disabled. ! IF NOT .SMP$GL_FLAGS[SMP$V_ENABLED] THEN BEGIN pal_mtpr_tbis(.addr); END ELSE BEGIN ! ! If ASSUME_SHARED is specified, do SMP-wide invalidate. ! %IF %IDENTICAL(environ,assume_shared) %THEN mmg$tbi_single (.addr); %ELSE ! ! If ASSUME_PRIVATE is specified, PCBADDR MUST be specified. ! %IF %IDENTICAL(environ,assume_private) %THEN %IF (%NULL(PCBADDR) OR %IDENTICAL(pcbaddr, no_pcb)) %THEN %ERROR('The PCB address must be specified') %ELSE IF .pcbaddr[pcb$l_multithread] LEQ 1 THEN pal_mtpr_tbis(.addr) ELSE mmg$tbi_single_threads(.addr); %FI %ELSE ! ! If ADDR is a shared VA, do SMP-wide invalidate. If ADDR is not a shared VA ! PCBADDR MUST be specified. ! IF ($is_shared_va (va=.addr)) THEN mmg$tbi_single (.addr) ELSE BEGIN LOCAL $$temp : ref $bblock; %IF (%NULL(PCBADDR) OR %IDENTICAL(pcbaddr, no_pcb)) %THEN $$temp = 0; %ELSE $$temp = .pcbaddr; %FI IF .$$temp[pcb$l_multithread] LEQ 1 THEN pal_mtpr_tbis(.addr) ELSE mmg$tbi_single_threads(.addr); END; %FI %FI END; %FI END % ; ! ! $GET_ITEM_CODE ! ! This macro fetches the contents of the item code field from an item list ! entry. Note that the item code field is in the same place for 32-bit and ! 64-bit item list entries. ! ! ! ARGUMENTS: ! ! Itmlst: Specifies the item list entry from which the item code ! is extracted. ! ! USAGE: ! Item_code = $GET_ITEM_CODE (ITMLST = Item_list); ! KEYWORDMACRO $GET_ITEM_CODE (Itmlst) = BEGIN MAP Itmlst : REF BLOCK [, BYTE]; .Itmlst [Ilea_64$w_code] END%; ! ! $GET_LENGTH ! ! This macro fetches the contents of the length field from an item list ! entry. ! ! ! ARGUMENTS: ! ! Flag: A flag denoting the type of item list specified. Low ! bit set denotes a 64-bit item list, while low bit clear ! denotes a 32-bit item list. ! ! Itmlst: Specifies the item list entry from which the length ! is extracted. ! ! ! USAGE: ! Item_length = $GET_LENGTH (FLAG = Flag, ITMLST = Item_list); ! KEYWORDMACRO $GET_LENGTH (Flag, Itmlst) = BEGIN MAP Itmlst : REF BLOCK [, BYTE]; IF NOT .Flag THEN .Itmlst [Ile2$w_length] ELSE .Itmlst [Ilea_64$q_length] END%; ! ! $GET_BUFADDR ! ! This macro fetches the contents of the buffer address field from an item list ! entry. ! ! ! ARGUMENTS: ! ! Flag: A flag denoting the type of item list specified. Low ! bit set denotes a 64-bit item list, while low bit clear ! denotes a 32-bit item list. ! ! Itmlst: Specifies the item list entry from which the buffer ! address is extracted. ! ! ! USAGE: ! Item_bufaddr = $GET_BUFADDR (FLAG = Flag, ITMLST = Item_list); ! KEYWORDMACRO $GET_BUFADDR (Flag, Itmlst) = BEGIN MAP Itmlst : REF BLOCK [, BYTE]; IF NOT .Flag THEN .Itmlst [Ile2$ps_bufaddr] ELSE .Itmlst [Ilea_64$pq_bufaddr] END%; ! ! $GET_RETLEN_ADDR ! ! This macro fetches the contents of the return length address field from an ! item list entry. The return length address field only exists for item_list_3 ! and item_list_64_b item list types. ! ! ! ARGUMENTS: ! ! ! Flag: A flag denoting the type of item list specified. Low ! bit set denotes a 64-bit item list, while low bit clear ! denotes a 32-bit item list. ! ! Itmlst: Specifies the item list entry from which the return ! length address is extracted. ! ! ! USAGE: ! Item_retlen_addr = $GET_RETLEN_ADDR (FLAG = Flag, ITMLST = Item_list); ! KEYWORDMACRO $GET_RETLEN_ADDR (Flag, Itmlst) = BEGIN MAP Itmlst : REF BLOCK [, BYTE]; IF NOT .Flag THEN .Itmlst [Ile3$ps_retlen_addr] ELSE .Itmlst [Ileb_64$pq_retlen_addr] END%; ! ! $GET_ILE_FIELDS ! ! This macro fetches the contents of the item list entry fields and writes ! them to the user-supplied registers. ! ! ! ARGUMENTS: ! ! Flag: A flag denoting the type of item list entry specified ! in the item list argument. Low bit set denotes a ! 64-bit item list, while low bit clear denotes a 32-bit ! item list. ! ! Item_list: An item list entry from which to fetch the contents of ! the various fields. ! ! Item_code: Contents of the item code field are recorded here. ! ! Length: Contents of the length field are recorded here. ! ! Bufaddr: Contents of the buffer address field are recorded here. ! ! Retlen_addr: Contents of the return length address field are ! recorded here. ! ! ! USAGE: ! $get_ile_fields (FLAG = Flag, ITMLST = Item_list, ITEMCODE = Item_code, ! LENGTH = Length, BUFADDR = Bufaddr, RETLEN_ADDR = Retlen_addr); ! KEYWORDMACRO $GET_ILE_FIELDS (Flag, Itmlst, Itemcode, Length, Bufaddr, Retlen_addr) = BEGIN MAP Itmlst : REF BLOCK [, BYTE]; %IF %NULL (Flag) %THEN %ERROR ('Flag argument not specified') %FI %IF %NULL (Itmlst) %THEN %ERROR ('Itmlst argument not specified') %FI %IF NOT %NULL (Itemcode) %THEN IF NOT .Flag THEN Itemcode = .Itmlst [Ile3$w_code] ELSE Itemcode = .Itmlst [Ileb_64$w_code]; %FI %IF NOT %NULL (Length) %THEN IF NOT .Flag THEN Length = .Itmlst [Ile3$w_length] ELSE Length = .Itmlst [Ileb_64$q_length]; %FI %IF NOT %NULL (Bufaddr) %THEN IF NOT .Flag THEN Bufaddr = .Itmlst [Ile3$ps_bufaddr] ELSE Bufaddr = .Itmlst [Ileb_64$pq_bufaddr]; %FI %IF NOT %NULL (Retlen_addr) %THEN IF NOT .Flag THEN Retlen_addr = .Itmlst [Ile3$ps_retlen_addr] ELSE Retlen_addr = .Itmlst [Ileb_64$pq_retlen_addr]; %FI END%; !-- ! TR_PRINT - Debug print ! ! This macro adds an informational message to the TR trace buffer. ! The ctrstr argument has similar syntax to a "printf" statement. ! ! Inputs: ! ! ctrstr - The text and optional formatting directives to be ! saved in the trace ring buffer, only the following ! directives are allowed, no width: ! %s - zero-terminated string ! %a - ascii string (pointer & length) ! %d - decimal value ! %X - hexadecimal longword ! %L - hexadecimal quadword ! p1-p5 - The corresponding values to be formatted. For the %s ! directive, this is the address of the zero-terminated ! string. For the %a directive, this requires 2 arguments, ! first the address of the string buffer, then the length ! of the string (by value). For the other directives, this ! is passed by value. ! ! Outputs: ! None ! ! Usage Examples: ! Macro32: ! tr_print ctrstr=,p1=r4 ! tr_print ctrstr=,p1=r3,p2=r5 ! C: ! #include vms_macros ! tr_print (("this is a C test and needs double-parentheses, index %d", idx )); ! tr_print (("a hex number %X and a quadword %L", irp->irp$l_func, irp->irp$q_fr3 )); ! Bliss: ! tr_print ('this is a Bliss test, index %d', .idx ); ! tr_print ('a hex number %X and a quadword %L', .irp, .ucb ); ! !-- MACRO TR_PRINT(CTRSTR) = (BEGIN %IF NOT %DECLARED (TR$GQ_DEBUG) %THEN EXTERNAL TR$GQ_DEBUG : LONG; %FI LOCAL ANCHOR : REF $BBLOCK, ROUTINE_ADDRESS; BIND CS = UPLIT (%ASCIZ CTRSTR); ANCHOR = .TR$GQ_DEBUG<0,32,1>; IF (.ANCHOR AND 1) NEQ 0 ! skip, if tracing not enabled THEN BEGIN ANCHOR = .ANCHOR AND NOT 15; ! clear low nibble to get address ROUTINE_ADDRESS = .ANCHOR[0,0,32,1]; ! trace routine is in 1st longword (.ROUTINE_ADDRESS)(CS, %REMAINING); ! call trace print routine END END)%; !-- ! EXC_PRINT - Exception trace print ! ! This macro adds an informational message to the EXC trace buffer. ! The ctrstr argument has similar syntax to a "printf" statement. ! ! Inputs: ! ! ctrstr - The text and optional formatting directives to be ! saved in the trace ring buffer, only the following ! directives are allowed, no width: ! %s - zero-terminated string ! %a - ascii string (pointer & length) ! %d - decimal value ! %X - hexadecimal longword ! %L - hexadecimal quadword ! p1-p5 - The corresponding values to be formatted. For the %s ! directive, this is the address of the zero-terminated ! string. For the %a directive, this requires 2 arguments, ! first the address of the string buffer, then the length ! of the string (by value). For the other directives, this ! is passed by value. ! ! Outputs: ! None ! ! Usage Examples: ! Macro32: ! exc_print ctrstr=,p1=r4 ! exc_print ctrstr=,p1=r3,p2=r5 ! C: ! #include vms_macros ! exc_print (("this is a C test and needs double-parentheses, index %d", idx )); ! exc_print (("a hex number %X and a quadword %L", irp->irp$l_func, irp->irp$q_fr3 )); ! Bliss: ! exc_print ('this is a Bliss test, index %d', .idx ); ! exc_print ('a hex number %X and a quadword %L', .irp, .ucb ); ! !-- MACRO EXC_PRINT(CTRSTR) = (BEGIN %IF NOT %DECLARED (EXC$GQ_DEBUG) %THEN EXTERNAL EXC$GQ_DEBUG : LONG; %FI LOCAL ANCHOR : REF $BBLOCK, ROUTINE_ADDRESS; BIND CS = UPLIT (%ASCIZ CTRSTR); ANCHOR = .EXC$GQ_DEBUG<0,32,1>; IF (.ANCHOR AND 1) NEQ 0 ! skip, if tracing not enabled THEN BEGIN ANCHOR = .ANCHOR AND NOT 15; ! clear low nibble to get address ROUTINE_ADDRESS = .ANCHOR[0,0,32,1]; ! trace routine is in 1st longword (.ROUTINE_ADDRESS)(CS, %REMAINING); ! call exception trace print routine END END)%; ! ! ---- < End of module VMS-MACROS.REQ - 30-MAR-2010 16:39:04.47 > - !